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mmc: omap_hsmmc: fix ocr mask usage
[mirror_ubuntu-zesty-kernel.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
d900f712
DK		 20#include <linux/debugfs.h>
21#include <linux/seq_file.h>
a45c6cb8
MC		 22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/platform_device.h>
26#include <linux/workqueue.h>
27#include <linux/timer.h>
28#include <linux/clk.h>
29#include <linux/mmc/host.h>
13189e78 30#include <linux/mmc/core.h>
93caf8e6 31#include <linux/mmc/mmc.h>
a45c6cb8
MC		 32#include <linux/io.h>
33#include <linux/semaphore.h>
db0fefc5
AH		 34#include <linux/gpio.h>
35#include <linux/regulator/consumer.h>
ce491cf8 36#include <plat/dma.h>
a45c6cb8 37#include <mach/hardware.h>
ce491cf8
TL		 38#include <plat/board.h>
39#include <plat/mmc.h>
40#include <plat/cpu.h>
a45c6cb8
MC		 41
42/* OMAP HSMMC Host Controller Registers */
43#define OMAP_HSMMC_SYSCONFIG 0x0010
11dd62a7 44#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 45#define OMAP_HSMMC_CON 0x002C
46#define OMAP_HSMMC_BLK 0x0104
47#define OMAP_HSMMC_ARG 0x0108
48#define OMAP_HSMMC_CMD 0x010C
49#define OMAP_HSMMC_RSP10 0x0110
50#define OMAP_HSMMC_RSP32 0x0114
51#define OMAP_HSMMC_RSP54 0x0118
52#define OMAP_HSMMC_RSP76 0x011C
53#define OMAP_HSMMC_DATA 0x0120
54#define OMAP_HSMMC_HCTL 0x0128
55#define OMAP_HSMMC_SYSCTL 0x012C
56#define OMAP_HSMMC_STAT 0x0130
57#define OMAP_HSMMC_IE 0x0134
58#define OMAP_HSMMC_ISE 0x0138
59#define OMAP_HSMMC_CAPA 0x0140
60
61#define VS18 (1 << 26)
62#define VS30 (1 << 25)
63#define SDVS18 (0x5 << 9)
64#define SDVS30 (0x6 << 9)
eb250826 65#define SDVS33 (0x7 << 9)
1b331e69 66#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 67#define SDVSCLR 0xFFFFF1FF
68#define SDVSDET 0x00000400
69#define AUTOIDLE 0x1
70#define SDBP (1 << 8)
71#define DTO 0xe
72#define ICE 0x1
73#define ICS 0x2
74#define CEN (1 << 2)
75#define CLKD_MASK 0x0000FFC0
76#define CLKD_SHIFT 6
77#define DTO_MASK 0x000F0000
78#define DTO_SHIFT 16
79#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 80#define BWR_ENABLE (1 << 4)
81#define BRR_ENABLE (1 << 5)
93caf8e6 82#define DTO_ENABLE (1 << 20)
a45c6cb8
MC		 83#define INIT_STREAM (1 << 1)
84#define DP_SELECT (1 << 21)
85#define DDIR (1 << 4)
86#define DMA_EN 0x1
87#define MSBS (1 << 5)
88#define BCE (1 << 1)
89#define FOUR_BIT (1 << 1)
73153010 90#define DW8 (1 << 5)
a45c6cb8
MC		 91#define CC 0x1
92#define TC 0x02
93#define OD 0x1
94#define ERR (1 << 15)
95#define CMD_TIMEOUT (1 << 16)
96#define DATA_TIMEOUT (1 << 20)
97#define CMD_CRC (1 << 17)
98#define DATA_CRC (1 << 21)
99#define CARD_ERR (1 << 28)
100#define STAT_CLEAR 0xFFFFFFFF
101#define INIT_STREAM_CMD 0x00000000
102#define DUAL_VOLT_OCR_BIT 7
103#define SRC (1 << 25)
104#define SRD (1 << 26)
11dd62a7
DK		 105#define SOFTRESET (1 << 1)
106#define RESETDONE (1 << 0)
a45c6cb8
MC		 107
108/*
109 * FIXME: Most likely all the data using these _DEVID defines should come
110 * from the platform_data, or implemented in controller and slot specific
111 * functions.
112 */
113#define OMAP_MMC1_DEVID 0
114#define OMAP_MMC2_DEVID 1
f3e2f1dd 115#define OMAP_MMC3_DEVID 2
82cf818d 116#define OMAP_MMC4_DEVID 3
117#define OMAP_MMC5_DEVID 4
a45c6cb8 118
a45c6cb8
MC		 119#define MMC_TIMEOUT_MS 20
120#define OMAP_MMC_MASTER_CLOCK 96000000
0005ae73 121#define DRIVER_NAME "omap_hsmmc"
a45c6cb8 122
dd498eff
DK		 123/* Timeouts for entering power saving states on inactivity, msec */
124#define OMAP_MMC_DISABLED_TIMEOUT 100
13189e78
JL		 125#define OMAP_MMC_SLEEP_TIMEOUT 1000
126#define OMAP_MMC_OFF_TIMEOUT 8000
dd498eff 127
a45c6cb8
MC		 128/*
129 * One controller can have multiple slots, like on some omap boards using
130 * omap.c controller driver. Luckily this is not currently done on any known
131 * omap_hsmmc.c device.
132 */
133#define mmc_slot(host) (host->pdata->slots[host->slot_id])
134
135/*
136 * MMC Host controller read/write API's
137 */
138#define OMAP_HSMMC_READ(base, reg) \
139 __raw_readl((base) + OMAP_HSMMC_##reg)
140
141#define OMAP_HSMMC_WRITE(base, reg, val) \
142 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
143
70a3341a 144struct omap_hsmmc_host {
a45c6cb8
MC		 145 struct device *dev;
146 struct mmc_host *mmc;
147 struct mmc_request *mrq;
148 struct mmc_command *cmd;
149 struct mmc_data *data;
150 struct clk *fclk;
151 struct clk *iclk;
152 struct clk *dbclk;
db0fefc5
AH		 153 /*
154 * vcc == configured supply
155 * vcc_aux == optional
156 * - MMC1, supply for DAT4..DAT7
157 * - MMC2/MMC2, external level shifter voltage supply, for
158 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
159 */
160 struct regulator *vcc;
161 struct regulator *vcc_aux;
a45c6cb8
MC		 162 struct work_struct mmc_carddetect_work;
163 void __iomem *base;
164 resource_size_t mapbase;
4dffd7a2 165 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8
MC		 166 unsigned int id;
167 unsigned int dma_len;
0ccd76d4 168 unsigned int dma_sg_idx;
a45c6cb8 169 unsigned char bus_mode;
a3621465 170 unsigned char power_mode;
a45c6cb8
MC		 171 u32 *buffer;
172 u32 bytesleft;
173 int suspended;
174 int irq;
a45c6cb8 175 int use_dma, dma_ch;
f3e2f1dd 176 int dma_line_tx, dma_line_rx;
a45c6cb8 177 int slot_id;
2bec0893 178 int got_dbclk;
4a694dc9 179 int response_busy;
11dd62a7 180 int context_loss;
dd498eff 181 int dpm_state;
623821f7 182 int vdd;
b62f6228
AH		 183 int protect_card;
184 int reqs_blocked;
db0fefc5 185 int use_reg;
b417577d 186 int req_in_progress;
11dd62a7 187
a45c6cb8
MC		 188 struct omap_mmc_platform_data *pdata;
189};
190
db0fefc5
AH		 191static int omap_hsmmc_card_detect(struct device *dev, int slot)
192{
193 struct omap_mmc_platform_data *mmc = dev->platform_data;
194
195 /* NOTE: assumes card detect signal is active-low */
196 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
197}
198
199static int omap_hsmmc_get_wp(struct device *dev, int slot)
200{
201 struct omap_mmc_platform_data *mmc = dev->platform_data;
202
203 /* NOTE: assumes write protect signal is active-high */
204 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
205}
206
207static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
208{
209 struct omap_mmc_platform_data *mmc = dev->platform_data;
210
211 /* NOTE: assumes card detect signal is active-low */
212 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
213}
214
215#ifdef CONFIG_PM
216
217static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
218{
219 struct omap_mmc_platform_data *mmc = dev->platform_data;
220
221 disable_irq(mmc->slots[0].card_detect_irq);
222 return 0;
223}
224
225static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
226{
227 struct omap_mmc_platform_data *mmc = dev->platform_data;
228
229 enable_irq(mmc->slots[0].card_detect_irq);
230 return 0;
231}
232
233#else
234
235#define omap_hsmmc_suspend_cdirq NULL
236#define omap_hsmmc_resume_cdirq NULL
237
238#endif
239
b702b106
AH		 240#ifdef CONFIG_REGULATOR
241
db0fefc5
AH		 242static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
243 int vdd)
244{
245 struct omap_hsmmc_host *host =
246 platform_get_drvdata(to_platform_device(dev));
247 int ret;
248
249 if (mmc_slot(host).before_set_reg)
250 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
251
252 if (power_on)
99fc5131 253 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5 254 else
99fc5131 255 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
db0fefc5
AH		 256
257 if (mmc_slot(host).after_set_reg)
258 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
259
260 return ret;
261}
262
7715db5a 263static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
db0fefc5
AH		 264 int vdd)
265{
266 struct omap_hsmmc_host *host =
267 platform_get_drvdata(to_platform_device(dev));
268 int ret = 0;
269
270 /*
271 * If we don't see a Vcc regulator, assume it's a fixed
272 * voltage always-on regulator.
273 */
274 if (!host->vcc)
275 return 0;
276
277 if (mmc_slot(host).before_set_reg)
278 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
279
280 /*
281 * Assume Vcc regulator is used only to power the card ... OMAP
282 * VDDS is used to power the pins, optionally with a transceiver to
283 * support cards using voltages other than VDDS (1.8V nominal). When a
284 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
285 *
286 * In some cases this regulator won't support enable/disable;
287 * e.g. it's a fixed rail for a WLAN chip.
288 *
289 * In other cases vcc_aux switches interface power. Example, for
290 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
291 * chips/cards need an interface voltage rail too.
292 */
293 if (power_on) {
99fc5131 294 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 295 /* Enable interface voltage rail, if needed */
296 if (ret == 0 && host->vcc_aux) {
297 ret = regulator_enable(host->vcc_aux);
298 if (ret < 0)
99fc5131
LW		 299 ret = mmc_regulator_set_ocr(host->mmc,
300 host->vcc, 0);
db0fefc5
AH		 301 }
302 } else {
99fc5131 303 /* Shut down the rail */
6da20c89
AH		 304 if (host->vcc_aux)
305 ret = regulator_disable(host->vcc_aux);
99fc5131
LW		 306 if (!ret) {
307 /* Then proceed to shut down the local regulator */
308 ret = mmc_regulator_set_ocr(host->mmc,
309 host->vcc, 0);
310 }
db0fefc5
AH		 311 }
312
313 if (mmc_slot(host).after_set_reg)
314 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
315
316 return ret;
317}
318
7715db5a
KK		 319static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
320 int vdd)
321{
322 return 0;
323}
324
db0fefc5
AH		 325static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
326 int vdd, int cardsleep)
327{
328 struct omap_hsmmc_host *host =
329 platform_get_drvdata(to_platform_device(dev));
330 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
331
332 return regulator_set_mode(host->vcc, mode);
333}
334
7715db5a 335static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
db0fefc5
AH		 336 int vdd, int cardsleep)
337{
338 struct omap_hsmmc_host *host =
339 platform_get_drvdata(to_platform_device(dev));
340 int err, mode;
341
342 /*
343 * If we don't see a Vcc regulator, assume it's a fixed
344 * voltage always-on regulator.
345 */
346 if (!host->vcc)
347 return 0;
348
349 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
350
351 if (!host->vcc_aux)
352 return regulator_set_mode(host->vcc, mode);
353
354 if (cardsleep) {
355 /* VCC can be turned off if card is asleep */
356 if (sleep)
99fc5131 357 err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
db0fefc5 358 else
99fc5131 359 err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 360 } else
361 err = regulator_set_mode(host->vcc, mode);
362 if (err)
363 return err;
e0eb2424
AH		 364
365 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
366 return regulator_set_mode(host->vcc_aux, mode);
367
368 if (sleep)
369 return regulator_disable(host->vcc_aux);
370 else
371 return regulator_enable(host->vcc_aux);
db0fefc5
AH		 372}
373
7715db5a
KK		 374static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
375 int vdd, int cardsleep)
376{
377 return 0;
378}
379
db0fefc5
AH		 380static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
381{
382 struct regulator *reg;
383 int ret = 0;
64be9782 384 int ocr_value = 0;
db0fefc5
AH		 385
386 switch (host->id) {
387 case OMAP_MMC1_DEVID:
388 /* On-chip level shifting via PBIAS0/PBIAS1 */
389 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
390 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
391 break;
392 case OMAP_MMC2_DEVID:
393 case OMAP_MMC3_DEVID:
7715db5a 394 case OMAP_MMC5_DEVID:
db0fefc5 395 /* Off-chip level shifting, or none */
7715db5a
KK		 396 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
397 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
db0fefc5 398 break;
7715db5a
KK		 399 case OMAP_MMC4_DEVID:
400 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
401 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
db0fefc5
AH		 402 default:
403 pr_err("MMC%d configuration not supported!\n", host->id);
404 return -EINVAL;
405 }
406
407 reg = regulator_get(host->dev, "vmmc");
408 if (IS_ERR(reg)) {
409 dev_dbg(host->dev, "vmmc regulator missing\n");
410 /*
411 * HACK: until fixed.c regulator is usable,
412 * we don't require a main regulator
413 * for MMC2 or MMC3
414 */
415 if (host->id == OMAP_MMC1_DEVID) {
416 ret = PTR_ERR(reg);
417 goto err;
418 }
419 } else {
420 host->vcc = reg;
64be9782 421 ocr_value = mmc_regulator_get_ocrmask(reg);
422 if (!mmc_slot(host).ocr_mask) {
423 mmc_slot(host).ocr_mask = ocr_value;
424 } else {
425 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
426 pr_err("MMC%d ocrmask %x is not supported\n",
427 host->id, mmc_slot(host).ocr_mask);
428 mmc_slot(host).ocr_mask = 0;
429 return -EINVAL;
430 }
431 }
db0fefc5
AH		 432
433 /* Allow an aux regulator */
434 reg = regulator_get(host->dev, "vmmc_aux");
435 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
436
b1c1df7a
B		 437 /* For eMMC do not power off when not in sleep state */
438 if (mmc_slot(host).no_regulator_off_init)
439 return 0;
db0fefc5
AH		 440 /*
441 * UGLY HACK: workaround regulator framework bugs.
442 * When the bootloader leaves a supply active, it's
443 * initialized with zero usecount ... and we can't
444 * disable it without first enabling it. Until the
445 * framework is fixed, we need a workaround like this
446 * (which is safe for MMC, but not in general).
447 */
448 if (regulator_is_enabled(host->vcc) > 0) {
449 regulator_enable(host->vcc);
450 regulator_disable(host->vcc);
451 }
452 if (host->vcc_aux) {
453 if (regulator_is_enabled(reg) > 0) {
454 regulator_enable(reg);
455 regulator_disable(reg);
456 }
457 }
458 }
459
460 return 0;
461
462err:
463 mmc_slot(host).set_power = NULL;
464 mmc_slot(host).set_sleep = NULL;
465 return ret;
466}
467
468static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
469{
470 regulator_put(host->vcc);
471 regulator_put(host->vcc_aux);
472 mmc_slot(host).set_power = NULL;
473 mmc_slot(host).set_sleep = NULL;
474}
475
b702b106
AH		 476static inline int omap_hsmmc_have_reg(void)
477{
478 return 1;
479}
480
481#else
482
483static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
484{
485 return -EINVAL;
486}
487
488static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
489{
490}
491
492static inline int omap_hsmmc_have_reg(void)
493{
494 return 0;
495}
496
497#endif
498
499static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
500{
501 int ret;
502
503 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
b702b106
AH		 504 if (pdata->slots[0].cover)
505 pdata->slots[0].get_cover_state =
506 omap_hsmmc_get_cover_state;
507 else
508 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
509 pdata->slots[0].card_detect_irq =
510 gpio_to_irq(pdata->slots[0].switch_pin);
511 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
512 if (ret)
513 return ret;
514 ret = gpio_direction_input(pdata->slots[0].switch_pin);
515 if (ret)
516 goto err_free_sp;
517 } else
518 pdata->slots[0].switch_pin = -EINVAL;
519
520 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
521 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
522 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
523 if (ret)
524 goto err_free_cd;
525 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
526 if (ret)
527 goto err_free_wp;
528 } else
529 pdata->slots[0].gpio_wp = -EINVAL;
530
531 return 0;
532
533err_free_wp:
534 gpio_free(pdata->slots[0].gpio_wp);
535err_free_cd:
536 if (gpio_is_valid(pdata->slots[0].switch_pin))
537err_free_sp:
538 gpio_free(pdata->slots[0].switch_pin);
539 return ret;
540}
541
542static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
543{
544 if (gpio_is_valid(pdata->slots[0].gpio_wp))
545 gpio_free(pdata->slots[0].gpio_wp);
546 if (gpio_is_valid(pdata->slots[0].switch_pin))
547 gpio_free(pdata->slots[0].switch_pin);
548}
549
a45c6cb8
MC		 550/*
551 * Stop clock to the card
552 */
70a3341a 553static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 554{
555 OMAP_HSMMC_WRITE(host->base, SYSCTL,
556 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
557 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
558 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
559}
560
93caf8e6
AH		 561static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
562 struct mmc_command *cmd)
b417577d
AH		 563{
564 unsigned int irq_mask;
565
566 if (host->use_dma)
567 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
568 else
569 irq_mask = INT_EN_MASK;
570
93caf8e6
AH		 571 /* Disable timeout for erases */
572 if (cmd->opcode == MMC_ERASE)
573 irq_mask &= ~DTO_ENABLE;
574
b417577d
AH		 575 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
576 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
577 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
578}
579
580static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
581{
582 OMAP_HSMMC_WRITE(host->base, ISE, 0);
583 OMAP_HSMMC_WRITE(host->base, IE, 0);
584 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
585}
586
11dd62a7
DK		 587#ifdef CONFIG_PM
588
589/*
590 * Restore the MMC host context, if it was lost as result of a
591 * power state change.
592 */
70a3341a 593static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 594{
595 struct mmc_ios *ios = &host->mmc->ios;
596 struct omap_mmc_platform_data *pdata = host->pdata;
597 int context_loss = 0;
598 u32 hctl, capa, con;
599 u16 dsor = 0;
600 unsigned long timeout;
601
602 if (pdata->get_context_loss_count) {
603 context_loss = pdata->get_context_loss_count(host->dev);
604 if (context_loss < 0)
605 return 1;
606 }
607
608 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
609 context_loss == host->context_loss ? "not " : "");
610 if (host->context_loss == context_loss)
611 return 1;
612
613 /* Wait for hardware reset */
614 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
615 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
616 && time_before(jiffies, timeout))
617 ;
618
619 /* Do software reset */
620 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
621 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
622 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
623 && time_before(jiffies, timeout))
624 ;
625
626 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
627 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
628
629 if (host->id == OMAP_MMC1_DEVID) {
630 if (host->power_mode != MMC_POWER_OFF &&
631 (1 << ios->vdd) <= MMC_VDD_23_24)
632 hctl = SDVS18;
633 else
634 hctl = SDVS30;
635 capa = VS30 | VS18;
636 } else {
637 hctl = SDVS18;
638 capa = VS18;
639 }
640
641 OMAP_HSMMC_WRITE(host->base, HCTL,
642 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
643
644 OMAP_HSMMC_WRITE(host->base, CAPA,
645 OMAP_HSMMC_READ(host->base, CAPA) | capa);
646
647 OMAP_HSMMC_WRITE(host->base, HCTL,
648 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
649
650 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
651 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
652 && time_before(jiffies, timeout))
653 ;
654
b417577d 655 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 656
657 /* Do not initialize card-specific things if the power is off */
658 if (host->power_mode == MMC_POWER_OFF)
659 goto out;
660
661 con = OMAP_HSMMC_READ(host->base, CON);
662 switch (ios->bus_width) {
663 case MMC_BUS_WIDTH_8:
664 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
665 break;
666 case MMC_BUS_WIDTH_4:
667 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
668 OMAP_HSMMC_WRITE(host->base, HCTL,
669 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
670 break;
671 case MMC_BUS_WIDTH_1:
672 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
673 OMAP_HSMMC_WRITE(host->base, HCTL,
674 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
675 break;
676 }
677
678 if (ios->clock) {
679 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
680 if (dsor < 1)
681 dsor = 1;
682
683 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
684 dsor++;
685
686 if (dsor > 250)
687 dsor = 250;
688 }
689
690 OMAP_HSMMC_WRITE(host->base, SYSCTL,
691 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
692 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
693 OMAP_HSMMC_WRITE(host->base, SYSCTL,
694 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
695
696 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
697 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
698 && time_before(jiffies, timeout))
699 ;
700
701 OMAP_HSMMC_WRITE(host->base, SYSCTL,
702 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
703
704 con = OMAP_HSMMC_READ(host->base, CON);
705 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
706 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
707 else
708 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
709out:
710 host->context_loss = context_loss;
711
712 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
713 return 0;
714}
715
716/*
717 * Save the MMC host context (store the number of power state changes so far).
718 */
70a3341a 719static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 720{
721 struct omap_mmc_platform_data *pdata = host->pdata;
722 int context_loss;
723
724 if (pdata->get_context_loss_count) {
725 context_loss = pdata->get_context_loss_count(host->dev);
726 if (context_loss < 0)
727 return;
728 host->context_loss = context_loss;
729 }
730}
731
732#else
733
70a3341a 734static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 735{
736 return 0;
737}
738
70a3341a 739static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 740{
741}
742
743#endif
744
a45c6cb8
MC		 745/*
746 * Send init stream sequence to card
747 * before sending IDLE command
748 */
70a3341a 749static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 750{
751 int reg = 0;
752 unsigned long timeout;
753
b62f6228
AH		 754 if (host->protect_card)
755 return;
756
a45c6cb8 757 disable_irq(host->irq);
b417577d
AH		 758
759 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 760 OMAP_HSMMC_WRITE(host->base, CON,
761 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
762 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
763
764 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
765 while ((reg != CC) && time_before(jiffies, timeout))
766 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
767
768 OMAP_HSMMC_WRITE(host->base, CON,
769 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 770
771 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
772 OMAP_HSMMC_READ(host->base, STAT);
773
a45c6cb8
MC		 774 enable_irq(host->irq);
775}
776
777static inline
70a3341a 778int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 779{
780 int r = 1;
781
191d1f1d
DK		 782 if (mmc_slot(host).get_cover_state)
783 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 784 return r;
785}
786
787static ssize_t
70a3341a 788omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 789 char *buf)
790{
791 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 792 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 793
70a3341a
DK		 794 return sprintf(buf, "%s\n",
795 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 796}
797
70a3341a 798static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 799
800static ssize_t
70a3341a 801omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 802 char *buf)
803{
804 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 805 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 806
191d1f1d 807 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 808}
809
70a3341a 810static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 811
812/*
813 * Configure the response type and send the cmd.
814 */
815static void
70a3341a 816omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 817 struct mmc_data *data)
818{
819 int cmdreg = 0, resptype = 0, cmdtype = 0;
820
821 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
822 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
823 host->cmd = cmd;
824
93caf8e6 825 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 826
4a694dc9 827 host->response_busy = 0;
a45c6cb8
MC		 828 if (cmd->flags & MMC_RSP_PRESENT) {
829 if (cmd->flags & MMC_RSP_136)
830 resptype = 1;
4a694dc9
AH		 831 else if (cmd->flags & MMC_RSP_BUSY) {
832 resptype = 3;
833 host->response_busy = 1;
834 } else
a45c6cb8
MC		 835 resptype = 2;
836 }
837
838 /*
839 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
840 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
841 * a val of 0x3, rest 0x0.
842 */
843 if (cmd == host->mrq->stop)
844 cmdtype = 0x3;
845
846 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
847
848 if (data) {
849 cmdreg |= DP_SELECT | MSBS | BCE;
850 if (data->flags & MMC_DATA_READ)
851 cmdreg |= DDIR;
852 else
853 cmdreg &= ~(DDIR);
854 }
855
856 if (host->use_dma)
857 cmdreg |= DMA_EN;
858
b417577d 859 host->req_in_progress = 1;
4dffd7a2 860
a45c6cb8
MC		 861 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
862 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
863}
864
0ccd76d4 865static int
70a3341a 866omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 867{
868 if (data->flags & MMC_DATA_WRITE)
869 return DMA_TO_DEVICE;
870 else
871 return DMA_FROM_DEVICE;
872}
873
b417577d
AH		 874static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
875{
876 int dma_ch;
877
878 spin_lock(&host->irq_lock);
879 host->req_in_progress = 0;
880 dma_ch = host->dma_ch;
881 spin_unlock(&host->irq_lock);
882
883 omap_hsmmc_disable_irq(host);
884 /* Do not complete the request if DMA is still in progress */
885 if (mrq->data && host->use_dma && dma_ch != -1)
886 return;
887 host->mrq = NULL;
888 mmc_request_done(host->mmc, mrq);
889}
890
a45c6cb8
MC		 891/*
892 * Notify the transfer complete to MMC core
893 */
894static void
70a3341a 895omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 896{
4a694dc9
AH		 897 if (!data) {
898 struct mmc_request *mrq = host->mrq;
899
23050103
AH		 900 /* TC before CC from CMD6 - don't know why, but it happens */
901 if (host->cmd && host->cmd->opcode == 6 &&
902 host->response_busy) {
903 host->response_busy = 0;
904 return;
905 }
906
b417577d 907 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 908 return;
909 }
910
a45c6cb8
MC		 911 host->data = NULL;
912
a45c6cb8
MC		 913 if (!data->error)
914 data->bytes_xfered += data->blocks * (data->blksz);
915 else
916 data->bytes_xfered = 0;
917
918 if (!data->stop) {
b417577d 919 omap_hsmmc_request_done(host, data->mrq);
a45c6cb8
MC		 920 return;
921 }
70a3341a 922 omap_hsmmc_start_command(host, data->stop, NULL);
a45c6cb8
MC		 923}
924
925/*
926 * Notify the core about command completion
927 */
928static void
70a3341a 929omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 930{
931 host->cmd = NULL;
932
933 if (cmd->flags & MMC_RSP_PRESENT) {
934 if (cmd->flags & MMC_RSP_136) {
935 /* response type 2 */
936 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
937 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
938 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
939 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
940 } else {
941 /* response types 1, 1b, 3, 4, 5, 6 */
942 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
943 }
944 }
b417577d
AH		 945 if ((host->data == NULL && !host->response_busy) || cmd->error)
946 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 947}
948
949/*
950 * DMA clean up for command errors
951 */
70a3341a 952static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 953{
b417577d
AH		 954 int dma_ch;
955
82788ff5 956 host->data->error = errno;
a45c6cb8 957
b417577d
AH		 958 spin_lock(&host->irq_lock);
959 dma_ch = host->dma_ch;
960 host->dma_ch = -1;
961 spin_unlock(&host->irq_lock);
962
963 if (host->use_dma && dma_ch != -1) {
a45c6cb8 964 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
70a3341a 965 omap_hsmmc_get_dma_dir(host, host->data));
b417577d 966 omap_free_dma(dma_ch);
a45c6cb8
MC		 967 }
968 host->data = NULL;
a45c6cb8
MC		 969}
970
971/*
972 * Readable error output
973 */
974#ifdef CONFIG_MMC_DEBUG
70a3341a 975static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 976{
977 /* --- means reserved bit without definition at documentation */
70a3341a 978 static const char *omap_hsmmc_status_bits[] = {
a45c6cb8
MC		 979 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
980 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
981 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
982 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
983 };
984 char res[256];
985 char *buf = res;
986 int len, i;
987
988 len = sprintf(buf, "MMC IRQ 0x%x :", status);
989 buf += len;
990
70a3341a 991 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 992 if (status & (1 << i)) {
70a3341a 993 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 994 buf += len;
995 }
996
997 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
998}
999#endif /* CONFIG_MMC_DEBUG */
1000
3ebf74b1
JP		 1001/*
1002 * MMC controller internal state machines reset
1003 *
1004 * Used to reset command or data internal state machines, using respectively
1005 * SRC or SRD bit of SYSCTL register
1006 * Can be called from interrupt context
1007 */
70a3341a
DK		 1008static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1009 unsigned long bit)
3ebf74b1
JP		 1010{
1011 unsigned long i = 0;
1012 unsigned long limit = (loops_per_jiffy *
1013 msecs_to_jiffies(MMC_TIMEOUT_MS));
1014
1015 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1016 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1017
07ad64b6
MC		 1018 /*
1019 * OMAP4 ES2 and greater has an updated reset logic.
1020 * Monitor a 0->1 transition first
1021 */
1022 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
b432b4b3 1023 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
07ad64b6
MC		 1024 && (i++ < limit))
1025 cpu_relax();
1026 }
1027 i = 0;
1028
3ebf74b1
JP		 1029 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1030 (i++ < limit))
1031 cpu_relax();
1032
1033 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1034 dev_err(mmc_dev(host->mmc),
1035 "Timeout waiting on controller reset in %s\n",
1036 __func__);
1037}
a45c6cb8 1038
b417577d 1039static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 1040{
a45c6cb8 1041 struct mmc_data *data;
b417577d
AH		 1042 int end_cmd = 0, end_trans = 0;
1043
1044 if (!host->req_in_progress) {
1045 do {
1046 OMAP_HSMMC_WRITE(host->base, STAT, status);
1047 /* Flush posted write */
1048 status = OMAP_HSMMC_READ(host->base, STAT);
1049 } while (status & INT_EN_MASK);
1050 return;
a45c6cb8
MC		 1051 }
1052
1053 data = host->data;
a45c6cb8
MC		 1054 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1055
1056 if (status & ERR) {
1057#ifdef CONFIG_MMC_DEBUG
70a3341a 1058 omap_hsmmc_report_irq(host, status);
a45c6cb8
MC		 1059#endif
1060 if ((status & CMD_TIMEOUT) ||
1061 (status & CMD_CRC)) {
1062 if (host->cmd) {
1063 if (status & CMD_TIMEOUT) {
70a3341a
DK		 1064 omap_hsmmc_reset_controller_fsm(host,
1065 SRC);
a45c6cb8
MC		 1066 host->cmd->error = -ETIMEDOUT;
1067 } else {
1068 host->cmd->error = -EILSEQ;
1069 }
1070 end_cmd = 1;
1071 }
4a694dc9
AH		 1072 if (host->data || host->response_busy) {
1073 if (host->data)
70a3341a
DK		 1074 omap_hsmmc_dma_cleanup(host,
1075 -ETIMEDOUT);
4a694dc9 1076 host->response_busy = 0;
70a3341a 1077 omap_hsmmc_reset_controller_fsm(host, SRD);
c232f457 1078 }
a45c6cb8
MC		 1079 }
1080 if ((status & DATA_TIMEOUT) ||
1081 (status & DATA_CRC)) {
4a694dc9
AH		 1082 if (host->data || host->response_busy) {
1083 int err = (status & DATA_TIMEOUT) ?
1084 -ETIMEDOUT : -EILSEQ;
1085
1086 if (host->data)
70a3341a 1087 omap_hsmmc_dma_cleanup(host, err);
a45c6cb8 1088 else
4a694dc9
AH		 1089 host->mrq->cmd->error = err;
1090 host->response_busy = 0;
70a3341a 1091 omap_hsmmc_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 1092 end_trans = 1;
1093 }
1094 }
1095 if (status & CARD_ERR) {
1096 dev_dbg(mmc_dev(host->mmc),
1097 "Ignoring card err CMD%d\n", host->cmd->opcode);
1098 if (host->cmd)
1099 end_cmd = 1;
1100 if (host->data)
1101 end_trans = 1;
1102 }
1103 }
1104
1105 OMAP_HSMMC_WRITE(host->base, STAT, status);
1106
a8fe29d8 1107 if (end_cmd || ((status & CC) && host->cmd))
70a3341a 1108 omap_hsmmc_cmd_done(host, host->cmd);
0a40e647 1109 if ((end_trans || (status & TC)) && host->mrq)
70a3341a 1110 omap_hsmmc_xfer_done(host, data);
b417577d 1111}
a45c6cb8 1112
b417577d
AH		 1113/*
1114 * MMC controller IRQ handler
1115 */
1116static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1117{
1118 struct omap_hsmmc_host *host = dev_id;
1119 int status;
1120
1121 status = OMAP_HSMMC_READ(host->base, STAT);
1122 do {
1123 omap_hsmmc_do_irq(host, status);
1124 /* Flush posted write */
1125 status = OMAP_HSMMC_READ(host->base, STAT);
1126 } while (status & INT_EN_MASK);
4dffd7a2 1127
a45c6cb8
MC		 1128 return IRQ_HANDLED;
1129}
1130
70a3341a 1131static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1132{
1133 unsigned long i;
1134
1135 OMAP_HSMMC_WRITE(host->base, HCTL,
1136 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1137 for (i = 0; i < loops_per_jiffy; i++) {
1138 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1139 break;
1140 cpu_relax();
1141 }
1142}
1143
a45c6cb8 1144/*
eb250826
DB		 1145 * Switch MMC interface voltage ... only relevant for MMC1.
1146 *
1147 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1148 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1149 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1150 */
70a3341a 1151static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1152{
1153 u32 reg_val = 0;
1154 int ret;
1155
1156 /* Disable the clocks */
1157 clk_disable(host->fclk);
1158 clk_disable(host->iclk);
2bec0893
AH		 1159 if (host->got_dbclk)
1160 clk_disable(host->dbclk);
a45c6cb8
MC		 1161
1162 /* Turn the power off */
1163 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1164
1165 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1166 if (!ret)
1167 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1168 vdd);
1169 clk_enable(host->iclk);
1170 clk_enable(host->fclk);
1171 if (host->got_dbclk)
1172 clk_enable(host->dbclk);
1173
a45c6cb8
MC		 1174 if (ret != 0)
1175 goto err;
1176
a45c6cb8
MC		 1177 OMAP_HSMMC_WRITE(host->base, HCTL,
1178 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1179 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1180
a45c6cb8
MC		 1181 /*
1182 * If a MMC dual voltage card is detected, the set_ios fn calls
1183 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1184 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1185 *
eb250826
DB		 1186 * Cope with a bit of slop in the range ... per data sheets:
1187 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1188 * but recommended values are 1.71V to 1.89V
1189 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1190 * but recommended values are 2.7V to 3.3V
1191 *
1192 * Board setup code shouldn't permit anything very out-of-range.
1193 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1194 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1195 */
eb250826 1196 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1197 reg_val |= SDVS18;
eb250826
DB		 1198 else
1199 reg_val |= SDVS30;
a45c6cb8
MC		 1200
1201 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1202 set_sd_bus_power(host);
a45c6cb8
MC		 1203
1204 return 0;
1205err:
1206 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1207 return ret;
1208}
1209
b62f6228
AH		 1210/* Protect the card while the cover is open */
1211static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1212{
1213 if (!mmc_slot(host).get_cover_state)
1214 return;
1215
1216 host->reqs_blocked = 0;
1217 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1218 if (host->protect_card) {
1219 printk(KERN_INFO "%s: cover is closed, "
1220 "card is now accessible\n",
1221 mmc_hostname(host->mmc));
1222 host->protect_card = 0;
1223 }
1224 } else {
1225 if (!host->protect_card) {
1226 printk(KERN_INFO "%s: cover is open, "
1227 "card is now inaccessible\n",
1228 mmc_hostname(host->mmc));
1229 host->protect_card = 1;
1230 }
1231 }
1232}
1233
a45c6cb8
MC		 1234/*
1235 * Work Item to notify the core about card insertion/removal
1236 */
70a3341a 1237static void omap_hsmmc_detect(struct work_struct *work)
a45c6cb8 1238{
70a3341a
DK		 1239 struct omap_hsmmc_host *host =
1240 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
249d0fa9 1241 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1242 int carddetect;
1243
1244 if (host->suspended)
1245 return;
1246
1247 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1248
191d1f1d 1249 if (slot->card_detect)
db0fefc5 1250 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1251 else {
1252 omap_hsmmc_protect_card(host);
a6b2240d 1253 carddetect = -ENOSYS;
b62f6228 1254 }
a45c6cb8 1255
cdeebadd 1256 if (carddetect)
a45c6cb8 1257 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1258 else
a45c6cb8 1259 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1260}
1261
1262/*
1263 * ISR for handling card insertion and removal
1264 */
70a3341a 1265static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
a45c6cb8 1266{
70a3341a 1267 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
a45c6cb8 1268
a6b2240d
AH		 1269 if (host->suspended)
1270 return IRQ_HANDLED;
a45c6cb8
MC		 1271 schedule_work(&host->mmc_carddetect_work);
1272
1273 return IRQ_HANDLED;
1274}
1275
70a3341a 1276static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1277 struct mmc_data *data)
1278{
1279 int sync_dev;
1280
f3e2f1dd
GI		 1281 if (data->flags & MMC_DATA_WRITE)
1282 sync_dev = host->dma_line_tx;
1283 else
1284 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 1285 return sync_dev;
1286}
1287
70a3341a 1288static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1289 struct mmc_data *data,
1290 struct scatterlist *sgl)
1291{
1292 int blksz, nblk, dma_ch;
1293
1294 dma_ch = host->dma_ch;
1295 if (data->flags & MMC_DATA_WRITE) {
1296 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1297 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1298 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1299 sg_dma_address(sgl), 0, 0);
1300 } else {
1301 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
191d1f1d 1302 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
0ccd76d4
JY		 1303 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1304 sg_dma_address(sgl), 0, 0);
1305 }
1306
1307 blksz = host->data->blksz;
1308 nblk = sg_dma_len(sgl) / blksz;
1309
1310 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1311 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
70a3341a 1312 omap_hsmmc_get_dma_sync_dev(host, data),
0ccd76d4
JY		 1313 !(data->flags & MMC_DATA_WRITE));
1314
1315 omap_start_dma(dma_ch);
1316}
1317
a45c6cb8
MC		 1318/*
1319 * DMA call back function
1320 */
b417577d 1321static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
a45c6cb8 1322{
b417577d
AH		 1323 struct omap_hsmmc_host *host = cb_data;
1324 struct mmc_data *data = host->mrq->data;
1325 int dma_ch, req_in_progress;
a45c6cb8 1326
f3584e5e
V		 1327 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1328 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1329 ch_status);
1330 return;
1331 }
a45c6cb8 1332
b417577d
AH		 1333 spin_lock(&host->irq_lock);
1334 if (host->dma_ch < 0) {
1335 spin_unlock(&host->irq_lock);
a45c6cb8 1336 return;
b417577d 1337 }
a45c6cb8 1338
0ccd76d4
JY		 1339 host->dma_sg_idx++;
1340 if (host->dma_sg_idx < host->dma_len) {
1341 /* Fire up the next transfer. */
b417577d
AH		 1342 omap_hsmmc_config_dma_params(host, data,
1343 data->sg + host->dma_sg_idx);
1344 spin_unlock(&host->irq_lock);
0ccd76d4
JY		 1345 return;
1346 }
1347
b417577d
AH		 1348 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
1349 omap_hsmmc_get_dma_dir(host, data));
1350
1351 req_in_progress = host->req_in_progress;
1352 dma_ch = host->dma_ch;
a45c6cb8 1353 host->dma_ch = -1;
b417577d
AH		 1354 spin_unlock(&host->irq_lock);
1355
1356 omap_free_dma(dma_ch);
1357
1358 /* If DMA has finished after TC, complete the request */
1359 if (!req_in_progress) {
1360 struct mmc_request *mrq = host->mrq;
1361
1362 host->mrq = NULL;
1363 mmc_request_done(host->mmc, mrq);
1364 }
a45c6cb8
MC		 1365}
1366
a45c6cb8
MC		 1367/*
1368 * Routine to configure and start DMA for the MMC card
1369 */
70a3341a
DK		 1370static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1371 struct mmc_request *req)
a45c6cb8 1372{
b417577d 1373 int dma_ch = 0, ret = 0, i;
a45c6cb8
MC		 1374 struct mmc_data *data = req->data;
1375
0ccd76d4 1376 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1377 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1378 struct scatterlist *sgl;
1379
1380 sgl = data->sg + i;
1381 if (sgl->length % data->blksz)
1382 return -EINVAL;
1383 }
1384 if ((data->blksz % 4) != 0)
1385 /* REVISIT: The MMC buffer increments only when MSB is written.
1386 * Return error for blksz which is non multiple of four.
1387 */
1388 return -EINVAL;
1389
b417577d 1390 BUG_ON(host->dma_ch != -1);
a45c6cb8 1391
70a3341a
DK		 1392 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1393 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
a45c6cb8 1394 if (ret != 0) {
0ccd76d4 1395 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 1396 "%s: omap_request_dma() failed with %d\n",
1397 mmc_hostname(host->mmc), ret);
1398 return ret;
1399 }
1400
1401 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
70a3341a 1402 data->sg_len, omap_hsmmc_get_dma_dir(host, data));
a45c6cb8 1403 host->dma_ch = dma_ch;
0ccd76d4 1404 host->dma_sg_idx = 0;
a45c6cb8 1405
70a3341a 1406 omap_hsmmc_config_dma_params(host, data, data->sg);
a45c6cb8 1407
a45c6cb8
MC		 1408 return 0;
1409}
1410
70a3341a 1411static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1412 unsigned int timeout_ns,
1413 unsigned int timeout_clks)
a45c6cb8
MC		 1414{
1415 unsigned int timeout, cycle_ns;
1416 uint32_t reg, clkd, dto = 0;
1417
1418 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1419 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1420 if (clkd == 0)
1421 clkd = 1;
1422
1423 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1424 timeout = timeout_ns / cycle_ns;
1425 timeout += timeout_clks;
a45c6cb8
MC		 1426 if (timeout) {
1427 while ((timeout & 0x80000000) == 0) {
1428 dto += 1;
1429 timeout <<= 1;
1430 }
1431 dto = 31 - dto;
1432 timeout <<= 1;
1433 if (timeout && dto)
1434 dto += 1;
1435 if (dto >= 13)
1436 dto -= 13;
1437 else
1438 dto = 0;
1439 if (dto > 14)
1440 dto = 14;
1441 }
1442
1443 reg &= ~DTO_MASK;
1444 reg |= dto << DTO_SHIFT;
1445 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1446}
1447
1448/*
1449 * Configure block length for MMC/SD cards and initiate the transfer.
1450 */
1451static int
70a3341a 1452omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1453{
1454 int ret;
1455 host->data = req->data;
1456
1457 if (req->data == NULL) {
a45c6cb8 1458 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1459 /*
1460 * Set an arbitrary 100ms data timeout for commands with
1461 * busy signal.
1462 */
1463 if (req->cmd->flags & MMC_RSP_BUSY)
1464 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1465 return 0;
1466 }
1467
1468 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1469 | (req->data->blocks << 16));
e2bf08d6 1470 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1471
a45c6cb8 1472 if (host->use_dma) {
70a3341a 1473 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8
MC		 1474 if (ret != 0) {
1475 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1476 return ret;
1477 }
1478 }
1479 return 0;
1480}
1481
1482/*
1483 * Request function. for read/write operation
1484 */
70a3341a 1485static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1486{
70a3341a 1487 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1488 int err;
a45c6cb8 1489
b417577d
AH		 1490 BUG_ON(host->req_in_progress);
1491 BUG_ON(host->dma_ch != -1);
1492 if (host->protect_card) {
1493 if (host->reqs_blocked < 3) {
1494 /*
1495 * Ensure the controller is left in a consistent
1496 * state by resetting the command and data state
1497 * machines.
1498 */
1499 omap_hsmmc_reset_controller_fsm(host, SRD);
1500 omap_hsmmc_reset_controller_fsm(host, SRC);
1501 host->reqs_blocked += 1;
1502 }
1503 req->cmd->error = -EBADF;
1504 if (req->data)
1505 req->data->error = -EBADF;
1506 req->cmd->retries = 0;
1507 mmc_request_done(mmc, req);
1508 return;
1509 } else if (host->reqs_blocked)
1510 host->reqs_blocked = 0;
a45c6cb8
MC		 1511 WARN_ON(host->mrq != NULL);
1512 host->mrq = req;
70a3341a 1513 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1514 if (err) {
1515 req->cmd->error = err;
1516 if (req->data)
1517 req->data->error = err;
1518 host->mrq = NULL;
1519 mmc_request_done(mmc, req);
1520 return;
1521 }
1522
70a3341a 1523 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1524}
1525
a45c6cb8 1526/* Routine to configure clock values. Exposed API to core */
70a3341a 1527static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1528{
70a3341a 1529 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8
MC		 1530 u16 dsor = 0;
1531 unsigned long regval;
1532 unsigned long timeout;
73153010 1533 u32 con;
a3621465 1534 int do_send_init_stream = 0;
a45c6cb8 1535
5e2ea617
AH		 1536 mmc_host_enable(host->mmc);
1537
a3621465
AH		 1538 if (ios->power_mode != host->power_mode) {
1539 switch (ios->power_mode) {
1540 case MMC_POWER_OFF:
1541 mmc_slot(host).set_power(host->dev, host->slot_id,
1542 0, 0);
623821f7 1543 host->vdd = 0;
a3621465
AH		 1544 break;
1545 case MMC_POWER_UP:
1546 mmc_slot(host).set_power(host->dev, host->slot_id,
1547 1, ios->vdd);
623821f7 1548 host->vdd = ios->vdd;
a3621465
AH		 1549 break;
1550 case MMC_POWER_ON:
1551 do_send_init_stream = 1;
1552 break;
1553 }
1554 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1555 }
1556
dd498eff
DK		 1557 /* FIXME: set registers based only on changes to ios */
1558
73153010 1559 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1560 switch (mmc->ios.bus_width) {
73153010
JL		 1561 case MMC_BUS_WIDTH_8:
1562 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1563 break;
a45c6cb8 1564 case MMC_BUS_WIDTH_4:
73153010 1565 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1566 OMAP_HSMMC_WRITE(host->base, HCTL,
1567 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1568 break;
1569 case MMC_BUS_WIDTH_1:
73153010 1570 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1571 OMAP_HSMMC_WRITE(host->base, HCTL,
1572 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1573 break;
1574 }
1575
4621d5f8 1576 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
eb250826
DB		 1577 /* Only MMC1 can interface at 3V without some flavor
1578 * of external transceiver; but they all handle 1.8V.
1579 */
a45c6cb8
MC		 1580 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1581 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1582 /*
1583 * The mmc_select_voltage fn of the core does
1584 * not seem to set the power_mode to
1585 * MMC_POWER_UP upon recalculating the voltage.
1586 * vdd 1.8v.
1587 */
70a3341a
DK		 1588 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1589 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1590 "Switch operation failed\n");
1591 }
1592 }
1593
1594 if (ios->clock) {
1595 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1596 if (dsor < 1)
1597 dsor = 1;
1598
1599 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1600 dsor++;
1601
1602 if (dsor > 250)
1603 dsor = 250;
1604 }
70a3341a 1605 omap_hsmmc_stop_clock(host);
a45c6cb8
MC		 1606 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1607 regval = regval & ~(CLKD_MASK);
1608 regval = regval | (dsor << 6) | (DTO << 16);
1609 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1610 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1611 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1612
1613 /* Wait till the ICS bit is set */
1614 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
11dd62a7 1615 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
a45c6cb8
MC		 1616 && time_before(jiffies, timeout))
1617 msleep(1);
1618
1619 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1620 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1621
a3621465 1622 if (do_send_init_stream)
a45c6cb8
MC		 1623 send_init_stream(host);
1624
abb28e73 1625 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1626 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
abb28e73
DK		 1627 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1628 else
1629 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
5e2ea617 1630
dd498eff
DK		 1631 if (host->power_mode == MMC_POWER_OFF)
1632 mmc_host_disable(host->mmc);
1633 else
1634 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 1635}
1636
1637static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1638{
70a3341a 1639 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1640
191d1f1d 1641 if (!mmc_slot(host).card_detect)
a45c6cb8 1642 return -ENOSYS;
db0fefc5 1643 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1644}
1645
1646static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1647{
70a3341a 1648 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1649
191d1f1d 1650 if (!mmc_slot(host).get_ro)
a45c6cb8 1651 return -ENOSYS;
191d1f1d 1652 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1653}
1654
4816858c
GI		 1655static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1656{
1657 struct omap_hsmmc_host *host = mmc_priv(mmc);
1658
1659 if (mmc_slot(host).init_card)
1660 mmc_slot(host).init_card(card);
1661}
1662
70a3341a 1663static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1664{
1665 u32 hctl, capa, value;
1666
1667 /* Only MMC1 supports 3.0V */
4621d5f8 1668 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1b331e69
KK		 1669 hctl = SDVS30;
1670 capa = VS30 | VS18;
1671 } else {
1672 hctl = SDVS18;
1673 capa = VS18;
1674 }
1675
1676 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1677 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1678
1679 value = OMAP_HSMMC_READ(host->base, CAPA);
1680 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1681
1682 /* Set the controller to AUTO IDLE mode */
1683 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1684 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1685
1686 /* Set SD bus power bit */
e13bb300 1687 set_sd_bus_power(host);
1b331e69
KK		 1688}
1689
dd498eff
DK		 1690/*
1691 * Dynamic power saving handling, FSM:
13189e78
JL		 1692 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1693 * ^___________| | |
1694 * |______________________|______________________|
dd498eff
DK		 1695 *
1696 * ENABLED: mmc host is fully functional
1697 * DISABLED: fclk is off
13189e78
JL		 1698 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1699 * REGSLEEP: fclk is off, voltage regulator is asleep
1700 * OFF: fclk is off, voltage regulator is off
dd498eff
DK		 1701 *
1702 * Transition handlers return the timeout for the next state transition
1703 * or negative error.
1704 */
1705
13189e78 1706enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
dd498eff
DK		 1707
1708/* Handler for [ENABLED -> DISABLED] transition */
70a3341a 1709static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
dd498eff 1710{
70a3341a 1711 omap_hsmmc_context_save(host);
dd498eff
DK		 1712 clk_disable(host->fclk);
1713 host->dpm_state = DISABLED;
1714
1715 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1716
1717 if (host->power_mode == MMC_POWER_OFF)
1718 return 0;
1719
4380eea2 1720 return OMAP_MMC_SLEEP_TIMEOUT;
dd498eff
DK		 1721}
1722
13189e78 1723/* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
70a3341a 1724static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
dd498eff 1725{
13189e78 1726 int err, new_state;
dd498eff
DK		 1727
1728 if (!mmc_try_claim_host(host->mmc))
1729 return 0;
1730
1731 clk_enable(host->fclk);
70a3341a 1732 omap_hsmmc_context_restore(host);
13189e78
JL		 1733 if (mmc_card_can_sleep(host->mmc)) {
1734 err = mmc_card_sleep(host->mmc);
1735 if (err < 0) {
1736 clk_disable(host->fclk);
1737 mmc_release_host(host->mmc);
1738 return err;
1739 }
1740 new_state = CARDSLEEP;
70a3341a 1741 } else {
13189e78 1742 new_state = REGSLEEP;
70a3341a 1743 }
13189e78
JL		 1744 if (mmc_slot(host).set_sleep)
1745 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1746 new_state == CARDSLEEP);
1747 /* FIXME: turn off bus power and perhaps interrupts too */
1748 clk_disable(host->fclk);
1749 host->dpm_state = new_state;
1750
1751 mmc_release_host(host->mmc);
1752
1753 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1754 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff 1755
1df58db8
AH		 1756 if (mmc_slot(host).no_off)
1757 return 0;
1758
dd498eff
DK		 1759 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1760 mmc_slot(host).card_detect ||
1761 (mmc_slot(host).get_cover_state &&
13189e78 1762 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
4380eea2 1763 return OMAP_MMC_OFF_TIMEOUT;
13189e78
JL		 1764
1765 return 0;
1766}
1767
1768/* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
70a3341a 1769static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
13189e78
JL		 1770{
1771 if (!mmc_try_claim_host(host->mmc))
1772 return 0;
1773
1df58db8
AH		 1774 if (mmc_slot(host).no_off)
1775 return 0;
1776
13189e78
JL		 1777 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1778 mmc_slot(host).card_detect ||
1779 (mmc_slot(host).get_cover_state &&
1780 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1781 mmc_release_host(host->mmc);
1782 return 0;
623821f7 1783 }
dd498eff 1784
13189e78
JL		 1785 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1786 host->vdd = 0;
1787 host->power_mode = MMC_POWER_OFF;
dd498eff 1788
13189e78
JL		 1789 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1790 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff 1791
13189e78 1792 host->dpm_state = OFF;
dd498eff
DK		 1793
1794 mmc_release_host(host->mmc);
1795
1796 return 0;
1797}
1798
1799/* Handler for [DISABLED -> ENABLED] transition */
70a3341a 1800static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
dd498eff
DK		 1801{
1802 int err;
1803
1804 err = clk_enable(host->fclk);
1805 if (err < 0)
1806 return err;
1807
70a3341a 1808 omap_hsmmc_context_restore(host);
dd498eff
DK		 1809 host->dpm_state = ENABLED;
1810
1811 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1812
1813 return 0;
1814}
1815
13189e78 1816/* Handler for [SLEEP -> ENABLED] transition */
70a3341a 1817static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
dd498eff 1818{
13189e78
JL		 1819 if (!mmc_try_claim_host(host->mmc))
1820 return 0;
dd498eff 1821
13189e78 1822 clk_enable(host->fclk);
70a3341a 1823 omap_hsmmc_context_restore(host);
13189e78
JL		 1824 if (mmc_slot(host).set_sleep)
1825 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1826 host->vdd, host->dpm_state == CARDSLEEP);
1827 if (mmc_card_can_sleep(host->mmc))
1828 mmc_card_awake(host->mmc);
1829
1830 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1831 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff
DK		 1832
1833 host->dpm_state = ENABLED;
1834
13189e78 1835 mmc_release_host(host->mmc);
dd498eff
DK		 1836
1837 return 0;
1838}
1839
13189e78 1840/* Handler for [OFF -> ENABLED] transition */
70a3341a 1841static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
623821f7 1842{
623821f7 1843 clk_enable(host->fclk);
623821f7 1844
70a3341a
DK		 1845 omap_hsmmc_context_restore(host);
1846 omap_hsmmc_conf_bus_power(host);
13189e78 1847 mmc_power_restore_host(host->mmc);
623821f7
AH		 1848
1849 host->dpm_state = ENABLED;
1850
13189e78
JL		 1851 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1852
623821f7
AH		 1853 return 0;
1854}
1855
dd498eff
DK		 1856/*
1857 * Bring MMC host to ENABLED from any other PM state.
1858 */
70a3341a 1859static int omap_hsmmc_enable(struct mmc_host *mmc)
dd498eff 1860{
70a3341a 1861 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1862
1863 switch (host->dpm_state) {
1864 case DISABLED:
70a3341a 1865 return omap_hsmmc_disabled_to_enabled(host);
13189e78 1866 case CARDSLEEP:
623821f7 1867 case REGSLEEP:
70a3341a 1868 return omap_hsmmc_sleep_to_enabled(host);
dd498eff 1869 case OFF:
70a3341a 1870 return omap_hsmmc_off_to_enabled(host);
dd498eff
DK		 1871 default:
1872 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1873 return -EINVAL;
1874 }
1875}
1876
1877/*
1878 * Bring MMC host in PM state (one level deeper).
1879 */
70a3341a 1880static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
dd498eff 1881{
70a3341a 1882 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1883
1884 switch (host->dpm_state) {
1885 case ENABLED: {
1886 int delay;
1887
70a3341a 1888 delay = omap_hsmmc_enabled_to_disabled(host);
dd498eff
DK		 1889 if (lazy || delay < 0)
1890 return delay;
1891 return 0;
1892 }
1893 case DISABLED:
70a3341a 1894 return omap_hsmmc_disabled_to_sleep(host);
13189e78
JL		 1895 case CARDSLEEP:
1896 case REGSLEEP:
70a3341a 1897 return omap_hsmmc_sleep_to_off(host);
dd498eff
DK		 1898 default:
1899 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1900 return -EINVAL;
1901 }
1902}
1903
70a3341a 1904static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1905{
70a3341a 1906 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1907 int err;
1908
1909 err = clk_enable(host->fclk);
1910 if (err)
1911 return err;
1912 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
70a3341a 1913 omap_hsmmc_context_restore(host);
dd498eff
DK		 1914 return 0;
1915}
1916
70a3341a 1917static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
dd498eff 1918{
70a3341a 1919 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1920
70a3341a 1921 omap_hsmmc_context_save(host);
dd498eff
DK		 1922 clk_disable(host->fclk);
1923 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1924 return 0;
1925}
1926
70a3341a
DK		 1927static const struct mmc_host_ops omap_hsmmc_ops = {
1928 .enable = omap_hsmmc_enable_fclk,
1929 .disable = omap_hsmmc_disable_fclk,
1930 .request = omap_hsmmc_request,
1931 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1932 .get_cd = omap_hsmmc_get_cd,
1933 .get_ro = omap_hsmmc_get_ro,
4816858c 1934 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1935 /* NYET -- enable_sdio_irq */
1936};
1937
70a3341a
DK		 1938static const struct mmc_host_ops omap_hsmmc_ps_ops = {
1939 .enable = omap_hsmmc_enable,
1940 .disable = omap_hsmmc_disable,
1941 .request = omap_hsmmc_request,
1942 .set_ios = omap_hsmmc_set_ios,
a45c6cb8
MC		 1943 .get_cd = omap_hsmmc_get_cd,
1944 .get_ro = omap_hsmmc_get_ro,
4816858c 1945 .init_card = omap_hsmmc_init_card,
a45c6cb8
MC		 1946 /* NYET -- enable_sdio_irq */
1947};
1948
d900f712
DK		 1949#ifdef CONFIG_DEBUG_FS
1950
70a3341a 1951static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1952{
1953 struct mmc_host *mmc = s->private;
70a3341a 1954 struct omap_hsmmc_host *host = mmc_priv(mmc);
11dd62a7
DK		 1955 int context_loss = 0;
1956
70a3341a
DK		 1957 if (host->pdata->get_context_loss_count)
1958 context_loss = host->pdata->get_context_loss_count(host->dev);
d900f712 1959
5e2ea617
AH		 1960 seq_printf(s, "mmc%d:\n"
1961 " enabled:\t%d\n"
dd498eff 1962 " dpm_state:\t%d\n"
5e2ea617 1963 " nesting_cnt:\t%d\n"
11dd62a7 1964 " ctx_loss:\t%d:%d\n"
5e2ea617 1965 "\nregs:\n",
dd498eff
DK		 1966 mmc->index, mmc->enabled ? 1 : 0,
1967 host->dpm_state, mmc->nesting_cnt,
11dd62a7 1968 host->context_loss, context_loss);
5e2ea617 1969
13189e78 1970 if (host->suspended || host->dpm_state == OFF) {
dd498eff
DK		 1971 seq_printf(s, "host suspended, can't read registers\n");
1972 return 0;
1973 }
1974
5e2ea617
AH		 1975 if (clk_enable(host->fclk) != 0) {
1976 seq_printf(s, "can't read the regs\n");
dd498eff 1977 return 0;
5e2ea617 1978 }
d900f712
DK		 1979
1980 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1981 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1982 seq_printf(s, "CON:\t\t0x%08x\n",
1983 OMAP_HSMMC_READ(host->base, CON));
1984 seq_printf(s, "HCTL:\t\t0x%08x\n",
1985 OMAP_HSMMC_READ(host->base, HCTL));
1986 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1987 OMAP_HSMMC_READ(host->base, SYSCTL));
1988 seq_printf(s, "IE:\t\t0x%08x\n",
1989 OMAP_HSMMC_READ(host->base, IE));
1990 seq_printf(s, "ISE:\t\t0x%08x\n",
1991 OMAP_HSMMC_READ(host->base, ISE));
1992 seq_printf(s, "CAPA:\t\t0x%08x\n",
1993 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617
AH		 1994
1995 clk_disable(host->fclk);
dd498eff 1996
d900f712
DK		 1997 return 0;
1998}
1999
70a3341a 2000static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 2001{
70a3341a 2002 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 2003}
2004
2005static const struct file_operations mmc_regs_fops = {
70a3341a 2006 .open = omap_hsmmc_regs_open,
d900f712
DK		 2007 .read = seq_read,
2008 .llseek = seq_lseek,
2009 .release = single_release,
2010};
2011
70a3341a 2012static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 2013{
2014 if (mmc->debugfs_root)
2015 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
2016 mmc, &mmc_regs_fops);
2017}
2018
2019#else
2020
70a3341a 2021static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 2022{
2023}
2024
2025#endif
2026
70a3341a 2027static int __init omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 2028{
2029 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
2030 struct mmc_host *mmc;
70a3341a 2031 struct omap_hsmmc_host *host = NULL;
a45c6cb8 2032 struct resource *res;
db0fefc5 2033 int ret, irq;
a45c6cb8
MC		 2034
2035 if (pdata == NULL) {
2036 dev_err(&pdev->dev, "Platform Data is missing\n");
2037 return -ENXIO;
2038 }
2039
2040 if (pdata->nr_slots == 0) {
2041 dev_err(&pdev->dev, "No Slots\n");
2042 return -ENXIO;
2043 }
2044
2045 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2046 irq = platform_get_irq(pdev, 0);
2047 if (res == NULL || irq < 0)
2048 return -ENXIO;
2049
91a0b089 2050 res->start += pdata->reg_offset;
2051 res->end += pdata->reg_offset;
984b203a 2052 res = request_mem_region(res->start, resource_size(res), pdev->name);
a45c6cb8
MC		 2053 if (res == NULL)
2054 return -EBUSY;
2055
db0fefc5
AH		 2056 ret = omap_hsmmc_gpio_init(pdata);
2057 if (ret)
2058 goto err;
2059
70a3341a 2060 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 2061 if (!mmc) {
2062 ret = -ENOMEM;
db0fefc5 2063 goto err_alloc;
a45c6cb8
MC		 2064 }
2065
2066 host = mmc_priv(mmc);
2067 host->mmc = mmc;
2068 host->pdata = pdata;
2069 host->dev = &pdev->dev;
2070 host->use_dma = 1;
2071 host->dev->dma_mask = &pdata->dma_mask;
2072 host->dma_ch = -1;
2073 host->irq = irq;
2074 host->id = pdev->id;
2075 host->slot_id = 0;
2076 host->mapbase = res->start;
2077 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 2078 host->power_mode = MMC_POWER_OFF;
a45c6cb8
MC		 2079
2080 platform_set_drvdata(pdev, host);
70a3341a 2081 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
a45c6cb8 2082
191d1f1d 2083 if (mmc_slot(host).power_saving)
70a3341a 2084 mmc->ops = &omap_hsmmc_ps_ops;
dd498eff 2085 else
70a3341a 2086 mmc->ops = &omap_hsmmc_ops;
dd498eff 2087
e0eb2424
AH		 2088 /*
2089 * If regulator_disable can only put vcc_aux to sleep then there is
2090 * no off state.
2091 */
2092 if (mmc_slot(host).vcc_aux_disable_is_sleep)
2093 mmc_slot(host).no_off = 1;
2094
a45c6cb8
MC		 2095 mmc->f_min = 400000;
2096 mmc->f_max = 52000000;
2097
4dffd7a2 2098 spin_lock_init(&host->irq_lock);
a45c6cb8 2099
6f7607cc 2100 host->iclk = clk_get(&pdev->dev, "ick");
a45c6cb8
MC		 2101 if (IS_ERR(host->iclk)) {
2102 ret = PTR_ERR(host->iclk);
2103 host->iclk = NULL;
2104 goto err1;
2105 }
6f7607cc 2106 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 2107 if (IS_ERR(host->fclk)) {
2108 ret = PTR_ERR(host->fclk);
2109 host->fclk = NULL;
2110 clk_put(host->iclk);
2111 goto err1;
2112 }
2113
70a3341a 2114 omap_hsmmc_context_save(host);
11dd62a7 2115
5e2ea617 2116 mmc->caps |= MMC_CAP_DISABLE;
dd498eff
DK		 2117 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
2118 /* we start off in DISABLED state */
2119 host->dpm_state = DISABLED;
2120
a05dcdb9 2121 if (clk_enable(host->iclk) != 0) {
a45c6cb8
MC		 2122 clk_put(host->iclk);
2123 clk_put(host->fclk);
2124 goto err1;
2125 }
2126
a05dcdb9
PW		 2127 if (mmc_host_enable(host->mmc) != 0) {
2128 clk_disable(host->iclk);
a45c6cb8
MC		 2129 clk_put(host->iclk);
2130 clk_put(host->fclk);
2131 goto err1;
2132 }
2133
2bec0893
AH		 2134 if (cpu_is_omap2430()) {
2135 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2136 /*
2137 * MMC can still work without debounce clock.
2138 */
2139 if (IS_ERR(host->dbclk))
2140 dev_warn(mmc_dev(host->mmc),
2141 "Failed to get debounce clock\n");
a45c6cb8 2142 else
2bec0893
AH		 2143 host->got_dbclk = 1;
2144
2145 if (host->got_dbclk)
2146 if (clk_enable(host->dbclk) != 0)
2147 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2148 " clk failed\n");
2149 }
a45c6cb8 2150
0ccd76d4
JY		 2151 /* Since we do only SG emulation, we can have as many segs
2152 * as we want. */
a36274e0 2153 mmc->max_segs = 1024;
0ccd76d4 2154
a45c6cb8
MC		 2155 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2156 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2157 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2158 mmc->max_seg_size = mmc->max_req_size;
2159
13189e78 2160 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 2161 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 2162
3a63833e
SG		 2163 mmc->caps |= mmc_slot(host).caps;
2164 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 2165 mmc->caps |= MMC_CAP_4_BIT_DATA;
2166
191d1f1d 2167 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 2168 mmc->caps |= MMC_CAP_NONREMOVABLE;
2169
70a3341a 2170 omap_hsmmc_conf_bus_power(host);
a45c6cb8 2171
f3e2f1dd
GI		 2172 /* Select DMA lines */
2173 switch (host->id) {
2174 case OMAP_MMC1_DEVID:
2175 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2176 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2177 break;
2178 case OMAP_MMC2_DEVID:
2179 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2180 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2181 break;
2182 case OMAP_MMC3_DEVID:
2183 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2184 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2185 break;
82cf818d 2186 case OMAP_MMC4_DEVID:
2187 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2188 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2189 break;
2190 case OMAP_MMC5_DEVID:
2191 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2192 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2193 break;
f3e2f1dd
GI		 2194 default:
2195 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2196 goto err_irq;
2197 }
a45c6cb8
MC		 2198
2199 /* Request IRQ for MMC operations */
70a3341a 2200 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
a45c6cb8
MC		 2201 mmc_hostname(mmc), host);
2202 if (ret) {
2203 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2204 goto err_irq;
2205 }
2206
2207 if (pdata->init != NULL) {
2208 if (pdata->init(&pdev->dev) != 0) {
70a3341a
DK		 2209 dev_dbg(mmc_dev(host->mmc),
2210 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 2211 goto err_irq_cd_init;
2212 }
2213 }
db0fefc5 2214
b702b106 2215 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 2216 ret = omap_hsmmc_reg_get(host);
2217 if (ret)
2218 goto err_reg;
2219 host->use_reg = 1;
2220 }
2221
b583f26d 2222 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 2223
2224 /* Request IRQ for card detect */
e1a55f5e 2225 if ((mmc_slot(host).card_detect_irq)) {
a45c6cb8 2226 ret = request_irq(mmc_slot(host).card_detect_irq,
70a3341a 2227 omap_hsmmc_cd_handler,
a45c6cb8
MC		 2228 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2229 | IRQF_DISABLED,
2230 mmc_hostname(mmc), host);
2231 if (ret) {
2232 dev_dbg(mmc_dev(host->mmc),
2233 "Unable to grab MMC CD IRQ\n");
2234 goto err_irq_cd;
2235 }
72f2e2c7 2236 pdata->suspend = omap_hsmmc_suspend_cdirq;
2237 pdata->resume = omap_hsmmc_resume_cdirq;
a45c6cb8
MC		 2238 }
2239
b417577d 2240 omap_hsmmc_disable_irq(host);
a45c6cb8 2241
5e2ea617
AH		 2242 mmc_host_lazy_disable(host->mmc);
2243
b62f6228
AH		 2244 omap_hsmmc_protect_card(host);
2245
a45c6cb8
MC		 2246 mmc_add_host(mmc);
2247
191d1f1d 2248 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 2249 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2250 if (ret < 0)
2251 goto err_slot_name;
2252 }
191d1f1d 2253 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 2254 ret = device_create_file(&mmc->class_dev,
2255 &dev_attr_cover_switch);
2256 if (ret < 0)
db0fefc5 2257 goto err_slot_name;
a45c6cb8
MC		 2258 }
2259
70a3341a 2260 omap_hsmmc_debugfs(mmc);
d900f712 2261
a45c6cb8
MC		 2262 return 0;
2263
a45c6cb8
MC		 2264err_slot_name:
2265 mmc_remove_host(mmc);
a45c6cb8 2266 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 2267err_irq_cd:
2268 if (host->use_reg)
2269 omap_hsmmc_reg_put(host);
2270err_reg:
2271 if (host->pdata->cleanup)
2272 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 2273err_irq_cd_init:
2274 free_irq(host->irq, host);
2275err_irq:
5e2ea617 2276 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2277 clk_disable(host->iclk);
2278 clk_put(host->fclk);
2279 clk_put(host->iclk);
2bec0893 2280 if (host->got_dbclk) {
a45c6cb8
MC		 2281 clk_disable(host->dbclk);
2282 clk_put(host->dbclk);
2283 }
a45c6cb8
MC		 2284err1:
2285 iounmap(host->base);
db0fefc5
AH		 2286 platform_set_drvdata(pdev, NULL);
2287 mmc_free_host(mmc);
2288err_alloc:
2289 omap_hsmmc_gpio_free(pdata);
a45c6cb8 2290err:
984b203a 2291 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2292 return ret;
2293}
2294
70a3341a 2295static int omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2296{
70a3341a 2297 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2298 struct resource *res;
2299
2300 if (host) {
5e2ea617 2301 mmc_host_enable(host->mmc);
a45c6cb8 2302 mmc_remove_host(host->mmc);
db0fefc5
AH		 2303 if (host->use_reg)
2304 omap_hsmmc_reg_put(host);
a45c6cb8
MC		 2305 if (host->pdata->cleanup)
2306 host->pdata->cleanup(&pdev->dev);
2307 free_irq(host->irq, host);
2308 if (mmc_slot(host).card_detect_irq)
2309 free_irq(mmc_slot(host).card_detect_irq, host);
0d9ee5b2 2310 flush_work_sync(&host->mmc_carddetect_work);
a45c6cb8 2311
5e2ea617 2312 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2313 clk_disable(host->iclk);
2314 clk_put(host->fclk);
2315 clk_put(host->iclk);
2bec0893 2316 if (host->got_dbclk) {
a45c6cb8
MC		 2317 clk_disable(host->dbclk);
2318 clk_put(host->dbclk);
2319 }
2320
2321 mmc_free_host(host->mmc);
2322 iounmap(host->base);
db0fefc5 2323 omap_hsmmc_gpio_free(pdev->dev.platform_data);
a45c6cb8
MC		 2324 }
2325
2326 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2327 if (res)
984b203a 2328 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2329 platform_set_drvdata(pdev, NULL);
2330
2331 return 0;
2332}
2333
2334#ifdef CONFIG_PM
a791daa1 2335static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8
MC		 2336{
2337 int ret = 0;
a791daa1 2338 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2339 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2340
2341 if (host && host->suspended)
2342 return 0;
2343
2344 if (host) {
a6b2240d
AH		 2345 host->suspended = 1;
2346 if (host->pdata->suspend) {
2347 ret = host->pdata->suspend(&pdev->dev,
2348 host->slot_id);
2349 if (ret) {
2350 dev_dbg(mmc_dev(host->mmc),
2351 "Unable to handle MMC board"
2352 " level suspend\n");
2353 host->suspended = 0;
2354 return ret;
2355 }
2356 }
2357 cancel_work_sync(&host->mmc_carddetect_work);
1a13f8fa 2358 ret = mmc_suspend_host(host->mmc);
e7cb756f 2359 mmc_host_enable(host->mmc);
a45c6cb8 2360 if (ret == 0) {
b417577d 2361 omap_hsmmc_disable_irq(host);
0683af48 2362 OMAP_HSMMC_WRITE(host->base, HCTL,
191d1f1d 2363 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
5e2ea617 2364 mmc_host_disable(host->mmc);
a45c6cb8 2365 clk_disable(host->iclk);
2bec0893
AH		 2366 if (host->got_dbclk)
2367 clk_disable(host->dbclk);
a6b2240d
AH		 2368 } else {
2369 host->suspended = 0;
2370 if (host->pdata->resume) {
2371 ret = host->pdata->resume(&pdev->dev,
2372 host->slot_id);
2373 if (ret)
2374 dev_dbg(mmc_dev(host->mmc),
2375 "Unmask interrupt failed\n");
2376 }
5e2ea617 2377 mmc_host_disable(host->mmc);
a6b2240d 2378 }
a45c6cb8
MC		 2379
2380 }
2381 return ret;
2382}
2383
2384/* Routine to resume the MMC device */
a791daa1 2385static int omap_hsmmc_resume(struct device *dev)
a45c6cb8
MC		 2386{
2387 int ret = 0;
a791daa1 2388 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2389 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2390
2391 if (host && !host->suspended)
2392 return 0;
2393
2394 if (host) {
a45c6cb8 2395 ret = clk_enable(host->iclk);
11dd62a7 2396 if (ret)
a45c6cb8 2397 goto clk_en_err;
a45c6cb8 2398
11dd62a7
DK		 2399 if (mmc_host_enable(host->mmc) != 0) {
2400 clk_disable(host->iclk);
2401 goto clk_en_err;
2402 }
2403
2bec0893
AH		 2404 if (host->got_dbclk)
2405 clk_enable(host->dbclk);
2406
70a3341a 2407 omap_hsmmc_conf_bus_power(host);
1b331e69 2408
a45c6cb8
MC		 2409 if (host->pdata->resume) {
2410 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2411 if (ret)
2412 dev_dbg(mmc_dev(host->mmc),
2413 "Unmask interrupt failed\n");
2414 }
2415
b62f6228
AH		 2416 omap_hsmmc_protect_card(host);
2417
a45c6cb8
MC		 2418 /* Notify the core to resume the host */
2419 ret = mmc_resume_host(host->mmc);
2420 if (ret == 0)
2421 host->suspended = 0;
70a3341a 2422
5e2ea617 2423 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 2424 }
2425
2426 return ret;
2427
2428clk_en_err:
2429 dev_dbg(mmc_dev(host->mmc),
2430 "Failed to enable MMC clocks during resume\n");
2431 return ret;
2432}
2433
2434#else
70a3341a
DK		 2435#define omap_hsmmc_suspend NULL
2436#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2437#endif
2438
a791daa1 2439static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2440 .suspend = omap_hsmmc_suspend,
2441 .resume = omap_hsmmc_resume,
a791daa1
KH		 2442};
2443
2444static struct platform_driver omap_hsmmc_driver = {
2445 .remove = omap_hsmmc_remove,
a45c6cb8
MC		 2446 .driver = {
2447 .name = DRIVER_NAME,
2448 .owner = THIS_MODULE,
a791daa1 2449 .pm = &omap_hsmmc_dev_pm_ops,
a45c6cb8
MC		 2450 },
2451};
2452
70a3341a 2453static int __init omap_hsmmc_init(void)
a45c6cb8
MC		 2454{
2455 /* Register the MMC driver */
8753298a 2456 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
a45c6cb8
MC		 2457}
2458
70a3341a 2459static void __exit omap_hsmmc_cleanup(void)
a45c6cb8
MC		 2460{
2461 /* Unregister MMC driver */
70a3341a 2462 platform_driver_unregister(&omap_hsmmc_driver);
a45c6cb8
MC		 2463}
2464
70a3341a
DK		 2465module_init(omap_hsmmc_init);
2466module_exit(omap_hsmmc_cleanup);
a45c6cb8
MC		 2467
2468MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2469MODULE_LICENSE("GPL");
2470MODULE_ALIAS("platform:" DRIVER_NAME);
2471MODULE_AUTHOR("Texas Instruments Inc");
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