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b8c86fc5 PO |
1 | /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface |
2 | * | |
3 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or (at | |
8 | * your option) any later version. | |
9 | * | |
10 | * Thanks to the following companies for their support: | |
11 | * | |
12 | * - JMicron (hardware and technical support) | |
13 | */ | |
14 | ||
15 | #include <linux/delay.h> | |
16 | #include <linux/highmem.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 19 | #include <linux/slab.h> |
ccc92c23 | 20 | #include <linux/device.h> |
b8c86fc5 PO |
21 | |
22 | #include <linux/mmc/host.h> | |
23 | ||
24 | #include <asm/scatterlist.h> | |
25 | #include <asm/io.h> | |
26 | ||
27 | #include "sdhci.h" | |
28 | ||
29 | /* | |
30 | * PCI registers | |
31 | */ | |
32 | ||
33 | #define PCI_SDHCI_IFPIO 0x00 | |
34 | #define PCI_SDHCI_IFDMA 0x01 | |
35 | #define PCI_SDHCI_IFVENDOR 0x02 | |
36 | ||
37 | #define PCI_SLOT_INFO 0x40 /* 8 bits */ | |
38 | #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) | |
39 | #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 | |
40 | ||
41 | #define MAX_SLOTS 8 | |
42 | ||
22606405 | 43 | struct sdhci_pci_chip; |
4489428a | 44 | struct sdhci_pci_slot; |
22606405 PO |
45 | |
46 | struct sdhci_pci_fixes { | |
47 | unsigned int quirks; | |
48 | ||
49 | int (*probe)(struct sdhci_pci_chip*); | |
45211e21 | 50 | |
4489428a | 51 | int (*probe_slot)(struct sdhci_pci_slot*); |
1e72859e | 52 | void (*remove_slot)(struct sdhci_pci_slot*, int); |
4489428a PO |
53 | |
54 | int (*suspend)(struct sdhci_pci_chip*, | |
55 | pm_message_t); | |
45211e21 | 56 | int (*resume)(struct sdhci_pci_chip*); |
22606405 PO |
57 | }; |
58 | ||
59 | struct sdhci_pci_slot { | |
60 | struct sdhci_pci_chip *chip; | |
61 | struct sdhci_host *host; | |
b8c86fc5 | 62 | |
22606405 PO |
63 | int pci_bar; |
64 | }; | |
65 | ||
66 | struct sdhci_pci_chip { | |
67 | struct pci_dev *pdev; | |
68 | ||
69 | unsigned int quirks; | |
70 | const struct sdhci_pci_fixes *fixes; | |
71 | ||
72 | int num_slots; /* Slots on controller */ | |
73 | struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */ | |
74 | }; | |
75 | ||
76 | ||
77 | /*****************************************************************************\ | |
78 | * * | |
79 | * Hardware specific quirk handling * | |
80 | * * | |
81 | \*****************************************************************************/ | |
82 | ||
83 | static int ricoh_probe(struct sdhci_pci_chip *chip) | |
84 | { | |
c99436fb CB |
85 | if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || |
86 | chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) | |
22606405 | 87 | chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; |
ccc92c23 ML |
88 | return 0; |
89 | } | |
90 | ||
91 | static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) | |
92 | { | |
93 | slot->host->caps = | |
94 | ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) | |
95 | & SDHCI_TIMEOUT_CLK_MASK) | | |
22606405 | 96 | |
ccc92c23 ML |
97 | ((0x21 << SDHCI_CLOCK_BASE_SHIFT) |
98 | & SDHCI_CLOCK_BASE_MASK) | | |
99 | ||
100 | SDHCI_TIMEOUT_CLK_UNIT | | |
101 | SDHCI_CAN_VDD_330 | | |
102 | SDHCI_CAN_DO_SDMA; | |
103 | return 0; | |
104 | } | |
105 | ||
106 | static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) | |
107 | { | |
108 | /* Apply a delay to allow controller to settle */ | |
109 | /* Otherwise it becomes confused if card state changed | |
110 | during suspend */ | |
111 | msleep(500); | |
22606405 PO |
112 | return 0; |
113 | } | |
114 | ||
115 | static const struct sdhci_pci_fixes sdhci_ricoh = { | |
116 | .probe = ricoh_probe, | |
84938294 VK |
117 | .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | |
118 | SDHCI_QUIRK_FORCE_DMA | | |
119 | SDHCI_QUIRK_CLOCK_BEFORE_RESET, | |
22606405 PO |
120 | }; |
121 | ||
ccc92c23 ML |
122 | static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { |
123 | .probe_slot = ricoh_mmc_probe_slot, | |
124 | .resume = ricoh_mmc_resume, | |
125 | .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | | |
126 | SDHCI_QUIRK_CLOCK_BEFORE_RESET | | |
127 | SDHCI_QUIRK_NO_CARD_NO_RESET | | |
128 | SDHCI_QUIRK_MISSING_CAPS | |
129 | }; | |
130 | ||
22606405 PO |
131 | static const struct sdhci_pci_fixes sdhci_ene_712 = { |
132 | .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | | |
133 | SDHCI_QUIRK_BROKEN_DMA, | |
134 | }; | |
135 | ||
136 | static const struct sdhci_pci_fixes sdhci_ene_714 = { | |
137 | .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | | |
138 | SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | | |
139 | SDHCI_QUIRK_BROKEN_DMA, | |
140 | }; | |
141 | ||
142 | static const struct sdhci_pci_fixes sdhci_cafe = { | |
143 | .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | | |
a0874897 | 144 | SDHCI_QUIRK_NO_BUSY_IRQ | |
ee53ab5d | 145 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, |
22606405 PO |
146 | }; |
147 | ||
f9ee3eab AC |
148 | /* |
149 | * ADMA operation is disabled for Moorestown platform due to | |
150 | * hardware bugs. | |
151 | */ | |
35ac6f08 | 152 | static int mrst_hc_probe(struct sdhci_pci_chip *chip) |
f9ee3eab AC |
153 | { |
154 | /* | |
35ac6f08 JP |
155 | * slots number is fixed here for MRST as SDIO3/5 are never used and |
156 | * have hardware bugs. | |
f9ee3eab AC |
157 | */ |
158 | chip->num_slots = 1; | |
159 | return 0; | |
160 | } | |
161 | ||
162 | static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { | |
163 | .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, | |
164 | }; | |
165 | ||
35ac6f08 | 166 | static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { |
f9ee3eab | 167 | .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, |
35ac6f08 | 168 | .probe = mrst_hc_probe, |
f9ee3eab AC |
169 | }; |
170 | ||
29229052 XS |
171 | static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { |
172 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
173 | }; | |
174 | ||
175 | static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc_sdio = { | |
176 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
177 | }; | |
178 | ||
26daa1ed JL |
179 | /* O2Micro extra registers */ |
180 | #define O2_SD_LOCK_WP 0xD3 | |
181 | #define O2_SD_MULTI_VCC3V 0xEE | |
182 | #define O2_SD_CLKREQ 0xEC | |
183 | #define O2_SD_CAPS 0xE0 | |
184 | #define O2_SD_ADMA1 0xE2 | |
185 | #define O2_SD_ADMA2 0xE7 | |
186 | #define O2_SD_INF_MOD 0xF1 | |
187 | ||
188 | static int o2_probe(struct sdhci_pci_chip *chip) | |
189 | { | |
190 | int ret; | |
191 | u8 scratch; | |
192 | ||
193 | switch (chip->pdev->device) { | |
194 | case PCI_DEVICE_ID_O2_8220: | |
195 | case PCI_DEVICE_ID_O2_8221: | |
196 | case PCI_DEVICE_ID_O2_8320: | |
197 | case PCI_DEVICE_ID_O2_8321: | |
198 | /* This extra setup is required due to broken ADMA. */ | |
199 | ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); | |
200 | if (ret) | |
201 | return ret; | |
202 | scratch &= 0x7f; | |
203 | pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); | |
204 | ||
205 | /* Set Multi 3 to VCC3V# */ | |
206 | pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08); | |
207 | ||
208 | /* Disable CLK_REQ# support after media DET */ | |
209 | ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch); | |
210 | if (ret) | |
211 | return ret; | |
212 | scratch |= 0x20; | |
213 | pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch); | |
214 | ||
215 | /* Choose capabilities, enable SDMA. We have to write 0x01 | |
216 | * to the capabilities register first to unlock it. | |
217 | */ | |
218 | ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch); | |
219 | if (ret) | |
220 | return ret; | |
221 | scratch |= 0x01; | |
222 | pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch); | |
223 | pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73); | |
224 | ||
225 | /* Disable ADMA1/2 */ | |
226 | pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39); | |
227 | pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08); | |
228 | ||
229 | /* Disable the infinite transfer mode */ | |
230 | ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch); | |
231 | if (ret) | |
232 | return ret; | |
233 | scratch |= 0x08; | |
234 | pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch); | |
235 | ||
236 | /* Lock WP */ | |
237 | ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); | |
238 | if (ret) | |
239 | return ret; | |
240 | scratch |= 0x80; | |
241 | pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); | |
242 | } | |
243 | ||
244 | return 0; | |
245 | } | |
246 | ||
45211e21 PO |
247 | static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) |
248 | { | |
249 | u8 scratch; | |
250 | int ret; | |
251 | ||
252 | ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); | |
253 | if (ret) | |
254 | return ret; | |
255 | ||
256 | /* | |
257 | * Turn PMOS on [bit 0], set over current detection to 2.4 V | |
258 | * [bit 1:2] and enable over current debouncing [bit 6]. | |
259 | */ | |
260 | if (on) | |
261 | scratch |= 0x47; | |
262 | else | |
263 | scratch &= ~0x47; | |
264 | ||
265 | ret = pci_write_config_byte(chip->pdev, 0xAE, scratch); | |
266 | if (ret) | |
267 | return ret; | |
268 | ||
269 | return 0; | |
270 | } | |
271 | ||
272 | static int jmicron_probe(struct sdhci_pci_chip *chip) | |
273 | { | |
274 | int ret; | |
8f230f45 | 275 | u16 mmcdev = 0; |
45211e21 | 276 | |
93fc48c7 PO |
277 | if (chip->pdev->revision == 0) { |
278 | chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | | |
279 | SDHCI_QUIRK_32BIT_DMA_SIZE | | |
2134a922 | 280 | SDHCI_QUIRK_32BIT_ADMA_SIZE | |
4a3cba32 | 281 | SDHCI_QUIRK_RESET_AFTER_REQUEST | |
86a6a874 | 282 | SDHCI_QUIRK_BROKEN_SMALL_PIO; |
93fc48c7 PO |
283 | } |
284 | ||
4489428a PO |
285 | /* |
286 | * JMicron chips can have two interfaces to the same hardware | |
287 | * in order to work around limitations in Microsoft's driver. | |
288 | * We need to make sure we only bind to one of them. | |
289 | * | |
290 | * This code assumes two things: | |
291 | * | |
292 | * 1. The PCI code adds subfunctions in order. | |
293 | * | |
294 | * 2. The MMC interface has a lower subfunction number | |
295 | * than the SD interface. | |
296 | */ | |
8f230f45 TI |
297 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) |
298 | mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; | |
299 | else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) | |
300 | mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; | |
301 | ||
302 | if (mmcdev) { | |
4489428a PO |
303 | struct pci_dev *sd_dev; |
304 | ||
305 | sd_dev = NULL; | |
306 | while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, | |
8f230f45 | 307 | mmcdev, sd_dev)) != NULL) { |
4489428a PO |
308 | if ((PCI_SLOT(chip->pdev->devfn) == |
309 | PCI_SLOT(sd_dev->devfn)) && | |
310 | (chip->pdev->bus == sd_dev->bus)) | |
311 | break; | |
312 | } | |
313 | ||
314 | if (sd_dev) { | |
315 | pci_dev_put(sd_dev); | |
316 | dev_info(&chip->pdev->dev, "Refusing to bind to " | |
317 | "secondary interface.\n"); | |
318 | return -ENODEV; | |
319 | } | |
320 | } | |
321 | ||
45211e21 PO |
322 | /* |
323 | * JMicron chips need a bit of a nudge to enable the power | |
324 | * output pins. | |
325 | */ | |
326 | ret = jmicron_pmos(chip, 1); | |
327 | if (ret) { | |
328 | dev_err(&chip->pdev->dev, "Failure enabling card power\n"); | |
329 | return ret; | |
330 | } | |
331 | ||
332 | return 0; | |
333 | } | |
334 | ||
4489428a PO |
335 | static void jmicron_enable_mmc(struct sdhci_host *host, int on) |
336 | { | |
337 | u8 scratch; | |
338 | ||
339 | scratch = readb(host->ioaddr + 0xC0); | |
340 | ||
341 | if (on) | |
342 | scratch |= 0x01; | |
343 | else | |
344 | scratch &= ~0x01; | |
345 | ||
346 | writeb(scratch, host->ioaddr + 0xC0); | |
347 | } | |
348 | ||
349 | static int jmicron_probe_slot(struct sdhci_pci_slot *slot) | |
350 | { | |
2134a922 PO |
351 | if (slot->chip->pdev->revision == 0) { |
352 | u16 version; | |
353 | ||
354 | version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); | |
355 | version = (version & SDHCI_VENDOR_VER_MASK) >> | |
356 | SDHCI_VENDOR_VER_SHIFT; | |
357 | ||
358 | /* | |
359 | * Older versions of the chip have lots of nasty glitches | |
360 | * in the ADMA engine. It's best just to avoid it | |
361 | * completely. | |
362 | */ | |
363 | if (version < 0xAC) | |
364 | slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; | |
365 | } | |
366 | ||
8f230f45 TI |
367 | /* JM388 MMC doesn't support 1.8V while SD supports it */ |
368 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
369 | slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | | |
370 | MMC_VDD_29_30 | MMC_VDD_30_31 | | |
371 | MMC_VDD_165_195; /* allow 1.8V */ | |
372 | slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | | |
373 | MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ | |
374 | } | |
375 | ||
4489428a PO |
376 | /* |
377 | * The secondary interface requires a bit set to get the | |
378 | * interrupts. | |
379 | */ | |
8f230f45 TI |
380 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
381 | slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
4489428a PO |
382 | jmicron_enable_mmc(slot->host, 1); |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
1e72859e | 387 | static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) |
4489428a | 388 | { |
1e72859e PO |
389 | if (dead) |
390 | return; | |
391 | ||
8f230f45 TI |
392 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
393 | slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
4489428a PO |
394 | jmicron_enable_mmc(slot->host, 0); |
395 | } | |
396 | ||
397 | static int jmicron_suspend(struct sdhci_pci_chip *chip, pm_message_t state) | |
398 | { | |
399 | int i; | |
400 | ||
8f230f45 TI |
401 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
402 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
4489428a PO |
403 | for (i = 0;i < chip->num_slots;i++) |
404 | jmicron_enable_mmc(chip->slots[i]->host, 0); | |
405 | } | |
406 | ||
407 | return 0; | |
408 | } | |
409 | ||
45211e21 PO |
410 | static int jmicron_resume(struct sdhci_pci_chip *chip) |
411 | { | |
4489428a PO |
412 | int ret, i; |
413 | ||
8f230f45 TI |
414 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
415 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
4489428a PO |
416 | for (i = 0;i < chip->num_slots;i++) |
417 | jmicron_enable_mmc(chip->slots[i]->host, 1); | |
418 | } | |
45211e21 PO |
419 | |
420 | ret = jmicron_pmos(chip, 1); | |
421 | if (ret) { | |
422 | dev_err(&chip->pdev->dev, "Failure enabling card power\n"); | |
423 | return ret; | |
424 | } | |
425 | ||
426 | return 0; | |
427 | } | |
428 | ||
26daa1ed JL |
429 | static const struct sdhci_pci_fixes sdhci_o2 = { |
430 | .probe = o2_probe, | |
431 | }; | |
432 | ||
22606405 | 433 | static const struct sdhci_pci_fixes sdhci_jmicron = { |
45211e21 PO |
434 | .probe = jmicron_probe, |
435 | ||
4489428a PO |
436 | .probe_slot = jmicron_probe_slot, |
437 | .remove_slot = jmicron_remove_slot, | |
438 | ||
439 | .suspend = jmicron_suspend, | |
45211e21 | 440 | .resume = jmicron_resume, |
22606405 PO |
441 | }; |
442 | ||
a7a6186c NP |
443 | /* SysKonnect CardBus2SDIO extra registers */ |
444 | #define SYSKT_CTRL 0x200 | |
445 | #define SYSKT_RDFIFO_STAT 0x204 | |
446 | #define SYSKT_WRFIFO_STAT 0x208 | |
447 | #define SYSKT_POWER_DATA 0x20c | |
448 | #define SYSKT_POWER_330 0xef | |
449 | #define SYSKT_POWER_300 0xf8 | |
450 | #define SYSKT_POWER_184 0xcc | |
451 | #define SYSKT_POWER_CMD 0x20d | |
452 | #define SYSKT_POWER_START (1 << 7) | |
453 | #define SYSKT_POWER_STATUS 0x20e | |
454 | #define SYSKT_POWER_STATUS_OK (1 << 0) | |
455 | #define SYSKT_BOARD_REV 0x210 | |
456 | #define SYSKT_CHIP_REV 0x211 | |
457 | #define SYSKT_CONF_DATA 0x212 | |
458 | #define SYSKT_CONF_DATA_1V8 (1 << 2) | |
459 | #define SYSKT_CONF_DATA_2V5 (1 << 1) | |
460 | #define SYSKT_CONF_DATA_3V3 (1 << 0) | |
461 | ||
462 | static int syskt_probe(struct sdhci_pci_chip *chip) | |
463 | { | |
464 | if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { | |
465 | chip->pdev->class &= ~0x0000FF; | |
466 | chip->pdev->class |= PCI_SDHCI_IFDMA; | |
467 | } | |
468 | return 0; | |
469 | } | |
470 | ||
471 | static int syskt_probe_slot(struct sdhci_pci_slot *slot) | |
472 | { | |
473 | int tm, ps; | |
474 | ||
475 | u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); | |
476 | u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); | |
477 | dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " | |
478 | "board rev %d.%d, chip rev %d.%d\n", | |
479 | board_rev >> 4, board_rev & 0xf, | |
480 | chip_rev >> 4, chip_rev & 0xf); | |
481 | if (chip_rev >= 0x20) | |
482 | slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; | |
483 | ||
484 | writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); | |
485 | writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); | |
486 | udelay(50); | |
487 | tm = 10; /* Wait max 1 ms */ | |
488 | do { | |
489 | ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); | |
490 | if (ps & SYSKT_POWER_STATUS_OK) | |
491 | break; | |
492 | udelay(100); | |
493 | } while (--tm); | |
494 | if (!tm) { | |
495 | dev_err(&slot->chip->pdev->dev, | |
496 | "power regulator never stabilized"); | |
497 | writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); | |
498 | return -ENODEV; | |
499 | } | |
500 | ||
501 | return 0; | |
502 | } | |
503 | ||
504 | static const struct sdhci_pci_fixes sdhci_syskt = { | |
505 | .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, | |
506 | .probe = syskt_probe, | |
507 | .probe_slot = syskt_probe_slot, | |
508 | }; | |
509 | ||
557b0697 HW |
510 | static int via_probe(struct sdhci_pci_chip *chip) |
511 | { | |
512 | if (chip->pdev->revision == 0x10) | |
513 | chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; | |
514 | ||
515 | return 0; | |
516 | } | |
517 | ||
518 | static const struct sdhci_pci_fixes sdhci_via = { | |
519 | .probe = via_probe, | |
520 | }; | |
521 | ||
22606405 | 522 | static const struct pci_device_id pci_ids[] __devinitdata = { |
b8c86fc5 PO |
523 | { |
524 | .vendor = PCI_VENDOR_ID_RICOH, | |
525 | .device = PCI_DEVICE_ID_RICOH_R5C822, | |
22606405 | 526 | .subvendor = PCI_ANY_ID, |
b8c86fc5 | 527 | .subdevice = PCI_ANY_ID, |
22606405 | 528 | .driver_data = (kernel_ulong_t)&sdhci_ricoh, |
b8c86fc5 PO |
529 | }, |
530 | ||
ccc92c23 ML |
531 | { |
532 | .vendor = PCI_VENDOR_ID_RICOH, | |
533 | .device = 0x843, | |
534 | .subvendor = PCI_ANY_ID, | |
535 | .subdevice = PCI_ANY_ID, | |
536 | .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, | |
537 | }, | |
538 | ||
568133eb PC |
539 | { |
540 | .vendor = PCI_VENDOR_ID_RICOH, | |
541 | .device = 0xe822, | |
542 | .subvendor = PCI_ANY_ID, | |
543 | .subdevice = PCI_ANY_ID, | |
544 | .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, | |
545 | }, | |
546 | ||
b8c86fc5 PO |
547 | { |
548 | .vendor = PCI_VENDOR_ID_ENE, | |
549 | .device = PCI_DEVICE_ID_ENE_CB712_SD, | |
550 | .subvendor = PCI_ANY_ID, | |
551 | .subdevice = PCI_ANY_ID, | |
22606405 | 552 | .driver_data = (kernel_ulong_t)&sdhci_ene_712, |
b8c86fc5 PO |
553 | }, |
554 | ||
555 | { | |
556 | .vendor = PCI_VENDOR_ID_ENE, | |
557 | .device = PCI_DEVICE_ID_ENE_CB712_SD_2, | |
558 | .subvendor = PCI_ANY_ID, | |
559 | .subdevice = PCI_ANY_ID, | |
22606405 | 560 | .driver_data = (kernel_ulong_t)&sdhci_ene_712, |
b8c86fc5 PO |
561 | }, |
562 | ||
563 | { | |
564 | .vendor = PCI_VENDOR_ID_ENE, | |
565 | .device = PCI_DEVICE_ID_ENE_CB714_SD, | |
566 | .subvendor = PCI_ANY_ID, | |
567 | .subdevice = PCI_ANY_ID, | |
22606405 | 568 | .driver_data = (kernel_ulong_t)&sdhci_ene_714, |
b8c86fc5 PO |
569 | }, |
570 | ||
571 | { | |
572 | .vendor = PCI_VENDOR_ID_ENE, | |
573 | .device = PCI_DEVICE_ID_ENE_CB714_SD_2, | |
574 | .subvendor = PCI_ANY_ID, | |
575 | .subdevice = PCI_ANY_ID, | |
22606405 | 576 | .driver_data = (kernel_ulong_t)&sdhci_ene_714, |
b8c86fc5 PO |
577 | }, |
578 | ||
579 | { | |
580 | .vendor = PCI_VENDOR_ID_MARVELL, | |
8c5eb880 | 581 | .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, |
b8c86fc5 PO |
582 | .subvendor = PCI_ANY_ID, |
583 | .subdevice = PCI_ANY_ID, | |
22606405 | 584 | .driver_data = (kernel_ulong_t)&sdhci_cafe, |
b8c86fc5 PO |
585 | }, |
586 | ||
587 | { | |
588 | .vendor = PCI_VENDOR_ID_JMICRON, | |
589 | .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, | |
590 | .subvendor = PCI_ANY_ID, | |
591 | .subdevice = PCI_ANY_ID, | |
22606405 | 592 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, |
b8c86fc5 PO |
593 | }, |
594 | ||
4489428a PO |
595 | { |
596 | .vendor = PCI_VENDOR_ID_JMICRON, | |
597 | .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, | |
598 | .subvendor = PCI_ANY_ID, | |
599 | .subdevice = PCI_ANY_ID, | |
600 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, | |
8f230f45 TI |
601 | }, |
602 | ||
603 | { | |
604 | .vendor = PCI_VENDOR_ID_JMICRON, | |
605 | .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, | |
606 | .subvendor = PCI_ANY_ID, | |
607 | .subdevice = PCI_ANY_ID, | |
608 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, | |
609 | }, | |
610 | ||
611 | { | |
612 | .vendor = PCI_VENDOR_ID_JMICRON, | |
613 | .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, | |
614 | .subvendor = PCI_ANY_ID, | |
615 | .subdevice = PCI_ANY_ID, | |
616 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, | |
4489428a PO |
617 | }, |
618 | ||
a7a6186c NP |
619 | { |
620 | .vendor = PCI_VENDOR_ID_SYSKONNECT, | |
621 | .device = 0x8000, | |
622 | .subvendor = PCI_ANY_ID, | |
623 | .subdevice = PCI_ANY_ID, | |
624 | .driver_data = (kernel_ulong_t)&sdhci_syskt, | |
625 | }, | |
626 | ||
557b0697 HW |
627 | { |
628 | .vendor = PCI_VENDOR_ID_VIA, | |
629 | .device = 0x95d0, | |
630 | .subvendor = PCI_ANY_ID, | |
631 | .subdevice = PCI_ANY_ID, | |
632 | .driver_data = (kernel_ulong_t)&sdhci_via, | |
633 | }, | |
634 | ||
29229052 XS |
635 | { |
636 | .vendor = PCI_VENDOR_ID_INTEL, | |
f9ee3eab AC |
637 | .device = PCI_DEVICE_ID_INTEL_MRST_SD0, |
638 | .subvendor = PCI_ANY_ID, | |
639 | .subdevice = PCI_ANY_ID, | |
640 | .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, | |
641 | }, | |
642 | ||
643 | { | |
644 | .vendor = PCI_VENDOR_ID_INTEL, | |
645 | .device = PCI_DEVICE_ID_INTEL_MRST_SD1, | |
646 | .subvendor = PCI_ANY_ID, | |
647 | .subdevice = PCI_ANY_ID, | |
35ac6f08 JP |
648 | .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, |
649 | }, | |
650 | ||
651 | { | |
652 | .vendor = PCI_VENDOR_ID_INTEL, | |
653 | .device = PCI_DEVICE_ID_INTEL_MRST_SD2, | |
654 | .subvendor = PCI_ANY_ID, | |
655 | .subdevice = PCI_ANY_ID, | |
656 | .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, | |
f9ee3eab AC |
657 | }, |
658 | ||
659 | { | |
660 | .vendor = PCI_VENDOR_ID_INTEL, | |
29229052 XS |
661 | .device = PCI_DEVICE_ID_INTEL_MFD_SD, |
662 | .subvendor = PCI_ANY_ID, | |
663 | .subdevice = PCI_ANY_ID, | |
664 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, | |
665 | }, | |
666 | ||
667 | { | |
668 | .vendor = PCI_VENDOR_ID_INTEL, | |
669 | .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, | |
670 | .subvendor = PCI_ANY_ID, | |
671 | .subdevice = PCI_ANY_ID, | |
672 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio, | |
673 | }, | |
674 | ||
675 | { | |
676 | .vendor = PCI_VENDOR_ID_INTEL, | |
677 | .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, | |
678 | .subvendor = PCI_ANY_ID, | |
679 | .subdevice = PCI_ANY_ID, | |
680 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio, | |
681 | }, | |
682 | ||
683 | { | |
684 | .vendor = PCI_VENDOR_ID_INTEL, | |
685 | .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, | |
686 | .subvendor = PCI_ANY_ID, | |
687 | .subdevice = PCI_ANY_ID, | |
688 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio, | |
689 | }, | |
690 | ||
691 | { | |
692 | .vendor = PCI_VENDOR_ID_INTEL, | |
693 | .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, | |
694 | .subvendor = PCI_ANY_ID, | |
695 | .subdevice = PCI_ANY_ID, | |
696 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio, | |
697 | }, | |
698 | ||
26daa1ed JL |
699 | { |
700 | .vendor = PCI_VENDOR_ID_O2, | |
701 | .device = PCI_DEVICE_ID_O2_8120, | |
702 | .subvendor = PCI_ANY_ID, | |
703 | .subdevice = PCI_ANY_ID, | |
704 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
705 | }, | |
706 | ||
707 | { | |
708 | .vendor = PCI_VENDOR_ID_O2, | |
709 | .device = PCI_DEVICE_ID_O2_8220, | |
710 | .subvendor = PCI_ANY_ID, | |
711 | .subdevice = PCI_ANY_ID, | |
712 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
713 | }, | |
714 | ||
715 | { | |
716 | .vendor = PCI_VENDOR_ID_O2, | |
717 | .device = PCI_DEVICE_ID_O2_8221, | |
718 | .subvendor = PCI_ANY_ID, | |
719 | .subdevice = PCI_ANY_ID, | |
720 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
721 | }, | |
722 | ||
723 | { | |
724 | .vendor = PCI_VENDOR_ID_O2, | |
725 | .device = PCI_DEVICE_ID_O2_8320, | |
726 | .subvendor = PCI_ANY_ID, | |
727 | .subdevice = PCI_ANY_ID, | |
728 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
729 | }, | |
730 | ||
731 | { | |
732 | .vendor = PCI_VENDOR_ID_O2, | |
733 | .device = PCI_DEVICE_ID_O2_8321, | |
734 | .subvendor = PCI_ANY_ID, | |
735 | .subdevice = PCI_ANY_ID, | |
736 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
737 | }, | |
738 | ||
b8c86fc5 PO |
739 | { /* Generic SD host controller */ |
740 | PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) | |
741 | }, | |
742 | ||
743 | { /* end: all zeroes */ }, | |
744 | }; | |
745 | ||
746 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
747 | ||
b8c86fc5 PO |
748 | /*****************************************************************************\ |
749 | * * | |
750 | * SDHCI core callbacks * | |
751 | * * | |
752 | \*****************************************************************************/ | |
753 | ||
754 | static int sdhci_pci_enable_dma(struct sdhci_host *host) | |
755 | { | |
756 | struct sdhci_pci_slot *slot; | |
757 | struct pci_dev *pdev; | |
758 | int ret; | |
759 | ||
760 | slot = sdhci_priv(host); | |
761 | pdev = slot->chip->pdev; | |
762 | ||
763 | if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && | |
764 | ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && | |
a13abc7b | 765 | (host->flags & SDHCI_USE_SDMA)) { |
b8c86fc5 PO |
766 | dev_warn(&pdev->dev, "Will use DMA mode even though HW " |
767 | "doesn't fully claim to support it.\n"); | |
768 | } | |
769 | ||
284901a9 | 770 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
b8c86fc5 PO |
771 | if (ret) |
772 | return ret; | |
773 | ||
774 | pci_set_master(pdev); | |
775 | ||
776 | return 0; | |
777 | } | |
778 | ||
779 | static struct sdhci_ops sdhci_pci_ops = { | |
780 | .enable_dma = sdhci_pci_enable_dma, | |
781 | }; | |
782 | ||
783 | /*****************************************************************************\ | |
784 | * * | |
785 | * Suspend/resume * | |
786 | * * | |
787 | \*****************************************************************************/ | |
788 | ||
789 | #ifdef CONFIG_PM | |
790 | ||
791 | static int sdhci_pci_suspend (struct pci_dev *pdev, pm_message_t state) | |
792 | { | |
793 | struct sdhci_pci_chip *chip; | |
794 | struct sdhci_pci_slot *slot; | |
5f619704 | 795 | mmc_pm_flag_t slot_pm_flags; |
2f4cbb3d | 796 | mmc_pm_flag_t pm_flags = 0; |
b8c86fc5 PO |
797 | int i, ret; |
798 | ||
799 | chip = pci_get_drvdata(pdev); | |
800 | if (!chip) | |
801 | return 0; | |
802 | ||
803 | for (i = 0;i < chip->num_slots;i++) { | |
804 | slot = chip->slots[i]; | |
805 | if (!slot) | |
806 | continue; | |
807 | ||
808 | ret = sdhci_suspend_host(slot->host, state); | |
809 | ||
810 | if (ret) { | |
811 | for (i--;i >= 0;i--) | |
812 | sdhci_resume_host(chip->slots[i]->host); | |
813 | return ret; | |
814 | } | |
2f4cbb3d | 815 | |
5f619704 DD |
816 | slot_pm_flags = slot->host->mmc->pm_flags; |
817 | if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) | |
818 | sdhci_enable_irq_wakeups(slot->host); | |
819 | ||
820 | pm_flags |= slot_pm_flags; | |
b8c86fc5 PO |
821 | } |
822 | ||
4489428a PO |
823 | if (chip->fixes && chip->fixes->suspend) { |
824 | ret = chip->fixes->suspend(chip, state); | |
825 | if (ret) { | |
826 | for (i = chip->num_slots - 1;i >= 0;i--) | |
827 | sdhci_resume_host(chip->slots[i]->host); | |
828 | return ret; | |
829 | } | |
830 | } | |
831 | ||
b8c86fc5 | 832 | pci_save_state(pdev); |
2f4cbb3d | 833 | if (pm_flags & MMC_PM_KEEP_POWER) { |
5f619704 DD |
834 | if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) { |
835 | pci_pme_active(pdev, true); | |
2f4cbb3d | 836 | pci_enable_wake(pdev, PCI_D3hot, 1); |
5f619704 | 837 | } |
2f4cbb3d NP |
838 | pci_set_power_state(pdev, PCI_D3hot); |
839 | } else { | |
840 | pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); | |
841 | pci_disable_device(pdev); | |
842 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
843 | } | |
b8c86fc5 PO |
844 | |
845 | return 0; | |
846 | } | |
847 | ||
848 | static int sdhci_pci_resume (struct pci_dev *pdev) | |
849 | { | |
850 | struct sdhci_pci_chip *chip; | |
851 | struct sdhci_pci_slot *slot; | |
852 | int i, ret; | |
853 | ||
854 | chip = pci_get_drvdata(pdev); | |
855 | if (!chip) | |
856 | return 0; | |
857 | ||
858 | pci_set_power_state(pdev, PCI_D0); | |
859 | pci_restore_state(pdev); | |
860 | ret = pci_enable_device(pdev); | |
861 | if (ret) | |
862 | return ret; | |
863 | ||
45211e21 PO |
864 | if (chip->fixes && chip->fixes->resume) { |
865 | ret = chip->fixes->resume(chip); | |
866 | if (ret) | |
867 | return ret; | |
868 | } | |
869 | ||
b8c86fc5 PO |
870 | for (i = 0;i < chip->num_slots;i++) { |
871 | slot = chip->slots[i]; | |
872 | if (!slot) | |
873 | continue; | |
874 | ||
875 | ret = sdhci_resume_host(slot->host); | |
876 | if (ret) | |
877 | return ret; | |
878 | } | |
879 | ||
880 | return 0; | |
881 | } | |
882 | ||
883 | #else /* CONFIG_PM */ | |
884 | ||
885 | #define sdhci_pci_suspend NULL | |
886 | #define sdhci_pci_resume NULL | |
887 | ||
888 | #endif /* CONFIG_PM */ | |
889 | ||
890 | /*****************************************************************************\ | |
891 | * * | |
892 | * Device probing/removal * | |
893 | * * | |
894 | \*****************************************************************************/ | |
895 | ||
896 | static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot( | |
897 | struct pci_dev *pdev, struct sdhci_pci_chip *chip, int bar) | |
898 | { | |
899 | struct sdhci_pci_slot *slot; | |
900 | struct sdhci_host *host; | |
901 | ||
902 | resource_size_t addr; | |
903 | ||
904 | int ret; | |
905 | ||
906 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
907 | dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); | |
908 | return ERR_PTR(-ENODEV); | |
909 | } | |
910 | ||
911 | if (pci_resource_len(pdev, bar) != 0x100) { | |
912 | dev_err(&pdev->dev, "Invalid iomem size. You may " | |
913 | "experience problems.\n"); | |
914 | } | |
915 | ||
916 | if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { | |
917 | dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); | |
918 | return ERR_PTR(-ENODEV); | |
919 | } | |
920 | ||
921 | if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { | |
922 | dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); | |
923 | return ERR_PTR(-ENODEV); | |
924 | } | |
925 | ||
926 | host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); | |
927 | if (IS_ERR(host)) { | |
c60a32cd | 928 | dev_err(&pdev->dev, "cannot allocate host\n"); |
dc0fd7b5 | 929 | return ERR_CAST(host); |
b8c86fc5 PO |
930 | } |
931 | ||
932 | slot = sdhci_priv(host); | |
933 | ||
934 | slot->chip = chip; | |
935 | slot->host = host; | |
936 | slot->pci_bar = bar; | |
937 | ||
938 | host->hw_name = "PCI"; | |
939 | host->ops = &sdhci_pci_ops; | |
940 | host->quirks = chip->quirks; | |
941 | ||
942 | host->irq = pdev->irq; | |
943 | ||
944 | ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc)); | |
945 | if (ret) { | |
946 | dev_err(&pdev->dev, "cannot request region\n"); | |
c60a32cd | 947 | goto free; |
b8c86fc5 PO |
948 | } |
949 | ||
950 | addr = pci_resource_start(pdev, bar); | |
092f82ed | 951 | host->ioaddr = pci_ioremap_bar(pdev, bar); |
b8c86fc5 PO |
952 | if (!host->ioaddr) { |
953 | dev_err(&pdev->dev, "failed to remap registers\n"); | |
954 | goto release; | |
955 | } | |
956 | ||
4489428a PO |
957 | if (chip->fixes && chip->fixes->probe_slot) { |
958 | ret = chip->fixes->probe_slot(slot); | |
959 | if (ret) | |
960 | goto unmap; | |
961 | } | |
962 | ||
2f4cbb3d NP |
963 | host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; |
964 | ||
b8c86fc5 PO |
965 | ret = sdhci_add_host(host); |
966 | if (ret) | |
4489428a | 967 | goto remove; |
b8c86fc5 PO |
968 | |
969 | return slot; | |
970 | ||
4489428a PO |
971 | remove: |
972 | if (chip->fixes && chip->fixes->remove_slot) | |
1e72859e | 973 | chip->fixes->remove_slot(slot, 0); |
4489428a | 974 | |
b8c86fc5 PO |
975 | unmap: |
976 | iounmap(host->ioaddr); | |
977 | ||
978 | release: | |
979 | pci_release_region(pdev, bar); | |
c60a32cd DC |
980 | |
981 | free: | |
b8c86fc5 PO |
982 | sdhci_free_host(host); |
983 | ||
984 | return ERR_PTR(ret); | |
985 | } | |
986 | ||
987 | static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) | |
988 | { | |
1e72859e PO |
989 | int dead; |
990 | u32 scratch; | |
991 | ||
992 | dead = 0; | |
993 | scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); | |
994 | if (scratch == (u32)-1) | |
995 | dead = 1; | |
996 | ||
997 | sdhci_remove_host(slot->host, dead); | |
4489428a PO |
998 | |
999 | if (slot->chip->fixes && slot->chip->fixes->remove_slot) | |
1e72859e | 1000 | slot->chip->fixes->remove_slot(slot, dead); |
4489428a | 1001 | |
b8c86fc5 | 1002 | pci_release_region(slot->chip->pdev, slot->pci_bar); |
4489428a | 1003 | |
b8c86fc5 PO |
1004 | sdhci_free_host(slot->host); |
1005 | } | |
1006 | ||
1007 | static int __devinit sdhci_pci_probe(struct pci_dev *pdev, | |
1008 | const struct pci_device_id *ent) | |
1009 | { | |
1010 | struct sdhci_pci_chip *chip; | |
1011 | struct sdhci_pci_slot *slot; | |
1012 | ||
1013 | u8 slots, rev, first_bar; | |
1014 | int ret, i; | |
1015 | ||
1016 | BUG_ON(pdev == NULL); | |
1017 | BUG_ON(ent == NULL); | |
1018 | ||
1019 | pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev); | |
1020 | ||
1021 | dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", | |
1022 | (int)pdev->vendor, (int)pdev->device, (int)rev); | |
1023 | ||
1024 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); | |
1025 | if (ret) | |
1026 | return ret; | |
1027 | ||
1028 | slots = PCI_SLOT_INFO_SLOTS(slots) + 1; | |
1029 | dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); | |
1030 | if (slots == 0) | |
1031 | return -ENODEV; | |
1032 | ||
1033 | BUG_ON(slots > MAX_SLOTS); | |
1034 | ||
1035 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); | |
1036 | if (ret) | |
1037 | return ret; | |
1038 | ||
1039 | first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; | |
1040 | ||
1041 | if (first_bar > 5) { | |
1042 | dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); | |
1043 | return -ENODEV; | |
1044 | } | |
1045 | ||
1046 | ret = pci_enable_device(pdev); | |
1047 | if (ret) | |
1048 | return ret; | |
1049 | ||
1050 | chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL); | |
1051 | if (!chip) { | |
1052 | ret = -ENOMEM; | |
1053 | goto err; | |
1054 | } | |
1055 | ||
1056 | chip->pdev = pdev; | |
22606405 PO |
1057 | chip->fixes = (const struct sdhci_pci_fixes*)ent->driver_data; |
1058 | if (chip->fixes) | |
1059 | chip->quirks = chip->fixes->quirks; | |
b8c86fc5 PO |
1060 | chip->num_slots = slots; |
1061 | ||
1062 | pci_set_drvdata(pdev, chip); | |
1063 | ||
22606405 PO |
1064 | if (chip->fixes && chip->fixes->probe) { |
1065 | ret = chip->fixes->probe(chip); | |
1066 | if (ret) | |
1067 | goto free; | |
1068 | } | |
1069 | ||
225d85fe AC |
1070 | slots = chip->num_slots; /* Quirk may have changed this */ |
1071 | ||
b8c86fc5 PO |
1072 | for (i = 0;i < slots;i++) { |
1073 | slot = sdhci_pci_probe_slot(pdev, chip, first_bar + i); | |
1074 | if (IS_ERR(slot)) { | |
1075 | for (i--;i >= 0;i--) | |
1076 | sdhci_pci_remove_slot(chip->slots[i]); | |
1077 | ret = PTR_ERR(slot); | |
1078 | goto free; | |
1079 | } | |
1080 | ||
1081 | chip->slots[i] = slot; | |
1082 | } | |
1083 | ||
1084 | return 0; | |
1085 | ||
1086 | free: | |
1087 | pci_set_drvdata(pdev, NULL); | |
1088 | kfree(chip); | |
1089 | ||
1090 | err: | |
1091 | pci_disable_device(pdev); | |
1092 | return ret; | |
1093 | } | |
1094 | ||
1095 | static void __devexit sdhci_pci_remove(struct pci_dev *pdev) | |
1096 | { | |
1097 | int i; | |
1098 | struct sdhci_pci_chip *chip; | |
1099 | ||
1100 | chip = pci_get_drvdata(pdev); | |
1101 | ||
1102 | if (chip) { | |
1103 | for (i = 0;i < chip->num_slots; i++) | |
1104 | sdhci_pci_remove_slot(chip->slots[i]); | |
1105 | ||
1106 | pci_set_drvdata(pdev, NULL); | |
1107 | kfree(chip); | |
1108 | } | |
1109 | ||
1110 | pci_disable_device(pdev); | |
1111 | } | |
1112 | ||
1113 | static struct pci_driver sdhci_driver = { | |
1114 | .name = "sdhci-pci", | |
1115 | .id_table = pci_ids, | |
1116 | .probe = sdhci_pci_probe, | |
1117 | .remove = __devexit_p(sdhci_pci_remove), | |
1118 | .suspend = sdhci_pci_suspend, | |
1119 | .resume = sdhci_pci_resume, | |
1120 | }; | |
1121 | ||
1122 | /*****************************************************************************\ | |
1123 | * * | |
1124 | * Driver init/exit * | |
1125 | * * | |
1126 | \*****************************************************************************/ | |
1127 | ||
1128 | static int __init sdhci_drv_init(void) | |
1129 | { | |
1130 | return pci_register_driver(&sdhci_driver); | |
1131 | } | |
1132 | ||
1133 | static void __exit sdhci_drv_exit(void) | |
1134 | { | |
1135 | pci_unregister_driver(&sdhci_driver); | |
1136 | } | |
1137 | ||
1138 | module_init(sdhci_drv_init); | |
1139 | module_exit(sdhci_drv_exit); | |
1140 | ||
32710e8f | 1141 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
b8c86fc5 PO |
1142 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); |
1143 | MODULE_LICENSE("GPL"); |