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0d1bb41a BD |
1 | /* linux/drivers/mmc/host/sdhci-s3c.c |
2 | * | |
3 | * Copyright 2008 Openmoko Inc. | |
4 | * Copyright 2008 Simtec Electronics | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * http://armlinux.simtec.co.uk/ | |
7 | * | |
8 | * SDHCI (HSMMC) support for Samsung SoC | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
017210d1 | 15 | #include <linux/spinlock.h> |
0d1bb41a BD |
16 | #include <linux/delay.h> |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/platform_device.h> | |
cc014f3e | 19 | #include <linux/platform_data/mmc-sdhci-s3c.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
0d1bb41a BD |
21 | #include <linux/clk.h> |
22 | #include <linux/io.h> | |
17866e14 | 23 | #include <linux/gpio.h> |
55156d24 | 24 | #include <linux/module.h> |
d5e9c02c MB |
25 | #include <linux/of.h> |
26 | #include <linux/of_gpio.h> | |
27 | #include <linux/pm.h> | |
9f4e8151 | 28 | #include <linux/pm_runtime.h> |
0d1bb41a BD |
29 | |
30 | #include <linux/mmc/host.h> | |
31 | ||
cc014f3e | 32 | #include "sdhci-s3c-regs.h" |
0d1bb41a BD |
33 | #include "sdhci.h" |
34 | ||
35 | #define MAX_BUS_CLK (4) | |
36 | ||
37 | /** | |
38 | * struct sdhci_s3c - S3C SDHCI instance | |
39 | * @host: The SDHCI host created | |
40 | * @pdev: The platform device we where created from. | |
41 | * @ioarea: The resource created when we claimed the IO area. | |
42 | * @pdata: The platform data for this controller. | |
43 | * @cur_clk: The index of the current bus clock. | |
44 | * @clk_io: The clock for the internal bus interface. | |
45 | * @clk_bus: The clocks that are available for the SD/MMC bus clock. | |
46 | */ | |
47 | struct sdhci_s3c { | |
48 | struct sdhci_host *host; | |
49 | struct platform_device *pdev; | |
50 | struct resource *ioarea; | |
51 | struct s3c_sdhci_platdata *pdata; | |
3ac147fa | 52 | int cur_clk; |
17866e14 MS |
53 | int ext_cd_irq; |
54 | int ext_cd_gpio; | |
0d1bb41a BD |
55 | |
56 | struct clk *clk_io; | |
57 | struct clk *clk_bus[MAX_BUS_CLK]; | |
6eb28bdc | 58 | unsigned long clk_rates[MAX_BUS_CLK]; |
1771059c RK |
59 | |
60 | bool no_divider; | |
0d1bb41a BD |
61 | }; |
62 | ||
3119936a TA |
63 | /** |
64 | * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data | |
65 | * @sdhci_quirks: sdhci host specific quirks. | |
66 | * | |
67 | * Specifies platform specific configuration of sdhci controller. | |
68 | * Note: A structure for driver specific platform data is used for future | |
69 | * expansion of its usage. | |
70 | */ | |
71 | struct sdhci_s3c_drv_data { | |
72 | unsigned int sdhci_quirks; | |
1771059c | 73 | bool no_divider; |
3119936a TA |
74 | }; |
75 | ||
0d1bb41a BD |
76 | static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host) |
77 | { | |
78 | return sdhci_priv(host); | |
79 | } | |
80 | ||
0d1bb41a BD |
81 | /** |
82 | * sdhci_s3c_get_max_clk - callback to get maximum clock frequency. | |
83 | * @host: The SDHCI host instance. | |
84 | * | |
85 | * Callback to return the maximum clock rate acheivable by the controller. | |
86 | */ | |
87 | static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host) | |
88 | { | |
89 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 TF |
90 | unsigned long rate, max = 0; |
91 | int src; | |
0d1bb41a | 92 | |
222a13c5 TF |
93 | for (src = 0; src < MAX_BUS_CLK; src++) { |
94 | rate = ourhost->clk_rates[src]; | |
0d1bb41a BD |
95 | if (rate > max) |
96 | max = rate; | |
97 | } | |
98 | ||
99 | return max; | |
100 | } | |
101 | ||
0d1bb41a BD |
102 | /** |
103 | * sdhci_s3c_consider_clock - consider one the bus clocks for current setting | |
104 | * @ourhost: Our SDHCI instance. | |
105 | * @src: The source clock index. | |
106 | * @wanted: The clock frequency wanted. | |
107 | */ | |
108 | static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost, | |
109 | unsigned int src, | |
110 | unsigned int wanted) | |
111 | { | |
112 | unsigned long rate; | |
113 | struct clk *clksrc = ourhost->clk_bus[src]; | |
8880a4a5 | 114 | int shift; |
0d1bb41a | 115 | |
8f4b78d9 | 116 | if (IS_ERR(clksrc)) |
0d1bb41a BD |
117 | return UINT_MAX; |
118 | ||
253e0a7c | 119 | /* |
3119936a TA |
120 | * If controller uses a non-standard clock division, find the best clock |
121 | * speed possible with selected clock source and skip the division. | |
253e0a7c | 122 | */ |
1771059c | 123 | if (ourhost->no_divider) { |
253e0a7c JS |
124 | rate = clk_round_rate(clksrc, wanted); |
125 | return wanted - rate; | |
126 | } | |
127 | ||
6eb28bdc | 128 | rate = ourhost->clk_rates[src]; |
0d1bb41a | 129 | |
22003000 | 130 | for (shift = 0; shift <= 8; ++shift) { |
8880a4a5 | 131 | if ((rate >> shift) <= wanted) |
0d1bb41a BD |
132 | break; |
133 | } | |
22003000 TF |
134 | |
135 | if (shift > 8) { | |
136 | dev_dbg(&ourhost->pdev->dev, | |
137 | "clk %d: rate %ld, min rate %lu > wanted %u\n", | |
138 | src, rate, rate / 256, wanted); | |
139 | return UINT_MAX; | |
140 | } | |
0d1bb41a BD |
141 | |
142 | dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n", | |
8880a4a5 | 143 | src, rate, wanted, rate >> shift); |
0d1bb41a | 144 | |
8880a4a5 | 145 | return wanted - (rate >> shift); |
0d1bb41a BD |
146 | } |
147 | ||
148 | /** | |
149 | * sdhci_s3c_set_clock - callback on clock change | |
150 | * @host: The SDHCI host being changed | |
151 | * @clock: The clock rate being requested. | |
152 | * | |
153 | * When the card's clock is going to be changed, look at the new frequency | |
154 | * and find the best clock source to go with it. | |
155 | */ | |
156 | static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock) | |
157 | { | |
158 | struct sdhci_s3c *ourhost = to_s3c(host); | |
159 | unsigned int best = UINT_MAX; | |
160 | unsigned int delta; | |
161 | int best_src = 0; | |
162 | int src; | |
163 | u32 ctrl; | |
164 | ||
1650d0c7 RK |
165 | host->mmc->actual_clock = 0; |
166 | ||
0d1bb41a | 167 | /* don't bother if the clock is going off. */ |
1771059c RK |
168 | if (clock == 0) { |
169 | sdhci_set_clock(host, clock); | |
0d1bb41a | 170 | return; |
1771059c | 171 | } |
0d1bb41a BD |
172 | |
173 | for (src = 0; src < MAX_BUS_CLK; src++) { | |
174 | delta = sdhci_s3c_consider_clock(ourhost, src, clock); | |
175 | if (delta < best) { | |
176 | best = delta; | |
177 | best_src = src; | |
178 | } | |
179 | } | |
180 | ||
181 | dev_dbg(&ourhost->pdev->dev, | |
182 | "selected source %d, clock %d, delta %d\n", | |
183 | best_src, clock, best); | |
184 | ||
185 | /* select the new clock source */ | |
0d1bb41a BD |
186 | if (ourhost->cur_clk != best_src) { |
187 | struct clk *clk = ourhost->clk_bus[best_src]; | |
188 | ||
0f310a05 | 189 | clk_prepare_enable(clk); |
3ac147fa TF |
190 | if (ourhost->cur_clk >= 0) |
191 | clk_disable_unprepare( | |
192 | ourhost->clk_bus[ourhost->cur_clk]); | |
0d1bb41a BD |
193 | |
194 | ourhost->cur_clk = best_src; | |
6eb28bdc | 195 | host->max_clk = ourhost->clk_rates[best_src]; |
0d1bb41a BD |
196 | } |
197 | ||
3ac147fa TF |
198 | /* turn clock off to card before changing clock source */ |
199 | writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
200 | ||
201 | ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); | |
202 | ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK; | |
203 | ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; | |
204 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); | |
205 | ||
6fe47179 TA |
206 | /* reprogram default hardware configuration */ |
207 | writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, | |
208 | host->ioaddr + S3C64XX_SDHCI_CONTROL4); | |
209 | ||
210 | ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); | |
211 | ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | | |
212 | S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | | |
213 | S3C_SDHCI_CTRL2_ENFBCLKRX | | |
214 | S3C_SDHCI_CTRL2_DFCNT_NONE | | |
215 | S3C_SDHCI_CTRL2_ENCLKOUTHOLD); | |
216 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); | |
217 | ||
218 | /* reconfigure the controller for new clock rate */ | |
219 | ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); | |
220 | if (clock < 25 * 1000000) | |
221 | ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2); | |
222 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3); | |
1771059c RK |
223 | |
224 | sdhci_set_clock(host, clock); | |
0d1bb41a BD |
225 | } |
226 | ||
ce5f036b MS |
227 | /** |
228 | * sdhci_s3c_get_min_clock - callback to get minimal supported clock value | |
229 | * @host: The SDHCI host being queried | |
230 | * | |
231 | * To init mmc host properly a minimal clock value is needed. For high system | |
232 | * bus clock's values the standard formula gives values out of allowed range. | |
233 | * The clock still can be set to lower values, if clock source other then | |
234 | * system bus is selected. | |
235 | */ | |
236 | static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host) | |
237 | { | |
238 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 | 239 | unsigned long rate, min = ULONG_MAX; |
ce5f036b MS |
240 | int src; |
241 | ||
242 | for (src = 0; src < MAX_BUS_CLK; src++) { | |
222a13c5 TF |
243 | rate = ourhost->clk_rates[src] / 256; |
244 | if (!rate) | |
ce5f036b | 245 | continue; |
222a13c5 TF |
246 | if (rate < min) |
247 | min = rate; | |
ce5f036b | 248 | } |
222a13c5 | 249 | |
ce5f036b MS |
250 | return min; |
251 | } | |
252 | ||
253e0a7c JS |
253 | /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/ |
254 | static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host) | |
255 | { | |
256 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 TF |
257 | unsigned long rate, max = 0; |
258 | int src; | |
259 | ||
260 | for (src = 0; src < MAX_BUS_CLK; src++) { | |
261 | struct clk *clk; | |
262 | ||
263 | clk = ourhost->clk_bus[src]; | |
264 | if (IS_ERR(clk)) | |
265 | continue; | |
266 | ||
267 | rate = clk_round_rate(clk, ULONG_MAX); | |
268 | if (rate > max) | |
269 | max = rate; | |
270 | } | |
253e0a7c | 271 | |
222a13c5 | 272 | return max; |
253e0a7c JS |
273 | } |
274 | ||
275 | /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */ | |
276 | static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host) | |
277 | { | |
278 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 TF |
279 | unsigned long rate, min = ULONG_MAX; |
280 | int src; | |
253e0a7c | 281 | |
222a13c5 TF |
282 | for (src = 0; src < MAX_BUS_CLK; src++) { |
283 | struct clk *clk; | |
284 | ||
285 | clk = ourhost->clk_bus[src]; | |
286 | if (IS_ERR(clk)) | |
287 | continue; | |
288 | ||
289 | rate = clk_round_rate(clk, 0); | |
290 | if (rate < min) | |
291 | min = rate; | |
292 | } | |
293 | ||
294 | return min; | |
253e0a7c JS |
295 | } |
296 | ||
297 | /* sdhci_cmu_set_clock - callback on clock change.*/ | |
298 | static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock) | |
299 | { | |
300 | struct sdhci_s3c *ourhost = to_s3c(host); | |
2ad0b249 | 301 | struct device *dev = &ourhost->pdev->dev; |
3119936a TA |
302 | unsigned long timeout; |
303 | u16 clk = 0; | |
cd0cfdd2 | 304 | int ret; |
253e0a7c | 305 | |
1650d0c7 RK |
306 | host->mmc->actual_clock = 0; |
307 | ||
7ef2a5e2 JC |
308 | /* If the clock is going off, set to 0 at clock control register */ |
309 | if (clock == 0) { | |
310 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); | |
253e0a7c | 311 | return; |
7ef2a5e2 | 312 | } |
253e0a7c JS |
313 | |
314 | sdhci_s3c_set_clock(host, clock); | |
315 | ||
017210d1 PO |
316 | /* Reset SD Clock Enable */ |
317 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
318 | clk &= ~SDHCI_CLOCK_CARD_EN; | |
319 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
320 | ||
321 | spin_unlock_irq(&host->lock); | |
cd0cfdd2 | 322 | ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock); |
017210d1 | 323 | spin_lock_irq(&host->lock); |
cd0cfdd2 MB |
324 | if (ret != 0) { |
325 | dev_err(dev, "%s: failed to set clock rate %uHz\n", | |
326 | mmc_hostname(host->mmc), clock); | |
327 | return; | |
328 | } | |
253e0a7c | 329 | |
3119936a TA |
330 | clk = SDHCI_CLOCK_INT_EN; |
331 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
332 | ||
333 | /* Wait max 20 ms */ | |
334 | timeout = 20; | |
335 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) | |
336 | & SDHCI_CLOCK_INT_STABLE)) { | |
337 | if (timeout == 0) { | |
2ad0b249 JH |
338 | dev_err(dev, "%s: Internal clock never stabilised.\n", |
339 | mmc_hostname(host->mmc)); | |
3119936a TA |
340 | return; |
341 | } | |
342 | timeout--; | |
343 | mdelay(1); | |
344 | } | |
345 | ||
346 | clk |= SDHCI_CLOCK_CARD_EN; | |
347 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
253e0a7c JS |
348 | } |
349 | ||
548f07d2 | 350 | /** |
2317f56c | 351 | * sdhci_s3c_set_bus_width - support 8bit buswidth |
548f07d2 JC |
352 | * @host: The SDHCI host being queried |
353 | * @width: MMC_BUS_WIDTH_ macro for the bus width being requested | |
354 | * | |
355 | * We have 8-bit width support but is not a v3 controller. | |
7bc088d3 | 356 | * So we add platform_bus_width() and support 8bit width. |
548f07d2 | 357 | */ |
2317f56c | 358 | static void sdhci_s3c_set_bus_width(struct sdhci_host *host, int width) |
548f07d2 JC |
359 | { |
360 | u8 ctrl; | |
361 | ||
362 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
363 | ||
364 | switch (width) { | |
365 | case MMC_BUS_WIDTH_8: | |
366 | ctrl |= SDHCI_CTRL_8BITBUS; | |
367 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
368 | break; | |
369 | case MMC_BUS_WIDTH_4: | |
370 | ctrl |= SDHCI_CTRL_4BITBUS; | |
371 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
372 | break; | |
373 | default: | |
49bb1e61 G |
374 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
375 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
548f07d2 JC |
376 | break; |
377 | } | |
378 | ||
379 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
548f07d2 JC |
380 | } |
381 | ||
0d1bb41a BD |
382 | static struct sdhci_ops sdhci_s3c_ops = { |
383 | .get_max_clock = sdhci_s3c_get_max_clk, | |
0d1bb41a | 384 | .set_clock = sdhci_s3c_set_clock, |
ce5f036b | 385 | .get_min_clock = sdhci_s3c_get_min_clock, |
2317f56c | 386 | .set_bus_width = sdhci_s3c_set_bus_width, |
03231f9b | 387 | .reset = sdhci_reset, |
96d7b78c | 388 | .set_uhs_signaling = sdhci_set_uhs_signaling, |
0d1bb41a BD |
389 | }; |
390 | ||
cd1b00eb | 391 | #ifdef CONFIG_OF |
c3be1efd | 392 | static int sdhci_s3c_parse_dt(struct device *dev, |
cd1b00eb TA |
393 | struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) |
394 | { | |
395 | struct device_node *node = dev->of_node; | |
cd1b00eb | 396 | u32 max_width; |
cd1b00eb TA |
397 | |
398 | /* if the bus-width property is not specified, assume width as 1 */ | |
399 | if (of_property_read_u32(node, "bus-width", &max_width)) | |
400 | max_width = 1; | |
401 | pdata->max_width = max_width; | |
402 | ||
cd1b00eb | 403 | /* get the card detection method */ |
ab5023ef | 404 | if (of_get_property(node, "broken-cd", NULL)) { |
cd1b00eb | 405 | pdata->cd_type = S3C_SDHCI_CD_NONE; |
e19499ae | 406 | return 0; |
cd1b00eb TA |
407 | } |
408 | ||
ab5023ef | 409 | if (of_get_property(node, "non-removable", NULL)) { |
cd1b00eb | 410 | pdata->cd_type = S3C_SDHCI_CD_PERMANENT; |
e19499ae | 411 | return 0; |
cd1b00eb TA |
412 | } |
413 | ||
11bc9381 | 414 | if (of_get_named_gpio(node, "cd-gpios", 0)) |
b96efccb | 415 | return 0; |
cd1b00eb | 416 | |
e19499ae TA |
417 | /* assuming internal card detect that will be configured by pinctrl */ |
418 | pdata->cd_type = S3C_SDHCI_CD_INTERNAL; | |
cd1b00eb | 419 | return 0; |
cd1b00eb TA |
420 | } |
421 | #else | |
c3be1efd | 422 | static int sdhci_s3c_parse_dt(struct device *dev, |
cd1b00eb TA |
423 | struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) |
424 | { | |
425 | return -EINVAL; | |
426 | } | |
427 | #endif | |
428 | ||
429 | static const struct of_device_id sdhci_s3c_dt_match[]; | |
430 | ||
3119936a TA |
431 | static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data( |
432 | struct platform_device *pdev) | |
433 | { | |
cd1b00eb TA |
434 | #ifdef CONFIG_OF |
435 | if (pdev->dev.of_node) { | |
436 | const struct of_device_id *match; | |
437 | match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node); | |
438 | return (struct sdhci_s3c_drv_data *)match->data; | |
439 | } | |
440 | #endif | |
3119936a TA |
441 | return (struct sdhci_s3c_drv_data *) |
442 | platform_get_device_id(pdev)->driver_data; | |
443 | } | |
444 | ||
c3be1efd | 445 | static int sdhci_s3c_probe(struct platform_device *pdev) |
0d1bb41a | 446 | { |
1d4dc338 | 447 | struct s3c_sdhci_platdata *pdata; |
3119936a | 448 | struct sdhci_s3c_drv_data *drv_data; |
0d1bb41a BD |
449 | struct device *dev = &pdev->dev; |
450 | struct sdhci_host *host; | |
451 | struct sdhci_s3c *sc; | |
452 | struct resource *res; | |
453 | int ret, irq, ptr, clks; | |
454 | ||
cd1b00eb | 455 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
0d1bb41a BD |
456 | dev_err(dev, "no device data specified\n"); |
457 | return -ENOENT; | |
458 | } | |
459 | ||
460 | irq = platform_get_irq(pdev, 0); | |
461 | if (irq < 0) { | |
462 | dev_err(dev, "no irq specified\n"); | |
463 | return irq; | |
464 | } | |
465 | ||
0d1bb41a BD |
466 | host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c)); |
467 | if (IS_ERR(host)) { | |
468 | dev_err(dev, "sdhci_alloc_host() failed\n"); | |
469 | return PTR_ERR(host); | |
470 | } | |
cd1b00eb | 471 | sc = sdhci_priv(host); |
0d1bb41a | 472 | |
1d4dc338 TA |
473 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
474 | if (!pdata) { | |
475 | ret = -ENOMEM; | |
b1b8fea9 | 476 | goto err_pdata_io_clk; |
cd1b00eb TA |
477 | } |
478 | ||
479 | if (pdev->dev.of_node) { | |
480 | ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata); | |
481 | if (ret) | |
b1b8fea9 | 482 | goto err_pdata_io_clk; |
cd1b00eb TA |
483 | } else { |
484 | memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata)); | |
485 | sc->ext_cd_gpio = -1; /* invalid gpio number */ | |
1d4dc338 | 486 | } |
1d4dc338 | 487 | |
3119936a | 488 | drv_data = sdhci_s3c_get_driver_data(pdev); |
0d1bb41a BD |
489 | |
490 | sc->host = host; | |
491 | sc->pdev = pdev; | |
492 | sc->pdata = pdata; | |
3ac147fa | 493 | sc->cur_clk = -1; |
0d1bb41a BD |
494 | |
495 | platform_set_drvdata(pdev, host); | |
496 | ||
3aaf7ba7 | 497 | sc->clk_io = devm_clk_get(dev, "hsmmc"); |
0d1bb41a BD |
498 | if (IS_ERR(sc->clk_io)) { |
499 | dev_err(dev, "failed to get io clock\n"); | |
500 | ret = PTR_ERR(sc->clk_io); | |
b1b8fea9 | 501 | goto err_pdata_io_clk; |
0d1bb41a BD |
502 | } |
503 | ||
504 | /* enable the local io clock and keep it running for the moment. */ | |
0f310a05 | 505 | clk_prepare_enable(sc->clk_io); |
0d1bb41a BD |
506 | |
507 | for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) { | |
4346b6d9 | 508 | char name[14]; |
0d1bb41a | 509 | |
4346b6d9 | 510 | snprintf(name, 14, "mmc_busclk.%d", ptr); |
8f4b78d9 TF |
511 | sc->clk_bus[ptr] = devm_clk_get(dev, name); |
512 | if (IS_ERR(sc->clk_bus[ptr])) | |
0d1bb41a | 513 | continue; |
0d1bb41a BD |
514 | |
515 | clks++; | |
6eb28bdc TF |
516 | sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]); |
517 | ||
0d1bb41a | 518 | dev_info(dev, "clock source %d: %s (%ld Hz)\n", |
6eb28bdc | 519 | ptr, name, sc->clk_rates[ptr]); |
0d1bb41a BD |
520 | } |
521 | ||
522 | if (clks == 0) { | |
523 | dev_err(dev, "failed to find any bus clocks\n"); | |
524 | ret = -ENOENT; | |
525 | goto err_no_busclks; | |
526 | } | |
527 | ||
9bda6da7 | 528 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
a3e2cd7f TR |
529 | host->ioaddr = devm_ioremap_resource(&pdev->dev, res); |
530 | if (IS_ERR(host->ioaddr)) { | |
531 | ret = PTR_ERR(host->ioaddr); | |
0d1bb41a BD |
532 | goto err_req_regs; |
533 | } | |
534 | ||
535 | /* Ensure we have minimal gpio selected CMD/CLK/Detect */ | |
536 | if (pdata->cfg_gpio) | |
537 | pdata->cfg_gpio(pdev, pdata->max_width); | |
538 | ||
539 | host->hw_name = "samsung-hsmmc"; | |
540 | host->ops = &sdhci_s3c_ops; | |
541 | host->quirks = 0; | |
285e244f | 542 | host->quirks2 = 0; |
0d1bb41a BD |
543 | host->irq = irq; |
544 | ||
545 | /* Setup quirks for the controller */ | |
b2e75eff | 546 | host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC; |
a1d56460 | 547 | host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; |
1771059c | 548 | if (drv_data) { |
3119936a | 549 | host->quirks |= drv_data->sdhci_quirks; |
1771059c RK |
550 | sc->no_divider = drv_data->no_divider; |
551 | } | |
0d1bb41a BD |
552 | |
553 | #ifndef CONFIG_MMC_SDHCI_S3C_DMA | |
554 | ||
555 | /* we currently see overruns on errors, so disable the SDMA | |
556 | * support as well. */ | |
557 | host->quirks |= SDHCI_QUIRK_BROKEN_DMA; | |
558 | ||
559 | #endif /* CONFIG_MMC_SDHCI_S3C_DMA */ | |
560 | ||
561 | /* It seems we do not get an DATA transfer complete on non-busy | |
562 | * transfers, not sure if this is a problem with this specific | |
563 | * SDHCI block, or a missing configuration that needs to be set. */ | |
564 | host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ; | |
565 | ||
732f0e31 KP |
566 | /* This host supports the Auto CMD12 */ |
567 | host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; | |
568 | ||
7199e2b6 JC |
569 | /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */ |
570 | host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC; | |
571 | ||
17866e14 MS |
572 | if (pdata->cd_type == S3C_SDHCI_CD_NONE || |
573 | pdata->cd_type == S3C_SDHCI_CD_PERMANENT) | |
574 | host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; | |
575 | ||
576 | if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT) | |
577 | host->mmc->caps = MMC_CAP_NONREMOVABLE; | |
578 | ||
0d22c770 TA |
579 | switch (pdata->max_width) { |
580 | case 8: | |
581 | host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
582 | case 4: | |
583 | host->mmc->caps |= MMC_CAP_4_BIT_DATA; | |
584 | break; | |
585 | } | |
586 | ||
fa1773cc SL |
587 | if (pdata->pm_caps) |
588 | host->mmc->pm_caps |= pdata->pm_caps; | |
589 | ||
0d1bb41a BD |
590 | host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR | |
591 | SDHCI_QUIRK_32BIT_DMA_SIZE); | |
592 | ||
3fe42e07 HL |
593 | /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */ |
594 | host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; | |
595 | ||
253e0a7c JS |
596 | /* |
597 | * If controller does not have internal clock divider, | |
598 | * we can use overriding functions instead of default. | |
599 | */ | |
1771059c | 600 | if (sc->no_divider) { |
253e0a7c JS |
601 | sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock; |
602 | sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock; | |
603 | sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock; | |
604 | } | |
605 | ||
b3824f2c JS |
606 | /* It supports additional host capabilities if needed */ |
607 | if (pdata->host_caps) | |
608 | host->mmc->caps |= pdata->host_caps; | |
609 | ||
c1c4b66d JC |
610 | if (pdata->host_caps2) |
611 | host->mmc->caps2 |= pdata->host_caps2; | |
612 | ||
9f4e8151 MB |
613 | pm_runtime_enable(&pdev->dev); |
614 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); | |
615 | pm_runtime_use_autosuspend(&pdev->dev); | |
616 | pm_suspend_ignore_children(&pdev->dev, 1); | |
617 | ||
f8e3260c UH |
618 | ret = mmc_of_parse(host->mmc); |
619 | if (ret) | |
620 | goto err_req_regs; | |
11bc9381 | 621 | |
0d1bb41a BD |
622 | ret = sdhci_add_host(host); |
623 | if (ret) { | |
624 | dev_err(dev, "sdhci_add_host() failed\n"); | |
9bda6da7 | 625 | goto err_req_regs; |
0d1bb41a BD |
626 | } |
627 | ||
162d6f98 | 628 | #ifdef CONFIG_PM |
0aa55c23 SJ |
629 | if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL) |
630 | clk_disable_unprepare(sc->clk_io); | |
2abeb5c5 | 631 | #endif |
0d1bb41a BD |
632 | return 0; |
633 | ||
0d1bb41a | 634 | err_req_regs: |
221414db BZ |
635 | pm_runtime_disable(&pdev->dev); |
636 | ||
0d1bb41a | 637 | err_no_busclks: |
0f310a05 | 638 | clk_disable_unprepare(sc->clk_io); |
0d1bb41a | 639 | |
b1b8fea9 | 640 | err_pdata_io_clk: |
0d1bb41a BD |
641 | sdhci_free_host(host); |
642 | ||
643 | return ret; | |
644 | } | |
645 | ||
6e0ee714 | 646 | static int sdhci_s3c_remove(struct platform_device *pdev) |
0d1bb41a | 647 | { |
9d51a6b2 MS |
648 | struct sdhci_host *host = platform_get_drvdata(pdev); |
649 | struct sdhci_s3c *sc = sdhci_priv(host); | |
17866e14 MS |
650 | |
651 | if (sc->ext_cd_irq) | |
652 | free_irq(sc->ext_cd_irq, sc); | |
653 | ||
162d6f98 | 654 | #ifdef CONFIG_PM |
11bc9381 | 655 | if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL) |
0aa55c23 | 656 | clk_prepare_enable(sc->clk_io); |
2abeb5c5 | 657 | #endif |
9d51a6b2 MS |
658 | sdhci_remove_host(host, 1); |
659 | ||
387a8cbd | 660 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
9f4e8151 MB |
661 | pm_runtime_disable(&pdev->dev); |
662 | ||
0f310a05 | 663 | clk_disable_unprepare(sc->clk_io); |
9d51a6b2 | 664 | |
9d51a6b2 | 665 | sdhci_free_host(host); |
9d51a6b2 | 666 | |
0d1bb41a BD |
667 | return 0; |
668 | } | |
669 | ||
d5e9c02c | 670 | #ifdef CONFIG_PM_SLEEP |
29495aa0 | 671 | static int sdhci_s3c_suspend(struct device *dev) |
0d1bb41a | 672 | { |
29495aa0 | 673 | struct sdhci_host *host = dev_get_drvdata(dev); |
0d1bb41a | 674 | |
29495aa0 | 675 | return sdhci_suspend_host(host); |
0d1bb41a BD |
676 | } |
677 | ||
29495aa0 | 678 | static int sdhci_s3c_resume(struct device *dev) |
0d1bb41a | 679 | { |
29495aa0 | 680 | struct sdhci_host *host = dev_get_drvdata(dev); |
0d1bb41a | 681 | |
65d13516 | 682 | return sdhci_resume_host(host); |
0d1bb41a | 683 | } |
d5e9c02c | 684 | #endif |
0d1bb41a | 685 | |
162d6f98 | 686 | #ifdef CONFIG_PM |
9f4e8151 MB |
687 | static int sdhci_s3c_runtime_suspend(struct device *dev) |
688 | { | |
689 | struct sdhci_host *host = dev_get_drvdata(dev); | |
2abeb5c5 CK |
690 | struct sdhci_s3c *ourhost = to_s3c(host); |
691 | struct clk *busclk = ourhost->clk_io; | |
692 | int ret; | |
693 | ||
694 | ret = sdhci_runtime_suspend_host(host); | |
9f4e8151 | 695 | |
3ac147fa TF |
696 | if (ourhost->cur_clk >= 0) |
697 | clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]); | |
0f310a05 | 698 | clk_disable_unprepare(busclk); |
2abeb5c5 | 699 | return ret; |
9f4e8151 MB |
700 | } |
701 | ||
702 | static int sdhci_s3c_runtime_resume(struct device *dev) | |
703 | { | |
704 | struct sdhci_host *host = dev_get_drvdata(dev); | |
2abeb5c5 CK |
705 | struct sdhci_s3c *ourhost = to_s3c(host); |
706 | struct clk *busclk = ourhost->clk_io; | |
707 | int ret; | |
9f4e8151 | 708 | |
0f310a05 | 709 | clk_prepare_enable(busclk); |
3ac147fa TF |
710 | if (ourhost->cur_clk >= 0) |
711 | clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]); | |
2abeb5c5 CK |
712 | ret = sdhci_runtime_resume_host(host); |
713 | return ret; | |
9f4e8151 MB |
714 | } |
715 | #endif | |
716 | ||
d5e9c02c | 717 | #ifdef CONFIG_PM |
29495aa0 | 718 | static const struct dev_pm_ops sdhci_s3c_pmops = { |
d5e9c02c | 719 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume) |
9f4e8151 MB |
720 | SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume, |
721 | NULL) | |
29495aa0 ML |
722 | }; |
723 | ||
724 | #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops) | |
725 | ||
0d1bb41a | 726 | #else |
29495aa0 | 727 | #define SDHCI_S3C_PMOPS NULL |
0d1bb41a BD |
728 | #endif |
729 | ||
3119936a TA |
730 | #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) |
731 | static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = { | |
1771059c | 732 | .no_divider = true, |
3119936a TA |
733 | }; |
734 | #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data) | |
735 | #else | |
736 | #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL) | |
737 | #endif | |
738 | ||
4d0aa491 | 739 | static const struct platform_device_id sdhci_s3c_driver_ids[] = { |
3119936a TA |
740 | { |
741 | .name = "s3c-sdhci", | |
742 | .driver_data = (kernel_ulong_t)NULL, | |
743 | }, { | |
744 | .name = "exynos4-sdhci", | |
745 | .driver_data = EXYNOS4_SDHCI_DRV_DATA, | |
746 | }, | |
747 | { } | |
748 | }; | |
749 | MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids); | |
750 | ||
cd1b00eb TA |
751 | #ifdef CONFIG_OF |
752 | static const struct of_device_id sdhci_s3c_dt_match[] = { | |
753 | { .compatible = "samsung,s3c6410-sdhci", }, | |
754 | { .compatible = "samsung,exynos4210-sdhci", | |
755 | .data = (void *)EXYNOS4_SDHCI_DRV_DATA }, | |
756 | {}, | |
757 | }; | |
758 | MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match); | |
759 | #endif | |
760 | ||
0d1bb41a BD |
761 | static struct platform_driver sdhci_s3c_driver = { |
762 | .probe = sdhci_s3c_probe, | |
0433c143 | 763 | .remove = sdhci_s3c_remove, |
3119936a | 764 | .id_table = sdhci_s3c_driver_ids, |
0d1bb41a | 765 | .driver = { |
0d1bb41a | 766 | .name = "s3c-sdhci", |
cd1b00eb | 767 | .of_match_table = of_match_ptr(sdhci_s3c_dt_match), |
29495aa0 | 768 | .pm = SDHCI_S3C_PMOPS, |
0d1bb41a BD |
769 | }, |
770 | }; | |
771 | ||
d1f81a64 | 772 | module_platform_driver(sdhci_s3c_driver); |
0d1bb41a BD |
773 | |
774 | MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue"); | |
775 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
776 | MODULE_LICENSE("GPL v2"); | |
777 | MODULE_ALIAS("platform:s3c-sdhci"); |