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mmc: eSDHC: Add ADMA mode support
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
d129bceb 31
d129bceb
PO		 32#include "sdhci.h"
33
34#define DRIVER_NAME "sdhci"
d129bceb 35
d129bceb 36#define DBG(f, x...) \
c6563178 37 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 38
f9134319
PO		 39#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
40 defined(CONFIG_MMC_SDHCI_MODULE))
41#define SDHCI_USE_LEDS_CLASS
42#endif
43
b513ea25
AN		 44#define MAX_TUNING_LOOP 40
45
df673b22 46static unsigned int debug_quirks = 0;
66fd8ad5 47static unsigned int debug_quirks2;
67435274 48
d129bceb
PO		 49static void sdhci_finish_data(struct sdhci_host *);
50
51static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
52static void sdhci_finish_command(struct sdhci_host *);
069c9f14 53static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 54static void sdhci_tuning_timer(unsigned long data);
d129bceb 55
66fd8ad5
AH		 56#ifdef CONFIG_PM_RUNTIME
57static int sdhci_runtime_pm_get(struct sdhci_host *host);
58static int sdhci_runtime_pm_put(struct sdhci_host *host);
59#else
60static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
61{
62 return 0;
63}
64static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
65{
66 return 0;
67}
68#endif
69
d129bceb
PO		 70static void sdhci_dumpregs(struct sdhci_host *host)
71{
a3c76eb9 72 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 73 mmc_hostname(host->mmc));
d129bceb 74
a3c76eb9 75 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 76 sdhci_readl(host, SDHCI_DMA_ADDRESS),
77 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 78 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 79 sdhci_readw(host, SDHCI_BLOCK_SIZE),
80 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 81 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 82 sdhci_readl(host, SDHCI_ARGUMENT),
83 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 84 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 85 sdhci_readl(host, SDHCI_PRESENT_STATE),
86 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 87 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 88 sdhci_readb(host, SDHCI_POWER_CONTROL),
89 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 90 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 91 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
92 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 93 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 94 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
95 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 96 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 97 sdhci_readl(host, SDHCI_INT_ENABLE),
98 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 99 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 100 sdhci_readw(host, SDHCI_ACMD12_ERR),
101 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 102 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 103 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 104 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 105 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 106 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 107 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 108 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 109 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 110
be3f4ae0 111 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 112 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 113 readl(host->ioaddr + SDHCI_ADMA_ERROR),
114 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
115
a3c76eb9 116 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 117}
118
119/*****************************************************************************\
120 * *
121 * Low level functions *
122 * *
123\*****************************************************************************/
124
7260cf5e
AV		 125static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
126{
127 u32 ier;
128
129 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
130 ier &= ~clear;
131 ier |= set;
132 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
133 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
134}
135
136static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
137{
138 sdhci_clear_set_irqs(host, 0, irqs);
139}
140
141static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
142{
143 sdhci_clear_set_irqs(host, irqs, 0);
144}
145
146static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
147{
d25928d1 148 u32 present, irqs;
7260cf5e 149
c79396c1 150 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 151 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 152 return;
153
d25928d1
SG		 154 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
155 SDHCI_CARD_PRESENT;
156 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
157
7260cf5e
AV		 158 if (enable)
159 sdhci_unmask_irqs(host, irqs);
160 else
161 sdhci_mask_irqs(host, irqs);
162}
163
164static void sdhci_enable_card_detection(struct sdhci_host *host)
165{
166 sdhci_set_card_detection(host, true);
167}
168
169static void sdhci_disable_card_detection(struct sdhci_host *host)
170{
171 sdhci_set_card_detection(host, false);
172}
173
d129bceb
PO		 174static void sdhci_reset(struct sdhci_host *host, u8 mask)
175{
e16514d8 176 unsigned long timeout;
063a9dbb 177 u32 uninitialized_var(ier);
e16514d8 178
b8c86fc5 179 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 180 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 181 SDHCI_CARD_PRESENT))
182 return;
183 }
184
063a9dbb
AV		 185 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
186 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
187
393c1a34
PR		 188 if (host->ops->platform_reset_enter)
189 host->ops->platform_reset_enter(host, mask);
190
4e4141a5 191 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 192
e16514d8 193 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 194 host->clock = 0;
195
e16514d8
PO		 196 /* Wait max 100 ms */
197 timeout = 100;
198
199 /* hw clears the bit when it's done */
4e4141a5 200 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 201 if (timeout == 0) {
a3c76eb9 202 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 203 mmc_hostname(host->mmc), (int)mask);
204 sdhci_dumpregs(host);
205 return;
206 }
207 timeout--;
208 mdelay(1);
d129bceb 209 }
063a9dbb 210
393c1a34
PR		 211 if (host->ops->platform_reset_exit)
212 host->ops->platform_reset_exit(host, mask);
213
063a9dbb
AV		 214 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
215 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
3abc1e80
SX		 216
217 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
218 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
219 host->ops->enable_dma(host);
220 }
d129bceb
PO		 221}
222
2f4cbb3d
NP		 223static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
224
225static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 226{
2f4cbb3d
NP		 227 if (soft)
228 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
229 else
230 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 231
7260cf5e
AV		 232 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
233 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
235 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 236 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 237
238 if (soft) {
239 /* force clock reconfiguration */
240 host->clock = 0;
241 sdhci_set_ios(host->mmc, &host->mmc->ios);
242 }
7260cf5e 243}
d129bceb 244
7260cf5e
AV		 245static void sdhci_reinit(struct sdhci_host *host)
246{
2f4cbb3d 247 sdhci_init(host, 0);
b67c6b41
AL		 248 /*
249 * Retuning stuffs are affected by different cards inserted and only
250 * applicable to UHS-I cards. So reset these fields to their initial
251 * value when card is removed.
252 */
973905fe
AL		 253 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
254 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
255
b67c6b41
AL		 256 del_timer_sync(&host->tuning_timer);
257 host->flags &= ~SDHCI_NEEDS_RETUNING;
258 host->mmc->max_blk_count =
259 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
260 }
7260cf5e 261 sdhci_enable_card_detection(host);
d129bceb
PO		 262}
263
264static void sdhci_activate_led(struct sdhci_host *host)
265{
266 u8 ctrl;
267
4e4141a5 268 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 269 ctrl |= SDHCI_CTRL_LED;
4e4141a5 270 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 271}
272
273static void sdhci_deactivate_led(struct sdhci_host *host)
274{
275 u8 ctrl;
276
4e4141a5 277 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 278 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 279 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 280}
281
f9134319 282#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 283static void sdhci_led_control(struct led_classdev *led,
284 enum led_brightness brightness)
285{
286 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
287 unsigned long flags;
288
289 spin_lock_irqsave(&host->lock, flags);
290
66fd8ad5
AH		 291 if (host->runtime_suspended)
292 goto out;
293
2f730fec
PO		 294 if (brightness == LED_OFF)
295 sdhci_deactivate_led(host);
296 else
297 sdhci_activate_led(host);
66fd8ad5 298out:
2f730fec
PO		 299 spin_unlock_irqrestore(&host->lock, flags);
300}
301#endif
302
d129bceb
PO		 303/*****************************************************************************\
304 * *
305 * Core functions *
306 * *
307\*****************************************************************************/
308
a406f5a3 309static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 310{
7659150c
PO		 311 unsigned long flags;
312 size_t blksize, len, chunk;
7244b85b 313 u32 uninitialized_var(scratch);
7659150c 314 u8 *buf;
d129bceb 315
a406f5a3 316 DBG("PIO reading\n");
d129bceb 317
a406f5a3 318 blksize = host->data->blksz;
7659150c 319 chunk = 0;
d129bceb 320
7659150c 321 local_irq_save(flags);
d129bceb 322
a406f5a3 323 while (blksize) {
7659150c
PO		 324 if (!sg_miter_next(&host->sg_miter))
325 BUG();
d129bceb 326
7659150c 327 len = min(host->sg_miter.length, blksize);
d129bceb 328
7659150c
PO		 329 blksize -= len;
330 host->sg_miter.consumed = len;
14d836e7 331
7659150c 332 buf = host->sg_miter.addr;
d129bceb 333
7659150c
PO		 334 while (len) {
335 if (chunk == 0) {
4e4141a5 336 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 337 chunk = 4;
a406f5a3 338 }
7659150c
PO		 339
340 *buf = scratch & 0xFF;
341
342 buf++;
343 scratch >>= 8;
344 chunk--;
345 len--;
d129bceb 346 }
a406f5a3 347 }
7659150c
PO		 348
349 sg_miter_stop(&host->sg_miter);
350
351 local_irq_restore(flags);
a406f5a3 352}
d129bceb 353
a406f5a3
PO		 354static void sdhci_write_block_pio(struct sdhci_host *host)
355{
7659150c
PO		 356 unsigned long flags;
357 size_t blksize, len, chunk;
358 u32 scratch;
359 u8 *buf;
d129bceb 360
a406f5a3
PO		 361 DBG("PIO writing\n");
362
363 blksize = host->data->blksz;
7659150c
PO		 364 chunk = 0;
365 scratch = 0;
d129bceb 366
7659150c 367 local_irq_save(flags);
d129bceb 368
a406f5a3 369 while (blksize) {
7659150c
PO		 370 if (!sg_miter_next(&host->sg_miter))
371 BUG();
a406f5a3 372
7659150c
PO		 373 len = min(host->sg_miter.length, blksize);
374
375 blksize -= len;
376 host->sg_miter.consumed = len;
377
378 buf = host->sg_miter.addr;
d129bceb 379
7659150c
PO		 380 while (len) {
381 scratch |= (u32)*buf << (chunk * 8);
382
383 buf++;
384 chunk++;
385 len--;
386
387 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 388 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 389 chunk = 0;
390 scratch = 0;
d129bceb 391 }
d129bceb
PO		 392 }
393 }
7659150c
PO		 394
395 sg_miter_stop(&host->sg_miter);
396
397 local_irq_restore(flags);
a406f5a3
PO		 398}
399
400static void sdhci_transfer_pio(struct sdhci_host *host)
401{
402 u32 mask;
403
404 BUG_ON(!host->data);
405
7659150c 406 if (host->blocks == 0)
a406f5a3
PO		 407 return;
408
409 if (host->data->flags & MMC_DATA_READ)
410 mask = SDHCI_DATA_AVAILABLE;
411 else
412 mask = SDHCI_SPACE_AVAILABLE;
413
4a3cba32
PO		 414 /*
415 * Some controllers (JMicron JMB38x) mess up the buffer bits
416 * for transfers < 4 bytes. As long as it is just one block,
417 * we can ignore the bits.
418 */
419 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
420 (host->data->blocks == 1))
421 mask = ~0;
422
4e4141a5 423 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 424 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
425 udelay(100);
426
a406f5a3
PO		 427 if (host->data->flags & MMC_DATA_READ)
428 sdhci_read_block_pio(host);
429 else
430 sdhci_write_block_pio(host);
d129bceb 431
7659150c
PO		 432 host->blocks--;
433 if (host->blocks == 0)
a406f5a3 434 break;
a406f5a3 435 }
d129bceb 436
a406f5a3 437 DBG("PIO transfer complete.\n");
d129bceb
PO		 438}
439
2134a922
PO		 440static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
441{
442 local_irq_save(*flags);
482fce99 443 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 444}
445
446static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
447{
482fce99 448 kunmap_atomic(buffer);
2134a922
PO		 449 local_irq_restore(*flags);
450}
451
118cd17d
BD		 452static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
453{
9e506f35
BD		 454 __le32 *dataddr = (__le32 __force *)(desc + 4);
455 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 456
9e506f35
BD		 457 /* SDHCI specification says ADMA descriptors should be 4 byte
458 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 459
9e506f35
BD		 460 cmdlen[0] = cpu_to_le16(cmd);
461 cmdlen[1] = cpu_to_le16(len);
462
463 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 464}
465
8f1934ce 466static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 467 struct mmc_data *data)
468{
469 int direction;
470
471 u8 *desc;
472 u8 *align;
473 dma_addr_t addr;
474 dma_addr_t align_addr;
475 int len, offset;
476
477 struct scatterlist *sg;
478 int i;
479 char *buffer;
480 unsigned long flags;
481
482 /*
483 * The spec does not specify endianness of descriptor table.
484 * We currently guess that it is LE.
485 */
486
487 if (data->flags & MMC_DATA_READ)
488 direction = DMA_FROM_DEVICE;
489 else
490 direction = DMA_TO_DEVICE;
491
492 /*
493 * The ADMA descriptor table is mapped further down as we
494 * need to fill it with data first.
495 */
496
497 host->align_addr = dma_map_single(mmc_dev(host->mmc),
498 host->align_buffer, 128 * 4, direction);
8d8bb39b 499 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 500 goto fail;
2134a922
PO		 501 BUG_ON(host->align_addr & 0x3);
502
503 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
504 data->sg, data->sg_len, direction);
8f1934ce
PO		 505 if (host->sg_count == 0)
506 goto unmap_align;
2134a922
PO		 507
508 desc = host->adma_desc;
509 align = host->align_buffer;
510
511 align_addr = host->align_addr;
512
513 for_each_sg(data->sg, sg, host->sg_count, i) {
514 addr = sg_dma_address(sg);
515 len = sg_dma_len(sg);
516
517 /*
518 * The SDHCI specification states that ADMA
519 * addresses must be 32-bit aligned. If they
520 * aren't, then we use a bounce buffer for
521 * the (up to three) bytes that screw up the
522 * alignment.
523 */
524 offset = (4 - (addr & 0x3)) & 0x3;
525 if (offset) {
526 if (data->flags & MMC_DATA_WRITE) {
527 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 528 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 529 memcpy(align, buffer, offset);
530 sdhci_kunmap_atomic(buffer, &flags);
531 }
532
118cd17d
BD		 533 /* tran, valid */
534 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 535
536 BUG_ON(offset > 65536);
537
2134a922
PO		 538 align += 4;
539 align_addr += 4;
540
541 desc += 8;
542
543 addr += offset;
544 len -= offset;
545 }
546
2134a922
PO		 547 BUG_ON(len > 65536);
548
118cd17d
BD		 549 /* tran, valid */
550 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 551 desc += 8;
552
553 /*
554 * If this triggers then we have a calculation bug
555 * somewhere. :/
556 */
557 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
558 }
559
70764a90
TA		 560 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
561 /*
562 * Mark the last descriptor as the terminating descriptor
563 */
564 if (desc != host->adma_desc) {
565 desc -= 8;
566 desc[0] |= 0x2; /* end */
567 }
568 } else {
569 /*
570 * Add a terminating entry.
571 */
2134a922 572
70764a90
TA		 573 /* nop, end, valid */
574 sdhci_set_adma_desc(desc, 0, 0, 0x3);
575 }
2134a922
PO		 576
577 /*
578 * Resync align buffer as we might have changed it.
579 */
580 if (data->flags & MMC_DATA_WRITE) {
581 dma_sync_single_for_device(mmc_dev(host->mmc),
582 host->align_addr, 128 * 4, direction);
583 }
584
585 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
586 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 587 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 588 goto unmap_entries;
2134a922 589 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 590
591 return 0;
592
593unmap_entries:
594 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
595 data->sg_len, direction);
596unmap_align:
597 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
598 128 * 4, direction);
599fail:
600 return -EINVAL;
2134a922
PO		 601}
602
603static void sdhci_adma_table_post(struct sdhci_host *host,
604 struct mmc_data *data)
605{
606 int direction;
607
608 struct scatterlist *sg;
609 int i, size;
610 u8 *align;
611 char *buffer;
612 unsigned long flags;
613
614 if (data->flags & MMC_DATA_READ)
615 direction = DMA_FROM_DEVICE;
616 else
617 direction = DMA_TO_DEVICE;
618
619 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
620 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
621
622 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
623 128 * 4, direction);
624
625 if (data->flags & MMC_DATA_READ) {
626 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
627 data->sg_len, direction);
628
629 align = host->align_buffer;
630
631 for_each_sg(data->sg, sg, host->sg_count, i) {
632 if (sg_dma_address(sg) & 0x3) {
633 size = 4 - (sg_dma_address(sg) & 0x3);
634
635 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 636 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 637 memcpy(buffer, align, size);
638 sdhci_kunmap_atomic(buffer, &flags);
639
640 align += 4;
641 }
642 }
643 }
644
645 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
646 data->sg_len, direction);
647}
648
a3c7778f 649static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 650{
1c8cde92 651 u8 count;
a3c7778f 652 struct mmc_data *data = cmd->data;
1c8cde92 653 unsigned target_timeout, current_timeout;
d129bceb 654
ee53ab5d
PO		 655 /*
656 * If the host controller provides us with an incorrect timeout
657 * value, just skip the check and use 0xE. The hardware may take
658 * longer to time out, but that's much better than having a too-short
659 * timeout value.
660 */
11a2f1b7 661 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 662 return 0xE;
e538fbe8 663
a3c7778f
AW		 664 /* Unspecified timeout, assume max */
665 if (!data && !cmd->cmd_timeout_ms)
666 return 0xE;
d129bceb 667
a3c7778f
AW		 668 /* timeout in us */
669 if (!data)
670 target_timeout = cmd->cmd_timeout_ms * 1000;
78a2ca27
AS		 671 else {
672 target_timeout = data->timeout_ns / 1000;
673 if (host->clock)
674 target_timeout += data->timeout_clks / host->clock;
675 }
81b39802 676
1c8cde92
PO		 677 /*
678 * Figure out needed cycles.
679 * We do this in steps in order to fit inside a 32 bit int.
680 * The first step is the minimum timeout, which will have a
681 * minimum resolution of 6 bits:
682 * (1) 2^13*1000 > 2^22,
683 * (2) host->timeout_clk < 2^16
684 * =>
685 * (1) / (2) > 2^6
686 */
687 count = 0;
688 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
689 while (current_timeout < target_timeout) {
690 count++;
691 current_timeout <<= 1;
692 if (count >= 0xF)
693 break;
694 }
695
696 if (count >= 0xF) {
09eeff52
CB		 697 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
698 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 699 count = 0xE;
700 }
701
ee53ab5d
PO		 702 return count;
703}
704
6aa943ab
AV		 705static void sdhci_set_transfer_irqs(struct sdhci_host *host)
706{
707 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
708 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
709
710 if (host->flags & SDHCI_REQ_USE_DMA)
711 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
712 else
713 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
714}
715
a3c7778f 716static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 717{
718 u8 count;
2134a922 719 u8 ctrl;
a3c7778f 720 struct mmc_data *data = cmd->data;
8f1934ce 721 int ret;
ee53ab5d
PO		 722
723 WARN_ON(host->data);
724
a3c7778f
AW		 725 if (data || (cmd->flags & MMC_RSP_BUSY)) {
726 count = sdhci_calc_timeout(host, cmd);
727 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
728 }
729
730 if (!data)
ee53ab5d
PO		 731 return;
732
733 /* Sanity checks */
734 BUG_ON(data->blksz * data->blocks > 524288);
735 BUG_ON(data->blksz > host->mmc->max_blk_size);
736 BUG_ON(data->blocks > 65535);
737
738 host->data = data;
739 host->data_early = 0;
f6a03cbf 740 host->data->bytes_xfered = 0;
ee53ab5d 741
a13abc7b 742 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 743 host->flags |= SDHCI_REQ_USE_DMA;
744
2134a922
PO		 745 /*
746 * FIXME: This doesn't account for merging when mapping the
747 * scatterlist.
748 */
749 if (host->flags & SDHCI_REQ_USE_DMA) {
750 int broken, i;
751 struct scatterlist *sg;
752
753 broken = 0;
754 if (host->flags & SDHCI_USE_ADMA) {
755 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
756 broken = 1;
757 } else {
758 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
759 broken = 1;
760 }
761
762 if (unlikely(broken)) {
763 for_each_sg(data->sg, sg, data->sg_len, i) {
764 if (sg->length & 0x3) {
765 DBG("Reverting to PIO because of "
766 "transfer size (%d)\n",
767 sg->length);
768 host->flags &= ~SDHCI_REQ_USE_DMA;
769 break;
770 }
771 }
772 }
c9fddbc4
PO		 773 }
774
775 /*
776 * The assumption here being that alignment is the same after
777 * translation to device address space.
778 */
2134a922
PO		 779 if (host->flags & SDHCI_REQ_USE_DMA) {
780 int broken, i;
781 struct scatterlist *sg;
782
783 broken = 0;
784 if (host->flags & SDHCI_USE_ADMA) {
785 /*
786 * As we use 3 byte chunks to work around
787 * alignment problems, we need to check this
788 * quirk.
789 */
790 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
791 broken = 1;
792 } else {
793 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
794 broken = 1;
795 }
796
797 if (unlikely(broken)) {
798 for_each_sg(data->sg, sg, data->sg_len, i) {
799 if (sg->offset & 0x3) {
800 DBG("Reverting to PIO because of "
801 "bad alignment\n");
802 host->flags &= ~SDHCI_REQ_USE_DMA;
803 break;
804 }
805 }
806 }
807 }
808
8f1934ce
PO		 809 if (host->flags & SDHCI_REQ_USE_DMA) {
810 if (host->flags & SDHCI_USE_ADMA) {
811 ret = sdhci_adma_table_pre(host, data);
812 if (ret) {
813 /*
814 * This only happens when someone fed
815 * us an invalid request.
816 */
817 WARN_ON(1);
ebd6d357 818 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 819 } else {
4e4141a5
AV		 820 sdhci_writel(host, host->adma_addr,
821 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 822 }
823 } else {
c8b3e02e 824 int sg_cnt;
8f1934ce 825
c8b3e02e 826 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 827 data->sg, data->sg_len,
828 (data->flags & MMC_DATA_READ) ?
829 DMA_FROM_DEVICE :
830 DMA_TO_DEVICE);
c8b3e02e 831 if (sg_cnt == 0) {
8f1934ce
PO		 832 /*
833 * This only happens when someone fed
834 * us an invalid request.
835 */
836 WARN_ON(1);
ebd6d357 837 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 838 } else {
719a61b4 839 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 840 sdhci_writel(host, sg_dma_address(data->sg),
841 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 842 }
843 }
844 }
845
2134a922
PO		 846 /*
847 * Always adjust the DMA selection as some controllers
848 * (e.g. JMicron) can't do PIO properly when the selection
849 * is ADMA.
850 */
851 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 852 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 853 ctrl &= ~SDHCI_CTRL_DMA_MASK;
854 if ((host->flags & SDHCI_REQ_USE_DMA) &&
855 (host->flags & SDHCI_USE_ADMA))
856 ctrl |= SDHCI_CTRL_ADMA32;
857 else
858 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 859 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 860 }
861
8f1934ce 862 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 863 int flags;
864
865 flags = SG_MITER_ATOMIC;
866 if (host->data->flags & MMC_DATA_READ)
867 flags |= SG_MITER_TO_SG;
868 else
869 flags |= SG_MITER_FROM_SG;
870 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 871 host->blocks = data->blocks;
d129bceb 872 }
c7fa9963 873
6aa943ab
AV		 874 sdhci_set_transfer_irqs(host);
875
f6a03cbf
MV		 876 /* Set the DMA boundary value and block size */
877 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
878 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 879 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 880}
881
882static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 883 struct mmc_command *cmd)
c7fa9963
PO		 884{
885 u16 mode;
e89d456f 886 struct mmc_data *data = cmd->data;
c7fa9963 887
c7fa9963
PO		 888 if (data == NULL)
889 return;
890
e538fbe8
PO		 891 WARN_ON(!host->data);
892
c7fa9963 893 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 894 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
895 mode |= SDHCI_TRNS_MULTI;
896 /*
897 * If we are sending CMD23, CMD12 never gets sent
898 * on successful completion (so no Auto-CMD12).
899 */
900 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
901 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 902 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
903 mode |= SDHCI_TRNS_AUTO_CMD23;
904 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
905 }
c4512f79 906 }
8edf6371 907
c7fa9963
PO		 908 if (data->flags & MMC_DATA_READ)
909 mode |= SDHCI_TRNS_READ;
c9fddbc4 910 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 911 mode |= SDHCI_TRNS_DMA;
912
4e4141a5 913 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 914}
915
916static void sdhci_finish_data(struct sdhci_host *host)
917{
918 struct mmc_data *data;
d129bceb
PO		 919
920 BUG_ON(!host->data);
921
922 data = host->data;
923 host->data = NULL;
924
c9fddbc4 925 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 926 if (host->flags & SDHCI_USE_ADMA)
927 sdhci_adma_table_post(host, data);
928 else {
929 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
930 data->sg_len, (data->flags & MMC_DATA_READ) ?
931 DMA_FROM_DEVICE : DMA_TO_DEVICE);
932 }
d129bceb
PO		 933 }
934
935 /*
c9b74c5b
PO		 936 * The specification states that the block count register must
937 * be updated, but it does not specify at what point in the
938 * data flow. That makes the register entirely useless to read
939 * back so we have to assume that nothing made it to the card
940 * in the event of an error.
d129bceb 941 */
c9b74c5b
PO		 942 if (data->error)
943 data->bytes_xfered = 0;
d129bceb 944 else
c9b74c5b 945 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 946
e89d456f
AW		 947 /*
948 * Need to send CMD12 if -
949 * a) open-ended multiblock transfer (no CMD23)
950 * b) error in multiblock transfer
951 */
952 if (data->stop &&
953 (data->error ||
954 !host->mrq->sbc)) {
955
d129bceb
PO		 956 /*
957 * The controller needs a reset of internal state machines
958 * upon error conditions.
959 */
17b0429d 960 if (data->error) {
d129bceb
PO		 961 sdhci_reset(host, SDHCI_RESET_CMD);
962 sdhci_reset(host, SDHCI_RESET_DATA);
963 }
964
965 sdhci_send_command(host, data->stop);
966 } else
967 tasklet_schedule(&host->finish_tasklet);
968}
969
970static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
971{
972 int flags;
fd2208d7 973 u32 mask;
7cb2c76f 974 unsigned long timeout;
d129bceb
PO		 975
976 WARN_ON(host->cmd);
977
d129bceb 978 /* Wait max 10 ms */
7cb2c76f 979 timeout = 10;
fd2208d7
PO		 980
981 mask = SDHCI_CMD_INHIBIT;
982 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
983 mask |= SDHCI_DATA_INHIBIT;
984
985 /* We shouldn't wait for data inihibit for stop commands, even
986 though they might use busy signaling */
987 if (host->mrq->data && (cmd == host->mrq->data->stop))
988 mask &= ~SDHCI_DATA_INHIBIT;
989
4e4141a5 990 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 991 if (timeout == 0) {
a3c76eb9 992 pr_err("%s: Controller never released "
acf1da45 993 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 994 sdhci_dumpregs(host);
17b0429d 995 cmd->error = -EIO;
d129bceb
PO		 996 tasklet_schedule(&host->finish_tasklet);
997 return;
998 }
7cb2c76f
PO		 999 timeout--;
1000 mdelay(1);
1001 }
d129bceb
PO		 1002
1003 mod_timer(&host->timer, jiffies + 10 * HZ);
1004
1005 host->cmd = cmd;
1006
a3c7778f 1007 sdhci_prepare_data(host, cmd);
d129bceb 1008
4e4141a5 1009 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1010
e89d456f 1011 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1012
d129bceb 1013 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1014 pr_err("%s: Unsupported response type!\n",
d129bceb 1015 mmc_hostname(host->mmc));
17b0429d 1016 cmd->error = -EINVAL;
d129bceb
PO		 1017 tasklet_schedule(&host->finish_tasklet);
1018 return;
1019 }
1020
1021 if (!(cmd->flags & MMC_RSP_PRESENT))
1022 flags = SDHCI_CMD_RESP_NONE;
1023 else if (cmd->flags & MMC_RSP_136)
1024 flags = SDHCI_CMD_RESP_LONG;
1025 else if (cmd->flags & MMC_RSP_BUSY)
1026 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1027 else
1028 flags = SDHCI_CMD_RESP_SHORT;
1029
1030 if (cmd->flags & MMC_RSP_CRC)
1031 flags |= SDHCI_CMD_CRC;
1032 if (cmd->flags & MMC_RSP_OPCODE)
1033 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1034
1035 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1036 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1037 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1038 flags |= SDHCI_CMD_DATA;
1039
4e4141a5 1040 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 1041}
1042
1043static void sdhci_finish_command(struct sdhci_host *host)
1044{
1045 int i;
1046
1047 BUG_ON(host->cmd == NULL);
1048
1049 if (host->cmd->flags & MMC_RSP_PRESENT) {
1050 if (host->cmd->flags & MMC_RSP_136) {
1051 /* CRC is stripped so we need to do some shifting. */
1052 for (i = 0;i < 4;i++) {
4e4141a5 1053 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1054 SDHCI_RESPONSE + (3-i)*4) << 8;
1055 if (i != 3)
1056 host->cmd->resp[i] |=
4e4141a5 1057 sdhci_readb(host,
d129bceb
PO		 1058 SDHCI_RESPONSE + (3-i)*4-1);
1059 }
1060 } else {
4e4141a5 1061 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1062 }
1063 }
1064
17b0429d 1065 host->cmd->error = 0;
d129bceb 1066
e89d456f
AW		 1067 /* Finished CMD23, now send actual command. */
1068 if (host->cmd == host->mrq->sbc) {
1069 host->cmd = NULL;
1070 sdhci_send_command(host, host->mrq->cmd);
1071 } else {
e538fbe8 1072
e89d456f
AW		 1073 /* Processed actual command. */
1074 if (host->data && host->data_early)
1075 sdhci_finish_data(host);
d129bceb 1076
e89d456f
AW		 1077 if (!host->cmd->data)
1078 tasklet_schedule(&host->finish_tasklet);
1079
1080 host->cmd = NULL;
1081 }
d129bceb
PO		 1082}
1083
1084static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1085{
c3ed3877 1086 int div = 0; /* Initialized for compiler warning */
df16219f 1087 int real_div = div, clk_mul = 1;
c3ed3877 1088 u16 clk = 0;
7cb2c76f 1089 unsigned long timeout;
d129bceb 1090
30832ab5 1091 if (clock && clock == host->clock)
d129bceb
PO		 1092 return;
1093
df16219f
GC		 1094 host->mmc->actual_clock = 0;
1095
8114634c
AV		 1096 if (host->ops->set_clock) {
1097 host->ops->set_clock(host, clock);
1098 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1099 return;
1100 }
1101
4e4141a5 1102 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1103
1104 if (clock == 0)
1105 goto out;
1106
85105c53 1107 if (host->version >= SDHCI_SPEC_300) {
c3ed3877
AN		 1108 /*
1109 * Check if the Host Controller supports Programmable Clock
1110 * Mode.
1111 */
1112 if (host->clk_mul) {
1113 u16 ctrl;
1114
1115 /*
1116 * We need to figure out whether the Host Driver needs
1117 * to select Programmable Clock Mode, or the value can
1118 * be set automatically by the Host Controller based on
1119 * the Preset Value registers.
1120 */
1121 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1122 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1123 for (div = 1; div <= 1024; div++) {
1124 if (((host->max_clk * host->clk_mul) /
1125 div) <= clock)
1126 break;
1127 }
1128 /*
1129 * Set Programmable Clock Mode in the Clock
1130 * Control register.
1131 */
1132 clk = SDHCI_PROG_CLOCK_MODE;
df16219f
GC		 1133 real_div = div;
1134 clk_mul = host->clk_mul;
c3ed3877
AN		 1135 div--;
1136 }
1137 } else {
1138 /* Version 3.00 divisors must be a multiple of 2. */
1139 if (host->max_clk <= clock)
1140 div = 1;
1141 else {
1142 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1143 div += 2) {
1144 if ((host->max_clk / div) <= clock)
1145 break;
1146 }
85105c53 1147 }
df16219f 1148 real_div = div;
c3ed3877 1149 div >>= 1;
85105c53
ZG		 1150 }
1151 } else {
1152 /* Version 2.00 divisors must be a power of 2. */
0397526d 1153 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1154 if ((host->max_clk / div) <= clock)
1155 break;
1156 }
df16219f 1157 real_div = div;
c3ed3877 1158 div >>= 1;
d129bceb 1159 }
d129bceb 1160
df16219f
GC		 1161 if (real_div)
1162 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1163
c3ed3877 1164 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1165 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1166 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1167 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1168 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1169
27f6cb16
CB		 1170 /* Wait max 20 ms */
1171 timeout = 20;
4e4141a5 1172 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1173 & SDHCI_CLOCK_INT_STABLE)) {
1174 if (timeout == 0) {
a3c76eb9 1175 pr_err("%s: Internal clock never "
acf1da45 1176 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1177 sdhci_dumpregs(host);
1178 return;
1179 }
7cb2c76f
PO		 1180 timeout--;
1181 mdelay(1);
1182 }
d129bceb
PO		 1183
1184 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1185 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1186
1187out:
1188 host->clock = clock;
1189}
1190
ceb6143b 1191static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
146ad66e 1192{
8364248a 1193 u8 pwr = 0;
146ad66e 1194
8364248a 1195 if (power != (unsigned short)-1) {
ae628903
PO		 1196 switch (1 << power) {
1197 case MMC_VDD_165_195:
1198 pwr = SDHCI_POWER_180;
1199 break;
1200 case MMC_VDD_29_30:
1201 case MMC_VDD_30_31:
1202 pwr = SDHCI_POWER_300;
1203 break;
1204 case MMC_VDD_32_33:
1205 case MMC_VDD_33_34:
1206 pwr = SDHCI_POWER_330;
1207 break;
1208 default:
1209 BUG();
1210 }
1211 }
1212
1213 if (host->pwr == pwr)
ceb6143b 1214 return -1;
146ad66e 1215
ae628903
PO		 1216 host->pwr = pwr;
1217
1218 if (pwr == 0) {
4e4141a5 1219 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ceb6143b 1220 return 0;
9e9dc5f2
DS		 1221 }
1222
1223 /*
1224 * Spec says that we should clear the power reg before setting
1225 * a new value. Some controllers don't seem to like this though.
1226 */
b8c86fc5 1227 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1228 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1229
e08c1694 1230 /*
c71f6512 1231 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1232 * and set turn on power at the same time, so set the voltage first.
1233 */
11a2f1b7 1234 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1235 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1236
ae628903 1237 pwr |= SDHCI_POWER_ON;
146ad66e 1238
ae628903 1239 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1240
1241 /*
1242 * Some controllers need an extra 10ms delay of 10ms before they
1243 * can apply clock after applying power
1244 */
11a2f1b7 1245 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1246 mdelay(10);
ceb6143b
AH		 1247
1248 return power;
146ad66e
PO		 1249}
1250
d129bceb
PO		 1251/*****************************************************************************\
1252 * *
1253 * MMC callbacks *
1254 * *
1255\*****************************************************************************/
1256
1257static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1258{
1259 struct sdhci_host *host;
68d1fb7e 1260 bool present;
d129bceb 1261 unsigned long flags;
473b095a 1262 u32 tuning_opcode;
d129bceb
PO		 1263
1264 host = mmc_priv(mmc);
1265
66fd8ad5
AH		 1266 sdhci_runtime_pm_get(host);
1267
d129bceb
PO		 1268 spin_lock_irqsave(&host->lock, flags);
1269
1270 WARN_ON(host->mrq != NULL);
1271
f9134319 1272#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1273 sdhci_activate_led(host);
2f730fec 1274#endif
e89d456f
AW		 1275
1276 /*
1277 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1278 * requests if Auto-CMD12 is enabled.
1279 */
1280 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1281 if (mrq->stop) {
1282 mrq->data->stop = NULL;
1283 mrq->stop = NULL;
1284 }
1285 }
d129bceb
PO		 1286
1287 host->mrq = mrq;
1288
68d1fb7e
AV		 1289 /* If polling, assume that the card is always present. */
1290 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1291 present = true;
1292 else
1293 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1294 SDHCI_CARD_PRESENT;
1295
1296 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1297 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1298 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1299 } else {
1300 u32 present_state;
1301
1302 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1303 /*
1304 * Check if the re-tuning timer has already expired and there
1305 * is no on-going data transfer. If so, we need to execute
1306 * tuning procedure before sending command.
1307 */
1308 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1309 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
473b095a
AL		 1310 /* eMMC uses cmd21 while sd and sdio use cmd19 */
1311 tuning_opcode = mmc->card->type == MMC_TYPE_MMC ?
1312 MMC_SEND_TUNING_BLOCK_HS200 :
1313 MMC_SEND_TUNING_BLOCK;
cf2b5eea 1314 spin_unlock_irqrestore(&host->lock, flags);
473b095a 1315 sdhci_execute_tuning(mmc, tuning_opcode);
cf2b5eea
AN		 1316 spin_lock_irqsave(&host->lock, flags);
1317
1318 /* Restore original mmc_request structure */
1319 host->mrq = mrq;
1320 }
1321
8edf6371 1322 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1323 sdhci_send_command(host, mrq->sbc);
1324 else
1325 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1326 }
d129bceb 1327
5f25a66f 1328 mmiowb();
d129bceb
PO		 1329 spin_unlock_irqrestore(&host->lock, flags);
1330}
1331
66fd8ad5 1332static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1333{
d129bceb 1334 unsigned long flags;
ceb6143b 1335 int vdd_bit = -1;
d129bceb
PO		 1336 u8 ctrl;
1337
d129bceb
PO		 1338 spin_lock_irqsave(&host->lock, flags);
1339
ceb6143b
AH		 1340 if (host->flags & SDHCI_DEVICE_DEAD) {
1341 spin_unlock_irqrestore(&host->lock, flags);
1342 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1343 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1344 return;
1345 }
1e72859e 1346
d129bceb
PO		 1347 /*
1348 * Reset the chip on each power off.
1349 * Should clear out any weird states.
1350 */
1351 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1352 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1353 sdhci_reinit(host);
d129bceb
PO		 1354 }
1355
1356 sdhci_set_clock(host, ios->clock);
1357
1358 if (ios->power_mode == MMC_POWER_OFF)
ceb6143b 1359 vdd_bit = sdhci_set_power(host, -1);
d129bceb 1360 else
ceb6143b
AH		 1361 vdd_bit = sdhci_set_power(host, ios->vdd);
1362
1363 if (host->vmmc && vdd_bit != -1) {
1364 spin_unlock_irqrestore(&host->lock, flags);
1365 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1366 spin_lock_irqsave(&host->lock, flags);
1367 }
d129bceb 1368
643a81ff
PR		 1369 if (host->ops->platform_send_init_74_clocks)
1370 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1371
15ec4461
PR		 1372 /*
1373 * If your platform has 8-bit width support but is not a v3 controller,
1374 * or if it requires special setup code, you should implement that in
1375 * platform_8bit_width().
1376 */
1377 if (host->ops->platform_8bit_width)
1378 host->ops->platform_8bit_width(host, ios->bus_width);
1379 else {
1380 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1381 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1382 ctrl &= ~SDHCI_CTRL_4BITBUS;
1383 if (host->version >= SDHCI_SPEC_300)
1384 ctrl |= SDHCI_CTRL_8BITBUS;
1385 } else {
1386 if (host->version >= SDHCI_SPEC_300)
1387 ctrl &= ~SDHCI_CTRL_8BITBUS;
1388 if (ios->bus_width == MMC_BUS_WIDTH_4)
1389 ctrl |= SDHCI_CTRL_4BITBUS;
1390 else
1391 ctrl &= ~SDHCI_CTRL_4BITBUS;
1392 }
1393 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1394 }
ae6d6c92 1395
15ec4461 1396 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1397
3ab9c8da
PR		 1398 if ((ios->timing == MMC_TIMING_SD_HS ||
1399 ios->timing == MMC_TIMING_MMC_HS)
1400 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1401 ctrl |= SDHCI_CTRL_HISPD;
1402 else
1403 ctrl &= ~SDHCI_CTRL_HISPD;
1404
d6d50a15 1405 if (host->version >= SDHCI_SPEC_300) {
49c468fc
AN		 1406 u16 clk, ctrl_2;
1407 unsigned int clock;
1408
1409 /* In case of UHS-I modes, set High Speed Enable */
069c9f14
G		 1410 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1411 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1412 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1413 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1414 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1415 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1416
1417 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1418 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1419 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1420 /*
1421 * We only need to set Driver Strength if the
1422 * preset value enable is not set.
1423 */
1424 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1425 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1426 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1427 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1428 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1429
1430 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1431 } else {
1432 /*
1433 * According to SDHC Spec v3.00, if the Preset Value
1434 * Enable in the Host Control 2 register is set, we
1435 * need to reset SD Clock Enable before changing High
1436 * Speed Enable to avoid generating clock gliches.
1437 */
758535c4
AN		 1438
1439 /* Reset SD Clock Enable */
1440 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1441 clk &= ~SDHCI_CLOCK_CARD_EN;
1442 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1443
1444 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1445
1446 /* Re-enable SD Clock */
1447 clock = host->clock;
1448 host->clock = 0;
1449 sdhci_set_clock(host, clock);
d6d50a15 1450 }
49c468fc 1451
49c468fc
AN		 1452
1453 /* Reset SD Clock Enable */
1454 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1455 clk &= ~SDHCI_CLOCK_CARD_EN;
1456 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1457
6322cdd0
PR		 1458 if (host->ops->set_uhs_signaling)
1459 host->ops->set_uhs_signaling(host, ios->timing);
1460 else {
1461 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1462 /* Select Bus Speed Mode for host */
1463 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
069c9f14
G		 1464 if (ios->timing == MMC_TIMING_MMC_HS200)
1465 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1466 else if (ios->timing == MMC_TIMING_UHS_SDR12)
6322cdd0
PR		 1467 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1468 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1469 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1470 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1471 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1472 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1473 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1474 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1475 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1476 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1477 }
49c468fc
AN		 1478
1479 /* Re-enable SD Clock */
1480 clock = host->clock;
1481 host->clock = 0;
1482 sdhci_set_clock(host, clock);
758535c4
AN		 1483 } else
1484 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1485
b8352260
LD		 1486 /*
1487 * Some (ENE) controllers go apeshit on some ios operation,
1488 * signalling timeout and CRC errors even on CMD0. Resetting
1489 * it on each ios seems to solve the problem.
1490 */
b8c86fc5 1491 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1492 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1493
5f25a66f 1494 mmiowb();
d129bceb
PO		 1495 spin_unlock_irqrestore(&host->lock, flags);
1496}
1497
66fd8ad5
AH		 1498static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1499{
1500 struct sdhci_host *host = mmc_priv(mmc);
1501
1502 sdhci_runtime_pm_get(host);
1503 sdhci_do_set_ios(host, ios);
1504 sdhci_runtime_pm_put(host);
1505}
1506
1507static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1508{
d129bceb 1509 unsigned long flags;
2dfb579c 1510 int is_readonly;
d129bceb 1511
d129bceb
PO		 1512 spin_lock_irqsave(&host->lock, flags);
1513
1e72859e 1514 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1515 is_readonly = 0;
1516 else if (host->ops->get_ro)
1517 is_readonly = host->ops->get_ro(host);
1e72859e 1518 else
2dfb579c
WS		 1519 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1520 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1521
1522 spin_unlock_irqrestore(&host->lock, flags);
1523
2dfb579c
WS		 1524 /* This quirk needs to be replaced by a callback-function later */
1525 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1526 !is_readonly : is_readonly;
d129bceb
PO		 1527}
1528
82b0e23a
TI		 1529#define SAMPLE_COUNT 5
1530
66fd8ad5 1531static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1532{
82b0e23a
TI		 1533 int i, ro_count;
1534
82b0e23a 1535 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1536 return sdhci_check_ro(host);
82b0e23a
TI		 1537
1538 ro_count = 0;
1539 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1540 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1541 if (++ro_count > SAMPLE_COUNT / 2)
1542 return 1;
1543 }
1544 msleep(30);
1545 }
1546 return 0;
1547}
1548
20758b66
AH		 1549static void sdhci_hw_reset(struct mmc_host *mmc)
1550{
1551 struct sdhci_host *host = mmc_priv(mmc);
1552
1553 if (host->ops && host->ops->hw_reset)
1554 host->ops->hw_reset(host);
1555}
1556
66fd8ad5 1557static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1558{
66fd8ad5
AH		 1559 struct sdhci_host *host = mmc_priv(mmc);
1560 int ret;
f75979b7 1561
66fd8ad5
AH		 1562 sdhci_runtime_pm_get(host);
1563 ret = sdhci_do_get_ro(host);
1564 sdhci_runtime_pm_put(host);
1565 return ret;
1566}
f75979b7 1567
66fd8ad5
AH		 1568static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1569{
1e72859e
PO		 1570 if (host->flags & SDHCI_DEVICE_DEAD)
1571 goto out;
1572
66fd8ad5
AH		 1573 if (enable)
1574 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1575 else
1576 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1577
1578 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1579 if (host->runtime_suspended)
1580 goto out;
1581
f75979b7 1582 if (enable)
7260cf5e
AV		 1583 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1584 else
1585 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1586out:
f75979b7 1587 mmiowb();
66fd8ad5
AH		 1588}
1589
1590static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1591{
1592 struct sdhci_host *host = mmc_priv(mmc);
1593 unsigned long flags;
f75979b7 1594
66fd8ad5
AH		 1595 spin_lock_irqsave(&host->lock, flags);
1596 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1597 spin_unlock_irqrestore(&host->lock, flags);
1598}
1599
66fd8ad5
AH		 1600static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1601 struct mmc_ios *ios)
f2119df6 1602{
f2119df6
AN		 1603 u8 pwr;
1604 u16 clk, ctrl;
1605 u32 present_state;
1606
f2119df6
AN		 1607 /*
1608 * Signal Voltage Switching is only applicable for Host Controllers
1609 * v3.00 and above.
1610 */
1611 if (host->version < SDHCI_SPEC_300)
1612 return 0;
1613
1614 /*
1615 * We first check whether the request is to set signalling voltage
1616 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1617 */
1618 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1619 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1620 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1621 ctrl &= ~SDHCI_CTRL_VDD_180;
1622 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1623
1624 /* Wait for 5ms */
1625 usleep_range(5000, 5500);
1626
1627 /* 3.3V regulator output should be stable within 5 ms */
1628 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1629 if (!(ctrl & SDHCI_CTRL_VDD_180))
1630 return 0;
1631 else {
a3c76eb9 1632 pr_info(DRIVER_NAME ": Switching to 3.3V "
f2119df6
AN		 1633 "signalling voltage failed\n");
1634 return -EIO;
1635 }
1636 } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1637 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1638 /* Stop SDCLK */
1639 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1640 clk &= ~SDHCI_CLOCK_CARD_EN;
1641 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1642
1643 /* Check whether DAT[3:0] is 0000 */
1644 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1645 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1646 SDHCI_DATA_LVL_SHIFT)) {
1647 /*
1648 * Enable 1.8V Signal Enable in the Host Control2
1649 * register
1650 */
1651 ctrl |= SDHCI_CTRL_VDD_180;
1652 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1653
1654 /* Wait for 5ms */
1655 usleep_range(5000, 5500);
1656
1657 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1658 if (ctrl & SDHCI_CTRL_VDD_180) {
1659 /* Provide SDCLK again and wait for 1ms*/
1660 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1661 clk |= SDHCI_CLOCK_CARD_EN;
1662 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1663 usleep_range(1000, 1500);
1664
1665 /*
1666 * If DAT[3:0] level is 1111b, then the card
1667 * was successfully switched to 1.8V signaling.
1668 */
1669 present_state = sdhci_readl(host,
1670 SDHCI_PRESENT_STATE);
1671 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1672 SDHCI_DATA_LVL_MASK)
1673 return 0;
1674 }
1675 }
1676
1677 /*
1678 * If we are here, that means the switch to 1.8V signaling
1679 * failed. We power cycle the card, and retry initialization
1680 * sequence by setting S18R to 0.
1681 */
1682 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1683 pwr &= ~SDHCI_POWER_ON;
1684 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
38cfc2f7
PR		 1685 if (host->vmmc)
1686 regulator_disable(host->vmmc);
f2119df6
AN		 1687
1688 /* Wait for 1ms as per the spec */
1689 usleep_range(1000, 1500);
1690 pwr |= SDHCI_POWER_ON;
1691 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
38cfc2f7
PR		 1692 if (host->vmmc)
1693 regulator_enable(host->vmmc);
f2119df6 1694
a3c76eb9 1695 pr_info(DRIVER_NAME ": Switching to 1.8V signalling "
f2119df6
AN		 1696 "voltage failed, retrying with S18R set to 0\n");
1697 return -EAGAIN;
1698 } else
1699 /* No signal voltage switch required */
1700 return 0;
1701}
1702
66fd8ad5
AH		 1703static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1704 struct mmc_ios *ios)
1705{
1706 struct sdhci_host *host = mmc_priv(mmc);
1707 int err;
1708
1709 if (host->version < SDHCI_SPEC_300)
1710 return 0;
1711 sdhci_runtime_pm_get(host);
1712 err = sdhci_do_start_signal_voltage_switch(host, ios);
1713 sdhci_runtime_pm_put(host);
1714 return err;
1715}
1716
069c9f14 1717static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25
AN		 1718{
1719 struct sdhci_host *host;
1720 u16 ctrl;
1721 u32 ier;
1722 int tuning_loop_counter = MAX_TUNING_LOOP;
1723 unsigned long timeout;
1724 int err = 0;
069c9f14 1725 bool requires_tuning_nonuhs = false;
b513ea25
AN		 1726
1727 host = mmc_priv(mmc);
1728
66fd8ad5 1729 sdhci_runtime_pm_get(host);
b513ea25
AN		 1730 disable_irq(host->irq);
1731 spin_lock(&host->lock);
1732
1733 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1734
1735 /*
069c9f14
G		 1736 * The Host Controller needs tuning only in case of SDR104 mode
1737 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1738 * Capabilities register.
069c9f14
G		 1739 * If the Host Controller supports the HS200 mode then the
1740 * tuning function has to be executed.
b513ea25 1741 */
069c9f14
G		 1742 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1743 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1744 host->flags & SDHCI_HS200_NEEDS_TUNING))
1745 requires_tuning_nonuhs = true;
1746
b513ea25 1747 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
069c9f14 1748 requires_tuning_nonuhs)
b513ea25
AN		 1749 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1750 else {
1751 spin_unlock(&host->lock);
1752 enable_irq(host->irq);
66fd8ad5 1753 sdhci_runtime_pm_put(host);
b513ea25
AN		 1754 return 0;
1755 }
1756
1757 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1758
1759 /*
1760 * As per the Host Controller spec v3.00, tuning command
1761 * generates Buffer Read Ready interrupt, so enable that.
1762 *
1763 * Note: The spec clearly says that when tuning sequence
1764 * is being performed, the controller does not generate
1765 * interrupts other than Buffer Read Ready interrupt. But
1766 * to make sure we don't hit a controller bug, we _only_
1767 * enable Buffer Read Ready interrupt here.
1768 */
1769 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1770 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1771
1772 /*
1773 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1774 * of loops reaches 40 times or a timeout of 150ms occurs.
1775 */
1776 timeout = 150;
1777 do {
1778 struct mmc_command cmd = {0};
66fd8ad5 1779 struct mmc_request mrq = {NULL};
b513ea25
AN		 1780
1781 if (!tuning_loop_counter && !timeout)
1782 break;
1783
069c9f14 1784 cmd.opcode = opcode;
b513ea25
AN		 1785 cmd.arg = 0;
1786 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1787 cmd.retries = 0;
1788 cmd.data = NULL;
1789 cmd.error = 0;
1790
1791 mrq.cmd = &cmd;
1792 host->mrq = &mrq;
1793
1794 /*
1795 * In response to CMD19, the card sends 64 bytes of tuning
1796 * block to the Host Controller. So we set the block size
1797 * to 64 here.
1798 */
069c9f14
G		 1799 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1800 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1801 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1802 SDHCI_BLOCK_SIZE);
1803 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1804 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1805 SDHCI_BLOCK_SIZE);
1806 } else {
1807 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1808 SDHCI_BLOCK_SIZE);
1809 }
b513ea25
AN		 1810
1811 /*
1812 * The tuning block is sent by the card to the host controller.
1813 * So we set the TRNS_READ bit in the Transfer Mode register.
1814 * This also takes care of setting DMA Enable and Multi Block
1815 * Select in the same register to 0.
1816 */
1817 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1818
1819 sdhci_send_command(host, &cmd);
1820
1821 host->cmd = NULL;
1822 host->mrq = NULL;
1823
1824 spin_unlock(&host->lock);
1825 enable_irq(host->irq);
1826
1827 /* Wait for Buffer Read Ready interrupt */
1828 wait_event_interruptible_timeout(host->buf_ready_int,
1829 (host->tuning_done == 1),
1830 msecs_to_jiffies(50));
1831 disable_irq(host->irq);
1832 spin_lock(&host->lock);
1833
1834 if (!host->tuning_done) {
a3c76eb9 1835 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1836 "Buffer Read Ready interrupt during tuning "
1837 "procedure, falling back to fixed sampling "
1838 "clock\n");
1839 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1840 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1841 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1842 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1843
1844 err = -EIO;
1845 goto out;
1846 }
1847
1848 host->tuning_done = 0;
1849
1850 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1851 tuning_loop_counter--;
1852 timeout--;
1853 mdelay(1);
1854 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1855
1856 /*
1857 * The Host Driver has exhausted the maximum number of loops allowed,
1858 * so use fixed sampling frequency.
1859 */
1860 if (!tuning_loop_counter || !timeout) {
1861 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1862 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1863 } else {
1864 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 1865 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 1866 " failed, falling back to fixed sampling"
1867 " clock\n");
1868 err = -EIO;
1869 }
1870 }
1871
1872out:
cf2b5eea
AN		 1873 /*
1874 * If this is the very first time we are here, we start the retuning
1875 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1876 * flag won't be set, we check this condition before actually starting
1877 * the timer.
1878 */
1879 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1880 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
973905fe 1881 host->flags |= SDHCI_USING_RETUNING_TIMER;
cf2b5eea
AN		 1882 mod_timer(&host->tuning_timer, jiffies +
1883 host->tuning_count * HZ);
1884 /* Tuning mode 1 limits the maximum data length to 4MB */
1885 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1886 } else {
1887 host->flags &= ~SDHCI_NEEDS_RETUNING;
1888 /* Reload the new initial value for timer */
1889 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1890 mod_timer(&host->tuning_timer, jiffies +
1891 host->tuning_count * HZ);
1892 }
1893
1894 /*
1895 * In case tuning fails, host controllers which support re-tuning can
1896 * try tuning again at a later time, when the re-tuning timer expires.
1897 * So for these controllers, we return 0. Since there might be other
1898 * controllers who do not have this capability, we return error for
973905fe
AL		 1899 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
1900 * a retuning timer to do the retuning for the card.
cf2b5eea 1901 */
973905fe 1902 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 1903 err = 0;
1904
b513ea25
AN		 1905 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1906 spin_unlock(&host->lock);
1907 enable_irq(host->irq);
66fd8ad5 1908 sdhci_runtime_pm_put(host);
b513ea25
AN		 1909
1910 return err;
1911}
1912
66fd8ad5 1913static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 1914{
4d55c5a1
AN		 1915 u16 ctrl;
1916 unsigned long flags;
1917
4d55c5a1
AN		 1918 /* Host Controller v3.00 defines preset value registers */
1919 if (host->version < SDHCI_SPEC_300)
1920 return;
1921
1922 spin_lock_irqsave(&host->lock, flags);
1923
1924 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1925
1926 /*
1927 * We only enable or disable Preset Value if they are not already
1928 * enabled or disabled respectively. Otherwise, we bail out.
1929 */
1930 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1931 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1932 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 1933 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 1934 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1935 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1936 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 1937 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1
AN		 1938 }
1939
1940 spin_unlock_irqrestore(&host->lock, flags);
1941}
1942
66fd8ad5
AH		 1943static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1944{
1945 struct sdhci_host *host = mmc_priv(mmc);
1946
1947 sdhci_runtime_pm_get(host);
1948 sdhci_do_enable_preset_value(host, enable);
1949 sdhci_runtime_pm_put(host);
1950}
1951
ab7aefd0 1952static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1953 .request = sdhci_request,
1954 .set_ios = sdhci_set_ios,
1955 .get_ro = sdhci_get_ro,
20758b66 1956 .hw_reset = sdhci_hw_reset,
f75979b7 1957 .enable_sdio_irq = sdhci_enable_sdio_irq,
f2119df6 1958 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b513ea25 1959 .execute_tuning = sdhci_execute_tuning,
4d55c5a1 1960 .enable_preset_value = sdhci_enable_preset_value,
d129bceb
PO		 1961};
1962
1963/*****************************************************************************\
1964 * *
1965 * Tasklets *
1966 * *
1967\*****************************************************************************/
1968
1969static void sdhci_tasklet_card(unsigned long param)
1970{
1971 struct sdhci_host *host;
1972 unsigned long flags;
1973
1974 host = (struct sdhci_host*)param;
1975
1976 spin_lock_irqsave(&host->lock, flags);
1977
66fd8ad5
AH		 1978 /* Check host->mrq first in case we are runtime suspended */
1979 if (host->mrq &&
1980 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
a3c76eb9 1981 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 1982 mmc_hostname(host->mmc));
a3c76eb9 1983 pr_err("%s: Resetting controller.\n",
66fd8ad5 1984 mmc_hostname(host->mmc));
d129bceb 1985
66fd8ad5
AH		 1986 sdhci_reset(host, SDHCI_RESET_CMD);
1987 sdhci_reset(host, SDHCI_RESET_DATA);
d129bceb 1988
66fd8ad5
AH		 1989 host->mrq->cmd->error = -ENOMEDIUM;
1990 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 1991 }
1992
1993 spin_unlock_irqrestore(&host->lock, flags);
1994
04cf585d 1995 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 1996}
1997
1998static void sdhci_tasklet_finish(unsigned long param)
1999{
2000 struct sdhci_host *host;
2001 unsigned long flags;
2002 struct mmc_request *mrq;
2003
2004 host = (struct sdhci_host*)param;
2005
66fd8ad5
AH		 2006 spin_lock_irqsave(&host->lock, flags);
2007
0c9c99a7
CB		 2008 /*
2009 * If this tasklet gets rescheduled while running, it will
2010 * be run again afterwards but without any active request.
2011 */
66fd8ad5
AH		 2012 if (!host->mrq) {
2013 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2014 return;
66fd8ad5 2015 }
d129bceb
PO		 2016
2017 del_timer(&host->timer);
2018
2019 mrq = host->mrq;
2020
d129bceb
PO		 2021 /*
2022 * The controller needs a reset of internal state machines
2023 * upon error conditions.
2024 */
1e72859e 2025 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2026 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 2027 (mrq->data && (mrq->data->error ||
2028 (mrq->data->stop && mrq->data->stop->error))) ||
2029 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2030
2031 /* Some controllers need this kick or reset won't work here */
b8c86fc5 2032 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 2033 unsigned int clock;
2034
2035 /* This is to force an update */
2036 clock = host->clock;
2037 host->clock = 0;
2038 sdhci_set_clock(host, clock);
2039 }
2040
2041 /* Spec says we should do both at the same time, but Ricoh
2042 controllers do not like that. */
d129bceb
PO		 2043 sdhci_reset(host, SDHCI_RESET_CMD);
2044 sdhci_reset(host, SDHCI_RESET_DATA);
2045 }
2046
2047 host->mrq = NULL;
2048 host->cmd = NULL;
2049 host->data = NULL;
2050
f9134319 2051#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2052 sdhci_deactivate_led(host);
2f730fec 2053#endif
d129bceb 2054
5f25a66f 2055 mmiowb();
d129bceb
PO		 2056 spin_unlock_irqrestore(&host->lock, flags);
2057
2058 mmc_request_done(host->mmc, mrq);
66fd8ad5 2059 sdhci_runtime_pm_put(host);
d129bceb
PO		 2060}
2061
2062static void sdhci_timeout_timer(unsigned long data)
2063{
2064 struct sdhci_host *host;
2065 unsigned long flags;
2066
2067 host = (struct sdhci_host*)data;
2068
2069 spin_lock_irqsave(&host->lock, flags);
2070
2071 if (host->mrq) {
a3c76eb9 2072 pr_err("%s: Timeout waiting for hardware "
acf1da45 2073 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2074 sdhci_dumpregs(host);
2075
2076 if (host->data) {
17b0429d 2077 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2078 sdhci_finish_data(host);
2079 } else {
2080 if (host->cmd)
17b0429d 2081 host->cmd->error = -ETIMEDOUT;
d129bceb 2082 else
17b0429d 2083 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2084
2085 tasklet_schedule(&host->finish_tasklet);
2086 }
2087 }
2088
5f25a66f 2089 mmiowb();
d129bceb
PO		 2090 spin_unlock_irqrestore(&host->lock, flags);
2091}
2092
cf2b5eea
AN		 2093static void sdhci_tuning_timer(unsigned long data)
2094{
2095 struct sdhci_host *host;
2096 unsigned long flags;
2097
2098 host = (struct sdhci_host *)data;
2099
2100 spin_lock_irqsave(&host->lock, flags);
2101
2102 host->flags |= SDHCI_NEEDS_RETUNING;
2103
2104 spin_unlock_irqrestore(&host->lock, flags);
2105}
2106
d129bceb
PO		 2107/*****************************************************************************\
2108 * *
2109 * Interrupt handling *
2110 * *
2111\*****************************************************************************/
2112
2113static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2114{
2115 BUG_ON(intmask == 0);
2116
2117 if (!host->cmd) {
a3c76eb9 2118 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2119 "though no command operation was in progress.\n",
2120 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2121 sdhci_dumpregs(host);
2122 return;
2123 }
2124
43b58b36 2125 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2126 host->cmd->error = -ETIMEDOUT;
2127 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2128 SDHCI_INT_INDEX))
2129 host->cmd->error = -EILSEQ;
43b58b36 2130
e809517f 2131 if (host->cmd->error) {
d129bceb 2132 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2133 return;
2134 }
2135
2136 /*
2137 * The host can send and interrupt when the busy state has
2138 * ended, allowing us to wait without wasting CPU cycles.
2139 * Unfortunately this is overloaded on the "data complete"
2140 * interrupt, so we need to take some care when handling
2141 * it.
2142 *
2143 * Note: The 1.0 specification is a bit ambiguous about this
2144 * feature so there might be some problems with older
2145 * controllers.
2146 */
2147 if (host->cmd->flags & MMC_RSP_BUSY) {
2148 if (host->cmd->data)
2149 DBG("Cannot wait for busy signal when also "
2150 "doing a data transfer");
f945405c 2151 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2152 return;
f945405c
BD		 2153
2154 /* The controller does not support the end-of-busy IRQ,
2155 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2156 }
2157
2158 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2159 sdhci_finish_command(host);
d129bceb
PO		 2160}
2161
0957c333 2162#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2163static void sdhci_show_adma_error(struct sdhci_host *host)
2164{
2165 const char *name = mmc_hostname(host->mmc);
2166 u8 *desc = host->adma_desc;
2167 __le32 *dma;
2168 __le16 *len;
2169 u8 attr;
2170
2171 sdhci_dumpregs(host);
2172
2173 while (true) {
2174 dma = (__le32 *)(desc + 4);
2175 len = (__le16 *)(desc + 2);
2176 attr = *desc;
2177
2178 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2179 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2180
2181 desc += 8;
2182
2183 if (attr & 2)
2184 break;
2185 }
2186}
2187#else
2188static void sdhci_show_adma_error(struct sdhci_host *host) { }
2189#endif
2190
d129bceb
PO		 2191static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2192{
069c9f14 2193 u32 command;
d129bceb
PO		 2194 BUG_ON(intmask == 0);
2195
b513ea25
AN		 2196 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2197 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2198 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2199 if (command == MMC_SEND_TUNING_BLOCK ||
2200 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2201 host->tuning_done = 1;
2202 wake_up(&host->buf_ready_int);
2203 return;
2204 }
2205 }
2206
d129bceb
PO		 2207 if (!host->data) {
2208 /*
e809517f
PO		 2209 * The "data complete" interrupt is also used to
2210 * indicate that a busy state has ended. See comment
2211 * above in sdhci_cmd_irq().
d129bceb 2212 */
e809517f
PO		 2213 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2214 if (intmask & SDHCI_INT_DATA_END) {
2215 sdhci_finish_command(host);
2216 return;
2217 }
2218 }
d129bceb 2219
a3c76eb9 2220 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2221 "though no data operation was in progress.\n",
2222 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2223 sdhci_dumpregs(host);
2224
2225 return;
2226 }
2227
2228 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2229 host->data->error = -ETIMEDOUT;
22113efd
AL		 2230 else if (intmask & SDHCI_INT_DATA_END_BIT)
2231 host->data->error = -EILSEQ;
2232 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2233 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2234 != MMC_BUS_TEST_R)
17b0429d 2235 host->data->error = -EILSEQ;
6882a8c0 2236 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2237 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2238 sdhci_show_adma_error(host);
2134a922 2239 host->data->error = -EIO;
6882a8c0 2240 }
d129bceb 2241
17b0429d 2242 if (host->data->error)
d129bceb
PO		 2243 sdhci_finish_data(host);
2244 else {
a406f5a3 2245 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2246 sdhci_transfer_pio(host);
2247
6ba736a1
PO		 2248 /*
2249 * We currently don't do anything fancy with DMA
2250 * boundaries, but as we can't disable the feature
2251 * we need to at least restart the transfer.
f6a03cbf
MV		 2252 *
2253 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2254 * should return a valid address to continue from, but as
2255 * some controllers are faulty, don't trust them.
6ba736a1 2256 */
f6a03cbf
MV		 2257 if (intmask & SDHCI_INT_DMA_END) {
2258 u32 dmastart, dmanow;
2259 dmastart = sg_dma_address(host->data->sg);
2260 dmanow = dmastart + host->data->bytes_xfered;
2261 /*
2262 * Force update to the next DMA block boundary.
2263 */
2264 dmanow = (dmanow &
2265 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2266 SDHCI_DEFAULT_BOUNDARY_SIZE;
2267 host->data->bytes_xfered = dmanow - dmastart;
2268 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2269 " next 0x%08x\n",
2270 mmc_hostname(host->mmc), dmastart,
2271 host->data->bytes_xfered, dmanow);
2272 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2273 }
6ba736a1 2274
e538fbe8
PO		 2275 if (intmask & SDHCI_INT_DATA_END) {
2276 if (host->cmd) {
2277 /*
2278 * Data managed to finish before the
2279 * command completed. Make sure we do
2280 * things in the proper order.
2281 */
2282 host->data_early = 1;
2283 } else {
2284 sdhci_finish_data(host);
2285 }
2286 }
d129bceb
PO		 2287 }
2288}
2289
7d12e780 2290static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 2291{
2292 irqreturn_t result;
66fd8ad5 2293 struct sdhci_host *host = dev_id;
6379b237
AS		 2294 u32 intmask, unexpected = 0;
2295 int cardint = 0, max_loops = 16;
d129bceb
PO		 2296
2297 spin_lock(&host->lock);
2298
66fd8ad5
AH		 2299 if (host->runtime_suspended) {
2300 spin_unlock(&host->lock);
a3c76eb9 2301 pr_warning("%s: got irq while runtime suspended\n",
66fd8ad5
AH		 2302 mmc_hostname(host->mmc));
2303 return IRQ_HANDLED;
2304 }
2305
4e4141a5 2306 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 2307
62df67a5 2308 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2309 result = IRQ_NONE;
2310 goto out;
2311 }
2312
6379b237 2313again:
b69c9058
PO		 2314 DBG("*** %s got interrupt: 0x%08x\n",
2315 mmc_hostname(host->mmc), intmask);
d129bceb 2316
3192a28f 2317 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d25928d1
SG		 2318 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2319 SDHCI_CARD_PRESENT;
2320
2321 /*
2322 * There is a observation on i.mx esdhc. INSERT bit will be
2323 * immediately set again when it gets cleared, if a card is
2324 * inserted. We have to mask the irq to prevent interrupt
2325 * storm which will freeze the system. And the REMOVE gets
2326 * the same situation.
2327 *
2328 * More testing are needed here to ensure it works for other
2329 * platforms though.
2330 */
2331 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2332 SDHCI_INT_CARD_REMOVE);
2333 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2334 SDHCI_INT_CARD_INSERT);
2335
4e4141a5 2336 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
d25928d1
SG		 2337 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2338 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 2339 tasklet_schedule(&host->card_tasklet);
3192a28f 2340 }
d129bceb 2341
3192a28f 2342 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 2343 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2344 SDHCI_INT_STATUS);
3192a28f 2345 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 2346 }
2347
2348 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 2349 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2350 SDHCI_INT_STATUS);
3192a28f 2351 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 2352 }
2353
2354 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2355
964f9ce2
PO		 2356 intmask &= ~SDHCI_INT_ERROR;
2357
d129bceb 2358 if (intmask & SDHCI_INT_BUS_POWER) {
a3c76eb9 2359 pr_err("%s: Card is consuming too much power!\n",
d129bceb 2360 mmc_hostname(host->mmc));
4e4141a5 2361 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 2362 }
2363
9d26a5d3 2364 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 2365
f75979b7
PO		 2366 if (intmask & SDHCI_INT_CARD_INT)
2367 cardint = 1;
2368
2369 intmask &= ~SDHCI_INT_CARD_INT;
2370
3192a28f 2371 if (intmask) {
6379b237 2372 unexpected |= intmask;
4e4141a5 2373 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 2374 }
d129bceb
PO		 2375
2376 result = IRQ_HANDLED;
2377
6379b237
AS		 2378 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2379 if (intmask && --max_loops)
2380 goto again;
d129bceb
PO		 2381out:
2382 spin_unlock(&host->lock);
2383
6379b237
AS		 2384 if (unexpected) {
2385 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2386 mmc_hostname(host->mmc), unexpected);
2387 sdhci_dumpregs(host);
2388 }
f75979b7
PO		 2389 /*
2390 * We have to delay this as it calls back into the driver.
2391 */
2392 if (cardint)
2393 mmc_signal_sdio_irq(host->mmc);
2394
d129bceb
PO		 2395 return result;
2396}
2397
2398/*****************************************************************************\
2399 * *
2400 * Suspend/resume *
2401 * *
2402\*****************************************************************************/
2403
2404#ifdef CONFIG_PM
2405
29495aa0 2406int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2407{
b8c86fc5 2408 int ret;
a715dfc7 2409
a1b13b4e
CB		 2410 if (host->ops->platform_suspend)
2411 host->ops->platform_suspend(host);
2412
7260cf5e
AV		 2413 sdhci_disable_card_detection(host);
2414
cf2b5eea 2415 /* Disable tuning since we are suspending */
973905fe 2416 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2417 del_timer_sync(&host->tuning_timer);
cf2b5eea 2418 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2419 }
2420
1a13f8fa 2421 ret = mmc_suspend_host(host->mmc);
38a60ea2 2422 if (ret) {
973905fe 2423 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
38a60ea2
AL		 2424 host->flags |= SDHCI_NEEDS_RETUNING;
2425 mod_timer(&host->tuning_timer, jiffies +
2426 host->tuning_count * HZ);
2427 }
2428
2429 sdhci_enable_card_detection(host);
2430
b8c86fc5 2431 return ret;
38a60ea2 2432 }
a715dfc7 2433
b8c86fc5 2434 free_irq(host->irq, host);
d129bceb 2435
9bea3c85 2436 return ret;
d129bceb
PO		 2437}
2438
b8c86fc5 2439EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2440
b8c86fc5
PO		 2441int sdhci_resume_host(struct sdhci_host *host)
2442{
2443 int ret;
d129bceb 2444
a13abc7b 2445 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2446 if (host->ops->enable_dma)
2447 host->ops->enable_dma(host);
2448 }
d129bceb 2449
b8c86fc5
PO		 2450 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2451 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 2452 if (ret)
2453 return ret;
d129bceb 2454
6308d290
AH		 2455 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2456 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2457 /* Card keeps power but host controller does not */
2458 sdhci_init(host, 0);
2459 host->pwr = 0;
2460 host->clock = 0;
2461 sdhci_do_set_ios(host, &host->mmc->ios);
2462 } else {
2463 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2464 mmiowb();
2465 }
b8c86fc5
PO		 2466
2467 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 2468 sdhci_enable_card_detection(host);
2469
a1b13b4e
CB		 2470 if (host->ops->platform_resume)
2471 host->ops->platform_resume(host);
2472
cf2b5eea 2473 /* Set the re-tuning expiration flag */
973905fe 2474 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2475 host->flags |= SDHCI_NEEDS_RETUNING;
2476
2f4cbb3d 2477 return ret;
d129bceb
PO		 2478}
2479
b8c86fc5 2480EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb 2481
5f619704
DD		 2482void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2483{
2484 u8 val;
2485 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2486 val |= SDHCI_WAKE_ON_INT;
2487 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2488}
2489
2490EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2491
d129bceb
PO		 2492#endif /* CONFIG_PM */
2493
66fd8ad5
AH		 2494#ifdef CONFIG_PM_RUNTIME
2495
2496static int sdhci_runtime_pm_get(struct sdhci_host *host)
2497{
2498 return pm_runtime_get_sync(host->mmc->parent);
2499}
2500
2501static int sdhci_runtime_pm_put(struct sdhci_host *host)
2502{
2503 pm_runtime_mark_last_busy(host->mmc->parent);
2504 return pm_runtime_put_autosuspend(host->mmc->parent);
2505}
2506
2507int sdhci_runtime_suspend_host(struct sdhci_host *host)
2508{
2509 unsigned long flags;
2510 int ret = 0;
2511
2512 /* Disable tuning since we are suspending */
973905fe 2513 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2514 del_timer_sync(&host->tuning_timer);
2515 host->flags &= ~SDHCI_NEEDS_RETUNING;
2516 }
2517
2518 spin_lock_irqsave(&host->lock, flags);
2519 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2520 spin_unlock_irqrestore(&host->lock, flags);
2521
2522 synchronize_irq(host->irq);
2523
2524 spin_lock_irqsave(&host->lock, flags);
2525 host->runtime_suspended = true;
2526 spin_unlock_irqrestore(&host->lock, flags);
2527
2528 return ret;
2529}
2530EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2531
2532int sdhci_runtime_resume_host(struct sdhci_host *host)
2533{
2534 unsigned long flags;
2535 int ret = 0, host_flags = host->flags;
2536
2537 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2538 if (host->ops->enable_dma)
2539 host->ops->enable_dma(host);
2540 }
2541
2542 sdhci_init(host, 0);
2543
2544 /* Force clock and power re-program */
2545 host->pwr = 0;
2546 host->clock = 0;
2547 sdhci_do_set_ios(host, &host->mmc->ios);
2548
2549 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2550 if (host_flags & SDHCI_PV_ENABLED)
2551 sdhci_do_enable_preset_value(host, true);
2552
2553 /* Set the re-tuning expiration flag */
973905fe 2554 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2555 host->flags |= SDHCI_NEEDS_RETUNING;
2556
2557 spin_lock_irqsave(&host->lock, flags);
2558
2559 host->runtime_suspended = false;
2560
2561 /* Enable SDIO IRQ */
2562 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2563 sdhci_enable_sdio_irq_nolock(host, true);
2564
2565 /* Enable Card Detection */
2566 sdhci_enable_card_detection(host);
2567
2568 spin_unlock_irqrestore(&host->lock, flags);
2569
2570 return ret;
2571}
2572EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2573
2574#endif
2575
d129bceb
PO		 2576/*****************************************************************************\
2577 * *
b8c86fc5 2578 * Device allocation/registration *
d129bceb
PO		 2579 * *
2580\*****************************************************************************/
2581
b8c86fc5
PO		 2582struct sdhci_host *sdhci_alloc_host(struct device *dev,
2583 size_t priv_size)
d129bceb 2584{
d129bceb
PO		 2585 struct mmc_host *mmc;
2586 struct sdhci_host *host;
2587
b8c86fc5 2588 WARN_ON(dev == NULL);
d129bceb 2589
b8c86fc5 2590 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2591 if (!mmc)
b8c86fc5 2592 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2593
2594 host = mmc_priv(mmc);
2595 host->mmc = mmc;
2596
b8c86fc5
PO		 2597 return host;
2598}
8a4da143 2599
b8c86fc5 2600EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2601
b8c86fc5
PO		 2602int sdhci_add_host(struct sdhci_host *host)
2603{
2604 struct mmc_host *mmc;
bd6a8c30 2605 u32 caps[2] = {0, 0};
f2119df6
AN		 2606 u32 max_current_caps;
2607 unsigned int ocr_avail;
b8c86fc5 2608 int ret;
d129bceb 2609
b8c86fc5
PO		 2610 WARN_ON(host == NULL);
2611 if (host == NULL)
2612 return -EINVAL;
d129bceb 2613
b8c86fc5 2614 mmc = host->mmc;
d129bceb 2615
b8c86fc5
PO		 2616 if (debug_quirks)
2617 host->quirks = debug_quirks;
66fd8ad5
AH		 2618 if (debug_quirks2)
2619 host->quirks2 = debug_quirks2;
d129bceb 2620
d96649ed
PO		 2621 sdhci_reset(host, SDHCI_RESET_ALL);
2622
4e4141a5 2623 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2624 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2625 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2626 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2627 pr_err("%s: Unknown controller version (%d). "
b69c9058 2628 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2629 host->version);
4a965505
PO		 2630 }
2631
f2119df6 2632 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2633 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2634
bd6a8c30
PR		 2635 if (host->version >= SDHCI_SPEC_300)
2636 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2637 host->caps1 :
2638 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2639
b8c86fc5 2640 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2641 host->flags |= SDHCI_USE_SDMA;
f2119df6 2642 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2643 DBG("Controller doesn't have SDMA capability\n");
67435274 2644 else
a13abc7b 2645 host->flags |= SDHCI_USE_SDMA;
d129bceb 2646
b8c86fc5 2647 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2648 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2649 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2650 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2651 }
2652
f2119df6
AN		 2653 if ((host->version >= SDHCI_SPEC_200) &&
2654 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2655 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2656
2657 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2658 (host->flags & SDHCI_USE_ADMA)) {
2659 DBG("Disabling ADMA as it is marked broken\n");
2660 host->flags &= ~SDHCI_USE_ADMA;
2661 }
2662
a13abc7b 2663 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2664 if (host->ops->enable_dma) {
2665 if (host->ops->enable_dma(host)) {
a3c76eb9 2666 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2667 "available. Falling back to PIO.\n",
2668 mmc_hostname(mmc));
a13abc7b
RR		 2669 host->flags &=
2670 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2671 }
d129bceb
PO		 2672 }
2673 }
2674
2134a922
PO		 2675 if (host->flags & SDHCI_USE_ADMA) {
2676 /*
2677 * We need to allocate descriptors for all sg entries
2678 * (128) and potentially one alignment transfer for
2679 * each of those entries.
2680 */
2681 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2682 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2683 if (!host->adma_desc || !host->align_buffer) {
2684 kfree(host->adma_desc);
2685 kfree(host->align_buffer);
a3c76eb9 2686 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2687 "buffers. Falling back to standard DMA.\n",
2688 mmc_hostname(mmc));
2689 host->flags &= ~SDHCI_USE_ADMA;
2690 }
2691 }
2692
7659150c
PO		 2693 /*
2694 * If we use DMA, then it's up to the caller to set the DMA
2695 * mask, but PIO does not need the hw shim so we set a new
2696 * mask here in that case.
2697 */
a13abc7b 2698 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2699 host->dma_mask = DMA_BIT_MASK(64);
2700 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2701 }
d129bceb 2702
c4687d5f 2703 if (host->version >= SDHCI_SPEC_300)
f2119df6 2704 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2705 >> SDHCI_CLOCK_BASE_SHIFT;
2706 else
f2119df6 2707 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2708 >> SDHCI_CLOCK_BASE_SHIFT;
2709
4240ff0a 2710 host->max_clk *= 1000000;
f27f47ef
AV		 2711 if (host->max_clk == 0 || host->quirks &
2712 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2713 if (!host->ops->get_max_clock) {
a3c76eb9 2714 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2715 "frequency.\n", mmc_hostname(mmc));
2716 return -ENODEV;
2717 }
2718 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2719 }
d129bceb 2720
c3ed3877
AN		 2721 /*
2722 * In case of Host Controller v3.00, find out whether clock
2723 * multiplier is supported.
2724 */
2725 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2726 SDHCI_CLOCK_MUL_SHIFT;
2727
2728 /*
2729 * In case the value in Clock Multiplier is 0, then programmable
2730 * clock mode is not supported, otherwise the actual clock
2731 * multiplier is one more than the value of Clock Multiplier
2732 * in the Capabilities Register.
2733 */
2734 if (host->clk_mul)
2735 host->clk_mul += 1;
2736
d129bceb
PO		 2737 /*
2738 * Set host parameters.
2739 */
2740 mmc->ops = &sdhci_ops;
c3ed3877 2741 mmc->f_max = host->max_clk;
ce5f036b 2742 if (host->ops->get_min_clock)
a9e58f25 2743 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2744 else if (host->version >= SDHCI_SPEC_300) {
2745 if (host->clk_mul) {
2746 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2747 mmc->f_max = host->max_clk * host->clk_mul;
2748 } else
2749 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2750 } else
0397526d 2751 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2752
272308ca
AS		 2753 host->timeout_clk =
2754 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2755 if (host->timeout_clk == 0) {
2756 if (host->ops->get_timeout_clock) {
2757 host->timeout_clk = host->ops->get_timeout_clock(host);
2758 } else if (!(host->quirks &
2759 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2760 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2761 "frequency.\n", mmc_hostname(mmc));
2762 return -ENODEV;
2763 }
2764 }
2765 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2766 host->timeout_clk *= 1000;
2767
2768 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2769 host->timeout_clk = mmc->f_max / 1000;
272308ca 2770
65be3fef 2771 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
58d1246d 2772
e89d456f
AW		 2773 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2774
2775 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2776 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2777
8edf6371 2778 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2779 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2780 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2781 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2782 host->flags |= SDHCI_AUTO_CMD23;
2783 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2784 } else {
2785 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2786 }
2787
15ec4461
PR		 2788 /*
2789 * A controller may support 8-bit width, but the board itself
2790 * might not have the pins brought out. Boards that support
2791 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2792 * their platform code before calling sdhci_add_host(), and we
2793 * won't assume 8-bit width for hosts without that CAP.
2794 */
5fe23c7f 2795 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2796 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2797
f2119df6 2798 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2799 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2800
176d1ed4 2801 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
eb6d5ae1 2802 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 2803 mmc->caps |= MMC_CAP_NEEDS_POLL;
2804
4188bba0
AC		 2805 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2806 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2807 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 2808 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2809
2810 /* SDR104 supports also implies SDR50 support */
2811 if (caps[1] & SDHCI_SUPPORT_SDR104)
2812 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2813 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2814 mmc->caps |= MMC_CAP_UHS_SDR50;
2815
2816 if (caps[1] & SDHCI_SUPPORT_DDR50)
2817 mmc->caps |= MMC_CAP_UHS_DDR50;
2818
069c9f14 2819 /* Does the host need tuning for SDR50? */
b513ea25
AN		 2820 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2821 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2822
069c9f14
G		 2823 /* Does the host need tuning for HS200? */
2824 if (mmc->caps2 & MMC_CAP2_HS200)
2825 host->flags |= SDHCI_HS200_NEEDS_TUNING;
2826
d6d50a15
AN		 2827 /* Driver Type(s) (A, C, D) supported by the host */
2828 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2829 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2830 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2831 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2832 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2833 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2834
bec8726a
G		 2835 /*
2836 * If Power Off Notify capability is enabled by the host,
2837 * set notify to short power off notify timeout value.
2838 */
2839 if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
2840 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
2841 else
2842 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
2843
cf2b5eea
AN		 2844 /* Initial value for re-tuning timer count */
2845 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2846 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2847
2848 /*
2849 * In case Re-tuning Timer is not disabled, the actual value of
2850 * re-tuning timer will be 2 ^ (n - 1).
2851 */
2852 if (host->tuning_count)
2853 host->tuning_count = 1 << (host->tuning_count - 1);
2854
2855 /* Re-tuning mode supported by the Host Controller */
2856 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2857 SDHCI_RETUNING_MODE_SHIFT;
2858
8f230f45 2859 ocr_avail = 0;
bad37e1a
PR		 2860
2861 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2862 if (IS_ERR(host->vmmc)) {
2863 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
2864 host->vmmc = NULL;
2865 }
2866
68737043
PR		 2867#ifdef CONFIG_REGULATOR
2868 if (host->vmmc) {
2869 ret = regulator_is_supported_voltage(host->vmmc, 3300000,
2870 3300000);
2871 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
2872 caps[0] &= ~SDHCI_CAN_VDD_330;
2873 ret = regulator_is_supported_voltage(host->vmmc, 3000000,
2874 3000000);
2875 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
2876 caps[0] &= ~SDHCI_CAN_VDD_300;
2877 ret = regulator_is_supported_voltage(host->vmmc, 1800000,
2878 1800000);
2879 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
2880 caps[0] &= ~SDHCI_CAN_VDD_180;
2881 }
2882#endif /* CONFIG_REGULATOR */
2883
f2119df6
AN		 2884 /*
2885 * According to SD Host Controller spec v3.00, if the Host System
2886 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2887 * the value is meaningful only if Voltage Support in the Capabilities
2888 * register is set. The actual current value is 4 times the register
2889 * value.
2890 */
2891 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
bad37e1a
PR		 2892 if (!max_current_caps && host->vmmc) {
2893 u32 curr = regulator_get_current_limit(host->vmmc);
2894 if (curr > 0) {
2895
2896 /* convert to SDHCI_MAX_CURRENT format */
2897 curr = curr/1000; /* convert to mA */
2898 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
2899
2900 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
2901 max_current_caps =
2902 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
2903 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
2904 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
2905 }
2906 }
f2119df6
AN		 2907
2908 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 2909 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 2910
55c4665e 2911 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 2912 SDHCI_MAX_CURRENT_330_MASK) >>
2913 SDHCI_MAX_CURRENT_330_SHIFT) *
2914 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 2915 }
2916 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 2917 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 2918
55c4665e 2919 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 2920 SDHCI_MAX_CURRENT_300_MASK) >>
2921 SDHCI_MAX_CURRENT_300_SHIFT) *
2922 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 2923 }
2924 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 2925 ocr_avail |= MMC_VDD_165_195;
2926
55c4665e 2927 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 2928 SDHCI_MAX_CURRENT_180_MASK) >>
2929 SDHCI_MAX_CURRENT_180_SHIFT) *
2930 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 2931 }
2932
8f230f45
TI		 2933 mmc->ocr_avail = ocr_avail;
2934 mmc->ocr_avail_sdio = ocr_avail;
2935 if (host->ocr_avail_sdio)
2936 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2937 mmc->ocr_avail_sd = ocr_avail;
2938 if (host->ocr_avail_sd)
2939 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2940 else /* normal SD controllers don't support 1.8V */
2941 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2942 mmc->ocr_avail_mmc = ocr_avail;
2943 if (host->ocr_avail_mmc)
2944 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 2945
2946 if (mmc->ocr_avail == 0) {
a3c76eb9 2947 pr_err("%s: Hardware doesn't report any "
b69c9058 2948 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 2949 return -ENODEV;
146ad66e
PO		 2950 }
2951
d129bceb
PO		 2952 spin_lock_init(&host->lock);
2953
2954 /*
2134a922
PO		 2955 * Maximum number of segments. Depends on if the hardware
2956 * can do scatter/gather or not.
d129bceb 2957 */
2134a922 2958 if (host->flags & SDHCI_USE_ADMA)
a36274e0 2959 mmc->max_segs = 128;
a13abc7b 2960 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 2961 mmc->max_segs = 1;
2134a922 2962 else /* PIO */
a36274e0 2963 mmc->max_segs = 128;
d129bceb
PO		 2964
2965 /*
bab76961 2966 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 2967 * size (512KiB).
d129bceb 2968 */
55db890a 2969 mmc->max_req_size = 524288;
d129bceb
PO		 2970
2971 /*
2972 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 2973 * of bytes. When doing hardware scatter/gather, each entry cannot
2974 * be larger than 64 KiB though.
d129bceb 2975 */
30652aa3
OJ		 2976 if (host->flags & SDHCI_USE_ADMA) {
2977 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2978 mmc->max_seg_size = 65535;
2979 else
2980 mmc->max_seg_size = 65536;
2981 } else {
2134a922 2982 mmc->max_seg_size = mmc->max_req_size;
30652aa3 2983 }
d129bceb 2984
fe4a3c7a
PO		 2985 /*
2986 * Maximum block size. This varies from controller to controller and
2987 * is specified in the capabilities register.
2988 */
0633f654
AV		 2989 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2990 mmc->max_blk_size = 2;
2991 } else {
f2119df6 2992 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 2993 SDHCI_MAX_BLOCK_SHIFT;
2994 if (mmc->max_blk_size >= 3) {
a3c76eb9 2995 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 2996 "assuming 512 bytes\n", mmc_hostname(mmc));
2997 mmc->max_blk_size = 0;
2998 }
2999 }
3000
3001 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3002
55db890a
PO		 3003 /*
3004 * Maximum block count.
3005 */
1388eefd 3006 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3007
d129bceb
PO		 3008 /*
3009 * Init tasklets.
3010 */
3011 tasklet_init(&host->card_tasklet,
3012 sdhci_tasklet_card, (unsigned long)host);
3013 tasklet_init(&host->finish_tasklet,
3014 sdhci_tasklet_finish, (unsigned long)host);
3015
e4cad1b5 3016 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3017
cf2b5eea 3018 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3019 init_waitqueue_head(&host->buf_ready_int);
3020
cf2b5eea
AN		 3021 /* Initialize re-tuning timer */
3022 init_timer(&host->tuning_timer);
3023 host->tuning_timer.data = (unsigned long)host;
3024 host->tuning_timer.function = sdhci_tuning_timer;
3025 }
3026
dace1453 3027 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 3028 mmc_hostname(mmc), host);
0fc81ee3
MB		 3029 if (ret) {
3030 pr_err("%s: Failed to request IRQ %d: %d\n",
3031 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3032 goto untasklet;
0fc81ee3 3033 }
d129bceb 3034
2f4cbb3d 3035 sdhci_init(host, 0);
d129bceb
PO		 3036
3037#ifdef CONFIG_MMC_DEBUG
3038 sdhci_dumpregs(host);
3039#endif
3040
f9134319 3041#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3042 snprintf(host->led_name, sizeof(host->led_name),
3043 "%s::", mmc_hostname(mmc));
3044 host->led.name = host->led_name;
2f730fec
PO		 3045 host->led.brightness = LED_OFF;
3046 host->led.default_trigger = mmc_hostname(mmc);
3047 host->led.brightness_set = sdhci_led_control;
3048
b8c86fc5 3049 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3050 if (ret) {
3051 pr_err("%s: Failed to register LED device: %d\n",
3052 mmc_hostname(mmc), ret);
2f730fec 3053 goto reset;
0fc81ee3 3054 }
2f730fec
PO		 3055#endif
3056
5f25a66f
PO		 3057 mmiowb();
3058
d129bceb
PO		 3059 mmc_add_host(mmc);
3060
a3c76eb9 3061 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3062 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 3063 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3064 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3065
7260cf5e
AV		 3066 sdhci_enable_card_detection(host);
3067
d129bceb
PO		 3068 return 0;
3069
f9134319 3070#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3071reset:
3072 sdhci_reset(host, SDHCI_RESET_ALL);
3073 free_irq(host->irq, host);
3074#endif
8ef1a143 3075untasklet:
d129bceb
PO		 3076 tasklet_kill(&host->card_tasklet);
3077 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3078
3079 return ret;
3080}
3081
b8c86fc5 3082EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3083
1e72859e 3084void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3085{
1e72859e
PO		 3086 unsigned long flags;
3087
3088 if (dead) {
3089 spin_lock_irqsave(&host->lock, flags);
3090
3091 host->flags |= SDHCI_DEVICE_DEAD;
3092
3093 if (host->mrq) {
a3c76eb9 3094 pr_err("%s: Controller removed during "
1e72859e
PO		 3095 " transfer!\n", mmc_hostname(host->mmc));
3096
3097 host->mrq->cmd->error = -ENOMEDIUM;
3098 tasklet_schedule(&host->finish_tasklet);
3099 }
3100
3101 spin_unlock_irqrestore(&host->lock, flags);
3102 }
3103
7260cf5e
AV		 3104 sdhci_disable_card_detection(host);
3105
b8c86fc5 3106 mmc_remove_host(host->mmc);
d129bceb 3107
f9134319 3108#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3109 led_classdev_unregister(&host->led);
3110#endif
3111
1e72859e
PO		 3112 if (!dead)
3113 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 3114
3115 free_irq(host->irq, host);
3116
3117 del_timer_sync(&host->timer);
3118
3119 tasklet_kill(&host->card_tasklet);
3120 tasklet_kill(&host->finish_tasklet);
2134a922 3121
ceb6143b 3122 if (host->vmmc)
9bea3c85 3123 regulator_put(host->vmmc);
9bea3c85 3124
2134a922
PO		 3125 kfree(host->adma_desc);
3126 kfree(host->align_buffer);
3127
3128 host->adma_desc = NULL;
3129 host->align_buffer = NULL;
d129bceb
PO		 3130}
3131
b8c86fc5 3132EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3133
b8c86fc5 3134void sdhci_free_host(struct sdhci_host *host)
d129bceb 3135{
b8c86fc5 3136 mmc_free_host(host->mmc);
d129bceb
PO		 3137}
3138
b8c86fc5 3139EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3140
3141/*****************************************************************************\
3142 * *
3143 * Driver init/exit *
3144 * *
3145\*****************************************************************************/
3146
3147static int __init sdhci_drv_init(void)
3148{
a3c76eb9 3149 pr_info(DRIVER_NAME
52fbf9c9 3150 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3151 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3152
b8c86fc5 3153 return 0;
d129bceb
PO		 3154}
3155
3156static void __exit sdhci_drv_exit(void)
3157{
d129bceb
PO		 3158}
3159
3160module_init(sdhci_drv_init);
3161module_exit(sdhci_drv_exit);
3162
df673b22 3163module_param(debug_quirks, uint, 0444);
66fd8ad5 3164module_param(debug_quirks2, uint, 0444);
67435274 3165
32710e8f 3166MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3167MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3168MODULE_LICENSE("GPL");
67435274 3169
df673b22 3170MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3171MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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