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mmc: sdhci: Reduce spin lock usage in sdhci_execute_tuning
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb 16#include <linux/delay.h>
5a436cc0 17#include <linux/ktime.h>
d129bceb 18#include <linux/highmem.h>
b8c86fc5 19#include <linux/io.h>
88b47679 20#include <linux/module.h>
d129bceb 21#include <linux/dma-mapping.h>
5a0e3ad6 22#include <linux/slab.h>
11763609 23#include <linux/scatterlist.h>
9bea3c85 24#include <linux/regulator/consumer.h>
66fd8ad5 25#include <linux/pm_runtime.h>
92e0c44b 26#include <linux/of.h>
d129bceb 27
2f730fec
PO		 28#include <linux/leds.h>
29
22113efd 30#include <linux/mmc/mmc.h>
d129bceb 31#include <linux/mmc/host.h>
473b095a 32#include <linux/mmc/card.h>
85cc1c33 33#include <linux/mmc/sdio.h>
bec9d4e5 34#include <linux/mmc/slot-gpio.h>
d129bceb 35
d129bceb
PO		 36#include "sdhci.h"
37
38#define DRIVER_NAME "sdhci"
d129bceb 39
d129bceb 40#define DBG(f, x...) \
c6563178 41 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 42
b513ea25
AN		 43#define MAX_TUNING_LOOP 40
44
df673b22 45static unsigned int debug_quirks = 0;
66fd8ad5 46static unsigned int debug_quirks2;
67435274 47
d129bceb
PO		 48static void sdhci_finish_data(struct sdhci_host *);
49
52983382 50static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb
PO		 51
52static void sdhci_dumpregs(struct sdhci_host *host)
53{
a7c53671
CD		 54 pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
55 mmc_hostname(host->mmc));
d129bceb 56
a7c53671
CD		 57 pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
58 sdhci_readl(host, SDHCI_DMA_ADDRESS),
59 sdhci_readw(host, SDHCI_HOST_VERSION));
60 pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
61 sdhci_readw(host, SDHCI_BLOCK_SIZE),
62 sdhci_readw(host, SDHCI_BLOCK_COUNT));
63 pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
64 sdhci_readl(host, SDHCI_ARGUMENT),
65 sdhci_readw(host, SDHCI_TRANSFER_MODE));
66 pr_err(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
67 sdhci_readl(host, SDHCI_PRESENT_STATE),
68 sdhci_readb(host, SDHCI_HOST_CONTROL));
69 pr_err(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
70 sdhci_readb(host, SDHCI_POWER_CONTROL),
71 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
72 pr_err(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
73 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
74 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
75 pr_err(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
76 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
77 sdhci_readl(host, SDHCI_INT_STATUS));
78 pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
79 sdhci_readl(host, SDHCI_INT_ENABLE),
80 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
81 pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
82 sdhci_readw(host, SDHCI_ACMD12_ERR),
83 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
84 pr_err(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
85 sdhci_readl(host, SDHCI_CAPABILITIES),
86 sdhci_readl(host, SDHCI_CAPABILITIES_1));
87 pr_err(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
88 sdhci_readw(host, SDHCI_COMMAND),
89 sdhci_readl(host, SDHCI_MAX_CURRENT));
90 pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n",
91 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 92
e57a5f61
AH		 93 if (host->flags & SDHCI_USE_ADMA) {
94 if (host->flags & SDHCI_USE_64_BIT_DMA)
a7c53671
CD		 95 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
96 readl(host->ioaddr + SDHCI_ADMA_ERROR),
97 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
98 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
e57a5f61 99 else
a7c53671
CD		 100 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
101 readl(host->ioaddr + SDHCI_ADMA_ERROR),
102 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
e57a5f61 103 }
be3f4ae0 104
a7c53671 105 pr_err(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 106}
107
108/*****************************************************************************\
109 * *
110 * Low level functions *
111 * *
112\*****************************************************************************/
113
56a590dc
AH		 114static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
115{
116 return cmd->data || cmd->flags & MMC_RSP_BUSY;
117}
118
7260cf5e
AV		 119static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
120{
5b4f1f6c 121 u32 present;
7260cf5e 122
c79396c1 123 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
860951c5 124 !mmc_card_is_removable(host->mmc))
66fd8ad5
AH		 125 return;
126
5b4f1f6c
RK		 127 if (enable) {
128 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
129 SDHCI_CARD_PRESENT;
d25928d1 130
5b4f1f6c
RK		 131 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
132 SDHCI_INT_CARD_INSERT;
133 } else {
134 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
135 }
b537f94c
RK		 136
137 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
138 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 139}
140
141static void sdhci_enable_card_detection(struct sdhci_host *host)
142{
143 sdhci_set_card_detection(host, true);
144}
145
146static void sdhci_disable_card_detection(struct sdhci_host *host)
147{
148 sdhci_set_card_detection(host, false);
149}
150
02d0b685
UH		 151static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
152{
153 if (host->bus_on)
154 return;
155 host->bus_on = true;
156 pm_runtime_get_noresume(host->mmc->parent);
157}
158
159static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
160{
161 if (!host->bus_on)
162 return;
163 host->bus_on = false;
164 pm_runtime_put_noidle(host->mmc->parent);
165}
166
03231f9b 167void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 168{
5a436cc0 169 ktime_t timeout;
393c1a34 170
4e4141a5 171 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 172
f0710a55 173 if (mask & SDHCI_RESET_ALL) {
d129bceb 174 host->clock = 0;
f0710a55
AH		 175 /* Reset-all turns off SD Bus Power */
176 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
177 sdhci_runtime_pm_bus_off(host);
178 }
d129bceb 179
e16514d8 180 /* Wait max 100 ms */
5a436cc0 181 timeout = ktime_add_ms(ktime_get(), 100);
e16514d8
PO		 182
183 /* hw clears the bit when it's done */
4e4141a5 184 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
5a436cc0 185 if (ktime_after(ktime_get(), timeout)) {
a3c76eb9 186 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 187 mmc_hostname(host->mmc), (int)mask);
188 sdhci_dumpregs(host);
189 return;
190 }
5a436cc0 191 udelay(10);
d129bceb 192 }
03231f9b
RK		 193}
194EXPORT_SYMBOL_GPL(sdhci_reset);
195
196static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
197{
198 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
d3940f27
AH		 199 struct mmc_host *mmc = host->mmc;
200
201 if (!mmc->ops->get_cd(mmc))
03231f9b
RK		 202 return;
203 }
063a9dbb 204
03231f9b 205 host->ops->reset(host, mask);
393c1a34 206
da91a8f9
RK		 207 if (mask & SDHCI_RESET_ALL) {
208 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
209 if (host->ops->enable_dma)
210 host->ops->enable_dma(host);
211 }
212
213 /* Resetting the controller clears many */
214 host->preset_enabled = false;
3abc1e80 215 }
d129bceb
PO		 216}
217
2f4cbb3d 218static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 219{
d3940f27
AH		 220 struct mmc_host *mmc = host->mmc;
221
2f4cbb3d 222 if (soft)
03231f9b 223 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 224 else
03231f9b 225 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 226
b537f94c
RK		 227 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
228 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
229 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
230 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
231 SDHCI_INT_RESPONSE;
232
f37b20eb
DA		 233 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
234 host->tuning_mode == SDHCI_TUNING_MODE_3)
235 host->ier |= SDHCI_INT_RETUNE;
236
b537f94c
RK		 237 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
238 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 239
240 if (soft) {
241 /* force clock reconfiguration */
242 host->clock = 0;
d3940f27 243 mmc->ops->set_ios(mmc, &mmc->ios);
2f4cbb3d 244 }
7260cf5e 245}
d129bceb 246
7260cf5e
AV		 247static void sdhci_reinit(struct sdhci_host *host)
248{
2f4cbb3d 249 sdhci_init(host, 0);
7260cf5e 250 sdhci_enable_card_detection(host);
d129bceb
PO		 251}
252
061d17a6 253static void __sdhci_led_activate(struct sdhci_host *host)
d129bceb
PO		 254{
255 u8 ctrl;
256
4e4141a5 257 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 258 ctrl |= SDHCI_CTRL_LED;
4e4141a5 259 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 260}
261
061d17a6 262static void __sdhci_led_deactivate(struct sdhci_host *host)
d129bceb
PO		 263{
264 u8 ctrl;
265
4e4141a5 266 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 267 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 268 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 269}
270
4f78230f 271#if IS_REACHABLE(CONFIG_LEDS_CLASS)
2f730fec 272static void sdhci_led_control(struct led_classdev *led,
061d17a6 273 enum led_brightness brightness)
2f730fec
PO		 274{
275 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
276 unsigned long flags;
277
278 spin_lock_irqsave(&host->lock, flags);
279
66fd8ad5
AH		 280 if (host->runtime_suspended)
281 goto out;
282
2f730fec 283 if (brightness == LED_OFF)
061d17a6 284 __sdhci_led_deactivate(host);
2f730fec 285 else
061d17a6 286 __sdhci_led_activate(host);
66fd8ad5 287out:
2f730fec
PO		 288 spin_unlock_irqrestore(&host->lock, flags);
289}
061d17a6
AH		 290
291static int sdhci_led_register(struct sdhci_host *host)
292{
293 struct mmc_host *mmc = host->mmc;
294
295 snprintf(host->led_name, sizeof(host->led_name),
296 "%s::", mmc_hostname(mmc));
297
298 host->led.name = host->led_name;
299 host->led.brightness = LED_OFF;
300 host->led.default_trigger = mmc_hostname(mmc);
301 host->led.brightness_set = sdhci_led_control;
302
303 return led_classdev_register(mmc_dev(mmc), &host->led);
304}
305
306static void sdhci_led_unregister(struct sdhci_host *host)
307{
308 led_classdev_unregister(&host->led);
309}
310
311static inline void sdhci_led_activate(struct sdhci_host *host)
312{
313}
314
315static inline void sdhci_led_deactivate(struct sdhci_host *host)
316{
317}
318
319#else
320
321static inline int sdhci_led_register(struct sdhci_host *host)
322{
323 return 0;
324}
325
326static inline void sdhci_led_unregister(struct sdhci_host *host)
327{
328}
329
330static inline void sdhci_led_activate(struct sdhci_host *host)
331{
332 __sdhci_led_activate(host);
333}
334
335static inline void sdhci_led_deactivate(struct sdhci_host *host)
336{
337 __sdhci_led_deactivate(host);
338}
339
2f730fec
PO		 340#endif
341
d129bceb
PO		 342/*****************************************************************************\
343 * *
344 * Core functions *
345 * *
346\*****************************************************************************/
347
a406f5a3 348static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 349{
7659150c
PO		 350 unsigned long flags;
351 size_t blksize, len, chunk;
7244b85b 352 u32 uninitialized_var(scratch);
7659150c 353 u8 *buf;
d129bceb 354
a406f5a3 355 DBG("PIO reading\n");
d129bceb 356
a406f5a3 357 blksize = host->data->blksz;
7659150c 358 chunk = 0;
d129bceb 359
7659150c 360 local_irq_save(flags);
d129bceb 361
a406f5a3 362 while (blksize) {
bf3a35ac 363 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 364
7659150c 365 len = min(host->sg_miter.length, blksize);
d129bceb 366
7659150c
PO		 367 blksize -= len;
368 host->sg_miter.consumed = len;
14d836e7 369
7659150c 370 buf = host->sg_miter.addr;
d129bceb 371
7659150c
PO		 372 while (len) {
373 if (chunk == 0) {
4e4141a5 374 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 375 chunk = 4;
a406f5a3 376 }
7659150c
PO		 377
378 *buf = scratch & 0xFF;
379
380 buf++;
381 scratch >>= 8;
382 chunk--;
383 len--;
d129bceb 384 }
a406f5a3 385 }
7659150c
PO		 386
387 sg_miter_stop(&host->sg_miter);
388
389 local_irq_restore(flags);
a406f5a3 390}
d129bceb 391
a406f5a3
PO		 392static void sdhci_write_block_pio(struct sdhci_host *host)
393{
7659150c
PO		 394 unsigned long flags;
395 size_t blksize, len, chunk;
396 u32 scratch;
397 u8 *buf;
d129bceb 398
a406f5a3
PO		 399 DBG("PIO writing\n");
400
401 blksize = host->data->blksz;
7659150c
PO		 402 chunk = 0;
403 scratch = 0;
d129bceb 404
7659150c 405 local_irq_save(flags);
d129bceb 406
a406f5a3 407 while (blksize) {
bf3a35ac 408 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 409
7659150c
PO		 410 len = min(host->sg_miter.length, blksize);
411
412 blksize -= len;
413 host->sg_miter.consumed = len;
414
415 buf = host->sg_miter.addr;
d129bceb 416
7659150c
PO		 417 while (len) {
418 scratch |= (u32)*buf << (chunk * 8);
419
420 buf++;
421 chunk++;
422 len--;
423
424 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 425 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 426 chunk = 0;
427 scratch = 0;
d129bceb 428 }
d129bceb
PO		 429 }
430 }
7659150c
PO		 431
432 sg_miter_stop(&host->sg_miter);
433
434 local_irq_restore(flags);
a406f5a3
PO		 435}
436
437static void sdhci_transfer_pio(struct sdhci_host *host)
438{
439 u32 mask;
440
7659150c 441 if (host->blocks == 0)
a406f5a3
PO		 442 return;
443
444 if (host->data->flags & MMC_DATA_READ)
445 mask = SDHCI_DATA_AVAILABLE;
446 else
447 mask = SDHCI_SPACE_AVAILABLE;
448
4a3cba32
PO		 449 /*
450 * Some controllers (JMicron JMB38x) mess up the buffer bits
451 * for transfers < 4 bytes. As long as it is just one block,
452 * we can ignore the bits.
453 */
454 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
455 (host->data->blocks == 1))
456 mask = ~0;
457
4e4141a5 458 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 459 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
460 udelay(100);
461
a406f5a3
PO		 462 if (host->data->flags & MMC_DATA_READ)
463 sdhci_read_block_pio(host);
464 else
465 sdhci_write_block_pio(host);
d129bceb 466
7659150c
PO		 467 host->blocks--;
468 if (host->blocks == 0)
a406f5a3 469 break;
a406f5a3 470 }
d129bceb 471
a406f5a3 472 DBG("PIO transfer complete.\n");
d129bceb
PO		 473}
474
48857d9b 475static int sdhci_pre_dma_transfer(struct sdhci_host *host,
c0999b72 476 struct mmc_data *data, int cookie)
48857d9b
RK		 477{
478 int sg_count;
479
94538e51
RK		 480 /*
481 * If the data buffers are already mapped, return the previous
482 * dma_map_sg() result.
483 */
484 if (data->host_cookie == COOKIE_PRE_MAPPED)
48857d9b 485 return data->sg_count;
48857d9b
RK		 486
487 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
488 data->flags & MMC_DATA_WRITE ?
489 DMA_TO_DEVICE : DMA_FROM_DEVICE);
490
491 if (sg_count == 0)
492 return -ENOSPC;
493
494 data->sg_count = sg_count;
c0999b72 495 data->host_cookie = cookie;
48857d9b
RK		 496
497 return sg_count;
498}
499
2134a922
PO		 500static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
501{
502 local_irq_save(*flags);
482fce99 503 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 504}
505
506static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
507{
482fce99 508 kunmap_atomic(buffer);
2134a922
PO		 509 local_irq_restore(*flags);
510}
511
e57a5f61
AH		 512static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
513 dma_addr_t addr, int len, unsigned cmd)
118cd17d 514{
e57a5f61 515 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 516
e57a5f61 517 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 518 dma_desc->cmd = cpu_to_le16(cmd);
519 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 520 dma_desc->addr_lo = cpu_to_le32((u32)addr);
521
522 if (host->flags & SDHCI_USE_64_BIT_DMA)
523 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 524}
525
b5ffa674
AH		 526static void sdhci_adma_mark_end(void *desc)
527{
e57a5f61 528 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 529
e57a5f61 530 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 531 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 532}
533
60c64762
RK		 534static void sdhci_adma_table_pre(struct sdhci_host *host,
535 struct mmc_data *data, int sg_count)
2134a922 536{
2134a922 537 struct scatterlist *sg;
2134a922 538 unsigned long flags;
acc3ad13
RK		 539 dma_addr_t addr, align_addr;
540 void *desc, *align;
541 char *buffer;
542 int len, offset, i;
2134a922
PO		 543
544 /*
545 * The spec does not specify endianness of descriptor table.
546 * We currently guess that it is LE.
547 */
548
60c64762 549 host->sg_count = sg_count;
2134a922 550
4efaa6fb 551 desc = host->adma_table;
2134a922
PO		 552 align = host->align_buffer;
553
554 align_addr = host->align_addr;
555
556 for_each_sg(data->sg, sg, host->sg_count, i) {
557 addr = sg_dma_address(sg);
558 len = sg_dma_len(sg);
559
560 /*
acc3ad13
RK		 561 * The SDHCI specification states that ADMA addresses must
562 * be 32-bit aligned. If they aren't, then we use a bounce
563 * buffer for the (up to three) bytes that screw up the
2134a922
PO		 564 * alignment.
565 */
04a5ae6f
AH		 566 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
567 SDHCI_ADMA2_MASK;
2134a922
PO		 568 if (offset) {
569 if (data->flags & MMC_DATA_WRITE) {
570 buffer = sdhci_kmap_atomic(sg, &flags);
571 memcpy(align, buffer, offset);
572 sdhci_kunmap_atomic(buffer, &flags);
573 }
574
118cd17d 575 /* tran, valid */
e57a5f61 576 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 577 ADMA2_TRAN_VALID);
2134a922
PO		 578
579 BUG_ON(offset > 65536);
580
04a5ae6f
AH		 581 align += SDHCI_ADMA2_ALIGN;
582 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 583
76fe379a 584 desc += host->desc_sz;
2134a922
PO		 585
586 addr += offset;
587 len -= offset;
588 }
589
2134a922
PO		 590 BUG_ON(len > 65536);
591
347ea32d
AH		 592 if (len) {
593 /* tran, valid */
594 sdhci_adma_write_desc(host, desc, addr, len,
595 ADMA2_TRAN_VALID);
596 desc += host->desc_sz;
597 }
2134a922
PO		 598
599 /*
600 * If this triggers then we have a calculation bug
601 * somewhere. :/
602 */
76fe379a 603 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 604 }
605
70764a90 606 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
acc3ad13 607 /* Mark the last descriptor as the terminating descriptor */
4efaa6fb 608 if (desc != host->adma_table) {
76fe379a 609 desc -= host->desc_sz;
b5ffa674 610 sdhci_adma_mark_end(desc);
70764a90
TA		 611 }
612 } else {
acc3ad13 613 /* Add a terminating entry - nop, end, valid */
e57a5f61 614 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 615 }
2134a922
PO		 616}
617
618static void sdhci_adma_table_post(struct sdhci_host *host,
619 struct mmc_data *data)
620{
2134a922
PO		 621 struct scatterlist *sg;
622 int i, size;
1c3d5f6d 623 void *align;
2134a922
PO		 624 char *buffer;
625 unsigned long flags;
626
47fa9613
RK		 627 if (data->flags & MMC_DATA_READ) {
628 bool has_unaligned = false;
de0b65a7 629
47fa9613
RK		 630 /* Do a quick scan of the SG list for any unaligned mappings */
631 for_each_sg(data->sg, sg, host->sg_count, i)
632 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
633 has_unaligned = true;
634 break;
635 }
2134a922 636
47fa9613
RK		 637 if (has_unaligned) {
638 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
f55c98f7 639 data->sg_len, DMA_FROM_DEVICE);
2134a922 640
47fa9613 641 align = host->align_buffer;
2134a922 642
47fa9613
RK		 643 for_each_sg(data->sg, sg, host->sg_count, i) {
644 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
645 size = SDHCI_ADMA2_ALIGN -
646 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
647
648 buffer = sdhci_kmap_atomic(sg, &flags);
649 memcpy(buffer, align, size);
650 sdhci_kunmap_atomic(buffer, &flags);
2134a922 651
47fa9613
RK		 652 align += SDHCI_ADMA2_ALIGN;
653 }
2134a922
PO		 654 }
655 }
656 }
2134a922
PO		 657}
658
a3c7778f 659static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 660{
1c8cde92 661 u8 count;
a3c7778f 662 struct mmc_data *data = cmd->data;
1c8cde92 663 unsigned target_timeout, current_timeout;
d129bceb 664
ee53ab5d
PO		 665 /*
666 * If the host controller provides us with an incorrect timeout
667 * value, just skip the check and use 0xE. The hardware may take
668 * longer to time out, but that's much better than having a too-short
669 * timeout value.
670 */
11a2f1b7 671 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 672 return 0xE;
e538fbe8 673
a3c7778f 674 /* Unspecified timeout, assume max */
1d4d7744 675 if (!data && !cmd->busy_timeout)
a3c7778f 676 return 0xE;
d129bceb 677
a3c7778f
AW		 678 /* timeout in us */
679 if (!data)
1d4d7744 680 target_timeout = cmd->busy_timeout * 1000;
78a2ca27 681 else {
fafcfda9 682 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
7f05538a
RK		 683 if (host->clock && data->timeout_clks) {
684 unsigned long long val;
685
686 /*
687 * data->timeout_clks is in units of clock cycles.
688 * host->clock is in Hz. target_timeout is in us.
689 * Hence, us = 1000000 * cycles / Hz. Round up.
690 */
02265cd6 691 val = 1000000ULL * data->timeout_clks;
7f05538a
RK		 692 if (do_div(val, host->clock))
693 target_timeout++;
694 target_timeout += val;
695 }
78a2ca27 696 }
81b39802 697
1c8cde92
PO		 698 /*
699 * Figure out needed cycles.
700 * We do this in steps in order to fit inside a 32 bit int.
701 * The first step is the minimum timeout, which will have a
702 * minimum resolution of 6 bits:
703 * (1) 2^13*1000 > 2^22,
704 * (2) host->timeout_clk < 2^16
705 * =>
706 * (1) / (2) > 2^6
707 */
708 count = 0;
709 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
710 while (current_timeout < target_timeout) {
711 count++;
712 current_timeout <<= 1;
713 if (count >= 0xF)
714 break;
715 }
716
717 if (count >= 0xF) {
09eeff52
CB		 718 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
719 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 720 count = 0xE;
721 }
722
ee53ab5d
PO		 723 return count;
724}
725
6aa943ab
AV		 726static void sdhci_set_transfer_irqs(struct sdhci_host *host)
727{
728 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
729 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
730
731 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 732 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 733 else
b537f94c
RK		 734 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
735
736 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
737 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 738}
739
b45e668a 740static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 741{
742 u8 count;
b45e668a
AD		 743
744 if (host->ops->set_timeout) {
745 host->ops->set_timeout(host, cmd);
746 } else {
747 count = sdhci_calc_timeout(host, cmd);
748 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
749 }
750}
751
752static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
753{
2134a922 754 u8 ctrl;
a3c7778f 755 struct mmc_data *data = cmd->data;
ee53ab5d 756
56a590dc 757 if (sdhci_data_line_cmd(cmd))
b45e668a 758 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 759
760 if (!data)
ee53ab5d
PO		 761 return;
762
43dea098
AH		 763 WARN_ON(host->data);
764
ee53ab5d
PO		 765 /* Sanity checks */
766 BUG_ON(data->blksz * data->blocks > 524288);
767 BUG_ON(data->blksz > host->mmc->max_blk_size);
768 BUG_ON(data->blocks > 65535);
769
770 host->data = data;
771 host->data_early = 0;
f6a03cbf 772 host->data->bytes_xfered = 0;
ee53ab5d 773
fce14421 774 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2134a922 775 struct scatterlist *sg;
df953925 776 unsigned int length_mask, offset_mask;
a0eaf0f9 777 int i;
2134a922 778
fce14421
RK		 779 host->flags |= SDHCI_REQ_USE_DMA;
780
781 /*
782 * FIXME: This doesn't account for merging when mapping the
783 * scatterlist.
784 *
785 * The assumption here being that alignment and lengths are
786 * the same after DMA mapping to device address space.
787 */
a0eaf0f9 788 length_mask = 0;
df953925 789 offset_mask = 0;
2134a922 790 if (host->flags & SDHCI_USE_ADMA) {
df953925 791 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
a0eaf0f9 792 length_mask = 3;
df953925
RK		 793 /*
794 * As we use up to 3 byte chunks to work
795 * around alignment problems, we need to
796 * check the offset as well.
797 */
798 offset_mask = 3;
799 }
2134a922
PO		 800 } else {
801 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
a0eaf0f9 802 length_mask = 3;
df953925
RK		 803 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
804 offset_mask = 3;
2134a922
PO		 805 }
806
df953925 807 if (unlikely(length_mask | offset_mask)) {
2134a922 808 for_each_sg(data->sg, sg, data->sg_len, i) {
a0eaf0f9 809 if (sg->length & length_mask) {
2e4456f0 810 DBG("Reverting to PIO because of transfer size (%d)\n",
a0eaf0f9 811 sg->length);
2134a922
PO		 812 host->flags &= ~SDHCI_REQ_USE_DMA;
813 break;
814 }
a0eaf0f9 815 if (sg->offset & offset_mask) {
2e4456f0 816 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 817 host->flags &= ~SDHCI_REQ_USE_DMA;
818 break;
819 }
820 }
821 }
822 }
823
8f1934ce 824 if (host->flags & SDHCI_REQ_USE_DMA) {
c0999b72 825 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
60c64762
RK		 826
827 if (sg_cnt <= 0) {
828 /*
829 * This only happens when someone fed
830 * us an invalid request.
831 */
832 WARN_ON(1);
833 host->flags &= ~SDHCI_REQ_USE_DMA;
834 } else if (host->flags & SDHCI_USE_ADMA) {
835 sdhci_adma_table_pre(host, data, sg_cnt);
836
837 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
838 if (host->flags & SDHCI_USE_64_BIT_DMA)
839 sdhci_writel(host,
840 (u64)host->adma_addr >> 32,
841 SDHCI_ADMA_ADDRESS_HI);
8f1934ce 842 } else {
60c64762
RK		 843 WARN_ON(sg_cnt != 1);
844 sdhci_writel(host, sg_dma_address(data->sg),
845 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 846 }
847 }
848
2134a922
PO		 849 /*
850 * Always adjust the DMA selection as some controllers
851 * (e.g. JMicron) can't do PIO properly when the selection
852 * is ADMA.
853 */
854 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 855 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 856 ctrl &= ~SDHCI_CTRL_DMA_MASK;
857 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 858 (host->flags & SDHCI_USE_ADMA)) {
859 if (host->flags & SDHCI_USE_64_BIT_DMA)
860 ctrl |= SDHCI_CTRL_ADMA64;
861 else
862 ctrl |= SDHCI_CTRL_ADMA32;
863 } else {
2134a922 864 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 865 }
4e4141a5 866 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 867 }
868
8f1934ce 869 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 870 int flags;
871
872 flags = SG_MITER_ATOMIC;
873 if (host->data->flags & MMC_DATA_READ)
874 flags |= SG_MITER_TO_SG;
875 else
876 flags |= SG_MITER_FROM_SG;
877 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 878 host->blocks = data->blocks;
d129bceb 879 }
c7fa9963 880
6aa943ab
AV		 881 sdhci_set_transfer_irqs(host);
882
f6a03cbf
MV		 883 /* Set the DMA boundary value and block size */
884 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
885 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 886 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 887}
888
0293d501
AH		 889static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
890 struct mmc_request *mrq)
891{
20845bef
AH		 892 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
893 !mrq->cap_cmd_during_tfr;
0293d501
AH		 894}
895
c7fa9963 896static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 897 struct mmc_command *cmd)
c7fa9963 898{
d3fc5d71 899 u16 mode = 0;
e89d456f 900 struct mmc_data *data = cmd->data;
c7fa9963 901
2b558c13 902 if (data == NULL) {
9b8ffea6
VW		 903 if (host->quirks2 &
904 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
905 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
906 } else {
2b558c13 907 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 908 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
909 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 910 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 911 }
c7fa9963 912 return;
2b558c13 913 }
c7fa9963 914
e538fbe8
PO		 915 WARN_ON(!host->data);
916
d3fc5d71
VY		 917 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
918 mode = SDHCI_TRNS_BLK_CNT_EN;
919
e89d456f 920 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 921 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 922 /*
923 * If we are sending CMD23, CMD12 never gets sent
924 * on successful completion (so no Auto-CMD12).
925 */
0293d501 926 if (sdhci_auto_cmd12(host, cmd->mrq) &&
85cc1c33 927 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 928 mode |= SDHCI_TRNS_AUTO_CMD12;
a4c73aba 929 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
8edf6371 930 mode |= SDHCI_TRNS_AUTO_CMD23;
a4c73aba 931 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
8edf6371 932 }
c4512f79 933 }
8edf6371 934
c7fa9963
PO		 935 if (data->flags & MMC_DATA_READ)
936 mode |= SDHCI_TRNS_READ;
c9fddbc4 937 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 938 mode |= SDHCI_TRNS_DMA;
939
4e4141a5 940 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 941}
942
0cc563ce
AH		 943static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
944{
945 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
946 ((mrq->cmd && mrq->cmd->error) ||
947 (mrq->sbc && mrq->sbc->error) ||
948 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
949 (mrq->data->stop && mrq->data->stop->error))) ||
950 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
951}
952
4e9f8fe5
AH		 953static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
954{
955 int i;
956
957 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
958 if (host->mrqs_done[i] == mrq) {
959 WARN_ON(1);
960 return;
961 }
962 }
963
964 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
965 if (!host->mrqs_done[i]) {
966 host->mrqs_done[i] = mrq;
967 break;
968 }
969 }
970
971 WARN_ON(i >= SDHCI_MAX_MRQS);
972
973 tasklet_schedule(&host->finish_tasklet);
974}
975
a6d3bdd5
AH		 976static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
977{
5a8a3fef
AH		 978 if (host->cmd && host->cmd->mrq == mrq)
979 host->cmd = NULL;
980
981 if (host->data_cmd && host->data_cmd->mrq == mrq)
982 host->data_cmd = NULL;
983
984 if (host->data && host->data->mrq == mrq)
985 host->data = NULL;
986
ed1563de
AH		 987 if (sdhci_needs_reset(host, mrq))
988 host->pending_reset = true;
989
4e9f8fe5 990 __sdhci_finish_mrq(host, mrq);
a6d3bdd5
AH		 991}
992
d129bceb
PO		 993static void sdhci_finish_data(struct sdhci_host *host)
994{
33a57adb
AH		 995 struct mmc_command *data_cmd = host->data_cmd;
996 struct mmc_data *data = host->data;
d129bceb 997
d129bceb 998 host->data = NULL;
7c89a3d9 999 host->data_cmd = NULL;
d129bceb 1000
add8913d
RK		 1001 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1002 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1003 sdhci_adma_table_post(host, data);
d129bceb
PO		 1004
1005 /*
c9b74c5b
PO		 1006 * The specification states that the block count register must
1007 * be updated, but it does not specify at what point in the
1008 * data flow. That makes the register entirely useless to read
1009 * back so we have to assume that nothing made it to the card
1010 * in the event of an error.
d129bceb 1011 */
c9b74c5b
PO		 1012 if (data->error)
1013 data->bytes_xfered = 0;
d129bceb 1014 else
c9b74c5b 1015 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 1016
e89d456f
AW		 1017 /*
1018 * Need to send CMD12 if -
1019 * a) open-ended multiblock transfer (no CMD23)
1020 * b) error in multiblock transfer
1021 */
1022 if (data->stop &&
1023 (data->error ||
a4c73aba 1024 !data->mrq->sbc)) {
e89d456f 1025
d129bceb
PO		 1026 /*
1027 * The controller needs a reset of internal state machines
1028 * upon error conditions.
1029 */
17b0429d 1030 if (data->error) {
33a57adb
AH		 1031 if (!host->cmd || host->cmd == data_cmd)
1032 sdhci_do_reset(host, SDHCI_RESET_CMD);
03231f9b 1033 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 1034 }
1035
20845bef
AH		 1036 /*
1037 * 'cap_cmd_during_tfr' request must not use the command line
1038 * after mmc_command_done() has been called. It is upper layer's
1039 * responsibility to send the stop command if required.
1040 */
1041 if (data->mrq->cap_cmd_during_tfr) {
1042 sdhci_finish_mrq(host, data->mrq);
1043 } else {
1044 /* Avoid triggering warning in sdhci_send_command() */
1045 host->cmd = NULL;
1046 sdhci_send_command(host, data->stop);
1047 }
a6d3bdd5
AH		 1048 } else {
1049 sdhci_finish_mrq(host, data->mrq);
1050 }
d129bceb
PO		 1051}
1052
d7422fb4
AH		 1053static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1054 unsigned long timeout)
1055{
1056 if (sdhci_data_line_cmd(mrq->cmd))
1057 mod_timer(&host->data_timer, timeout);
1058 else
1059 mod_timer(&host->timer, timeout);
1060}
1061
1062static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1063{
1064 if (sdhci_data_line_cmd(mrq->cmd))
1065 del_timer(&host->data_timer);
1066 else
1067 del_timer(&host->timer);
1068}
1069
c0e55129 1070void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 1071{
1072 int flags;
fd2208d7 1073 u32 mask;
7cb2c76f 1074 unsigned long timeout;
d129bceb
PO		 1075
1076 WARN_ON(host->cmd);
1077
96776200
RK		 1078 /* Initially, a command has no error */
1079 cmd->error = 0;
1080
fc605f1d
AH		 1081 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1082 cmd->opcode == MMC_STOP_TRANSMISSION)
1083 cmd->flags |= MMC_RSP_BUSY;
1084
d129bceb 1085 /* Wait max 10 ms */
7cb2c76f 1086 timeout = 10;
fd2208d7
PO		 1087
1088 mask = SDHCI_CMD_INHIBIT;
56a590dc 1089 if (sdhci_data_line_cmd(cmd))
fd2208d7
PO		 1090 mask |= SDHCI_DATA_INHIBIT;
1091
1092 /* We shouldn't wait for data inihibit for stop commands, even
1093 though they might use busy signaling */
a4c73aba 1094 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
fd2208d7
PO		 1095 mask &= ~SDHCI_DATA_INHIBIT;
1096
4e4141a5 1097 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1098 if (timeout == 0) {
2e4456f0
MV		 1099 pr_err("%s: Controller never released inhibit bit(s).\n",
1100 mmc_hostname(host->mmc));
d129bceb 1101 sdhci_dumpregs(host);
17b0429d 1102 cmd->error = -EIO;
a6d3bdd5 1103 sdhci_finish_mrq(host, cmd->mrq);
d129bceb
PO		 1104 return;
1105 }
7cb2c76f
PO		 1106 timeout--;
1107 mdelay(1);
1108 }
d129bceb 1109
3e1a6892 1110 timeout = jiffies;
1d4d7744
UH		 1111 if (!cmd->data && cmd->busy_timeout > 9000)
1112 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1113 else
1114 timeout += 10 * HZ;
d7422fb4 1115 sdhci_mod_timer(host, cmd->mrq, timeout);
d129bceb
PO		 1116
1117 host->cmd = cmd;
56a590dc 1118 if (sdhci_data_line_cmd(cmd)) {
7c89a3d9
AH		 1119 WARN_ON(host->data_cmd);
1120 host->data_cmd = cmd;
1121 }
d129bceb 1122
a3c7778f 1123 sdhci_prepare_data(host, cmd);
d129bceb 1124
4e4141a5 1125 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1126
e89d456f 1127 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1128
d129bceb 1129 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1130 pr_err("%s: Unsupported response type!\n",
d129bceb 1131 mmc_hostname(host->mmc));
17b0429d 1132 cmd->error = -EINVAL;
a6d3bdd5 1133 sdhci_finish_mrq(host, cmd->mrq);
d129bceb
PO		 1134 return;
1135 }
1136
1137 if (!(cmd->flags & MMC_RSP_PRESENT))
1138 flags = SDHCI_CMD_RESP_NONE;
1139 else if (cmd->flags & MMC_RSP_136)
1140 flags = SDHCI_CMD_RESP_LONG;
1141 else if (cmd->flags & MMC_RSP_BUSY)
1142 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1143 else
1144 flags = SDHCI_CMD_RESP_SHORT;
1145
1146 if (cmd->flags & MMC_RSP_CRC)
1147 flags |= SDHCI_CMD_CRC;
1148 if (cmd->flags & MMC_RSP_OPCODE)
1149 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1150
1151 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1152 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1153 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1154 flags |= SDHCI_CMD_DATA;
1155
4e4141a5 1156 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1157}
c0e55129 1158EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1159
1160static void sdhci_finish_command(struct sdhci_host *host)
1161{
e0a5640a 1162 struct mmc_command *cmd = host->cmd;
d129bceb
PO		 1163 int i;
1164
e0a5640a
AH		 1165 host->cmd = NULL;
1166
1167 if (cmd->flags & MMC_RSP_PRESENT) {
1168 if (cmd->flags & MMC_RSP_136) {
d129bceb
PO		 1169 /* CRC is stripped so we need to do some shifting. */
1170 for (i = 0;i < 4;i++) {
e0a5640a 1171 cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1172 SDHCI_RESPONSE + (3-i)*4) << 8;
1173 if (i != 3)
e0a5640a 1174 cmd->resp[i] |=
4e4141a5 1175 sdhci_readb(host,
d129bceb
PO		 1176 SDHCI_RESPONSE + (3-i)*4-1);
1177 }
1178 } else {
e0a5640a 1179 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1180 }
1181 }
1182
20845bef
AH		 1183 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1184 mmc_command_done(host->mmc, cmd->mrq);
1185
6bde8681
AH		 1186 /*
1187 * The host can send and interrupt when the busy state has
1188 * ended, allowing us to wait without wasting CPU cycles.
1189 * The busy signal uses DAT0 so this is similar to waiting
1190 * for data to complete.
1191 *
1192 * Note: The 1.0 specification is a bit ambiguous about this
1193 * feature so there might be some problems with older
1194 * controllers.
1195 */
e0a5640a
AH		 1196 if (cmd->flags & MMC_RSP_BUSY) {
1197 if (cmd->data) {
6bde8681
AH		 1198 DBG("Cannot wait for busy signal when also doing a data transfer");
1199 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
ea968023
AH		 1200 cmd == host->data_cmd) {
1201 /* Command complete before busy is ended */
6bde8681
AH		 1202 return;
1203 }
1204 }
1205
e89d456f 1206 /* Finished CMD23, now send actual command. */
a4c73aba
AH		 1207 if (cmd == cmd->mrq->sbc) {
1208 sdhci_send_command(host, cmd->mrq->cmd);
e89d456f 1209 } else {
e538fbe8 1210
e89d456f
AW		 1211 /* Processed actual command. */
1212 if (host->data && host->data_early)
1213 sdhci_finish_data(host);
d129bceb 1214
e0a5640a 1215 if (!cmd->data)
a6d3bdd5 1216 sdhci_finish_mrq(host, cmd->mrq);
e89d456f 1217 }
d129bceb
PO		 1218}
1219
52983382
KL		 1220static u16 sdhci_get_preset_value(struct sdhci_host *host)
1221{
d975f121 1222 u16 preset = 0;
52983382 1223
d975f121
RK		 1224 switch (host->timing) {
1225 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1226 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1227 break;
d975f121 1228 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1229 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1230 break;
d975f121 1231 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1232 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1233 break;
d975f121
RK		 1234 case MMC_TIMING_UHS_SDR104:
1235 case MMC_TIMING_MMC_HS200:
52983382
KL		 1236 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1237 break;
d975f121 1238 case MMC_TIMING_UHS_DDR50:
0dafa60e 1239 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1240 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1241 break;
e9fb05d5
AH		 1242 case MMC_TIMING_MMC_HS400:
1243 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1244 break;
52983382
KL		 1245 default:
1246 pr_warn("%s: Invalid UHS-I mode selected\n",
1247 mmc_hostname(host->mmc));
1248 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1249 break;
1250 }
1251 return preset;
1252}
1253
fb9ee047
LD		 1254u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1255 unsigned int *actual_clock)
d129bceb 1256{
c3ed3877 1257 int div = 0; /* Initialized for compiler warning */
df16219f 1258 int real_div = div, clk_mul = 1;
c3ed3877 1259 u16 clk = 0;
5497159c 1260 bool switch_base_clk = false;
d129bceb 1261
85105c53 1262 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1263 if (host->preset_enabled) {
52983382
KL		 1264 u16 pre_val;
1265
1266 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1267 pre_val = sdhci_get_preset_value(host);
1268 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1269 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1270 if (host->clk_mul &&
1271 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1272 clk = SDHCI_PROG_CLOCK_MODE;
1273 real_div = div + 1;
1274 clk_mul = host->clk_mul;
1275 } else {
1276 real_div = max_t(int, 1, div << 1);
1277 }
1278 goto clock_set;
1279 }
1280
c3ed3877
AN		 1281 /*
1282 * Check if the Host Controller supports Programmable Clock
1283 * Mode.
1284 */
1285 if (host->clk_mul) {
52983382
KL		 1286 for (div = 1; div <= 1024; div++) {
1287 if ((host->max_clk * host->clk_mul / div)
1288 <= clock)
1289 break;
1290 }
5497159c 1291 if ((host->max_clk * host->clk_mul / div) <= clock) {
1292 /*
1293 * Set Programmable Clock Mode in the Clock
1294 * Control register.
1295 */
1296 clk = SDHCI_PROG_CLOCK_MODE;
1297 real_div = div;
1298 clk_mul = host->clk_mul;
1299 div--;
1300 } else {
1301 /*
1302 * Divisor can be too small to reach clock
1303 * speed requirement. Then use the base clock.
1304 */
1305 switch_base_clk = true;
1306 }
1307 }
1308
1309 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1310 /* Version 3.00 divisors must be a multiple of 2. */
1311 if (host->max_clk <= clock)
1312 div = 1;
1313 else {
1314 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1315 div += 2) {
1316 if ((host->max_clk / div) <= clock)
1317 break;
1318 }
85105c53 1319 }
df16219f 1320 real_div = div;
c3ed3877 1321 div >>= 1;
d1955c3a
SG		 1322 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1323 && !div && host->max_clk <= 25000000)
1324 div = 1;
85105c53
ZG		 1325 }
1326 } else {
1327 /* Version 2.00 divisors must be a power of 2. */
0397526d 1328 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1329 if ((host->max_clk / div) <= clock)
1330 break;
1331 }
df16219f 1332 real_div = div;
c3ed3877 1333 div >>= 1;
d129bceb 1334 }
d129bceb 1335
52983382 1336clock_set:
03d6f5ff 1337 if (real_div)
fb9ee047 1338 *actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1339 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1340 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1341 << SDHCI_DIVIDER_HI_SHIFT;
fb9ee047
LD		 1342
1343 return clk;
1344}
1345EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1346
fec79673 1347void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
fb9ee047 1348{
5a436cc0 1349 ktime_t timeout;
fb9ee047 1350
d129bceb 1351 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1352 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1353
27f6cb16 1354 /* Wait max 20 ms */
5a436cc0 1355 timeout = ktime_add_ms(ktime_get(), 20);
4e4141a5 1356 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f 1357 & SDHCI_CLOCK_INT_STABLE)) {
5a436cc0 1358 if (ktime_after(ktime_get(), timeout)) {
2e4456f0
MV		 1359 pr_err("%s: Internal clock never stabilised.\n",
1360 mmc_hostname(host->mmc));
d129bceb
PO		 1361 sdhci_dumpregs(host);
1362 return;
1363 }
5a436cc0 1364 udelay(10);
7cb2c76f 1365 }
d129bceb
PO		 1366
1367 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1368 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1369}
fec79673
RH		 1370EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1371
1372void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1373{
1374 u16 clk;
1375
1376 host->mmc->actual_clock = 0;
1377
1378 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1379
1380 if (clock == 0)
1381 return;
1382
1383 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1384 sdhci_enable_clk(host, clk);
1385}
1771059c 1386EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1387
1dceb041
AH		 1388static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1389 unsigned short vdd)
146ad66e 1390{
3a48edc4 1391 struct mmc_host *mmc = host->mmc;
1dceb041 1392
1dceb041 1393 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1dceb041
AH		 1394
1395 if (mode != MMC_POWER_OFF)
1396 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1397 else
1398 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1399}
1400
606d3131
AH		 1401void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1402 unsigned short vdd)
1dceb041 1403{
8364248a 1404 u8 pwr = 0;
146ad66e 1405
24fbb3ca
RK		 1406 if (mode != MMC_POWER_OFF) {
1407 switch (1 << vdd) {
ae628903
PO		 1408 case MMC_VDD_165_195:
1409 pwr = SDHCI_POWER_180;
1410 break;
1411 case MMC_VDD_29_30:
1412 case MMC_VDD_30_31:
1413 pwr = SDHCI_POWER_300;
1414 break;
1415 case MMC_VDD_32_33:
1416 case MMC_VDD_33_34:
1417 pwr = SDHCI_POWER_330;
1418 break;
1419 default:
9d5de93f
AH		 1420 WARN(1, "%s: Invalid vdd %#x\n",
1421 mmc_hostname(host->mmc), vdd);
1422 break;
ae628903
PO		 1423 }
1424 }
1425
1426 if (host->pwr == pwr)
e921a8b6 1427 return;
146ad66e 1428
ae628903
PO		 1429 host->pwr = pwr;
1430
1431 if (pwr == 0) {
4e4141a5 1432 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1433 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1434 sdhci_runtime_pm_bus_off(host);
e921a8b6
RK		 1435 } else {
1436 /*
1437 * Spec says that we should clear the power reg before setting
1438 * a new value. Some controllers don't seem to like this though.
1439 */
1440 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1441 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1442
e921a8b6
RK		 1443 /*
1444 * At least the Marvell CaFe chip gets confused if we set the
1445 * voltage and set turn on power at the same time, so set the
1446 * voltage first.
1447 */
1448 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1449 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1450
e921a8b6 1451 pwr |= SDHCI_POWER_ON;
146ad66e 1452
e921a8b6 1453 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1454
e921a8b6
RK		 1455 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1456 sdhci_runtime_pm_bus_on(host);
f0710a55 1457
e921a8b6
RK		 1458 /*
1459 * Some controllers need an extra 10ms delay of 10ms before
1460 * they can apply clock after applying power
1461 */
1462 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1463 mdelay(10);
1464 }
1dceb041 1465}
606d3131 1466EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
918f4cbd 1467
606d3131
AH		 1468void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1469 unsigned short vdd)
1dceb041 1470{
606d3131
AH		 1471 if (IS_ERR(host->mmc->supply.vmmc))
1472 sdhci_set_power_noreg(host, mode, vdd);
1dceb041 1473 else
606d3131 1474 sdhci_set_power_reg(host, mode, vdd);
146ad66e 1475}
606d3131 1476EXPORT_SYMBOL_GPL(sdhci_set_power);
146ad66e 1477
d129bceb
PO		 1478/*****************************************************************************\
1479 * *
1480 * MMC callbacks *
1481 * *
1482\*****************************************************************************/
1483
1484static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1485{
1486 struct sdhci_host *host;
505a8680 1487 int present;
d129bceb
PO		 1488 unsigned long flags;
1489
1490 host = mmc_priv(mmc);
1491
04e079cf 1492 /* Firstly check card presence */
8d28b7a7 1493 present = mmc->ops->get_cd(mmc);
2836766a 1494
d129bceb
PO		 1495 spin_lock_irqsave(&host->lock, flags);
1496
061d17a6 1497 sdhci_led_activate(host);
e89d456f
AW		 1498
1499 /*
1500 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1501 * requests if Auto-CMD12 is enabled.
1502 */
0293d501 1503 if (sdhci_auto_cmd12(host, mrq)) {
c4512f79
JH		 1504 if (mrq->stop) {
1505 mrq->data->stop = NULL;
1506 mrq->stop = NULL;
1507 }
1508 }
d129bceb 1509
68d1fb7e 1510 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
a4c73aba 1511 mrq->cmd->error = -ENOMEDIUM;
a6d3bdd5 1512 sdhci_finish_mrq(host, mrq);
cf2b5eea 1513 } else {
8edf6371 1514 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1515 sdhci_send_command(host, mrq->sbc);
1516 else
1517 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1518 }
d129bceb 1519
5f25a66f 1520 mmiowb();
d129bceb
PO		 1521 spin_unlock_irqrestore(&host->lock, flags);
1522}
1523
2317f56c
RK		 1524void sdhci_set_bus_width(struct sdhci_host *host, int width)
1525{
1526 u8 ctrl;
1527
1528 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1529 if (width == MMC_BUS_WIDTH_8) {
1530 ctrl &= ~SDHCI_CTRL_4BITBUS;
1531 if (host->version >= SDHCI_SPEC_300)
1532 ctrl |= SDHCI_CTRL_8BITBUS;
1533 } else {
1534 if (host->version >= SDHCI_SPEC_300)
1535 ctrl &= ~SDHCI_CTRL_8BITBUS;
1536 if (width == MMC_BUS_WIDTH_4)
1537 ctrl |= SDHCI_CTRL_4BITBUS;
1538 else
1539 ctrl &= ~SDHCI_CTRL_4BITBUS;
1540 }
1541 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1542}
1543EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1544
96d7b78c
RK		 1545void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1546{
1547 u16 ctrl_2;
1548
1549 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1550 /* Select Bus Speed Mode for host */
1551 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1552 if ((timing == MMC_TIMING_MMC_HS200) ||
1553 (timing == MMC_TIMING_UHS_SDR104))
1554 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1555 else if (timing == MMC_TIMING_UHS_SDR12)
1556 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1557 else if (timing == MMC_TIMING_UHS_SDR25)
1558 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1559 else if (timing == MMC_TIMING_UHS_SDR50)
1560 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1561 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1562 (timing == MMC_TIMING_MMC_DDR52))
1563 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1564 else if (timing == MMC_TIMING_MMC_HS400)
1565 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1566 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1567}
1568EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1569
ded97e0b 1570static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
d129bceb 1571{
ded97e0b 1572 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 1573 u8 ctrl;
1574
84ec048b
AH		 1575 if (ios->power_mode == MMC_POWER_UNDEFINED)
1576 return;
1577
ceb6143b 1578 if (host->flags & SDHCI_DEVICE_DEAD) {
3a48edc4
TK		 1579 if (!IS_ERR(mmc->supply.vmmc) &&
1580 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1581 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1582 return;
1583 }
1e72859e 1584
d129bceb
PO		 1585 /*
1586 * Reset the chip on each power off.
1587 * Should clear out any weird states.
1588 */
1589 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1590 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1591 sdhci_reinit(host);
d129bceb
PO		 1592 }
1593
52983382 1594 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1595 (ios->power_mode == MMC_POWER_UP) &&
1596 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1597 sdhci_enable_preset_value(host, false);
1598
373073ef 1599 if (!ios->clock || ios->clock != host->clock) {
1771059c 1600 host->ops->set_clock(host, ios->clock);
373073ef 1601 host->clock = ios->clock;
03d6f5ff
AD		 1602
1603 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1604 host->clock) {
1605 host->timeout_clk = host->mmc->actual_clock ?
1606 host->mmc->actual_clock / 1000 :
1607 host->clock / 1000;
1608 host->mmc->max_busy_timeout =
1609 host->ops->get_max_timeout_count ?
1610 host->ops->get_max_timeout_count(host) :
1611 1 << 27;
1612 host->mmc->max_busy_timeout /= host->timeout_clk;
1613 }
373073ef 1614 }
d129bceb 1615
606d3131
AH		 1616 if (host->ops->set_power)
1617 host->ops->set_power(host, ios->power_mode, ios->vdd);
1618 else
1619 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1620
643a81ff
PR		 1621 if (host->ops->platform_send_init_74_clocks)
1622 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1623
2317f56c 1624 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1625
15ec4461 1626 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1627
3ab9c8da 1628 if ((ios->timing == MMC_TIMING_SD_HS ||
273c5414
JC		 1629 ios->timing == MMC_TIMING_MMC_HS ||
1630 ios->timing == MMC_TIMING_MMC_HS400 ||
1631 ios->timing == MMC_TIMING_MMC_HS200 ||
1632 ios->timing == MMC_TIMING_MMC_DDR52 ||
1633 ios->timing == MMC_TIMING_UHS_SDR50 ||
1634 ios->timing == MMC_TIMING_UHS_SDR104 ||
1635 ios->timing == MMC_TIMING_UHS_DDR50 ||
1636 ios->timing == MMC_TIMING_UHS_SDR25)
3ab9c8da 1637 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1638 ctrl |= SDHCI_CTRL_HISPD;
1639 else
1640 ctrl &= ~SDHCI_CTRL_HISPD;
1641
d6d50a15 1642 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1643 u16 clk, ctrl_2;
49c468fc 1644
da91a8f9 1645 if (!host->preset_enabled) {
758535c4 1646 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1647 /*
1648 * We only need to set Driver Strength if the
1649 * preset value enable is not set.
1650 */
da91a8f9 1651 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1652 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1653 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1654 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1655 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1656 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1657 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1658 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1659 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1660 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1661 else {
2e4456f0
MV		 1662 pr_warn("%s: invalid driver type, default to driver type B\n",
1663 mmc_hostname(mmc));
43e943a0
PG		 1664 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1665 }
d6d50a15
AN		 1666
1667 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1668 } else {
1669 /*
1670 * According to SDHC Spec v3.00, if the Preset Value
1671 * Enable in the Host Control 2 register is set, we
1672 * need to reset SD Clock Enable before changing High
1673 * Speed Enable to avoid generating clock gliches.
1674 */
758535c4
AN		 1675
1676 /* Reset SD Clock Enable */
1677 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1678 clk &= ~SDHCI_CLOCK_CARD_EN;
1679 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1680
1681 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1682
1683 /* Re-enable SD Clock */
1771059c 1684 host->ops->set_clock(host, host->clock);
d6d50a15 1685 }
49c468fc 1686
49c468fc
AN		 1687 /* Reset SD Clock Enable */
1688 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1689 clk &= ~SDHCI_CLOCK_CARD_EN;
1690 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1691
96d7b78c 1692 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1693 host->timing = ios->timing;
49c468fc 1694
52983382
KL		 1695 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1696 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1697 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1698 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1699 (ios->timing == MMC_TIMING_UHS_SDR104) ||
0dafa60e
JZ		 1700 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1701 (ios->timing == MMC_TIMING_MMC_DDR52))) {
52983382
KL		 1702 u16 preset;
1703
1704 sdhci_enable_preset_value(host, true);
1705 preset = sdhci_get_preset_value(host);
1706 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1707 >> SDHCI_PRESET_DRV_SHIFT;
1708 }
1709
49c468fc 1710 /* Re-enable SD Clock */
1771059c 1711 host->ops->set_clock(host, host->clock);
758535c4
AN		 1712 } else
1713 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1714
b8352260
LD		 1715 /*
1716 * Some (ENE) controllers go apeshit on some ios operation,
1717 * signalling timeout and CRC errors even on CMD0. Resetting
1718 * it on each ios seems to solve the problem.
1719 */
c63705e1 1720 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1721 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1722
5f25a66f 1723 mmiowb();
d129bceb
PO		 1724}
1725
ded97e0b 1726static int sdhci_get_cd(struct mmc_host *mmc)
66fd8ad5
AH		 1727{
1728 struct sdhci_host *host = mmc_priv(mmc);
ded97e0b 1729 int gpio_cd = mmc_gpio_get_cd(mmc);
94144a46
KL		 1730
1731 if (host->flags & SDHCI_DEVICE_DEAD)
1732 return 0;
1733
88af5655 1734 /* If nonremovable, assume that the card is always present. */
860951c5 1735 if (!mmc_card_is_removable(host->mmc))
94144a46
KL		 1736 return 1;
1737
88af5655
II		 1738 /*
1739 * Try slot gpio detect, if defined it take precedence
1740 * over build in controller functionality
1741 */
287980e4 1742 if (gpio_cd >= 0)
94144a46
KL		 1743 return !!gpio_cd;
1744
88af5655
II		 1745 /* If polling, assume that the card is always present. */
1746 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1747 return 1;
1748
94144a46
KL		 1749 /* Host native card detect */
1750 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1751}
1752
66fd8ad5 1753static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1754{
d129bceb 1755 unsigned long flags;
2dfb579c 1756 int is_readonly;
d129bceb 1757
d129bceb
PO		 1758 spin_lock_irqsave(&host->lock, flags);
1759
1e72859e 1760 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1761 is_readonly = 0;
1762 else if (host->ops->get_ro)
1763 is_readonly = host->ops->get_ro(host);
1e72859e 1764 else
2dfb579c
WS		 1765 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1766 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1767
1768 spin_unlock_irqrestore(&host->lock, flags);
1769
2dfb579c
WS		 1770 /* This quirk needs to be replaced by a callback-function later */
1771 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1772 !is_readonly : is_readonly;
d129bceb
PO		 1773}
1774
82b0e23a
TI		 1775#define SAMPLE_COUNT 5
1776
ded97e0b 1777static int sdhci_get_ro(struct mmc_host *mmc)
82b0e23a 1778{
ded97e0b 1779 struct sdhci_host *host = mmc_priv(mmc);
82b0e23a
TI		 1780 int i, ro_count;
1781
82b0e23a 1782 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1783 return sdhci_check_ro(host);
82b0e23a
TI		 1784
1785 ro_count = 0;
1786 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1787 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1788 if (++ro_count > SAMPLE_COUNT / 2)
1789 return 1;
1790 }
1791 msleep(30);
1792 }
1793 return 0;
1794}
1795
20758b66
AH		 1796static void sdhci_hw_reset(struct mmc_host *mmc)
1797{
1798 struct sdhci_host *host = mmc_priv(mmc);
1799
1800 if (host->ops && host->ops->hw_reset)
1801 host->ops->hw_reset(host);
1802}
1803
66fd8ad5
AH		 1804static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1805{
be138554 1806 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1807 if (enable)
b537f94c 1808 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1809 else
b537f94c
RK		 1810 host->ier &= ~SDHCI_INT_CARD_INT;
1811
1812 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1813 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1814 mmiowb();
1815 }
66fd8ad5
AH		 1816}
1817
1818static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1819{
1820 struct sdhci_host *host = mmc_priv(mmc);
1821 unsigned long flags;
f75979b7 1822
923713b3
HG		 1823 if (enable)
1824 pm_runtime_get_noresume(host->mmc->parent);
1825
66fd8ad5 1826 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1827 if (enable)
1828 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1829 else
1830 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1831
66fd8ad5 1832 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1833 spin_unlock_irqrestore(&host->lock, flags);
923713b3
HG		 1834
1835 if (!enable)
1836 pm_runtime_put_noidle(host->mmc->parent);
f75979b7
PO		 1837}
1838
ded97e0b
DA		 1839static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1840 struct mmc_ios *ios)
f2119df6 1841{
ded97e0b 1842 struct sdhci_host *host = mmc_priv(mmc);
20b92a30 1843 u16 ctrl;
6231f3de 1844 int ret;
f2119df6 1845
20b92a30
KL		 1846 /*
1847 * Signal Voltage Switching is only applicable for Host Controllers
1848 * v3.00 and above.
1849 */
1850 if (host->version < SDHCI_SPEC_300)
1851 return 0;
6231f3de 1852
f2119df6 1853 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1854
21f5998f 1855 switch (ios->signal_voltage) {
20b92a30 1856 case MMC_SIGNAL_VOLTAGE_330:
8cb851a4
AH		 1857 if (!(host->flags & SDHCI_SIGNALING_330))
1858 return -EINVAL;
20b92a30
KL		 1859 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1860 ctrl &= ~SDHCI_CTRL_VDD_180;
1861 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1862
3a48edc4 1863 if (!IS_ERR(mmc->supply.vqmmc)) {
761daa36 1864 ret = mmc_regulator_set_vqmmc(mmc, ios);
20b92a30 1865 if (ret) {
6606110d
JP		 1866 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1867 mmc_hostname(mmc));
20b92a30
KL		 1868 return -EIO;
1869 }
1870 }
1871 /* Wait for 5ms */
1872 usleep_range(5000, 5500);
f2119df6 1873
20b92a30
KL		 1874 /* 3.3V regulator output should be stable within 5 ms */
1875 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1876 if (!(ctrl & SDHCI_CTRL_VDD_180))
1877 return 0;
6231f3de 1878
6606110d
JP		 1879 pr_warn("%s: 3.3V regulator output did not became stable\n",
1880 mmc_hostname(mmc));
20b92a30
KL		 1881
1882 return -EAGAIN;
1883 case MMC_SIGNAL_VOLTAGE_180:
8cb851a4
AH		 1884 if (!(host->flags & SDHCI_SIGNALING_180))
1885 return -EINVAL;
3a48edc4 1886 if (!IS_ERR(mmc->supply.vqmmc)) {
761daa36 1887 ret = mmc_regulator_set_vqmmc(mmc, ios);
20b92a30 1888 if (ret) {
6606110d
JP		 1889 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1890 mmc_hostname(mmc));
20b92a30
KL		 1891 return -EIO;
1892 }
1893 }
6231f3de 1894
6231f3de
PR		 1895 /*
1896 * Enable 1.8V Signal Enable in the Host Control2
1897 * register
1898 */
20b92a30
KL		 1899 ctrl |= SDHCI_CTRL_VDD_180;
1900 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1901
9d967a61
VY		 1902 /* Some controller need to do more when switching */
1903 if (host->ops->voltage_switch)
1904 host->ops->voltage_switch(host);
1905
20b92a30
KL		 1906 /* 1.8V regulator output should be stable within 5 ms */
1907 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1908 if (ctrl & SDHCI_CTRL_VDD_180)
1909 return 0;
f2119df6 1910
6606110d
JP		 1911 pr_warn("%s: 1.8V regulator output did not became stable\n",
1912 mmc_hostname(mmc));
f2119df6 1913
20b92a30
KL		 1914 return -EAGAIN;
1915 case MMC_SIGNAL_VOLTAGE_120:
8cb851a4
AH		 1916 if (!(host->flags & SDHCI_SIGNALING_120))
1917 return -EINVAL;
3a48edc4 1918 if (!IS_ERR(mmc->supply.vqmmc)) {
761daa36 1919 ret = mmc_regulator_set_vqmmc(mmc, ios);
20b92a30 1920 if (ret) {
6606110d
JP		 1921 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1922 mmc_hostname(mmc));
20b92a30 1923 return -EIO;
f2119df6
AN		 1924 }
1925 }
6231f3de 1926 return 0;
20b92a30 1927 default:
f2119df6
AN		 1928 /* No signal voltage switch required */
1929 return 0;
20b92a30 1930 }
f2119df6
AN		 1931}
1932
20b92a30
KL		 1933static int sdhci_card_busy(struct mmc_host *mmc)
1934{
1935 struct sdhci_host *host = mmc_priv(mmc);
1936 u32 present_state;
1937
e613cc47 1938 /* Check whether DAT[0] is 0 */
20b92a30 1939 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
20b92a30 1940
e613cc47 1941 return !(present_state & SDHCI_DATA_0_LVL_MASK);
20b92a30
KL		 1942}
1943
b5540ce1
AH		 1944static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1945{
1946 struct sdhci_host *host = mmc_priv(mmc);
1947 unsigned long flags;
1948
1949 spin_lock_irqsave(&host->lock, flags);
1950 host->flags |= SDHCI_HS400_TUNING;
1951 spin_unlock_irqrestore(&host->lock, flags);
1952
1953 return 0;
1954}
1955
da4bc4f2
AH		 1956static void sdhci_start_tuning(struct sdhci_host *host)
1957{
1958 u16 ctrl;
1959
1960 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1961 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1962 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1963 ctrl |= SDHCI_CTRL_TUNED_CLK;
1964 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1965
1966 /*
1967 * As per the Host Controller spec v3.00, tuning command
1968 * generates Buffer Read Ready interrupt, so enable that.
1969 *
1970 * Note: The spec clearly says that when tuning sequence
1971 * is being performed, the controller does not generate
1972 * interrupts other than Buffer Read Ready interrupt. But
1973 * to make sure we don't hit a controller bug, we _only_
1974 * enable Buffer Read Ready interrupt here.
1975 */
1976 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1977 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1978}
1979
1980static void sdhci_end_tuning(struct sdhci_host *host)
1981{
1982 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1983 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1984}
1985
1986static void sdhci_reset_tuning(struct sdhci_host *host)
1987{
1988 u16 ctrl;
1989
1990 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1991 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1992 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1993 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1994}
1995
2a85ef25 1996static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
da4bc4f2
AH		 1997{
1998 sdhci_reset_tuning(host);
1999
2000 sdhci_do_reset(host, SDHCI_RESET_CMD);
2001 sdhci_do_reset(host, SDHCI_RESET_DATA);
2002
2003 sdhci_end_tuning(host);
2004
da4bc4f2 2005 mmc_abort_tuning(host->mmc, opcode);
da4bc4f2
AH		 2006}
2007
2008/*
2009 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2010 * tuning command does not have a data payload (or rather the hardware does it
2011 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2012 * interrupt setup is different to other commands and there is no timeout
2013 * interrupt so special handling is needed.
2014 */
2a85ef25 2015static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
da4bc4f2
AH		 2016{
2017 struct mmc_host *mmc = host->mmc;
c7836d15
MY		 2018 struct mmc_command cmd = {};
2019 struct mmc_request mrq = {};
2a85ef25
AH		 2020 unsigned long flags;
2021
2022 spin_lock_irqsave(&host->lock, flags);
da4bc4f2
AH		 2023
2024 cmd.opcode = opcode;
2025 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2026 cmd.mrq = &mrq;
2027
2028 mrq.cmd = &cmd;
2029 /*
2030 * In response to CMD19, the card sends 64 bytes of tuning
2031 * block to the Host Controller. So we set the block size
2032 * to 64 here.
2033 */
85336109
AH		 2034 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2035 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2036 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), SDHCI_BLOCK_SIZE);
2037 else
2038 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
da4bc4f2
AH		 2039
2040 /*
2041 * The tuning block is sent by the card to the host controller.
2042 * So we set the TRNS_READ bit in the Transfer Mode register.
2043 * This also takes care of setting DMA Enable and Multi Block
2044 * Select in the same register to 0.
2045 */
2046 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2047
2048 sdhci_send_command(host, &cmd);
2049
2050 host->cmd = NULL;
2051
2052 sdhci_del_timer(host, &mrq);
2053
2054 host->tuning_done = 0;
2055
2a85ef25 2056 mmiowb();
da4bc4f2
AH		 2057 spin_unlock_irqrestore(&host->lock, flags);
2058
2059 /* Wait for Buffer Read Ready interrupt */
2060 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2061 msecs_to_jiffies(50));
2062
da4bc4f2
AH		 2063}
2064
2a85ef25 2065static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
6b11e70b
AH		 2066{
2067 int i;
2068
2069 /*
2070 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2071 * of loops reaches 40 times.
2072 */
2073 for (i = 0; i < MAX_TUNING_LOOP; i++) {
2074 u16 ctrl;
2075
2a85ef25 2076 sdhci_send_tuning(host, opcode);
6b11e70b
AH		 2077
2078 if (!host->tuning_done) {
2079 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
2080 mmc_hostname(host->mmc));
2a85ef25 2081 sdhci_abort_tuning(host, opcode);
6b11e70b
AH		 2082 return;
2083 }
2084
2085 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2086 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2087 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2088 return; /* Success! */
2089 break;
2090 }
2091
2092 /* eMMC spec does not require a delay between tuning cycles */
2093 if (opcode == MMC_SEND_TUNING_BLOCK)
2094 mdelay(1);
2095 }
2096
2097 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2098 mmc_hostname(host->mmc));
2099 sdhci_reset_tuning(host);
2100}
2101
85a882c2 2102int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 2103{
4b6f37d3 2104 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 2105 int err = 0;
38e40bf5 2106 unsigned int tuning_count = 0;
b5540ce1 2107 bool hs400_tuning;
b513ea25 2108
b5540ce1 2109 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
b5540ce1 2110
38e40bf5
AH		 2111 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2112 tuning_count = host->tuning_count;
2113
b513ea25 2114 /*
9faac7b9
WY		 2115 * The Host Controller needs tuning in case of SDR104 and DDR50
2116 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2117 * the Capabilities register.
069c9f14
G		 2118 * If the Host Controller supports the HS200 mode then the
2119 * tuning function has to be executed.
b513ea25 2120 */
4b6f37d3 2121 switch (host->timing) {
b5540ce1 2122 /* HS400 tuning is done in HS200 mode */
e9fb05d5 2123 case MMC_TIMING_MMC_HS400:
b5540ce1 2124 err = -EINVAL;
2a85ef25 2125 goto out;
b5540ce1 2126
4b6f37d3 2127 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 2128 /*
2129 * Periodic re-tuning for HS400 is not expected to be needed, so
2130 * disable it here.
2131 */
2132 if (hs400_tuning)
2133 tuning_count = 0;
2134 break;
2135
4b6f37d3 2136 case MMC_TIMING_UHS_SDR104:
9faac7b9 2137 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 2138 break;
2139
2140 case MMC_TIMING_UHS_SDR50:
4228b213 2141 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
4b6f37d3
RK		 2142 break;
2143 /* FALLTHROUGH */
2144
2145 default:
2a85ef25 2146 goto out;
b513ea25
AN		 2147 }
2148
45251812 2149 if (host->ops->platform_execute_tuning) {
8a8fa879 2150 err = host->ops->platform_execute_tuning(host, opcode);
2a85ef25 2151 goto out;
45251812
DA		 2152 }
2153
6b11e70b 2154 host->mmc->retune_period = tuning_count;
b513ea25 2155
6b11e70b 2156 sdhci_start_tuning(host);
da4bc4f2 2157
2a85ef25 2158 __sdhci_execute_tuning(host, opcode);
cf2b5eea 2159
da4bc4f2 2160 sdhci_end_tuning(host);
2a85ef25 2161out:
8a8fa879 2162 host->flags &= ~SDHCI_HS400_TUNING;
6b11e70b 2163
b513ea25
AN		 2164 return err;
2165}
85a882c2 2166EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
b513ea25 2167
52983382 2168static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2169{
4d55c5a1
AN		 2170 /* Host Controller v3.00 defines preset value registers */
2171 if (host->version < SDHCI_SPEC_300)
2172 return;
2173
4d55c5a1
AN		 2174 /*
2175 * We only enable or disable Preset Value if they are not already
2176 * enabled or disabled respectively. Otherwise, we bail out.
2177 */
da91a8f9
RK		 2178 if (host->preset_enabled != enable) {
2179 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2180
2181 if (enable)
2182 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2183 else
2184 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2185
4d55c5a1 2186 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2187
2188 if (enable)
2189 host->flags |= SDHCI_PV_ENABLED;
2190 else
2191 host->flags &= ~SDHCI_PV_ENABLED;
2192
2193 host->preset_enabled = enable;
4d55c5a1 2194 }
66fd8ad5
AH		 2195}
2196
348487cb
HC		 2197static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2198 int err)
2199{
2200 struct sdhci_host *host = mmc_priv(mmc);
2201 struct mmc_data *data = mrq->data;
2202
f48f039c 2203 if (data->host_cookie != COOKIE_UNMAPPED)
771a3dc2
RK		 2204 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2205 data->flags & MMC_DATA_WRITE ?
2206 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2207
2208 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2209}
2210
d3c6aac3 2211static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
348487cb
HC		 2212{
2213 struct sdhci_host *host = mmc_priv(mmc);
2214
d31911b9 2215 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2216
2217 if (host->flags & SDHCI_REQ_USE_DMA)
94538e51 2218 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
348487cb
HC		 2219}
2220
5d0d11c5
AH		 2221static inline bool sdhci_has_requests(struct sdhci_host *host)
2222{
2223 return host->cmd || host->data_cmd;
2224}
2225
2226static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2227{
2228 if (host->data_cmd) {
2229 host->data_cmd->error = err;
2230 sdhci_finish_mrq(host, host->data_cmd->mrq);
2231 }
2232
2233 if (host->cmd) {
2234 host->cmd->error = err;
2235 sdhci_finish_mrq(host, host->cmd->mrq);
2236 }
2237}
2238
71e69211 2239static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2240{
71e69211 2241 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2242 unsigned long flags;
2836766a 2243 int present;
d129bceb 2244
722e1280
CD		 2245 /* First check if client has provided their own card event */
2246 if (host->ops->card_event)
2247 host->ops->card_event(host);
2248
d3940f27 2249 present = mmc->ops->get_cd(mmc);
2836766a 2250
d129bceb
PO		 2251 spin_lock_irqsave(&host->lock, flags);
2252
5d0d11c5
AH		 2253 /* Check sdhci_has_requests() first in case we are runtime suspended */
2254 if (sdhci_has_requests(host) && !present) {
a3c76eb9 2255 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2256 mmc_hostname(host->mmc));
a3c76eb9 2257 pr_err("%s: Resetting controller.\n",
66fd8ad5 2258 mmc_hostname(host->mmc));
d129bceb 2259
03231f9b
RK		 2260 sdhci_do_reset(host, SDHCI_RESET_CMD);
2261 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2262
5d0d11c5 2263 sdhci_error_out_mrqs(host, -ENOMEDIUM);
d129bceb
PO		 2264 }
2265
2266 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2267}
2268
2269static const struct mmc_host_ops sdhci_ops = {
2270 .request = sdhci_request,
348487cb
HC		 2271 .post_req = sdhci_post_req,
2272 .pre_req = sdhci_pre_req,
71e69211 2273 .set_ios = sdhci_set_ios,
94144a46 2274 .get_cd = sdhci_get_cd,
71e69211
GL		 2275 .get_ro = sdhci_get_ro,
2276 .hw_reset = sdhci_hw_reset,
2277 .enable_sdio_irq = sdhci_enable_sdio_irq,
2278 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2279 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2280 .execute_tuning = sdhci_execute_tuning,
71e69211 2281 .card_event = sdhci_card_event,
20b92a30 2282 .card_busy = sdhci_card_busy,
71e69211
GL		 2283};
2284
2285/*****************************************************************************\
2286 * *
2287 * Tasklets *
2288 * *
2289\*****************************************************************************/
2290
4e9f8fe5 2291static bool sdhci_request_done(struct sdhci_host *host)
d129bceb 2292{
d129bceb
PO		 2293 unsigned long flags;
2294 struct mmc_request *mrq;
4e9f8fe5 2295 int i;
d129bceb 2296
66fd8ad5
AH		 2297 spin_lock_irqsave(&host->lock, flags);
2298
4e9f8fe5
AH		 2299 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2300 mrq = host->mrqs_done[i];
6ebebeab 2301 if (mrq)
4e9f8fe5 2302 break;
66fd8ad5 2303 }
d129bceb 2304
4e9f8fe5
AH		 2305 if (!mrq) {
2306 spin_unlock_irqrestore(&host->lock, flags);
2307 return true;
2308 }
d129bceb 2309
d7422fb4
AH		 2310 sdhci_del_timer(host, mrq);
2311
054cedff
RK		 2312 /*
2313 * Always unmap the data buffers if they were mapped by
2314 * sdhci_prepare_data() whenever we finish with a request.
2315 * This avoids leaking DMA mappings on error.
2316 */
2317 if (host->flags & SDHCI_REQ_USE_DMA) {
2318 struct mmc_data *data = mrq->data;
2319
2320 if (data && data->host_cookie == COOKIE_MAPPED) {
2321 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2322 (data->flags & MMC_DATA_READ) ?
2323 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2324 data->host_cookie = COOKIE_UNMAPPED;
2325 }
2326 }
2327
d129bceb
PO		 2328 /*
2329 * The controller needs a reset of internal state machines
2330 * upon error conditions.
2331 */
0cc563ce 2332 if (sdhci_needs_reset(host, mrq)) {
6ebebeab
AH		 2333 /*
2334 * Do not finish until command and data lines are available for
2335 * reset. Note there can only be one other mrq, so it cannot
2336 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2337 * would both be null.
2338 */
2339 if (host->cmd || host->data_cmd) {
2340 spin_unlock_irqrestore(&host->lock, flags);
2341 return true;
2342 }
2343
645289dc 2344 /* Some controllers need this kick or reset won't work here */
8213af3b 2345 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2346 /* This is to force an update */
1771059c 2347 host->ops->set_clock(host, host->clock);
645289dc
PO		 2348
2349 /* Spec says we should do both at the same time, but Ricoh
2350 controllers do not like that. */
6ebebeab
AH		 2351 sdhci_do_reset(host, SDHCI_RESET_CMD);
2352 sdhci_do_reset(host, SDHCI_RESET_DATA);
ed1563de
AH		 2353
2354 host->pending_reset = false;
d129bceb
PO		 2355 }
2356
4e9f8fe5
AH		 2357 if (!sdhci_has_requests(host))
2358 sdhci_led_deactivate(host);
d129bceb 2359
6ebebeab
AH		 2360 host->mrqs_done[i] = NULL;
2361
5f25a66f 2362 mmiowb();
d129bceb
PO		 2363 spin_unlock_irqrestore(&host->lock, flags);
2364
2365 mmc_request_done(host->mmc, mrq);
4e9f8fe5
AH		 2366
2367 return false;
2368}
2369
2370static void sdhci_tasklet_finish(unsigned long param)
2371{
2372 struct sdhci_host *host = (struct sdhci_host *)param;
2373
2374 while (!sdhci_request_done(host))
2375 ;
d129bceb
PO		 2376}
2377
2378static void sdhci_timeout_timer(unsigned long data)
2379{
2380 struct sdhci_host *host;
2381 unsigned long flags;
2382
2383 host = (struct sdhci_host*)data;
2384
2385 spin_lock_irqsave(&host->lock, flags);
2386
d7422fb4
AH		 2387 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2388 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2389 mmc_hostname(host->mmc));
2390 sdhci_dumpregs(host);
2391
2392 host->cmd->error = -ETIMEDOUT;
2393 sdhci_finish_mrq(host, host->cmd->mrq);
2394 }
2395
2396 mmiowb();
2397 spin_unlock_irqrestore(&host->lock, flags);
2398}
2399
2400static void sdhci_timeout_data_timer(unsigned long data)
2401{
2402 struct sdhci_host *host;
2403 unsigned long flags;
2404
2405 host = (struct sdhci_host *)data;
2406
2407 spin_lock_irqsave(&host->lock, flags);
2408
2409 if (host->data || host->data_cmd ||
2410 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2e4456f0
MV		 2411 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2412 mmc_hostname(host->mmc));
d129bceb
PO		 2413 sdhci_dumpregs(host);
2414
2415 if (host->data) {
17b0429d 2416 host->data->error = -ETIMEDOUT;
d129bceb 2417 sdhci_finish_data(host);
d7422fb4
AH		 2418 } else if (host->data_cmd) {
2419 host->data_cmd->error = -ETIMEDOUT;
2420 sdhci_finish_mrq(host, host->data_cmd->mrq);
d129bceb 2421 } else {
d7422fb4
AH		 2422 host->cmd->error = -ETIMEDOUT;
2423 sdhci_finish_mrq(host, host->cmd->mrq);
d129bceb
PO		 2424 }
2425 }
2426
5f25a66f 2427 mmiowb();
d129bceb
PO		 2428 spin_unlock_irqrestore(&host->lock, flags);
2429}
2430
2431/*****************************************************************************\
2432 * *
2433 * Interrupt handling *
2434 * *
2435\*****************************************************************************/
2436
fc605f1d 2437static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
d129bceb 2438{
d129bceb 2439 if (!host->cmd) {
ed1563de
AH		 2440 /*
2441 * SDHCI recovers from errors by resetting the cmd and data
2442 * circuits. Until that is done, there very well might be more
2443 * interrupts, so ignore them in that case.
2444 */
2445 if (host->pending_reset)
2446 return;
2e4456f0
MV		 2447 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2448 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2449 sdhci_dumpregs(host);
2450 return;
2451 }
2452
ec014cba
RK		 2453 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2454 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2455 if (intmask & SDHCI_INT_TIMEOUT)
2456 host->cmd->error = -ETIMEDOUT;
2457 else
2458 host->cmd->error = -EILSEQ;
43b58b36 2459
71fcbda0
RK		 2460 /*
2461 * If this command initiates a data phase and a response
2462 * CRC error is signalled, the card can start transferring
2463 * data - the card may have received the command without
2464 * error. We must not terminate the mmc_request early.
2465 *
2466 * If the card did not receive the command or returned an
2467 * error which prevented it sending data, the data phase
2468 * will time out.
2469 */
2470 if (host->cmd->data &&
2471 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2472 SDHCI_INT_CRC) {
2473 host->cmd = NULL;
2474 return;
2475 }
2476
a6d3bdd5 2477 sdhci_finish_mrq(host, host->cmd->mrq);
e809517f
PO		 2478 return;
2479 }
2480
e809517f 2481 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2482 sdhci_finish_command(host);
d129bceb
PO		 2483}
2484
0957c333 2485#ifdef CONFIG_MMC_DEBUG
08621b18 2486static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2487{
2488 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2489 void *desc = host->adma_table;
6882a8c0
BD		 2490
2491 sdhci_dumpregs(host);
2492
2493 while (true) {
e57a5f61
AH		 2494 struct sdhci_adma2_64_desc *dma_desc = desc;
2495
2496 if (host->flags & SDHCI_USE_64_BIT_DMA)
2497 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2498 name, desc, le32_to_cpu(dma_desc->addr_hi),
2499 le32_to_cpu(dma_desc->addr_lo),
2500 le16_to_cpu(dma_desc->len),
2501 le16_to_cpu(dma_desc->cmd));
2502 else
2503 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2504 name, desc, le32_to_cpu(dma_desc->addr_lo),
2505 le16_to_cpu(dma_desc->len),
2506 le16_to_cpu(dma_desc->cmd));
6882a8c0 2507
76fe379a 2508 desc += host->desc_sz;
6882a8c0 2509
0545230f 2510 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2511 break;
2512 }
2513}
2514#else
08621b18 2515static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2516#endif
2517
d129bceb
PO		 2518static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2519{
069c9f14 2520 u32 command;
d129bceb 2521
b513ea25
AN		 2522 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2523 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2524 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2525 if (command == MMC_SEND_TUNING_BLOCK ||
2526 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2527 host->tuning_done = 1;
2528 wake_up(&host->buf_ready_int);
2529 return;
2530 }
2531 }
2532
d129bceb 2533 if (!host->data) {
7c89a3d9
AH		 2534 struct mmc_command *data_cmd = host->data_cmd;
2535
d129bceb 2536 /*
e809517f
PO		 2537 * The "data complete" interrupt is also used to
2538 * indicate that a busy state has ended. See comment
2539 * above in sdhci_cmd_irq().
d129bceb 2540 */
7c89a3d9 2541 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8 2542 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
69b962a6 2543 host->data_cmd = NULL;
7c89a3d9 2544 data_cmd->error = -ETIMEDOUT;
a6d3bdd5 2545 sdhci_finish_mrq(host, data_cmd->mrq);
c5abd5e8
MC		 2546 return;
2547 }
e809517f 2548 if (intmask & SDHCI_INT_DATA_END) {
69b962a6 2549 host->data_cmd = NULL;
e99783a4
CM		 2550 /*
2551 * Some cards handle busy-end interrupt
2552 * before the command completed, so make
2553 * sure we do things in the proper order.
2554 */
ea968023
AH		 2555 if (host->cmd == data_cmd)
2556 return;
2557
a6d3bdd5 2558 sdhci_finish_mrq(host, data_cmd->mrq);
e809517f
PO		 2559 return;
2560 }
2561 }
d129bceb 2562
ed1563de
AH		 2563 /*
2564 * SDHCI recovers from errors by resetting the cmd and data
2565 * circuits. Until that is done, there very well might be more
2566 * interrupts, so ignore them in that case.
2567 */
2568 if (host->pending_reset)
2569 return;
2570
2e4456f0
MV		 2571 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2572 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2573 sdhci_dumpregs(host);
2574
2575 return;
2576 }
2577
2578 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2579 host->data->error = -ETIMEDOUT;
22113efd
AL		 2580 else if (intmask & SDHCI_INT_DATA_END_BIT)
2581 host->data->error = -EILSEQ;
2582 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2583 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2584 != MMC_BUS_TEST_R)
17b0429d 2585 host->data->error = -EILSEQ;
6882a8c0 2586 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2587 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2588 sdhci_adma_show_error(host);
2134a922 2589 host->data->error = -EIO;
a4071fbb
HZ		 2590 if (host->ops->adma_workaround)
2591 host->ops->adma_workaround(host, intmask);
6882a8c0 2592 }
d129bceb 2593
17b0429d 2594 if (host->data->error)
d129bceb
PO		 2595 sdhci_finish_data(host);
2596 else {
a406f5a3 2597 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2598 sdhci_transfer_pio(host);
2599
6ba736a1
PO		 2600 /*
2601 * We currently don't do anything fancy with DMA
2602 * boundaries, but as we can't disable the feature
2603 * we need to at least restart the transfer.
f6a03cbf
MV		 2604 *
2605 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2606 * should return a valid address to continue from, but as
2607 * some controllers are faulty, don't trust them.
6ba736a1 2608 */
f6a03cbf
MV		 2609 if (intmask & SDHCI_INT_DMA_END) {
2610 u32 dmastart, dmanow;
2611 dmastart = sg_dma_address(host->data->sg);
2612 dmanow = dmastart + host->data->bytes_xfered;
2613 /*
2614 * Force update to the next DMA block boundary.
2615 */
2616 dmanow = (dmanow &
2617 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2618 SDHCI_DEFAULT_BOUNDARY_SIZE;
2619 host->data->bytes_xfered = dmanow - dmastart;
2620 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2621 " next 0x%08x\n",
2622 mmc_hostname(host->mmc), dmastart,
2623 host->data->bytes_xfered, dmanow);
2624 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2625 }
6ba736a1 2626
e538fbe8 2627 if (intmask & SDHCI_INT_DATA_END) {
7c89a3d9 2628 if (host->cmd == host->data_cmd) {
e538fbe8
PO		 2629 /*
2630 * Data managed to finish before the
2631 * command completed. Make sure we do
2632 * things in the proper order.
2633 */
2634 host->data_early = 1;
2635 } else {
2636 sdhci_finish_data(host);
2637 }
2638 }
d129bceb
PO		 2639 }
2640}
2641
7d12e780 2642static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2643{
781e989c 2644 irqreturn_t result = IRQ_NONE;
66fd8ad5 2645 struct sdhci_host *host = dev_id;
41005003 2646 u32 intmask, mask, unexpected = 0;
781e989c 2647 int max_loops = 16;
d129bceb
PO		 2648
2649 spin_lock(&host->lock);
2650
be138554 2651 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2652 spin_unlock(&host->lock);
655bca76 2653 return IRQ_NONE;
66fd8ad5
AH		 2654 }
2655
4e4141a5 2656 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2657 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2658 result = IRQ_NONE;
2659 goto out;
2660 }
2661
41005003
RK		 2662 do {
2663 /* Clear selected interrupts. */
2664 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2665 SDHCI_INT_BUS_POWER);
2666 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2667
41005003
RK		 2668 DBG("*** %s got interrupt: 0x%08x\n",
2669 mmc_hostname(host->mmc), intmask);
d129bceb 2670
41005003
RK		 2671 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2672 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2673 SDHCI_CARD_PRESENT;
d129bceb 2674
41005003
RK		 2675 /*
2676 * There is a observation on i.mx esdhc. INSERT
2677 * bit will be immediately set again when it gets
2678 * cleared, if a card is inserted. We have to mask
2679 * the irq to prevent interrupt storm which will
2680 * freeze the system. And the REMOVE gets the
2681 * same situation.
2682 *
2683 * More testing are needed here to ensure it works
2684 * for other platforms though.
2685 */
b537f94c
RK		 2686 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2687 SDHCI_INT_CARD_REMOVE);
2688 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2689 SDHCI_INT_CARD_INSERT;
2690 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2691 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2692
2693 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2694 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2695
2696 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2697 SDHCI_INT_CARD_REMOVE);
2698 result = IRQ_WAKE_THREAD;
41005003 2699 }
d129bceb 2700
41005003 2701 if (intmask & SDHCI_INT_CMD_MASK)
fc605f1d 2702 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
964f9ce2 2703
41005003
RK		 2704 if (intmask & SDHCI_INT_DATA_MASK)
2705 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2706
41005003
RK		 2707 if (intmask & SDHCI_INT_BUS_POWER)
2708 pr_err("%s: Card is consuming too much power!\n",
2709 mmc_hostname(host->mmc));
3192a28f 2710
f37b20eb
DA		 2711 if (intmask & SDHCI_INT_RETUNE)
2712 mmc_retune_needed(host->mmc);
2713
161e6d44
GKB		 2714 if ((intmask & SDHCI_INT_CARD_INT) &&
2715 (host->ier & SDHCI_INT_CARD_INT)) {
781e989c
RK		 2716 sdhci_enable_sdio_irq_nolock(host, false);
2717 host->thread_isr |= SDHCI_INT_CARD_INT;
2718 result = IRQ_WAKE_THREAD;
2719 }
f75979b7 2720
41005003
RK		 2721 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2722 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2723 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
f37b20eb 2724 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
f75979b7 2725
41005003
RK		 2726 if (intmask) {
2727 unexpected |= intmask;
2728 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2729 }
d129bceb 2730
781e989c
RK		 2731 if (result == IRQ_NONE)
2732 result = IRQ_HANDLED;
d129bceb 2733
41005003 2734 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2735 } while (intmask && --max_loops);
d129bceb
PO		 2736out:
2737 spin_unlock(&host->lock);
2738
6379b237
AS		 2739 if (unexpected) {
2740 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2741 mmc_hostname(host->mmc), unexpected);
2742 sdhci_dumpregs(host);
2743 }
f75979b7 2744
d129bceb
PO		 2745 return result;
2746}
2747
781e989c
RK		 2748static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2749{
2750 struct sdhci_host *host = dev_id;
2751 unsigned long flags;
2752 u32 isr;
2753
2754 spin_lock_irqsave(&host->lock, flags);
2755 isr = host->thread_isr;
2756 host->thread_isr = 0;
2757 spin_unlock_irqrestore(&host->lock, flags);
2758
3560db8e 2759 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d3940f27
AH		 2760 struct mmc_host *mmc = host->mmc;
2761
2762 mmc->ops->card_event(mmc);
2763 mmc_detect_change(mmc, msecs_to_jiffies(200));
3560db8e
RK		 2764 }
2765
781e989c
RK		 2766 if (isr & SDHCI_INT_CARD_INT) {
2767 sdio_run_irqs(host->mmc);
2768
2769 spin_lock_irqsave(&host->lock, flags);
2770 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2771 sdhci_enable_sdio_irq_nolock(host, true);
2772 spin_unlock_irqrestore(&host->lock, flags);
2773 }
2774
2775 return isr ? IRQ_HANDLED : IRQ_NONE;
2776}
2777
d129bceb
PO		 2778/*****************************************************************************\
2779 * *
2780 * Suspend/resume *
2781 * *
2782\*****************************************************************************/
2783
2784#ifdef CONFIG_PM
84d62605
LD		 2785/*
2786 * To enable wakeup events, the corresponding events have to be enabled in
2787 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2788 * Table' in the SD Host Controller Standard Specification.
2789 * It is useless to restore SDHCI_INT_ENABLE state in
2790 * sdhci_disable_irq_wakeups() since it will be set by
2791 * sdhci_enable_card_detection() or sdhci_init().
2792 */
ad080d79
KL		 2793void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2794{
2795 u8 val;
2796 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2797 | SDHCI_WAKE_ON_INT;
84d62605
LD		 2798 u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2799 SDHCI_INT_CARD_INT;
ad080d79
KL		 2800
2801 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2802 val |= mask ;
2803 /* Avoid fake wake up */
84d62605 2804 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
ad080d79 2805 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
84d62605
LD		 2806 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2807 }
ad080d79 2808 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
84d62605 2809 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
ad080d79
KL		 2810}
2811EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2812
0b10f478 2813static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2814{
2815 u8 val;
2816 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2817 | SDHCI_WAKE_ON_INT;
2818
2819 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2820 val &= ~mask;
2821 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2822}
d129bceb 2823
29495aa0 2824int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2825{
7260cf5e
AV		 2826 sdhci_disable_card_detection(host);
2827
66c39dfc 2828 mmc_retune_timer_stop(host->mmc);
cf2b5eea 2829
ad080d79 2830 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2831 host->ier = 0;
2832 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2833 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2834 free_irq(host->irq, host);
2835 } else {
2836 sdhci_enable_irq_wakeups(host);
2837 enable_irq_wake(host->irq);
2838 }
4ee14ec6 2839 return 0;
d129bceb
PO		 2840}
2841
b8c86fc5 2842EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2843
b8c86fc5
PO		 2844int sdhci_resume_host(struct sdhci_host *host)
2845{
d3940f27 2846 struct mmc_host *mmc = host->mmc;
4ee14ec6 2847 int ret = 0;
d129bceb 2848
a13abc7b 2849 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2850 if (host->ops->enable_dma)
2851 host->ops->enable_dma(host);
2852 }
d129bceb 2853
6308d290
AH		 2854 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2855 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2856 /* Card keeps power but host controller does not */
2857 sdhci_init(host, 0);
2858 host->pwr = 0;
2859 host->clock = 0;
d3940f27 2860 mmc->ops->set_ios(mmc, &mmc->ios);
6308d290
AH		 2861 } else {
2862 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2863 mmiowb();
2864 }
b8c86fc5 2865
14a7b416
HC		 2866 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2867 ret = request_threaded_irq(host->irq, sdhci_irq,
2868 sdhci_thread_irq, IRQF_SHARED,
2869 mmc_hostname(host->mmc), host);
2870 if (ret)
2871 return ret;
2872 } else {
2873 sdhci_disable_irq_wakeups(host);
2874 disable_irq_wake(host->irq);
2875 }
2876
7260cf5e
AV		 2877 sdhci_enable_card_detection(host);
2878
2f4cbb3d 2879 return ret;
d129bceb
PO		 2880}
2881
b8c86fc5 2882EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5 2883
66fd8ad5
AH		 2884int sdhci_runtime_suspend_host(struct sdhci_host *host)
2885{
2886 unsigned long flags;
66fd8ad5 2887
66c39dfc 2888 mmc_retune_timer_stop(host->mmc);
66fd8ad5
AH		 2889
2890 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2891 host->ier &= SDHCI_INT_CARD_INT;
2892 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2893 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2894 spin_unlock_irqrestore(&host->lock, flags);
2895
781e989c 2896 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2897
2898 spin_lock_irqsave(&host->lock, flags);
2899 host->runtime_suspended = true;
2900 spin_unlock_irqrestore(&host->lock, flags);
2901
8a125bad 2902 return 0;
66fd8ad5
AH		 2903}
2904EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2905
2906int sdhci_runtime_resume_host(struct sdhci_host *host)
2907{
d3940f27 2908 struct mmc_host *mmc = host->mmc;
66fd8ad5 2909 unsigned long flags;
8a125bad 2910 int host_flags = host->flags;
66fd8ad5
AH		 2911
2912 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2913 if (host->ops->enable_dma)
2914 host->ops->enable_dma(host);
2915 }
2916
2917 sdhci_init(host, 0);
2918
84ec048b
AH		 2919 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED) {
2920 /* Force clock and power re-program */
2921 host->pwr = 0;
2922 host->clock = 0;
2923 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
2924 mmc->ops->set_ios(mmc, &mmc->ios);
66fd8ad5 2925
84ec048b
AH		 2926 if ((host_flags & SDHCI_PV_ENABLED) &&
2927 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2928 spin_lock_irqsave(&host->lock, flags);
2929 sdhci_enable_preset_value(host, true);
2930 spin_unlock_irqrestore(&host->lock, flags);
2931 }
66fd8ad5 2932
84ec048b
AH		 2933 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
2934 mmc->ops->hs400_enhanced_strobe)
2935 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
2936 }
086b0ddb 2937
66fd8ad5
AH		 2938 spin_lock_irqsave(&host->lock, flags);
2939
2940 host->runtime_suspended = false;
2941
2942 /* Enable SDIO IRQ */
ef104333 2943 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2944 sdhci_enable_sdio_irq_nolock(host, true);
2945
2946 /* Enable Card Detection */
2947 sdhci_enable_card_detection(host);
2948
2949 spin_unlock_irqrestore(&host->lock, flags);
2950
8a125bad 2951 return 0;
66fd8ad5
AH		 2952}
2953EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2954
162d6f98 2955#endif /* CONFIG_PM */
66fd8ad5 2956
d129bceb
PO		 2957/*****************************************************************************\
2958 * *
b8c86fc5 2959 * Device allocation/registration *
d129bceb
PO		 2960 * *
2961\*****************************************************************************/
2962
b8c86fc5
PO		 2963struct sdhci_host *sdhci_alloc_host(struct device *dev,
2964 size_t priv_size)
d129bceb 2965{
d129bceb
PO		 2966 struct mmc_host *mmc;
2967 struct sdhci_host *host;
2968
b8c86fc5 2969 WARN_ON(dev == NULL);
d129bceb 2970
b8c86fc5 2971 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2972 if (!mmc)
b8c86fc5 2973 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2974
2975 host = mmc_priv(mmc);
2976 host->mmc = mmc;
bf60e592
AH		 2977 host->mmc_host_ops = sdhci_ops;
2978 mmc->ops = &host->mmc_host_ops;
d129bceb 2979
8cb851a4
AH		 2980 host->flags = SDHCI_SIGNALING_330;
2981
b8c86fc5
PO		 2982 return host;
2983}
8a4da143 2984
b8c86fc5 2985EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2986
7b91369b
AC		 2987static int sdhci_set_dma_mask(struct sdhci_host *host)
2988{
2989 struct mmc_host *mmc = host->mmc;
2990 struct device *dev = mmc_dev(mmc);
2991 int ret = -EINVAL;
2992
2993 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
2994 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2995
2996 /* Try 64-bit mask if hardware is capable of it */
2997 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2998 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
2999 if (ret) {
3000 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3001 mmc_hostname(mmc));
3002 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3003 }
3004 }
3005
3006 /* 32-bit mask as default & fallback */
3007 if (ret) {
3008 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3009 if (ret)
3010 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3011 mmc_hostname(mmc));
3012 }
3013
3014 return ret;
3015}
3016
6132a3bf
AH		 3017void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
3018{
3019 u16 v;
92e0c44b
ZB		 3020 u64 dt_caps_mask = 0;
3021 u64 dt_caps = 0;
6132a3bf
AH		 3022
3023 if (host->read_caps)
3024 return;
3025
3026 host->read_caps = true;
3027
3028 if (debug_quirks)
3029 host->quirks = debug_quirks;
3030
3031 if (debug_quirks2)
3032 host->quirks2 = debug_quirks2;
3033
3034 sdhci_do_reset(host, SDHCI_RESET_ALL);
3035
92e0c44b
ZB		 3036 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3037 "sdhci-caps-mask", &dt_caps_mask);
3038 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3039 "sdhci-caps", &dt_caps);
3040
6132a3bf
AH		 3041 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3042 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3043
3044 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3045 return;
3046
92e0c44b
ZB		 3047 if (caps) {
3048 host->caps = *caps;
3049 } else {
3050 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3051 host->caps &= ~lower_32_bits(dt_caps_mask);
3052 host->caps |= lower_32_bits(dt_caps);
3053 }
6132a3bf
AH		 3054
3055 if (host->version < SDHCI_SPEC_300)
3056 return;
3057
92e0c44b
ZB		 3058 if (caps1) {
3059 host->caps1 = *caps1;
3060 } else {
3061 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3062 host->caps1 &= ~upper_32_bits(dt_caps_mask);
3063 host->caps1 |= upper_32_bits(dt_caps);
3064 }
6132a3bf
AH		 3065}
3066EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3067
52f5336d 3068int sdhci_setup_host(struct sdhci_host *host)
b8c86fc5
PO		 3069{
3070 struct mmc_host *mmc;
f2119df6
AN		 3071 u32 max_current_caps;
3072 unsigned int ocr_avail;
f5fa92e5 3073 unsigned int override_timeout_clk;
59241757 3074 u32 max_clk;
b8c86fc5 3075 int ret;
d129bceb 3076
b8c86fc5
PO		 3077 WARN_ON(host == NULL);
3078 if (host == NULL)
3079 return -EINVAL;
d129bceb 3080
b8c86fc5 3081 mmc = host->mmc;
d129bceb 3082
efba142b
JH		 3083 /*
3084 * If there are external regulators, get them. Note this must be done
3085 * early before resetting the host and reading the capabilities so that
3086 * the host can take the appropriate action if regulators are not
3087 * available.
3088 */
3089 ret = mmc_regulator_get_supply(mmc);
3090 if (ret == -EPROBE_DEFER)
3091 return ret;
3092
6132a3bf 3093 sdhci_read_caps(host);
d129bceb 3094
f5fa92e5
AH		 3095 override_timeout_clk = host->timeout_clk;
3096
85105c53 3097 if (host->version > SDHCI_SPEC_300) {
2e4456f0
MV		 3098 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3099 mmc_hostname(mmc), host->version);
4a965505
PO		 3100 }
3101
b8c86fc5 3102 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 3103 host->flags |= SDHCI_USE_SDMA;
28da3589 3104 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
a13abc7b 3105 DBG("Controller doesn't have SDMA capability\n");
67435274 3106 else
a13abc7b 3107 host->flags |= SDHCI_USE_SDMA;
d129bceb 3108
b8c86fc5 3109 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 3110 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 3111 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 3112 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 3113 }
3114
f2119df6 3115 if ((host->version >= SDHCI_SPEC_200) &&
28da3589 3116 (host->caps & SDHCI_CAN_DO_ADMA2))
a13abc7b 3117 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 3118
3119 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3120 (host->flags & SDHCI_USE_ADMA)) {
3121 DBG("Disabling ADMA as it is marked broken\n");
3122 host->flags &= ~SDHCI_USE_ADMA;
3123 }
3124
e57a5f61
AH		 3125 /*
3126 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3127 * and *must* do 64-bit DMA. A driver has the opportunity to change
3128 * that during the first call to ->enable_dma(). Similarly
3129 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3130 * implement.
3131 */
28da3589 3132 if (host->caps & SDHCI_CAN_64BIT)
e57a5f61
AH		 3133 host->flags |= SDHCI_USE_64_BIT_DMA;
3134
a13abc7b 3135 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
7b91369b
AC		 3136 ret = sdhci_set_dma_mask(host);
3137
3138 if (!ret && host->ops->enable_dma)
3139 ret = host->ops->enable_dma(host);
3140
3141 if (ret) {
3142 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3143 mmc_hostname(mmc));
3144 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3145
3146 ret = 0;
d129bceb
PO		 3147 }
3148 }
3149
e57a5f61
AH		 3150 /* SDMA does not support 64-bit DMA */
3151 if (host->flags & SDHCI_USE_64_BIT_DMA)
3152 host->flags &= ~SDHCI_USE_SDMA;
3153
2134a922 3154 if (host->flags & SDHCI_USE_ADMA) {
e66e61cb
RK		 3155 dma_addr_t dma;
3156 void *buf;
3157
2134a922 3158 /*
76fe379a
AH		 3159 * The DMA descriptor table size is calculated as the maximum
3160 * number of segments times 2, to allow for an alignment
3161 * descriptor for each segment, plus 1 for a nop end descriptor,
3162 * all multipled by the descriptor size.
2134a922 3163 */
e57a5f61
AH		 3164 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3165 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3166 SDHCI_ADMA2_64_DESC_SZ;
e57a5f61 3167 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
e57a5f61
AH		 3168 } else {
3169 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3170 SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 3171 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 3172 }
e66e61cb 3173
04a5ae6f 3174 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
e66e61cb
RK		 3175 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3176 host->adma_table_sz, &dma, GFP_KERNEL);
3177 if (!buf) {
6606110d 3178 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 3179 mmc_hostname(mmc));
3180 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 3181 } else if ((dma + host->align_buffer_sz) &
3182 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 3183 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3184 mmc_hostname(mmc));
d1e49f77 3185 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 3186 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3187 host->adma_table_sz, buf, dma);
3188 } else {
3189 host->align_buffer = buf;
3190 host->align_addr = dma;
edd63fcc 3191
e66e61cb
RK		 3192 host->adma_table = buf + host->align_buffer_sz;
3193 host->adma_addr = dma + host->align_buffer_sz;
3194 }
2134a922
PO		 3195 }
3196
7659150c
PO		 3197 /*
3198 * If we use DMA, then it's up to the caller to set the DMA
3199 * mask, but PIO does not need the hw shim so we set a new
3200 * mask here in that case.
3201 */
a13abc7b 3202 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 3203 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 3204 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 3205 }
d129bceb 3206
c4687d5f 3207 if (host->version >= SDHCI_SPEC_300)
28da3589 3208 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 3209 >> SDHCI_CLOCK_BASE_SHIFT;
3210 else
28da3589 3211 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 3212 >> SDHCI_CLOCK_BASE_SHIFT;
3213
4240ff0a 3214 host->max_clk *= 1000000;
f27f47ef
AV		 3215 if (host->max_clk == 0 || host->quirks &
3216 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 3217 if (!host->ops->get_max_clock) {
2e4456f0
MV		 3218 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3219 mmc_hostname(mmc));
eb5c20de
AH		 3220 ret = -ENODEV;
3221 goto undma;
4240ff0a
BD		 3222 }
3223 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 3224 }
d129bceb 3225
c3ed3877
AN		 3226 /*
3227 * In case of Host Controller v3.00, find out whether clock
3228 * multiplier is supported.
3229 */
28da3589 3230 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
c3ed3877
AN		 3231 SDHCI_CLOCK_MUL_SHIFT;
3232
3233 /*
3234 * In case the value in Clock Multiplier is 0, then programmable
3235 * clock mode is not supported, otherwise the actual clock
3236 * multiplier is one more than the value of Clock Multiplier
3237 * in the Capabilities Register.
3238 */
3239 if (host->clk_mul)
3240 host->clk_mul += 1;
3241
d129bceb
PO		 3242 /*
3243 * Set host parameters.
3244 */
59241757
DA		 3245 max_clk = host->max_clk;
3246
ce5f036b 3247 if (host->ops->get_min_clock)
a9e58f25 3248 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3249 else if (host->version >= SDHCI_SPEC_300) {
3250 if (host->clk_mul) {
3251 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 3252 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 3253 } else
3254 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3255 } else
0397526d 3256 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3257
d310ae49 3258 if (!mmc->f_max || mmc->f_max > max_clk)
59241757
DA		 3259 mmc->f_max = max_clk;
3260
28aab053 3261 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
28da3589 3262 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
28aab053
AD		 3263 SDHCI_TIMEOUT_CLK_SHIFT;
3264 if (host->timeout_clk == 0) {
3265 if (host->ops->get_timeout_clock) {
3266 host->timeout_clk =
3267 host->ops->get_timeout_clock(host);
3268 } else {
3269 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3270 mmc_hostname(mmc));
eb5c20de
AH		 3271 ret = -ENODEV;
3272 goto undma;
28aab053 3273 }
272308ca 3274 }
272308ca 3275
28da3589 3276 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
28aab053 3277 host->timeout_clk *= 1000;
272308ca 3278
99513624
AH		 3279 if (override_timeout_clk)
3280 host->timeout_clk = override_timeout_clk;
3281
28aab053 3282 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3283 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3284 mmc->max_busy_timeout /= host->timeout_clk;
3285 }
58d1246d 3286
e89d456f 3287 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3288 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3289
3290 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3291 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3292
8edf6371 3293 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3294 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3295 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3296 !(host->flags & SDHCI_USE_SDMA)) &&
3297 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3298 host->flags |= SDHCI_AUTO_CMD23;
3299 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3300 } else {
3301 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3302 }
3303
15ec4461
PR		 3304 /*
3305 * A controller may support 8-bit width, but the board itself
3306 * might not have the pins brought out. Boards that support
3307 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3308 * their platform code before calling sdhci_add_host(), and we
3309 * won't assume 8-bit width for hosts without that CAP.
3310 */
5fe23c7f 3311 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3312 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3313
63ef5d8c
JH		 3314 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3315 mmc->caps &= ~MMC_CAP_CMD23;
3316
28da3589 3317 if (host->caps & SDHCI_CAN_DO_HISPD)
a29e7e18 3318 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3319
176d1ed4 3320 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
860951c5 3321 mmc_card_is_removable(mmc) &&
287980e4 3322 mmc_gpio_get_cd(host->mmc) < 0)
68d1fb7e
AV		 3323 mmc->caps |= MMC_CAP_NEEDS_POLL;
3324
6231f3de 3325 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3326 if (!IS_ERR(mmc->supply.vqmmc)) {
3327 ret = regulator_enable(mmc->supply.vqmmc);
3328 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3329 1950000))
28da3589
AH		 3330 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3331 SDHCI_SUPPORT_SDR50 |
3332 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3333 if (ret) {
3334 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3335 mmc_hostname(mmc), ret);
4bb74313 3336 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3337 }
8363c374 3338 }
6231f3de 3339
28da3589
AH		 3340 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3341 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3342 SDHCI_SUPPORT_DDR50);
3343 }
6a66180a 3344
4188bba0 3345 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
28da3589
AH		 3346 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3347 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3348 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3349
3350 /* SDR104 supports also implies SDR50 support */
28da3589 3351 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
f2119df6 3352 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3353 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3354 * field can be promoted to support HS200.
3355 */
549c0b18 3356 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3357 mmc->caps2 |= MMC_CAP2_HS200;
28da3589 3358 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
f2119df6 3359 mmc->caps |= MMC_CAP_UHS_SDR50;
28da3589 3360 }
f2119df6 3361
e9fb05d5 3362 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
28da3589 3363 (host->caps1 & SDHCI_SUPPORT_HS400))
e9fb05d5
AH		 3364 mmc->caps2 |= MMC_CAP2_HS400;
3365
549c0b18
AH		 3366 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3367 (IS_ERR(mmc->supply.vqmmc) ||
3368 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3369 1300000)))
3370 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3371
28da3589
AH		 3372 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3373 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3374 mmc->caps |= MMC_CAP_UHS_DDR50;
3375
069c9f14 3376 /* Does the host need tuning for SDR50? */
28da3589 3377 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
b513ea25
AN		 3378 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3379
d6d50a15 3380 /* Driver Type(s) (A, C, D) supported by the host */
28da3589 3381 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
d6d50a15 3382 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
28da3589 3383 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
d6d50a15 3384 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
28da3589 3385 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
d6d50a15
AN		 3386 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3387
cf2b5eea 3388 /* Initial value for re-tuning timer count */
28da3589
AH		 3389 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3390 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
cf2b5eea
AN		 3391
3392 /*
3393 * In case Re-tuning Timer is not disabled, the actual value of
3394 * re-tuning timer will be 2 ^ (n - 1).
3395 */
3396 if (host->tuning_count)
3397 host->tuning_count = 1 << (host->tuning_count - 1);
3398
3399 /* Re-tuning mode supported by the Host Controller */
28da3589 3400 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
cf2b5eea
AN		 3401 SDHCI_RETUNING_MODE_SHIFT;
3402
8f230f45 3403 ocr_avail = 0;
bad37e1a 3404
f2119df6
AN		 3405 /*
3406 * According to SD Host Controller spec v3.00, if the Host System
3407 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3408 * the value is meaningful only if Voltage Support in the Capabilities
3409 * register is set. The actual current value is 4 times the register
3410 * value.
3411 */
3412 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3413 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3414 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3415 if (curr > 0) {
3416
3417 /* convert to SDHCI_MAX_CURRENT format */
3418 curr = curr/1000; /* convert to mA */
3419 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3420
3421 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3422 max_current_caps =
3423 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3424 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3425 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3426 }
3427 }
f2119df6 3428
28da3589 3429 if (host->caps & SDHCI_CAN_VDD_330) {
8f230f45 3430 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3431
55c4665e 3432 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3433 SDHCI_MAX_CURRENT_330_MASK) >>
3434 SDHCI_MAX_CURRENT_330_SHIFT) *
3435 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 3436 }
28da3589 3437 if (host->caps & SDHCI_CAN_VDD_300) {
8f230f45 3438 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3439
55c4665e 3440 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3441 SDHCI_MAX_CURRENT_300_MASK) >>
3442 SDHCI_MAX_CURRENT_300_SHIFT) *
3443 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 3444 }
28da3589 3445 if (host->caps & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3446 ocr_avail |= MMC_VDD_165_195;
3447
55c4665e 3448 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3449 SDHCI_MAX_CURRENT_180_MASK) >>
3450 SDHCI_MAX_CURRENT_180_SHIFT) *
3451 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3452 }
3453
5fd26c7e
UH		 3454 /* If OCR set by host, use it instead. */
3455 if (host->ocr_mask)
3456 ocr_avail = host->ocr_mask;
3457
3458 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3459 if (mmc->ocr_avail)
52221610 3460 ocr_avail = mmc->ocr_avail;
3a48edc4 3461
8f230f45
TI		 3462 mmc->ocr_avail = ocr_avail;
3463 mmc->ocr_avail_sdio = ocr_avail;
3464 if (host->ocr_avail_sdio)
3465 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3466 mmc->ocr_avail_sd = ocr_avail;
3467 if (host->ocr_avail_sd)
3468 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3469 else /* normal SD controllers don't support 1.8V */
3470 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3471 mmc->ocr_avail_mmc = ocr_avail;
3472 if (host->ocr_avail_mmc)
3473 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3474
3475 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 3476 pr_err("%s: Hardware doesn't report any support voltages.\n",
3477 mmc_hostname(mmc));
eb5c20de
AH		 3478 ret = -ENODEV;
3479 goto unreg;
146ad66e
PO		 3480 }
3481
8cb851a4
AH		 3482 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3483 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3484 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3485 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3486 host->flags |= SDHCI_SIGNALING_180;
3487
3488 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3489 host->flags |= SDHCI_SIGNALING_120;
3490
d129bceb
PO		 3491 spin_lock_init(&host->lock);
3492
3493 /*
2134a922
PO		 3494 * Maximum number of segments. Depends on if the hardware
3495 * can do scatter/gather or not.
d129bceb 3496 */
2134a922 3497 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3498 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3499 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3500 mmc->max_segs = 1;
2134a922 3501 else /* PIO */
4fb213f8 3502 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3503
3504 /*
ac00531d
AH		 3505 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3506 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3507 * is less anyway.
d129bceb 3508 */
55db890a 3509 mmc->max_req_size = 524288;
d129bceb
PO		 3510
3511 /*
3512 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3513 * of bytes. When doing hardware scatter/gather, each entry cannot
3514 * be larger than 64 KiB though.
d129bceb 3515 */
30652aa3
OJ		 3516 if (host->flags & SDHCI_USE_ADMA) {
3517 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3518 mmc->max_seg_size = 65535;
3519 else
3520 mmc->max_seg_size = 65536;
3521 } else {
2134a922 3522 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3523 }
d129bceb 3524
fe4a3c7a
PO		 3525 /*
3526 * Maximum block size. This varies from controller to controller and
3527 * is specified in the capabilities register.
3528 */
0633f654
AV		 3529 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3530 mmc->max_blk_size = 2;
3531 } else {
28da3589 3532 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3533 SDHCI_MAX_BLOCK_SHIFT;
3534 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3535 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3536 mmc_hostname(mmc));
0633f654
AV		 3537 mmc->max_blk_size = 0;
3538 }
3539 }
3540
3541 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3542
55db890a
PO		 3543 /*
3544 * Maximum block count.
3545 */
1388eefd 3546 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3547
52f5336d
AH		 3548 return 0;
3549
3550unreg:
3551 if (!IS_ERR(mmc->supply.vqmmc))
3552 regulator_disable(mmc->supply.vqmmc);
3553undma:
3554 if (host->align_buffer)
3555 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3556 host->adma_table_sz, host->align_buffer,
3557 host->align_addr);
3558 host->adma_table = NULL;
3559 host->align_buffer = NULL;
3560
3561 return ret;
3562}
3563EXPORT_SYMBOL_GPL(sdhci_setup_host);
3564
3565int __sdhci_add_host(struct sdhci_host *host)
3566{
3567 struct mmc_host *mmc = host->mmc;
3568 int ret;
3569
d129bceb
PO		 3570 /*
3571 * Init tasklets.
3572 */
d129bceb
PO		 3573 tasklet_init(&host->finish_tasklet,
3574 sdhci_tasklet_finish, (unsigned long)host);
3575
e4cad1b5 3576 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d7422fb4
AH		 3577 setup_timer(&host->data_timer, sdhci_timeout_data_timer,
3578 (unsigned long)host);
d129bceb 3579
250fb7b4 3580 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3581
2af502ca
SG		 3582 sdhci_init(host, 0);
3583
781e989c
RK		 3584 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3585 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3586 if (ret) {
3587 pr_err("%s: Failed to request IRQ %d: %d\n",
3588 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3589 goto untasklet;
0fc81ee3 3590 }
d129bceb 3591
d129bceb
PO		 3592#ifdef CONFIG_MMC_DEBUG
3593 sdhci_dumpregs(host);
3594#endif
3595
061d17a6 3596 ret = sdhci_led_register(host);
0fc81ee3
MB		 3597 if (ret) {
3598 pr_err("%s: Failed to register LED device: %d\n",
3599 mmc_hostname(mmc), ret);
eb5c20de 3600 goto unirq;
0fc81ee3 3601 }
2f730fec 3602
5f25a66f
PO		 3603 mmiowb();
3604
eb5c20de
AH		 3605 ret = mmc_add_host(mmc);
3606 if (ret)
3607 goto unled;
d129bceb 3608
a3c76eb9 3609 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3610 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3611 (host->flags & SDHCI_USE_ADMA) ?
3612 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3613 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3614
7260cf5e
AV		 3615 sdhci_enable_card_detection(host);
3616
d129bceb
PO		 3617 return 0;
3618
eb5c20de 3619unled:
061d17a6 3620 sdhci_led_unregister(host);
eb5c20de 3621unirq:
03231f9b 3622 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3623 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3624 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec 3625 free_irq(host->irq, host);
8ef1a143 3626untasklet:
d129bceb 3627 tasklet_kill(&host->finish_tasklet);
52f5336d 3628
eb5c20de
AH		 3629 if (!IS_ERR(mmc->supply.vqmmc))
3630 regulator_disable(mmc->supply.vqmmc);
52f5336d 3631
eb5c20de
AH		 3632 if (host->align_buffer)
3633 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3634 host->adma_table_sz, host->align_buffer,
3635 host->align_addr);
3636 host->adma_table = NULL;
3637 host->align_buffer = NULL;
d129bceb
PO		 3638
3639 return ret;
3640}
52f5336d
AH		 3641EXPORT_SYMBOL_GPL(__sdhci_add_host);
3642
3643int sdhci_add_host(struct sdhci_host *host)
3644{
3645 int ret;
3646
3647 ret = sdhci_setup_host(host);
3648 if (ret)
3649 return ret;
d129bceb 3650
52f5336d
AH		 3651 return __sdhci_add_host(host);
3652}
b8c86fc5 3653EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3654
1e72859e 3655void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3656{
3a48edc4 3657 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3658 unsigned long flags;
3659
3660 if (dead) {
3661 spin_lock_irqsave(&host->lock, flags);
3662
3663 host->flags |= SDHCI_DEVICE_DEAD;
3664
5d0d11c5 3665 if (sdhci_has_requests(host)) {
a3c76eb9 3666 pr_err("%s: Controller removed during "
4e743f1f 3667 " transfer!\n", mmc_hostname(mmc));
5d0d11c5 3668 sdhci_error_out_mrqs(host, -ENOMEDIUM);
1e72859e
PO		 3669 }
3670
3671 spin_unlock_irqrestore(&host->lock, flags);
3672 }
3673
7260cf5e
AV		 3674 sdhci_disable_card_detection(host);
3675
4e743f1f 3676 mmc_remove_host(mmc);
d129bceb 3677
061d17a6 3678 sdhci_led_unregister(host);
2f730fec 3679
1e72859e 3680 if (!dead)
03231f9b 3681 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3682
b537f94c
RK		 3683 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3684 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3685 free_irq(host->irq, host);
3686
3687 del_timer_sync(&host->timer);
d7422fb4 3688 del_timer_sync(&host->data_timer);
d129bceb 3689
d129bceb 3690 tasklet_kill(&host->finish_tasklet);
2134a922 3691
3a48edc4
TK		 3692 if (!IS_ERR(mmc->supply.vqmmc))
3693 regulator_disable(mmc->supply.vqmmc);
6231f3de 3694
edd63fcc 3695 if (host->align_buffer)
e66e61cb
RK		 3696 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3697 host->adma_table_sz, host->align_buffer,
3698 host->align_addr);
2134a922 3699
4efaa6fb 3700 host->adma_table = NULL;
2134a922 3701 host->align_buffer = NULL;
d129bceb
PO		 3702}
3703
b8c86fc5 3704EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3705
b8c86fc5 3706void sdhci_free_host(struct sdhci_host *host)
d129bceb 3707{
b8c86fc5 3708 mmc_free_host(host->mmc);
d129bceb
PO		 3709}
3710
b8c86fc5 3711EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3712
3713/*****************************************************************************\
3714 * *
3715 * Driver init/exit *
3716 * *
3717\*****************************************************************************/
3718
3719static int __init sdhci_drv_init(void)
3720{
a3c76eb9 3721 pr_info(DRIVER_NAME
52fbf9c9 3722 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3723 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3724
b8c86fc5 3725 return 0;
d129bceb
PO		 3726}
3727
3728static void __exit sdhci_drv_exit(void)
3729{
d129bceb
PO		 3730}
3731
3732module_init(sdhci_drv_init);
3733module_exit(sdhci_drv_exit);
3734
df673b22 3735module_param(debug_quirks, uint, 0444);
66fd8ad5 3736module_param(debug_quirks2, uint, 0444);
67435274 3737
32710e8f 3738MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3739MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3740MODULE_LICENSE("GPL");
67435274 3741
df673b22 3742MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3743MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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