]>
Commit | Line | Data |
---|---|---|
d129bceb | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver |
d129bceb | 3 | * |
b69c9058 | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
d129bceb PO |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or (at | |
9 | * your option) any later version. | |
84c46a53 PO |
10 | * |
11 | * Thanks to the following companies for their support: | |
12 | * | |
13 | * - JMicron (hardware and technical support) | |
d129bceb PO |
14 | */ |
15 | ||
d129bceb PO |
16 | #include <linux/delay.h> |
17 | #include <linux/highmem.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/dma-mapping.h> | |
11763609 | 20 | #include <linux/scatterlist.h> |
d129bceb | 21 | |
2f730fec PO |
22 | #include <linux/leds.h> |
23 | ||
d129bceb | 24 | #include <linux/mmc/host.h> |
d129bceb | 25 | |
d129bceb PO |
26 | #include "sdhci.h" |
27 | ||
28 | #define DRIVER_NAME "sdhci" | |
d129bceb | 29 | |
d129bceb | 30 | #define DBG(f, x...) \ |
c6563178 | 31 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
d129bceb | 32 | |
df673b22 | 33 | static unsigned int debug_quirks = 0; |
67435274 | 34 | |
dc93441b PO |
35 | /* |
36 | * Different quirks to handle when the hardware deviates from a strict | |
37 | * interpretation of the SDHCI specification. | |
38 | */ | |
39 | ||
40 | /* Controller doesn't honor resets unless we touch the clock register */ | |
645289dc | 41 | #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) |
dc93441b | 42 | /* Controller has bad caps bits, but really supports DMA */ |
98608076 | 43 | #define SDHCI_QUIRK_FORCE_DMA (1<<1) |
0b82684c | 44 | /* Controller doesn't like to be reset when there is no card inserted. */ |
8a4da143 | 45 | #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) |
dc93441b | 46 | /* Controller doesn't like clearing the power reg before a change */ |
9e9dc5f2 | 47 | #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) |
dc93441b | 48 | /* Controller has flaky internal state so reset it on each ios change */ |
b8352260 | 49 | #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) |
dc93441b | 50 | /* Controller has an unusable DMA engine */ |
7c168e3d | 51 | #define SDHCI_QUIRK_BROKEN_DMA (1<<5) |
c9fddbc4 PO |
52 | /* Controller can only DMA from 32-bit aligned addresses */ |
53 | #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<6) | |
54 | /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ | |
55 | #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<7) | |
84c46a53 PO |
56 | /* Controller needs to be reset after each request to stay stable */ |
57 | #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<8) | |
e08c1694 AS |
58 | /* Controller needs voltage and power writes to happen separately */ |
59 | #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<9) | |
603ded16 AS |
60 | /* Controller has an off-by-one issue with timeout value */ |
61 | #define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<10) | |
645289dc | 62 | |
d129bceb | 63 | static const struct pci_device_id pci_ids[] __devinitdata = { |
645289dc PO |
64 | { |
65 | .vendor = PCI_VENDOR_ID_RICOH, | |
66 | .device = PCI_DEVICE_ID_RICOH_R5C822, | |
67 | .subvendor = PCI_VENDOR_ID_IBM, | |
68 | .subdevice = PCI_ANY_ID, | |
98608076 PO |
69 | .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET | |
70 | SDHCI_QUIRK_FORCE_DMA, | |
71 | }, | |
72 | ||
73 | { | |
74 | .vendor = PCI_VENDOR_ID_RICOH, | |
75 | .device = PCI_DEVICE_ID_RICOH_R5C822, | |
0b82684c | 76 | .subvendor = PCI_VENDOR_ID_SAMSUNG, |
98608076 | 77 | .subdevice = PCI_ANY_ID, |
8a4da143 PO |
78 | .driver_data = SDHCI_QUIRK_FORCE_DMA | |
79 | SDHCI_QUIRK_NO_CARD_NO_RESET, | |
98608076 PO |
80 | }, |
81 | ||
0b82684c PO |
82 | { |
83 | .vendor = PCI_VENDOR_ID_RICOH, | |
84 | .device = PCI_DEVICE_ID_RICOH_R5C822, | |
85 | .subvendor = PCI_ANY_ID, | |
86 | .subdevice = PCI_ANY_ID, | |
87 | .driver_data = SDHCI_QUIRK_FORCE_DMA, | |
88 | }, | |
89 | ||
98608076 PO |
90 | { |
91 | .vendor = PCI_VENDOR_ID_TI, | |
92 | .device = PCI_DEVICE_ID_TI_XX21_XX11_SD, | |
93 | .subvendor = PCI_ANY_ID, | |
94 | .subdevice = PCI_ANY_ID, | |
95 | .driver_data = SDHCI_QUIRK_FORCE_DMA, | |
645289dc PO |
96 | }, |
97 | ||
9e9dc5f2 DS |
98 | { |
99 | .vendor = PCI_VENDOR_ID_ENE, | |
100 | .device = PCI_DEVICE_ID_ENE_CB712_SD, | |
101 | .subvendor = PCI_ANY_ID, | |
102 | .subdevice = PCI_ANY_ID, | |
7c168e3d FT |
103 | .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE | |
104 | SDHCI_QUIRK_BROKEN_DMA, | |
9e9dc5f2 DS |
105 | }, |
106 | ||
7de064eb MK |
107 | { |
108 | .vendor = PCI_VENDOR_ID_ENE, | |
109 | .device = PCI_DEVICE_ID_ENE_CB712_SD_2, | |
110 | .subvendor = PCI_ANY_ID, | |
111 | .subdevice = PCI_ANY_ID, | |
7c168e3d FT |
112 | .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE | |
113 | SDHCI_QUIRK_BROKEN_DMA, | |
7de064eb MK |
114 | }, |
115 | ||
b8352260 LD |
116 | { |
117 | .vendor = PCI_VENDOR_ID_ENE, | |
118 | .device = PCI_DEVICE_ID_ENE_CB714_SD, | |
119 | .subvendor = PCI_ANY_ID, | |
120 | .subdevice = PCI_ANY_ID, | |
121 | .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE | | |
bf5b1935 PO |
122 | SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | |
123 | SDHCI_QUIRK_BROKEN_DMA, | |
b8352260 LD |
124 | }, |
125 | ||
126 | { | |
127 | .vendor = PCI_VENDOR_ID_ENE, | |
128 | .device = PCI_DEVICE_ID_ENE_CB714_SD_2, | |
129 | .subvendor = PCI_ANY_ID, | |
130 | .subdevice = PCI_ANY_ID, | |
131 | .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE | | |
bf5b1935 PO |
132 | SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | |
133 | SDHCI_QUIRK_BROKEN_DMA, | |
b8352260 LD |
134 | }, |
135 | ||
e08c1694 AS |
136 | { |
137 | .vendor = PCI_VENDOR_ID_MARVELL, | |
138 | .device = PCI_DEVICE_ID_MARVELL_CAFE_SD, | |
139 | .subvendor = PCI_ANY_ID, | |
140 | .subdevice = PCI_ANY_ID, | |
603ded16 AS |
141 | .driver_data = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | |
142 | SDHCI_QUIRK_INCR_TIMEOUT_CONTROL, | |
e08c1694 AS |
143 | }, |
144 | ||
84c46a53 PO |
145 | { |
146 | .vendor = PCI_VENDOR_ID_JMICRON, | |
147 | .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, | |
148 | .subvendor = PCI_ANY_ID, | |
149 | .subdevice = PCI_ANY_ID, | |
150 | .driver_data = SDHCI_QUIRK_32BIT_DMA_ADDR | | |
151 | SDHCI_QUIRK_32BIT_DMA_SIZE | | |
152 | SDHCI_QUIRK_RESET_AFTER_REQUEST, | |
153 | }, | |
154 | ||
645289dc PO |
155 | { /* Generic SD host controller */ |
156 | PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) | |
157 | }, | |
158 | ||
d129bceb PO |
159 | { /* end: all zeroes */ }, |
160 | }; | |
161 | ||
162 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
163 | ||
164 | static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *); | |
165 | static void sdhci_finish_data(struct sdhci_host *); | |
166 | ||
167 | static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); | |
168 | static void sdhci_finish_command(struct sdhci_host *); | |
169 | ||
170 | static void sdhci_dumpregs(struct sdhci_host *host) | |
171 | { | |
172 | printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n"); | |
173 | ||
174 | printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", | |
175 | readl(host->ioaddr + SDHCI_DMA_ADDRESS), | |
176 | readw(host->ioaddr + SDHCI_HOST_VERSION)); | |
177 | printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", | |
178 | readw(host->ioaddr + SDHCI_BLOCK_SIZE), | |
179 | readw(host->ioaddr + SDHCI_BLOCK_COUNT)); | |
180 | printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", | |
181 | readl(host->ioaddr + SDHCI_ARGUMENT), | |
182 | readw(host->ioaddr + SDHCI_TRANSFER_MODE)); | |
183 | printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", | |
184 | readl(host->ioaddr + SDHCI_PRESENT_STATE), | |
185 | readb(host->ioaddr + SDHCI_HOST_CONTROL)); | |
186 | printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", | |
187 | readb(host->ioaddr + SDHCI_POWER_CONTROL), | |
188 | readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL)); | |
189 | printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", | |
2df3b71b | 190 | readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL), |
d129bceb PO |
191 | readw(host->ioaddr + SDHCI_CLOCK_CONTROL)); |
192 | printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", | |
193 | readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL), | |
194 | readl(host->ioaddr + SDHCI_INT_STATUS)); | |
195 | printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", | |
196 | readl(host->ioaddr + SDHCI_INT_ENABLE), | |
197 | readl(host->ioaddr + SDHCI_SIGNAL_ENABLE)); | |
198 | printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", | |
199 | readw(host->ioaddr + SDHCI_ACMD12_ERR), | |
200 | readw(host->ioaddr + SDHCI_SLOT_INT_STATUS)); | |
201 | printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n", | |
202 | readl(host->ioaddr + SDHCI_CAPABILITIES), | |
203 | readl(host->ioaddr + SDHCI_MAX_CURRENT)); | |
204 | ||
205 | printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n"); | |
206 | } | |
207 | ||
208 | /*****************************************************************************\ | |
209 | * * | |
210 | * Low level functions * | |
211 | * * | |
212 | \*****************************************************************************/ | |
213 | ||
214 | static void sdhci_reset(struct sdhci_host *host, u8 mask) | |
215 | { | |
e16514d8 PO |
216 | unsigned long timeout; |
217 | ||
8a4da143 PO |
218 | if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { |
219 | if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & | |
220 | SDHCI_CARD_PRESENT)) | |
221 | return; | |
222 | } | |
223 | ||
d129bceb PO |
224 | writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET); |
225 | ||
e16514d8 | 226 | if (mask & SDHCI_RESET_ALL) |
d129bceb PO |
227 | host->clock = 0; |
228 | ||
e16514d8 PO |
229 | /* Wait max 100 ms */ |
230 | timeout = 100; | |
231 | ||
232 | /* hw clears the bit when it's done */ | |
233 | while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) { | |
234 | if (timeout == 0) { | |
acf1da45 | 235 | printk(KERN_ERR "%s: Reset 0x%x never completed.\n", |
e16514d8 PO |
236 | mmc_hostname(host->mmc), (int)mask); |
237 | sdhci_dumpregs(host); | |
238 | return; | |
239 | } | |
240 | timeout--; | |
241 | mdelay(1); | |
d129bceb PO |
242 | } |
243 | } | |
244 | ||
245 | static void sdhci_init(struct sdhci_host *host) | |
246 | { | |
247 | u32 intmask; | |
248 | ||
249 | sdhci_reset(host, SDHCI_RESET_ALL); | |
250 | ||
3192a28f PO |
251 | intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | |
252 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | | |
253 | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | | |
254 | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | | |
a406f5a3 | 255 | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | |
3192a28f | 256 | SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE; |
d129bceb PO |
257 | |
258 | writel(intmask, host->ioaddr + SDHCI_INT_ENABLE); | |
259 | writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE); | |
d129bceb PO |
260 | } |
261 | ||
262 | static void sdhci_activate_led(struct sdhci_host *host) | |
263 | { | |
264 | u8 ctrl; | |
265 | ||
266 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); | |
267 | ctrl |= SDHCI_CTRL_LED; | |
268 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); | |
269 | } | |
270 | ||
271 | static void sdhci_deactivate_led(struct sdhci_host *host) | |
272 | { | |
273 | u8 ctrl; | |
274 | ||
275 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); | |
276 | ctrl &= ~SDHCI_CTRL_LED; | |
277 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); | |
278 | } | |
279 | ||
2f730fec PO |
280 | #ifdef CONFIG_LEDS_CLASS |
281 | static void sdhci_led_control(struct led_classdev *led, | |
282 | enum led_brightness brightness) | |
283 | { | |
284 | struct sdhci_host *host = container_of(led, struct sdhci_host, led); | |
285 | unsigned long flags; | |
286 | ||
287 | spin_lock_irqsave(&host->lock, flags); | |
288 | ||
289 | if (brightness == LED_OFF) | |
290 | sdhci_deactivate_led(host); | |
291 | else | |
292 | sdhci_activate_led(host); | |
293 | ||
294 | spin_unlock_irqrestore(&host->lock, flags); | |
295 | } | |
296 | #endif | |
297 | ||
d129bceb PO |
298 | /*****************************************************************************\ |
299 | * * | |
300 | * Core functions * | |
301 | * * | |
302 | \*****************************************************************************/ | |
303 | ||
2a22b14e | 304 | static inline char* sdhci_sg_to_buffer(struct sdhci_host* host) |
d129bceb | 305 | { |
45711f1a | 306 | return sg_virt(host->cur_sg); |
d129bceb PO |
307 | } |
308 | ||
309 | static inline int sdhci_next_sg(struct sdhci_host* host) | |
310 | { | |
311 | /* | |
312 | * Skip to next SG entry. | |
313 | */ | |
314 | host->cur_sg++; | |
315 | host->num_sg--; | |
316 | ||
317 | /* | |
318 | * Any entries left? | |
319 | */ | |
320 | if (host->num_sg > 0) { | |
321 | host->offset = 0; | |
322 | host->remain = host->cur_sg->length; | |
323 | } | |
324 | ||
325 | return host->num_sg; | |
326 | } | |
327 | ||
a406f5a3 | 328 | static void sdhci_read_block_pio(struct sdhci_host *host) |
d129bceb | 329 | { |
a406f5a3 PO |
330 | int blksize, chunk_remain; |
331 | u32 data; | |
d129bceb | 332 | char *buffer; |
a406f5a3 | 333 | int size; |
d129bceb | 334 | |
a406f5a3 | 335 | DBG("PIO reading\n"); |
d129bceb | 336 | |
a406f5a3 PO |
337 | blksize = host->data->blksz; |
338 | chunk_remain = 0; | |
339 | data = 0; | |
d129bceb | 340 | |
2a22b14e | 341 | buffer = sdhci_sg_to_buffer(host) + host->offset; |
d129bceb | 342 | |
a406f5a3 PO |
343 | while (blksize) { |
344 | if (chunk_remain == 0) { | |
345 | data = readl(host->ioaddr + SDHCI_BUFFER); | |
346 | chunk_remain = min(blksize, 4); | |
347 | } | |
d129bceb | 348 | |
14d836e7 | 349 | size = min(host->remain, chunk_remain); |
d129bceb | 350 | |
a406f5a3 PO |
351 | chunk_remain -= size; |
352 | blksize -= size; | |
353 | host->offset += size; | |
354 | host->remain -= size; | |
14d836e7 | 355 | |
a406f5a3 PO |
356 | while (size) { |
357 | *buffer = data & 0xFF; | |
358 | buffer++; | |
359 | data >>= 8; | |
360 | size--; | |
361 | } | |
d129bceb | 362 | |
a406f5a3 | 363 | if (host->remain == 0) { |
a406f5a3 PO |
364 | if (sdhci_next_sg(host) == 0) { |
365 | BUG_ON(blksize != 0); | |
366 | return; | |
367 | } | |
2a22b14e | 368 | buffer = sdhci_sg_to_buffer(host); |
d129bceb | 369 | } |
a406f5a3 | 370 | } |
a406f5a3 | 371 | } |
d129bceb | 372 | |
a406f5a3 PO |
373 | static void sdhci_write_block_pio(struct sdhci_host *host) |
374 | { | |
375 | int blksize, chunk_remain; | |
376 | u32 data; | |
377 | char *buffer; | |
378 | int bytes, size; | |
d129bceb | 379 | |
a406f5a3 PO |
380 | DBG("PIO writing\n"); |
381 | ||
382 | blksize = host->data->blksz; | |
383 | chunk_remain = 4; | |
384 | data = 0; | |
d129bceb | 385 | |
a406f5a3 | 386 | bytes = 0; |
2a22b14e | 387 | buffer = sdhci_sg_to_buffer(host) + host->offset; |
d129bceb | 388 | |
a406f5a3 | 389 | while (blksize) { |
14d836e7 | 390 | size = min(host->remain, chunk_remain); |
a406f5a3 PO |
391 | |
392 | chunk_remain -= size; | |
393 | blksize -= size; | |
d129bceb PO |
394 | host->offset += size; |
395 | host->remain -= size; | |
14d836e7 | 396 | |
a406f5a3 PO |
397 | while (size) { |
398 | data >>= 8; | |
399 | data |= (u32)*buffer << 24; | |
400 | buffer++; | |
401 | size--; | |
402 | } | |
403 | ||
404 | if (chunk_remain == 0) { | |
405 | writel(data, host->ioaddr + SDHCI_BUFFER); | |
406 | chunk_remain = min(blksize, 4); | |
407 | } | |
d129bceb PO |
408 | |
409 | if (host->remain == 0) { | |
d129bceb | 410 | if (sdhci_next_sg(host) == 0) { |
a406f5a3 | 411 | BUG_ON(blksize != 0); |
d129bceb PO |
412 | return; |
413 | } | |
2a22b14e | 414 | buffer = sdhci_sg_to_buffer(host); |
d129bceb PO |
415 | } |
416 | } | |
a406f5a3 PO |
417 | } |
418 | ||
419 | static void sdhci_transfer_pio(struct sdhci_host *host) | |
420 | { | |
421 | u32 mask; | |
422 | ||
423 | BUG_ON(!host->data); | |
424 | ||
14d836e7 | 425 | if (host->num_sg == 0) |
a406f5a3 PO |
426 | return; |
427 | ||
428 | if (host->data->flags & MMC_DATA_READ) | |
429 | mask = SDHCI_DATA_AVAILABLE; | |
430 | else | |
431 | mask = SDHCI_SPACE_AVAILABLE; | |
432 | ||
433 | while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) { | |
434 | if (host->data->flags & MMC_DATA_READ) | |
435 | sdhci_read_block_pio(host); | |
436 | else | |
437 | sdhci_write_block_pio(host); | |
d129bceb | 438 | |
14d836e7 | 439 | if (host->num_sg == 0) |
a406f5a3 | 440 | break; |
a406f5a3 | 441 | } |
d129bceb | 442 | |
a406f5a3 | 443 | DBG("PIO transfer complete.\n"); |
d129bceb PO |
444 | } |
445 | ||
446 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) | |
447 | { | |
1c8cde92 PO |
448 | u8 count; |
449 | unsigned target_timeout, current_timeout; | |
d129bceb PO |
450 | |
451 | WARN_ON(host->data); | |
452 | ||
c7fa9963 | 453 | if (data == NULL) |
d129bceb | 454 | return; |
d129bceb | 455 | |
bab76961 PO |
456 | /* Sanity checks */ |
457 | BUG_ON(data->blksz * data->blocks > 524288); | |
fe4a3c7a | 458 | BUG_ON(data->blksz > host->mmc->max_blk_size); |
1d676e02 | 459 | BUG_ON(data->blocks > 65535); |
d129bceb | 460 | |
e538fbe8 PO |
461 | host->data = data; |
462 | host->data_early = 0; | |
463 | ||
1c8cde92 PO |
464 | /* timeout in us */ |
465 | target_timeout = data->timeout_ns / 1000 + | |
466 | data->timeout_clks / host->clock; | |
d129bceb | 467 | |
1c8cde92 PO |
468 | /* |
469 | * Figure out needed cycles. | |
470 | * We do this in steps in order to fit inside a 32 bit int. | |
471 | * The first step is the minimum timeout, which will have a | |
472 | * minimum resolution of 6 bits: | |
473 | * (1) 2^13*1000 > 2^22, | |
474 | * (2) host->timeout_clk < 2^16 | |
475 | * => | |
476 | * (1) / (2) > 2^6 | |
477 | */ | |
478 | count = 0; | |
479 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; | |
480 | while (current_timeout < target_timeout) { | |
481 | count++; | |
482 | current_timeout <<= 1; | |
483 | if (count >= 0xF) | |
484 | break; | |
485 | } | |
486 | ||
603ded16 AS |
487 | /* |
488 | * Compensate for an off-by-one error in the CaFe hardware; otherwise, | |
489 | * a too-small count gives us interrupt timeouts. | |
490 | */ | |
491 | if ((host->chip->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) | |
492 | count++; | |
493 | ||
1c8cde92 PO |
494 | if (count >= 0xF) { |
495 | printk(KERN_WARNING "%s: Too large timeout requested!\n", | |
496 | mmc_hostname(host->mmc)); | |
497 | count = 0xE; | |
498 | } | |
499 | ||
500 | writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL); | |
d129bceb | 501 | |
c9fddbc4 PO |
502 | if (host->flags & SDHCI_USE_DMA) |
503 | host->flags |= SDHCI_REQ_USE_DMA; | |
504 | ||
505 | if (unlikely((host->flags & SDHCI_REQ_USE_DMA) && | |
506 | (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && | |
507 | ((data->blksz * data->blocks) & 0x3))) { | |
508 | DBG("Reverting to PIO because of transfer size (%d)\n", | |
509 | data->blksz * data->blocks); | |
510 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
511 | } | |
512 | ||
513 | /* | |
514 | * The assumption here being that alignment is the same after | |
515 | * translation to device address space. | |
516 | */ | |
517 | if (unlikely((host->flags & SDHCI_REQ_USE_DMA) && | |
518 | (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && | |
519 | (data->sg->offset & 0x3))) { | |
520 | DBG("Reverting to PIO because of bad alignment\n"); | |
521 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
522 | } | |
523 | ||
524 | if (host->flags & SDHCI_REQ_USE_DMA) { | |
d129bceb PO |
525 | int count; |
526 | ||
527 | count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len, | |
528 | (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE); | |
529 | BUG_ON(count != 1); | |
530 | ||
531 | writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS); | |
532 | } else { | |
d129bceb PO |
533 | host->cur_sg = data->sg; |
534 | host->num_sg = data->sg_len; | |
535 | ||
536 | host->offset = 0; | |
537 | host->remain = host->cur_sg->length; | |
538 | } | |
c7fa9963 | 539 | |
bab76961 PO |
540 | /* We do not handle DMA boundaries, so set it to max (512 KiB) */ |
541 | writew(SDHCI_MAKE_BLKSZ(7, data->blksz), | |
542 | host->ioaddr + SDHCI_BLOCK_SIZE); | |
c7fa9963 PO |
543 | writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT); |
544 | } | |
545 | ||
546 | static void sdhci_set_transfer_mode(struct sdhci_host *host, | |
547 | struct mmc_data *data) | |
548 | { | |
549 | u16 mode; | |
550 | ||
c7fa9963 PO |
551 | if (data == NULL) |
552 | return; | |
553 | ||
e538fbe8 PO |
554 | WARN_ON(!host->data); |
555 | ||
c7fa9963 PO |
556 | mode = SDHCI_TRNS_BLK_CNT_EN; |
557 | if (data->blocks > 1) | |
558 | mode |= SDHCI_TRNS_MULTI; | |
559 | if (data->flags & MMC_DATA_READ) | |
560 | mode |= SDHCI_TRNS_READ; | |
c9fddbc4 | 561 | if (host->flags & SDHCI_REQ_USE_DMA) |
c7fa9963 PO |
562 | mode |= SDHCI_TRNS_DMA; |
563 | ||
564 | writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE); | |
d129bceb PO |
565 | } |
566 | ||
567 | static void sdhci_finish_data(struct sdhci_host *host) | |
568 | { | |
569 | struct mmc_data *data; | |
d129bceb PO |
570 | u16 blocks; |
571 | ||
572 | BUG_ON(!host->data); | |
573 | ||
574 | data = host->data; | |
575 | host->data = NULL; | |
576 | ||
c9fddbc4 | 577 | if (host->flags & SDHCI_REQ_USE_DMA) { |
d129bceb PO |
578 | pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len, |
579 | (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE); | |
d129bceb PO |
580 | } |
581 | ||
582 | /* | |
583 | * Controller doesn't count down when in single block mode. | |
584 | */ | |
2b061973 | 585 | if (data->blocks == 1) |
17b0429d | 586 | blocks = (data->error == 0) ? 0 : 1; |
d129bceb PO |
587 | else |
588 | blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT); | |
a3fd4a1b | 589 | data->bytes_xfered = data->blksz * (data->blocks - blocks); |
d129bceb | 590 | |
17b0429d | 591 | if (!data->error && blocks) { |
d129bceb | 592 | printk(KERN_ERR "%s: Controller signalled completion even " |
acf1da45 PO |
593 | "though there were blocks left.\n", |
594 | mmc_hostname(host->mmc)); | |
17b0429d | 595 | data->error = -EIO; |
d129bceb PO |
596 | } |
597 | ||
d129bceb PO |
598 | if (data->stop) { |
599 | /* | |
600 | * The controller needs a reset of internal state machines | |
601 | * upon error conditions. | |
602 | */ | |
17b0429d | 603 | if (data->error) { |
d129bceb PO |
604 | sdhci_reset(host, SDHCI_RESET_CMD); |
605 | sdhci_reset(host, SDHCI_RESET_DATA); | |
606 | } | |
607 | ||
608 | sdhci_send_command(host, data->stop); | |
609 | } else | |
610 | tasklet_schedule(&host->finish_tasklet); | |
611 | } | |
612 | ||
613 | static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) | |
614 | { | |
615 | int flags; | |
fd2208d7 | 616 | u32 mask; |
7cb2c76f | 617 | unsigned long timeout; |
d129bceb PO |
618 | |
619 | WARN_ON(host->cmd); | |
620 | ||
d129bceb | 621 | /* Wait max 10 ms */ |
7cb2c76f | 622 | timeout = 10; |
fd2208d7 PO |
623 | |
624 | mask = SDHCI_CMD_INHIBIT; | |
625 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) | |
626 | mask |= SDHCI_DATA_INHIBIT; | |
627 | ||
628 | /* We shouldn't wait for data inihibit for stop commands, even | |
629 | though they might use busy signaling */ | |
630 | if (host->mrq->data && (cmd == host->mrq->data->stop)) | |
631 | mask &= ~SDHCI_DATA_INHIBIT; | |
632 | ||
633 | while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) { | |
7cb2c76f | 634 | if (timeout == 0) { |
d129bceb | 635 | printk(KERN_ERR "%s: Controller never released " |
acf1da45 | 636 | "inhibit bit(s).\n", mmc_hostname(host->mmc)); |
d129bceb | 637 | sdhci_dumpregs(host); |
17b0429d | 638 | cmd->error = -EIO; |
d129bceb PO |
639 | tasklet_schedule(&host->finish_tasklet); |
640 | return; | |
641 | } | |
7cb2c76f PO |
642 | timeout--; |
643 | mdelay(1); | |
644 | } | |
d129bceb PO |
645 | |
646 | mod_timer(&host->timer, jiffies + 10 * HZ); | |
647 | ||
648 | host->cmd = cmd; | |
649 | ||
650 | sdhci_prepare_data(host, cmd->data); | |
651 | ||
652 | writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT); | |
653 | ||
c7fa9963 PO |
654 | sdhci_set_transfer_mode(host, cmd->data); |
655 | ||
d129bceb | 656 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
acf1da45 | 657 | printk(KERN_ERR "%s: Unsupported response type!\n", |
d129bceb | 658 | mmc_hostname(host->mmc)); |
17b0429d | 659 | cmd->error = -EINVAL; |
d129bceb PO |
660 | tasklet_schedule(&host->finish_tasklet); |
661 | return; | |
662 | } | |
663 | ||
664 | if (!(cmd->flags & MMC_RSP_PRESENT)) | |
665 | flags = SDHCI_CMD_RESP_NONE; | |
666 | else if (cmd->flags & MMC_RSP_136) | |
667 | flags = SDHCI_CMD_RESP_LONG; | |
668 | else if (cmd->flags & MMC_RSP_BUSY) | |
669 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
670 | else | |
671 | flags = SDHCI_CMD_RESP_SHORT; | |
672 | ||
673 | if (cmd->flags & MMC_RSP_CRC) | |
674 | flags |= SDHCI_CMD_CRC; | |
675 | if (cmd->flags & MMC_RSP_OPCODE) | |
676 | flags |= SDHCI_CMD_INDEX; | |
677 | if (cmd->data) | |
678 | flags |= SDHCI_CMD_DATA; | |
679 | ||
fb61e289 | 680 | writew(SDHCI_MAKE_CMD(cmd->opcode, flags), |
d129bceb PO |
681 | host->ioaddr + SDHCI_COMMAND); |
682 | } | |
683 | ||
684 | static void sdhci_finish_command(struct sdhci_host *host) | |
685 | { | |
686 | int i; | |
687 | ||
688 | BUG_ON(host->cmd == NULL); | |
689 | ||
690 | if (host->cmd->flags & MMC_RSP_PRESENT) { | |
691 | if (host->cmd->flags & MMC_RSP_136) { | |
692 | /* CRC is stripped so we need to do some shifting. */ | |
693 | for (i = 0;i < 4;i++) { | |
694 | host->cmd->resp[i] = readl(host->ioaddr + | |
695 | SDHCI_RESPONSE + (3-i)*4) << 8; | |
696 | if (i != 3) | |
697 | host->cmd->resp[i] |= | |
698 | readb(host->ioaddr + | |
699 | SDHCI_RESPONSE + (3-i)*4-1); | |
700 | } | |
701 | } else { | |
702 | host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE); | |
703 | } | |
704 | } | |
705 | ||
17b0429d | 706 | host->cmd->error = 0; |
d129bceb | 707 | |
e538fbe8 PO |
708 | if (host->data && host->data_early) |
709 | sdhci_finish_data(host); | |
710 | ||
711 | if (!host->cmd->data) | |
d129bceb PO |
712 | tasklet_schedule(&host->finish_tasklet); |
713 | ||
714 | host->cmd = NULL; | |
715 | } | |
716 | ||
717 | static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) | |
718 | { | |
719 | int div; | |
720 | u16 clk; | |
7cb2c76f | 721 | unsigned long timeout; |
d129bceb PO |
722 | |
723 | if (clock == host->clock) | |
724 | return; | |
725 | ||
726 | writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
727 | ||
728 | if (clock == 0) | |
729 | goto out; | |
730 | ||
731 | for (div = 1;div < 256;div *= 2) { | |
732 | if ((host->max_clk / div) <= clock) | |
733 | break; | |
734 | } | |
735 | div >>= 1; | |
736 | ||
737 | clk = div << SDHCI_DIVIDER_SHIFT; | |
738 | clk |= SDHCI_CLOCK_INT_EN; | |
739 | writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
740 | ||
741 | /* Wait max 10 ms */ | |
7cb2c76f PO |
742 | timeout = 10; |
743 | while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL)) | |
744 | & SDHCI_CLOCK_INT_STABLE)) { | |
745 | if (timeout == 0) { | |
acf1da45 PO |
746 | printk(KERN_ERR "%s: Internal clock never " |
747 | "stabilised.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
748 | sdhci_dumpregs(host); |
749 | return; | |
750 | } | |
7cb2c76f PO |
751 | timeout--; |
752 | mdelay(1); | |
753 | } | |
d129bceb PO |
754 | |
755 | clk |= SDHCI_CLOCK_CARD_EN; | |
756 | writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
757 | ||
758 | out: | |
759 | host->clock = clock; | |
760 | } | |
761 | ||
146ad66e PO |
762 | static void sdhci_set_power(struct sdhci_host *host, unsigned short power) |
763 | { | |
764 | u8 pwr; | |
765 | ||
766 | if (host->power == power) | |
767 | return; | |
768 | ||
9e9dc5f2 DS |
769 | if (power == (unsigned short)-1) { |
770 | writeb(0, host->ioaddr + SDHCI_POWER_CONTROL); | |
146ad66e | 771 | goto out; |
9e9dc5f2 DS |
772 | } |
773 | ||
774 | /* | |
775 | * Spec says that we should clear the power reg before setting | |
776 | * a new value. Some controllers don't seem to like this though. | |
777 | */ | |
778 | if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) | |
779 | writeb(0, host->ioaddr + SDHCI_POWER_CONTROL); | |
146ad66e PO |
780 | |
781 | pwr = SDHCI_POWER_ON; | |
782 | ||
4be34c99 | 783 | switch (1 << power) { |
55556da0 | 784 | case MMC_VDD_165_195: |
146ad66e PO |
785 | pwr |= SDHCI_POWER_180; |
786 | break; | |
4be34c99 PL |
787 | case MMC_VDD_29_30: |
788 | case MMC_VDD_30_31: | |
146ad66e PO |
789 | pwr |= SDHCI_POWER_300; |
790 | break; | |
4be34c99 PL |
791 | case MMC_VDD_32_33: |
792 | case MMC_VDD_33_34: | |
146ad66e PO |
793 | pwr |= SDHCI_POWER_330; |
794 | break; | |
795 | default: | |
796 | BUG(); | |
797 | } | |
798 | ||
e08c1694 AS |
799 | /* |
800 | * At least the CaFe chip gets confused if we set the voltage | |
801 | * and set turn on power at the same time, so set the voltage first. | |
802 | */ | |
803 | if ((host->chip->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)) | |
804 | writeb(pwr & ~SDHCI_POWER_ON, | |
805 | host->ioaddr + SDHCI_POWER_CONTROL); | |
806 | ||
146ad66e PO |
807 | writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL); |
808 | ||
809 | out: | |
810 | host->power = power; | |
811 | } | |
812 | ||
d129bceb PO |
813 | /*****************************************************************************\ |
814 | * * | |
815 | * MMC callbacks * | |
816 | * * | |
817 | \*****************************************************************************/ | |
818 | ||
819 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
820 | { | |
821 | struct sdhci_host *host; | |
822 | unsigned long flags; | |
823 | ||
824 | host = mmc_priv(mmc); | |
825 | ||
826 | spin_lock_irqsave(&host->lock, flags); | |
827 | ||
828 | WARN_ON(host->mrq != NULL); | |
829 | ||
2f730fec | 830 | #ifndef CONFIG_LEDS_CLASS |
d129bceb | 831 | sdhci_activate_led(host); |
2f730fec | 832 | #endif |
d129bceb PO |
833 | |
834 | host->mrq = mrq; | |
835 | ||
836 | if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { | |
17b0429d | 837 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb PO |
838 | tasklet_schedule(&host->finish_tasklet); |
839 | } else | |
840 | sdhci_send_command(host, mrq->cmd); | |
841 | ||
5f25a66f | 842 | mmiowb(); |
d129bceb PO |
843 | spin_unlock_irqrestore(&host->lock, flags); |
844 | } | |
845 | ||
846 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
847 | { | |
848 | struct sdhci_host *host; | |
849 | unsigned long flags; | |
850 | u8 ctrl; | |
851 | ||
852 | host = mmc_priv(mmc); | |
853 | ||
854 | spin_lock_irqsave(&host->lock, flags); | |
855 | ||
d129bceb PO |
856 | /* |
857 | * Reset the chip on each power off. | |
858 | * Should clear out any weird states. | |
859 | */ | |
860 | if (ios->power_mode == MMC_POWER_OFF) { | |
861 | writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE); | |
d129bceb | 862 | sdhci_init(host); |
d129bceb PO |
863 | } |
864 | ||
865 | sdhci_set_clock(host, ios->clock); | |
866 | ||
867 | if (ios->power_mode == MMC_POWER_OFF) | |
146ad66e | 868 | sdhci_set_power(host, -1); |
d129bceb | 869 | else |
146ad66e | 870 | sdhci_set_power(host, ios->vdd); |
d129bceb PO |
871 | |
872 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); | |
cd9277c0 | 873 | |
d129bceb PO |
874 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
875 | ctrl |= SDHCI_CTRL_4BITBUS; | |
876 | else | |
877 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
cd9277c0 PO |
878 | |
879 | if (ios->timing == MMC_TIMING_SD_HS) | |
880 | ctrl |= SDHCI_CTRL_HISPD; | |
881 | else | |
882 | ctrl &= ~SDHCI_CTRL_HISPD; | |
883 | ||
d129bceb PO |
884 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); |
885 | ||
b8352260 LD |
886 | /* |
887 | * Some (ENE) controllers go apeshit on some ios operation, | |
888 | * signalling timeout and CRC errors even on CMD0. Resetting | |
889 | * it on each ios seems to solve the problem. | |
890 | */ | |
891 | if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) | |
892 | sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); | |
893 | ||
5f25a66f | 894 | mmiowb(); |
d129bceb PO |
895 | spin_unlock_irqrestore(&host->lock, flags); |
896 | } | |
897 | ||
898 | static int sdhci_get_ro(struct mmc_host *mmc) | |
899 | { | |
900 | struct sdhci_host *host; | |
901 | unsigned long flags; | |
902 | int present; | |
903 | ||
904 | host = mmc_priv(mmc); | |
905 | ||
906 | spin_lock_irqsave(&host->lock, flags); | |
907 | ||
908 | present = readl(host->ioaddr + SDHCI_PRESENT_STATE); | |
909 | ||
910 | spin_unlock_irqrestore(&host->lock, flags); | |
911 | ||
912 | return !(present & SDHCI_WRITE_PROTECT); | |
913 | } | |
914 | ||
f75979b7 PO |
915 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
916 | { | |
917 | struct sdhci_host *host; | |
918 | unsigned long flags; | |
919 | u32 ier; | |
920 | ||
921 | host = mmc_priv(mmc); | |
922 | ||
923 | spin_lock_irqsave(&host->lock, flags); | |
924 | ||
925 | ier = readl(host->ioaddr + SDHCI_INT_ENABLE); | |
926 | ||
927 | ier &= ~SDHCI_INT_CARD_INT; | |
928 | if (enable) | |
929 | ier |= SDHCI_INT_CARD_INT; | |
930 | ||
931 | writel(ier, host->ioaddr + SDHCI_INT_ENABLE); | |
932 | writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE); | |
933 | ||
934 | mmiowb(); | |
935 | ||
936 | spin_unlock_irqrestore(&host->lock, flags); | |
937 | } | |
938 | ||
ab7aefd0 | 939 | static const struct mmc_host_ops sdhci_ops = { |
d129bceb PO |
940 | .request = sdhci_request, |
941 | .set_ios = sdhci_set_ios, | |
942 | .get_ro = sdhci_get_ro, | |
f75979b7 | 943 | .enable_sdio_irq = sdhci_enable_sdio_irq, |
d129bceb PO |
944 | }; |
945 | ||
946 | /*****************************************************************************\ | |
947 | * * | |
948 | * Tasklets * | |
949 | * * | |
950 | \*****************************************************************************/ | |
951 | ||
952 | static void sdhci_tasklet_card(unsigned long param) | |
953 | { | |
954 | struct sdhci_host *host; | |
955 | unsigned long flags; | |
956 | ||
957 | host = (struct sdhci_host*)param; | |
958 | ||
959 | spin_lock_irqsave(&host->lock, flags); | |
960 | ||
961 | if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { | |
962 | if (host->mrq) { | |
963 | printk(KERN_ERR "%s: Card removed during transfer!\n", | |
964 | mmc_hostname(host->mmc)); | |
965 | printk(KERN_ERR "%s: Resetting controller.\n", | |
966 | mmc_hostname(host->mmc)); | |
967 | ||
968 | sdhci_reset(host, SDHCI_RESET_CMD); | |
969 | sdhci_reset(host, SDHCI_RESET_DATA); | |
970 | ||
17b0429d | 971 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb PO |
972 | tasklet_schedule(&host->finish_tasklet); |
973 | } | |
974 | } | |
975 | ||
976 | spin_unlock_irqrestore(&host->lock, flags); | |
977 | ||
978 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); | |
979 | } | |
980 | ||
981 | static void sdhci_tasklet_finish(unsigned long param) | |
982 | { | |
983 | struct sdhci_host *host; | |
984 | unsigned long flags; | |
985 | struct mmc_request *mrq; | |
986 | ||
987 | host = (struct sdhci_host*)param; | |
988 | ||
989 | spin_lock_irqsave(&host->lock, flags); | |
990 | ||
991 | del_timer(&host->timer); | |
992 | ||
993 | mrq = host->mrq; | |
994 | ||
d129bceb PO |
995 | /* |
996 | * The controller needs a reset of internal state machines | |
997 | * upon error conditions. | |
998 | */ | |
17b0429d PO |
999 | if (mrq->cmd->error || |
1000 | (mrq->data && (mrq->data->error || | |
84c46a53 PO |
1001 | (mrq->data->stop && mrq->data->stop->error))) || |
1002 | (host->chip->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { | |
645289dc PO |
1003 | |
1004 | /* Some controllers need this kick or reset won't work here */ | |
1005 | if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) { | |
1006 | unsigned int clock; | |
1007 | ||
1008 | /* This is to force an update */ | |
1009 | clock = host->clock; | |
1010 | host->clock = 0; | |
1011 | sdhci_set_clock(host, clock); | |
1012 | } | |
1013 | ||
1014 | /* Spec says we should do both at the same time, but Ricoh | |
1015 | controllers do not like that. */ | |
d129bceb PO |
1016 | sdhci_reset(host, SDHCI_RESET_CMD); |
1017 | sdhci_reset(host, SDHCI_RESET_DATA); | |
1018 | } | |
1019 | ||
1020 | host->mrq = NULL; | |
1021 | host->cmd = NULL; | |
1022 | host->data = NULL; | |
1023 | ||
2f730fec | 1024 | #ifndef CONFIG_LEDS_CLASS |
d129bceb | 1025 | sdhci_deactivate_led(host); |
2f730fec | 1026 | #endif |
d129bceb | 1027 | |
5f25a66f | 1028 | mmiowb(); |
d129bceb PO |
1029 | spin_unlock_irqrestore(&host->lock, flags); |
1030 | ||
1031 | mmc_request_done(host->mmc, mrq); | |
1032 | } | |
1033 | ||
1034 | static void sdhci_timeout_timer(unsigned long data) | |
1035 | { | |
1036 | struct sdhci_host *host; | |
1037 | unsigned long flags; | |
1038 | ||
1039 | host = (struct sdhci_host*)data; | |
1040 | ||
1041 | spin_lock_irqsave(&host->lock, flags); | |
1042 | ||
1043 | if (host->mrq) { | |
acf1da45 PO |
1044 | printk(KERN_ERR "%s: Timeout waiting for hardware " |
1045 | "interrupt.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
1046 | sdhci_dumpregs(host); |
1047 | ||
1048 | if (host->data) { | |
17b0429d | 1049 | host->data->error = -ETIMEDOUT; |
d129bceb PO |
1050 | sdhci_finish_data(host); |
1051 | } else { | |
1052 | if (host->cmd) | |
17b0429d | 1053 | host->cmd->error = -ETIMEDOUT; |
d129bceb | 1054 | else |
17b0429d | 1055 | host->mrq->cmd->error = -ETIMEDOUT; |
d129bceb PO |
1056 | |
1057 | tasklet_schedule(&host->finish_tasklet); | |
1058 | } | |
1059 | } | |
1060 | ||
5f25a66f | 1061 | mmiowb(); |
d129bceb PO |
1062 | spin_unlock_irqrestore(&host->lock, flags); |
1063 | } | |
1064 | ||
1065 | /*****************************************************************************\ | |
1066 | * * | |
1067 | * Interrupt handling * | |
1068 | * * | |
1069 | \*****************************************************************************/ | |
1070 | ||
1071 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) | |
1072 | { | |
1073 | BUG_ON(intmask == 0); | |
1074 | ||
1075 | if (!host->cmd) { | |
b67ac3f3 PO |
1076 | printk(KERN_ERR "%s: Got command interrupt 0x%08x even " |
1077 | "though no command operation was in progress.\n", | |
1078 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
1079 | sdhci_dumpregs(host); |
1080 | return; | |
1081 | } | |
1082 | ||
43b58b36 | 1083 | if (intmask & SDHCI_INT_TIMEOUT) |
17b0429d PO |
1084 | host->cmd->error = -ETIMEDOUT; |
1085 | else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | | |
1086 | SDHCI_INT_INDEX)) | |
1087 | host->cmd->error = -EILSEQ; | |
43b58b36 | 1088 | |
17b0429d | 1089 | if (host->cmd->error) |
d129bceb | 1090 | tasklet_schedule(&host->finish_tasklet); |
43b58b36 PO |
1091 | else if (intmask & SDHCI_INT_RESPONSE) |
1092 | sdhci_finish_command(host); | |
d129bceb PO |
1093 | } |
1094 | ||
1095 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) | |
1096 | { | |
1097 | BUG_ON(intmask == 0); | |
1098 | ||
1099 | if (!host->data) { | |
1100 | /* | |
1101 | * A data end interrupt is sent together with the response | |
1102 | * for the stop command. | |
1103 | */ | |
1104 | if (intmask & SDHCI_INT_DATA_END) | |
1105 | return; | |
1106 | ||
b67ac3f3 PO |
1107 | printk(KERN_ERR "%s: Got data interrupt 0x%08x even " |
1108 | "though no data operation was in progress.\n", | |
1109 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
1110 | sdhci_dumpregs(host); |
1111 | ||
1112 | return; | |
1113 | } | |
1114 | ||
1115 | if (intmask & SDHCI_INT_DATA_TIMEOUT) | |
17b0429d PO |
1116 | host->data->error = -ETIMEDOUT; |
1117 | else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) | |
1118 | host->data->error = -EILSEQ; | |
d129bceb | 1119 | |
17b0429d | 1120 | if (host->data->error) |
d129bceb PO |
1121 | sdhci_finish_data(host); |
1122 | else { | |
a406f5a3 | 1123 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
d129bceb PO |
1124 | sdhci_transfer_pio(host); |
1125 | ||
6ba736a1 PO |
1126 | /* |
1127 | * We currently don't do anything fancy with DMA | |
1128 | * boundaries, but as we can't disable the feature | |
1129 | * we need to at least restart the transfer. | |
1130 | */ | |
1131 | if (intmask & SDHCI_INT_DMA_END) | |
1132 | writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS), | |
1133 | host->ioaddr + SDHCI_DMA_ADDRESS); | |
1134 | ||
e538fbe8 PO |
1135 | if (intmask & SDHCI_INT_DATA_END) { |
1136 | if (host->cmd) { | |
1137 | /* | |
1138 | * Data managed to finish before the | |
1139 | * command completed. Make sure we do | |
1140 | * things in the proper order. | |
1141 | */ | |
1142 | host->data_early = 1; | |
1143 | } else { | |
1144 | sdhci_finish_data(host); | |
1145 | } | |
1146 | } | |
d129bceb PO |
1147 | } |
1148 | } | |
1149 | ||
7d12e780 | 1150 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
d129bceb PO |
1151 | { |
1152 | irqreturn_t result; | |
1153 | struct sdhci_host* host = dev_id; | |
1154 | u32 intmask; | |
f75979b7 | 1155 | int cardint = 0; |
d129bceb PO |
1156 | |
1157 | spin_lock(&host->lock); | |
1158 | ||
1159 | intmask = readl(host->ioaddr + SDHCI_INT_STATUS); | |
1160 | ||
62df67a5 | 1161 | if (!intmask || intmask == 0xffffffff) { |
d129bceb PO |
1162 | result = IRQ_NONE; |
1163 | goto out; | |
1164 | } | |
1165 | ||
b69c9058 PO |
1166 | DBG("*** %s got interrupt: 0x%08x\n", |
1167 | mmc_hostname(host->mmc), intmask); | |
d129bceb | 1168 | |
3192a28f PO |
1169 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
1170 | writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE), | |
1171 | host->ioaddr + SDHCI_INT_STATUS); | |
d129bceb | 1172 | tasklet_schedule(&host->card_tasklet); |
3192a28f | 1173 | } |
d129bceb | 1174 | |
3192a28f | 1175 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); |
d129bceb | 1176 | |
3192a28f | 1177 | if (intmask & SDHCI_INT_CMD_MASK) { |
d129bceb PO |
1178 | writel(intmask & SDHCI_INT_CMD_MASK, |
1179 | host->ioaddr + SDHCI_INT_STATUS); | |
3192a28f | 1180 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); |
d129bceb PO |
1181 | } |
1182 | ||
1183 | if (intmask & SDHCI_INT_DATA_MASK) { | |
d129bceb PO |
1184 | writel(intmask & SDHCI_INT_DATA_MASK, |
1185 | host->ioaddr + SDHCI_INT_STATUS); | |
3192a28f | 1186 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); |
d129bceb PO |
1187 | } |
1188 | ||
1189 | intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); | |
1190 | ||
964f9ce2 PO |
1191 | intmask &= ~SDHCI_INT_ERROR; |
1192 | ||
d129bceb | 1193 | if (intmask & SDHCI_INT_BUS_POWER) { |
3192a28f | 1194 | printk(KERN_ERR "%s: Card is consuming too much power!\n", |
d129bceb | 1195 | mmc_hostname(host->mmc)); |
3192a28f | 1196 | writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS); |
d129bceb PO |
1197 | } |
1198 | ||
9d26a5d3 | 1199 | intmask &= ~SDHCI_INT_BUS_POWER; |
3192a28f | 1200 | |
f75979b7 PO |
1201 | if (intmask & SDHCI_INT_CARD_INT) |
1202 | cardint = 1; | |
1203 | ||
1204 | intmask &= ~SDHCI_INT_CARD_INT; | |
1205 | ||
3192a28f | 1206 | if (intmask) { |
acf1da45 | 1207 | printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n", |
3192a28f | 1208 | mmc_hostname(host->mmc), intmask); |
d129bceb PO |
1209 | sdhci_dumpregs(host); |
1210 | ||
d129bceb | 1211 | writel(intmask, host->ioaddr + SDHCI_INT_STATUS); |
3192a28f | 1212 | } |
d129bceb PO |
1213 | |
1214 | result = IRQ_HANDLED; | |
1215 | ||
5f25a66f | 1216 | mmiowb(); |
d129bceb PO |
1217 | out: |
1218 | spin_unlock(&host->lock); | |
1219 | ||
f75979b7 PO |
1220 | /* |
1221 | * We have to delay this as it calls back into the driver. | |
1222 | */ | |
1223 | if (cardint) | |
1224 | mmc_signal_sdio_irq(host->mmc); | |
1225 | ||
d129bceb PO |
1226 | return result; |
1227 | } | |
1228 | ||
1229 | /*****************************************************************************\ | |
1230 | * * | |
1231 | * Suspend/resume * | |
1232 | * * | |
1233 | \*****************************************************************************/ | |
1234 | ||
1235 | #ifdef CONFIG_PM | |
1236 | ||
1237 | static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state) | |
1238 | { | |
1239 | struct sdhci_chip *chip; | |
1240 | int i, ret; | |
1241 | ||
1242 | chip = pci_get_drvdata(pdev); | |
1243 | if (!chip) | |
1244 | return 0; | |
1245 | ||
1246 | DBG("Suspending...\n"); | |
1247 | ||
1248 | for (i = 0;i < chip->num_slots;i++) { | |
1249 | if (!chip->hosts[i]) | |
1250 | continue; | |
1251 | ret = mmc_suspend_host(chip->hosts[i]->mmc, state); | |
1252 | if (ret) { | |
1253 | for (i--;i >= 0;i--) | |
1254 | mmc_resume_host(chip->hosts[i]->mmc); | |
1255 | return ret; | |
1256 | } | |
1257 | } | |
1258 | ||
1259 | pci_save_state(pdev); | |
1260 | pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); | |
a715dfc7 PO |
1261 | |
1262 | for (i = 0;i < chip->num_slots;i++) { | |
1263 | if (!chip->hosts[i]) | |
1264 | continue; | |
1265 | free_irq(chip->hosts[i]->irq, chip->hosts[i]); | |
1266 | } | |
1267 | ||
d129bceb PO |
1268 | pci_disable_device(pdev); |
1269 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1270 | ||
1271 | return 0; | |
1272 | } | |
1273 | ||
1274 | static int sdhci_resume (struct pci_dev *pdev) | |
1275 | { | |
1276 | struct sdhci_chip *chip; | |
1277 | int i, ret; | |
1278 | ||
1279 | chip = pci_get_drvdata(pdev); | |
1280 | if (!chip) | |
1281 | return 0; | |
1282 | ||
1283 | DBG("Resuming...\n"); | |
1284 | ||
1285 | pci_set_power_state(pdev, PCI_D0); | |
1286 | pci_restore_state(pdev); | |
df1c4b7b PO |
1287 | ret = pci_enable_device(pdev); |
1288 | if (ret) | |
1289 | return ret; | |
d129bceb PO |
1290 | |
1291 | for (i = 0;i < chip->num_slots;i++) { | |
1292 | if (!chip->hosts[i]) | |
1293 | continue; | |
1294 | if (chip->hosts[i]->flags & SDHCI_USE_DMA) | |
1295 | pci_set_master(pdev); | |
a715dfc7 | 1296 | ret = request_irq(chip->hosts[i]->irq, sdhci_irq, |
b69c9058 | 1297 | IRQF_SHARED, mmc_hostname(chip->hosts[i]->mmc), |
a715dfc7 PO |
1298 | chip->hosts[i]); |
1299 | if (ret) | |
1300 | return ret; | |
d129bceb | 1301 | sdhci_init(chip->hosts[i]); |
5f25a66f | 1302 | mmiowb(); |
d129bceb PO |
1303 | ret = mmc_resume_host(chip->hosts[i]->mmc); |
1304 | if (ret) | |
1305 | return ret; | |
1306 | } | |
1307 | ||
1308 | return 0; | |
1309 | } | |
1310 | ||
1311 | #else /* CONFIG_PM */ | |
1312 | ||
1313 | #define sdhci_suspend NULL | |
1314 | #define sdhci_resume NULL | |
1315 | ||
1316 | #endif /* CONFIG_PM */ | |
1317 | ||
1318 | /*****************************************************************************\ | |
1319 | * * | |
1320 | * Device probing/removal * | |
1321 | * * | |
1322 | \*****************************************************************************/ | |
1323 | ||
1324 | static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot) | |
1325 | { | |
1326 | int ret; | |
4a965505 | 1327 | unsigned int version; |
d129bceb PO |
1328 | struct sdhci_chip *chip; |
1329 | struct mmc_host *mmc; | |
1330 | struct sdhci_host *host; | |
1331 | ||
1332 | u8 first_bar; | |
1333 | unsigned int caps; | |
1334 | ||
1335 | chip = pci_get_drvdata(pdev); | |
1336 | BUG_ON(!chip); | |
1337 | ||
1338 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); | |
1339 | if (ret) | |
1340 | return ret; | |
1341 | ||
1342 | first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; | |
1343 | ||
1344 | if (first_bar > 5) { | |
1345 | printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n"); | |
1346 | return -ENODEV; | |
1347 | } | |
1348 | ||
1349 | if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) { | |
1350 | printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n"); | |
1351 | return -ENODEV; | |
1352 | } | |
1353 | ||
1354 | if (pci_resource_len(pdev, first_bar + slot) != 0x100) { | |
a98087cf PO |
1355 | printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. " |
1356 | "You may experience problems.\n"); | |
d129bceb PO |
1357 | } |
1358 | ||
67435274 PO |
1359 | if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { |
1360 | printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n"); | |
1361 | return -ENODEV; | |
1362 | } | |
1363 | ||
1364 | if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { | |
1365 | printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n"); | |
1366 | return -ENODEV; | |
1367 | } | |
1368 | ||
d129bceb PO |
1369 | mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev); |
1370 | if (!mmc) | |
1371 | return -ENOMEM; | |
1372 | ||
1373 | host = mmc_priv(mmc); | |
1374 | host->mmc = mmc; | |
1375 | ||
8a4da143 PO |
1376 | host->chip = chip; |
1377 | chip->hosts[slot] = host; | |
1378 | ||
d129bceb PO |
1379 | host->bar = first_bar + slot; |
1380 | ||
1381 | host->addr = pci_resource_start(pdev, host->bar); | |
1382 | host->irq = pdev->irq; | |
1383 | ||
1384 | DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq); | |
1385 | ||
b69c9058 | 1386 | ret = pci_request_region(pdev, host->bar, mmc_hostname(mmc)); |
d129bceb PO |
1387 | if (ret) |
1388 | goto free; | |
1389 | ||
1390 | host->ioaddr = ioremap_nocache(host->addr, | |
1391 | pci_resource_len(pdev, host->bar)); | |
1392 | if (!host->ioaddr) { | |
1393 | ret = -ENOMEM; | |
1394 | goto release; | |
1395 | } | |
1396 | ||
d96649ed PO |
1397 | sdhci_reset(host, SDHCI_RESET_ALL); |
1398 | ||
4a965505 PO |
1399 | version = readw(host->ioaddr + SDHCI_HOST_VERSION); |
1400 | version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; | |
c6573c94 | 1401 | if (version > 1) { |
4a965505 | 1402 | printk(KERN_ERR "%s: Unknown controller version (%d). " |
b69c9058 | 1403 | "You may experience problems.\n", mmc_hostname(mmc), |
4a965505 | 1404 | version); |
4a965505 PO |
1405 | } |
1406 | ||
d129bceb PO |
1407 | caps = readl(host->ioaddr + SDHCI_CAPABILITIES); |
1408 | ||
d6f8deec | 1409 | if (chip->quirks & SDHCI_QUIRK_FORCE_DMA) |
98608076 | 1410 | host->flags |= SDHCI_USE_DMA; |
67435274 PO |
1411 | else if (!(caps & SDHCI_CAN_DO_DMA)) |
1412 | DBG("Controller doesn't have DMA capability\n"); | |
1413 | else | |
d129bceb PO |
1414 | host->flags |= SDHCI_USE_DMA; |
1415 | ||
7c168e3d FT |
1416 | if ((chip->quirks & SDHCI_QUIRK_BROKEN_DMA) && |
1417 | (host->flags & SDHCI_USE_DMA)) { | |
cee687ce | 1418 | DBG("Disabling DMA as it is marked broken\n"); |
7c168e3d FT |
1419 | host->flags &= ~SDHCI_USE_DMA; |
1420 | } | |
1421 | ||
56e71efe FT |
1422 | if (((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && |
1423 | (host->flags & SDHCI_USE_DMA)) { | |
1424 | printk(KERN_WARNING "%s: Will use DMA " | |
1425 | "mode even though HW doesn't fully " | |
b69c9058 | 1426 | "claim to support it.\n", mmc_hostname(mmc)); |
56e71efe FT |
1427 | } |
1428 | ||
d129bceb PO |
1429 | if (host->flags & SDHCI_USE_DMA) { |
1430 | if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { | |
1431 | printk(KERN_WARNING "%s: No suitable DMA available. " | |
b69c9058 | 1432 | "Falling back to PIO.\n", mmc_hostname(mmc)); |
d129bceb PO |
1433 | host->flags &= ~SDHCI_USE_DMA; |
1434 | } | |
1435 | } | |
1436 | ||
1437 | if (host->flags & SDHCI_USE_DMA) | |
1438 | pci_set_master(pdev); | |
1439 | else /* XXX: Hack to get MMC layer to avoid highmem */ | |
1440 | pdev->dma_mask = 0; | |
1441 | ||
8ef1a143 PO |
1442 | host->max_clk = |
1443 | (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; | |
1444 | if (host->max_clk == 0) { | |
1445 | printk(KERN_ERR "%s: Hardware doesn't specify base clock " | |
b69c9058 | 1446 | "frequency.\n", mmc_hostname(mmc)); |
8ef1a143 PO |
1447 | ret = -ENODEV; |
1448 | goto unmap; | |
1449 | } | |
d129bceb PO |
1450 | host->max_clk *= 1000000; |
1451 | ||
1c8cde92 PO |
1452 | host->timeout_clk = |
1453 | (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; | |
1454 | if (host->timeout_clk == 0) { | |
1455 | printk(KERN_ERR "%s: Hardware doesn't specify timeout clock " | |
b69c9058 | 1456 | "frequency.\n", mmc_hostname(mmc)); |
1c8cde92 PO |
1457 | ret = -ENODEV; |
1458 | goto unmap; | |
1459 | } | |
1460 | if (caps & SDHCI_TIMEOUT_CLK_UNIT) | |
1461 | host->timeout_clk *= 1000; | |
d129bceb PO |
1462 | |
1463 | /* | |
1464 | * Set host parameters. | |
1465 | */ | |
1466 | mmc->ops = &sdhci_ops; | |
1467 | mmc->f_min = host->max_clk / 256; | |
1468 | mmc->f_max = host->max_clk; | |
f75979b7 | 1469 | mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_SDIO_IRQ; |
d129bceb | 1470 | |
cd9277c0 PO |
1471 | if (caps & SDHCI_CAN_DO_HISPD) |
1472 | mmc->caps |= MMC_CAP_SD_HIGHSPEED; | |
1473 | ||
146ad66e PO |
1474 | mmc->ocr_avail = 0; |
1475 | if (caps & SDHCI_CAN_VDD_330) | |
1476 | mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34; | |
c70840e8 | 1477 | if (caps & SDHCI_CAN_VDD_300) |
146ad66e | 1478 | mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31; |
c70840e8 | 1479 | if (caps & SDHCI_CAN_VDD_180) |
55556da0 | 1480 | mmc->ocr_avail |= MMC_VDD_165_195; |
146ad66e PO |
1481 | |
1482 | if (mmc->ocr_avail == 0) { | |
1483 | printk(KERN_ERR "%s: Hardware doesn't report any " | |
b69c9058 | 1484 | "support voltages.\n", mmc_hostname(mmc)); |
146ad66e PO |
1485 | ret = -ENODEV; |
1486 | goto unmap; | |
1487 | } | |
1488 | ||
d129bceb PO |
1489 | spin_lock_init(&host->lock); |
1490 | ||
1491 | /* | |
1492 | * Maximum number of segments. Hardware cannot do scatter lists. | |
1493 | */ | |
1494 | if (host->flags & SDHCI_USE_DMA) | |
1495 | mmc->max_hw_segs = 1; | |
1496 | else | |
1497 | mmc->max_hw_segs = 16; | |
1498 | mmc->max_phys_segs = 16; | |
1499 | ||
1500 | /* | |
bab76961 | 1501 | * Maximum number of sectors in one transfer. Limited by DMA boundary |
55db890a | 1502 | * size (512KiB). |
d129bceb | 1503 | */ |
55db890a | 1504 | mmc->max_req_size = 524288; |
d129bceb PO |
1505 | |
1506 | /* | |
1507 | * Maximum segment size. Could be one segment with the maximum number | |
55db890a | 1508 | * of bytes. |
d129bceb | 1509 | */ |
55db890a | 1510 | mmc->max_seg_size = mmc->max_req_size; |
d129bceb | 1511 | |
fe4a3c7a PO |
1512 | /* |
1513 | * Maximum block size. This varies from controller to controller and | |
1514 | * is specified in the capabilities register. | |
1515 | */ | |
1516 | mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT; | |
1517 | if (mmc->max_blk_size >= 3) { | |
b69c9058 PO |
1518 | printk(KERN_WARNING "%s: Invalid maximum block size, " |
1519 | "assuming 512 bytes\n", mmc_hostname(mmc)); | |
03f8590d DV |
1520 | mmc->max_blk_size = 512; |
1521 | } else | |
1522 | mmc->max_blk_size = 512 << mmc->max_blk_size; | |
fe4a3c7a | 1523 | |
55db890a PO |
1524 | /* |
1525 | * Maximum block count. | |
1526 | */ | |
1527 | mmc->max_blk_count = 65535; | |
1528 | ||
d129bceb PO |
1529 | /* |
1530 | * Init tasklets. | |
1531 | */ | |
1532 | tasklet_init(&host->card_tasklet, | |
1533 | sdhci_tasklet_card, (unsigned long)host); | |
1534 | tasklet_init(&host->finish_tasklet, | |
1535 | sdhci_tasklet_finish, (unsigned long)host); | |
1536 | ||
e4cad1b5 | 1537 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
d129bceb | 1538 | |
dace1453 | 1539 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
b69c9058 | 1540 | mmc_hostname(mmc), host); |
d129bceb | 1541 | if (ret) |
8ef1a143 | 1542 | goto untasklet; |
d129bceb PO |
1543 | |
1544 | sdhci_init(host); | |
1545 | ||
1546 | #ifdef CONFIG_MMC_DEBUG | |
1547 | sdhci_dumpregs(host); | |
1548 | #endif | |
1549 | ||
2f730fec PO |
1550 | #ifdef CONFIG_LEDS_CLASS |
1551 | host->led.name = mmc_hostname(mmc); | |
1552 | host->led.brightness = LED_OFF; | |
1553 | host->led.default_trigger = mmc_hostname(mmc); | |
1554 | host->led.brightness_set = sdhci_led_control; | |
1555 | ||
1556 | ret = led_classdev_register(&pdev->dev, &host->led); | |
1557 | if (ret) | |
1558 | goto reset; | |
1559 | #endif | |
1560 | ||
5f25a66f PO |
1561 | mmiowb(); |
1562 | ||
d129bceb PO |
1563 | mmc_add_host(mmc); |
1564 | ||
b69c9058 PO |
1565 | printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", |
1566 | mmc_hostname(mmc), host->addr, host->irq, | |
d129bceb PO |
1567 | (host->flags & SDHCI_USE_DMA)?"DMA":"PIO"); |
1568 | ||
1569 | return 0; | |
1570 | ||
2f730fec PO |
1571 | #ifdef CONFIG_LEDS_CLASS |
1572 | reset: | |
1573 | sdhci_reset(host, SDHCI_RESET_ALL); | |
1574 | free_irq(host->irq, host); | |
1575 | #endif | |
8ef1a143 | 1576 | untasklet: |
d129bceb PO |
1577 | tasklet_kill(&host->card_tasklet); |
1578 | tasklet_kill(&host->finish_tasklet); | |
8ef1a143 | 1579 | unmap: |
d129bceb PO |
1580 | iounmap(host->ioaddr); |
1581 | release: | |
1582 | pci_release_region(pdev, host->bar); | |
1583 | free: | |
1584 | mmc_free_host(mmc); | |
1585 | ||
1586 | return ret; | |
1587 | } | |
1588 | ||
1589 | static void sdhci_remove_slot(struct pci_dev *pdev, int slot) | |
1590 | { | |
1591 | struct sdhci_chip *chip; | |
1592 | struct mmc_host *mmc; | |
1593 | struct sdhci_host *host; | |
1594 | ||
1595 | chip = pci_get_drvdata(pdev); | |
1596 | host = chip->hosts[slot]; | |
1597 | mmc = host->mmc; | |
1598 | ||
1599 | chip->hosts[slot] = NULL; | |
1600 | ||
1601 | mmc_remove_host(mmc); | |
1602 | ||
2f730fec PO |
1603 | #ifdef CONFIG_LEDS_CLASS |
1604 | led_classdev_unregister(&host->led); | |
1605 | #endif | |
1606 | ||
d129bceb PO |
1607 | sdhci_reset(host, SDHCI_RESET_ALL); |
1608 | ||
1609 | free_irq(host->irq, host); | |
1610 | ||
1611 | del_timer_sync(&host->timer); | |
1612 | ||
1613 | tasklet_kill(&host->card_tasklet); | |
1614 | tasklet_kill(&host->finish_tasklet); | |
1615 | ||
1616 | iounmap(host->ioaddr); | |
1617 | ||
1618 | pci_release_region(pdev, host->bar); | |
1619 | ||
1620 | mmc_free_host(mmc); | |
1621 | } | |
1622 | ||
1623 | static int __devinit sdhci_probe(struct pci_dev *pdev, | |
1624 | const struct pci_device_id *ent) | |
1625 | { | |
1626 | int ret, i; | |
51f82bc0 | 1627 | u8 slots, rev; |
d129bceb PO |
1628 | struct sdhci_chip *chip; |
1629 | ||
1630 | BUG_ON(pdev == NULL); | |
1631 | BUG_ON(ent == NULL); | |
1632 | ||
51f82bc0 PO |
1633 | pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev); |
1634 | ||
1635 | printk(KERN_INFO DRIVER_NAME | |
1636 | ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n", | |
1637 | pci_name(pdev), (int)pdev->vendor, (int)pdev->device, | |
1638 | (int)rev); | |
d129bceb PO |
1639 | |
1640 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); | |
1641 | if (ret) | |
1642 | return ret; | |
1643 | ||
1644 | slots = PCI_SLOT_INFO_SLOTS(slots) + 1; | |
1645 | DBG("found %d slot(s)\n", slots); | |
1646 | if (slots == 0) | |
1647 | return -ENODEV; | |
1648 | ||
1649 | ret = pci_enable_device(pdev); | |
1650 | if (ret) | |
1651 | return ret; | |
1652 | ||
1653 | chip = kzalloc(sizeof(struct sdhci_chip) + | |
1654 | sizeof(struct sdhci_host*) * slots, GFP_KERNEL); | |
1655 | if (!chip) { | |
1656 | ret = -ENOMEM; | |
1657 | goto err; | |
1658 | } | |
1659 | ||
1660 | chip->pdev = pdev; | |
df673b22 PO |
1661 | chip->quirks = ent->driver_data; |
1662 | ||
1663 | if (debug_quirks) | |
1664 | chip->quirks = debug_quirks; | |
d129bceb PO |
1665 | |
1666 | chip->num_slots = slots; | |
1667 | pci_set_drvdata(pdev, chip); | |
1668 | ||
1669 | for (i = 0;i < slots;i++) { | |
1670 | ret = sdhci_probe_slot(pdev, i); | |
1671 | if (ret) { | |
1672 | for (i--;i >= 0;i--) | |
1673 | sdhci_remove_slot(pdev, i); | |
1674 | goto free; | |
1675 | } | |
1676 | } | |
1677 | ||
1678 | return 0; | |
1679 | ||
1680 | free: | |
1681 | pci_set_drvdata(pdev, NULL); | |
1682 | kfree(chip); | |
1683 | ||
1684 | err: | |
1685 | pci_disable_device(pdev); | |
1686 | return ret; | |
1687 | } | |
1688 | ||
1689 | static void __devexit sdhci_remove(struct pci_dev *pdev) | |
1690 | { | |
1691 | int i; | |
1692 | struct sdhci_chip *chip; | |
1693 | ||
1694 | chip = pci_get_drvdata(pdev); | |
1695 | ||
1696 | if (chip) { | |
1697 | for (i = 0;i < chip->num_slots;i++) | |
1698 | sdhci_remove_slot(pdev, i); | |
1699 | ||
1700 | pci_set_drvdata(pdev, NULL); | |
1701 | ||
1702 | kfree(chip); | |
1703 | } | |
1704 | ||
1705 | pci_disable_device(pdev); | |
1706 | } | |
1707 | ||
1708 | static struct pci_driver sdhci_driver = { | |
1709 | .name = DRIVER_NAME, | |
1710 | .id_table = pci_ids, | |
1711 | .probe = sdhci_probe, | |
1712 | .remove = __devexit_p(sdhci_remove), | |
1713 | .suspend = sdhci_suspend, | |
1714 | .resume = sdhci_resume, | |
1715 | }; | |
1716 | ||
1717 | /*****************************************************************************\ | |
1718 | * * | |
1719 | * Driver init/exit * | |
1720 | * * | |
1721 | \*****************************************************************************/ | |
1722 | ||
1723 | static int __init sdhci_drv_init(void) | |
1724 | { | |
1725 | printk(KERN_INFO DRIVER_NAME | |
52fbf9c9 | 1726 | ": Secure Digital Host Controller Interface driver\n"); |
d129bceb PO |
1727 | printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
1728 | ||
1729 | return pci_register_driver(&sdhci_driver); | |
1730 | } | |
1731 | ||
1732 | static void __exit sdhci_drv_exit(void) | |
1733 | { | |
1734 | DBG("Exiting\n"); | |
1735 | ||
1736 | pci_unregister_driver(&sdhci_driver); | |
1737 | } | |
1738 | ||
1739 | module_init(sdhci_drv_init); | |
1740 | module_exit(sdhci_drv_exit); | |
1741 | ||
df673b22 | 1742 | module_param(debug_quirks, uint, 0444); |
67435274 | 1743 | |
d129bceb PO |
1744 | MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>"); |
1745 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver"); | |
d129bceb | 1746 | MODULE_LICENSE("GPL"); |
67435274 | 1747 | |
df673b22 | 1748 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |