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d129bceb PO |
1 | /* |
2 | * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver | |
3 | * | |
14d836e7 | 4 | * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved. |
d129bceb PO |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or (at | |
9 | * your option) any later version. | |
d129bceb PO |
10 | */ |
11 | ||
d129bceb PO |
12 | #include <linux/delay.h> |
13 | #include <linux/highmem.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | ||
17 | #include <linux/mmc/host.h> | |
d129bceb PO |
18 | |
19 | #include <asm/scatterlist.h> | |
20 | ||
21 | #include "sdhci.h" | |
22 | ||
23 | #define DRIVER_NAME "sdhci" | |
d129bceb | 24 | |
d129bceb | 25 | #define DBG(f, x...) \ |
c6563178 | 26 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
d129bceb | 27 | |
67435274 PO |
28 | static unsigned int debug_nodma = 0; |
29 | static unsigned int debug_forcedma = 0; | |
df673b22 | 30 | static unsigned int debug_quirks = 0; |
67435274 | 31 | |
645289dc | 32 | #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) |
98608076 | 33 | #define SDHCI_QUIRK_FORCE_DMA (1<<1) |
8a4da143 PO |
34 | /* Controller doesn't like some resets when there is no card inserted. */ |
35 | #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) | |
9e9dc5f2 | 36 | #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) |
645289dc | 37 | |
d129bceb | 38 | static const struct pci_device_id pci_ids[] __devinitdata = { |
645289dc PO |
39 | { |
40 | .vendor = PCI_VENDOR_ID_RICOH, | |
41 | .device = PCI_DEVICE_ID_RICOH_R5C822, | |
42 | .subvendor = PCI_VENDOR_ID_IBM, | |
43 | .subdevice = PCI_ANY_ID, | |
98608076 PO |
44 | .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET | |
45 | SDHCI_QUIRK_FORCE_DMA, | |
46 | }, | |
47 | ||
48 | { | |
49 | .vendor = PCI_VENDOR_ID_RICOH, | |
50 | .device = PCI_DEVICE_ID_RICOH_R5C822, | |
51 | .subvendor = PCI_ANY_ID, | |
52 | .subdevice = PCI_ANY_ID, | |
8a4da143 PO |
53 | .driver_data = SDHCI_QUIRK_FORCE_DMA | |
54 | SDHCI_QUIRK_NO_CARD_NO_RESET, | |
98608076 PO |
55 | }, |
56 | ||
57 | { | |
58 | .vendor = PCI_VENDOR_ID_TI, | |
59 | .device = PCI_DEVICE_ID_TI_XX21_XX11_SD, | |
60 | .subvendor = PCI_ANY_ID, | |
61 | .subdevice = PCI_ANY_ID, | |
62 | .driver_data = SDHCI_QUIRK_FORCE_DMA, | |
645289dc PO |
63 | }, |
64 | ||
9e9dc5f2 DS |
65 | { |
66 | .vendor = PCI_VENDOR_ID_ENE, | |
67 | .device = PCI_DEVICE_ID_ENE_CB712_SD, | |
68 | .subvendor = PCI_ANY_ID, | |
69 | .subdevice = PCI_ANY_ID, | |
70 | .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE, | |
71 | }, | |
72 | ||
645289dc PO |
73 | { /* Generic SD host controller */ |
74 | PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) | |
75 | }, | |
76 | ||
d129bceb PO |
77 | { /* end: all zeroes */ }, |
78 | }; | |
79 | ||
80 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
81 | ||
82 | static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *); | |
83 | static void sdhci_finish_data(struct sdhci_host *); | |
84 | ||
85 | static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); | |
86 | static void sdhci_finish_command(struct sdhci_host *); | |
87 | ||
88 | static void sdhci_dumpregs(struct sdhci_host *host) | |
89 | { | |
90 | printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n"); | |
91 | ||
92 | printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", | |
93 | readl(host->ioaddr + SDHCI_DMA_ADDRESS), | |
94 | readw(host->ioaddr + SDHCI_HOST_VERSION)); | |
95 | printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", | |
96 | readw(host->ioaddr + SDHCI_BLOCK_SIZE), | |
97 | readw(host->ioaddr + SDHCI_BLOCK_COUNT)); | |
98 | printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", | |
99 | readl(host->ioaddr + SDHCI_ARGUMENT), | |
100 | readw(host->ioaddr + SDHCI_TRANSFER_MODE)); | |
101 | printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", | |
102 | readl(host->ioaddr + SDHCI_PRESENT_STATE), | |
103 | readb(host->ioaddr + SDHCI_HOST_CONTROL)); | |
104 | printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", | |
105 | readb(host->ioaddr + SDHCI_POWER_CONTROL), | |
106 | readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL)); | |
107 | printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", | |
108 | readb(host->ioaddr + SDHCI_WALK_UP_CONTROL), | |
109 | readw(host->ioaddr + SDHCI_CLOCK_CONTROL)); | |
110 | printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", | |
111 | readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL), | |
112 | readl(host->ioaddr + SDHCI_INT_STATUS)); | |
113 | printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", | |
114 | readl(host->ioaddr + SDHCI_INT_ENABLE), | |
115 | readl(host->ioaddr + SDHCI_SIGNAL_ENABLE)); | |
116 | printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", | |
117 | readw(host->ioaddr + SDHCI_ACMD12_ERR), | |
118 | readw(host->ioaddr + SDHCI_SLOT_INT_STATUS)); | |
119 | printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n", | |
120 | readl(host->ioaddr + SDHCI_CAPABILITIES), | |
121 | readl(host->ioaddr + SDHCI_MAX_CURRENT)); | |
122 | ||
123 | printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n"); | |
124 | } | |
125 | ||
126 | /*****************************************************************************\ | |
127 | * * | |
128 | * Low level functions * | |
129 | * * | |
130 | \*****************************************************************************/ | |
131 | ||
132 | static void sdhci_reset(struct sdhci_host *host, u8 mask) | |
133 | { | |
e16514d8 PO |
134 | unsigned long timeout; |
135 | ||
8a4da143 PO |
136 | if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { |
137 | if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & | |
138 | SDHCI_CARD_PRESENT)) | |
139 | return; | |
140 | } | |
141 | ||
d129bceb PO |
142 | writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET); |
143 | ||
e16514d8 | 144 | if (mask & SDHCI_RESET_ALL) |
d129bceb PO |
145 | host->clock = 0; |
146 | ||
e16514d8 PO |
147 | /* Wait max 100 ms */ |
148 | timeout = 100; | |
149 | ||
150 | /* hw clears the bit when it's done */ | |
151 | while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) { | |
152 | if (timeout == 0) { | |
acf1da45 | 153 | printk(KERN_ERR "%s: Reset 0x%x never completed.\n", |
e16514d8 PO |
154 | mmc_hostname(host->mmc), (int)mask); |
155 | sdhci_dumpregs(host); | |
156 | return; | |
157 | } | |
158 | timeout--; | |
159 | mdelay(1); | |
d129bceb PO |
160 | } |
161 | } | |
162 | ||
163 | static void sdhci_init(struct sdhci_host *host) | |
164 | { | |
165 | u32 intmask; | |
166 | ||
167 | sdhci_reset(host, SDHCI_RESET_ALL); | |
168 | ||
3192a28f PO |
169 | intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | |
170 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | | |
171 | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | | |
172 | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | | |
a406f5a3 | 173 | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | |
3192a28f | 174 | SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE; |
d129bceb PO |
175 | |
176 | writel(intmask, host->ioaddr + SDHCI_INT_ENABLE); | |
177 | writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE); | |
d129bceb PO |
178 | } |
179 | ||
180 | static void sdhci_activate_led(struct sdhci_host *host) | |
181 | { | |
182 | u8 ctrl; | |
183 | ||
184 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); | |
185 | ctrl |= SDHCI_CTRL_LED; | |
186 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); | |
187 | } | |
188 | ||
189 | static void sdhci_deactivate_led(struct sdhci_host *host) | |
190 | { | |
191 | u8 ctrl; | |
192 | ||
193 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); | |
194 | ctrl &= ~SDHCI_CTRL_LED; | |
195 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); | |
196 | } | |
197 | ||
198 | /*****************************************************************************\ | |
199 | * * | |
200 | * Core functions * | |
201 | * * | |
202 | \*****************************************************************************/ | |
203 | ||
2a22b14e | 204 | static inline char* sdhci_sg_to_buffer(struct sdhci_host* host) |
d129bceb | 205 | { |
2a22b14e | 206 | return page_address(host->cur_sg->page) + host->cur_sg->offset; |
d129bceb PO |
207 | } |
208 | ||
209 | static inline int sdhci_next_sg(struct sdhci_host* host) | |
210 | { | |
211 | /* | |
212 | * Skip to next SG entry. | |
213 | */ | |
214 | host->cur_sg++; | |
215 | host->num_sg--; | |
216 | ||
217 | /* | |
218 | * Any entries left? | |
219 | */ | |
220 | if (host->num_sg > 0) { | |
221 | host->offset = 0; | |
222 | host->remain = host->cur_sg->length; | |
223 | } | |
224 | ||
225 | return host->num_sg; | |
226 | } | |
227 | ||
a406f5a3 | 228 | static void sdhci_read_block_pio(struct sdhci_host *host) |
d129bceb | 229 | { |
a406f5a3 PO |
230 | int blksize, chunk_remain; |
231 | u32 data; | |
d129bceb | 232 | char *buffer; |
a406f5a3 | 233 | int size; |
d129bceb | 234 | |
a406f5a3 | 235 | DBG("PIO reading\n"); |
d129bceb | 236 | |
a406f5a3 PO |
237 | blksize = host->data->blksz; |
238 | chunk_remain = 0; | |
239 | data = 0; | |
d129bceb | 240 | |
2a22b14e | 241 | buffer = sdhci_sg_to_buffer(host) + host->offset; |
d129bceb | 242 | |
a406f5a3 PO |
243 | while (blksize) { |
244 | if (chunk_remain == 0) { | |
245 | data = readl(host->ioaddr + SDHCI_BUFFER); | |
246 | chunk_remain = min(blksize, 4); | |
247 | } | |
d129bceb | 248 | |
14d836e7 | 249 | size = min(host->remain, chunk_remain); |
d129bceb | 250 | |
a406f5a3 PO |
251 | chunk_remain -= size; |
252 | blksize -= size; | |
253 | host->offset += size; | |
254 | host->remain -= size; | |
14d836e7 | 255 | |
a406f5a3 PO |
256 | while (size) { |
257 | *buffer = data & 0xFF; | |
258 | buffer++; | |
259 | data >>= 8; | |
260 | size--; | |
261 | } | |
d129bceb | 262 | |
a406f5a3 | 263 | if (host->remain == 0) { |
a406f5a3 PO |
264 | if (sdhci_next_sg(host) == 0) { |
265 | BUG_ON(blksize != 0); | |
266 | return; | |
267 | } | |
2a22b14e | 268 | buffer = sdhci_sg_to_buffer(host); |
d129bceb | 269 | } |
a406f5a3 | 270 | } |
a406f5a3 | 271 | } |
d129bceb | 272 | |
a406f5a3 PO |
273 | static void sdhci_write_block_pio(struct sdhci_host *host) |
274 | { | |
275 | int blksize, chunk_remain; | |
276 | u32 data; | |
277 | char *buffer; | |
278 | int bytes, size; | |
d129bceb | 279 | |
a406f5a3 PO |
280 | DBG("PIO writing\n"); |
281 | ||
282 | blksize = host->data->blksz; | |
283 | chunk_remain = 4; | |
284 | data = 0; | |
d129bceb | 285 | |
a406f5a3 | 286 | bytes = 0; |
2a22b14e | 287 | buffer = sdhci_sg_to_buffer(host) + host->offset; |
d129bceb | 288 | |
a406f5a3 | 289 | while (blksize) { |
14d836e7 | 290 | size = min(host->remain, chunk_remain); |
a406f5a3 PO |
291 | |
292 | chunk_remain -= size; | |
293 | blksize -= size; | |
d129bceb PO |
294 | host->offset += size; |
295 | host->remain -= size; | |
14d836e7 | 296 | |
a406f5a3 PO |
297 | while (size) { |
298 | data >>= 8; | |
299 | data |= (u32)*buffer << 24; | |
300 | buffer++; | |
301 | size--; | |
302 | } | |
303 | ||
304 | if (chunk_remain == 0) { | |
305 | writel(data, host->ioaddr + SDHCI_BUFFER); | |
306 | chunk_remain = min(blksize, 4); | |
307 | } | |
d129bceb PO |
308 | |
309 | if (host->remain == 0) { | |
d129bceb | 310 | if (sdhci_next_sg(host) == 0) { |
a406f5a3 | 311 | BUG_ON(blksize != 0); |
d129bceb PO |
312 | return; |
313 | } | |
2a22b14e | 314 | buffer = sdhci_sg_to_buffer(host); |
d129bceb PO |
315 | } |
316 | } | |
a406f5a3 PO |
317 | } |
318 | ||
319 | static void sdhci_transfer_pio(struct sdhci_host *host) | |
320 | { | |
321 | u32 mask; | |
322 | ||
323 | BUG_ON(!host->data); | |
324 | ||
14d836e7 | 325 | if (host->num_sg == 0) |
a406f5a3 PO |
326 | return; |
327 | ||
328 | if (host->data->flags & MMC_DATA_READ) | |
329 | mask = SDHCI_DATA_AVAILABLE; | |
330 | else | |
331 | mask = SDHCI_SPACE_AVAILABLE; | |
332 | ||
333 | while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) { | |
334 | if (host->data->flags & MMC_DATA_READ) | |
335 | sdhci_read_block_pio(host); | |
336 | else | |
337 | sdhci_write_block_pio(host); | |
d129bceb | 338 | |
14d836e7 | 339 | if (host->num_sg == 0) |
a406f5a3 | 340 | break; |
a406f5a3 | 341 | } |
d129bceb | 342 | |
a406f5a3 | 343 | DBG("PIO transfer complete.\n"); |
d129bceb PO |
344 | } |
345 | ||
346 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) | |
347 | { | |
1c8cde92 PO |
348 | u8 count; |
349 | unsigned target_timeout, current_timeout; | |
d129bceb PO |
350 | |
351 | WARN_ON(host->data); | |
352 | ||
c7fa9963 | 353 | if (data == NULL) |
d129bceb | 354 | return; |
d129bceb PO |
355 | |
356 | DBG("blksz %04x blks %04x flags %08x\n", | |
a3fd4a1b | 357 | data->blksz, data->blocks, data->flags); |
d129bceb PO |
358 | DBG("tsac %d ms nsac %d clk\n", |
359 | data->timeout_ns / 1000000, data->timeout_clks); | |
360 | ||
bab76961 PO |
361 | /* Sanity checks */ |
362 | BUG_ON(data->blksz * data->blocks > 524288); | |
fe4a3c7a | 363 | BUG_ON(data->blksz > host->mmc->max_blk_size); |
1d676e02 | 364 | BUG_ON(data->blocks > 65535); |
d129bceb | 365 | |
1c8cde92 PO |
366 | /* timeout in us */ |
367 | target_timeout = data->timeout_ns / 1000 + | |
368 | data->timeout_clks / host->clock; | |
d129bceb | 369 | |
1c8cde92 PO |
370 | /* |
371 | * Figure out needed cycles. | |
372 | * We do this in steps in order to fit inside a 32 bit int. | |
373 | * The first step is the minimum timeout, which will have a | |
374 | * minimum resolution of 6 bits: | |
375 | * (1) 2^13*1000 > 2^22, | |
376 | * (2) host->timeout_clk < 2^16 | |
377 | * => | |
378 | * (1) / (2) > 2^6 | |
379 | */ | |
380 | count = 0; | |
381 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; | |
382 | while (current_timeout < target_timeout) { | |
383 | count++; | |
384 | current_timeout <<= 1; | |
385 | if (count >= 0xF) | |
386 | break; | |
387 | } | |
388 | ||
389 | if (count >= 0xF) { | |
390 | printk(KERN_WARNING "%s: Too large timeout requested!\n", | |
391 | mmc_hostname(host->mmc)); | |
392 | count = 0xE; | |
393 | } | |
394 | ||
395 | writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL); | |
d129bceb PO |
396 | |
397 | if (host->flags & SDHCI_USE_DMA) { | |
398 | int count; | |
399 | ||
400 | count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len, | |
401 | (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE); | |
402 | BUG_ON(count != 1); | |
403 | ||
404 | writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS); | |
405 | } else { | |
d129bceb PO |
406 | host->cur_sg = data->sg; |
407 | host->num_sg = data->sg_len; | |
408 | ||
409 | host->offset = 0; | |
410 | host->remain = host->cur_sg->length; | |
411 | } | |
c7fa9963 | 412 | |
bab76961 PO |
413 | /* We do not handle DMA boundaries, so set it to max (512 KiB) */ |
414 | writew(SDHCI_MAKE_BLKSZ(7, data->blksz), | |
415 | host->ioaddr + SDHCI_BLOCK_SIZE); | |
c7fa9963 PO |
416 | writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT); |
417 | } | |
418 | ||
419 | static void sdhci_set_transfer_mode(struct sdhci_host *host, | |
420 | struct mmc_data *data) | |
421 | { | |
422 | u16 mode; | |
423 | ||
424 | WARN_ON(host->data); | |
425 | ||
426 | if (data == NULL) | |
427 | return; | |
428 | ||
429 | mode = SDHCI_TRNS_BLK_CNT_EN; | |
430 | if (data->blocks > 1) | |
431 | mode |= SDHCI_TRNS_MULTI; | |
432 | if (data->flags & MMC_DATA_READ) | |
433 | mode |= SDHCI_TRNS_READ; | |
434 | if (host->flags & SDHCI_USE_DMA) | |
435 | mode |= SDHCI_TRNS_DMA; | |
436 | ||
437 | writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE); | |
d129bceb PO |
438 | } |
439 | ||
440 | static void sdhci_finish_data(struct sdhci_host *host) | |
441 | { | |
442 | struct mmc_data *data; | |
d129bceb PO |
443 | u16 blocks; |
444 | ||
445 | BUG_ON(!host->data); | |
446 | ||
447 | data = host->data; | |
448 | host->data = NULL; | |
449 | ||
450 | if (host->flags & SDHCI_USE_DMA) { | |
451 | pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len, | |
452 | (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE); | |
d129bceb PO |
453 | } |
454 | ||
455 | /* | |
456 | * Controller doesn't count down when in single block mode. | |
457 | */ | |
458 | if ((data->blocks == 1) && (data->error == MMC_ERR_NONE)) | |
459 | blocks = 0; | |
460 | else | |
461 | blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT); | |
a3fd4a1b | 462 | data->bytes_xfered = data->blksz * (data->blocks - blocks); |
d129bceb PO |
463 | |
464 | if ((data->error == MMC_ERR_NONE) && blocks) { | |
465 | printk(KERN_ERR "%s: Controller signalled completion even " | |
acf1da45 PO |
466 | "though there were blocks left.\n", |
467 | mmc_hostname(host->mmc)); | |
d129bceb | 468 | data->error = MMC_ERR_FAILED; |
d129bceb PO |
469 | } |
470 | ||
471 | DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered); | |
472 | ||
473 | if (data->stop) { | |
474 | /* | |
475 | * The controller needs a reset of internal state machines | |
476 | * upon error conditions. | |
477 | */ | |
478 | if (data->error != MMC_ERR_NONE) { | |
479 | sdhci_reset(host, SDHCI_RESET_CMD); | |
480 | sdhci_reset(host, SDHCI_RESET_DATA); | |
481 | } | |
482 | ||
483 | sdhci_send_command(host, data->stop); | |
484 | } else | |
485 | tasklet_schedule(&host->finish_tasklet); | |
486 | } | |
487 | ||
488 | static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) | |
489 | { | |
490 | int flags; | |
fd2208d7 | 491 | u32 mask; |
7cb2c76f | 492 | unsigned long timeout; |
d129bceb PO |
493 | |
494 | WARN_ON(host->cmd); | |
495 | ||
496 | DBG("Sending cmd (%x)\n", cmd->opcode); | |
497 | ||
498 | /* Wait max 10 ms */ | |
7cb2c76f | 499 | timeout = 10; |
fd2208d7 PO |
500 | |
501 | mask = SDHCI_CMD_INHIBIT; | |
502 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) | |
503 | mask |= SDHCI_DATA_INHIBIT; | |
504 | ||
505 | /* We shouldn't wait for data inihibit for stop commands, even | |
506 | though they might use busy signaling */ | |
507 | if (host->mrq->data && (cmd == host->mrq->data->stop)) | |
508 | mask &= ~SDHCI_DATA_INHIBIT; | |
509 | ||
510 | while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) { | |
7cb2c76f | 511 | if (timeout == 0) { |
d129bceb | 512 | printk(KERN_ERR "%s: Controller never released " |
acf1da45 | 513 | "inhibit bit(s).\n", mmc_hostname(host->mmc)); |
d129bceb PO |
514 | sdhci_dumpregs(host); |
515 | cmd->error = MMC_ERR_FAILED; | |
516 | tasklet_schedule(&host->finish_tasklet); | |
517 | return; | |
518 | } | |
7cb2c76f PO |
519 | timeout--; |
520 | mdelay(1); | |
521 | } | |
d129bceb PO |
522 | |
523 | mod_timer(&host->timer, jiffies + 10 * HZ); | |
524 | ||
525 | host->cmd = cmd; | |
526 | ||
527 | sdhci_prepare_data(host, cmd->data); | |
528 | ||
529 | writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT); | |
530 | ||
c7fa9963 PO |
531 | sdhci_set_transfer_mode(host, cmd->data); |
532 | ||
d129bceb | 533 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
acf1da45 | 534 | printk(KERN_ERR "%s: Unsupported response type!\n", |
d129bceb PO |
535 | mmc_hostname(host->mmc)); |
536 | cmd->error = MMC_ERR_INVALID; | |
537 | tasklet_schedule(&host->finish_tasklet); | |
538 | return; | |
539 | } | |
540 | ||
541 | if (!(cmd->flags & MMC_RSP_PRESENT)) | |
542 | flags = SDHCI_CMD_RESP_NONE; | |
543 | else if (cmd->flags & MMC_RSP_136) | |
544 | flags = SDHCI_CMD_RESP_LONG; | |
545 | else if (cmd->flags & MMC_RSP_BUSY) | |
546 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
547 | else | |
548 | flags = SDHCI_CMD_RESP_SHORT; | |
549 | ||
550 | if (cmd->flags & MMC_RSP_CRC) | |
551 | flags |= SDHCI_CMD_CRC; | |
552 | if (cmd->flags & MMC_RSP_OPCODE) | |
553 | flags |= SDHCI_CMD_INDEX; | |
554 | if (cmd->data) | |
555 | flags |= SDHCI_CMD_DATA; | |
556 | ||
fb61e289 | 557 | writew(SDHCI_MAKE_CMD(cmd->opcode, flags), |
d129bceb PO |
558 | host->ioaddr + SDHCI_COMMAND); |
559 | } | |
560 | ||
561 | static void sdhci_finish_command(struct sdhci_host *host) | |
562 | { | |
563 | int i; | |
564 | ||
565 | BUG_ON(host->cmd == NULL); | |
566 | ||
567 | if (host->cmd->flags & MMC_RSP_PRESENT) { | |
568 | if (host->cmd->flags & MMC_RSP_136) { | |
569 | /* CRC is stripped so we need to do some shifting. */ | |
570 | for (i = 0;i < 4;i++) { | |
571 | host->cmd->resp[i] = readl(host->ioaddr + | |
572 | SDHCI_RESPONSE + (3-i)*4) << 8; | |
573 | if (i != 3) | |
574 | host->cmd->resp[i] |= | |
575 | readb(host->ioaddr + | |
576 | SDHCI_RESPONSE + (3-i)*4-1); | |
577 | } | |
578 | } else { | |
579 | host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE); | |
580 | } | |
581 | } | |
582 | ||
583 | host->cmd->error = MMC_ERR_NONE; | |
584 | ||
585 | DBG("Ending cmd (%x)\n", host->cmd->opcode); | |
586 | ||
3192a28f | 587 | if (host->cmd->data) |
d129bceb | 588 | host->data = host->cmd->data; |
3192a28f | 589 | else |
d129bceb PO |
590 | tasklet_schedule(&host->finish_tasklet); |
591 | ||
592 | host->cmd = NULL; | |
593 | } | |
594 | ||
595 | static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) | |
596 | { | |
597 | int div; | |
598 | u16 clk; | |
7cb2c76f | 599 | unsigned long timeout; |
d129bceb PO |
600 | |
601 | if (clock == host->clock) | |
602 | return; | |
603 | ||
604 | writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
605 | ||
606 | if (clock == 0) | |
607 | goto out; | |
608 | ||
609 | for (div = 1;div < 256;div *= 2) { | |
610 | if ((host->max_clk / div) <= clock) | |
611 | break; | |
612 | } | |
613 | div >>= 1; | |
614 | ||
615 | clk = div << SDHCI_DIVIDER_SHIFT; | |
616 | clk |= SDHCI_CLOCK_INT_EN; | |
617 | writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
618 | ||
619 | /* Wait max 10 ms */ | |
7cb2c76f PO |
620 | timeout = 10; |
621 | while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL)) | |
622 | & SDHCI_CLOCK_INT_STABLE)) { | |
623 | if (timeout == 0) { | |
acf1da45 PO |
624 | printk(KERN_ERR "%s: Internal clock never " |
625 | "stabilised.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
626 | sdhci_dumpregs(host); |
627 | return; | |
628 | } | |
7cb2c76f PO |
629 | timeout--; |
630 | mdelay(1); | |
631 | } | |
d129bceb PO |
632 | |
633 | clk |= SDHCI_CLOCK_CARD_EN; | |
634 | writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
635 | ||
636 | out: | |
637 | host->clock = clock; | |
638 | } | |
639 | ||
146ad66e PO |
640 | static void sdhci_set_power(struct sdhci_host *host, unsigned short power) |
641 | { | |
642 | u8 pwr; | |
643 | ||
644 | if (host->power == power) | |
645 | return; | |
646 | ||
9e9dc5f2 DS |
647 | if (power == (unsigned short)-1) { |
648 | writeb(0, host->ioaddr + SDHCI_POWER_CONTROL); | |
146ad66e | 649 | goto out; |
9e9dc5f2 DS |
650 | } |
651 | ||
652 | /* | |
653 | * Spec says that we should clear the power reg before setting | |
654 | * a new value. Some controllers don't seem to like this though. | |
655 | */ | |
656 | if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) | |
657 | writeb(0, host->ioaddr + SDHCI_POWER_CONTROL); | |
146ad66e PO |
658 | |
659 | pwr = SDHCI_POWER_ON; | |
660 | ||
4be34c99 | 661 | switch (1 << power) { |
55556da0 | 662 | case MMC_VDD_165_195: |
146ad66e PO |
663 | pwr |= SDHCI_POWER_180; |
664 | break; | |
4be34c99 PL |
665 | case MMC_VDD_29_30: |
666 | case MMC_VDD_30_31: | |
146ad66e PO |
667 | pwr |= SDHCI_POWER_300; |
668 | break; | |
4be34c99 PL |
669 | case MMC_VDD_32_33: |
670 | case MMC_VDD_33_34: | |
146ad66e PO |
671 | pwr |= SDHCI_POWER_330; |
672 | break; | |
673 | default: | |
674 | BUG(); | |
675 | } | |
676 | ||
677 | writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL); | |
678 | ||
679 | out: | |
680 | host->power = power; | |
681 | } | |
682 | ||
d129bceb PO |
683 | /*****************************************************************************\ |
684 | * * | |
685 | * MMC callbacks * | |
686 | * * | |
687 | \*****************************************************************************/ | |
688 | ||
689 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
690 | { | |
691 | struct sdhci_host *host; | |
692 | unsigned long flags; | |
693 | ||
694 | host = mmc_priv(mmc); | |
695 | ||
696 | spin_lock_irqsave(&host->lock, flags); | |
697 | ||
698 | WARN_ON(host->mrq != NULL); | |
699 | ||
700 | sdhci_activate_led(host); | |
701 | ||
702 | host->mrq = mrq; | |
703 | ||
704 | if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { | |
705 | host->mrq->cmd->error = MMC_ERR_TIMEOUT; | |
706 | tasklet_schedule(&host->finish_tasklet); | |
707 | } else | |
708 | sdhci_send_command(host, mrq->cmd); | |
709 | ||
5f25a66f | 710 | mmiowb(); |
d129bceb PO |
711 | spin_unlock_irqrestore(&host->lock, flags); |
712 | } | |
713 | ||
714 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
715 | { | |
716 | struct sdhci_host *host; | |
717 | unsigned long flags; | |
718 | u8 ctrl; | |
719 | ||
720 | host = mmc_priv(mmc); | |
721 | ||
722 | spin_lock_irqsave(&host->lock, flags); | |
723 | ||
d129bceb PO |
724 | /* |
725 | * Reset the chip on each power off. | |
726 | * Should clear out any weird states. | |
727 | */ | |
728 | if (ios->power_mode == MMC_POWER_OFF) { | |
729 | writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE); | |
d129bceb | 730 | sdhci_init(host); |
d129bceb PO |
731 | } |
732 | ||
733 | sdhci_set_clock(host, ios->clock); | |
734 | ||
735 | if (ios->power_mode == MMC_POWER_OFF) | |
146ad66e | 736 | sdhci_set_power(host, -1); |
d129bceb | 737 | else |
146ad66e | 738 | sdhci_set_power(host, ios->vdd); |
d129bceb PO |
739 | |
740 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); | |
cd9277c0 | 741 | |
d129bceb PO |
742 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
743 | ctrl |= SDHCI_CTRL_4BITBUS; | |
744 | else | |
745 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
cd9277c0 PO |
746 | |
747 | if (ios->timing == MMC_TIMING_SD_HS) | |
748 | ctrl |= SDHCI_CTRL_HISPD; | |
749 | else | |
750 | ctrl &= ~SDHCI_CTRL_HISPD; | |
751 | ||
d129bceb PO |
752 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); |
753 | ||
5f25a66f | 754 | mmiowb(); |
d129bceb PO |
755 | spin_unlock_irqrestore(&host->lock, flags); |
756 | } | |
757 | ||
758 | static int sdhci_get_ro(struct mmc_host *mmc) | |
759 | { | |
760 | struct sdhci_host *host; | |
761 | unsigned long flags; | |
762 | int present; | |
763 | ||
764 | host = mmc_priv(mmc); | |
765 | ||
766 | spin_lock_irqsave(&host->lock, flags); | |
767 | ||
768 | present = readl(host->ioaddr + SDHCI_PRESENT_STATE); | |
769 | ||
770 | spin_unlock_irqrestore(&host->lock, flags); | |
771 | ||
772 | return !(present & SDHCI_WRITE_PROTECT); | |
773 | } | |
774 | ||
ab7aefd0 | 775 | static const struct mmc_host_ops sdhci_ops = { |
d129bceb PO |
776 | .request = sdhci_request, |
777 | .set_ios = sdhci_set_ios, | |
778 | .get_ro = sdhci_get_ro, | |
779 | }; | |
780 | ||
781 | /*****************************************************************************\ | |
782 | * * | |
783 | * Tasklets * | |
784 | * * | |
785 | \*****************************************************************************/ | |
786 | ||
787 | static void sdhci_tasklet_card(unsigned long param) | |
788 | { | |
789 | struct sdhci_host *host; | |
790 | unsigned long flags; | |
791 | ||
792 | host = (struct sdhci_host*)param; | |
793 | ||
794 | spin_lock_irqsave(&host->lock, flags); | |
795 | ||
796 | if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { | |
797 | if (host->mrq) { | |
798 | printk(KERN_ERR "%s: Card removed during transfer!\n", | |
799 | mmc_hostname(host->mmc)); | |
800 | printk(KERN_ERR "%s: Resetting controller.\n", | |
801 | mmc_hostname(host->mmc)); | |
802 | ||
803 | sdhci_reset(host, SDHCI_RESET_CMD); | |
804 | sdhci_reset(host, SDHCI_RESET_DATA); | |
805 | ||
806 | host->mrq->cmd->error = MMC_ERR_FAILED; | |
807 | tasklet_schedule(&host->finish_tasklet); | |
808 | } | |
809 | } | |
810 | ||
811 | spin_unlock_irqrestore(&host->lock, flags); | |
812 | ||
813 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); | |
814 | } | |
815 | ||
816 | static void sdhci_tasklet_finish(unsigned long param) | |
817 | { | |
818 | struct sdhci_host *host; | |
819 | unsigned long flags; | |
820 | struct mmc_request *mrq; | |
821 | ||
822 | host = (struct sdhci_host*)param; | |
823 | ||
824 | spin_lock_irqsave(&host->lock, flags); | |
825 | ||
826 | del_timer(&host->timer); | |
827 | ||
828 | mrq = host->mrq; | |
829 | ||
830 | DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode); | |
831 | ||
832 | /* | |
833 | * The controller needs a reset of internal state machines | |
834 | * upon error conditions. | |
835 | */ | |
836 | if ((mrq->cmd->error != MMC_ERR_NONE) || | |
837 | (mrq->data && ((mrq->data->error != MMC_ERR_NONE) || | |
838 | (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) { | |
645289dc PO |
839 | |
840 | /* Some controllers need this kick or reset won't work here */ | |
841 | if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) { | |
842 | unsigned int clock; | |
843 | ||
844 | /* This is to force an update */ | |
845 | clock = host->clock; | |
846 | host->clock = 0; | |
847 | sdhci_set_clock(host, clock); | |
848 | } | |
849 | ||
850 | /* Spec says we should do both at the same time, but Ricoh | |
851 | controllers do not like that. */ | |
d129bceb PO |
852 | sdhci_reset(host, SDHCI_RESET_CMD); |
853 | sdhci_reset(host, SDHCI_RESET_DATA); | |
854 | } | |
855 | ||
856 | host->mrq = NULL; | |
857 | host->cmd = NULL; | |
858 | host->data = NULL; | |
859 | ||
860 | sdhci_deactivate_led(host); | |
861 | ||
5f25a66f | 862 | mmiowb(); |
d129bceb PO |
863 | spin_unlock_irqrestore(&host->lock, flags); |
864 | ||
865 | mmc_request_done(host->mmc, mrq); | |
866 | } | |
867 | ||
868 | static void sdhci_timeout_timer(unsigned long data) | |
869 | { | |
870 | struct sdhci_host *host; | |
871 | unsigned long flags; | |
872 | ||
873 | host = (struct sdhci_host*)data; | |
874 | ||
875 | spin_lock_irqsave(&host->lock, flags); | |
876 | ||
877 | if (host->mrq) { | |
acf1da45 PO |
878 | printk(KERN_ERR "%s: Timeout waiting for hardware " |
879 | "interrupt.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
880 | sdhci_dumpregs(host); |
881 | ||
882 | if (host->data) { | |
883 | host->data->error = MMC_ERR_TIMEOUT; | |
884 | sdhci_finish_data(host); | |
885 | } else { | |
886 | if (host->cmd) | |
887 | host->cmd->error = MMC_ERR_TIMEOUT; | |
888 | else | |
889 | host->mrq->cmd->error = MMC_ERR_TIMEOUT; | |
890 | ||
891 | tasklet_schedule(&host->finish_tasklet); | |
892 | } | |
893 | } | |
894 | ||
5f25a66f | 895 | mmiowb(); |
d129bceb PO |
896 | spin_unlock_irqrestore(&host->lock, flags); |
897 | } | |
898 | ||
899 | /*****************************************************************************\ | |
900 | * * | |
901 | * Interrupt handling * | |
902 | * * | |
903 | \*****************************************************************************/ | |
904 | ||
905 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) | |
906 | { | |
907 | BUG_ON(intmask == 0); | |
908 | ||
909 | if (!host->cmd) { | |
910 | printk(KERN_ERR "%s: Got command interrupt even though no " | |
911 | "command operation was in progress.\n", | |
912 | mmc_hostname(host->mmc)); | |
d129bceb PO |
913 | sdhci_dumpregs(host); |
914 | return; | |
915 | } | |
916 | ||
917 | if (intmask & SDHCI_INT_RESPONSE) | |
918 | sdhci_finish_command(host); | |
919 | else { | |
920 | if (intmask & SDHCI_INT_TIMEOUT) | |
921 | host->cmd->error = MMC_ERR_TIMEOUT; | |
922 | else if (intmask & SDHCI_INT_CRC) | |
923 | host->cmd->error = MMC_ERR_BADCRC; | |
924 | else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) | |
925 | host->cmd->error = MMC_ERR_FAILED; | |
926 | else | |
927 | host->cmd->error = MMC_ERR_INVALID; | |
928 | ||
929 | tasklet_schedule(&host->finish_tasklet); | |
930 | } | |
931 | } | |
932 | ||
933 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) | |
934 | { | |
935 | BUG_ON(intmask == 0); | |
936 | ||
937 | if (!host->data) { | |
938 | /* | |
939 | * A data end interrupt is sent together with the response | |
940 | * for the stop command. | |
941 | */ | |
942 | if (intmask & SDHCI_INT_DATA_END) | |
943 | return; | |
944 | ||
945 | printk(KERN_ERR "%s: Got data interrupt even though no " | |
946 | "data operation was in progress.\n", | |
947 | mmc_hostname(host->mmc)); | |
d129bceb PO |
948 | sdhci_dumpregs(host); |
949 | ||
950 | return; | |
951 | } | |
952 | ||
953 | if (intmask & SDHCI_INT_DATA_TIMEOUT) | |
954 | host->data->error = MMC_ERR_TIMEOUT; | |
955 | else if (intmask & SDHCI_INT_DATA_CRC) | |
956 | host->data->error = MMC_ERR_BADCRC; | |
957 | else if (intmask & SDHCI_INT_DATA_END_BIT) | |
958 | host->data->error = MMC_ERR_FAILED; | |
959 | ||
960 | if (host->data->error != MMC_ERR_NONE) | |
961 | sdhci_finish_data(host); | |
962 | else { | |
a406f5a3 | 963 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
d129bceb PO |
964 | sdhci_transfer_pio(host); |
965 | ||
6ba736a1 PO |
966 | /* |
967 | * We currently don't do anything fancy with DMA | |
968 | * boundaries, but as we can't disable the feature | |
969 | * we need to at least restart the transfer. | |
970 | */ | |
971 | if (intmask & SDHCI_INT_DMA_END) | |
972 | writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS), | |
973 | host->ioaddr + SDHCI_DMA_ADDRESS); | |
974 | ||
d129bceb PO |
975 | if (intmask & SDHCI_INT_DATA_END) |
976 | sdhci_finish_data(host); | |
977 | } | |
978 | } | |
979 | ||
7d12e780 | 980 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
d129bceb PO |
981 | { |
982 | irqreturn_t result; | |
983 | struct sdhci_host* host = dev_id; | |
984 | u32 intmask; | |
985 | ||
986 | spin_lock(&host->lock); | |
987 | ||
988 | intmask = readl(host->ioaddr + SDHCI_INT_STATUS); | |
989 | ||
62df67a5 | 990 | if (!intmask || intmask == 0xffffffff) { |
d129bceb PO |
991 | result = IRQ_NONE; |
992 | goto out; | |
993 | } | |
994 | ||
995 | DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask); | |
996 | ||
3192a28f PO |
997 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
998 | writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE), | |
999 | host->ioaddr + SDHCI_INT_STATUS); | |
d129bceb | 1000 | tasklet_schedule(&host->card_tasklet); |
3192a28f | 1001 | } |
d129bceb | 1002 | |
3192a28f | 1003 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); |
d129bceb | 1004 | |
3192a28f | 1005 | if (intmask & SDHCI_INT_CMD_MASK) { |
d129bceb PO |
1006 | writel(intmask & SDHCI_INT_CMD_MASK, |
1007 | host->ioaddr + SDHCI_INT_STATUS); | |
3192a28f | 1008 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); |
d129bceb PO |
1009 | } |
1010 | ||
1011 | if (intmask & SDHCI_INT_DATA_MASK) { | |
d129bceb PO |
1012 | writel(intmask & SDHCI_INT_DATA_MASK, |
1013 | host->ioaddr + SDHCI_INT_STATUS); | |
3192a28f | 1014 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); |
d129bceb PO |
1015 | } |
1016 | ||
1017 | intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); | |
1018 | ||
d129bceb | 1019 | if (intmask & SDHCI_INT_BUS_POWER) { |
3192a28f | 1020 | printk(KERN_ERR "%s: Card is consuming too much power!\n", |
d129bceb | 1021 | mmc_hostname(host->mmc)); |
3192a28f | 1022 | writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS); |
d129bceb PO |
1023 | } |
1024 | ||
3192a28f PO |
1025 | intmask &= SDHCI_INT_BUS_POWER; |
1026 | ||
1027 | if (intmask) { | |
acf1da45 | 1028 | printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n", |
3192a28f | 1029 | mmc_hostname(host->mmc), intmask); |
d129bceb PO |
1030 | sdhci_dumpregs(host); |
1031 | ||
d129bceb | 1032 | writel(intmask, host->ioaddr + SDHCI_INT_STATUS); |
3192a28f | 1033 | } |
d129bceb PO |
1034 | |
1035 | result = IRQ_HANDLED; | |
1036 | ||
5f25a66f | 1037 | mmiowb(); |
d129bceb PO |
1038 | out: |
1039 | spin_unlock(&host->lock); | |
1040 | ||
1041 | return result; | |
1042 | } | |
1043 | ||
1044 | /*****************************************************************************\ | |
1045 | * * | |
1046 | * Suspend/resume * | |
1047 | * * | |
1048 | \*****************************************************************************/ | |
1049 | ||
1050 | #ifdef CONFIG_PM | |
1051 | ||
1052 | static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state) | |
1053 | { | |
1054 | struct sdhci_chip *chip; | |
1055 | int i, ret; | |
1056 | ||
1057 | chip = pci_get_drvdata(pdev); | |
1058 | if (!chip) | |
1059 | return 0; | |
1060 | ||
1061 | DBG("Suspending...\n"); | |
1062 | ||
1063 | for (i = 0;i < chip->num_slots;i++) { | |
1064 | if (!chip->hosts[i]) | |
1065 | continue; | |
1066 | ret = mmc_suspend_host(chip->hosts[i]->mmc, state); | |
1067 | if (ret) { | |
1068 | for (i--;i >= 0;i--) | |
1069 | mmc_resume_host(chip->hosts[i]->mmc); | |
1070 | return ret; | |
1071 | } | |
1072 | } | |
1073 | ||
1074 | pci_save_state(pdev); | |
1075 | pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); | |
a715dfc7 PO |
1076 | |
1077 | for (i = 0;i < chip->num_slots;i++) { | |
1078 | if (!chip->hosts[i]) | |
1079 | continue; | |
1080 | free_irq(chip->hosts[i]->irq, chip->hosts[i]); | |
1081 | } | |
1082 | ||
d129bceb PO |
1083 | pci_disable_device(pdev); |
1084 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1085 | ||
1086 | return 0; | |
1087 | } | |
1088 | ||
1089 | static int sdhci_resume (struct pci_dev *pdev) | |
1090 | { | |
1091 | struct sdhci_chip *chip; | |
1092 | int i, ret; | |
1093 | ||
1094 | chip = pci_get_drvdata(pdev); | |
1095 | if (!chip) | |
1096 | return 0; | |
1097 | ||
1098 | DBG("Resuming...\n"); | |
1099 | ||
1100 | pci_set_power_state(pdev, PCI_D0); | |
1101 | pci_restore_state(pdev); | |
df1c4b7b PO |
1102 | ret = pci_enable_device(pdev); |
1103 | if (ret) | |
1104 | return ret; | |
d129bceb PO |
1105 | |
1106 | for (i = 0;i < chip->num_slots;i++) { | |
1107 | if (!chip->hosts[i]) | |
1108 | continue; | |
1109 | if (chip->hosts[i]->flags & SDHCI_USE_DMA) | |
1110 | pci_set_master(pdev); | |
a715dfc7 PO |
1111 | ret = request_irq(chip->hosts[i]->irq, sdhci_irq, |
1112 | IRQF_SHARED, chip->hosts[i]->slot_descr, | |
1113 | chip->hosts[i]); | |
1114 | if (ret) | |
1115 | return ret; | |
d129bceb | 1116 | sdhci_init(chip->hosts[i]); |
5f25a66f | 1117 | mmiowb(); |
d129bceb PO |
1118 | ret = mmc_resume_host(chip->hosts[i]->mmc); |
1119 | if (ret) | |
1120 | return ret; | |
1121 | } | |
1122 | ||
1123 | return 0; | |
1124 | } | |
1125 | ||
1126 | #else /* CONFIG_PM */ | |
1127 | ||
1128 | #define sdhci_suspend NULL | |
1129 | #define sdhci_resume NULL | |
1130 | ||
1131 | #endif /* CONFIG_PM */ | |
1132 | ||
1133 | /*****************************************************************************\ | |
1134 | * * | |
1135 | * Device probing/removal * | |
1136 | * * | |
1137 | \*****************************************************************************/ | |
1138 | ||
1139 | static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot) | |
1140 | { | |
1141 | int ret; | |
4a965505 | 1142 | unsigned int version; |
d129bceb PO |
1143 | struct sdhci_chip *chip; |
1144 | struct mmc_host *mmc; | |
1145 | struct sdhci_host *host; | |
1146 | ||
1147 | u8 first_bar; | |
1148 | unsigned int caps; | |
1149 | ||
1150 | chip = pci_get_drvdata(pdev); | |
1151 | BUG_ON(!chip); | |
1152 | ||
1153 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); | |
1154 | if (ret) | |
1155 | return ret; | |
1156 | ||
1157 | first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; | |
1158 | ||
1159 | if (first_bar > 5) { | |
1160 | printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n"); | |
1161 | return -ENODEV; | |
1162 | } | |
1163 | ||
1164 | if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) { | |
1165 | printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n"); | |
1166 | return -ENODEV; | |
1167 | } | |
1168 | ||
1169 | if (pci_resource_len(pdev, first_bar + slot) != 0x100) { | |
a98087cf PO |
1170 | printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. " |
1171 | "You may experience problems.\n"); | |
d129bceb PO |
1172 | } |
1173 | ||
67435274 PO |
1174 | if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { |
1175 | printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n"); | |
1176 | return -ENODEV; | |
1177 | } | |
1178 | ||
1179 | if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { | |
1180 | printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n"); | |
1181 | return -ENODEV; | |
1182 | } | |
1183 | ||
d129bceb PO |
1184 | mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev); |
1185 | if (!mmc) | |
1186 | return -ENOMEM; | |
1187 | ||
1188 | host = mmc_priv(mmc); | |
1189 | host->mmc = mmc; | |
1190 | ||
8a4da143 PO |
1191 | host->chip = chip; |
1192 | chip->hosts[slot] = host; | |
1193 | ||
d129bceb PO |
1194 | host->bar = first_bar + slot; |
1195 | ||
1196 | host->addr = pci_resource_start(pdev, host->bar); | |
1197 | host->irq = pdev->irq; | |
1198 | ||
1199 | DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq); | |
1200 | ||
1201 | snprintf(host->slot_descr, 20, "sdhci:slot%d", slot); | |
1202 | ||
1203 | ret = pci_request_region(pdev, host->bar, host->slot_descr); | |
1204 | if (ret) | |
1205 | goto free; | |
1206 | ||
1207 | host->ioaddr = ioremap_nocache(host->addr, | |
1208 | pci_resource_len(pdev, host->bar)); | |
1209 | if (!host->ioaddr) { | |
1210 | ret = -ENOMEM; | |
1211 | goto release; | |
1212 | } | |
1213 | ||
d96649ed PO |
1214 | sdhci_reset(host, SDHCI_RESET_ALL); |
1215 | ||
4a965505 PO |
1216 | version = readw(host->ioaddr + SDHCI_HOST_VERSION); |
1217 | version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; | |
1218 | if (version != 0) { | |
1219 | printk(KERN_ERR "%s: Unknown controller version (%d). " | |
8b1b2185 | 1220 | "You may experience problems.\n", host->slot_descr, |
4a965505 | 1221 | version); |
4a965505 PO |
1222 | } |
1223 | ||
d129bceb PO |
1224 | caps = readl(host->ioaddr + SDHCI_CAPABILITIES); |
1225 | ||
67435274 PO |
1226 | if (debug_nodma) |
1227 | DBG("DMA forced off\n"); | |
1228 | else if (debug_forcedma) { | |
1229 | DBG("DMA forced on\n"); | |
1230 | host->flags |= SDHCI_USE_DMA; | |
98608076 PO |
1231 | } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA) |
1232 | host->flags |= SDHCI_USE_DMA; | |
1233 | else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) | |
67435274 PO |
1234 | DBG("Controller doesn't have DMA interface\n"); |
1235 | else if (!(caps & SDHCI_CAN_DO_DMA)) | |
1236 | DBG("Controller doesn't have DMA capability\n"); | |
1237 | else | |
d129bceb PO |
1238 | host->flags |= SDHCI_USE_DMA; |
1239 | ||
1240 | if (host->flags & SDHCI_USE_DMA) { | |
1241 | if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { | |
1242 | printk(KERN_WARNING "%s: No suitable DMA available. " | |
1243 | "Falling back to PIO.\n", host->slot_descr); | |
1244 | host->flags &= ~SDHCI_USE_DMA; | |
1245 | } | |
1246 | } | |
1247 | ||
1248 | if (host->flags & SDHCI_USE_DMA) | |
1249 | pci_set_master(pdev); | |
1250 | else /* XXX: Hack to get MMC layer to avoid highmem */ | |
1251 | pdev->dma_mask = 0; | |
1252 | ||
8ef1a143 PO |
1253 | host->max_clk = |
1254 | (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; | |
1255 | if (host->max_clk == 0) { | |
1256 | printk(KERN_ERR "%s: Hardware doesn't specify base clock " | |
1257 | "frequency.\n", host->slot_descr); | |
1258 | ret = -ENODEV; | |
1259 | goto unmap; | |
1260 | } | |
d129bceb PO |
1261 | host->max_clk *= 1000000; |
1262 | ||
1c8cde92 PO |
1263 | host->timeout_clk = |
1264 | (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; | |
1265 | if (host->timeout_clk == 0) { | |
1266 | printk(KERN_ERR "%s: Hardware doesn't specify timeout clock " | |
1267 | "frequency.\n", host->slot_descr); | |
1268 | ret = -ENODEV; | |
1269 | goto unmap; | |
1270 | } | |
1271 | if (caps & SDHCI_TIMEOUT_CLK_UNIT) | |
1272 | host->timeout_clk *= 1000; | |
d129bceb PO |
1273 | |
1274 | /* | |
1275 | * Set host parameters. | |
1276 | */ | |
1277 | mmc->ops = &sdhci_ops; | |
1278 | mmc->f_min = host->max_clk / 256; | |
1279 | mmc->f_max = host->max_clk; | |
42431acb | 1280 | mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK; |
d129bceb | 1281 | |
cd9277c0 PO |
1282 | if (caps & SDHCI_CAN_DO_HISPD) |
1283 | mmc->caps |= MMC_CAP_SD_HIGHSPEED; | |
1284 | ||
146ad66e PO |
1285 | mmc->ocr_avail = 0; |
1286 | if (caps & SDHCI_CAN_VDD_330) | |
1287 | mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34; | |
c70840e8 | 1288 | if (caps & SDHCI_CAN_VDD_300) |
146ad66e | 1289 | mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31; |
c70840e8 | 1290 | if (caps & SDHCI_CAN_VDD_180) |
55556da0 | 1291 | mmc->ocr_avail |= MMC_VDD_165_195; |
146ad66e PO |
1292 | |
1293 | if (mmc->ocr_avail == 0) { | |
1294 | printk(KERN_ERR "%s: Hardware doesn't report any " | |
1295 | "support voltages.\n", host->slot_descr); | |
1296 | ret = -ENODEV; | |
1297 | goto unmap; | |
1298 | } | |
1299 | ||
d129bceb PO |
1300 | spin_lock_init(&host->lock); |
1301 | ||
1302 | /* | |
1303 | * Maximum number of segments. Hardware cannot do scatter lists. | |
1304 | */ | |
1305 | if (host->flags & SDHCI_USE_DMA) | |
1306 | mmc->max_hw_segs = 1; | |
1307 | else | |
1308 | mmc->max_hw_segs = 16; | |
1309 | mmc->max_phys_segs = 16; | |
1310 | ||
1311 | /* | |
bab76961 | 1312 | * Maximum number of sectors in one transfer. Limited by DMA boundary |
55db890a | 1313 | * size (512KiB). |
d129bceb | 1314 | */ |
55db890a | 1315 | mmc->max_req_size = 524288; |
d129bceb PO |
1316 | |
1317 | /* | |
1318 | * Maximum segment size. Could be one segment with the maximum number | |
55db890a | 1319 | * of bytes. |
d129bceb | 1320 | */ |
55db890a | 1321 | mmc->max_seg_size = mmc->max_req_size; |
d129bceb | 1322 | |
fe4a3c7a PO |
1323 | /* |
1324 | * Maximum block size. This varies from controller to controller and | |
1325 | * is specified in the capabilities register. | |
1326 | */ | |
1327 | mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT; | |
1328 | if (mmc->max_blk_size >= 3) { | |
1329 | printk(KERN_ERR "%s: Invalid maximum block size.\n", | |
1330 | host->slot_descr); | |
1331 | ret = -ENODEV; | |
1332 | goto unmap; | |
1333 | } | |
1334 | mmc->max_blk_size = 512 << mmc->max_blk_size; | |
1335 | ||
55db890a PO |
1336 | /* |
1337 | * Maximum block count. | |
1338 | */ | |
1339 | mmc->max_blk_count = 65535; | |
1340 | ||
d129bceb PO |
1341 | /* |
1342 | * Init tasklets. | |
1343 | */ | |
1344 | tasklet_init(&host->card_tasklet, | |
1345 | sdhci_tasklet_card, (unsigned long)host); | |
1346 | tasklet_init(&host->finish_tasklet, | |
1347 | sdhci_tasklet_finish, (unsigned long)host); | |
1348 | ||
e4cad1b5 | 1349 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
d129bceb | 1350 | |
dace1453 | 1351 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
d129bceb PO |
1352 | host->slot_descr, host); |
1353 | if (ret) | |
8ef1a143 | 1354 | goto untasklet; |
d129bceb PO |
1355 | |
1356 | sdhci_init(host); | |
1357 | ||
1358 | #ifdef CONFIG_MMC_DEBUG | |
1359 | sdhci_dumpregs(host); | |
1360 | #endif | |
1361 | ||
5f25a66f PO |
1362 | mmiowb(); |
1363 | ||
d129bceb PO |
1364 | mmc_add_host(mmc); |
1365 | ||
1366 | printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc), | |
1367 | host->addr, host->irq, | |
1368 | (host->flags & SDHCI_USE_DMA)?"DMA":"PIO"); | |
1369 | ||
1370 | return 0; | |
1371 | ||
8ef1a143 | 1372 | untasklet: |
d129bceb PO |
1373 | tasklet_kill(&host->card_tasklet); |
1374 | tasklet_kill(&host->finish_tasklet); | |
8ef1a143 | 1375 | unmap: |
d129bceb PO |
1376 | iounmap(host->ioaddr); |
1377 | release: | |
1378 | pci_release_region(pdev, host->bar); | |
1379 | free: | |
1380 | mmc_free_host(mmc); | |
1381 | ||
1382 | return ret; | |
1383 | } | |
1384 | ||
1385 | static void sdhci_remove_slot(struct pci_dev *pdev, int slot) | |
1386 | { | |
1387 | struct sdhci_chip *chip; | |
1388 | struct mmc_host *mmc; | |
1389 | struct sdhci_host *host; | |
1390 | ||
1391 | chip = pci_get_drvdata(pdev); | |
1392 | host = chip->hosts[slot]; | |
1393 | mmc = host->mmc; | |
1394 | ||
1395 | chip->hosts[slot] = NULL; | |
1396 | ||
1397 | mmc_remove_host(mmc); | |
1398 | ||
1399 | sdhci_reset(host, SDHCI_RESET_ALL); | |
1400 | ||
1401 | free_irq(host->irq, host); | |
1402 | ||
1403 | del_timer_sync(&host->timer); | |
1404 | ||
1405 | tasklet_kill(&host->card_tasklet); | |
1406 | tasklet_kill(&host->finish_tasklet); | |
1407 | ||
1408 | iounmap(host->ioaddr); | |
1409 | ||
1410 | pci_release_region(pdev, host->bar); | |
1411 | ||
1412 | mmc_free_host(mmc); | |
1413 | } | |
1414 | ||
1415 | static int __devinit sdhci_probe(struct pci_dev *pdev, | |
1416 | const struct pci_device_id *ent) | |
1417 | { | |
1418 | int ret, i; | |
51f82bc0 | 1419 | u8 slots, rev; |
d129bceb PO |
1420 | struct sdhci_chip *chip; |
1421 | ||
1422 | BUG_ON(pdev == NULL); | |
1423 | BUG_ON(ent == NULL); | |
1424 | ||
51f82bc0 PO |
1425 | pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev); |
1426 | ||
1427 | printk(KERN_INFO DRIVER_NAME | |
1428 | ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n", | |
1429 | pci_name(pdev), (int)pdev->vendor, (int)pdev->device, | |
1430 | (int)rev); | |
d129bceb PO |
1431 | |
1432 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); | |
1433 | if (ret) | |
1434 | return ret; | |
1435 | ||
1436 | slots = PCI_SLOT_INFO_SLOTS(slots) + 1; | |
1437 | DBG("found %d slot(s)\n", slots); | |
1438 | if (slots == 0) | |
1439 | return -ENODEV; | |
1440 | ||
1441 | ret = pci_enable_device(pdev); | |
1442 | if (ret) | |
1443 | return ret; | |
1444 | ||
1445 | chip = kzalloc(sizeof(struct sdhci_chip) + | |
1446 | sizeof(struct sdhci_host*) * slots, GFP_KERNEL); | |
1447 | if (!chip) { | |
1448 | ret = -ENOMEM; | |
1449 | goto err; | |
1450 | } | |
1451 | ||
1452 | chip->pdev = pdev; | |
df673b22 PO |
1453 | chip->quirks = ent->driver_data; |
1454 | ||
1455 | if (debug_quirks) | |
1456 | chip->quirks = debug_quirks; | |
d129bceb PO |
1457 | |
1458 | chip->num_slots = slots; | |
1459 | pci_set_drvdata(pdev, chip); | |
1460 | ||
1461 | for (i = 0;i < slots;i++) { | |
1462 | ret = sdhci_probe_slot(pdev, i); | |
1463 | if (ret) { | |
1464 | for (i--;i >= 0;i--) | |
1465 | sdhci_remove_slot(pdev, i); | |
1466 | goto free; | |
1467 | } | |
1468 | } | |
1469 | ||
1470 | return 0; | |
1471 | ||
1472 | free: | |
1473 | pci_set_drvdata(pdev, NULL); | |
1474 | kfree(chip); | |
1475 | ||
1476 | err: | |
1477 | pci_disable_device(pdev); | |
1478 | return ret; | |
1479 | } | |
1480 | ||
1481 | static void __devexit sdhci_remove(struct pci_dev *pdev) | |
1482 | { | |
1483 | int i; | |
1484 | struct sdhci_chip *chip; | |
1485 | ||
1486 | chip = pci_get_drvdata(pdev); | |
1487 | ||
1488 | if (chip) { | |
1489 | for (i = 0;i < chip->num_slots;i++) | |
1490 | sdhci_remove_slot(pdev, i); | |
1491 | ||
1492 | pci_set_drvdata(pdev, NULL); | |
1493 | ||
1494 | kfree(chip); | |
1495 | } | |
1496 | ||
1497 | pci_disable_device(pdev); | |
1498 | } | |
1499 | ||
1500 | static struct pci_driver sdhci_driver = { | |
1501 | .name = DRIVER_NAME, | |
1502 | .id_table = pci_ids, | |
1503 | .probe = sdhci_probe, | |
1504 | .remove = __devexit_p(sdhci_remove), | |
1505 | .suspend = sdhci_suspend, | |
1506 | .resume = sdhci_resume, | |
1507 | }; | |
1508 | ||
1509 | /*****************************************************************************\ | |
1510 | * * | |
1511 | * Driver init/exit * | |
1512 | * * | |
1513 | \*****************************************************************************/ | |
1514 | ||
1515 | static int __init sdhci_drv_init(void) | |
1516 | { | |
1517 | printk(KERN_INFO DRIVER_NAME | |
52fbf9c9 | 1518 | ": Secure Digital Host Controller Interface driver\n"); |
d129bceb PO |
1519 | printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
1520 | ||
1521 | return pci_register_driver(&sdhci_driver); | |
1522 | } | |
1523 | ||
1524 | static void __exit sdhci_drv_exit(void) | |
1525 | { | |
1526 | DBG("Exiting\n"); | |
1527 | ||
1528 | pci_unregister_driver(&sdhci_driver); | |
1529 | } | |
1530 | ||
1531 | module_init(sdhci_drv_init); | |
1532 | module_exit(sdhci_drv_exit); | |
1533 | ||
67435274 PO |
1534 | module_param(debug_nodma, uint, 0444); |
1535 | module_param(debug_forcedma, uint, 0444); | |
df673b22 | 1536 | module_param(debug_quirks, uint, 0444); |
67435274 | 1537 | |
d129bceb PO |
1538 | MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>"); |
1539 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver"); | |
d129bceb | 1540 | MODULE_LICENSE("GPL"); |
67435274 PO |
1541 | |
1542 | MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)"); | |
1543 | MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)"); | |
df673b22 | 1544 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |