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clk: apn806: Turn the eMMC clock as optional for dts backwards compatible
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb 16#include <linux/delay.h>
5a436cc0 17#include <linux/ktime.h>
d129bceb 18#include <linux/highmem.h>
b8c86fc5 19#include <linux/io.h>
88b47679 20#include <linux/module.h>
d129bceb 21#include <linux/dma-mapping.h>
5a0e3ad6 22#include <linux/slab.h>
11763609 23#include <linux/scatterlist.h>
9bea3c85 24#include <linux/regulator/consumer.h>
66fd8ad5 25#include <linux/pm_runtime.h>
92e0c44b 26#include <linux/of.h>
d129bceb 27
2f730fec
PO		 28#include <linux/leds.h>
29
22113efd 30#include <linux/mmc/mmc.h>
d129bceb 31#include <linux/mmc/host.h>
473b095a 32#include <linux/mmc/card.h>
85cc1c33 33#include <linux/mmc/sdio.h>
bec9d4e5 34#include <linux/mmc/slot-gpio.h>
d129bceb 35
d129bceb
PO		 36#include "sdhci.h"
37
38#define DRIVER_NAME "sdhci"
d129bceb 39
d129bceb 40#define DBG(f, x...) \
f421865d 41 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
d129bceb 42
85ad90e2
AH		 43#define SDHCI_DUMP(f, x...) \
44 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
45
b513ea25
AN		 46#define MAX_TUNING_LOOP 40
47
df673b22 48static unsigned int debug_quirks = 0;
66fd8ad5 49static unsigned int debug_quirks2;
67435274 50
d129bceb
PO		 51static void sdhci_finish_data(struct sdhci_host *);
52
52983382 53static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 54
d2898172 55void sdhci_dumpregs(struct sdhci_host *host)
d129bceb 56{
85ad90e2
AH		 57 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
58
59 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
60 sdhci_readl(host, SDHCI_DMA_ADDRESS),
61 sdhci_readw(host, SDHCI_HOST_VERSION));
62 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
63 sdhci_readw(host, SDHCI_BLOCK_SIZE),
64 sdhci_readw(host, SDHCI_BLOCK_COUNT));
65 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
66 sdhci_readl(host, SDHCI_ARGUMENT),
67 sdhci_readw(host, SDHCI_TRANSFER_MODE));
68 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
69 sdhci_readl(host, SDHCI_PRESENT_STATE),
70 sdhci_readb(host, SDHCI_HOST_CONTROL));
71 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
72 sdhci_readb(host, SDHCI_POWER_CONTROL),
73 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
74 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
75 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
76 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
77 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
78 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
79 sdhci_readl(host, SDHCI_INT_STATUS));
80 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
81 sdhci_readl(host, SDHCI_INT_ENABLE),
82 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
83 SDHCI_DUMP("AC12 err: 0x%08x | Slot int: 0x%08x\n",
84 sdhci_readw(host, SDHCI_ACMD12_ERR),
85 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
86 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
87 sdhci_readl(host, SDHCI_CAPABILITIES),
88 sdhci_readl(host, SDHCI_CAPABILITIES_1));
89 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
90 sdhci_readw(host, SDHCI_COMMAND),
91 sdhci_readl(host, SDHCI_MAX_CURRENT));
92 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
7962302f
AH		 93 sdhci_readl(host, SDHCI_RESPONSE),
94 sdhci_readl(host, SDHCI_RESPONSE + 4));
85ad90e2 95 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
7962302f
AH		 96 sdhci_readl(host, SDHCI_RESPONSE + 8),
97 sdhci_readl(host, SDHCI_RESPONSE + 12));
85ad90e2
AH		 98 SDHCI_DUMP("Host ctl2: 0x%08x\n",
99 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 100
e57a5f61 101 if (host->flags & SDHCI_USE_ADMA) {
85ad90e2
AH		 102 if (host->flags & SDHCI_USE_64_BIT_DMA) {
103 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
104 sdhci_readl(host, SDHCI_ADMA_ERROR),
105 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
106 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
107 } else {
108 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
109 sdhci_readl(host, SDHCI_ADMA_ERROR),
110 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
111 }
e57a5f61 112 }
be3f4ae0 113
85ad90e2 114 SDHCI_DUMP("============================================\n");
d129bceb 115}
d2898172 116EXPORT_SYMBOL_GPL(sdhci_dumpregs);
d129bceb
PO		 117
118/*****************************************************************************\
119 * *
120 * Low level functions *
121 * *
122\*****************************************************************************/
123
56a590dc
AH		 124static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
125{
126 return cmd->data || cmd->flags & MMC_RSP_BUSY;
127}
128
7260cf5e
AV		 129static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
130{
5b4f1f6c 131 u32 present;
7260cf5e 132
c79396c1 133 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
860951c5 134 !mmc_card_is_removable(host->mmc))
66fd8ad5
AH		 135 return;
136
5b4f1f6c
RK		 137 if (enable) {
138 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
139 SDHCI_CARD_PRESENT;
d25928d1 140
5b4f1f6c
RK		 141 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
142 SDHCI_INT_CARD_INSERT;
143 } else {
144 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
145 }
b537f94c
RK		 146
147 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
148 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 149}
150
151static void sdhci_enable_card_detection(struct sdhci_host *host)
152{
153 sdhci_set_card_detection(host, true);
154}
155
156static void sdhci_disable_card_detection(struct sdhci_host *host)
157{
158 sdhci_set_card_detection(host, false);
159}
160
02d0b685
UH		 161static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
162{
163 if (host->bus_on)
164 return;
165 host->bus_on = true;
166 pm_runtime_get_noresume(host->mmc->parent);
167}
168
169static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
170{
171 if (!host->bus_on)
172 return;
173 host->bus_on = false;
174 pm_runtime_put_noidle(host->mmc->parent);
175}
176
03231f9b 177void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 178{
5a436cc0 179 ktime_t timeout;
393c1a34 180
4e4141a5 181 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 182
f0710a55 183 if (mask & SDHCI_RESET_ALL) {
d129bceb 184 host->clock = 0;
f0710a55
AH		 185 /* Reset-all turns off SD Bus Power */
186 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
187 sdhci_runtime_pm_bus_off(host);
188 }
d129bceb 189
e16514d8 190 /* Wait max 100 ms */
5a436cc0 191 timeout = ktime_add_ms(ktime_get(), 100);
e16514d8
PO		 192
193 /* hw clears the bit when it's done */
4e4141a5 194 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
5a436cc0 195 if (ktime_after(ktime_get(), timeout)) {
a3c76eb9 196 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 197 mmc_hostname(host->mmc), (int)mask);
198 sdhci_dumpregs(host);
199 return;
200 }
5a436cc0 201 udelay(10);
d129bceb 202 }
03231f9b
RK		 203}
204EXPORT_SYMBOL_GPL(sdhci_reset);
205
206static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
207{
208 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
d3940f27
AH		 209 struct mmc_host *mmc = host->mmc;
210
211 if (!mmc->ops->get_cd(mmc))
03231f9b
RK		 212 return;
213 }
063a9dbb 214
03231f9b 215 host->ops->reset(host, mask);
393c1a34 216
da91a8f9
RK		 217 if (mask & SDHCI_RESET_ALL) {
218 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
219 if (host->ops->enable_dma)
220 host->ops->enable_dma(host);
221 }
222
223 /* Resetting the controller clears many */
224 host->preset_enabled = false;
3abc1e80 225 }
d129bceb
PO		 226}
227
f5c1ab82 228static void sdhci_set_default_irqs(struct sdhci_host *host)
d129bceb 229{
b537f94c
RK		 230 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
231 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
232 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
233 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
234 SDHCI_INT_RESPONSE;
235
f37b20eb
DA		 236 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
237 host->tuning_mode == SDHCI_TUNING_MODE_3)
238 host->ier |= SDHCI_INT_RETUNE;
239
b537f94c
RK		 240 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
241 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
f5c1ab82
AH		 242}
243
244static void sdhci_init(struct sdhci_host *host, int soft)
245{
246 struct mmc_host *mmc = host->mmc;
247
248 if (soft)
249 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
250 else
251 sdhci_do_reset(host, SDHCI_RESET_ALL);
252
253 sdhci_set_default_irqs(host);
2f4cbb3d 254
f12e39db
AH		 255 host->cqe_on = false;
256
2f4cbb3d
NP		 257 if (soft) {
258 /* force clock reconfiguration */
259 host->clock = 0;
d3940f27 260 mmc->ops->set_ios(mmc, &mmc->ios);
2f4cbb3d 261 }
7260cf5e 262}
d129bceb 263
7260cf5e
AV		 264static void sdhci_reinit(struct sdhci_host *host)
265{
2f4cbb3d 266 sdhci_init(host, 0);
7260cf5e 267 sdhci_enable_card_detection(host);
d129bceb
PO		 268}
269
061d17a6 270static void __sdhci_led_activate(struct sdhci_host *host)
d129bceb
PO		 271{
272 u8 ctrl;
273
4e4141a5 274 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 275 ctrl |= SDHCI_CTRL_LED;
4e4141a5 276 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 277}
278
061d17a6 279static void __sdhci_led_deactivate(struct sdhci_host *host)
d129bceb
PO		 280{
281 u8 ctrl;
282
4e4141a5 283 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 284 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 285 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 286}
287
4f78230f 288#if IS_REACHABLE(CONFIG_LEDS_CLASS)
2f730fec 289static void sdhci_led_control(struct led_classdev *led,
061d17a6 290 enum led_brightness brightness)
2f730fec
PO		 291{
292 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
293 unsigned long flags;
294
295 spin_lock_irqsave(&host->lock, flags);
296
66fd8ad5
AH		 297 if (host->runtime_suspended)
298 goto out;
299
2f730fec 300 if (brightness == LED_OFF)
061d17a6 301 __sdhci_led_deactivate(host);
2f730fec 302 else
061d17a6 303 __sdhci_led_activate(host);
66fd8ad5 304out:
2f730fec
PO		 305 spin_unlock_irqrestore(&host->lock, flags);
306}
061d17a6
AH		 307
308static int sdhci_led_register(struct sdhci_host *host)
309{
310 struct mmc_host *mmc = host->mmc;
311
312 snprintf(host->led_name, sizeof(host->led_name),
313 "%s::", mmc_hostname(mmc));
314
315 host->led.name = host->led_name;
316 host->led.brightness = LED_OFF;
317 host->led.default_trigger = mmc_hostname(mmc);
318 host->led.brightness_set = sdhci_led_control;
319
320 return led_classdev_register(mmc_dev(mmc), &host->led);
321}
322
323static void sdhci_led_unregister(struct sdhci_host *host)
324{
325 led_classdev_unregister(&host->led);
326}
327
328static inline void sdhci_led_activate(struct sdhci_host *host)
329{
330}
331
332static inline void sdhci_led_deactivate(struct sdhci_host *host)
333{
334}
335
336#else
337
338static inline int sdhci_led_register(struct sdhci_host *host)
339{
340 return 0;
341}
342
343static inline void sdhci_led_unregister(struct sdhci_host *host)
344{
345}
346
347static inline void sdhci_led_activate(struct sdhci_host *host)
348{
349 __sdhci_led_activate(host);
350}
351
352static inline void sdhci_led_deactivate(struct sdhci_host *host)
353{
354 __sdhci_led_deactivate(host);
355}
356
2f730fec
PO		 357#endif
358
d129bceb
PO		 359/*****************************************************************************\
360 * *
361 * Core functions *
362 * *
363\*****************************************************************************/
364
a406f5a3 365static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 366{
7659150c
PO		 367 unsigned long flags;
368 size_t blksize, len, chunk;
7244b85b 369 u32 uninitialized_var(scratch);
7659150c 370 u8 *buf;
d129bceb 371
a406f5a3 372 DBG("PIO reading\n");
d129bceb 373
a406f5a3 374 blksize = host->data->blksz;
7659150c 375 chunk = 0;
d129bceb 376
7659150c 377 local_irq_save(flags);
d129bceb 378
a406f5a3 379 while (blksize) {
bf3a35ac 380 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 381
7659150c 382 len = min(host->sg_miter.length, blksize);
d129bceb 383
7659150c
PO		 384 blksize -= len;
385 host->sg_miter.consumed = len;
14d836e7 386
7659150c 387 buf = host->sg_miter.addr;
d129bceb 388
7659150c
PO		 389 while (len) {
390 if (chunk == 0) {
4e4141a5 391 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 392 chunk = 4;
a406f5a3 393 }
7659150c
PO		 394
395 *buf = scratch & 0xFF;
396
397 buf++;
398 scratch >>= 8;
399 chunk--;
400 len--;
d129bceb 401 }
a406f5a3 402 }
7659150c
PO		 403
404 sg_miter_stop(&host->sg_miter);
405
406 local_irq_restore(flags);
a406f5a3 407}
d129bceb 408
a406f5a3
PO		 409static void sdhci_write_block_pio(struct sdhci_host *host)
410{
7659150c
PO		 411 unsigned long flags;
412 size_t blksize, len, chunk;
413 u32 scratch;
414 u8 *buf;
d129bceb 415
a406f5a3
PO		 416 DBG("PIO writing\n");
417
418 blksize = host->data->blksz;
7659150c
PO		 419 chunk = 0;
420 scratch = 0;
d129bceb 421
7659150c 422 local_irq_save(flags);
d129bceb 423
a406f5a3 424 while (blksize) {
bf3a35ac 425 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 426
7659150c
PO		 427 len = min(host->sg_miter.length, blksize);
428
429 blksize -= len;
430 host->sg_miter.consumed = len;
431
432 buf = host->sg_miter.addr;
d129bceb 433
7659150c
PO		 434 while (len) {
435 scratch |= (u32)*buf << (chunk * 8);
436
437 buf++;
438 chunk++;
439 len--;
440
441 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 442 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 443 chunk = 0;
444 scratch = 0;
d129bceb 445 }
d129bceb
PO		 446 }
447 }
7659150c
PO		 448
449 sg_miter_stop(&host->sg_miter);
450
451 local_irq_restore(flags);
a406f5a3
PO		 452}
453
454static void sdhci_transfer_pio(struct sdhci_host *host)
455{
456 u32 mask;
457
7659150c 458 if (host->blocks == 0)
a406f5a3
PO		 459 return;
460
461 if (host->data->flags & MMC_DATA_READ)
462 mask = SDHCI_DATA_AVAILABLE;
463 else
464 mask = SDHCI_SPACE_AVAILABLE;
465
4a3cba32
PO		 466 /*
467 * Some controllers (JMicron JMB38x) mess up the buffer bits
468 * for transfers < 4 bytes. As long as it is just one block,
469 * we can ignore the bits.
470 */
471 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
472 (host->data->blocks == 1))
473 mask = ~0;
474
4e4141a5 475 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 476 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
477 udelay(100);
478
a406f5a3
PO		 479 if (host->data->flags & MMC_DATA_READ)
480 sdhci_read_block_pio(host);
481 else
482 sdhci_write_block_pio(host);
d129bceb 483
7659150c
PO		 484 host->blocks--;
485 if (host->blocks == 0)
a406f5a3 486 break;
a406f5a3 487 }
d129bceb 488
a406f5a3 489 DBG("PIO transfer complete.\n");
d129bceb
PO		 490}
491
48857d9b 492static int sdhci_pre_dma_transfer(struct sdhci_host *host,
c0999b72 493 struct mmc_data *data, int cookie)
48857d9b
RK		 494{
495 int sg_count;
496
94538e51
RK		 497 /*
498 * If the data buffers are already mapped, return the previous
499 * dma_map_sg() result.
500 */
501 if (data->host_cookie == COOKIE_PRE_MAPPED)
48857d9b 502 return data->sg_count;
48857d9b
RK		 503
504 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
feeef096 505 mmc_get_dma_dir(data));
48857d9b
RK		 506
507 if (sg_count == 0)
508 return -ENOSPC;
509
510 data->sg_count = sg_count;
c0999b72 511 data->host_cookie = cookie;
48857d9b
RK		 512
513 return sg_count;
514}
515
2134a922
PO		 516static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
517{
518 local_irq_save(*flags);
482fce99 519 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 520}
521
522static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
523{
482fce99 524 kunmap_atomic(buffer);
2134a922
PO		 525 local_irq_restore(*flags);
526}
527
e57a5f61
AH		 528static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
529 dma_addr_t addr, int len, unsigned cmd)
118cd17d 530{
e57a5f61 531 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 532
e57a5f61 533 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 534 dma_desc->cmd = cpu_to_le16(cmd);
535 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 536 dma_desc->addr_lo = cpu_to_le32((u32)addr);
537
538 if (host->flags & SDHCI_USE_64_BIT_DMA)
539 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 540}
541
b5ffa674
AH		 542static void sdhci_adma_mark_end(void *desc)
543{
e57a5f61 544 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 545
e57a5f61 546 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 547 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 548}
549
60c64762
RK		 550static void sdhci_adma_table_pre(struct sdhci_host *host,
551 struct mmc_data *data, int sg_count)
2134a922 552{
2134a922 553 struct scatterlist *sg;
2134a922 554 unsigned long flags;
acc3ad13
RK		 555 dma_addr_t addr, align_addr;
556 void *desc, *align;
557 char *buffer;
558 int len, offset, i;
2134a922
PO		 559
560 /*
561 * The spec does not specify endianness of descriptor table.
562 * We currently guess that it is LE.
563 */
564
60c64762 565 host->sg_count = sg_count;
2134a922 566
4efaa6fb 567 desc = host->adma_table;
2134a922
PO		 568 align = host->align_buffer;
569
570 align_addr = host->align_addr;
571
572 for_each_sg(data->sg, sg, host->sg_count, i) {
573 addr = sg_dma_address(sg);
574 len = sg_dma_len(sg);
575
576 /*
acc3ad13
RK		 577 * The SDHCI specification states that ADMA addresses must
578 * be 32-bit aligned. If they aren't, then we use a bounce
579 * buffer for the (up to three) bytes that screw up the
2134a922
PO		 580 * alignment.
581 */
04a5ae6f
AH		 582 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
583 SDHCI_ADMA2_MASK;
2134a922
PO		 584 if (offset) {
585 if (data->flags & MMC_DATA_WRITE) {
586 buffer = sdhci_kmap_atomic(sg, &flags);
587 memcpy(align, buffer, offset);
588 sdhci_kunmap_atomic(buffer, &flags);
589 }
590
118cd17d 591 /* tran, valid */
e57a5f61 592 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 593 ADMA2_TRAN_VALID);
2134a922
PO		 594
595 BUG_ON(offset > 65536);
596
04a5ae6f
AH		 597 align += SDHCI_ADMA2_ALIGN;
598 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 599
76fe379a 600 desc += host->desc_sz;
2134a922
PO		 601
602 addr += offset;
603 len -= offset;
604 }
605
2134a922
PO		 606 BUG_ON(len > 65536);
607
347ea32d
AH		 608 if (len) {
609 /* tran, valid */
610 sdhci_adma_write_desc(host, desc, addr, len,
611 ADMA2_TRAN_VALID);
612 desc += host->desc_sz;
613 }
2134a922
PO		 614
615 /*
616 * If this triggers then we have a calculation bug
617 * somewhere. :/
618 */
76fe379a 619 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 620 }
621
70764a90 622 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
acc3ad13 623 /* Mark the last descriptor as the terminating descriptor */
4efaa6fb 624 if (desc != host->adma_table) {
76fe379a 625 desc -= host->desc_sz;
b5ffa674 626 sdhci_adma_mark_end(desc);
70764a90
TA		 627 }
628 } else {
acc3ad13 629 /* Add a terminating entry - nop, end, valid */
e57a5f61 630 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 631 }
2134a922
PO		 632}
633
634static void sdhci_adma_table_post(struct sdhci_host *host,
635 struct mmc_data *data)
636{
2134a922
PO		 637 struct scatterlist *sg;
638 int i, size;
1c3d5f6d 639 void *align;
2134a922
PO		 640 char *buffer;
641 unsigned long flags;
642
47fa9613
RK		 643 if (data->flags & MMC_DATA_READ) {
644 bool has_unaligned = false;
de0b65a7 645
47fa9613
RK		 646 /* Do a quick scan of the SG list for any unaligned mappings */
647 for_each_sg(data->sg, sg, host->sg_count, i)
648 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
649 has_unaligned = true;
650 break;
651 }
2134a922 652
47fa9613
RK		 653 if (has_unaligned) {
654 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
f55c98f7 655 data->sg_len, DMA_FROM_DEVICE);
2134a922 656
47fa9613 657 align = host->align_buffer;
2134a922 658
47fa9613
RK		 659 for_each_sg(data->sg, sg, host->sg_count, i) {
660 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
661 size = SDHCI_ADMA2_ALIGN -
662 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
663
664 buffer = sdhci_kmap_atomic(sg, &flags);
665 memcpy(buffer, align, size);
666 sdhci_kunmap_atomic(buffer, &flags);
2134a922 667
47fa9613
RK		 668 align += SDHCI_ADMA2_ALIGN;
669 }
2134a922
PO		 670 }
671 }
672 }
2134a922
PO		 673}
674
a3c7778f 675static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 676{
1c8cde92 677 u8 count;
a3c7778f 678 struct mmc_data *data = cmd->data;
1c8cde92 679 unsigned target_timeout, current_timeout;
d129bceb 680
ee53ab5d
PO		 681 /*
682 * If the host controller provides us with an incorrect timeout
683 * value, just skip the check and use 0xE. The hardware may take
684 * longer to time out, but that's much better than having a too-short
685 * timeout value.
686 */
11a2f1b7 687 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 688 return 0xE;
e538fbe8 689
a3c7778f 690 /* Unspecified timeout, assume max */
1d4d7744 691 if (!data && !cmd->busy_timeout)
a3c7778f 692 return 0xE;
d129bceb 693
a3c7778f
AW		 694 /* timeout in us */
695 if (!data)
1d4d7744 696 target_timeout = cmd->busy_timeout * 1000;
78a2ca27 697 else {
fafcfda9 698 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
7f05538a
RK		 699 if (host->clock && data->timeout_clks) {
700 unsigned long long val;
701
702 /*
703 * data->timeout_clks is in units of clock cycles.
704 * host->clock is in Hz. target_timeout is in us.
705 * Hence, us = 1000000 * cycles / Hz. Round up.
706 */
02265cd6 707 val = 1000000ULL * data->timeout_clks;
7f05538a
RK		 708 if (do_div(val, host->clock))
709 target_timeout++;
710 target_timeout += val;
711 }
78a2ca27 712 }
81b39802 713
1c8cde92
PO		 714 /*
715 * Figure out needed cycles.
716 * We do this in steps in order to fit inside a 32 bit int.
717 * The first step is the minimum timeout, which will have a
718 * minimum resolution of 6 bits:
719 * (1) 2^13*1000 > 2^22,
720 * (2) host->timeout_clk < 2^16
721 * =>
722 * (1) / (2) > 2^6
723 */
724 count = 0;
725 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
726 while (current_timeout < target_timeout) {
727 count++;
728 current_timeout <<= 1;
729 if (count >= 0xF)
730 break;
731 }
732
733 if (count >= 0xF) {
f421865d
AH		 734 DBG("Too large timeout 0x%x requested for CMD%d!\n",
735 count, cmd->opcode);
1c8cde92
PO		 736 count = 0xE;
737 }
738
ee53ab5d
PO		 739 return count;
740}
741
6aa943ab
AV		 742static void sdhci_set_transfer_irqs(struct sdhci_host *host)
743{
744 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
745 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
746
747 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 748 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 749 else
b537f94c
RK		 750 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
751
752 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
753 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 754}
755
b45e668a 756static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 757{
758 u8 count;
b45e668a
AD		 759
760 if (host->ops->set_timeout) {
761 host->ops->set_timeout(host, cmd);
762 } else {
763 count = sdhci_calc_timeout(host, cmd);
764 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
765 }
766}
767
768static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
769{
2134a922 770 u8 ctrl;
a3c7778f 771 struct mmc_data *data = cmd->data;
ee53ab5d 772
56a590dc 773 if (sdhci_data_line_cmd(cmd))
b45e668a 774 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 775
776 if (!data)
ee53ab5d
PO		 777 return;
778
43dea098
AH		 779 WARN_ON(host->data);
780
ee53ab5d
PO		 781 /* Sanity checks */
782 BUG_ON(data->blksz * data->blocks > 524288);
783 BUG_ON(data->blksz > host->mmc->max_blk_size);
784 BUG_ON(data->blocks > 65535);
785
786 host->data = data;
787 host->data_early = 0;
f6a03cbf 788 host->data->bytes_xfered = 0;
ee53ab5d 789
fce14421 790 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2134a922 791 struct scatterlist *sg;
df953925 792 unsigned int length_mask, offset_mask;
a0eaf0f9 793 int i;
2134a922 794
fce14421
RK		 795 host->flags |= SDHCI_REQ_USE_DMA;
796
797 /*
798 * FIXME: This doesn't account for merging when mapping the
799 * scatterlist.
800 *
801 * The assumption here being that alignment and lengths are
802 * the same after DMA mapping to device address space.
803 */
a0eaf0f9 804 length_mask = 0;
df953925 805 offset_mask = 0;
2134a922 806 if (host->flags & SDHCI_USE_ADMA) {
df953925 807 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
a0eaf0f9 808 length_mask = 3;
df953925
RK		 809 /*
810 * As we use up to 3 byte chunks to work
811 * around alignment problems, we need to
812 * check the offset as well.
813 */
814 offset_mask = 3;
815 }
2134a922
PO		 816 } else {
817 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
a0eaf0f9 818 length_mask = 3;
df953925
RK		 819 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
820 offset_mask = 3;
2134a922
PO		 821 }
822
df953925 823 if (unlikely(length_mask | offset_mask)) {
2134a922 824 for_each_sg(data->sg, sg, data->sg_len, i) {
a0eaf0f9 825 if (sg->length & length_mask) {
2e4456f0 826 DBG("Reverting to PIO because of transfer size (%d)\n",
a0eaf0f9 827 sg->length);
2134a922
PO		 828 host->flags &= ~SDHCI_REQ_USE_DMA;
829 break;
830 }
a0eaf0f9 831 if (sg->offset & offset_mask) {
2e4456f0 832 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 833 host->flags &= ~SDHCI_REQ_USE_DMA;
834 break;
835 }
836 }
837 }
838 }
839
8f1934ce 840 if (host->flags & SDHCI_REQ_USE_DMA) {
c0999b72 841 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
60c64762
RK		 842
843 if (sg_cnt <= 0) {
844 /*
845 * This only happens when someone fed
846 * us an invalid request.
847 */
848 WARN_ON(1);
849 host->flags &= ~SDHCI_REQ_USE_DMA;
850 } else if (host->flags & SDHCI_USE_ADMA) {
851 sdhci_adma_table_pre(host, data, sg_cnt);
852
853 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
854 if (host->flags & SDHCI_USE_64_BIT_DMA)
855 sdhci_writel(host,
856 (u64)host->adma_addr >> 32,
857 SDHCI_ADMA_ADDRESS_HI);
8f1934ce 858 } else {
60c64762
RK		 859 WARN_ON(sg_cnt != 1);
860 sdhci_writel(host, sg_dma_address(data->sg),
861 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 862 }
863 }
864
2134a922
PO		 865 /*
866 * Always adjust the DMA selection as some controllers
867 * (e.g. JMicron) can't do PIO properly when the selection
868 * is ADMA.
869 */
870 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 871 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 872 ctrl &= ~SDHCI_CTRL_DMA_MASK;
873 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 874 (host->flags & SDHCI_USE_ADMA)) {
875 if (host->flags & SDHCI_USE_64_BIT_DMA)
876 ctrl |= SDHCI_CTRL_ADMA64;
877 else
878 ctrl |= SDHCI_CTRL_ADMA32;
879 } else {
2134a922 880 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 881 }
4e4141a5 882 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 883 }
884
8f1934ce 885 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 886 int flags;
887
888 flags = SG_MITER_ATOMIC;
889 if (host->data->flags & MMC_DATA_READ)
890 flags |= SG_MITER_TO_SG;
891 else
892 flags |= SG_MITER_FROM_SG;
893 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 894 host->blocks = data->blocks;
d129bceb 895 }
c7fa9963 896
6aa943ab
AV		 897 sdhci_set_transfer_irqs(host);
898
f6a03cbf
MV		 899 /* Set the DMA boundary value and block size */
900 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
901 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 902 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 903}
904
0293d501
AH		 905static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
906 struct mmc_request *mrq)
907{
20845bef
AH		 908 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
909 !mrq->cap_cmd_during_tfr;
0293d501
AH		 910}
911
c7fa9963 912static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 913 struct mmc_command *cmd)
c7fa9963 914{
d3fc5d71 915 u16 mode = 0;
e89d456f 916 struct mmc_data *data = cmd->data;
c7fa9963 917
2b558c13 918 if (data == NULL) {
9b8ffea6
VW		 919 if (host->quirks2 &
920 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
921 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
922 } else {
2b558c13 923 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 924 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
925 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 926 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 927 }
c7fa9963 928 return;
2b558c13 929 }
c7fa9963 930
e538fbe8
PO		 931 WARN_ON(!host->data);
932
d3fc5d71
VY		 933 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
934 mode = SDHCI_TRNS_BLK_CNT_EN;
935
e89d456f 936 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 937 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 938 /*
939 * If we are sending CMD23, CMD12 never gets sent
940 * on successful completion (so no Auto-CMD12).
941 */
0293d501 942 if (sdhci_auto_cmd12(host, cmd->mrq) &&
85cc1c33 943 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 944 mode |= SDHCI_TRNS_AUTO_CMD12;
a4c73aba 945 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
8edf6371 946 mode |= SDHCI_TRNS_AUTO_CMD23;
a4c73aba 947 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
8edf6371 948 }
c4512f79 949 }
8edf6371 950
c7fa9963
PO		 951 if (data->flags & MMC_DATA_READ)
952 mode |= SDHCI_TRNS_READ;
c9fddbc4 953 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 954 mode |= SDHCI_TRNS_DMA;
955
4e4141a5 956 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 957}
958
0cc563ce
AH		 959static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
960{
961 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
962 ((mrq->cmd && mrq->cmd->error) ||
963 (mrq->sbc && mrq->sbc->error) ||
964 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
965 (mrq->data->stop && mrq->data->stop->error))) ||
966 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
967}
968
4e9f8fe5
AH		 969static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
970{
971 int i;
972
973 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
974 if (host->mrqs_done[i] == mrq) {
975 WARN_ON(1);
976 return;
977 }
978 }
979
980 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
981 if (!host->mrqs_done[i]) {
982 host->mrqs_done[i] = mrq;
983 break;
984 }
985 }
986
987 WARN_ON(i >= SDHCI_MAX_MRQS);
988
989 tasklet_schedule(&host->finish_tasklet);
990}
991
a6d3bdd5
AH		 992static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
993{
5a8a3fef
AH		 994 if (host->cmd && host->cmd->mrq == mrq)
995 host->cmd = NULL;
996
997 if (host->data_cmd && host->data_cmd->mrq == mrq)
998 host->data_cmd = NULL;
999
1000 if (host->data && host->data->mrq == mrq)
1001 host->data = NULL;
1002
ed1563de
AH		 1003 if (sdhci_needs_reset(host, mrq))
1004 host->pending_reset = true;
1005
4e9f8fe5 1006 __sdhci_finish_mrq(host, mrq);
a6d3bdd5
AH		 1007}
1008
d129bceb
PO		 1009static void sdhci_finish_data(struct sdhci_host *host)
1010{
33a57adb
AH		 1011 struct mmc_command *data_cmd = host->data_cmd;
1012 struct mmc_data *data = host->data;
d129bceb 1013
d129bceb 1014 host->data = NULL;
7c89a3d9 1015 host->data_cmd = NULL;
d129bceb 1016
add8913d
RK		 1017 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1018 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1019 sdhci_adma_table_post(host, data);
d129bceb
PO		 1020
1021 /*
c9b74c5b
PO		 1022 * The specification states that the block count register must
1023 * be updated, but it does not specify at what point in the
1024 * data flow. That makes the register entirely useless to read
1025 * back so we have to assume that nothing made it to the card
1026 * in the event of an error.
d129bceb 1027 */
c9b74c5b
PO		 1028 if (data->error)
1029 data->bytes_xfered = 0;
d129bceb 1030 else
c9b74c5b 1031 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 1032
e89d456f
AW		 1033 /*
1034 * Need to send CMD12 if -
1035 * a) open-ended multiblock transfer (no CMD23)
1036 * b) error in multiblock transfer
1037 */
1038 if (data->stop &&
1039 (data->error ||
a4c73aba 1040 !data->mrq->sbc)) {
e89d456f 1041
d129bceb
PO		 1042 /*
1043 * The controller needs a reset of internal state machines
1044 * upon error conditions.
1045 */
17b0429d 1046 if (data->error) {
33a57adb
AH		 1047 if (!host->cmd || host->cmd == data_cmd)
1048 sdhci_do_reset(host, SDHCI_RESET_CMD);
03231f9b 1049 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 1050 }
1051
20845bef
AH		 1052 /*
1053 * 'cap_cmd_during_tfr' request must not use the command line
1054 * after mmc_command_done() has been called. It is upper layer's
1055 * responsibility to send the stop command if required.
1056 */
1057 if (data->mrq->cap_cmd_during_tfr) {
1058 sdhci_finish_mrq(host, data->mrq);
1059 } else {
1060 /* Avoid triggering warning in sdhci_send_command() */
1061 host->cmd = NULL;
1062 sdhci_send_command(host, data->stop);
1063 }
a6d3bdd5
AH		 1064 } else {
1065 sdhci_finish_mrq(host, data->mrq);
1066 }
d129bceb
PO		 1067}
1068
d7422fb4
AH		 1069static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1070 unsigned long timeout)
1071{
1072 if (sdhci_data_line_cmd(mrq->cmd))
1073 mod_timer(&host->data_timer, timeout);
1074 else
1075 mod_timer(&host->timer, timeout);
1076}
1077
1078static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1079{
1080 if (sdhci_data_line_cmd(mrq->cmd))
1081 del_timer(&host->data_timer);
1082 else
1083 del_timer(&host->timer);
1084}
1085
c0e55129 1086void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 1087{
1088 int flags;
fd2208d7 1089 u32 mask;
7cb2c76f 1090 unsigned long timeout;
d129bceb
PO		 1091
1092 WARN_ON(host->cmd);
1093
96776200
RK		 1094 /* Initially, a command has no error */
1095 cmd->error = 0;
1096
fc605f1d
AH		 1097 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1098 cmd->opcode == MMC_STOP_TRANSMISSION)
1099 cmd->flags |= MMC_RSP_BUSY;
1100
d129bceb 1101 /* Wait max 10 ms */
7cb2c76f 1102 timeout = 10;
fd2208d7
PO		 1103
1104 mask = SDHCI_CMD_INHIBIT;
56a590dc 1105 if (sdhci_data_line_cmd(cmd))
fd2208d7
PO		 1106 mask |= SDHCI_DATA_INHIBIT;
1107
1108 /* We shouldn't wait for data inihibit for stop commands, even
1109 though they might use busy signaling */
a4c73aba 1110 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
fd2208d7
PO		 1111 mask &= ~SDHCI_DATA_INHIBIT;
1112
4e4141a5 1113 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1114 if (timeout == 0) {
2e4456f0
MV		 1115 pr_err("%s: Controller never released inhibit bit(s).\n",
1116 mmc_hostname(host->mmc));
d129bceb 1117 sdhci_dumpregs(host);
17b0429d 1118 cmd->error = -EIO;
a6d3bdd5 1119 sdhci_finish_mrq(host, cmd->mrq);
d129bceb
PO		 1120 return;
1121 }
7cb2c76f
PO		 1122 timeout--;
1123 mdelay(1);
1124 }
d129bceb 1125
3e1a6892 1126 timeout = jiffies;
1d4d7744
UH		 1127 if (!cmd->data && cmd->busy_timeout > 9000)
1128 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1129 else
1130 timeout += 10 * HZ;
d7422fb4 1131 sdhci_mod_timer(host, cmd->mrq, timeout);
d129bceb
PO		 1132
1133 host->cmd = cmd;
56a590dc 1134 if (sdhci_data_line_cmd(cmd)) {
7c89a3d9
AH		 1135 WARN_ON(host->data_cmd);
1136 host->data_cmd = cmd;
1137 }
d129bceb 1138
a3c7778f 1139 sdhci_prepare_data(host, cmd);
d129bceb 1140
4e4141a5 1141 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1142
e89d456f 1143 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1144
d129bceb 1145 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1146 pr_err("%s: Unsupported response type!\n",
d129bceb 1147 mmc_hostname(host->mmc));
17b0429d 1148 cmd->error = -EINVAL;
a6d3bdd5 1149 sdhci_finish_mrq(host, cmd->mrq);
d129bceb
PO		 1150 return;
1151 }
1152
1153 if (!(cmd->flags & MMC_RSP_PRESENT))
1154 flags = SDHCI_CMD_RESP_NONE;
1155 else if (cmd->flags & MMC_RSP_136)
1156 flags = SDHCI_CMD_RESP_LONG;
1157 else if (cmd->flags & MMC_RSP_BUSY)
1158 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1159 else
1160 flags = SDHCI_CMD_RESP_SHORT;
1161
1162 if (cmd->flags & MMC_RSP_CRC)
1163 flags |= SDHCI_CMD_CRC;
1164 if (cmd->flags & MMC_RSP_OPCODE)
1165 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1166
1167 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1168 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1169 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1170 flags |= SDHCI_CMD_DATA;
1171
4e4141a5 1172 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1173}
c0e55129 1174EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1175
1176static void sdhci_finish_command(struct sdhci_host *host)
1177{
e0a5640a 1178 struct mmc_command *cmd = host->cmd;
d129bceb
PO		 1179 int i;
1180
e0a5640a
AH		 1181 host->cmd = NULL;
1182
1183 if (cmd->flags & MMC_RSP_PRESENT) {
1184 if (cmd->flags & MMC_RSP_136) {
d129bceb
PO		 1185 /* CRC is stripped so we need to do some shifting. */
1186 for (i = 0;i < 4;i++) {
e0a5640a 1187 cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1188 SDHCI_RESPONSE + (3-i)*4) << 8;
1189 if (i != 3)
e0a5640a 1190 cmd->resp[i] |=
4e4141a5 1191 sdhci_readb(host,
d129bceb
PO		 1192 SDHCI_RESPONSE + (3-i)*4-1);
1193 }
1194 } else {
e0a5640a 1195 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1196 }
1197 }
1198
20845bef
AH		 1199 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1200 mmc_command_done(host->mmc, cmd->mrq);
1201
6bde8681
AH		 1202 /*
1203 * The host can send and interrupt when the busy state has
1204 * ended, allowing us to wait without wasting CPU cycles.
1205 * The busy signal uses DAT0 so this is similar to waiting
1206 * for data to complete.
1207 *
1208 * Note: The 1.0 specification is a bit ambiguous about this
1209 * feature so there might be some problems with older
1210 * controllers.
1211 */
e0a5640a
AH		 1212 if (cmd->flags & MMC_RSP_BUSY) {
1213 if (cmd->data) {
6bde8681
AH		 1214 DBG("Cannot wait for busy signal when also doing a data transfer");
1215 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
ea968023
AH		 1216 cmd == host->data_cmd) {
1217 /* Command complete before busy is ended */
6bde8681
AH		 1218 return;
1219 }
1220 }
1221
e89d456f 1222 /* Finished CMD23, now send actual command. */
a4c73aba
AH		 1223 if (cmd == cmd->mrq->sbc) {
1224 sdhci_send_command(host, cmd->mrq->cmd);
e89d456f 1225 } else {
e538fbe8 1226
e89d456f
AW		 1227 /* Processed actual command. */
1228 if (host->data && host->data_early)
1229 sdhci_finish_data(host);
d129bceb 1230
e0a5640a 1231 if (!cmd->data)
a6d3bdd5 1232 sdhci_finish_mrq(host, cmd->mrq);
e89d456f 1233 }
d129bceb
PO		 1234}
1235
52983382
KL		 1236static u16 sdhci_get_preset_value(struct sdhci_host *host)
1237{
d975f121 1238 u16 preset = 0;
52983382 1239
d975f121
RK		 1240 switch (host->timing) {
1241 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1242 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1243 break;
d975f121 1244 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1245 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1246 break;
d975f121 1247 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1248 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1249 break;
d975f121
RK		 1250 case MMC_TIMING_UHS_SDR104:
1251 case MMC_TIMING_MMC_HS200:
52983382
KL		 1252 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1253 break;
d975f121 1254 case MMC_TIMING_UHS_DDR50:
0dafa60e 1255 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1256 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1257 break;
e9fb05d5
AH		 1258 case MMC_TIMING_MMC_HS400:
1259 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1260 break;
52983382
KL		 1261 default:
1262 pr_warn("%s: Invalid UHS-I mode selected\n",
1263 mmc_hostname(host->mmc));
1264 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1265 break;
1266 }
1267 return preset;
1268}
1269
fb9ee047
LD		 1270u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1271 unsigned int *actual_clock)
d129bceb 1272{
c3ed3877 1273 int div = 0; /* Initialized for compiler warning */
df16219f 1274 int real_div = div, clk_mul = 1;
c3ed3877 1275 u16 clk = 0;
5497159c 1276 bool switch_base_clk = false;
d129bceb 1277
85105c53 1278 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1279 if (host->preset_enabled) {
52983382
KL		 1280 u16 pre_val;
1281
1282 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1283 pre_val = sdhci_get_preset_value(host);
1284 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1285 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1286 if (host->clk_mul &&
1287 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1288 clk = SDHCI_PROG_CLOCK_MODE;
1289 real_div = div + 1;
1290 clk_mul = host->clk_mul;
1291 } else {
1292 real_div = max_t(int, 1, div << 1);
1293 }
1294 goto clock_set;
1295 }
1296
c3ed3877
AN		 1297 /*
1298 * Check if the Host Controller supports Programmable Clock
1299 * Mode.
1300 */
1301 if (host->clk_mul) {
52983382
KL		 1302 for (div = 1; div <= 1024; div++) {
1303 if ((host->max_clk * host->clk_mul / div)
1304 <= clock)
1305 break;
1306 }
5497159c 1307 if ((host->max_clk * host->clk_mul / div) <= clock) {
1308 /*
1309 * Set Programmable Clock Mode in the Clock
1310 * Control register.
1311 */
1312 clk = SDHCI_PROG_CLOCK_MODE;
1313 real_div = div;
1314 clk_mul = host->clk_mul;
1315 div--;
1316 } else {
1317 /*
1318 * Divisor can be too small to reach clock
1319 * speed requirement. Then use the base clock.
1320 */
1321 switch_base_clk = true;
1322 }
1323 }
1324
1325 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1326 /* Version 3.00 divisors must be a multiple of 2. */
1327 if (host->max_clk <= clock)
1328 div = 1;
1329 else {
1330 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1331 div += 2) {
1332 if ((host->max_clk / div) <= clock)
1333 break;
1334 }
85105c53 1335 }
df16219f 1336 real_div = div;
c3ed3877 1337 div >>= 1;
d1955c3a
SG		 1338 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1339 && !div && host->max_clk <= 25000000)
1340 div = 1;
85105c53
ZG		 1341 }
1342 } else {
1343 /* Version 2.00 divisors must be a power of 2. */
0397526d 1344 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1345 if ((host->max_clk / div) <= clock)
1346 break;
1347 }
df16219f 1348 real_div = div;
c3ed3877 1349 div >>= 1;
d129bceb 1350 }
d129bceb 1351
52983382 1352clock_set:
03d6f5ff 1353 if (real_div)
fb9ee047 1354 *actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1355 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1356 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1357 << SDHCI_DIVIDER_HI_SHIFT;
fb9ee047
LD		 1358
1359 return clk;
1360}
1361EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1362
fec79673 1363void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
fb9ee047 1364{
5a436cc0 1365 ktime_t timeout;
fb9ee047 1366
d129bceb 1367 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1368 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1369
27f6cb16 1370 /* Wait max 20 ms */
5a436cc0 1371 timeout = ktime_add_ms(ktime_get(), 20);
4e4141a5 1372 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f 1373 & SDHCI_CLOCK_INT_STABLE)) {
5a436cc0 1374 if (ktime_after(ktime_get(), timeout)) {
2e4456f0
MV		 1375 pr_err("%s: Internal clock never stabilised.\n",
1376 mmc_hostname(host->mmc));
d129bceb
PO		 1377 sdhci_dumpregs(host);
1378 return;
1379 }
5a436cc0 1380 udelay(10);
7cb2c76f 1381 }
d129bceb
PO		 1382
1383 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1384 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1385}
fec79673
RH		 1386EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1387
1388void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1389{
1390 u16 clk;
1391
1392 host->mmc->actual_clock = 0;
1393
1394 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1395
1396 if (clock == 0)
1397 return;
1398
1399 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1400 sdhci_enable_clk(host, clk);
1401}
1771059c 1402EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1403
1dceb041
AH		 1404static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1405 unsigned short vdd)
146ad66e 1406{
3a48edc4 1407 struct mmc_host *mmc = host->mmc;
1dceb041 1408
1dceb041 1409 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1dceb041
AH		 1410
1411 if (mode != MMC_POWER_OFF)
1412 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1413 else
1414 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1415}
1416
606d3131
AH		 1417void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1418 unsigned short vdd)
1dceb041 1419{
8364248a 1420 u8 pwr = 0;
146ad66e 1421
24fbb3ca
RK		 1422 if (mode != MMC_POWER_OFF) {
1423 switch (1 << vdd) {
ae628903
PO		 1424 case MMC_VDD_165_195:
1425 pwr = SDHCI_POWER_180;
1426 break;
1427 case MMC_VDD_29_30:
1428 case MMC_VDD_30_31:
1429 pwr = SDHCI_POWER_300;
1430 break;
1431 case MMC_VDD_32_33:
1432 case MMC_VDD_33_34:
1433 pwr = SDHCI_POWER_330;
1434 break;
1435 default:
9d5de93f
AH		 1436 WARN(1, "%s: Invalid vdd %#x\n",
1437 mmc_hostname(host->mmc), vdd);
1438 break;
ae628903
PO		 1439 }
1440 }
1441
1442 if (host->pwr == pwr)
e921a8b6 1443 return;
146ad66e 1444
ae628903
PO		 1445 host->pwr = pwr;
1446
1447 if (pwr == 0) {
4e4141a5 1448 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1449 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1450 sdhci_runtime_pm_bus_off(host);
e921a8b6
RK		 1451 } else {
1452 /*
1453 * Spec says that we should clear the power reg before setting
1454 * a new value. Some controllers don't seem to like this though.
1455 */
1456 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1457 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1458
e921a8b6
RK		 1459 /*
1460 * At least the Marvell CaFe chip gets confused if we set the
1461 * voltage and set turn on power at the same time, so set the
1462 * voltage first.
1463 */
1464 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1465 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1466
e921a8b6 1467 pwr |= SDHCI_POWER_ON;
146ad66e 1468
e921a8b6 1469 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1470
e921a8b6
RK		 1471 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1472 sdhci_runtime_pm_bus_on(host);
f0710a55 1473
e921a8b6
RK		 1474 /*
1475 * Some controllers need an extra 10ms delay of 10ms before
1476 * they can apply clock after applying power
1477 */
1478 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1479 mdelay(10);
1480 }
1dceb041 1481}
606d3131 1482EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
918f4cbd 1483
606d3131
AH		 1484void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1485 unsigned short vdd)
1dceb041 1486{
606d3131
AH		 1487 if (IS_ERR(host->mmc->supply.vmmc))
1488 sdhci_set_power_noreg(host, mode, vdd);
1dceb041 1489 else
606d3131 1490 sdhci_set_power_reg(host, mode, vdd);
146ad66e 1491}
606d3131 1492EXPORT_SYMBOL_GPL(sdhci_set_power);
146ad66e 1493
d129bceb
PO		 1494/*****************************************************************************\
1495 * *
1496 * MMC callbacks *
1497 * *
1498\*****************************************************************************/
1499
1500static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1501{
1502 struct sdhci_host *host;
505a8680 1503 int present;
d129bceb
PO		 1504 unsigned long flags;
1505
1506 host = mmc_priv(mmc);
1507
04e079cf 1508 /* Firstly check card presence */
8d28b7a7 1509 present = mmc->ops->get_cd(mmc);
2836766a 1510
d129bceb
PO		 1511 spin_lock_irqsave(&host->lock, flags);
1512
061d17a6 1513 sdhci_led_activate(host);
e89d456f
AW		 1514
1515 /*
1516 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1517 * requests if Auto-CMD12 is enabled.
1518 */
0293d501 1519 if (sdhci_auto_cmd12(host, mrq)) {
c4512f79
JH		 1520 if (mrq->stop) {
1521 mrq->data->stop = NULL;
1522 mrq->stop = NULL;
1523 }
1524 }
d129bceb 1525
68d1fb7e 1526 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
a4c73aba 1527 mrq->cmd->error = -ENOMEDIUM;
a6d3bdd5 1528 sdhci_finish_mrq(host, mrq);
cf2b5eea 1529 } else {
8edf6371 1530 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1531 sdhci_send_command(host, mrq->sbc);
1532 else
1533 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1534 }
d129bceb 1535
5f25a66f 1536 mmiowb();
d129bceb
PO		 1537 spin_unlock_irqrestore(&host->lock, flags);
1538}
1539
2317f56c
RK		 1540void sdhci_set_bus_width(struct sdhci_host *host, int width)
1541{
1542 u8 ctrl;
1543
1544 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1545 if (width == MMC_BUS_WIDTH_8) {
1546 ctrl &= ~SDHCI_CTRL_4BITBUS;
1547 if (host->version >= SDHCI_SPEC_300)
1548 ctrl |= SDHCI_CTRL_8BITBUS;
1549 } else {
1550 if (host->version >= SDHCI_SPEC_300)
1551 ctrl &= ~SDHCI_CTRL_8BITBUS;
1552 if (width == MMC_BUS_WIDTH_4)
1553 ctrl |= SDHCI_CTRL_4BITBUS;
1554 else
1555 ctrl &= ~SDHCI_CTRL_4BITBUS;
1556 }
1557 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1558}
1559EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1560
96d7b78c
RK		 1561void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1562{
1563 u16 ctrl_2;
1564
1565 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1566 /* Select Bus Speed Mode for host */
1567 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1568 if ((timing == MMC_TIMING_MMC_HS200) ||
1569 (timing == MMC_TIMING_UHS_SDR104))
1570 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1571 else if (timing == MMC_TIMING_UHS_SDR12)
1572 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1573 else if (timing == MMC_TIMING_UHS_SDR25)
1574 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1575 else if (timing == MMC_TIMING_UHS_SDR50)
1576 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1577 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1578 (timing == MMC_TIMING_MMC_DDR52))
1579 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1580 else if (timing == MMC_TIMING_MMC_HS400)
1581 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1582 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1583}
1584EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1585
ded97e0b 1586static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
d129bceb 1587{
ded97e0b 1588 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 1589 u8 ctrl;
1590
84ec048b
AH		 1591 if (ios->power_mode == MMC_POWER_UNDEFINED)
1592 return;
1593
ceb6143b 1594 if (host->flags & SDHCI_DEVICE_DEAD) {
3a48edc4
TK		 1595 if (!IS_ERR(mmc->supply.vmmc) &&
1596 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1597 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1598 return;
1599 }
1e72859e 1600
d129bceb
PO		 1601 /*
1602 * Reset the chip on each power off.
1603 * Should clear out any weird states.
1604 */
1605 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1606 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1607 sdhci_reinit(host);
d129bceb
PO		 1608 }
1609
52983382 1610 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1611 (ios->power_mode == MMC_POWER_UP) &&
1612 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1613 sdhci_enable_preset_value(host, false);
1614
373073ef 1615 if (!ios->clock || ios->clock != host->clock) {
1771059c 1616 host->ops->set_clock(host, ios->clock);
373073ef 1617 host->clock = ios->clock;
03d6f5ff
AD		 1618
1619 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1620 host->clock) {
1621 host->timeout_clk = host->mmc->actual_clock ?
1622 host->mmc->actual_clock / 1000 :
1623 host->clock / 1000;
1624 host->mmc->max_busy_timeout =
1625 host->ops->get_max_timeout_count ?
1626 host->ops->get_max_timeout_count(host) :
1627 1 << 27;
1628 host->mmc->max_busy_timeout /= host->timeout_clk;
1629 }
373073ef 1630 }
d129bceb 1631
606d3131
AH		 1632 if (host->ops->set_power)
1633 host->ops->set_power(host, ios->power_mode, ios->vdd);
1634 else
1635 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1636
643a81ff
PR		 1637 if (host->ops->platform_send_init_74_clocks)
1638 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1639
2317f56c 1640 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1641
15ec4461 1642 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1643
3ab9c8da 1644 if ((ios->timing == MMC_TIMING_SD_HS ||
273c5414
JC		 1645 ios->timing == MMC_TIMING_MMC_HS ||
1646 ios->timing == MMC_TIMING_MMC_HS400 ||
1647 ios->timing == MMC_TIMING_MMC_HS200 ||
1648 ios->timing == MMC_TIMING_MMC_DDR52 ||
1649 ios->timing == MMC_TIMING_UHS_SDR50 ||
1650 ios->timing == MMC_TIMING_UHS_SDR104 ||
1651 ios->timing == MMC_TIMING_UHS_DDR50 ||
1652 ios->timing == MMC_TIMING_UHS_SDR25)
3ab9c8da 1653 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1654 ctrl |= SDHCI_CTRL_HISPD;
1655 else
1656 ctrl &= ~SDHCI_CTRL_HISPD;
1657
d6d50a15 1658 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1659 u16 clk, ctrl_2;
49c468fc 1660
da91a8f9 1661 if (!host->preset_enabled) {
758535c4 1662 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1663 /*
1664 * We only need to set Driver Strength if the
1665 * preset value enable is not set.
1666 */
da91a8f9 1667 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1668 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1669 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1670 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1671 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1672 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1673 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1674 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1675 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1676 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1677 else {
2e4456f0
MV		 1678 pr_warn("%s: invalid driver type, default to driver type B\n",
1679 mmc_hostname(mmc));
43e943a0
PG		 1680 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1681 }
d6d50a15
AN		 1682
1683 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1684 } else {
1685 /*
1686 * According to SDHC Spec v3.00, if the Preset Value
1687 * Enable in the Host Control 2 register is set, we
1688 * need to reset SD Clock Enable before changing High
1689 * Speed Enable to avoid generating clock gliches.
1690 */
758535c4
AN		 1691
1692 /* Reset SD Clock Enable */
1693 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1694 clk &= ~SDHCI_CLOCK_CARD_EN;
1695 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1696
1697 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1698
1699 /* Re-enable SD Clock */
1771059c 1700 host->ops->set_clock(host, host->clock);
d6d50a15 1701 }
49c468fc 1702
49c468fc
AN		 1703 /* Reset SD Clock Enable */
1704 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1705 clk &= ~SDHCI_CLOCK_CARD_EN;
1706 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1707
96d7b78c 1708 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1709 host->timing = ios->timing;
49c468fc 1710
52983382
KL		 1711 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1712 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1713 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1714 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1715 (ios->timing == MMC_TIMING_UHS_SDR104) ||
0dafa60e
JZ		 1716 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1717 (ios->timing == MMC_TIMING_MMC_DDR52))) {
52983382
KL		 1718 u16 preset;
1719
1720 sdhci_enable_preset_value(host, true);
1721 preset = sdhci_get_preset_value(host);
1722 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1723 >> SDHCI_PRESET_DRV_SHIFT;
1724 }
1725
49c468fc 1726 /* Re-enable SD Clock */
1771059c 1727 host->ops->set_clock(host, host->clock);
758535c4
AN		 1728 } else
1729 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1730
b8352260
LD		 1731 /*
1732 * Some (ENE) controllers go apeshit on some ios operation,
1733 * signalling timeout and CRC errors even on CMD0. Resetting
1734 * it on each ios seems to solve the problem.
1735 */
c63705e1 1736 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1737 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1738
5f25a66f 1739 mmiowb();
d129bceb
PO		 1740}
1741
ded97e0b 1742static int sdhci_get_cd(struct mmc_host *mmc)
66fd8ad5
AH		 1743{
1744 struct sdhci_host *host = mmc_priv(mmc);
ded97e0b 1745 int gpio_cd = mmc_gpio_get_cd(mmc);
94144a46
KL		 1746
1747 if (host->flags & SDHCI_DEVICE_DEAD)
1748 return 0;
1749
88af5655 1750 /* If nonremovable, assume that the card is always present. */
860951c5 1751 if (!mmc_card_is_removable(host->mmc))
94144a46
KL		 1752 return 1;
1753
88af5655
II		 1754 /*
1755 * Try slot gpio detect, if defined it take precedence
1756 * over build in controller functionality
1757 */
287980e4 1758 if (gpio_cd >= 0)
94144a46
KL		 1759 return !!gpio_cd;
1760
88af5655
II		 1761 /* If polling, assume that the card is always present. */
1762 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1763 return 1;
1764
94144a46
KL		 1765 /* Host native card detect */
1766 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1767}
1768
66fd8ad5 1769static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1770{
d129bceb 1771 unsigned long flags;
2dfb579c 1772 int is_readonly;
d129bceb 1773
d129bceb
PO		 1774 spin_lock_irqsave(&host->lock, flags);
1775
1e72859e 1776 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1777 is_readonly = 0;
1778 else if (host->ops->get_ro)
1779 is_readonly = host->ops->get_ro(host);
1e72859e 1780 else
2dfb579c
WS		 1781 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1782 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1783
1784 spin_unlock_irqrestore(&host->lock, flags);
1785
2dfb579c
WS		 1786 /* This quirk needs to be replaced by a callback-function later */
1787 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1788 !is_readonly : is_readonly;
d129bceb
PO		 1789}
1790
82b0e23a
TI		 1791#define SAMPLE_COUNT 5
1792
ded97e0b 1793static int sdhci_get_ro(struct mmc_host *mmc)
82b0e23a 1794{
ded97e0b 1795 struct sdhci_host *host = mmc_priv(mmc);
82b0e23a
TI		 1796 int i, ro_count;
1797
82b0e23a 1798 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1799 return sdhci_check_ro(host);
82b0e23a
TI		 1800
1801 ro_count = 0;
1802 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1803 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1804 if (++ro_count > SAMPLE_COUNT / 2)
1805 return 1;
1806 }
1807 msleep(30);
1808 }
1809 return 0;
1810}
1811
20758b66
AH		 1812static void sdhci_hw_reset(struct mmc_host *mmc)
1813{
1814 struct sdhci_host *host = mmc_priv(mmc);
1815
1816 if (host->ops && host->ops->hw_reset)
1817 host->ops->hw_reset(host);
1818}
1819
66fd8ad5
AH		 1820static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1821{
be138554 1822 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1823 if (enable)
b537f94c 1824 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1825 else
b537f94c
RK		 1826 host->ier &= ~SDHCI_INT_CARD_INT;
1827
1828 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1829 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1830 mmiowb();
1831 }
66fd8ad5
AH		 1832}
1833
1834static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1835{
1836 struct sdhci_host *host = mmc_priv(mmc);
1837 unsigned long flags;
f75979b7 1838
923713b3
HG		 1839 if (enable)
1840 pm_runtime_get_noresume(host->mmc->parent);
1841
66fd8ad5 1842 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1843 if (enable)
1844 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1845 else
1846 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1847
66fd8ad5 1848 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1849 spin_unlock_irqrestore(&host->lock, flags);
923713b3
HG		 1850
1851 if (!enable)
1852 pm_runtime_put_noidle(host->mmc->parent);
f75979b7
PO		 1853}
1854
ded97e0b
DA		 1855static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1856 struct mmc_ios *ios)
f2119df6 1857{
ded97e0b 1858 struct sdhci_host *host = mmc_priv(mmc);
20b92a30 1859 u16 ctrl;
6231f3de 1860 int ret;
f2119df6 1861
20b92a30
KL		 1862 /*
1863 * Signal Voltage Switching is only applicable for Host Controllers
1864 * v3.00 and above.
1865 */
1866 if (host->version < SDHCI_SPEC_300)
1867 return 0;
6231f3de 1868
f2119df6 1869 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1870
21f5998f 1871 switch (ios->signal_voltage) {
20b92a30 1872 case MMC_SIGNAL_VOLTAGE_330:
8cb851a4
AH		 1873 if (!(host->flags & SDHCI_SIGNALING_330))
1874 return -EINVAL;
20b92a30
KL		 1875 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1876 ctrl &= ~SDHCI_CTRL_VDD_180;
1877 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1878
3a48edc4 1879 if (!IS_ERR(mmc->supply.vqmmc)) {
761daa36 1880 ret = mmc_regulator_set_vqmmc(mmc, ios);
20b92a30 1881 if (ret) {
6606110d
JP		 1882 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1883 mmc_hostname(mmc));
20b92a30
KL		 1884 return -EIO;
1885 }
1886 }
1887 /* Wait for 5ms */
1888 usleep_range(5000, 5500);
f2119df6 1889
20b92a30
KL		 1890 /* 3.3V regulator output should be stable within 5 ms */
1891 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1892 if (!(ctrl & SDHCI_CTRL_VDD_180))
1893 return 0;
6231f3de 1894
6606110d
JP		 1895 pr_warn("%s: 3.3V regulator output did not became stable\n",
1896 mmc_hostname(mmc));
20b92a30
KL		 1897
1898 return -EAGAIN;
1899 case MMC_SIGNAL_VOLTAGE_180:
8cb851a4
AH		 1900 if (!(host->flags & SDHCI_SIGNALING_180))
1901 return -EINVAL;
3a48edc4 1902 if (!IS_ERR(mmc->supply.vqmmc)) {
761daa36 1903 ret = mmc_regulator_set_vqmmc(mmc, ios);
20b92a30 1904 if (ret) {
6606110d
JP		 1905 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1906 mmc_hostname(mmc));
20b92a30
KL		 1907 return -EIO;
1908 }
1909 }
6231f3de 1910
6231f3de
PR		 1911 /*
1912 * Enable 1.8V Signal Enable in the Host Control2
1913 * register
1914 */
20b92a30
KL		 1915 ctrl |= SDHCI_CTRL_VDD_180;
1916 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1917
9d967a61
VY		 1918 /* Some controller need to do more when switching */
1919 if (host->ops->voltage_switch)
1920 host->ops->voltage_switch(host);
1921
20b92a30
KL		 1922 /* 1.8V regulator output should be stable within 5 ms */
1923 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1924 if (ctrl & SDHCI_CTRL_VDD_180)
1925 return 0;
f2119df6 1926
6606110d
JP		 1927 pr_warn("%s: 1.8V regulator output did not became stable\n",
1928 mmc_hostname(mmc));
f2119df6 1929
20b92a30
KL		 1930 return -EAGAIN;
1931 case MMC_SIGNAL_VOLTAGE_120:
8cb851a4
AH		 1932 if (!(host->flags & SDHCI_SIGNALING_120))
1933 return -EINVAL;
3a48edc4 1934 if (!IS_ERR(mmc->supply.vqmmc)) {
761daa36 1935 ret = mmc_regulator_set_vqmmc(mmc, ios);
20b92a30 1936 if (ret) {
6606110d
JP		 1937 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1938 mmc_hostname(mmc));
20b92a30 1939 return -EIO;
f2119df6
AN		 1940 }
1941 }
6231f3de 1942 return 0;
20b92a30 1943 default:
f2119df6
AN		 1944 /* No signal voltage switch required */
1945 return 0;
20b92a30 1946 }
f2119df6
AN		 1947}
1948
20b92a30
KL		 1949static int sdhci_card_busy(struct mmc_host *mmc)
1950{
1951 struct sdhci_host *host = mmc_priv(mmc);
1952 u32 present_state;
1953
e613cc47 1954 /* Check whether DAT[0] is 0 */
20b92a30 1955 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
20b92a30 1956
e613cc47 1957 return !(present_state & SDHCI_DATA_0_LVL_MASK);
20b92a30
KL		 1958}
1959
b5540ce1
AH		 1960static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1961{
1962 struct sdhci_host *host = mmc_priv(mmc);
1963 unsigned long flags;
1964
1965 spin_lock_irqsave(&host->lock, flags);
1966 host->flags |= SDHCI_HS400_TUNING;
1967 spin_unlock_irqrestore(&host->lock, flags);
1968
1969 return 0;
1970}
1971
da4bc4f2
AH		 1972static void sdhci_start_tuning(struct sdhci_host *host)
1973{
1974 u16 ctrl;
1975
1976 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1977 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1978 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1979 ctrl |= SDHCI_CTRL_TUNED_CLK;
1980 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1981
1982 /*
1983 * As per the Host Controller spec v3.00, tuning command
1984 * generates Buffer Read Ready interrupt, so enable that.
1985 *
1986 * Note: The spec clearly says that when tuning sequence
1987 * is being performed, the controller does not generate
1988 * interrupts other than Buffer Read Ready interrupt. But
1989 * to make sure we don't hit a controller bug, we _only_
1990 * enable Buffer Read Ready interrupt here.
1991 */
1992 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1993 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1994}
1995
1996static void sdhci_end_tuning(struct sdhci_host *host)
1997{
1998 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1999 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2000}
2001
2002static void sdhci_reset_tuning(struct sdhci_host *host)
2003{
2004 u16 ctrl;
2005
2006 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2007 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2008 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2009 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2010}
2011
2a85ef25 2012static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
da4bc4f2
AH		 2013{
2014 sdhci_reset_tuning(host);
2015
2016 sdhci_do_reset(host, SDHCI_RESET_CMD);
2017 sdhci_do_reset(host, SDHCI_RESET_DATA);
2018
2019 sdhci_end_tuning(host);
2020
da4bc4f2 2021 mmc_abort_tuning(host->mmc, opcode);
da4bc4f2
AH		 2022}
2023
2024/*
2025 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2026 * tuning command does not have a data payload (or rather the hardware does it
2027 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2028 * interrupt setup is different to other commands and there is no timeout
2029 * interrupt so special handling is needed.
2030 */
2a85ef25 2031static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
da4bc4f2
AH		 2032{
2033 struct mmc_host *mmc = host->mmc;
c7836d15
MY		 2034 struct mmc_command cmd = {};
2035 struct mmc_request mrq = {};
2a85ef25
AH		 2036 unsigned long flags;
2037
2038 spin_lock_irqsave(&host->lock, flags);
da4bc4f2
AH		 2039
2040 cmd.opcode = opcode;
2041 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2042 cmd.mrq = &mrq;
2043
2044 mrq.cmd = &cmd;
2045 /*
2046 * In response to CMD19, the card sends 64 bytes of tuning
2047 * block to the Host Controller. So we set the block size
2048 * to 64 here.
2049 */
85336109
AH		 2050 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2051 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2052 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), SDHCI_BLOCK_SIZE);
2053 else
2054 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
da4bc4f2
AH		 2055
2056 /*
2057 * The tuning block is sent by the card to the host controller.
2058 * So we set the TRNS_READ bit in the Transfer Mode register.
2059 * This also takes care of setting DMA Enable and Multi Block
2060 * Select in the same register to 0.
2061 */
2062 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2063
2064 sdhci_send_command(host, &cmd);
2065
2066 host->cmd = NULL;
2067
2068 sdhci_del_timer(host, &mrq);
2069
2070 host->tuning_done = 0;
2071
2a85ef25 2072 mmiowb();
da4bc4f2
AH		 2073 spin_unlock_irqrestore(&host->lock, flags);
2074
2075 /* Wait for Buffer Read Ready interrupt */
2076 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2077 msecs_to_jiffies(50));
2078
da4bc4f2
AH		 2079}
2080
2a85ef25 2081static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
6b11e70b
AH		 2082{
2083 int i;
2084
2085 /*
2086 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2087 * of loops reaches 40 times.
2088 */
2089 for (i = 0; i < MAX_TUNING_LOOP; i++) {
2090 u16 ctrl;
2091
2a85ef25 2092 sdhci_send_tuning(host, opcode);
6b11e70b
AH		 2093
2094 if (!host->tuning_done) {
2095 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
2096 mmc_hostname(host->mmc));
2a85ef25 2097 sdhci_abort_tuning(host, opcode);
6b11e70b
AH		 2098 return;
2099 }
2100
2101 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2102 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2103 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2104 return; /* Success! */
2105 break;
2106 }
2107
2108 /* eMMC spec does not require a delay between tuning cycles */
2109 if (opcode == MMC_SEND_TUNING_BLOCK)
2110 mdelay(1);
2111 }
2112
2113 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2114 mmc_hostname(host->mmc));
2115 sdhci_reset_tuning(host);
2116}
2117
85a882c2 2118int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 2119{
4b6f37d3 2120 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 2121 int err = 0;
38e40bf5 2122 unsigned int tuning_count = 0;
b5540ce1 2123 bool hs400_tuning;
b513ea25 2124
b5540ce1 2125 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
b5540ce1 2126
38e40bf5
AH		 2127 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2128 tuning_count = host->tuning_count;
2129
b513ea25 2130 /*
9faac7b9
WY		 2131 * The Host Controller needs tuning in case of SDR104 and DDR50
2132 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2133 * the Capabilities register.
069c9f14
G		 2134 * If the Host Controller supports the HS200 mode then the
2135 * tuning function has to be executed.
b513ea25 2136 */
4b6f37d3 2137 switch (host->timing) {
b5540ce1 2138 /* HS400 tuning is done in HS200 mode */
e9fb05d5 2139 case MMC_TIMING_MMC_HS400:
b5540ce1 2140 err = -EINVAL;
2a85ef25 2141 goto out;
b5540ce1 2142
4b6f37d3 2143 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 2144 /*
2145 * Periodic re-tuning for HS400 is not expected to be needed, so
2146 * disable it here.
2147 */
2148 if (hs400_tuning)
2149 tuning_count = 0;
2150 break;
2151
4b6f37d3 2152 case MMC_TIMING_UHS_SDR104:
9faac7b9 2153 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 2154 break;
2155
2156 case MMC_TIMING_UHS_SDR50:
4228b213 2157 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
4b6f37d3
RK		 2158 break;
2159 /* FALLTHROUGH */
2160
2161 default:
2a85ef25 2162 goto out;
b513ea25
AN		 2163 }
2164
45251812 2165 if (host->ops->platform_execute_tuning) {
8a8fa879 2166 err = host->ops->platform_execute_tuning(host, opcode);
2a85ef25 2167 goto out;
45251812
DA		 2168 }
2169
6b11e70b 2170 host->mmc->retune_period = tuning_count;
b513ea25 2171
6b11e70b 2172 sdhci_start_tuning(host);
da4bc4f2 2173
2a85ef25 2174 __sdhci_execute_tuning(host, opcode);
cf2b5eea 2175
da4bc4f2 2176 sdhci_end_tuning(host);
2a85ef25 2177out:
8a8fa879 2178 host->flags &= ~SDHCI_HS400_TUNING;
6b11e70b 2179
b513ea25
AN		 2180 return err;
2181}
85a882c2 2182EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
b513ea25 2183
52983382 2184static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2185{
4d55c5a1
AN		 2186 /* Host Controller v3.00 defines preset value registers */
2187 if (host->version < SDHCI_SPEC_300)
2188 return;
2189
4d55c5a1
AN		 2190 /*
2191 * We only enable or disable Preset Value if they are not already
2192 * enabled or disabled respectively. Otherwise, we bail out.
2193 */
da91a8f9
RK		 2194 if (host->preset_enabled != enable) {
2195 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2196
2197 if (enable)
2198 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2199 else
2200 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2201
4d55c5a1 2202 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2203
2204 if (enable)
2205 host->flags |= SDHCI_PV_ENABLED;
2206 else
2207 host->flags &= ~SDHCI_PV_ENABLED;
2208
2209 host->preset_enabled = enable;
4d55c5a1 2210 }
66fd8ad5
AH		 2211}
2212
348487cb
HC		 2213static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2214 int err)
2215{
2216 struct sdhci_host *host = mmc_priv(mmc);
2217 struct mmc_data *data = mrq->data;
2218
f48f039c 2219 if (data->host_cookie != COOKIE_UNMAPPED)
771a3dc2 2220 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
feeef096 2221 mmc_get_dma_dir(data));
771a3dc2
RK		 2222
2223 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2224}
2225
d3c6aac3 2226static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
348487cb
HC		 2227{
2228 struct sdhci_host *host = mmc_priv(mmc);
2229
d31911b9 2230 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2231
2232 if (host->flags & SDHCI_REQ_USE_DMA)
94538e51 2233 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
348487cb
HC		 2234}
2235
5d0d11c5
AH		 2236static inline bool sdhci_has_requests(struct sdhci_host *host)
2237{
2238 return host->cmd || host->data_cmd;
2239}
2240
2241static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2242{
2243 if (host->data_cmd) {
2244 host->data_cmd->error = err;
2245 sdhci_finish_mrq(host, host->data_cmd->mrq);
2246 }
2247
2248 if (host->cmd) {
2249 host->cmd->error = err;
2250 sdhci_finish_mrq(host, host->cmd->mrq);
2251 }
2252}
2253
71e69211 2254static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2255{
71e69211 2256 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2257 unsigned long flags;
2836766a 2258 int present;
d129bceb 2259
722e1280
CD		 2260 /* First check if client has provided their own card event */
2261 if (host->ops->card_event)
2262 host->ops->card_event(host);
2263
d3940f27 2264 present = mmc->ops->get_cd(mmc);
2836766a 2265
d129bceb
PO		 2266 spin_lock_irqsave(&host->lock, flags);
2267
5d0d11c5
AH		 2268 /* Check sdhci_has_requests() first in case we are runtime suspended */
2269 if (sdhci_has_requests(host) && !present) {
a3c76eb9 2270 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2271 mmc_hostname(host->mmc));
a3c76eb9 2272 pr_err("%s: Resetting controller.\n",
66fd8ad5 2273 mmc_hostname(host->mmc));
d129bceb 2274
03231f9b
RK		 2275 sdhci_do_reset(host, SDHCI_RESET_CMD);
2276 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2277
5d0d11c5 2278 sdhci_error_out_mrqs(host, -ENOMEDIUM);
d129bceb
PO		 2279 }
2280
2281 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2282}
2283
2284static const struct mmc_host_ops sdhci_ops = {
2285 .request = sdhci_request,
348487cb
HC		 2286 .post_req = sdhci_post_req,
2287 .pre_req = sdhci_pre_req,
71e69211 2288 .set_ios = sdhci_set_ios,
94144a46 2289 .get_cd = sdhci_get_cd,
71e69211
GL		 2290 .get_ro = sdhci_get_ro,
2291 .hw_reset = sdhci_hw_reset,
2292 .enable_sdio_irq = sdhci_enable_sdio_irq,
2293 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2294 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2295 .execute_tuning = sdhci_execute_tuning,
71e69211 2296 .card_event = sdhci_card_event,
20b92a30 2297 .card_busy = sdhci_card_busy,
71e69211
GL		 2298};
2299
2300/*****************************************************************************\
2301 * *
2302 * Tasklets *
2303 * *
2304\*****************************************************************************/
2305
4e9f8fe5 2306static bool sdhci_request_done(struct sdhci_host *host)
d129bceb 2307{
d129bceb
PO		 2308 unsigned long flags;
2309 struct mmc_request *mrq;
4e9f8fe5 2310 int i;
d129bceb 2311
66fd8ad5
AH		 2312 spin_lock_irqsave(&host->lock, flags);
2313
4e9f8fe5
AH		 2314 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2315 mrq = host->mrqs_done[i];
6ebebeab 2316 if (mrq)
4e9f8fe5 2317 break;
66fd8ad5 2318 }
d129bceb 2319
4e9f8fe5
AH		 2320 if (!mrq) {
2321 spin_unlock_irqrestore(&host->lock, flags);
2322 return true;
2323 }
d129bceb 2324
d7422fb4
AH		 2325 sdhci_del_timer(host, mrq);
2326
054cedff
RK		 2327 /*
2328 * Always unmap the data buffers if they were mapped by
2329 * sdhci_prepare_data() whenever we finish with a request.
2330 * This avoids leaking DMA mappings on error.
2331 */
2332 if (host->flags & SDHCI_REQ_USE_DMA) {
2333 struct mmc_data *data = mrq->data;
2334
2335 if (data && data->host_cookie == COOKIE_MAPPED) {
2336 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
feeef096 2337 mmc_get_dma_dir(data));
054cedff
RK		 2338 data->host_cookie = COOKIE_UNMAPPED;
2339 }
2340 }
2341
d129bceb
PO		 2342 /*
2343 * The controller needs a reset of internal state machines
2344 * upon error conditions.
2345 */
0cc563ce 2346 if (sdhci_needs_reset(host, mrq)) {
6ebebeab
AH		 2347 /*
2348 * Do not finish until command and data lines are available for
2349 * reset. Note there can only be one other mrq, so it cannot
2350 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2351 * would both be null.
2352 */
2353 if (host->cmd || host->data_cmd) {
2354 spin_unlock_irqrestore(&host->lock, flags);
2355 return true;
2356 }
2357
645289dc 2358 /* Some controllers need this kick or reset won't work here */
8213af3b 2359 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2360 /* This is to force an update */
1771059c 2361 host->ops->set_clock(host, host->clock);
645289dc
PO		 2362
2363 /* Spec says we should do both at the same time, but Ricoh
2364 controllers do not like that. */
6ebebeab
AH		 2365 sdhci_do_reset(host, SDHCI_RESET_CMD);
2366 sdhci_do_reset(host, SDHCI_RESET_DATA);
ed1563de
AH		 2367
2368 host->pending_reset = false;
d129bceb
PO		 2369 }
2370
4e9f8fe5
AH		 2371 if (!sdhci_has_requests(host))
2372 sdhci_led_deactivate(host);
d129bceb 2373
6ebebeab
AH		 2374 host->mrqs_done[i] = NULL;
2375
5f25a66f 2376 mmiowb();
d129bceb
PO		 2377 spin_unlock_irqrestore(&host->lock, flags);
2378
2379 mmc_request_done(host->mmc, mrq);
4e9f8fe5
AH		 2380
2381 return false;
2382}
2383
2384static void sdhci_tasklet_finish(unsigned long param)
2385{
2386 struct sdhci_host *host = (struct sdhci_host *)param;
2387
2388 while (!sdhci_request_done(host))
2389 ;
d129bceb
PO		 2390}
2391
2392static void sdhci_timeout_timer(unsigned long data)
2393{
2394 struct sdhci_host *host;
2395 unsigned long flags;
2396
2397 host = (struct sdhci_host*)data;
2398
2399 spin_lock_irqsave(&host->lock, flags);
2400
d7422fb4
AH		 2401 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2402 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2403 mmc_hostname(host->mmc));
2404 sdhci_dumpregs(host);
2405
2406 host->cmd->error = -ETIMEDOUT;
2407 sdhci_finish_mrq(host, host->cmd->mrq);
2408 }
2409
2410 mmiowb();
2411 spin_unlock_irqrestore(&host->lock, flags);
2412}
2413
2414static void sdhci_timeout_data_timer(unsigned long data)
2415{
2416 struct sdhci_host *host;
2417 unsigned long flags;
2418
2419 host = (struct sdhci_host *)data;
2420
2421 spin_lock_irqsave(&host->lock, flags);
2422
2423 if (host->data || host->data_cmd ||
2424 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2e4456f0
MV		 2425 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2426 mmc_hostname(host->mmc));
d129bceb
PO		 2427 sdhci_dumpregs(host);
2428
2429 if (host->data) {
17b0429d 2430 host->data->error = -ETIMEDOUT;
d129bceb 2431 sdhci_finish_data(host);
d7422fb4
AH		 2432 } else if (host->data_cmd) {
2433 host->data_cmd->error = -ETIMEDOUT;
2434 sdhci_finish_mrq(host, host->data_cmd->mrq);
d129bceb 2435 } else {
d7422fb4
AH		 2436 host->cmd->error = -ETIMEDOUT;
2437 sdhci_finish_mrq(host, host->cmd->mrq);
d129bceb
PO		 2438 }
2439 }
2440
5f25a66f 2441 mmiowb();
d129bceb
PO		 2442 spin_unlock_irqrestore(&host->lock, flags);
2443}
2444
2445/*****************************************************************************\
2446 * *
2447 * Interrupt handling *
2448 * *
2449\*****************************************************************************/
2450
fc605f1d 2451static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
d129bceb 2452{
d129bceb 2453 if (!host->cmd) {
ed1563de
AH		 2454 /*
2455 * SDHCI recovers from errors by resetting the cmd and data
2456 * circuits. Until that is done, there very well might be more
2457 * interrupts, so ignore them in that case.
2458 */
2459 if (host->pending_reset)
2460 return;
2e4456f0
MV		 2461 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2462 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2463 sdhci_dumpregs(host);
2464 return;
2465 }
2466
ec014cba
RK		 2467 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2468 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2469 if (intmask & SDHCI_INT_TIMEOUT)
2470 host->cmd->error = -ETIMEDOUT;
2471 else
2472 host->cmd->error = -EILSEQ;
43b58b36 2473
71fcbda0
RK		 2474 /*
2475 * If this command initiates a data phase and a response
2476 * CRC error is signalled, the card can start transferring
2477 * data - the card may have received the command without
2478 * error. We must not terminate the mmc_request early.
2479 *
2480 * If the card did not receive the command or returned an
2481 * error which prevented it sending data, the data phase
2482 * will time out.
2483 */
2484 if (host->cmd->data &&
2485 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2486 SDHCI_INT_CRC) {
2487 host->cmd = NULL;
2488 return;
2489 }
2490
a6d3bdd5 2491 sdhci_finish_mrq(host, host->cmd->mrq);
e809517f
PO		 2492 return;
2493 }
2494
e809517f 2495 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2496 sdhci_finish_command(host);
d129bceb
PO		 2497}
2498
0957c333 2499#ifdef CONFIG_MMC_DEBUG
08621b18 2500static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0 2501{
1c3d5f6d 2502 void *desc = host->adma_table;
6882a8c0
BD		 2503
2504 sdhci_dumpregs(host);
2505
2506 while (true) {
e57a5f61
AH		 2507 struct sdhci_adma2_64_desc *dma_desc = desc;
2508
2509 if (host->flags & SDHCI_USE_64_BIT_DMA)
f421865d
AH		 2510 DBG("%p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2511 desc, le32_to_cpu(dma_desc->addr_hi),
e57a5f61
AH		 2512 le32_to_cpu(dma_desc->addr_lo),
2513 le16_to_cpu(dma_desc->len),
2514 le16_to_cpu(dma_desc->cmd));
2515 else
f421865d
AH		 2516 DBG("%p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2517 desc, le32_to_cpu(dma_desc->addr_lo),
e57a5f61
AH		 2518 le16_to_cpu(dma_desc->len),
2519 le16_to_cpu(dma_desc->cmd));
6882a8c0 2520
76fe379a 2521 desc += host->desc_sz;
6882a8c0 2522
0545230f 2523 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2524 break;
2525 }
2526}
2527#else
08621b18 2528static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2529#endif
2530
d129bceb
PO		 2531static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2532{
069c9f14 2533 u32 command;
d129bceb 2534
b513ea25
AN		 2535 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2536 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2537 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2538 if (command == MMC_SEND_TUNING_BLOCK ||
2539 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2540 host->tuning_done = 1;
2541 wake_up(&host->buf_ready_int);
2542 return;
2543 }
2544 }
2545
d129bceb 2546 if (!host->data) {
7c89a3d9
AH		 2547 struct mmc_command *data_cmd = host->data_cmd;
2548
d129bceb 2549 /*
e809517f
PO		 2550 * The "data complete" interrupt is also used to
2551 * indicate that a busy state has ended. See comment
2552 * above in sdhci_cmd_irq().
d129bceb 2553 */
7c89a3d9 2554 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8 2555 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
69b962a6 2556 host->data_cmd = NULL;
7c89a3d9 2557 data_cmd->error = -ETIMEDOUT;
a6d3bdd5 2558 sdhci_finish_mrq(host, data_cmd->mrq);
c5abd5e8
MC		 2559 return;
2560 }
e809517f 2561 if (intmask & SDHCI_INT_DATA_END) {
69b962a6 2562 host->data_cmd = NULL;
e99783a4
CM		 2563 /*
2564 * Some cards handle busy-end interrupt
2565 * before the command completed, so make
2566 * sure we do things in the proper order.
2567 */
ea968023
AH		 2568 if (host->cmd == data_cmd)
2569 return;
2570
a6d3bdd5 2571 sdhci_finish_mrq(host, data_cmd->mrq);
e809517f
PO		 2572 return;
2573 }
2574 }
d129bceb 2575
ed1563de
AH		 2576 /*
2577 * SDHCI recovers from errors by resetting the cmd and data
2578 * circuits. Until that is done, there very well might be more
2579 * interrupts, so ignore them in that case.
2580 */
2581 if (host->pending_reset)
2582 return;
2583
2e4456f0
MV		 2584 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2585 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2586 sdhci_dumpregs(host);
2587
2588 return;
2589 }
2590
2591 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2592 host->data->error = -ETIMEDOUT;
22113efd
AL		 2593 else if (intmask & SDHCI_INT_DATA_END_BIT)
2594 host->data->error = -EILSEQ;
2595 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2596 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2597 != MMC_BUS_TEST_R)
17b0429d 2598 host->data->error = -EILSEQ;
6882a8c0 2599 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2600 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2601 sdhci_adma_show_error(host);
2134a922 2602 host->data->error = -EIO;
a4071fbb
HZ		 2603 if (host->ops->adma_workaround)
2604 host->ops->adma_workaround(host, intmask);
6882a8c0 2605 }
d129bceb 2606
17b0429d 2607 if (host->data->error)
d129bceb
PO		 2608 sdhci_finish_data(host);
2609 else {
a406f5a3 2610 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2611 sdhci_transfer_pio(host);
2612
6ba736a1
PO		 2613 /*
2614 * We currently don't do anything fancy with DMA
2615 * boundaries, but as we can't disable the feature
2616 * we need to at least restart the transfer.
f6a03cbf
MV		 2617 *
2618 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2619 * should return a valid address to continue from, but as
2620 * some controllers are faulty, don't trust them.
6ba736a1 2621 */
f6a03cbf
MV		 2622 if (intmask & SDHCI_INT_DMA_END) {
2623 u32 dmastart, dmanow;
2624 dmastart = sg_dma_address(host->data->sg);
2625 dmanow = dmastart + host->data->bytes_xfered;
2626 /*
2627 * Force update to the next DMA block boundary.
2628 */
2629 dmanow = (dmanow &
2630 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2631 SDHCI_DEFAULT_BOUNDARY_SIZE;
2632 host->data->bytes_xfered = dmanow - dmastart;
f421865d
AH		 2633 DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n",
2634 dmastart, host->data->bytes_xfered, dmanow);
f6a03cbf
MV		 2635 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2636 }
6ba736a1 2637
e538fbe8 2638 if (intmask & SDHCI_INT_DATA_END) {
7c89a3d9 2639 if (host->cmd == host->data_cmd) {
e538fbe8
PO		 2640 /*
2641 * Data managed to finish before the
2642 * command completed. Make sure we do
2643 * things in the proper order.
2644 */
2645 host->data_early = 1;
2646 } else {
2647 sdhci_finish_data(host);
2648 }
2649 }
d129bceb
PO		 2650 }
2651}
2652
7d12e780 2653static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2654{
781e989c 2655 irqreturn_t result = IRQ_NONE;
66fd8ad5 2656 struct sdhci_host *host = dev_id;
41005003 2657 u32 intmask, mask, unexpected = 0;
781e989c 2658 int max_loops = 16;
d129bceb
PO		 2659
2660 spin_lock(&host->lock);
2661
be138554 2662 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2663 spin_unlock(&host->lock);
655bca76 2664 return IRQ_NONE;
66fd8ad5
AH		 2665 }
2666
4e4141a5 2667 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2668 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2669 result = IRQ_NONE;
2670 goto out;
2671 }
2672
41005003 2673 do {
f12e39db
AH		 2674 DBG("IRQ status 0x%08x\n", intmask);
2675
2676 if (host->ops->irq) {
2677 intmask = host->ops->irq(host, intmask);
2678 if (!intmask)
2679 goto cont;
2680 }
2681
41005003
RK		 2682 /* Clear selected interrupts. */
2683 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2684 SDHCI_INT_BUS_POWER);
2685 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2686
41005003
RK		 2687 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2688 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2689 SDHCI_CARD_PRESENT;
d129bceb 2690
41005003
RK		 2691 /*
2692 * There is a observation on i.mx esdhc. INSERT
2693 * bit will be immediately set again when it gets
2694 * cleared, if a card is inserted. We have to mask
2695 * the irq to prevent interrupt storm which will
2696 * freeze the system. And the REMOVE gets the
2697 * same situation.
2698 *
2699 * More testing are needed here to ensure it works
2700 * for other platforms though.
2701 */
b537f94c
RK		 2702 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2703 SDHCI_INT_CARD_REMOVE);
2704 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2705 SDHCI_INT_CARD_INSERT;
2706 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2707 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2708
2709 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2710 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2711
2712 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2713 SDHCI_INT_CARD_REMOVE);
2714 result = IRQ_WAKE_THREAD;
41005003 2715 }
d129bceb 2716
41005003 2717 if (intmask & SDHCI_INT_CMD_MASK)
fc605f1d 2718 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
964f9ce2 2719
41005003
RK		 2720 if (intmask & SDHCI_INT_DATA_MASK)
2721 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2722
41005003
RK		 2723 if (intmask & SDHCI_INT_BUS_POWER)
2724 pr_err("%s: Card is consuming too much power!\n",
2725 mmc_hostname(host->mmc));
3192a28f 2726
f37b20eb
DA		 2727 if (intmask & SDHCI_INT_RETUNE)
2728 mmc_retune_needed(host->mmc);
2729
161e6d44
GKB		 2730 if ((intmask & SDHCI_INT_CARD_INT) &&
2731 (host->ier & SDHCI_INT_CARD_INT)) {
781e989c
RK		 2732 sdhci_enable_sdio_irq_nolock(host, false);
2733 host->thread_isr |= SDHCI_INT_CARD_INT;
2734 result = IRQ_WAKE_THREAD;
2735 }
f75979b7 2736
41005003
RK		 2737 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2738 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2739 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
f37b20eb 2740 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
f75979b7 2741
41005003
RK		 2742 if (intmask) {
2743 unexpected |= intmask;
2744 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2745 }
f12e39db 2746cont:
781e989c
RK		 2747 if (result == IRQ_NONE)
2748 result = IRQ_HANDLED;
d129bceb 2749
41005003 2750 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2751 } while (intmask && --max_loops);
d129bceb
PO		 2752out:
2753 spin_unlock(&host->lock);
2754
6379b237
AS		 2755 if (unexpected) {
2756 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2757 mmc_hostname(host->mmc), unexpected);
2758 sdhci_dumpregs(host);
2759 }
f75979b7 2760
d129bceb
PO		 2761 return result;
2762}
2763
781e989c
RK		 2764static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2765{
2766 struct sdhci_host *host = dev_id;
2767 unsigned long flags;
2768 u32 isr;
2769
2770 spin_lock_irqsave(&host->lock, flags);
2771 isr = host->thread_isr;
2772 host->thread_isr = 0;
2773 spin_unlock_irqrestore(&host->lock, flags);
2774
3560db8e 2775 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d3940f27
AH		 2776 struct mmc_host *mmc = host->mmc;
2777
2778 mmc->ops->card_event(mmc);
2779 mmc_detect_change(mmc, msecs_to_jiffies(200));
3560db8e
RK		 2780 }
2781
781e989c
RK		 2782 if (isr & SDHCI_INT_CARD_INT) {
2783 sdio_run_irqs(host->mmc);
2784
2785 spin_lock_irqsave(&host->lock, flags);
2786 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2787 sdhci_enable_sdio_irq_nolock(host, true);
2788 spin_unlock_irqrestore(&host->lock, flags);
2789 }
2790
2791 return isr ? IRQ_HANDLED : IRQ_NONE;
2792}
2793
d129bceb
PO		 2794/*****************************************************************************\
2795 * *
2796 * Suspend/resume *
2797 * *
2798\*****************************************************************************/
2799
2800#ifdef CONFIG_PM
84d62605
LD		 2801/*
2802 * To enable wakeup events, the corresponding events have to be enabled in
2803 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2804 * Table' in the SD Host Controller Standard Specification.
2805 * It is useless to restore SDHCI_INT_ENABLE state in
2806 * sdhci_disable_irq_wakeups() since it will be set by
2807 * sdhci_enable_card_detection() or sdhci_init().
2808 */
ad080d79
KL		 2809void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2810{
2811 u8 val;
2812 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2813 | SDHCI_WAKE_ON_INT;
84d62605
LD		 2814 u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2815 SDHCI_INT_CARD_INT;
ad080d79
KL		 2816
2817 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2818 val |= mask ;
2819 /* Avoid fake wake up */
84d62605 2820 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
ad080d79 2821 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
84d62605
LD		 2822 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2823 }
ad080d79 2824 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
84d62605 2825 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
ad080d79
KL		 2826}
2827EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2828
0b10f478 2829static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2830{
2831 u8 val;
2832 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2833 | SDHCI_WAKE_ON_INT;
2834
2835 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2836 val &= ~mask;
2837 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2838}
d129bceb 2839
29495aa0 2840int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2841{
7260cf5e
AV		 2842 sdhci_disable_card_detection(host);
2843
66c39dfc 2844 mmc_retune_timer_stop(host->mmc);
cf2b5eea 2845
ad080d79 2846 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2847 host->ier = 0;
2848 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2849 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2850 free_irq(host->irq, host);
2851 } else {
2852 sdhci_enable_irq_wakeups(host);
2853 enable_irq_wake(host->irq);
2854 }
4ee14ec6 2855 return 0;
d129bceb
PO		 2856}
2857
b8c86fc5 2858EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2859
b8c86fc5
PO		 2860int sdhci_resume_host(struct sdhci_host *host)
2861{
d3940f27 2862 struct mmc_host *mmc = host->mmc;
4ee14ec6 2863 int ret = 0;
d129bceb 2864
a13abc7b 2865 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2866 if (host->ops->enable_dma)
2867 host->ops->enable_dma(host);
2868 }
d129bceb 2869
6308d290
AH		 2870 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2871 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2872 /* Card keeps power but host controller does not */
2873 sdhci_init(host, 0);
2874 host->pwr = 0;
2875 host->clock = 0;
d3940f27 2876 mmc->ops->set_ios(mmc, &mmc->ios);
6308d290
AH		 2877 } else {
2878 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2879 mmiowb();
2880 }
b8c86fc5 2881
14a7b416
HC		 2882 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2883 ret = request_threaded_irq(host->irq, sdhci_irq,
2884 sdhci_thread_irq, IRQF_SHARED,
2885 mmc_hostname(host->mmc), host);
2886 if (ret)
2887 return ret;
2888 } else {
2889 sdhci_disable_irq_wakeups(host);
2890 disable_irq_wake(host->irq);
2891 }
2892
7260cf5e
AV		 2893 sdhci_enable_card_detection(host);
2894
2f4cbb3d 2895 return ret;
d129bceb
PO		 2896}
2897
b8c86fc5 2898EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5 2899
66fd8ad5
AH		 2900int sdhci_runtime_suspend_host(struct sdhci_host *host)
2901{
2902 unsigned long flags;
66fd8ad5 2903
66c39dfc 2904 mmc_retune_timer_stop(host->mmc);
66fd8ad5
AH		 2905
2906 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2907 host->ier &= SDHCI_INT_CARD_INT;
2908 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2909 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2910 spin_unlock_irqrestore(&host->lock, flags);
2911
781e989c 2912 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2913
2914 spin_lock_irqsave(&host->lock, flags);
2915 host->runtime_suspended = true;
2916 spin_unlock_irqrestore(&host->lock, flags);
2917
8a125bad 2918 return 0;
66fd8ad5
AH		 2919}
2920EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2921
2922int sdhci_runtime_resume_host(struct sdhci_host *host)
2923{
d3940f27 2924 struct mmc_host *mmc = host->mmc;
66fd8ad5 2925 unsigned long flags;
8a125bad 2926 int host_flags = host->flags;
66fd8ad5
AH		 2927
2928 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2929 if (host->ops->enable_dma)
2930 host->ops->enable_dma(host);
2931 }
2932
2933 sdhci_init(host, 0);
2934
84ec048b
AH		 2935 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED) {
2936 /* Force clock and power re-program */
2937 host->pwr = 0;
2938 host->clock = 0;
2939 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
2940 mmc->ops->set_ios(mmc, &mmc->ios);
66fd8ad5 2941
84ec048b
AH		 2942 if ((host_flags & SDHCI_PV_ENABLED) &&
2943 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2944 spin_lock_irqsave(&host->lock, flags);
2945 sdhci_enable_preset_value(host, true);
2946 spin_unlock_irqrestore(&host->lock, flags);
2947 }
66fd8ad5 2948
84ec048b
AH		 2949 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
2950 mmc->ops->hs400_enhanced_strobe)
2951 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
2952 }
086b0ddb 2953
66fd8ad5
AH		 2954 spin_lock_irqsave(&host->lock, flags);
2955
2956 host->runtime_suspended = false;
2957
2958 /* Enable SDIO IRQ */
ef104333 2959 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2960 sdhci_enable_sdio_irq_nolock(host, true);
2961
2962 /* Enable Card Detection */
2963 sdhci_enable_card_detection(host);
2964
2965 spin_unlock_irqrestore(&host->lock, flags);
2966
8a125bad 2967 return 0;
66fd8ad5
AH		 2968}
2969EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2970
162d6f98 2971#endif /* CONFIG_PM */
66fd8ad5 2972
f12e39db
AH		 2973/*****************************************************************************\
2974 * *
2975 * Command Queue Engine (CQE) helpers *
2976 * *
2977\*****************************************************************************/
2978
2979void sdhci_cqe_enable(struct mmc_host *mmc)
2980{
2981 struct sdhci_host *host = mmc_priv(mmc);
2982 unsigned long flags;
2983 u8 ctrl;
2984
2985 spin_lock_irqsave(&host->lock, flags);
2986
2987 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2988 ctrl &= ~SDHCI_CTRL_DMA_MASK;
2989 if (host->flags & SDHCI_USE_64_BIT_DMA)
2990 ctrl |= SDHCI_CTRL_ADMA64;
2991 else
2992 ctrl |= SDHCI_CTRL_ADMA32;
2993 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2994
2995 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 512),
2996 SDHCI_BLOCK_SIZE);
2997
2998 /* Set maximum timeout */
2999 sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL);
3000
3001 host->ier = host->cqe_ier;
3002
3003 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3004 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3005
3006 host->cqe_on = true;
3007
3008 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3009 mmc_hostname(mmc), host->ier,
3010 sdhci_readl(host, SDHCI_INT_STATUS));
3011
3012 mmiowb();
3013 spin_unlock_irqrestore(&host->lock, flags);
3014}
3015EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3016
3017void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3018{
3019 struct sdhci_host *host = mmc_priv(mmc);
3020 unsigned long flags;
3021
3022 spin_lock_irqsave(&host->lock, flags);
3023
3024 sdhci_set_default_irqs(host);
3025
3026 host->cqe_on = false;
3027
3028 if (recovery) {
3029 sdhci_do_reset(host, SDHCI_RESET_CMD);
3030 sdhci_do_reset(host, SDHCI_RESET_DATA);
3031 }
3032
3033 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3034 mmc_hostname(mmc), host->ier,
3035 sdhci_readl(host, SDHCI_INT_STATUS));
3036
3037 mmiowb();
3038 spin_unlock_irqrestore(&host->lock, flags);
3039}
3040EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3041
3042bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3043 int *data_error)
3044{
3045 u32 mask;
3046
3047 if (!host->cqe_on)
3048 return false;
3049
3050 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3051 *cmd_error = -EILSEQ;
3052 else if (intmask & SDHCI_INT_TIMEOUT)
3053 *cmd_error = -ETIMEDOUT;
3054 else
3055 *cmd_error = 0;
3056
3057 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3058 *data_error = -EILSEQ;
3059 else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3060 *data_error = -ETIMEDOUT;
3061 else if (intmask & SDHCI_INT_ADMA_ERROR)
3062 *data_error = -EIO;
3063 else
3064 *data_error = 0;
3065
3066 /* Clear selected interrupts. */
3067 mask = intmask & host->cqe_ier;
3068 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3069
3070 if (intmask & SDHCI_INT_BUS_POWER)
3071 pr_err("%s: Card is consuming too much power!\n",
3072 mmc_hostname(host->mmc));
3073
3074 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3075 if (intmask) {
3076 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3077 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3078 mmc_hostname(host->mmc), intmask);
3079 sdhci_dumpregs(host);
3080 }
3081
3082 return true;
3083}
3084EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3085
d129bceb
PO		 3086/*****************************************************************************\
3087 * *
b8c86fc5 3088 * Device allocation/registration *
d129bceb
PO		 3089 * *
3090\*****************************************************************************/
3091
b8c86fc5
PO		 3092struct sdhci_host *sdhci_alloc_host(struct device *dev,
3093 size_t priv_size)
d129bceb 3094{
d129bceb
PO		 3095 struct mmc_host *mmc;
3096 struct sdhci_host *host;
3097
b8c86fc5 3098 WARN_ON(dev == NULL);
d129bceb 3099
b8c86fc5 3100 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 3101 if (!mmc)
b8c86fc5 3102 return ERR_PTR(-ENOMEM);
d129bceb
PO		 3103
3104 host = mmc_priv(mmc);
3105 host->mmc = mmc;
bf60e592
AH		 3106 host->mmc_host_ops = sdhci_ops;
3107 mmc->ops = &host->mmc_host_ops;
d129bceb 3108
8cb851a4
AH		 3109 host->flags = SDHCI_SIGNALING_330;
3110
f12e39db
AH		 3111 host->cqe_ier = SDHCI_CQE_INT_MASK;
3112 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3113
b8c86fc5
PO		 3114 return host;
3115}
8a4da143 3116
b8c86fc5 3117EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 3118
7b91369b
AC		 3119static int sdhci_set_dma_mask(struct sdhci_host *host)
3120{
3121 struct mmc_host *mmc = host->mmc;
3122 struct device *dev = mmc_dev(mmc);
3123 int ret = -EINVAL;
3124
3125 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3126 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3127
3128 /* Try 64-bit mask if hardware is capable of it */
3129 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3130 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3131 if (ret) {
3132 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3133 mmc_hostname(mmc));
3134 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3135 }
3136 }
3137
3138 /* 32-bit mask as default & fallback */
3139 if (ret) {
3140 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3141 if (ret)
3142 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3143 mmc_hostname(mmc));
3144 }
3145
3146 return ret;
3147}
3148
6132a3bf
AH		 3149void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
3150{
3151 u16 v;
92e0c44b
ZB		 3152 u64 dt_caps_mask = 0;
3153 u64 dt_caps = 0;
6132a3bf
AH		 3154
3155 if (host->read_caps)
3156 return;
3157
3158 host->read_caps = true;
3159
3160 if (debug_quirks)
3161 host->quirks = debug_quirks;
3162
3163 if (debug_quirks2)
3164 host->quirks2 = debug_quirks2;
3165
3166 sdhci_do_reset(host, SDHCI_RESET_ALL);
3167
92e0c44b
ZB		 3168 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3169 "sdhci-caps-mask", &dt_caps_mask);
3170 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3171 "sdhci-caps", &dt_caps);
3172
6132a3bf
AH		 3173 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3174 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3175
3176 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3177 return;
3178
92e0c44b
ZB		 3179 if (caps) {
3180 host->caps = *caps;
3181 } else {
3182 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3183 host->caps &= ~lower_32_bits(dt_caps_mask);
3184 host->caps |= lower_32_bits(dt_caps);
3185 }
6132a3bf
AH		 3186
3187 if (host->version < SDHCI_SPEC_300)
3188 return;
3189
92e0c44b
ZB		 3190 if (caps1) {
3191 host->caps1 = *caps1;
3192 } else {
3193 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3194 host->caps1 &= ~upper_32_bits(dt_caps_mask);
3195 host->caps1 |= upper_32_bits(dt_caps);
3196 }
6132a3bf
AH		 3197}
3198EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3199
52f5336d 3200int sdhci_setup_host(struct sdhci_host *host)
b8c86fc5
PO		 3201{
3202 struct mmc_host *mmc;
f2119df6
AN		 3203 u32 max_current_caps;
3204 unsigned int ocr_avail;
f5fa92e5 3205 unsigned int override_timeout_clk;
59241757 3206 u32 max_clk;
b8c86fc5 3207 int ret;
d129bceb 3208
b8c86fc5
PO		 3209 WARN_ON(host == NULL);
3210 if (host == NULL)
3211 return -EINVAL;
d129bceb 3212
b8c86fc5 3213 mmc = host->mmc;
d129bceb 3214
efba142b
JH		 3215 /*
3216 * If there are external regulators, get them. Note this must be done
3217 * early before resetting the host and reading the capabilities so that
3218 * the host can take the appropriate action if regulators are not
3219 * available.
3220 */
3221 ret = mmc_regulator_get_supply(mmc);
3222 if (ret == -EPROBE_DEFER)
3223 return ret;
3224
6132a3bf 3225 sdhci_read_caps(host);
d129bceb 3226
f5fa92e5
AH		 3227 override_timeout_clk = host->timeout_clk;
3228
85105c53 3229 if (host->version > SDHCI_SPEC_300) {
2e4456f0
MV		 3230 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3231 mmc_hostname(mmc), host->version);
4a965505
PO		 3232 }
3233
b8c86fc5 3234 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 3235 host->flags |= SDHCI_USE_SDMA;
28da3589 3236 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
a13abc7b 3237 DBG("Controller doesn't have SDMA capability\n");
67435274 3238 else
a13abc7b 3239 host->flags |= SDHCI_USE_SDMA;
d129bceb 3240
b8c86fc5 3241 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 3242 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 3243 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 3244 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 3245 }
3246
f2119df6 3247 if ((host->version >= SDHCI_SPEC_200) &&
28da3589 3248 (host->caps & SDHCI_CAN_DO_ADMA2))
a13abc7b 3249 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 3250
3251 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3252 (host->flags & SDHCI_USE_ADMA)) {
3253 DBG("Disabling ADMA as it is marked broken\n");
3254 host->flags &= ~SDHCI_USE_ADMA;
3255 }
3256
e57a5f61
AH		 3257 /*
3258 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3259 * and *must* do 64-bit DMA. A driver has the opportunity to change
3260 * that during the first call to ->enable_dma(). Similarly
3261 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3262 * implement.
3263 */
28da3589 3264 if (host->caps & SDHCI_CAN_64BIT)
e57a5f61
AH		 3265 host->flags |= SDHCI_USE_64_BIT_DMA;
3266
a13abc7b 3267 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
7b91369b
AC		 3268 ret = sdhci_set_dma_mask(host);
3269
3270 if (!ret && host->ops->enable_dma)
3271 ret = host->ops->enable_dma(host);
3272
3273 if (ret) {
3274 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3275 mmc_hostname(mmc));
3276 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3277
3278 ret = 0;
d129bceb
PO		 3279 }
3280 }
3281
e57a5f61
AH		 3282 /* SDMA does not support 64-bit DMA */
3283 if (host->flags & SDHCI_USE_64_BIT_DMA)
3284 host->flags &= ~SDHCI_USE_SDMA;
3285
2134a922 3286 if (host->flags & SDHCI_USE_ADMA) {
e66e61cb
RK		 3287 dma_addr_t dma;
3288 void *buf;
3289
2134a922 3290 /*
76fe379a
AH		 3291 * The DMA descriptor table size is calculated as the maximum
3292 * number of segments times 2, to allow for an alignment
3293 * descriptor for each segment, plus 1 for a nop end descriptor,
3294 * all multipled by the descriptor size.
2134a922 3295 */
e57a5f61
AH		 3296 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3297 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3298 SDHCI_ADMA2_64_DESC_SZ;
e57a5f61 3299 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
e57a5f61
AH		 3300 } else {
3301 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3302 SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 3303 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 3304 }
e66e61cb 3305
04a5ae6f 3306 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
e66e61cb
RK		 3307 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3308 host->adma_table_sz, &dma, GFP_KERNEL);
3309 if (!buf) {
6606110d 3310 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 3311 mmc_hostname(mmc));
3312 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 3313 } else if ((dma + host->align_buffer_sz) &
3314 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 3315 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3316 mmc_hostname(mmc));
d1e49f77 3317 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 3318 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3319 host->adma_table_sz, buf, dma);
3320 } else {
3321 host->align_buffer = buf;
3322 host->align_addr = dma;
edd63fcc 3323
e66e61cb
RK		 3324 host->adma_table = buf + host->align_buffer_sz;
3325 host->adma_addr = dma + host->align_buffer_sz;
3326 }
2134a922
PO		 3327 }
3328
7659150c
PO		 3329 /*
3330 * If we use DMA, then it's up to the caller to set the DMA
3331 * mask, but PIO does not need the hw shim so we set a new
3332 * mask here in that case.
3333 */
a13abc7b 3334 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 3335 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 3336 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 3337 }
d129bceb 3338
c4687d5f 3339 if (host->version >= SDHCI_SPEC_300)
28da3589 3340 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 3341 >> SDHCI_CLOCK_BASE_SHIFT;
3342 else
28da3589 3343 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 3344 >> SDHCI_CLOCK_BASE_SHIFT;
3345
4240ff0a 3346 host->max_clk *= 1000000;
f27f47ef
AV		 3347 if (host->max_clk == 0 || host->quirks &
3348 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 3349 if (!host->ops->get_max_clock) {
2e4456f0
MV		 3350 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3351 mmc_hostname(mmc));
eb5c20de
AH		 3352 ret = -ENODEV;
3353 goto undma;
4240ff0a
BD		 3354 }
3355 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 3356 }
d129bceb 3357
c3ed3877
AN		 3358 /*
3359 * In case of Host Controller v3.00, find out whether clock
3360 * multiplier is supported.
3361 */
28da3589 3362 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
c3ed3877
AN		 3363 SDHCI_CLOCK_MUL_SHIFT;
3364
3365 /*
3366 * In case the value in Clock Multiplier is 0, then programmable
3367 * clock mode is not supported, otherwise the actual clock
3368 * multiplier is one more than the value of Clock Multiplier
3369 * in the Capabilities Register.
3370 */
3371 if (host->clk_mul)
3372 host->clk_mul += 1;
3373
d129bceb
PO		 3374 /*
3375 * Set host parameters.
3376 */
59241757
DA		 3377 max_clk = host->max_clk;
3378
ce5f036b 3379 if (host->ops->get_min_clock)
a9e58f25 3380 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3381 else if (host->version >= SDHCI_SPEC_300) {
3382 if (host->clk_mul) {
3383 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 3384 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 3385 } else
3386 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3387 } else
0397526d 3388 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3389
d310ae49 3390 if (!mmc->f_max || mmc->f_max > max_clk)
59241757
DA		 3391 mmc->f_max = max_clk;
3392
28aab053 3393 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
28da3589 3394 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
28aab053 3395 SDHCI_TIMEOUT_CLK_SHIFT;
8cc35289
SL		 3396
3397 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3398 host->timeout_clk *= 1000;
3399
28aab053 3400 if (host->timeout_clk == 0) {
8cc35289 3401 if (!host->ops->get_timeout_clock) {
28aab053
AD		 3402 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3403 mmc_hostname(mmc));
eb5c20de
AH		 3404 ret = -ENODEV;
3405 goto undma;
28aab053 3406 }
272308ca 3407
8cc35289
SL		 3408 host->timeout_clk =
3409 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
3410 1000);
3411 }
272308ca 3412
99513624
AH		 3413 if (override_timeout_clk)
3414 host->timeout_clk = override_timeout_clk;
3415
28aab053 3416 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3417 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3418 mmc->max_busy_timeout /= host->timeout_clk;
3419 }
58d1246d 3420
e89d456f 3421 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3422 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3423
3424 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3425 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3426
8edf6371 3427 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3428 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3429 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3430 !(host->flags & SDHCI_USE_SDMA)) &&
3431 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371 3432 host->flags |= SDHCI_AUTO_CMD23;
f421865d 3433 DBG("Auto-CMD23 available\n");
8edf6371 3434 } else {
f421865d 3435 DBG("Auto-CMD23 unavailable\n");
8edf6371
AW		 3436 }
3437
15ec4461
PR		 3438 /*
3439 * A controller may support 8-bit width, but the board itself
3440 * might not have the pins brought out. Boards that support
3441 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3442 * their platform code before calling sdhci_add_host(), and we
3443 * won't assume 8-bit width for hosts without that CAP.
3444 */
5fe23c7f 3445 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3446 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3447
63ef5d8c
JH		 3448 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3449 mmc->caps &= ~MMC_CAP_CMD23;
3450
28da3589 3451 if (host->caps & SDHCI_CAN_DO_HISPD)
a29e7e18 3452 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3453
176d1ed4 3454 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
860951c5 3455 mmc_card_is_removable(mmc) &&
287980e4 3456 mmc_gpio_get_cd(host->mmc) < 0)
68d1fb7e
AV		 3457 mmc->caps |= MMC_CAP_NEEDS_POLL;
3458
6231f3de 3459 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3460 if (!IS_ERR(mmc->supply.vqmmc)) {
3461 ret = regulator_enable(mmc->supply.vqmmc);
3462 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3463 1950000))
28da3589
AH		 3464 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3465 SDHCI_SUPPORT_SDR50 |
3466 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3467 if (ret) {
3468 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3469 mmc_hostname(mmc), ret);
4bb74313 3470 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3471 }
8363c374 3472 }
6231f3de 3473
28da3589
AH		 3474 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3475 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3476 SDHCI_SUPPORT_DDR50);
3477 }
6a66180a 3478
4188bba0 3479 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
28da3589
AH		 3480 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3481 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3482 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3483
3484 /* SDR104 supports also implies SDR50 support */
28da3589 3485 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
f2119df6 3486 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3487 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3488 * field can be promoted to support HS200.
3489 */
549c0b18 3490 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3491 mmc->caps2 |= MMC_CAP2_HS200;
28da3589 3492 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
f2119df6 3493 mmc->caps |= MMC_CAP_UHS_SDR50;
28da3589 3494 }
f2119df6 3495
e9fb05d5 3496 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
28da3589 3497 (host->caps1 & SDHCI_SUPPORT_HS400))
e9fb05d5
AH		 3498 mmc->caps2 |= MMC_CAP2_HS400;
3499
549c0b18
AH		 3500 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3501 (IS_ERR(mmc->supply.vqmmc) ||
3502 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3503 1300000)))
3504 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3505
28da3589
AH		 3506 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3507 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3508 mmc->caps |= MMC_CAP_UHS_DDR50;
3509
069c9f14 3510 /* Does the host need tuning for SDR50? */
28da3589 3511 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
b513ea25
AN		 3512 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3513
d6d50a15 3514 /* Driver Type(s) (A, C, D) supported by the host */
28da3589 3515 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
d6d50a15 3516 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
28da3589 3517 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
d6d50a15 3518 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
28da3589 3519 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
d6d50a15
AN		 3520 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3521
cf2b5eea 3522 /* Initial value for re-tuning timer count */
28da3589
AH		 3523 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3524 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
cf2b5eea
AN		 3525
3526 /*
3527 * In case Re-tuning Timer is not disabled, the actual value of
3528 * re-tuning timer will be 2 ^ (n - 1).
3529 */
3530 if (host->tuning_count)
3531 host->tuning_count = 1 << (host->tuning_count - 1);
3532
3533 /* Re-tuning mode supported by the Host Controller */
28da3589 3534 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
cf2b5eea
AN		 3535 SDHCI_RETUNING_MODE_SHIFT;
3536
8f230f45 3537 ocr_avail = 0;
bad37e1a 3538
f2119df6
AN		 3539 /*
3540 * According to SD Host Controller spec v3.00, if the Host System
3541 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3542 * the value is meaningful only if Voltage Support in the Capabilities
3543 * register is set. The actual current value is 4 times the register
3544 * value.
3545 */
3546 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3547 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3548 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3549 if (curr > 0) {
3550
3551 /* convert to SDHCI_MAX_CURRENT format */
3552 curr = curr/1000; /* convert to mA */
3553 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3554
3555 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3556 max_current_caps =
3557 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3558 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3559 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3560 }
3561 }
f2119df6 3562
28da3589 3563 if (host->caps & SDHCI_CAN_VDD_330) {
8f230f45 3564 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3565
55c4665e 3566 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3567 SDHCI_MAX_CURRENT_330_MASK) >>
3568 SDHCI_MAX_CURRENT_330_SHIFT) *
3569 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 3570 }
28da3589 3571 if (host->caps & SDHCI_CAN_VDD_300) {
8f230f45 3572 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3573
55c4665e 3574 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3575 SDHCI_MAX_CURRENT_300_MASK) >>
3576 SDHCI_MAX_CURRENT_300_SHIFT) *
3577 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 3578 }
28da3589 3579 if (host->caps & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3580 ocr_avail |= MMC_VDD_165_195;
3581
55c4665e 3582 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3583 SDHCI_MAX_CURRENT_180_MASK) >>
3584 SDHCI_MAX_CURRENT_180_SHIFT) *
3585 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3586 }
3587
5fd26c7e
UH		 3588 /* If OCR set by host, use it instead. */
3589 if (host->ocr_mask)
3590 ocr_avail = host->ocr_mask;
3591
3592 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3593 if (mmc->ocr_avail)
52221610 3594 ocr_avail = mmc->ocr_avail;
3a48edc4 3595
8f230f45
TI		 3596 mmc->ocr_avail = ocr_avail;
3597 mmc->ocr_avail_sdio = ocr_avail;
3598 if (host->ocr_avail_sdio)
3599 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3600 mmc->ocr_avail_sd = ocr_avail;
3601 if (host->ocr_avail_sd)
3602 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3603 else /* normal SD controllers don't support 1.8V */
3604 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3605 mmc->ocr_avail_mmc = ocr_avail;
3606 if (host->ocr_avail_mmc)
3607 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3608
3609 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 3610 pr_err("%s: Hardware doesn't report any support voltages.\n",
3611 mmc_hostname(mmc));
eb5c20de
AH		 3612 ret = -ENODEV;
3613 goto unreg;
146ad66e
PO		 3614 }
3615
8cb851a4
AH		 3616 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3617 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3618 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3619 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3620 host->flags |= SDHCI_SIGNALING_180;
3621
3622 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3623 host->flags |= SDHCI_SIGNALING_120;
3624
d129bceb
PO		 3625 spin_lock_init(&host->lock);
3626
3627 /*
2134a922
PO		 3628 * Maximum number of segments. Depends on if the hardware
3629 * can do scatter/gather or not.
d129bceb 3630 */
2134a922 3631 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3632 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3633 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3634 mmc->max_segs = 1;
2134a922 3635 else /* PIO */
4fb213f8 3636 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3637
3638 /*
ac00531d
AH		 3639 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3640 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3641 * is less anyway.
d129bceb 3642 */
55db890a 3643 mmc->max_req_size = 524288;
d129bceb
PO		 3644
3645 /*
3646 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3647 * of bytes. When doing hardware scatter/gather, each entry cannot
3648 * be larger than 64 KiB though.
d129bceb 3649 */
30652aa3
OJ		 3650 if (host->flags & SDHCI_USE_ADMA) {
3651 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3652 mmc->max_seg_size = 65535;
3653 else
3654 mmc->max_seg_size = 65536;
3655 } else {
2134a922 3656 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3657 }
d129bceb 3658
fe4a3c7a
PO		 3659 /*
3660 * Maximum block size. This varies from controller to controller and
3661 * is specified in the capabilities register.
3662 */
0633f654
AV		 3663 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3664 mmc->max_blk_size = 2;
3665 } else {
28da3589 3666 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3667 SDHCI_MAX_BLOCK_SHIFT;
3668 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3669 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3670 mmc_hostname(mmc));
0633f654
AV		 3671 mmc->max_blk_size = 0;
3672 }
3673 }
3674
3675 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3676
55db890a
PO		 3677 /*
3678 * Maximum block count.
3679 */
1388eefd 3680 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3681
52f5336d
AH		 3682 return 0;
3683
3684unreg:
3685 if (!IS_ERR(mmc->supply.vqmmc))
3686 regulator_disable(mmc->supply.vqmmc);
3687undma:
3688 if (host->align_buffer)
3689 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3690 host->adma_table_sz, host->align_buffer,
3691 host->align_addr);
3692 host->adma_table = NULL;
3693 host->align_buffer = NULL;
3694
3695 return ret;
3696}
3697EXPORT_SYMBOL_GPL(sdhci_setup_host);
3698
4180ffa8
AH		 3699void sdhci_cleanup_host(struct sdhci_host *host)
3700{
3701 struct mmc_host *mmc = host->mmc;
3702
3703 if (!IS_ERR(mmc->supply.vqmmc))
3704 regulator_disable(mmc->supply.vqmmc);
3705
3706 if (host->align_buffer)
3707 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3708 host->adma_table_sz, host->align_buffer,
3709 host->align_addr);
3710 host->adma_table = NULL;
3711 host->align_buffer = NULL;
3712}
3713EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
3714
52f5336d
AH		 3715int __sdhci_add_host(struct sdhci_host *host)
3716{
3717 struct mmc_host *mmc = host->mmc;
3718 int ret;
3719
d129bceb
PO		 3720 /*
3721 * Init tasklets.
3722 */
d129bceb
PO		 3723 tasklet_init(&host->finish_tasklet,
3724 sdhci_tasklet_finish, (unsigned long)host);
3725
e4cad1b5 3726 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d7422fb4
AH		 3727 setup_timer(&host->data_timer, sdhci_timeout_data_timer,
3728 (unsigned long)host);
d129bceb 3729
250fb7b4 3730 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3731
2af502ca
SG		 3732 sdhci_init(host, 0);
3733
781e989c
RK		 3734 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3735 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3736 if (ret) {
3737 pr_err("%s: Failed to request IRQ %d: %d\n",
3738 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3739 goto untasklet;
0fc81ee3 3740 }
d129bceb 3741
d129bceb
PO		 3742#ifdef CONFIG_MMC_DEBUG
3743 sdhci_dumpregs(host);
3744#endif
3745
061d17a6 3746 ret = sdhci_led_register(host);
0fc81ee3
MB		 3747 if (ret) {
3748 pr_err("%s: Failed to register LED device: %d\n",
3749 mmc_hostname(mmc), ret);
eb5c20de 3750 goto unirq;
0fc81ee3 3751 }
2f730fec 3752
5f25a66f
PO		 3753 mmiowb();
3754
eb5c20de
AH		 3755 ret = mmc_add_host(mmc);
3756 if (ret)
3757 goto unled;
d129bceb 3758
a3c76eb9 3759 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3760 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3761 (host->flags & SDHCI_USE_ADMA) ?
3762 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3763 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3764
7260cf5e
AV		 3765 sdhci_enable_card_detection(host);
3766
d129bceb
PO		 3767 return 0;
3768
eb5c20de 3769unled:
061d17a6 3770 sdhci_led_unregister(host);
eb5c20de 3771unirq:
03231f9b 3772 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3773 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3774 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec 3775 free_irq(host->irq, host);
8ef1a143 3776untasklet:
d129bceb 3777 tasklet_kill(&host->finish_tasklet);
52f5336d 3778
d129bceb
PO		 3779 return ret;
3780}
52f5336d
AH		 3781EXPORT_SYMBOL_GPL(__sdhci_add_host);
3782
3783int sdhci_add_host(struct sdhci_host *host)
3784{
3785 int ret;
3786
3787 ret = sdhci_setup_host(host);
3788 if (ret)
3789 return ret;
d129bceb 3790
4180ffa8
AH		 3791 ret = __sdhci_add_host(host);
3792 if (ret)
3793 goto cleanup;
3794
3795 return 0;
3796
3797cleanup:
3798 sdhci_cleanup_host(host);
3799
3800 return ret;
52f5336d 3801}
b8c86fc5 3802EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3803
1e72859e 3804void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3805{
3a48edc4 3806 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3807 unsigned long flags;
3808
3809 if (dead) {
3810 spin_lock_irqsave(&host->lock, flags);
3811
3812 host->flags |= SDHCI_DEVICE_DEAD;
3813
5d0d11c5 3814 if (sdhci_has_requests(host)) {
a3c76eb9 3815 pr_err("%s: Controller removed during "
4e743f1f 3816 " transfer!\n", mmc_hostname(mmc));
5d0d11c5 3817 sdhci_error_out_mrqs(host, -ENOMEDIUM);
1e72859e
PO		 3818 }
3819
3820 spin_unlock_irqrestore(&host->lock, flags);
3821 }
3822
7260cf5e
AV		 3823 sdhci_disable_card_detection(host);
3824
4e743f1f 3825 mmc_remove_host(mmc);
d129bceb 3826
061d17a6 3827 sdhci_led_unregister(host);
2f730fec 3828
1e72859e 3829 if (!dead)
03231f9b 3830 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3831
b537f94c
RK		 3832 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3833 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3834 free_irq(host->irq, host);
3835
3836 del_timer_sync(&host->timer);
d7422fb4 3837 del_timer_sync(&host->data_timer);
d129bceb 3838
d129bceb 3839 tasklet_kill(&host->finish_tasklet);
2134a922 3840
3a48edc4
TK		 3841 if (!IS_ERR(mmc->supply.vqmmc))
3842 regulator_disable(mmc->supply.vqmmc);
6231f3de 3843
edd63fcc 3844 if (host->align_buffer)
e66e61cb
RK		 3845 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3846 host->adma_table_sz, host->align_buffer,
3847 host->align_addr);
2134a922 3848
4efaa6fb 3849 host->adma_table = NULL;
2134a922 3850 host->align_buffer = NULL;
d129bceb
PO		 3851}
3852
b8c86fc5 3853EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3854
b8c86fc5 3855void sdhci_free_host(struct sdhci_host *host)
d129bceb 3856{
b8c86fc5 3857 mmc_free_host(host->mmc);
d129bceb
PO		 3858}
3859
b8c86fc5 3860EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3861
3862/*****************************************************************************\
3863 * *
3864 * Driver init/exit *
3865 * *
3866\*****************************************************************************/
3867
3868static int __init sdhci_drv_init(void)
3869{
a3c76eb9 3870 pr_info(DRIVER_NAME
52fbf9c9 3871 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3872 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3873
b8c86fc5 3874 return 0;
d129bceb
PO		 3875}
3876
3877static void __exit sdhci_drv_exit(void)
3878{
d129bceb
PO		 3879}
3880
3881module_init(sdhci_drv_init);
3882module_exit(sdhci_drv_exit);
3883
df673b22 3884module_param(debug_quirks, uint, 0444);
66fd8ad5 3885module_param(debug_quirks2, uint, 0444);
67435274 3886
32710e8f 3887MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3888MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3889MODULE_LICENSE("GPL");
67435274 3890
df673b22 3891MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3892MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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