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mmc: core: Use CMD23 for multiblock transfers when we can.
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
d129bceb 19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
11763609 21#include <linux/scatterlist.h>
9bea3c85 22#include <linux/regulator/consumer.h>
d129bceb 23
2f730fec
PO		 24#include <linux/leds.h>
25
22113efd 26#include <linux/mmc/mmc.h>
d129bceb 27#include <linux/mmc/host.h>
d129bceb 28
d129bceb
PO		 29#include "sdhci.h"
30
31#define DRIVER_NAME "sdhci"
d129bceb 32
d129bceb 33#define DBG(f, x...) \
c6563178 34 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 35
f9134319
PO		 36#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
37 defined(CONFIG_MMC_SDHCI_MODULE))
38#define SDHCI_USE_LEDS_CLASS
39#endif
40
b513ea25
AN		 41#define MAX_TUNING_LOOP 40
42
df673b22 43static unsigned int debug_quirks = 0;
67435274 44
d129bceb
PO		 45static void sdhci_finish_data(struct sdhci_host *);
46
47static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
48static void sdhci_finish_command(struct sdhci_host *);
cf2b5eea
AN		 49static int sdhci_execute_tuning(struct mmc_host *mmc);
50static void sdhci_tuning_timer(unsigned long data);
d129bceb
PO		 51
52static void sdhci_dumpregs(struct sdhci_host *host)
53{
412ab659
PR		 54 printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
55 mmc_hostname(host->mmc));
d129bceb
PO		 56
57 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 58 sdhci_readl(host, SDHCI_DMA_ADDRESS),
59 sdhci_readw(host, SDHCI_HOST_VERSION));
d129bceb 60 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 61 sdhci_readw(host, SDHCI_BLOCK_SIZE),
62 sdhci_readw(host, SDHCI_BLOCK_COUNT));
d129bceb 63 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 64 sdhci_readl(host, SDHCI_ARGUMENT),
65 sdhci_readw(host, SDHCI_TRANSFER_MODE));
d129bceb 66 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 67 sdhci_readl(host, SDHCI_PRESENT_STATE),
68 sdhci_readb(host, SDHCI_HOST_CONTROL));
d129bceb 69 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 70 sdhci_readb(host, SDHCI_POWER_CONTROL),
71 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
d129bceb 72 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 73 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
74 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
d129bceb 75 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 76 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
77 sdhci_readl(host, SDHCI_INT_STATUS));
d129bceb 78 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 79 sdhci_readl(host, SDHCI_INT_ENABLE),
80 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
d129bceb 81 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 82 sdhci_readw(host, SDHCI_ACMD12_ERR),
83 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
e8120ad1 84 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 85 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1
PR		 86 sdhci_readl(host, SDHCI_CAPABILITIES_1));
87 printk(KERN_DEBUG DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
88 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 89 sdhci_readl(host, SDHCI_MAX_CURRENT));
f2119df6
AN		 90 printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n",
91 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 92
be3f4ae0
BD		 93 if (host->flags & SDHCI_USE_ADMA)
94 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
95 readl(host->ioaddr + SDHCI_ADMA_ERROR),
96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
97
d129bceb
PO		 98 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
99}
100
101/*****************************************************************************\
102 * *
103 * Low level functions *
104 * *
105\*****************************************************************************/
106
7260cf5e
AV		 107static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
108{
109 u32 ier;
110
111 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
112 ier &= ~clear;
113 ier |= set;
114 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
115 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
116}
117
118static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
119{
120 sdhci_clear_set_irqs(host, 0, irqs);
121}
122
123static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
124{
125 sdhci_clear_set_irqs(host, irqs, 0);
126}
127
128static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
129{
130 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
131
68d1fb7e
AV		 132 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
133 return;
134
7260cf5e
AV		 135 if (enable)
136 sdhci_unmask_irqs(host, irqs);
137 else
138 sdhci_mask_irqs(host, irqs);
139}
140
141static void sdhci_enable_card_detection(struct sdhci_host *host)
142{
143 sdhci_set_card_detection(host, true);
144}
145
146static void sdhci_disable_card_detection(struct sdhci_host *host)
147{
148 sdhci_set_card_detection(host, false);
149}
150
d129bceb
PO		 151static void sdhci_reset(struct sdhci_host *host, u8 mask)
152{
e16514d8 153 unsigned long timeout;
063a9dbb 154 u32 uninitialized_var(ier);
e16514d8 155
b8c86fc5 156 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 157 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 158 SDHCI_CARD_PRESENT))
159 return;
160 }
161
063a9dbb
AV		 162 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
163 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
164
393c1a34
PR		 165 if (host->ops->platform_reset_enter)
166 host->ops->platform_reset_enter(host, mask);
167
4e4141a5 168 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 169
e16514d8 170 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 171 host->clock = 0;
172
e16514d8
PO		 173 /* Wait max 100 ms */
174 timeout = 100;
175
176 /* hw clears the bit when it's done */
4e4141a5 177 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 178 if (timeout == 0) {
acf1da45 179 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 180 mmc_hostname(host->mmc), (int)mask);
181 sdhci_dumpregs(host);
182 return;
183 }
184 timeout--;
185 mdelay(1);
d129bceb 186 }
063a9dbb 187
393c1a34
PR		 188 if (host->ops->platform_reset_exit)
189 host->ops->platform_reset_exit(host, mask);
190
063a9dbb
AV		 191 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
192 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
d129bceb
PO		 193}
194
2f4cbb3d
NP		 195static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
196
197static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 198{
2f4cbb3d
NP		 199 if (soft)
200 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
201 else
202 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 203
7260cf5e
AV		 204 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
205 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 206 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
207 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 208 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 209
210 if (soft) {
211 /* force clock reconfiguration */
212 host->clock = 0;
213 sdhci_set_ios(host->mmc, &host->mmc->ios);
214 }
7260cf5e 215}
d129bceb 216
7260cf5e
AV		 217static void sdhci_reinit(struct sdhci_host *host)
218{
2f4cbb3d 219 sdhci_init(host, 0);
7260cf5e 220 sdhci_enable_card_detection(host);
d129bceb
PO		 221}
222
223static void sdhci_activate_led(struct sdhci_host *host)
224{
225 u8 ctrl;
226
4e4141a5 227 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 228 ctrl |= SDHCI_CTRL_LED;
4e4141a5 229 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 230}
231
232static void sdhci_deactivate_led(struct sdhci_host *host)
233{
234 u8 ctrl;
235
4e4141a5 236 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 237 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 238 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 239}
240
f9134319 241#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 242static void sdhci_led_control(struct led_classdev *led,
243 enum led_brightness brightness)
244{
245 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
246 unsigned long flags;
247
248 spin_lock_irqsave(&host->lock, flags);
249
250 if (brightness == LED_OFF)
251 sdhci_deactivate_led(host);
252 else
253 sdhci_activate_led(host);
254
255 spin_unlock_irqrestore(&host->lock, flags);
256}
257#endif
258
d129bceb
PO		 259/*****************************************************************************\
260 * *
261 * Core functions *
262 * *
263\*****************************************************************************/
264
a406f5a3 265static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 266{
7659150c
PO		 267 unsigned long flags;
268 size_t blksize, len, chunk;
7244b85b 269 u32 uninitialized_var(scratch);
7659150c 270 u8 *buf;
d129bceb 271
a406f5a3 272 DBG("PIO reading\n");
d129bceb 273
a406f5a3 274 blksize = host->data->blksz;
7659150c 275 chunk = 0;
d129bceb 276
7659150c 277 local_irq_save(flags);
d129bceb 278
a406f5a3 279 while (blksize) {
7659150c
PO		 280 if (!sg_miter_next(&host->sg_miter))
281 BUG();
d129bceb 282
7659150c 283 len = min(host->sg_miter.length, blksize);
d129bceb 284
7659150c
PO		 285 blksize -= len;
286 host->sg_miter.consumed = len;
14d836e7 287
7659150c 288 buf = host->sg_miter.addr;
d129bceb 289
7659150c
PO		 290 while (len) {
291 if (chunk == 0) {
4e4141a5 292 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 293 chunk = 4;
a406f5a3 294 }
7659150c
PO		 295
296 *buf = scratch & 0xFF;
297
298 buf++;
299 scratch >>= 8;
300 chunk--;
301 len--;
d129bceb 302 }
a406f5a3 303 }
7659150c
PO		 304
305 sg_miter_stop(&host->sg_miter);
306
307 local_irq_restore(flags);
a406f5a3 308}
d129bceb 309
a406f5a3
PO		 310static void sdhci_write_block_pio(struct sdhci_host *host)
311{
7659150c
PO		 312 unsigned long flags;
313 size_t blksize, len, chunk;
314 u32 scratch;
315 u8 *buf;
d129bceb 316
a406f5a3
PO		 317 DBG("PIO writing\n");
318
319 blksize = host->data->blksz;
7659150c
PO		 320 chunk = 0;
321 scratch = 0;
d129bceb 322
7659150c 323 local_irq_save(flags);
d129bceb 324
a406f5a3 325 while (blksize) {
7659150c
PO		 326 if (!sg_miter_next(&host->sg_miter))
327 BUG();
a406f5a3 328
7659150c
PO		 329 len = min(host->sg_miter.length, blksize);
330
331 blksize -= len;
332 host->sg_miter.consumed = len;
333
334 buf = host->sg_miter.addr;
d129bceb 335
7659150c
PO		 336 while (len) {
337 scratch |= (u32)*buf << (chunk * 8);
338
339 buf++;
340 chunk++;
341 len--;
342
343 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 344 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 345 chunk = 0;
346 scratch = 0;
d129bceb 347 }
d129bceb
PO		 348 }
349 }
7659150c
PO		 350
351 sg_miter_stop(&host->sg_miter);
352
353 local_irq_restore(flags);
a406f5a3
PO		 354}
355
356static void sdhci_transfer_pio(struct sdhci_host *host)
357{
358 u32 mask;
359
360 BUG_ON(!host->data);
361
7659150c 362 if (host->blocks == 0)
a406f5a3
PO		 363 return;
364
365 if (host->data->flags & MMC_DATA_READ)
366 mask = SDHCI_DATA_AVAILABLE;
367 else
368 mask = SDHCI_SPACE_AVAILABLE;
369
4a3cba32
PO		 370 /*
371 * Some controllers (JMicron JMB38x) mess up the buffer bits
372 * for transfers < 4 bytes. As long as it is just one block,
373 * we can ignore the bits.
374 */
375 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
376 (host->data->blocks == 1))
377 mask = ~0;
378
4e4141a5 379 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 380 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
381 udelay(100);
382
a406f5a3
PO		 383 if (host->data->flags & MMC_DATA_READ)
384 sdhci_read_block_pio(host);
385 else
386 sdhci_write_block_pio(host);
d129bceb 387
7659150c
PO		 388 host->blocks--;
389 if (host->blocks == 0)
a406f5a3 390 break;
a406f5a3 391 }
d129bceb 392
a406f5a3 393 DBG("PIO transfer complete.\n");
d129bceb
PO		 394}
395
2134a922
PO		 396static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
397{
398 local_irq_save(*flags);
399 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
400}
401
402static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
403{
404 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
405 local_irq_restore(*flags);
406}
407
118cd17d
BD		 408static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
409{
9e506f35
BD		 410 __le32 *dataddr = (__le32 __force *)(desc + 4);
411 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 412
9e506f35
BD		 413 /* SDHCI specification says ADMA descriptors should be 4 byte
414 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 415
9e506f35
BD		 416 cmdlen[0] = cpu_to_le16(cmd);
417 cmdlen[1] = cpu_to_le16(len);
418
419 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 420}
421
8f1934ce 422static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 423 struct mmc_data *data)
424{
425 int direction;
426
427 u8 *desc;
428 u8 *align;
429 dma_addr_t addr;
430 dma_addr_t align_addr;
431 int len, offset;
432
433 struct scatterlist *sg;
434 int i;
435 char *buffer;
436 unsigned long flags;
437
438 /*
439 * The spec does not specify endianness of descriptor table.
440 * We currently guess that it is LE.
441 */
442
443 if (data->flags & MMC_DATA_READ)
444 direction = DMA_FROM_DEVICE;
445 else
446 direction = DMA_TO_DEVICE;
447
448 /*
449 * The ADMA descriptor table is mapped further down as we
450 * need to fill it with data first.
451 */
452
453 host->align_addr = dma_map_single(mmc_dev(host->mmc),
454 host->align_buffer, 128 * 4, direction);
8d8bb39b 455 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 456 goto fail;
2134a922
PO		 457 BUG_ON(host->align_addr & 0x3);
458
459 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
460 data->sg, data->sg_len, direction);
8f1934ce
PO		 461 if (host->sg_count == 0)
462 goto unmap_align;
2134a922
PO		 463
464 desc = host->adma_desc;
465 align = host->align_buffer;
466
467 align_addr = host->align_addr;
468
469 for_each_sg(data->sg, sg, host->sg_count, i) {
470 addr = sg_dma_address(sg);
471 len = sg_dma_len(sg);
472
473 /*
474 * The SDHCI specification states that ADMA
475 * addresses must be 32-bit aligned. If they
476 * aren't, then we use a bounce buffer for
477 * the (up to three) bytes that screw up the
478 * alignment.
479 */
480 offset = (4 - (addr & 0x3)) & 0x3;
481 if (offset) {
482 if (data->flags & MMC_DATA_WRITE) {
483 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 484 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 485 memcpy(align, buffer, offset);
486 sdhci_kunmap_atomic(buffer, &flags);
487 }
488
118cd17d
BD		 489 /* tran, valid */
490 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 491
492 BUG_ON(offset > 65536);
493
2134a922
PO		 494 align += 4;
495 align_addr += 4;
496
497 desc += 8;
498
499 addr += offset;
500 len -= offset;
501 }
502
2134a922
PO		 503 BUG_ON(len > 65536);
504
118cd17d
BD		 505 /* tran, valid */
506 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 507 desc += 8;
508
509 /*
510 * If this triggers then we have a calculation bug
511 * somewhere. :/
512 */
513 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
514 }
515
70764a90
TA		 516 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
517 /*
518 * Mark the last descriptor as the terminating descriptor
519 */
520 if (desc != host->adma_desc) {
521 desc -= 8;
522 desc[0] |= 0x2; /* end */
523 }
524 } else {
525 /*
526 * Add a terminating entry.
527 */
2134a922 528
70764a90
TA		 529 /* nop, end, valid */
530 sdhci_set_adma_desc(desc, 0, 0, 0x3);
531 }
2134a922
PO		 532
533 /*
534 * Resync align buffer as we might have changed it.
535 */
536 if (data->flags & MMC_DATA_WRITE) {
537 dma_sync_single_for_device(mmc_dev(host->mmc),
538 host->align_addr, 128 * 4, direction);
539 }
540
541 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
542 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 543 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 544 goto unmap_entries;
2134a922 545 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 546
547 return 0;
548
549unmap_entries:
550 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
551 data->sg_len, direction);
552unmap_align:
553 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
554 128 * 4, direction);
555fail:
556 return -EINVAL;
2134a922
PO		 557}
558
559static void sdhci_adma_table_post(struct sdhci_host *host,
560 struct mmc_data *data)
561{
562 int direction;
563
564 struct scatterlist *sg;
565 int i, size;
566 u8 *align;
567 char *buffer;
568 unsigned long flags;
569
570 if (data->flags & MMC_DATA_READ)
571 direction = DMA_FROM_DEVICE;
572 else
573 direction = DMA_TO_DEVICE;
574
575 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
576 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
577
578 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
579 128 * 4, direction);
580
581 if (data->flags & MMC_DATA_READ) {
582 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
583 data->sg_len, direction);
584
585 align = host->align_buffer;
586
587 for_each_sg(data->sg, sg, host->sg_count, i) {
588 if (sg_dma_address(sg) & 0x3) {
589 size = 4 - (sg_dma_address(sg) & 0x3);
590
591 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 592 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 593 memcpy(buffer, align, size);
594 sdhci_kunmap_atomic(buffer, &flags);
595
596 align += 4;
597 }
598 }
599 }
600
601 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
602 data->sg_len, direction);
603}
604
a3c7778f 605static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 606{
1c8cde92 607 u8 count;
a3c7778f 608 struct mmc_data *data = cmd->data;
1c8cde92 609 unsigned target_timeout, current_timeout;
d129bceb 610
ee53ab5d
PO		 611 /*
612 * If the host controller provides us with an incorrect timeout
613 * value, just skip the check and use 0xE. The hardware may take
614 * longer to time out, but that's much better than having a too-short
615 * timeout value.
616 */
11a2f1b7 617 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 618 return 0xE;
e538fbe8 619
a3c7778f
AW		 620 /* Unspecified timeout, assume max */
621 if (!data && !cmd->cmd_timeout_ms)
622 return 0xE;
d129bceb 623
a3c7778f
AW		 624 /* timeout in us */
625 if (!data)
626 target_timeout = cmd->cmd_timeout_ms * 1000;
627 else
628 target_timeout = data->timeout_ns / 1000 +
629 data->timeout_clks / host->clock;
81b39802 630
4b01681c
MB		 631 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
632 host->timeout_clk = host->clock / 1000;
633
1c8cde92
PO		 634 /*
635 * Figure out needed cycles.
636 * We do this in steps in order to fit inside a 32 bit int.
637 * The first step is the minimum timeout, which will have a
638 * minimum resolution of 6 bits:
639 * (1) 2^13*1000 > 2^22,
640 * (2) host->timeout_clk < 2^16
641 * =>
642 * (1) / (2) > 2^6
643 */
4b01681c 644 BUG_ON(!host->timeout_clk);
1c8cde92
PO		 645 count = 0;
646 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
647 while (current_timeout < target_timeout) {
648 count++;
649 current_timeout <<= 1;
650 if (count >= 0xF)
651 break;
652 }
653
654 if (count >= 0xF) {
a3c7778f
AW		 655 printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
656 mmc_hostname(host->mmc), cmd->opcode);
1c8cde92
PO		 657 count = 0xE;
658 }
659
ee53ab5d
PO		 660 return count;
661}
662
6aa943ab
AV		 663static void sdhci_set_transfer_irqs(struct sdhci_host *host)
664{
665 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
666 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
667
668 if (host->flags & SDHCI_REQ_USE_DMA)
669 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
670 else
671 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
672}
673
a3c7778f 674static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 675{
676 u8 count;
2134a922 677 u8 ctrl;
a3c7778f 678 struct mmc_data *data = cmd->data;
8f1934ce 679 int ret;
ee53ab5d
PO		 680
681 WARN_ON(host->data);
682
a3c7778f
AW		 683 if (data || (cmd->flags & MMC_RSP_BUSY)) {
684 count = sdhci_calc_timeout(host, cmd);
685 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
686 }
687
688 if (!data)
ee53ab5d
PO		 689 return;
690
691 /* Sanity checks */
692 BUG_ON(data->blksz * data->blocks > 524288);
693 BUG_ON(data->blksz > host->mmc->max_blk_size);
694 BUG_ON(data->blocks > 65535);
695
696 host->data = data;
697 host->data_early = 0;
f6a03cbf 698 host->data->bytes_xfered = 0;
ee53ab5d 699
a13abc7b 700 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 701 host->flags |= SDHCI_REQ_USE_DMA;
702
2134a922
PO		 703 /*
704 * FIXME: This doesn't account for merging when mapping the
705 * scatterlist.
706 */
707 if (host->flags & SDHCI_REQ_USE_DMA) {
708 int broken, i;
709 struct scatterlist *sg;
710
711 broken = 0;
712 if (host->flags & SDHCI_USE_ADMA) {
713 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
714 broken = 1;
715 } else {
716 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
717 broken = 1;
718 }
719
720 if (unlikely(broken)) {
721 for_each_sg(data->sg, sg, data->sg_len, i) {
722 if (sg->length & 0x3) {
723 DBG("Reverting to PIO because of "
724 "transfer size (%d)\n",
725 sg->length);
726 host->flags &= ~SDHCI_REQ_USE_DMA;
727 break;
728 }
729 }
730 }
c9fddbc4
PO		 731 }
732
733 /*
734 * The assumption here being that alignment is the same after
735 * translation to device address space.
736 */
2134a922
PO		 737 if (host->flags & SDHCI_REQ_USE_DMA) {
738 int broken, i;
739 struct scatterlist *sg;
740
741 broken = 0;
742 if (host->flags & SDHCI_USE_ADMA) {
743 /*
744 * As we use 3 byte chunks to work around
745 * alignment problems, we need to check this
746 * quirk.
747 */
748 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
749 broken = 1;
750 } else {
751 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
752 broken = 1;
753 }
754
755 if (unlikely(broken)) {
756 for_each_sg(data->sg, sg, data->sg_len, i) {
757 if (sg->offset & 0x3) {
758 DBG("Reverting to PIO because of "
759 "bad alignment\n");
760 host->flags &= ~SDHCI_REQ_USE_DMA;
761 break;
762 }
763 }
764 }
765 }
766
8f1934ce
PO		 767 if (host->flags & SDHCI_REQ_USE_DMA) {
768 if (host->flags & SDHCI_USE_ADMA) {
769 ret = sdhci_adma_table_pre(host, data);
770 if (ret) {
771 /*
772 * This only happens when someone fed
773 * us an invalid request.
774 */
775 WARN_ON(1);
ebd6d357 776 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 777 } else {
4e4141a5
AV		 778 sdhci_writel(host, host->adma_addr,
779 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 780 }
781 } else {
c8b3e02e 782 int sg_cnt;
8f1934ce 783
c8b3e02e 784 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 785 data->sg, data->sg_len,
786 (data->flags & MMC_DATA_READ) ?
787 DMA_FROM_DEVICE :
788 DMA_TO_DEVICE);
c8b3e02e 789 if (sg_cnt == 0) {
8f1934ce
PO		 790 /*
791 * This only happens when someone fed
792 * us an invalid request.
793 */
794 WARN_ON(1);
ebd6d357 795 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 796 } else {
719a61b4 797 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 798 sdhci_writel(host, sg_dma_address(data->sg),
799 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 800 }
801 }
802 }
803
2134a922
PO		 804 /*
805 * Always adjust the DMA selection as some controllers
806 * (e.g. JMicron) can't do PIO properly when the selection
807 * is ADMA.
808 */
809 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 810 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 811 ctrl &= ~SDHCI_CTRL_DMA_MASK;
812 if ((host->flags & SDHCI_REQ_USE_DMA) &&
813 (host->flags & SDHCI_USE_ADMA))
814 ctrl |= SDHCI_CTRL_ADMA32;
815 else
816 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 817 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 818 }
819
8f1934ce 820 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 821 int flags;
822
823 flags = SG_MITER_ATOMIC;
824 if (host->data->flags & MMC_DATA_READ)
825 flags |= SG_MITER_TO_SG;
826 else
827 flags |= SG_MITER_FROM_SG;
828 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 829 host->blocks = data->blocks;
d129bceb 830 }
c7fa9963 831
6aa943ab
AV		 832 sdhci_set_transfer_irqs(host);
833
f6a03cbf
MV		 834 /* Set the DMA boundary value and block size */
835 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
836 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 837 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 838}
839
840static void sdhci_set_transfer_mode(struct sdhci_host *host,
841 struct mmc_data *data)
842{
843 u16 mode;
844
c7fa9963
PO		 845 if (data == NULL)
846 return;
847
e538fbe8
PO		 848 WARN_ON(!host->data);
849
c7fa9963 850 mode = SDHCI_TRNS_BLK_CNT_EN;
c4512f79
JH		 851 if (data->blocks > 1) {
852 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
853 mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
854 else
855 mode |= SDHCI_TRNS_MULTI;
856 }
c7fa9963
PO		 857 if (data->flags & MMC_DATA_READ)
858 mode |= SDHCI_TRNS_READ;
c9fddbc4 859 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 860 mode |= SDHCI_TRNS_DMA;
861
4e4141a5 862 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 863}
864
865static void sdhci_finish_data(struct sdhci_host *host)
866{
867 struct mmc_data *data;
d129bceb
PO		 868
869 BUG_ON(!host->data);
870
871 data = host->data;
872 host->data = NULL;
873
c9fddbc4 874 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 875 if (host->flags & SDHCI_USE_ADMA)
876 sdhci_adma_table_post(host, data);
877 else {
878 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
879 data->sg_len, (data->flags & MMC_DATA_READ) ?
880 DMA_FROM_DEVICE : DMA_TO_DEVICE);
881 }
d129bceb
PO		 882 }
883
884 /*
c9b74c5b
PO		 885 * The specification states that the block count register must
886 * be updated, but it does not specify at what point in the
887 * data flow. That makes the register entirely useless to read
888 * back so we have to assume that nothing made it to the card
889 * in the event of an error.
d129bceb 890 */
c9b74c5b
PO		 891 if (data->error)
892 data->bytes_xfered = 0;
d129bceb 893 else
c9b74c5b 894 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 895
d129bceb
PO		 896 if (data->stop) {
897 /*
898 * The controller needs a reset of internal state machines
899 * upon error conditions.
900 */
17b0429d 901 if (data->error) {
d129bceb
PO		 902 sdhci_reset(host, SDHCI_RESET_CMD);
903 sdhci_reset(host, SDHCI_RESET_DATA);
904 }
905
906 sdhci_send_command(host, data->stop);
907 } else
908 tasklet_schedule(&host->finish_tasklet);
909}
910
911static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
912{
913 int flags;
fd2208d7 914 u32 mask;
7cb2c76f 915 unsigned long timeout;
d129bceb
PO		 916
917 WARN_ON(host->cmd);
918
d129bceb 919 /* Wait max 10 ms */
7cb2c76f 920 timeout = 10;
fd2208d7
PO		 921
922 mask = SDHCI_CMD_INHIBIT;
923 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
924 mask |= SDHCI_DATA_INHIBIT;
925
926 /* We shouldn't wait for data inihibit for stop commands, even
927 though they might use busy signaling */
928 if (host->mrq->data && (cmd == host->mrq->data->stop))
929 mask &= ~SDHCI_DATA_INHIBIT;
930
4e4141a5 931 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 932 if (timeout == 0) {
d129bceb 933 printk(KERN_ERR "%s: Controller never released "
acf1da45 934 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 935 sdhci_dumpregs(host);
17b0429d 936 cmd->error = -EIO;
d129bceb
PO		 937 tasklet_schedule(&host->finish_tasklet);
938 return;
939 }
7cb2c76f
PO		 940 timeout--;
941 mdelay(1);
942 }
d129bceb
PO		 943
944 mod_timer(&host->timer, jiffies + 10 * HZ);
945
946 host->cmd = cmd;
947
a3c7778f 948 sdhci_prepare_data(host, cmd);
d129bceb 949
4e4141a5 950 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 951
c7fa9963
PO		 952 sdhci_set_transfer_mode(host, cmd->data);
953
d129bceb 954 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 955 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb 956 mmc_hostname(host->mmc));
17b0429d 957 cmd->error = -EINVAL;
d129bceb
PO		 958 tasklet_schedule(&host->finish_tasklet);
959 return;
960 }
961
962 if (!(cmd->flags & MMC_RSP_PRESENT))
963 flags = SDHCI_CMD_RESP_NONE;
964 else if (cmd->flags & MMC_RSP_136)
965 flags = SDHCI_CMD_RESP_LONG;
966 else if (cmd->flags & MMC_RSP_BUSY)
967 flags = SDHCI_CMD_RESP_SHORT_BUSY;
968 else
969 flags = SDHCI_CMD_RESP_SHORT;
970
971 if (cmd->flags & MMC_RSP_CRC)
972 flags |= SDHCI_CMD_CRC;
973 if (cmd->flags & MMC_RSP_OPCODE)
974 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 975
976 /* CMD19 is special in that the Data Present Select should be set */
977 if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
d129bceb
PO		 978 flags |= SDHCI_CMD_DATA;
979
4e4141a5 980 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 981}
982
983static void sdhci_finish_command(struct sdhci_host *host)
984{
985 int i;
986
987 BUG_ON(host->cmd == NULL);
988
989 if (host->cmd->flags & MMC_RSP_PRESENT) {
990 if (host->cmd->flags & MMC_RSP_136) {
991 /* CRC is stripped so we need to do some shifting. */
992 for (i = 0;i < 4;i++) {
4e4141a5 993 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 994 SDHCI_RESPONSE + (3-i)*4) << 8;
995 if (i != 3)
996 host->cmd->resp[i] |=
4e4141a5 997 sdhci_readb(host,
d129bceb
PO		 998 SDHCI_RESPONSE + (3-i)*4-1);
999 }
1000 } else {
4e4141a5 1001 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1002 }
1003 }
1004
17b0429d 1005 host->cmd->error = 0;
d129bceb 1006
e538fbe8
PO		 1007 if (host->data && host->data_early)
1008 sdhci_finish_data(host);
1009
1010 if (!host->cmd->data)
d129bceb
PO		 1011 tasklet_schedule(&host->finish_tasklet);
1012
1013 host->cmd = NULL;
1014}
1015
1016static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1017{
c3ed3877
AN		 1018 int div = 0; /* Initialized for compiler warning */
1019 u16 clk = 0;
7cb2c76f 1020 unsigned long timeout;
d129bceb
PO		 1021
1022 if (clock == host->clock)
1023 return;
1024
8114634c
AV		 1025 if (host->ops->set_clock) {
1026 host->ops->set_clock(host, clock);
1027 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1028 return;
1029 }
1030
4e4141a5 1031 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1032
1033 if (clock == 0)
1034 goto out;
1035
85105c53 1036 if (host->version >= SDHCI_SPEC_300) {
c3ed3877
AN		 1037 /*
1038 * Check if the Host Controller supports Programmable Clock
1039 * Mode.
1040 */
1041 if (host->clk_mul) {
1042 u16 ctrl;
1043
1044 /*
1045 * We need to figure out whether the Host Driver needs
1046 * to select Programmable Clock Mode, or the value can
1047 * be set automatically by the Host Controller based on
1048 * the Preset Value registers.
1049 */
1050 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1051 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1052 for (div = 1; div <= 1024; div++) {
1053 if (((host->max_clk * host->clk_mul) /
1054 div) <= clock)
1055 break;
1056 }
1057 /*
1058 * Set Programmable Clock Mode in the Clock
1059 * Control register.
1060 */
1061 clk = SDHCI_PROG_CLOCK_MODE;
1062 div--;
1063 }
1064 } else {
1065 /* Version 3.00 divisors must be a multiple of 2. */
1066 if (host->max_clk <= clock)
1067 div = 1;
1068 else {
1069 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1070 div += 2) {
1071 if ((host->max_clk / div) <= clock)
1072 break;
1073 }
85105c53 1074 }
c3ed3877 1075 div >>= 1;
85105c53
ZG		 1076 }
1077 } else {
1078 /* Version 2.00 divisors must be a power of 2. */
0397526d 1079 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1080 if ((host->max_clk / div) <= clock)
1081 break;
1082 }
c3ed3877 1083 div >>= 1;
d129bceb 1084 }
d129bceb 1085
c3ed3877 1086 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1087 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1088 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1089 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1090 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1091
27f6cb16
CB		 1092 /* Wait max 20 ms */
1093 timeout = 20;
4e4141a5 1094 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1095 & SDHCI_CLOCK_INT_STABLE)) {
1096 if (timeout == 0) {
acf1da45
PO		 1097 printk(KERN_ERR "%s: Internal clock never "
1098 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1099 sdhci_dumpregs(host);
1100 return;
1101 }
7cb2c76f
PO		 1102 timeout--;
1103 mdelay(1);
1104 }
d129bceb
PO		 1105
1106 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1107 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1108
1109out:
1110 host->clock = clock;
1111}
1112
146ad66e
PO		 1113static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1114{
8364248a 1115 u8 pwr = 0;
146ad66e 1116
8364248a 1117 if (power != (unsigned short)-1) {
ae628903
PO		 1118 switch (1 << power) {
1119 case MMC_VDD_165_195:
1120 pwr = SDHCI_POWER_180;
1121 break;
1122 case MMC_VDD_29_30:
1123 case MMC_VDD_30_31:
1124 pwr = SDHCI_POWER_300;
1125 break;
1126 case MMC_VDD_32_33:
1127 case MMC_VDD_33_34:
1128 pwr = SDHCI_POWER_330;
1129 break;
1130 default:
1131 BUG();
1132 }
1133 }
1134
1135 if (host->pwr == pwr)
146ad66e
PO		 1136 return;
1137
ae628903
PO		 1138 host->pwr = pwr;
1139
1140 if (pwr == 0) {
4e4141a5 1141 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ae628903 1142 return;
9e9dc5f2
DS		 1143 }
1144
1145 /*
1146 * Spec says that we should clear the power reg before setting
1147 * a new value. Some controllers don't seem to like this though.
1148 */
b8c86fc5 1149 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1150 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1151
e08c1694 1152 /*
c71f6512 1153 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1154 * and set turn on power at the same time, so set the voltage first.
1155 */
11a2f1b7 1156 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1157 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1158
ae628903 1159 pwr |= SDHCI_POWER_ON;
146ad66e 1160
ae628903 1161 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1162
1163 /*
1164 * Some controllers need an extra 10ms delay of 10ms before they
1165 * can apply clock after applying power
1166 */
11a2f1b7 1167 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1168 mdelay(10);
146ad66e
PO		 1169}
1170
d129bceb
PO		 1171/*****************************************************************************\
1172 * *
1173 * MMC callbacks *
1174 * *
1175\*****************************************************************************/
1176
1177static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1178{
1179 struct sdhci_host *host;
68d1fb7e 1180 bool present;
d129bceb
PO		 1181 unsigned long flags;
1182
1183 host = mmc_priv(mmc);
1184
1185 spin_lock_irqsave(&host->lock, flags);
1186
1187 WARN_ON(host->mrq != NULL);
1188
f9134319 1189#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1190 sdhci_activate_led(host);
2f730fec 1191#endif
c4512f79
JH		 1192 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) {
1193 if (mrq->stop) {
1194 mrq->data->stop = NULL;
1195 mrq->stop = NULL;
1196 }
1197 }
d129bceb
PO		 1198
1199 host->mrq = mrq;
1200
68d1fb7e
AV		 1201 /* If polling, assume that the card is always present. */
1202 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1203 present = true;
1204 else
1205 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1206 SDHCI_CARD_PRESENT;
1207
1208 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1209 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1210 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1211 } else {
1212 u32 present_state;
1213
1214 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1215 /*
1216 * Check if the re-tuning timer has already expired and there
1217 * is no on-going data transfer. If so, we need to execute
1218 * tuning procedure before sending command.
1219 */
1220 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1221 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1222 spin_unlock_irqrestore(&host->lock, flags);
1223 sdhci_execute_tuning(mmc);
1224 spin_lock_irqsave(&host->lock, flags);
1225
1226 /* Restore original mmc_request structure */
1227 host->mrq = mrq;
1228 }
1229
d129bceb 1230 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1231 }
d129bceb 1232
5f25a66f 1233 mmiowb();
d129bceb
PO		 1234 spin_unlock_irqrestore(&host->lock, flags);
1235}
1236
1237static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1238{
1239 struct sdhci_host *host;
1240 unsigned long flags;
1241 u8 ctrl;
1242
1243 host = mmc_priv(mmc);
1244
1245 spin_lock_irqsave(&host->lock, flags);
1246
1e72859e
PO		 1247 if (host->flags & SDHCI_DEVICE_DEAD)
1248 goto out;
1249
d129bceb
PO		 1250 /*
1251 * Reset the chip on each power off.
1252 * Should clear out any weird states.
1253 */
1254 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1255 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1256 sdhci_reinit(host);
d129bceb
PO		 1257 }
1258
1259 sdhci_set_clock(host, ios->clock);
1260
1261 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 1262 sdhci_set_power(host, -1);
d129bceb 1263 else
146ad66e 1264 sdhci_set_power(host, ios->vdd);
d129bceb 1265
643a81ff
PR		 1266 if (host->ops->platform_send_init_74_clocks)
1267 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1268
15ec4461
PR		 1269 /*
1270 * If your platform has 8-bit width support but is not a v3 controller,
1271 * or if it requires special setup code, you should implement that in
1272 * platform_8bit_width().
1273 */
1274 if (host->ops->platform_8bit_width)
1275 host->ops->platform_8bit_width(host, ios->bus_width);
1276 else {
1277 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1278 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1279 ctrl &= ~SDHCI_CTRL_4BITBUS;
1280 if (host->version >= SDHCI_SPEC_300)
1281 ctrl |= SDHCI_CTRL_8BITBUS;
1282 } else {
1283 if (host->version >= SDHCI_SPEC_300)
1284 ctrl &= ~SDHCI_CTRL_8BITBUS;
1285 if (ios->bus_width == MMC_BUS_WIDTH_4)
1286 ctrl |= SDHCI_CTRL_4BITBUS;
1287 else
1288 ctrl &= ~SDHCI_CTRL_4BITBUS;
1289 }
1290 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1291 }
ae6d6c92 1292
15ec4461 1293 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1294
3ab9c8da
PR		 1295 if ((ios->timing == MMC_TIMING_SD_HS ||
1296 ios->timing == MMC_TIMING_MMC_HS)
1297 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1298 ctrl |= SDHCI_CTRL_HISPD;
1299 else
1300 ctrl &= ~SDHCI_CTRL_HISPD;
1301
d6d50a15 1302 if (host->version >= SDHCI_SPEC_300) {
49c468fc
AN		 1303 u16 clk, ctrl_2;
1304 unsigned int clock;
1305
1306 /* In case of UHS-I modes, set High Speed Enable */
1307 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1308 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1309 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1310 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1311 (ios->timing == MMC_TIMING_UHS_SDR12))
1312 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1313
1314 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1315 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1316 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1317 /*
1318 * We only need to set Driver Strength if the
1319 * preset value enable is not set.
1320 */
1321 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1322 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1323 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1324 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1325 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1326
1327 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1328 } else {
1329 /*
1330 * According to SDHC Spec v3.00, if the Preset Value
1331 * Enable in the Host Control 2 register is set, we
1332 * need to reset SD Clock Enable before changing High
1333 * Speed Enable to avoid generating clock gliches.
1334 */
758535c4
AN		 1335
1336 /* Reset SD Clock Enable */
1337 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1338 clk &= ~SDHCI_CLOCK_CARD_EN;
1339 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1340
1341 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1342
1343 /* Re-enable SD Clock */
1344 clock = host->clock;
1345 host->clock = 0;
1346 sdhci_set_clock(host, clock);
d6d50a15 1347 }
49c468fc 1348
49c468fc
AN		 1349
1350 /* Reset SD Clock Enable */
1351 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1352 clk &= ~SDHCI_CLOCK_CARD_EN;
1353 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1354
6322cdd0
PR		 1355 if (host->ops->set_uhs_signaling)
1356 host->ops->set_uhs_signaling(host, ios->timing);
1357 else {
1358 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1359 /* Select Bus Speed Mode for host */
1360 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1361 if (ios->timing == MMC_TIMING_UHS_SDR12)
1362 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1363 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1364 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1365 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1366 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1367 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1368 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1369 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1370 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1371 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1372 }
49c468fc
AN		 1373
1374 /* Re-enable SD Clock */
1375 clock = host->clock;
1376 host->clock = 0;
1377 sdhci_set_clock(host, clock);
758535c4
AN		 1378 } else
1379 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1380
b8352260
LD		 1381 /*
1382 * Some (ENE) controllers go apeshit on some ios operation,
1383 * signalling timeout and CRC errors even on CMD0. Resetting
1384 * it on each ios seems to solve the problem.
1385 */
b8c86fc5 1386 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1387 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1388
1e72859e 1389out:
5f25a66f 1390 mmiowb();
d129bceb
PO		 1391 spin_unlock_irqrestore(&host->lock, flags);
1392}
1393
82b0e23a 1394static int check_ro(struct sdhci_host *host)
d129bceb 1395{
d129bceb 1396 unsigned long flags;
2dfb579c 1397 int is_readonly;
d129bceb 1398
d129bceb
PO		 1399 spin_lock_irqsave(&host->lock, flags);
1400
1e72859e 1401 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1402 is_readonly = 0;
1403 else if (host->ops->get_ro)
1404 is_readonly = host->ops->get_ro(host);
1e72859e 1405 else
2dfb579c
WS		 1406 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1407 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1408
1409 spin_unlock_irqrestore(&host->lock, flags);
1410
2dfb579c
WS		 1411 /* This quirk needs to be replaced by a callback-function later */
1412 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1413 !is_readonly : is_readonly;
d129bceb
PO		 1414}
1415
82b0e23a
TI		 1416#define SAMPLE_COUNT 5
1417
1418static int sdhci_get_ro(struct mmc_host *mmc)
1419{
1420 struct sdhci_host *host;
1421 int i, ro_count;
1422
1423 host = mmc_priv(mmc);
1424
1425 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1426 return check_ro(host);
1427
1428 ro_count = 0;
1429 for (i = 0; i < SAMPLE_COUNT; i++) {
1430 if (check_ro(host)) {
1431 if (++ro_count > SAMPLE_COUNT / 2)
1432 return 1;
1433 }
1434 msleep(30);
1435 }
1436 return 0;
1437}
1438
f75979b7
PO		 1439static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1440{
1441 struct sdhci_host *host;
1442 unsigned long flags;
f75979b7
PO		 1443
1444 host = mmc_priv(mmc);
1445
1446 spin_lock_irqsave(&host->lock, flags);
1447
1e72859e
PO		 1448 if (host->flags & SDHCI_DEVICE_DEAD)
1449 goto out;
1450
f75979b7 1451 if (enable)
7260cf5e
AV		 1452 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1453 else
1454 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1455out:
f75979b7
PO		 1456 mmiowb();
1457
1458 spin_unlock_irqrestore(&host->lock, flags);
1459}
1460
f2119df6
AN		 1461static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1462 struct mmc_ios *ios)
1463{
1464 struct sdhci_host *host;
1465 u8 pwr;
1466 u16 clk, ctrl;
1467 u32 present_state;
1468
1469 host = mmc_priv(mmc);
1470
1471 /*
1472 * Signal Voltage Switching is only applicable for Host Controllers
1473 * v3.00 and above.
1474 */
1475 if (host->version < SDHCI_SPEC_300)
1476 return 0;
1477
1478 /*
1479 * We first check whether the request is to set signalling voltage
1480 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1481 */
1482 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1483 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1484 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1485 ctrl &= ~SDHCI_CTRL_VDD_180;
1486 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1487
1488 /* Wait for 5ms */
1489 usleep_range(5000, 5500);
1490
1491 /* 3.3V regulator output should be stable within 5 ms */
1492 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1493 if (!(ctrl & SDHCI_CTRL_VDD_180))
1494 return 0;
1495 else {
1496 printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V "
1497 "signalling voltage failed\n");
1498 return -EIO;
1499 }
1500 } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1501 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1502 /* Stop SDCLK */
1503 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1504 clk &= ~SDHCI_CLOCK_CARD_EN;
1505 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1506
1507 /* Check whether DAT[3:0] is 0000 */
1508 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1509 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1510 SDHCI_DATA_LVL_SHIFT)) {
1511 /*
1512 * Enable 1.8V Signal Enable in the Host Control2
1513 * register
1514 */
1515 ctrl |= SDHCI_CTRL_VDD_180;
1516 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1517
1518 /* Wait for 5ms */
1519 usleep_range(5000, 5500);
1520
1521 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1522 if (ctrl & SDHCI_CTRL_VDD_180) {
1523 /* Provide SDCLK again and wait for 1ms*/
1524 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1525 clk |= SDHCI_CLOCK_CARD_EN;
1526 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1527 usleep_range(1000, 1500);
1528
1529 /*
1530 * If DAT[3:0] level is 1111b, then the card
1531 * was successfully switched to 1.8V signaling.
1532 */
1533 present_state = sdhci_readl(host,
1534 SDHCI_PRESENT_STATE);
1535 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1536 SDHCI_DATA_LVL_MASK)
1537 return 0;
1538 }
1539 }
1540
1541 /*
1542 * If we are here, that means the switch to 1.8V signaling
1543 * failed. We power cycle the card, and retry initialization
1544 * sequence by setting S18R to 0.
1545 */
1546 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1547 pwr &= ~SDHCI_POWER_ON;
1548 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1549
1550 /* Wait for 1ms as per the spec */
1551 usleep_range(1000, 1500);
1552 pwr |= SDHCI_POWER_ON;
1553 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1554
1555 printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling "
1556 "voltage failed, retrying with S18R set to 0\n");
1557 return -EAGAIN;
1558 } else
1559 /* No signal voltage switch required */
1560 return 0;
1561}
1562
b513ea25
AN		 1563static int sdhci_execute_tuning(struct mmc_host *mmc)
1564{
1565 struct sdhci_host *host;
1566 u16 ctrl;
1567 u32 ier;
1568 int tuning_loop_counter = MAX_TUNING_LOOP;
1569 unsigned long timeout;
1570 int err = 0;
1571
1572 host = mmc_priv(mmc);
1573
1574 disable_irq(host->irq);
1575 spin_lock(&host->lock);
1576
1577 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1578
1579 /*
1580 * Host Controller needs tuning only in case of SDR104 mode
1581 * and for SDR50 mode when Use Tuning for SDR50 is set in
1582 * Capabilities register.
1583 */
1584 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1585 (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1586 (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1587 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1588 else {
1589 spin_unlock(&host->lock);
1590 enable_irq(host->irq);
1591 return 0;
1592 }
1593
1594 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1595
1596 /*
1597 * As per the Host Controller spec v3.00, tuning command
1598 * generates Buffer Read Ready interrupt, so enable that.
1599 *
1600 * Note: The spec clearly says that when tuning sequence
1601 * is being performed, the controller does not generate
1602 * interrupts other than Buffer Read Ready interrupt. But
1603 * to make sure we don't hit a controller bug, we _only_
1604 * enable Buffer Read Ready interrupt here.
1605 */
1606 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1607 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1608
1609 /*
1610 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1611 * of loops reaches 40 times or a timeout of 150ms occurs.
1612 */
1613 timeout = 150;
1614 do {
1615 struct mmc_command cmd = {0};
1616 struct mmc_request mrq = {0};
1617
1618 if (!tuning_loop_counter && !timeout)
1619 break;
1620
1621 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1622 cmd.arg = 0;
1623 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1624 cmd.retries = 0;
1625 cmd.data = NULL;
1626 cmd.error = 0;
1627
1628 mrq.cmd = &cmd;
1629 host->mrq = &mrq;
1630
1631 /*
1632 * In response to CMD19, the card sends 64 bytes of tuning
1633 * block to the Host Controller. So we set the block size
1634 * to 64 here.
1635 */
1636 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1637
1638 /*
1639 * The tuning block is sent by the card to the host controller.
1640 * So we set the TRNS_READ bit in the Transfer Mode register.
1641 * This also takes care of setting DMA Enable and Multi Block
1642 * Select in the same register to 0.
1643 */
1644 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1645
1646 sdhci_send_command(host, &cmd);
1647
1648 host->cmd = NULL;
1649 host->mrq = NULL;
1650
1651 spin_unlock(&host->lock);
1652 enable_irq(host->irq);
1653
1654 /* Wait for Buffer Read Ready interrupt */
1655 wait_event_interruptible_timeout(host->buf_ready_int,
1656 (host->tuning_done == 1),
1657 msecs_to_jiffies(50));
1658 disable_irq(host->irq);
1659 spin_lock(&host->lock);
1660
1661 if (!host->tuning_done) {
1662 printk(KERN_INFO DRIVER_NAME ": Timeout waiting for "
1663 "Buffer Read Ready interrupt during tuning "
1664 "procedure, falling back to fixed sampling "
1665 "clock\n");
1666 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1667 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1668 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1669 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1670
1671 err = -EIO;
1672 goto out;
1673 }
1674
1675 host->tuning_done = 0;
1676
1677 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1678 tuning_loop_counter--;
1679 timeout--;
1680 mdelay(1);
1681 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1682
1683 /*
1684 * The Host Driver has exhausted the maximum number of loops allowed,
1685 * so use fixed sampling frequency.
1686 */
1687 if (!tuning_loop_counter || !timeout) {
1688 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1689 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1690 } else {
1691 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1692 printk(KERN_INFO DRIVER_NAME ": Tuning procedure"
1693 " failed, falling back to fixed sampling"
1694 " clock\n");
1695 err = -EIO;
1696 }
1697 }
1698
1699out:
cf2b5eea
AN		 1700 /*
1701 * If this is the very first time we are here, we start the retuning
1702 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1703 * flag won't be set, we check this condition before actually starting
1704 * the timer.
1705 */
1706 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1707 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1708 mod_timer(&host->tuning_timer, jiffies +
1709 host->tuning_count * HZ);
1710 /* Tuning mode 1 limits the maximum data length to 4MB */
1711 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1712 } else {
1713 host->flags &= ~SDHCI_NEEDS_RETUNING;
1714 /* Reload the new initial value for timer */
1715 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1716 mod_timer(&host->tuning_timer, jiffies +
1717 host->tuning_count * HZ);
1718 }
1719
1720 /*
1721 * In case tuning fails, host controllers which support re-tuning can
1722 * try tuning again at a later time, when the re-tuning timer expires.
1723 * So for these controllers, we return 0. Since there might be other
1724 * controllers who do not have this capability, we return error for
1725 * them.
1726 */
1727 if (err && host->tuning_count &&
1728 host->tuning_mode == SDHCI_TUNING_MODE_1)
1729 err = 0;
1730
b513ea25
AN		 1731 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1732 spin_unlock(&host->lock);
1733 enable_irq(host->irq);
1734
1735 return err;
1736}
1737
4d55c5a1
AN		 1738static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1739{
1740 struct sdhci_host *host;
1741 u16 ctrl;
1742 unsigned long flags;
1743
1744 host = mmc_priv(mmc);
1745
1746 /* Host Controller v3.00 defines preset value registers */
1747 if (host->version < SDHCI_SPEC_300)
1748 return;
1749
1750 spin_lock_irqsave(&host->lock, flags);
1751
1752 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1753
1754 /*
1755 * We only enable or disable Preset Value if they are not already
1756 * enabled or disabled respectively. Otherwise, we bail out.
1757 */
1758 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1759 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1760 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1761 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1762 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1763 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1764 }
1765
1766 spin_unlock_irqrestore(&host->lock, flags);
1767}
1768
ab7aefd0 1769static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1770 .request = sdhci_request,
1771 .set_ios = sdhci_set_ios,
1772 .get_ro = sdhci_get_ro,
f75979b7 1773 .enable_sdio_irq = sdhci_enable_sdio_irq,
f2119df6 1774 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b513ea25 1775 .execute_tuning = sdhci_execute_tuning,
4d55c5a1 1776 .enable_preset_value = sdhci_enable_preset_value,
d129bceb
PO		 1777};
1778
1779/*****************************************************************************\
1780 * *
1781 * Tasklets *
1782 * *
1783\*****************************************************************************/
1784
1785static void sdhci_tasklet_card(unsigned long param)
1786{
1787 struct sdhci_host *host;
1788 unsigned long flags;
1789
1790 host = (struct sdhci_host*)param;
1791
1792 spin_lock_irqsave(&host->lock, flags);
1793
4e4141a5 1794 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
d129bceb
PO		 1795 if (host->mrq) {
1796 printk(KERN_ERR "%s: Card removed during transfer!\n",
1797 mmc_hostname(host->mmc));
1798 printk(KERN_ERR "%s: Resetting controller.\n",
1799 mmc_hostname(host->mmc));
1800
1801 sdhci_reset(host, SDHCI_RESET_CMD);
1802 sdhci_reset(host, SDHCI_RESET_DATA);
1803
17b0429d 1804 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1805 tasklet_schedule(&host->finish_tasklet);
1806 }
1807 }
1808
1809 spin_unlock_irqrestore(&host->lock, flags);
1810
04cf585d 1811 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 1812}
1813
1814static void sdhci_tasklet_finish(unsigned long param)
1815{
1816 struct sdhci_host *host;
1817 unsigned long flags;
1818 struct mmc_request *mrq;
1819
1820 host = (struct sdhci_host*)param;
1821
0c9c99a7
CB		 1822 /*
1823 * If this tasklet gets rescheduled while running, it will
1824 * be run again afterwards but without any active request.
1825 */
1826 if (!host->mrq)
1827 return;
1828
d129bceb
PO		 1829 spin_lock_irqsave(&host->lock, flags);
1830
1831 del_timer(&host->timer);
1832
cf2b5eea
AN		 1833 if (host->version >= SDHCI_SPEC_300)
1834 del_timer(&host->tuning_timer);
1835
d129bceb
PO		 1836 mrq = host->mrq;
1837
d129bceb
PO		 1838 /*
1839 * The controller needs a reset of internal state machines
1840 * upon error conditions.
1841 */
1e72859e 1842 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 1843 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 1844 (mrq->data && (mrq->data->error ||
1845 (mrq->data->stop && mrq->data->stop->error))) ||
1846 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 1847
1848 /* Some controllers need this kick or reset won't work here */
b8c86fc5 1849 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 1850 unsigned int clock;
1851
1852 /* This is to force an update */
1853 clock = host->clock;
1854 host->clock = 0;
1855 sdhci_set_clock(host, clock);
1856 }
1857
1858 /* Spec says we should do both at the same time, but Ricoh
1859 controllers do not like that. */
d129bceb
PO		 1860 sdhci_reset(host, SDHCI_RESET_CMD);
1861 sdhci_reset(host, SDHCI_RESET_DATA);
1862 }
1863
1864 host->mrq = NULL;
1865 host->cmd = NULL;
1866 host->data = NULL;
1867
f9134319 1868#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1869 sdhci_deactivate_led(host);
2f730fec 1870#endif
d129bceb 1871
5f25a66f 1872 mmiowb();
d129bceb
PO		 1873 spin_unlock_irqrestore(&host->lock, flags);
1874
1875 mmc_request_done(host->mmc, mrq);
1876}
1877
1878static void sdhci_timeout_timer(unsigned long data)
1879{
1880 struct sdhci_host *host;
1881 unsigned long flags;
1882
1883 host = (struct sdhci_host*)data;
1884
1885 spin_lock_irqsave(&host->lock, flags);
1886
1887 if (host->mrq) {
acf1da45
PO		 1888 printk(KERN_ERR "%s: Timeout waiting for hardware "
1889 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1890 sdhci_dumpregs(host);
1891
1892 if (host->data) {
17b0429d 1893 host->data->error = -ETIMEDOUT;
d129bceb
PO		 1894 sdhci_finish_data(host);
1895 } else {
1896 if (host->cmd)
17b0429d 1897 host->cmd->error = -ETIMEDOUT;
d129bceb 1898 else
17b0429d 1899 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 1900
1901 tasklet_schedule(&host->finish_tasklet);
1902 }
1903 }
1904
5f25a66f 1905 mmiowb();
d129bceb
PO		 1906 spin_unlock_irqrestore(&host->lock, flags);
1907}
1908
cf2b5eea
AN		 1909static void sdhci_tuning_timer(unsigned long data)
1910{
1911 struct sdhci_host *host;
1912 unsigned long flags;
1913
1914 host = (struct sdhci_host *)data;
1915
1916 spin_lock_irqsave(&host->lock, flags);
1917
1918 host->flags |= SDHCI_NEEDS_RETUNING;
1919
1920 spin_unlock_irqrestore(&host->lock, flags);
1921}
1922
d129bceb
PO		 1923/*****************************************************************************\
1924 * *
1925 * Interrupt handling *
1926 * *
1927\*****************************************************************************/
1928
1929static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1930{
1931 BUG_ON(intmask == 0);
1932
1933 if (!host->cmd) {
b67ac3f3
PO		 1934 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1935 "though no command operation was in progress.\n",
1936 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1937 sdhci_dumpregs(host);
1938 return;
1939 }
1940
43b58b36 1941 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 1942 host->cmd->error = -ETIMEDOUT;
1943 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1944 SDHCI_INT_INDEX))
1945 host->cmd->error = -EILSEQ;
43b58b36 1946
e809517f 1947 if (host->cmd->error) {
d129bceb 1948 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 1949 return;
1950 }
1951
1952 /*
1953 * The host can send and interrupt when the busy state has
1954 * ended, allowing us to wait without wasting CPU cycles.
1955 * Unfortunately this is overloaded on the "data complete"
1956 * interrupt, so we need to take some care when handling
1957 * it.
1958 *
1959 * Note: The 1.0 specification is a bit ambiguous about this
1960 * feature so there might be some problems with older
1961 * controllers.
1962 */
1963 if (host->cmd->flags & MMC_RSP_BUSY) {
1964 if (host->cmd->data)
1965 DBG("Cannot wait for busy signal when also "
1966 "doing a data transfer");
f945405c 1967 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 1968 return;
f945405c
BD		 1969
1970 /* The controller does not support the end-of-busy IRQ,
1971 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 1972 }
1973
1974 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 1975 sdhci_finish_command(host);
d129bceb
PO		 1976}
1977
0957c333 1978#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 1979static void sdhci_show_adma_error(struct sdhci_host *host)
1980{
1981 const char *name = mmc_hostname(host->mmc);
1982 u8 *desc = host->adma_desc;
1983 __le32 *dma;
1984 __le16 *len;
1985 u8 attr;
1986
1987 sdhci_dumpregs(host);
1988
1989 while (true) {
1990 dma = (__le32 *)(desc + 4);
1991 len = (__le16 *)(desc + 2);
1992 attr = *desc;
1993
1994 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1995 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1996
1997 desc += 8;
1998
1999 if (attr & 2)
2000 break;
2001 }
2002}
2003#else
2004static void sdhci_show_adma_error(struct sdhci_host *host) { }
2005#endif
2006
d129bceb
PO		 2007static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2008{
2009 BUG_ON(intmask == 0);
2010
b513ea25
AN		 2011 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2012 if (intmask & SDHCI_INT_DATA_AVAIL) {
2013 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2014 MMC_SEND_TUNING_BLOCK) {
2015 host->tuning_done = 1;
2016 wake_up(&host->buf_ready_int);
2017 return;
2018 }
2019 }
2020
d129bceb
PO		 2021 if (!host->data) {
2022 /*
e809517f
PO		 2023 * The "data complete" interrupt is also used to
2024 * indicate that a busy state has ended. See comment
2025 * above in sdhci_cmd_irq().
d129bceb 2026 */
e809517f
PO		 2027 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2028 if (intmask & SDHCI_INT_DATA_END) {
2029 sdhci_finish_command(host);
2030 return;
2031 }
2032 }
d129bceb 2033
b67ac3f3
PO		 2034 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
2035 "though no data operation was in progress.\n",
2036 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2037 sdhci_dumpregs(host);
2038
2039 return;
2040 }
2041
2042 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2043 host->data->error = -ETIMEDOUT;
22113efd
AL		 2044 else if (intmask & SDHCI_INT_DATA_END_BIT)
2045 host->data->error = -EILSEQ;
2046 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2047 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2048 != MMC_BUS_TEST_R)
17b0429d 2049 host->data->error = -EILSEQ;
6882a8c0
BD		 2050 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2051 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
2052 sdhci_show_adma_error(host);
2134a922 2053 host->data->error = -EIO;
6882a8c0 2054 }
d129bceb 2055
17b0429d 2056 if (host->data->error)
d129bceb
PO		 2057 sdhci_finish_data(host);
2058 else {
a406f5a3 2059 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2060 sdhci_transfer_pio(host);
2061
6ba736a1
PO		 2062 /*
2063 * We currently don't do anything fancy with DMA
2064 * boundaries, but as we can't disable the feature
2065 * we need to at least restart the transfer.
f6a03cbf
MV		 2066 *
2067 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2068 * should return a valid address to continue from, but as
2069 * some controllers are faulty, don't trust them.
6ba736a1 2070 */
f6a03cbf
MV		 2071 if (intmask & SDHCI_INT_DMA_END) {
2072 u32 dmastart, dmanow;
2073 dmastart = sg_dma_address(host->data->sg);
2074 dmanow = dmastart + host->data->bytes_xfered;
2075 /*
2076 * Force update to the next DMA block boundary.
2077 */
2078 dmanow = (dmanow &
2079 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2080 SDHCI_DEFAULT_BOUNDARY_SIZE;
2081 host->data->bytes_xfered = dmanow - dmastart;
2082 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2083 " next 0x%08x\n",
2084 mmc_hostname(host->mmc), dmastart,
2085 host->data->bytes_xfered, dmanow);
2086 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2087 }
6ba736a1 2088
e538fbe8
PO		 2089 if (intmask & SDHCI_INT_DATA_END) {
2090 if (host->cmd) {
2091 /*
2092 * Data managed to finish before the
2093 * command completed. Make sure we do
2094 * things in the proper order.
2095 */
2096 host->data_early = 1;
2097 } else {
2098 sdhci_finish_data(host);
2099 }
2100 }
d129bceb
PO		 2101 }
2102}
2103
7d12e780 2104static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 2105{
2106 irqreturn_t result;
2107 struct sdhci_host* host = dev_id;
2108 u32 intmask;
f75979b7 2109 int cardint = 0;
d129bceb
PO		 2110
2111 spin_lock(&host->lock);
2112
4e4141a5 2113 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 2114
62df67a5 2115 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2116 result = IRQ_NONE;
2117 goto out;
2118 }
2119
b69c9058
PO		 2120 DBG("*** %s got interrupt: 0x%08x\n",
2121 mmc_hostname(host->mmc), intmask);
d129bceb 2122
3192a28f 2123 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
4e4141a5
AV		 2124 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2125 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
d129bceb 2126 tasklet_schedule(&host->card_tasklet);
3192a28f 2127 }
d129bceb 2128
3192a28f 2129 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 2130
3192a28f 2131 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 2132 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2133 SDHCI_INT_STATUS);
3192a28f 2134 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 2135 }
2136
2137 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 2138 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2139 SDHCI_INT_STATUS);
3192a28f 2140 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 2141 }
2142
2143 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2144
964f9ce2
PO		 2145 intmask &= ~SDHCI_INT_ERROR;
2146
d129bceb 2147 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 2148 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 2149 mmc_hostname(host->mmc));
4e4141a5 2150 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 2151 }
2152
9d26a5d3 2153 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 2154
f75979b7
PO		 2155 if (intmask & SDHCI_INT_CARD_INT)
2156 cardint = 1;
2157
2158 intmask &= ~SDHCI_INT_CARD_INT;
2159
3192a28f 2160 if (intmask) {
acf1da45 2161 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 2162 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 2163 sdhci_dumpregs(host);
2164
4e4141a5 2165 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 2166 }
d129bceb
PO		 2167
2168 result = IRQ_HANDLED;
2169
5f25a66f 2170 mmiowb();
d129bceb
PO		 2171out:
2172 spin_unlock(&host->lock);
2173
f75979b7
PO		 2174 /*
2175 * We have to delay this as it calls back into the driver.
2176 */
2177 if (cardint)
2178 mmc_signal_sdio_irq(host->mmc);
2179
d129bceb
PO		 2180 return result;
2181}
2182
2183/*****************************************************************************\
2184 * *
2185 * Suspend/resume *
2186 * *
2187\*****************************************************************************/
2188
2189#ifdef CONFIG_PM
2190
b8c86fc5 2191int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
d129bceb 2192{
b8c86fc5 2193 int ret;
a715dfc7 2194
7260cf5e
AV		 2195 sdhci_disable_card_detection(host);
2196
cf2b5eea
AN		 2197 /* Disable tuning since we are suspending */
2198 if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
2199 host->tuning_mode == SDHCI_TUNING_MODE_1) {
2200 host->flags &= ~SDHCI_NEEDS_RETUNING;
2201 mod_timer(&host->tuning_timer, jiffies +
2202 host->tuning_count * HZ);
2203 }
2204
1a13f8fa 2205 ret = mmc_suspend_host(host->mmc);
b8c86fc5
PO		 2206 if (ret)
2207 return ret;
a715dfc7 2208
b8c86fc5 2209 free_irq(host->irq, host);
d129bceb 2210
9bea3c85
MS		 2211 if (host->vmmc)
2212 ret = regulator_disable(host->vmmc);
2213
2214 return ret;
d129bceb
PO		 2215}
2216
b8c86fc5 2217EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2218
b8c86fc5
PO		 2219int sdhci_resume_host(struct sdhci_host *host)
2220{
2221 int ret;
d129bceb 2222
9bea3c85
MS		 2223 if (host->vmmc) {
2224 int ret = regulator_enable(host->vmmc);
2225 if (ret)
2226 return ret;
2227 }
2228
2229
a13abc7b 2230 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2231 if (host->ops->enable_dma)
2232 host->ops->enable_dma(host);
2233 }
d129bceb 2234
b8c86fc5
PO		 2235 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2236 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 2237 if (ret)
2238 return ret;
d129bceb 2239
2f4cbb3d 2240 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
b8c86fc5
PO		 2241 mmiowb();
2242
2243 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 2244 sdhci_enable_card_detection(host);
2245
cf2b5eea
AN		 2246 /* Set the re-tuning expiration flag */
2247 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2248 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2249 host->flags |= SDHCI_NEEDS_RETUNING;
2250
2f4cbb3d 2251 return ret;
d129bceb
PO		 2252}
2253
b8c86fc5 2254EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb 2255
5f619704
DD		 2256void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2257{
2258 u8 val;
2259 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2260 val |= SDHCI_WAKE_ON_INT;
2261 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2262}
2263
2264EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2265
d129bceb
PO		 2266#endif /* CONFIG_PM */
2267
2268/*****************************************************************************\
2269 * *
b8c86fc5 2270 * Device allocation/registration *
d129bceb
PO		 2271 * *
2272\*****************************************************************************/
2273
b8c86fc5
PO		 2274struct sdhci_host *sdhci_alloc_host(struct device *dev,
2275 size_t priv_size)
d129bceb 2276{
d129bceb
PO		 2277 struct mmc_host *mmc;
2278 struct sdhci_host *host;
2279
b8c86fc5 2280 WARN_ON(dev == NULL);
d129bceb 2281
b8c86fc5 2282 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2283 if (!mmc)
b8c86fc5 2284 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2285
2286 host = mmc_priv(mmc);
2287 host->mmc = mmc;
2288
b8c86fc5
PO		 2289 return host;
2290}
8a4da143 2291
b8c86fc5 2292EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2293
b8c86fc5
PO		 2294int sdhci_add_host(struct sdhci_host *host)
2295{
2296 struct mmc_host *mmc;
f2119df6
AN		 2297 u32 caps[2];
2298 u32 max_current_caps;
2299 unsigned int ocr_avail;
b8c86fc5 2300 int ret;
d129bceb 2301
b8c86fc5
PO		 2302 WARN_ON(host == NULL);
2303 if (host == NULL)
2304 return -EINVAL;
d129bceb 2305
b8c86fc5 2306 mmc = host->mmc;
d129bceb 2307
b8c86fc5
PO		 2308 if (debug_quirks)
2309 host->quirks = debug_quirks;
d129bceb 2310
d96649ed
PO		 2311 sdhci_reset(host, SDHCI_RESET_ALL);
2312
4e4141a5 2313 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2314 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2315 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2316 if (host->version > SDHCI_SPEC_300) {
4a965505 2317 printk(KERN_ERR "%s: Unknown controller version (%d). "
b69c9058 2318 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2319 host->version);
4a965505
PO		 2320 }
2321
f2119df6 2322 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2323 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2324
f2119df6
AN		 2325 caps[1] = (host->version >= SDHCI_SPEC_300) ?
2326 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2327
b8c86fc5 2328 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2329 host->flags |= SDHCI_USE_SDMA;
f2119df6 2330 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2331 DBG("Controller doesn't have SDMA capability\n");
67435274 2332 else
a13abc7b 2333 host->flags |= SDHCI_USE_SDMA;
d129bceb 2334
b8c86fc5 2335 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2336 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2337 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2338 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2339 }
2340
f2119df6
AN		 2341 if ((host->version >= SDHCI_SPEC_200) &&
2342 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2343 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2344
2345 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2346 (host->flags & SDHCI_USE_ADMA)) {
2347 DBG("Disabling ADMA as it is marked broken\n");
2348 host->flags &= ~SDHCI_USE_ADMA;
2349 }
2350
a13abc7b 2351 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2352 if (host->ops->enable_dma) {
2353 if (host->ops->enable_dma(host)) {
2354 printk(KERN_WARNING "%s: No suitable DMA "
2355 "available. Falling back to PIO.\n",
2356 mmc_hostname(mmc));
a13abc7b
RR		 2357 host->flags &=
2358 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2359 }
d129bceb
PO		 2360 }
2361 }
2362
2134a922
PO		 2363 if (host->flags & SDHCI_USE_ADMA) {
2364 /*
2365 * We need to allocate descriptors for all sg entries
2366 * (128) and potentially one alignment transfer for
2367 * each of those entries.
2368 */
2369 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2370 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2371 if (!host->adma_desc || !host->align_buffer) {
2372 kfree(host->adma_desc);
2373 kfree(host->align_buffer);
2374 printk(KERN_WARNING "%s: Unable to allocate ADMA "
2375 "buffers. Falling back to standard DMA.\n",
2376 mmc_hostname(mmc));
2377 host->flags &= ~SDHCI_USE_ADMA;
2378 }
2379 }
2380
7659150c
PO		 2381 /*
2382 * If we use DMA, then it's up to the caller to set the DMA
2383 * mask, but PIO does not need the hw shim so we set a new
2384 * mask here in that case.
2385 */
a13abc7b 2386 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2387 host->dma_mask = DMA_BIT_MASK(64);
2388 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2389 }
d129bceb 2390
c4687d5f 2391 if (host->version >= SDHCI_SPEC_300)
f2119df6 2392 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2393 >> SDHCI_CLOCK_BASE_SHIFT;
2394 else
f2119df6 2395 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2396 >> SDHCI_CLOCK_BASE_SHIFT;
2397
4240ff0a 2398 host->max_clk *= 1000000;
f27f47ef
AV		 2399 if (host->max_clk == 0 || host->quirks &
2400 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a
BD		 2401 if (!host->ops->get_max_clock) {
2402 printk(KERN_ERR
2403 "%s: Hardware doesn't specify base clock "
2404 "frequency.\n", mmc_hostname(mmc));
2405 return -ENODEV;
2406 }
2407 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2408 }
d129bceb 2409
1c8cde92 2410 host->timeout_clk =
f2119df6 2411 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1c8cde92 2412 if (host->timeout_clk == 0) {
81b39802
AV		 2413 if (host->ops->get_timeout_clock) {
2414 host->timeout_clk = host->ops->get_timeout_clock(host);
2415 } else if (!(host->quirks &
2416 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4240ff0a
BD		 2417 printk(KERN_ERR
2418 "%s: Hardware doesn't specify timeout clock "
2419 "frequency.\n", mmc_hostname(mmc));
2420 return -ENODEV;
2421 }
1c8cde92 2422 }
f2119df6 2423 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
1c8cde92 2424 host->timeout_clk *= 1000;
d129bceb 2425
c3ed3877
AN		 2426 /*
2427 * In case of Host Controller v3.00, find out whether clock
2428 * multiplier is supported.
2429 */
2430 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2431 SDHCI_CLOCK_MUL_SHIFT;
2432
2433 /*
2434 * In case the value in Clock Multiplier is 0, then programmable
2435 * clock mode is not supported, otherwise the actual clock
2436 * multiplier is one more than the value of Clock Multiplier
2437 * in the Capabilities Register.
2438 */
2439 if (host->clk_mul)
2440 host->clk_mul += 1;
2441
d129bceb
PO		 2442 /*
2443 * Set host parameters.
2444 */
2445 mmc->ops = &sdhci_ops;
c3ed3877 2446 mmc->f_max = host->max_clk;
ce5f036b 2447 if (host->ops->get_min_clock)
a9e58f25 2448 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2449 else if (host->version >= SDHCI_SPEC_300) {
2450 if (host->clk_mul) {
2451 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2452 mmc->f_max = host->max_clk * host->clk_mul;
2453 } else
2454 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2455 } else
0397526d 2456 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2457
a3c7778f 2458 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE;
5fe23c7f 2459
15ec4461
PR		 2460 /*
2461 * A controller may support 8-bit width, but the board itself
2462 * might not have the pins brought out. Boards that support
2463 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2464 * their platform code before calling sdhci_add_host(), and we
2465 * won't assume 8-bit width for hosts without that CAP.
2466 */
5fe23c7f 2467 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2468 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2469
f2119df6 2470 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2471 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2472
176d1ed4
JC		 2473 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2474 mmc_card_is_removable(mmc))
68d1fb7e
AV		 2475 mmc->caps |= MMC_CAP_NEEDS_POLL;
2476
f2119df6
AN		 2477 /* UHS-I mode(s) supported by the host controller. */
2478 if (host->version >= SDHCI_SPEC_300)
2479 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2480
2481 /* SDR104 supports also implies SDR50 support */
2482 if (caps[1] & SDHCI_SUPPORT_SDR104)
2483 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2484 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2485 mmc->caps |= MMC_CAP_UHS_SDR50;
2486
2487 if (caps[1] & SDHCI_SUPPORT_DDR50)
2488 mmc->caps |= MMC_CAP_UHS_DDR50;
2489
b513ea25
AN		 2490 /* Does the host needs tuning for SDR50? */
2491 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2492 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2493
d6d50a15
AN		 2494 /* Driver Type(s) (A, C, D) supported by the host */
2495 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2496 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2497 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2498 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2499 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2500 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2501
cf2b5eea
AN		 2502 /* Initial value for re-tuning timer count */
2503 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2504 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2505
2506 /*
2507 * In case Re-tuning Timer is not disabled, the actual value of
2508 * re-tuning timer will be 2 ^ (n - 1).
2509 */
2510 if (host->tuning_count)
2511 host->tuning_count = 1 << (host->tuning_count - 1);
2512
2513 /* Re-tuning mode supported by the Host Controller */
2514 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2515 SDHCI_RETUNING_MODE_SHIFT;
2516
8f230f45 2517 ocr_avail = 0;
f2119df6
AN		 2518 /*
2519 * According to SD Host Controller spec v3.00, if the Host System
2520 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2521 * the value is meaningful only if Voltage Support in the Capabilities
2522 * register is set. The actual current value is 4 times the register
2523 * value.
2524 */
2525 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2526
2527 if (caps[0] & SDHCI_CAN_VDD_330) {
2528 int max_current_330;
2529
8f230f45 2530 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6
AN		 2531
2532 max_current_330 = ((max_current_caps &
2533 SDHCI_MAX_CURRENT_330_MASK) >>
2534 SDHCI_MAX_CURRENT_330_SHIFT) *
2535 SDHCI_MAX_CURRENT_MULTIPLIER;
2536
2537 if (max_current_330 > 150)
2538 mmc->caps |= MMC_CAP_SET_XPC_330;
2539 }
2540 if (caps[0] & SDHCI_CAN_VDD_300) {
2541 int max_current_300;
2542
8f230f45 2543 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6
AN		 2544
2545 max_current_300 = ((max_current_caps &
2546 SDHCI_MAX_CURRENT_300_MASK) >>
2547 SDHCI_MAX_CURRENT_300_SHIFT) *
2548 SDHCI_MAX_CURRENT_MULTIPLIER;
2549
2550 if (max_current_300 > 150)
2551 mmc->caps |= MMC_CAP_SET_XPC_300;
2552 }
2553 if (caps[0] & SDHCI_CAN_VDD_180) {
2554 int max_current_180;
2555
8f230f45
TI		 2556 ocr_avail |= MMC_VDD_165_195;
2557
f2119df6
AN		 2558 max_current_180 = ((max_current_caps &
2559 SDHCI_MAX_CURRENT_180_MASK) >>
2560 SDHCI_MAX_CURRENT_180_SHIFT) *
2561 SDHCI_MAX_CURRENT_MULTIPLIER;
2562
2563 if (max_current_180 > 150)
2564 mmc->caps |= MMC_CAP_SET_XPC_180;
5371c927
AN		 2565
2566 /* Maximum current capabilities of the host at 1.8V */
2567 if (max_current_180 >= 800)
2568 mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2569 else if (max_current_180 >= 600)
2570 mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2571 else if (max_current_180 >= 400)
2572 mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2573 else
2574 mmc->caps |= MMC_CAP_MAX_CURRENT_200;
f2119df6
AN		 2575 }
2576
8f230f45
TI		 2577 mmc->ocr_avail = ocr_avail;
2578 mmc->ocr_avail_sdio = ocr_avail;
2579 if (host->ocr_avail_sdio)
2580 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2581 mmc->ocr_avail_sd = ocr_avail;
2582 if (host->ocr_avail_sd)
2583 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2584 else /* normal SD controllers don't support 1.8V */
2585 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2586 mmc->ocr_avail_mmc = ocr_avail;
2587 if (host->ocr_avail_mmc)
2588 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 2589
2590 if (mmc->ocr_avail == 0) {
2591 printk(KERN_ERR "%s: Hardware doesn't report any "
b69c9058 2592 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 2593 return -ENODEV;
146ad66e
PO		 2594 }
2595
d129bceb
PO		 2596 spin_lock_init(&host->lock);
2597
2598 /*
2134a922
PO		 2599 * Maximum number of segments. Depends on if the hardware
2600 * can do scatter/gather or not.
d129bceb 2601 */
2134a922 2602 if (host->flags & SDHCI_USE_ADMA)
a36274e0 2603 mmc->max_segs = 128;
a13abc7b 2604 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 2605 mmc->max_segs = 1;
2134a922 2606 else /* PIO */
a36274e0 2607 mmc->max_segs = 128;
d129bceb
PO		 2608
2609 /*
bab76961 2610 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 2611 * size (512KiB).
d129bceb 2612 */
55db890a 2613 mmc->max_req_size = 524288;
d129bceb
PO		 2614
2615 /*
2616 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 2617 * of bytes. When doing hardware scatter/gather, each entry cannot
2618 * be larger than 64 KiB though.
d129bceb 2619 */
30652aa3
OJ		 2620 if (host->flags & SDHCI_USE_ADMA) {
2621 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2622 mmc->max_seg_size = 65535;
2623 else
2624 mmc->max_seg_size = 65536;
2625 } else {
2134a922 2626 mmc->max_seg_size = mmc->max_req_size;
30652aa3 2627 }
d129bceb 2628
fe4a3c7a
PO		 2629 /*
2630 * Maximum block size. This varies from controller to controller and
2631 * is specified in the capabilities register.
2632 */
0633f654
AV		 2633 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2634 mmc->max_blk_size = 2;
2635 } else {
f2119df6 2636 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 2637 SDHCI_MAX_BLOCK_SHIFT;
2638 if (mmc->max_blk_size >= 3) {
2639 printk(KERN_WARNING "%s: Invalid maximum block size, "
2640 "assuming 512 bytes\n", mmc_hostname(mmc));
2641 mmc->max_blk_size = 0;
2642 }
2643 }
2644
2645 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 2646
55db890a
PO		 2647 /*
2648 * Maximum block count.
2649 */
1388eefd 2650 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 2651
d129bceb
PO		 2652 /*
2653 * Init tasklets.
2654 */
2655 tasklet_init(&host->card_tasklet,
2656 sdhci_tasklet_card, (unsigned long)host);
2657 tasklet_init(&host->finish_tasklet,
2658 sdhci_tasklet_finish, (unsigned long)host);
2659
e4cad1b5 2660 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 2661
cf2b5eea 2662 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 2663 init_waitqueue_head(&host->buf_ready_int);
2664
cf2b5eea
AN		 2665 /* Initialize re-tuning timer */
2666 init_timer(&host->tuning_timer);
2667 host->tuning_timer.data = (unsigned long)host;
2668 host->tuning_timer.function = sdhci_tuning_timer;
2669 }
2670
dace1453 2671 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 2672 mmc_hostname(mmc), host);
d129bceb 2673 if (ret)
8ef1a143 2674 goto untasklet;
d129bceb 2675
9bea3c85
MS		 2676 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2677 if (IS_ERR(host->vmmc)) {
2678 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
2679 host->vmmc = NULL;
2680 } else {
2681 regulator_enable(host->vmmc);
2682 }
2683
2f4cbb3d 2684 sdhci_init(host, 0);
d129bceb
PO		 2685
2686#ifdef CONFIG_MMC_DEBUG
2687 sdhci_dumpregs(host);
2688#endif
2689
f9134319 2690#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 2691 snprintf(host->led_name, sizeof(host->led_name),
2692 "%s::", mmc_hostname(mmc));
2693 host->led.name = host->led_name;
2f730fec
PO		 2694 host->led.brightness = LED_OFF;
2695 host->led.default_trigger = mmc_hostname(mmc);
2696 host->led.brightness_set = sdhci_led_control;
2697
b8c86fc5 2698 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 2699 if (ret)
2700 goto reset;
2701#endif
2702
5f25a66f
PO		 2703 mmiowb();
2704
d129bceb
PO		 2705 mmc_add_host(mmc);
2706
a13abc7b 2707 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 2708 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 2709 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2710 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 2711
7260cf5e
AV		 2712 sdhci_enable_card_detection(host);
2713
d129bceb
PO		 2714 return 0;
2715
f9134319 2716#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2717reset:
2718 sdhci_reset(host, SDHCI_RESET_ALL);
2719 free_irq(host->irq, host);
2720#endif
8ef1a143 2721untasklet:
d129bceb
PO		 2722 tasklet_kill(&host->card_tasklet);
2723 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 2724
2725 return ret;
2726}
2727
b8c86fc5 2728EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 2729
1e72859e 2730void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 2731{
1e72859e
PO		 2732 unsigned long flags;
2733
2734 if (dead) {
2735 spin_lock_irqsave(&host->lock, flags);
2736
2737 host->flags |= SDHCI_DEVICE_DEAD;
2738
2739 if (host->mrq) {
2740 printk(KERN_ERR "%s: Controller removed during "
2741 " transfer!\n", mmc_hostname(host->mmc));
2742
2743 host->mrq->cmd->error = -ENOMEDIUM;
2744 tasklet_schedule(&host->finish_tasklet);
2745 }
2746
2747 spin_unlock_irqrestore(&host->lock, flags);
2748 }
2749
7260cf5e
AV		 2750 sdhci_disable_card_detection(host);
2751
b8c86fc5 2752 mmc_remove_host(host->mmc);
d129bceb 2753
f9134319 2754#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2755 led_classdev_unregister(&host->led);
2756#endif
2757
1e72859e
PO		 2758 if (!dead)
2759 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 2760
2761 free_irq(host->irq, host);
2762
2763 del_timer_sync(&host->timer);
cf2b5eea
AN		 2764 if (host->version >= SDHCI_SPEC_300)
2765 del_timer_sync(&host->tuning_timer);
d129bceb
PO		 2766
2767 tasklet_kill(&host->card_tasklet);
2768 tasklet_kill(&host->finish_tasklet);
2134a922 2769
9bea3c85
MS		 2770 if (host->vmmc) {
2771 regulator_disable(host->vmmc);
2772 regulator_put(host->vmmc);
2773 }
2774
2134a922
PO		 2775 kfree(host->adma_desc);
2776 kfree(host->align_buffer);
2777
2778 host->adma_desc = NULL;
2779 host->align_buffer = NULL;
d129bceb
PO		 2780}
2781
b8c86fc5 2782EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 2783
b8c86fc5 2784void sdhci_free_host(struct sdhci_host *host)
d129bceb 2785{
b8c86fc5 2786 mmc_free_host(host->mmc);
d129bceb
PO		 2787}
2788
b8c86fc5 2789EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 2790
2791/*****************************************************************************\
2792 * *
2793 * Driver init/exit *
2794 * *
2795\*****************************************************************************/
2796
2797static int __init sdhci_drv_init(void)
2798{
2799 printk(KERN_INFO DRIVER_NAME
52fbf9c9 2800 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 2801 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2802
b8c86fc5 2803 return 0;
d129bceb
PO		 2804}
2805
2806static void __exit sdhci_drv_exit(void)
2807{
d129bceb
PO		 2808}
2809
2810module_init(sdhci_drv_init);
2811module_exit(sdhci_drv_exit);
2812
df673b22 2813module_param(debug_quirks, uint, 0444);
67435274 2814
32710e8f 2815MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 2816MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 2817MODULE_LICENSE("GPL");
67435274 2818
df673b22 2819MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
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