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mmc: tmio: Extract bus_width modifications to a separate function
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / tmio_mmc_pio.c
CommitLineData
b6147490
GL		 1/*
2 * linux/drivers/mmc/host/tmio_mmc_pio.c
3 *
4 * Copyright (C) 2011 Guennadi Liakhovetski
5 * Copyright (C) 2007 Ian Molton
6 * Copyright (C) 2004 Ian Molton
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Driver for the MMC / SD / SDIO IP found in:
13 *
14 * TC6393XB, TC6391XB, TC6387XB, T7L66XB, ASIC3, SH-Mobile SoCs
15 *
16 * This driver draws mainly on scattered spec sheets, Reverse engineering
17 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
18 * support). (Further 4 bit support from a later datasheet).
19 *
20 * TODO:
21 * Investigate using a workqueue for PIO transfers
22 * Eliminate FIXMEs
23 * SDIO support
24 * Better Power management
25 * Handle MMC errors better
26 * double buffer support
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <linux/highmem.h>
33#include <linux/interrupt.h>
34#include <linux/io.h>
35#include <linux/irq.h>
36#include <linux/mfd/tmio.h>
37#include <linux/mmc/host.h>
0f506a96 38#include <linux/mmc/mmc.h>
fd0ea65d 39#include <linux/mmc/slot-gpio.h>
cba179ae 40#include <linux/mmc/tmio.h>
b6147490
GL		 41#include <linux/module.h>
42#include <linux/pagemap.h>
43#include <linux/platform_device.h>
c419e611 44#include <linux/pm_qos.h>
e6ee7182 45#include <linux/pm_runtime.h>
619b08d4 46#include <linux/regulator/consumer.h>
b6147490 47#include <linux/scatterlist.h>
b6147490 48#include <linux/spinlock.h>
e3de2be7 49#include <linux/workqueue.h>
b6147490
GL		 50
51#include "tmio_mmc.h"
52
b6147490
GL		 53void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
54{
54680fe7
SH		 55 host->sdcard_irq_mask &= ~(i & TMIO_MASK_IRQ);
56 sd_ctrl_write32(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
b6147490
GL		 57}
58
59void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
60{
54680fe7
SH		 61 host->sdcard_irq_mask |= (i & TMIO_MASK_IRQ);
62 sd_ctrl_write32(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
b6147490
GL		 63}
64
65static void tmio_mmc_ack_mmc_irqs(struct tmio_mmc_host *host, u32 i)
66{
67 sd_ctrl_write32(host, CTL_STATUS, ~i);
68}
69
70static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data)
71{
72 host->sg_len = data->sg_len;
73 host->sg_ptr = data->sg;
74 host->sg_orig = data->sg;
75 host->sg_off = 0;
76}
77
78static int tmio_mmc_next_sg(struct tmio_mmc_host *host)
79{
80 host->sg_ptr = sg_next(host->sg_ptr);
81 host->sg_off = 0;
82 return --host->sg_len;
83}
84
85#ifdef CONFIG_MMC_DEBUG
86
87#define STATUS_TO_TEXT(a, status, i) \
88 do { \
89 if (status & TMIO_STAT_##a) { \
90 if (i++) \
91 printk(" | "); \
92 printk(#a); \
93 } \
94 } while (0)
95
96static void pr_debug_status(u32 status)
97{
98 int i = 0;
a3c76eb9 99 pr_debug("status: %08x = ", status);
b6147490
GL		 100 STATUS_TO_TEXT(CARD_REMOVE, status, i);
101 STATUS_TO_TEXT(CARD_INSERT, status, i);
102 STATUS_TO_TEXT(SIGSTATE, status, i);
103 STATUS_TO_TEXT(WRPROTECT, status, i);
104 STATUS_TO_TEXT(CARD_REMOVE_A, status, i);
105 STATUS_TO_TEXT(CARD_INSERT_A, status, i);
106 STATUS_TO_TEXT(SIGSTATE_A, status, i);
107 STATUS_TO_TEXT(CMD_IDX_ERR, status, i);
108 STATUS_TO_TEXT(STOPBIT_ERR, status, i);
109 STATUS_TO_TEXT(ILL_FUNC, status, i);
110 STATUS_TO_TEXT(CMD_BUSY, status, i);
111 STATUS_TO_TEXT(CMDRESPEND, status, i);
112 STATUS_TO_TEXT(DATAEND, status, i);
113 STATUS_TO_TEXT(CRCFAIL, status, i);
114 STATUS_TO_TEXT(DATATIMEOUT, status, i);
115 STATUS_TO_TEXT(CMDTIMEOUT, status, i);
116 STATUS_TO_TEXT(RXOVERFLOW, status, i);
117 STATUS_TO_TEXT(TXUNDERRUN, status, i);
118 STATUS_TO_TEXT(RXRDY, status, i);
119 STATUS_TO_TEXT(TXRQ, status, i);
120 STATUS_TO_TEXT(ILL_ACCESS, status, i);
121 printk("\n");
122}
123
124#else
125#define pr_debug_status(s) do { } while (0)
126#endif
127
128static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
129{
130 struct tmio_mmc_host *host = mmc_priv(mmc);
131
7501c431
UH		 132 if (enable && !host->sdio_irq_enabled) {
133 /* Keep device active while SDIO irq is enabled */
134 pm_runtime_get_sync(mmc_dev(mmc));
135 host->sdio_irq_enabled = true;
136
54680fe7
SH		 137 host->sdio_irq_mask = TMIO_SDIO_MASK_ALL &
138 ~TMIO_SDIO_STAT_IOIRQ;
b6147490 139 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
54680fe7 140 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
7501c431 141 } else if (!enable && host->sdio_irq_enabled) {
54680fe7
SH		 142 host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
143 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
b6147490 144 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000);
7501c431
UH		 145
146 host->sdio_irq_enabled = false;
0369483e
UH		 147 pm_runtime_mark_last_busy(mmc_dev(mmc));
148 pm_runtime_put_autosuspend(mmc_dev(mmc));
b6147490
GL		 149 }
150}
151
152static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
153{
154 u32 clk = 0, clock;
155
156 if (new_clock) {
157 for (clock = host->mmc->f_min, clk = 0x80000080;
158 new_clock >= (clock<<1); clk >>= 1)
159 clock <<= 1;
160 clk |= 0x100;
161 }
162
163 if (host->set_clk_div)
164 host->set_clk_div(host->pdev, (clk>>22) & 1);
165
166 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
619b08d4 167 msleep(10);
b6147490
GL		 168}
169
170static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
171{
69d1fe18 172 /* implicit BUG_ON(!res) */
5d60e500 173 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
69d1fe18
GL		 174 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
175 msleep(10);
176 }
d9b03421 177
b6147490
GL		 178 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 &
179 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
180 msleep(10);
181}
182
183static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
184{
b6147490
GL		 185 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
186 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
187 msleep(10);
d9b03421 188
69d1fe18 189 /* implicit BUG_ON(!res) */
5d60e500 190 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
69d1fe18
GL		 191 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
192 msleep(10);
193 }
b6147490
GL		 194}
195
196static void tmio_mmc_reset(struct tmio_mmc_host *host)
197{
198 /* FIXME - should we set stop clock reg here */
199 sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
69d1fe18 200 /* implicit BUG_ON(!res) */
5d60e500 201 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG)
69d1fe18 202 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
b6147490
GL		 203 msleep(10);
204 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
5d60e500 205 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG)
69d1fe18 206 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
b6147490
GL		 207 msleep(10);
208}
209
210static void tmio_mmc_reset_work(struct work_struct *work)
211{
212 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
213 delayed_reset_work.work);
214 struct mmc_request *mrq;
215 unsigned long flags;
216
217 spin_lock_irqsave(&host->lock, flags);
218 mrq = host->mrq;
219
df3ef2d3
GL		 220 /*
221 * is request already finished? Since we use a non-blocking
222 * cancel_delayed_work(), it can happen, that a .set_ios() call preempts
223 * us, so, have to check for IS_ERR(host->mrq)
224 */
225 if (IS_ERR_OR_NULL(mrq)
b6147490
GL		 226 || time_is_after_jiffies(host->last_req_ts +
227 msecs_to_jiffies(2000))) {
228 spin_unlock_irqrestore(&host->lock, flags);
229 return;
230 }
231
232 dev_warn(&host->pdev->dev,
233 "timeout waiting for hardware interrupt (CMD%u)\n",
234 mrq->cmd->opcode);
235
236 if (host->data)
237 host->data->error = -ETIMEDOUT;
238 else if (host->cmd)
239 host->cmd->error = -ETIMEDOUT;
240 else
241 mrq->cmd->error = -ETIMEDOUT;
242
243 host->cmd = NULL;
244 host->data = NULL;
b6147490
GL		 245 host->force_pio = false;
246
247 spin_unlock_irqrestore(&host->lock, flags);
248
249 tmio_mmc_reset(host);
250
df3ef2d3
GL		 251 /* Ready for new calls */
252 host->mrq = NULL;
253
e3de2be7 254 tmio_mmc_abort_dma(host);
b6147490 255 mmc_request_done(host->mmc, mrq);
0369483e
UH		 256
257 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
258 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
b6147490
GL		 259}
260
df3ef2d3 261/* called with host->lock held, interrupts disabled */
b6147490
GL		 262static void tmio_mmc_finish_request(struct tmio_mmc_host *host)
263{
b9269fdd
GL		 264 struct mmc_request *mrq;
265 unsigned long flags;
b6147490 266
b9269fdd
GL		 267 spin_lock_irqsave(&host->lock, flags);
268
269 mrq = host->mrq;
270 if (IS_ERR_OR_NULL(mrq)) {
271 spin_unlock_irqrestore(&host->lock, flags);
b6147490 272 return;
b9269fdd 273 }
b6147490 274
b6147490
GL		 275 host->cmd = NULL;
276 host->data = NULL;
277 host->force_pio = false;
278
279 cancel_delayed_work(&host->delayed_reset_work);
280
df3ef2d3 281 host->mrq = NULL;
b9269fdd 282 spin_unlock_irqrestore(&host->lock, flags);
df3ef2d3 283
e3de2be7
GL		 284 if (mrq->cmd->error || (mrq->data && mrq->data->error))
285 tmio_mmc_abort_dma(host);
286
b6147490 287 mmc_request_done(host->mmc, mrq);
0369483e
UH		 288
289 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
290 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
b6147490
GL		 291}
292
b9269fdd
GL		 293static void tmio_mmc_done_work(struct work_struct *work)
294{
295 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
296 done);
297 tmio_mmc_finish_request(host);
298}
299
b6147490
GL		 300/* These are the bitmasks the tmio chip requires to implement the MMC response
301 * types. Note that R1 and R6 are the same in this scheme. */
302#define APP_CMD 0x0040
303#define RESP_NONE 0x0300
304#define RESP_R1 0x0400
305#define RESP_R1B 0x0500
306#define RESP_R2 0x0600
307#define RESP_R3 0x0700
308#define DATA_PRESENT 0x0800
309#define TRANSFER_READ 0x1000
310#define TRANSFER_MULTI 0x2000
311#define SECURITY_CMD 0x4000
312
313static int tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
314{
315 struct mmc_data *data = host->data;
316 int c = cmd->opcode;
e23cd53c 317 u32 irq_mask = TMIO_MASK_CMD;
b6147490 318
0f506a96
GL		 319 /* CMD12 is handled by hardware */
320 if (cmd->opcode == MMC_STOP_TRANSMISSION && !cmd->arg) {
b6147490
GL		 321 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001);
322 return 0;
323 }
324
325 switch (mmc_resp_type(cmd)) {
326 case MMC_RSP_NONE: c |= RESP_NONE; break;
327 case MMC_RSP_R1: c |= RESP_R1; break;
328 case MMC_RSP_R1B: c |= RESP_R1B; break;
329 case MMC_RSP_R2: c |= RESP_R2; break;
330 case MMC_RSP_R3: c |= RESP_R3; break;
331 default:
332 pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
333 return -EINVAL;
334 }
335
336 host->cmd = cmd;
337
338/* FIXME - this seems to be ok commented out but the spec suggest this bit
339 * should be set when issuing app commands.
340 * if(cmd->flags & MMC_FLAG_ACMD)
341 * c |= APP_CMD;
342 */
343 if (data) {
344 c |= DATA_PRESENT;
345 if (data->blocks > 1) {
346 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100);
347 c |= TRANSFER_MULTI;
348 }
349 if (data->flags & MMC_DATA_READ)
350 c |= TRANSFER_READ;
351 }
352
e23cd53c
GL		 353 if (!host->native_hotplug)
354 irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
355 tmio_mmc_enable_mmc_irqs(host, irq_mask);
b6147490
GL		 356
357 /* Fire off the command */
358 sd_ctrl_write32(host, CTL_ARG_REG, cmd->arg);
359 sd_ctrl_write16(host, CTL_SD_CMD, c);
360
361 return 0;
362}
363
364/*
365 * This chip always returns (at least?) as much data as you ask for.
366 * I'm unsure what happens if you ask for less than a block. This should be
25985edc 367 * looked into to ensure that a funny length read doesn't hose the controller.
b6147490
GL		 368 */
369static void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
370{
371 struct mmc_data *data = host->data;
372 void *sg_virt;
373 unsigned short *buf;
374 unsigned int count;
375 unsigned long flags;
376
377 if ((host->chan_tx || host->chan_rx) && !host->force_pio) {
378 pr_err("PIO IRQ in DMA mode!\n");
379 return;
380 } else if (!data) {
381 pr_debug("Spurious PIO IRQ\n");
382 return;
383 }
384
385 sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags);
386 buf = (unsigned short *)(sg_virt + host->sg_off);
387
388 count = host->sg_ptr->length - host->sg_off;
389 if (count > data->blksz)
390 count = data->blksz;
391
392 pr_debug("count: %08x offset: %08x flags %08x\n",
393 count, host->sg_off, data->flags);
394
395 /* Transfer the data */
396 if (data->flags & MMC_DATA_READ)
397 sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
398 else
399 sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
400
401 host->sg_off += count;
402
403 tmio_mmc_kunmap_atomic(host->sg_ptr, &flags, sg_virt);
404
405 if (host->sg_off == host->sg_ptr->length)
406 tmio_mmc_next_sg(host);
407
408 return;
409}
410
411static void tmio_mmc_check_bounce_buffer(struct tmio_mmc_host *host)
412{
413 if (host->sg_ptr == &host->bounce_sg) {
414 unsigned long flags;
415 void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags);
416 memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length);
417 tmio_mmc_kunmap_atomic(host->sg_orig, &flags, sg_vaddr);
418 }
419}
420
421/* needs to be called with host->lock held */
422void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
423{
424 struct mmc_data *data = host->data;
425 struct mmc_command *stop;
426
427 host->data = NULL;
428
429 if (!data) {
430 dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
431 return;
432 }
433 stop = data->stop;
434
435 /* FIXME - return correct transfer count on errors */
436 if (!data->error)
437 data->bytes_xfered = data->blocks * data->blksz;
438 else
439 data->bytes_xfered = 0;
440
441 pr_debug("Completed data request\n");
442
443 /*
444 * FIXME: other drivers allow an optional stop command of any given type
445 * which we dont do, as the chip can auto generate them.
446 * Perhaps we can be smarter about when to use auto CMD12 and
447 * only issue the auto request when we know this is the desired
448 * stop command, allowing fallback to the stop command the
449 * upper layers expect. For now, we do what works.
450 */
451
452 if (data->flags & MMC_DATA_READ) {
453 if (host->chan_rx && !host->force_pio)
454 tmio_mmc_check_bounce_buffer(host);
455 dev_dbg(&host->pdev->dev, "Complete Rx request %p\n",
456 host->mrq);
457 } else {
458 dev_dbg(&host->pdev->dev, "Complete Tx request %p\n",
459 host->mrq);
460 }
461
462 if (stop) {
0f506a96 463 if (stop->opcode == MMC_STOP_TRANSMISSION && !stop->arg)
b6147490
GL		 464 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000);
465 else
466 BUG();
467 }
468
b9269fdd 469 schedule_work(&host->done);
b6147490
GL		 470}
471
472static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
473{
474 struct mmc_data *data;
475 spin_lock(&host->lock);
476 data = host->data;
477
478 if (!data)
479 goto out;
480
481 if (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) {
482 /*
483 * Has all data been written out yet? Testing on SuperH showed,
484 * that in most cases the first interrupt comes already with the
485 * BUSY status bit clear, but on some operations, like mount or
486 * in the beginning of a write / sync / umount, there is one
487 * DATAEND interrupt with the BUSY bit set, in this cases
488 * waiting for one more interrupt fixes the problem.
489 */
490 if (!(sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_CMD_BUSY)) {
491 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
492 tasklet_schedule(&host->dma_complete);
493 }
494 } else if (host->chan_rx && (data->flags & MMC_DATA_READ) && !host->force_pio) {
495 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
496 tasklet_schedule(&host->dma_complete);
497 } else {
498 tmio_mmc_do_data_irq(host);
499 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_READOP | TMIO_MASK_WRITEOP);
500 }
501out:
502 spin_unlock(&host->lock);
503}
504
505static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
506 unsigned int stat)
507{
508 struct mmc_command *cmd = host->cmd;
509 int i, addr;
510
511 spin_lock(&host->lock);
512
513 if (!host->cmd) {
514 pr_debug("Spurious CMD irq\n");
515 goto out;
516 }
517
518 host->cmd = NULL;
519
520 /* This controller is sicker than the PXA one. Not only do we need to
521 * drop the top 8 bits of the first response word, we also need to
522 * modify the order of the response for short response command types.
523 */
524
525 for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
526 cmd->resp[i] = sd_ctrl_read32(host, addr);
527
528 if (cmd->flags & MMC_RSP_136) {
529 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
530 cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
531 cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
532 cmd->resp[3] <<= 8;
533 } else if (cmd->flags & MMC_RSP_R3) {
534 cmd->resp[0] = cmd->resp[3];
535 }
536
537 if (stat & TMIO_STAT_CMDTIMEOUT)
538 cmd->error = -ETIMEDOUT;
539 else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
540 cmd->error = -EILSEQ;
541
542 /* If there is data to handle we enable data IRQs here, and
543 * we will ultimatley finish the request in the data_end handler.
544 * If theres no data or we encountered an error, finish now.
545 */
546 if (host->data && !cmd->error) {
547 if (host->data->flags & MMC_DATA_READ) {
548 if (host->force_pio || !host->chan_rx)
549 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_READOP);
550 else
551 tasklet_schedule(&host->dma_issue);
552 } else {
553 if (host->force_pio || !host->chan_tx)
554 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
555 else
556 tasklet_schedule(&host->dma_issue);
557 }
558 } else {
b9269fdd 559 schedule_work(&host->done);
b6147490
GL		 560 }
561
562out:
563 spin_unlock(&host->lock);
564}
565
7729c7a2
SH		 566static void tmio_mmc_card_irq_status(struct tmio_mmc_host *host,
567 int *ireg, int *status)
b6147490 568{
7729c7a2
SH		 569 *status = sd_ctrl_read32(host, CTL_STATUS);
570 *ireg = *status & TMIO_MASK_IRQ & ~host->sdcard_irq_mask;
b6147490 571
7729c7a2
SH		 572 pr_debug_status(*status);
573 pr_debug_status(*ireg);
574}
b6147490 575
7729c7a2
SH		 576static bool __tmio_mmc_card_detect_irq(struct tmio_mmc_host *host,
577 int ireg, int status)
578{
579 struct mmc_host *mmc = host->mmc;
b6147490 580
e312eb1e
PP		 581 /* Card insert / remove attempts */
582 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
583 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
584 TMIO_STAT_CARD_REMOVE);
71d111cd
GL		 585 if ((((ireg & TMIO_STAT_CARD_REMOVE) && mmc->card) ||
586 ((ireg & TMIO_STAT_CARD_INSERT) && !mmc->card)) &&
587 !work_pending(&mmc->detect.work))
b9269fdd 588 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
7729c7a2 589 return true;
b6147490
GL		 590 }
591
7729c7a2
SH		 592 return false;
593}
594
595irqreturn_t tmio_mmc_card_detect_irq(int irq, void *devid)
596{
597 unsigned int ireg, status;
598 struct tmio_mmc_host *host = devid;
b6147490 599
7729c7a2
SH		 600 tmio_mmc_card_irq_status(host, &ireg, &status);
601 __tmio_mmc_card_detect_irq(host, ireg, status);
602
603 return IRQ_HANDLED;
604}
605EXPORT_SYMBOL(tmio_mmc_card_detect_irq);
606
607static bool __tmio_mmc_sdcard_irq(struct tmio_mmc_host *host,
608 int ireg, int status)
609{
e312eb1e
PP		 610 /* Command completion */
611 if (ireg & (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT)) {
612 tmio_mmc_ack_mmc_irqs(host,
613 TMIO_STAT_CMDRESPEND |
614 TMIO_STAT_CMDTIMEOUT);
615 tmio_mmc_cmd_irq(host, status);
7729c7a2 616 return true;
e312eb1e 617 }
b6147490 618
e312eb1e
PP		 619 /* Data transfer */
620 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
621 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
622 tmio_mmc_pio_irq(host);
7729c7a2 623 return true;
e312eb1e 624 }
b6147490 625
e312eb1e
PP		 626 /* Data transfer completion */
627 if (ireg & TMIO_STAT_DATAEND) {
628 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_DATAEND);
629 tmio_mmc_data_irq(host);
7729c7a2 630 return true;
b6147490 631 }
e312eb1e 632
7729c7a2
SH		 633 return false;
634}
635
636irqreturn_t tmio_mmc_sdcard_irq(int irq, void *devid)
637{
638 unsigned int ireg, status;
639 struct tmio_mmc_host *host = devid;
640
641 tmio_mmc_card_irq_status(host, &ireg, &status);
642 __tmio_mmc_sdcard_irq(host, ireg, status);
643
644 return IRQ_HANDLED;
645}
646EXPORT_SYMBOL(tmio_mmc_sdcard_irq);
647
648irqreturn_t tmio_mmc_sdio_irq(int irq, void *devid)
649{
650 struct tmio_mmc_host *host = devid;
651 struct mmc_host *mmc = host->mmc;
652 struct tmio_mmc_data *pdata = host->pdata;
653 unsigned int ireg, status;
654
655 if (!(pdata->flags & TMIO_MMC_SDIO_IRQ))
656 return IRQ_HANDLED;
657
658 status = sd_ctrl_read16(host, CTL_SDIO_STATUS);
659 ireg = status & TMIO_SDIO_MASK_ALL & ~host->sdcard_irq_mask;
660
661 sd_ctrl_write16(host, CTL_SDIO_STATUS, status & ~TMIO_SDIO_MASK_ALL);
662
663 if (mmc->caps & MMC_CAP_SDIO_IRQ && ireg & TMIO_SDIO_STAT_IOIRQ)
664 mmc_signal_sdio_irq(mmc);
665
666 return IRQ_HANDLED;
667}
668EXPORT_SYMBOL(tmio_mmc_sdio_irq);
669
670irqreturn_t tmio_mmc_irq(int irq, void *devid)
671{
672 struct tmio_mmc_host *host = devid;
673 unsigned int ireg, status;
674
675 pr_debug("MMC IRQ begin\n");
676
677 tmio_mmc_card_irq_status(host, &ireg, &status);
678 if (__tmio_mmc_card_detect_irq(host, ireg, status))
679 return IRQ_HANDLED;
680 if (__tmio_mmc_sdcard_irq(host, ireg, status))
681 return IRQ_HANDLED;
682
683 tmio_mmc_sdio_irq(irq, devid);
b6147490 684
b6147490
GL		 685 return IRQ_HANDLED;
686}
8e7bfdb3 687EXPORT_SYMBOL(tmio_mmc_irq);
b6147490
GL		 688
689static int tmio_mmc_start_data(struct tmio_mmc_host *host,
690 struct mmc_data *data)
691{
692 struct tmio_mmc_data *pdata = host->pdata;
693
694 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
695 data->blksz, data->blocks);
696
697 /* Some hardware cannot perform 2 byte requests in 4 bit mode */
698 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
699 int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES;
700
701 if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) {
702 pr_err("%s: %d byte block unsupported in 4 bit mode\n",
703 mmc_hostname(host->mmc), data->blksz);
704 return -EINVAL;
705 }
706 }
707
708 tmio_mmc_init_sg(host, data);
709 host->data = data;
710
711 /* Set transfer length / blocksize */
712 sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
713 sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
714
715 tmio_mmc_start_dma(host, data);
716
717 return 0;
718}
719
720/* Process requests from the MMC layer */
721static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
722{
723 struct tmio_mmc_host *host = mmc_priv(mmc);
df3ef2d3 724 unsigned long flags;
b6147490
GL		 725 int ret;
726
df3ef2d3
GL		 727 spin_lock_irqsave(&host->lock, flags);
728
729 if (host->mrq) {
b6147490 730 pr_debug("request not null\n");
df3ef2d3
GL		 731 if (IS_ERR(host->mrq)) {
732 spin_unlock_irqrestore(&host->lock, flags);
733 mrq->cmd->error = -EAGAIN;
734 mmc_request_done(mmc, mrq);
735 return;
736 }
737 }
b6147490
GL		 738
739 host->last_req_ts = jiffies;
740 wmb();
741 host->mrq = mrq;
742
df3ef2d3
GL		 743 spin_unlock_irqrestore(&host->lock, flags);
744
0369483e
UH		 745 pm_runtime_get_sync(mmc_dev(mmc));
746
b6147490
GL		 747 if (mrq->data) {
748 ret = tmio_mmc_start_data(host, mrq->data);
749 if (ret)
750 goto fail;
751 }
752
753 ret = tmio_mmc_start_command(host, mrq->cmd);
754 if (!ret) {
755 schedule_delayed_work(&host->delayed_reset_work,
756 msecs_to_jiffies(2000));
757 return;
758 }
759
760fail:
b6147490 761 host->force_pio = false;
df3ef2d3 762 host->mrq = NULL;
b6147490
GL		 763 mrq->cmd->error = ret;
764 mmc_request_done(mmc, mrq);
0369483e
UH		 765
766 pm_runtime_mark_last_busy(mmc_dev(mmc));
767 pm_runtime_put_autosuspend(mmc_dev(mmc));
b6147490
GL		 768}
769
8c102a96
GL		 770static int tmio_mmc_clk_update(struct mmc_host *mmc)
771{
772 struct tmio_mmc_host *host = mmc_priv(mmc);
773 struct tmio_mmc_data *pdata = host->pdata;
774 int ret;
775
776 if (!pdata->clk_enable)
777 return -ENOTSUPP;
778
779 ret = pdata->clk_enable(host->pdev, &mmc->f_max);
780 if (!ret)
781 mmc->f_min = mmc->f_max / 512;
782
783 return ret;
784}
785
619b08d4 786static void tmio_mmc_power_on(struct tmio_mmc_host *host, unsigned short vdd)
b958a67c
GL		 787{
788 struct mmc_host *mmc = host->mmc;
619b08d4
GL		 789 int ret = 0;
790
791 /* .set_ios() is returning void, so, no chance to report an error */
b958a67c 792
9d731e75
CB		 793 if (host->set_pwr)
794 host->set_pwr(host->pdev, 1);
795
619b08d4
GL		 796 if (!IS_ERR(mmc->supply.vmmc)) {
797 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
798 /*
799 * Attention: empiric value. With a b43 WiFi SDIO card this
800 * delay proved necessary for reliable card-insertion probing.
801 * 100us were not enough. Is this the same 140us delay, as in
802 * tmio_mmc_set_ios()?
803 */
804 udelay(200);
805 }
806 /*
807 * It seems, VccQ should be switched on after Vcc, this is also what the
808 * omap_hsmmc.c driver does.
809 */
810 if (!IS_ERR(mmc->supply.vqmmc) && !ret) {
6d1d6b47 811 ret = regulator_enable(mmc->supply.vqmmc);
619b08d4
GL		 812 udelay(200);
813 }
6d1d6b47
GL		 814
815 if (ret < 0)
816 dev_dbg(&host->pdev->dev, "Regulators failed to power up: %d\n",
817 ret);
619b08d4
GL		 818}
819
820static void tmio_mmc_power_off(struct tmio_mmc_host *host)
821{
822 struct mmc_host *mmc = host->mmc;
823
824 if (!IS_ERR(mmc->supply.vqmmc))
825 regulator_disable(mmc->supply.vqmmc);
826
b958a67c 827 if (!IS_ERR(mmc->supply.vmmc))
619b08d4 828 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
9d731e75
CB		 829
830 if (host->set_pwr)
831 host->set_pwr(host->pdev, 0);
b958a67c
GL		 832}
833
9ae4ed7d
UH		 834static void tmio_mmc_set_bus_width(struct tmio_mmc_host *host,
835 unsigned char bus_width)
836{
837 switch (bus_width) {
838 case MMC_BUS_WIDTH_1:
839 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0);
840 break;
841 case MMC_BUS_WIDTH_4:
842 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x00e0);
843 break;
844 }
845}
846
b6147490
GL		 847/* Set MMC clock / power.
848 * Note: This controller uses a simple divider scheme therefore it cannot
849 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
850 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
851 * slowest setting.
852 */
853static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
854{
855 struct tmio_mmc_host *host = mmc_priv(mmc);
4932bd64 856 struct device *dev = &host->pdev->dev;
df3ef2d3
GL		 857 unsigned long flags;
858
0369483e
UH		 859 pm_runtime_get_sync(mmc_dev(mmc));
860
b9269fdd
GL		 861 mutex_lock(&host->ios_lock);
862
df3ef2d3
GL		 863 spin_lock_irqsave(&host->lock, flags);
864 if (host->mrq) {
865 if (IS_ERR(host->mrq)) {
4932bd64 866 dev_dbg(dev,
df3ef2d3
GL		 867 "%s.%d: concurrent .set_ios(), clk %u, mode %u\n",
868 current->comm, task_pid_nr(current),
869 ios->clock, ios->power_mode);
870 host->mrq = ERR_PTR(-EINTR);
871 } else {
4932bd64 872 dev_dbg(dev,
df3ef2d3
GL		 873 "%s.%d: CMD%u active since %lu, now %lu!\n",
874 current->comm, task_pid_nr(current),
875 host->mrq->cmd->opcode, host->last_req_ts, jiffies);
876 }
877 spin_unlock_irqrestore(&host->lock, flags);
b9269fdd
GL		 878
879 mutex_unlock(&host->ios_lock);
df3ef2d3
GL		 880 return;
881 }
882
883 host->mrq = ERR_PTR(-EBUSY);
884
885 spin_unlock_irqrestore(&host->lock, flags);
b6147490 886
71d111cd 887 /*
c391e1b9 888 * host->power toggles between false and true in both cases - either
c8be24c2
GL		 889 * or not the controller can be runtime-suspended during inactivity.
890 * But if the controller has to be kept on, the runtime-pm usage_count
891 * is kept positive, so no suspending actually takes place.
71d111cd
GL		 892 */
893 if (ios->power_mode == MMC_POWER_ON && ios->clock) {
e83b7a8a 894 if (host->power != TMIO_MMC_ON_RUN) {
8c102a96 895 tmio_mmc_clk_update(mmc);
b22ffdcd
GL		 896 if (host->resuming) {
897 tmio_mmc_reset(host);
898 host->resuming = false;
899 }
7311bef0 900 }
b9ec2744
GL		 901 if (host->power == TMIO_MMC_OFF_STOP)
902 tmio_mmc_reset(host);
71d111cd 903 tmio_mmc_set_clock(host, ios->clock);
e83b7a8a 904 if (host->power == TMIO_MMC_OFF_STOP)
619b08d4
GL		 905 /* power up SD card and the bus */
906 tmio_mmc_power_on(host, ios->vdd);
e83b7a8a 907 host->power = TMIO_MMC_ON_RUN;
5fd01579
GL		 908 /* start bus clock */
909 tmio_mmc_clk_start(host);
71d111cd 910 } else if (ios->power_mode != MMC_POWER_UP) {
e83b7a8a
GL		 911 struct tmio_mmc_data *pdata = host->pdata;
912 unsigned int old_power = host->power;
913
914 if (old_power != TMIO_MMC_OFF_STOP) {
915 if (ios->power_mode == MMC_POWER_OFF) {
619b08d4 916 tmio_mmc_power_off(host);
e83b7a8a
GL		 917 host->power = TMIO_MMC_OFF_STOP;
918 } else {
919 host->power = TMIO_MMC_ON_STOP;
920 }
921 }
922
923 if (old_power == TMIO_MMC_ON_RUN) {
6de707f2 924 tmio_mmc_clk_stop(host);
8c102a96
GL		 925 if (pdata->clk_disable)
926 pdata->clk_disable(host->pdev);
71d111cd 927 }
b6147490
GL		 928 }
929
9ae4ed7d
UH		 930 if (host->power != TMIO_MMC_OFF_STOP)
931 tmio_mmc_set_bus_width(host, ios->bus_width);
b6147490
GL		 932
933 /* Let things settle. delay taken from winCE driver */
934 udelay(140);
df3ef2d3
GL		 935 if (PTR_ERR(host->mrq) == -EINTR)
936 dev_dbg(&host->pdev->dev,
937 "%s.%d: IOS interrupted: clk %u, mode %u",
938 current->comm, task_pid_nr(current),
939 ios->clock, ios->power_mode);
940 host->mrq = NULL;
b9269fdd
GL		 941
942 mutex_unlock(&host->ios_lock);
0369483e
UH		 943
944 pm_runtime_mark_last_busy(mmc_dev(mmc));
945 pm_runtime_put_autosuspend(mmc_dev(mmc));
b6147490
GL		 946}
947
948static int tmio_mmc_get_ro(struct mmc_host *mmc)
949{
950 struct tmio_mmc_host *host = mmc_priv(mmc);
951 struct tmio_mmc_data *pdata = host->pdata;
3071cafb
GL		 952 int ret = mmc_gpio_get_ro(mmc);
953 if (ret >= 0)
954 return ret;
b6147490 955
0369483e
UH		 956 pm_runtime_get_sync(mmc_dev(mmc));
957 ret = !((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
958 (sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT));
959 pm_runtime_mark_last_busy(mmc_dev(mmc));
960 pm_runtime_put_autosuspend(mmc_dev(mmc));
961
962 return ret;
b6147490
GL		 963}
964
b6147490
GL		 965static const struct mmc_host_ops tmio_mmc_ops = {
966 .request = tmio_mmc_request,
967 .set_ios = tmio_mmc_set_ios,
968 .get_ro = tmio_mmc_get_ro,
2b63b341 969 .get_cd = mmc_gpio_get_cd,
b6147490
GL		 970 .enable_sdio_irq = tmio_mmc_enable_sdio_irq,
971};
972
05fae4a7 973static int tmio_mmc_init_ocr(struct tmio_mmc_host *host)
b958a67c
GL		 974{
975 struct tmio_mmc_data *pdata = host->pdata;
976 struct mmc_host *mmc = host->mmc;
977
978 mmc_regulator_get_supply(mmc);
979
05fae4a7 980 /* use ocr_mask if no regulator */
b958a67c 981 if (!mmc->ocr_avail)
05fae4a7
KM		 982 mmc->ocr_avail = pdata->ocr_mask;
983
984 /*
985 * try again.
986 * There is possibility that regulator has not been probed
987 */
988 if (!mmc->ocr_avail)
989 return -EPROBE_DEFER;
990
991 return 0;
b958a67c
GL		 992}
993
5a00a971
GL		 994static void tmio_mmc_of_parse(struct platform_device *pdev,
995 struct tmio_mmc_data *pdata)
996{
997 const struct device_node *np = pdev->dev.of_node;
998 if (!np)
999 return;
1000
1001 if (of_get_property(np, "toshiba,mmc-wrprotect-disable", NULL))
1002 pdata->flags |= TMIO_MMC_WRPROTECT_DISABLE;
1003}
1004
c3be1efd 1005int tmio_mmc_host_probe(struct tmio_mmc_host **host,
b6147490
GL		 1006 struct platform_device *pdev,
1007 struct tmio_mmc_data *pdata)
1008{
1009 struct tmio_mmc_host *_host;
1010 struct mmc_host *mmc;
1011 struct resource *res_ctl;
1012 int ret;
1013 u32 irq_mask = TMIO_MASK_CMD;
1014
5a00a971
GL		 1015 tmio_mmc_of_parse(pdev, pdata);
1016
7b952137
GL		 1017 if (!(pdata->flags & TMIO_MMC_HAS_IDLE_WAIT))
1018 pdata->write16_hook = NULL;
1019
b6147490
GL		 1020 res_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1021 if (!res_ctl)
1022 return -EINVAL;
1023
1024 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &pdev->dev);
1025 if (!mmc)
1026 return -ENOMEM;
1027
274a752b
SB		 1028 ret = mmc_of_parse(mmc);
1029 if (ret < 0)
1030 goto host_free;
5a00a971 1031
7311bef0 1032 pdata->dev = &pdev->dev;
b6147490
GL		 1033 _host = mmc_priv(mmc);
1034 _host->pdata = pdata;
1035 _host->mmc = mmc;
1036 _host->pdev = pdev;
1037 platform_set_drvdata(pdev, mmc);
1038
9d731e75 1039 _host->set_pwr = pdata->set_pwr;
b6147490
GL		 1040 _host->set_clk_div = pdata->set_clk_div;
1041
05fae4a7
KM		 1042 ret = tmio_mmc_init_ocr(_host);
1043 if (ret < 0)
1044 goto host_free;
1045
b6147490
GL		 1046 _host->ctl = ioremap(res_ctl->start, resource_size(res_ctl));
1047 if (!_host->ctl) {
1048 ret = -ENOMEM;
1049 goto host_free;
1050 }
1051
1052 mmc->ops = &tmio_mmc_ops;
5a00a971 1053 mmc->caps |= MMC_CAP_4_BIT_DATA | pdata->capabilities;
dd006b30 1054 mmc->caps2 |= pdata->capabilities2;
b6147490
GL		 1055 mmc->max_segs = 32;
1056 mmc->max_blk_size = 512;
1057 mmc->max_blk_count = (PAGE_CACHE_SIZE / mmc->max_blk_size) *
1058 mmc->max_segs;
1059 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1060 mmc->max_seg_size = mmc->max_req_size;
b6147490 1061
c8be24c2 1062 _host->native_hotplug = !(pdata->flags & TMIO_MMC_USE_GPIO_CD ||
2b1ac5c2 1063 mmc->caps & MMC_CAP_NEEDS_POLL ||
5a00a971
GL		 1064 mmc->caps & MMC_CAP_NONREMOVABLE ||
1065 mmc->slot.cd_irq >= 0);
2b1ac5c2 1066
e83b7a8a 1067 _host->power = TMIO_MMC_OFF_STOP;
8c102a96
GL		 1068 if (tmio_mmc_clk_update(mmc) < 0) {
1069 mmc->f_max = pdata->hclk;
1070 mmc->f_min = mmc->f_max / 512;
1071 }
1072
cbb18b30 1073 /*
0369483e
UH		 1074 * While using internal tmio hardware logic for card detection, we need
1075 * to ensure it stays powered for it to work.
cbb18b30 1076 */
2b1ac5c2 1077 if (_host->native_hotplug)
cbb18b30
BH		 1078 pm_runtime_get_noresume(&pdev->dev);
1079
b6147490
GL		 1080 tmio_mmc_clk_stop(_host);
1081 tmio_mmc_reset(_host);
1082
54680fe7 1083 _host->sdcard_irq_mask = sd_ctrl_read32(_host, CTL_IRQ_MASK);
b6147490 1084 tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL);
e0337cc8
GL		 1085
1086 /* Unmask the IRQs we want to know about */
1087 if (!_host->chan_rx)
1088 irq_mask |= TMIO_MASK_READOP;
1089 if (!_host->chan_tx)
1090 irq_mask |= TMIO_MASK_WRITEOP;
1091 if (!_host->native_hotplug)
1092 irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
1093
1094 _host->sdcard_irq_mask &= ~irq_mask;
1095
7501c431
UH		 1096 _host->sdio_irq_enabled = false;
1097 if (pdata->flags & TMIO_MMC_SDIO_IRQ) {
1098 _host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
1099 sd_ctrl_write16(_host, CTL_SDIO_IRQ_MASK, _host->sdio_irq_mask);
1100 sd_ctrl_write16(_host, CTL_TRANSACTION_CTL, 0x0000);
1101 }
b6147490 1102
b6147490 1103 spin_lock_init(&_host->lock);
b9269fdd 1104 mutex_init(&_host->ios_lock);
b6147490
GL		 1105
1106 /* Init delayed work for request timeouts */
1107 INIT_DELAYED_WORK(&_host->delayed_reset_work, tmio_mmc_reset_work);
b9269fdd 1108 INIT_WORK(&_host->done, tmio_mmc_done_work);
b6147490
GL		 1109
1110 /* See if we also get DMA */
1111 tmio_mmc_request_dma(_host, pdata);
1112
0369483e
UH		 1113 pm_runtime_set_active(&pdev->dev);
1114 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1115 pm_runtime_use_autosuspend(&pdev->dev);
1116 pm_runtime_enable(&pdev->dev);
1117
8c102a96
GL		 1118 ret = mmc_add_host(mmc);
1119 if (pdata->clk_disable)
1120 pdata->clk_disable(pdev);
1121 if (ret < 0) {
1122 tmio_mmc_host_remove(_host);
1123 return ret;
1124 }
b6147490 1125
c419e611
RW		 1126 dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1127
c8be24c2 1128 if (pdata->flags & TMIO_MMC_USE_GPIO_CD) {
214fc309 1129 ret = mmc_gpio_request_cd(mmc, pdata->cd_gpio, 0);
c8be24c2
GL		 1130 if (ret < 0) {
1131 tmio_mmc_host_remove(_host);
1132 return ret;
1133 }
1134 }
1135
b6147490
GL		 1136 *host = _host;
1137
1138 return 0;
1139
b6147490
GL		 1140host_free:
1141 mmc_free_host(mmc);
1142
1143 return ret;
1144}
1145EXPORT_SYMBOL(tmio_mmc_host_probe);
1146
1147void tmio_mmc_host_remove(struct tmio_mmc_host *host)
1148{
e6ee7182 1149 struct platform_device *pdev = host->pdev;
c8be24c2
GL		 1150 struct mmc_host *mmc = host->mmc;
1151
2b1ac5c2 1152 if (!host->native_hotplug)
7311bef0
GL		 1153 pm_runtime_get_sync(&pdev->dev);
1154
c419e611
RW		 1155 dev_pm_qos_hide_latency_limit(&pdev->dev);
1156
c8be24c2 1157 mmc_remove_host(mmc);
b9269fdd 1158 cancel_work_sync(&host->done);
b6147490
GL		 1159 cancel_delayed_work_sync(&host->delayed_reset_work);
1160 tmio_mmc_release_dma(host);
e6ee7182 1161
e6ee7182
GL		 1162 pm_runtime_put_sync(&pdev->dev);
1163 pm_runtime_disable(&pdev->dev);
7311bef0
GL		 1164
1165 iounmap(host->ctl);
c8be24c2 1166 mmc_free_host(mmc);
b6147490
GL		 1167}
1168EXPORT_SYMBOL(tmio_mmc_host_remove);
1169
710dec95 1170#ifdef CONFIG_PM_SLEEP
e6ee7182
GL		 1171int tmio_mmc_host_suspend(struct device *dev)
1172{
1173 struct mmc_host *mmc = dev_get_drvdata(dev);
1174 struct tmio_mmc_host *host = mmc_priv(mmc);
e6ee7182 1175
d62c9577
UH		 1176 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL);
1177 return 0;
e6ee7182
GL		 1178}
1179EXPORT_SYMBOL(tmio_mmc_host_suspend);
1180
1181int tmio_mmc_host_resume(struct device *dev)
1182{
1183 struct mmc_host *mmc = dev_get_drvdata(dev);
1184 struct tmio_mmc_host *host = mmc_priv(mmc);
1185
c8be24c2 1186 tmio_mmc_enable_dma(host, true);
e6ee7182 1187
c8be24c2 1188 /* The MMC core will perform the complete set up */
b22ffdcd 1189 host->resuming = true;
d62c9577 1190 return 0;
e6ee7182
GL		 1191}
1192EXPORT_SYMBOL(tmio_mmc_host_resume);
710dec95 1193#endif
e6ee7182 1194
710dec95 1195#ifdef CONFIG_PM_RUNTIME
7311bef0
GL		 1196int tmio_mmc_host_runtime_suspend(struct device *dev)
1197{
1198 return 0;
1199}
1200EXPORT_SYMBOL(tmio_mmc_host_runtime_suspend);
1201
1202int tmio_mmc_host_runtime_resume(struct device *dev)
1203{
1204 struct mmc_host *mmc = dev_get_drvdata(dev);
1205 struct tmio_mmc_host *host = mmc_priv(mmc);
7311bef0 1206
162f43e3 1207 tmio_mmc_enable_dma(host, true);
7311bef0 1208
7311bef0
GL		 1209 return 0;
1210}
1211EXPORT_SYMBOL(tmio_mmc_host_runtime_resume);
710dec95 1212#endif
7311bef0 1213
b6147490 1214MODULE_LICENSE("GPL v2");
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