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mmc: use .multi_io_quirk on omap_hsmmc
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / tmio_mmc_pio.c
CommitLineData
b6147490
GL		 1/*
2 * linux/drivers/mmc/host/tmio_mmc_pio.c
3 *
4 * Copyright (C) 2011 Guennadi Liakhovetski
5 * Copyright (C) 2007 Ian Molton
6 * Copyright (C) 2004 Ian Molton
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Driver for the MMC / SD / SDIO IP found in:
13 *
14 * TC6393XB, TC6391XB, TC6387XB, T7L66XB, ASIC3, SH-Mobile SoCs
15 *
16 * This driver draws mainly on scattered spec sheets, Reverse engineering
17 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
18 * support). (Further 4 bit support from a later datasheet).
19 *
20 * TODO:
21 * Investigate using a workqueue for PIO transfers
22 * Eliminate FIXMEs
23 * SDIO support
24 * Better Power management
25 * Handle MMC errors better
26 * double buffer support
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <linux/highmem.h>
33#include <linux/interrupt.h>
34#include <linux/io.h>
35#include <linux/irq.h>
36#include <linux/mfd/tmio.h>
37#include <linux/mmc/host.h>
0f506a96 38#include <linux/mmc/mmc.h>
fd0ea65d 39#include <linux/mmc/slot-gpio.h>
cba179ae 40#include <linux/mmc/tmio.h>
b6147490
GL		 41#include <linux/module.h>
42#include <linux/pagemap.h>
43#include <linux/platform_device.h>
c419e611 44#include <linux/pm_qos.h>
e6ee7182 45#include <linux/pm_runtime.h>
619b08d4 46#include <linux/regulator/consumer.h>
b8d11962 47#include <linux/mmc/sdio.h>
b6147490 48#include <linux/scatterlist.h>
b6147490 49#include <linux/spinlock.h>
e3de2be7 50#include <linux/workqueue.h>
b6147490
GL		 51
52#include "tmio_mmc.h"
53
b6147490
GL		 54void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
55{
54680fe7
SH		 56 host->sdcard_irq_mask &= ~(i & TMIO_MASK_IRQ);
57 sd_ctrl_write32(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
b6147490
GL		 58}
59
60void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
61{
54680fe7
SH		 62 host->sdcard_irq_mask |= (i & TMIO_MASK_IRQ);
63 sd_ctrl_write32(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
b6147490
GL		 64}
65
66static void tmio_mmc_ack_mmc_irqs(struct tmio_mmc_host *host, u32 i)
67{
68 sd_ctrl_write32(host, CTL_STATUS, ~i);
69}
70
71static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data)
72{
73 host->sg_len = data->sg_len;
74 host->sg_ptr = data->sg;
75 host->sg_orig = data->sg;
76 host->sg_off = 0;
77}
78
79static int tmio_mmc_next_sg(struct tmio_mmc_host *host)
80{
81 host->sg_ptr = sg_next(host->sg_ptr);
82 host->sg_off = 0;
83 return --host->sg_len;
84}
85
86#ifdef CONFIG_MMC_DEBUG
87
88#define STATUS_TO_TEXT(a, status, i) \
89 do { \
90 if (status & TMIO_STAT_##a) { \
91 if (i++) \
92 printk(" | "); \
93 printk(#a); \
94 } \
95 } while (0)
96
97static void pr_debug_status(u32 status)
98{
99 int i = 0;
a3c76eb9 100 pr_debug("status: %08x = ", status);
b6147490
GL		 101 STATUS_TO_TEXT(CARD_REMOVE, status, i);
102 STATUS_TO_TEXT(CARD_INSERT, status, i);
103 STATUS_TO_TEXT(SIGSTATE, status, i);
104 STATUS_TO_TEXT(WRPROTECT, status, i);
105 STATUS_TO_TEXT(CARD_REMOVE_A, status, i);
106 STATUS_TO_TEXT(CARD_INSERT_A, status, i);
107 STATUS_TO_TEXT(SIGSTATE_A, status, i);
108 STATUS_TO_TEXT(CMD_IDX_ERR, status, i);
109 STATUS_TO_TEXT(STOPBIT_ERR, status, i);
110 STATUS_TO_TEXT(ILL_FUNC, status, i);
111 STATUS_TO_TEXT(CMD_BUSY, status, i);
112 STATUS_TO_TEXT(CMDRESPEND, status, i);
113 STATUS_TO_TEXT(DATAEND, status, i);
114 STATUS_TO_TEXT(CRCFAIL, status, i);
115 STATUS_TO_TEXT(DATATIMEOUT, status, i);
116 STATUS_TO_TEXT(CMDTIMEOUT, status, i);
117 STATUS_TO_TEXT(RXOVERFLOW, status, i);
118 STATUS_TO_TEXT(TXUNDERRUN, status, i);
119 STATUS_TO_TEXT(RXRDY, status, i);
120 STATUS_TO_TEXT(TXRQ, status, i);
121 STATUS_TO_TEXT(ILL_ACCESS, status, i);
122 printk("\n");
123}
124
125#else
126#define pr_debug_status(s) do { } while (0)
127#endif
128
129static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
130{
131 struct tmio_mmc_host *host = mmc_priv(mmc);
132
7501c431
UH		 133 if (enable && !host->sdio_irq_enabled) {
134 /* Keep device active while SDIO irq is enabled */
135 pm_runtime_get_sync(mmc_dev(mmc));
136 host->sdio_irq_enabled = true;
137
54680fe7
SH		 138 host->sdio_irq_mask = TMIO_SDIO_MASK_ALL &
139 ~TMIO_SDIO_STAT_IOIRQ;
b6147490 140 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
54680fe7 141 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
7501c431 142 } else if (!enable && host->sdio_irq_enabled) {
54680fe7
SH		 143 host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
144 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
b6147490 145 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000);
7501c431
UH		 146
147 host->sdio_irq_enabled = false;
0369483e
UH		 148 pm_runtime_mark_last_busy(mmc_dev(mmc));
149 pm_runtime_put_autosuspend(mmc_dev(mmc));
b6147490
GL		 150 }
151}
152
ae12d250
UH		 153static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
154 unsigned int new_clock)
b6147490
GL		 155{
156 u32 clk = 0, clock;
157
158 if (new_clock) {
159 for (clock = host->mmc->f_min, clk = 0x80000080;
160 new_clock >= (clock<<1); clk >>= 1)
161 clock <<= 1;
da29fe2b
SU		 162
163 /* 1/1 clock is option */
164 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) &&
165 ((clk >> 22) & 0x1))
166 clk |= 0xff;
b6147490
GL		 167 }
168
169 if (host->set_clk_div)
170 host->set_clk_div(host->pdev, (clk>>22) & 1);
171
172 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
619b08d4 173 msleep(10);
b6147490
GL		 174}
175
176static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
177{
69d1fe18 178 /* implicit BUG_ON(!res) */
5d60e500 179 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
69d1fe18
GL		 180 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
181 msleep(10);
182 }
d9b03421 183
b6147490
GL		 184 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 &
185 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
186 msleep(10);
187}
188
189static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
190{
b6147490
GL		 191 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
192 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
193 msleep(10);
d9b03421 194
69d1fe18 195 /* implicit BUG_ON(!res) */
5d60e500 196 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
69d1fe18
GL		 197 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
198 msleep(10);
199 }
b6147490
GL		 200}
201
202static void tmio_mmc_reset(struct tmio_mmc_host *host)
203{
204 /* FIXME - should we set stop clock reg here */
205 sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
69d1fe18 206 /* implicit BUG_ON(!res) */
5d60e500 207 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG)
69d1fe18 208 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
b6147490
GL		 209 msleep(10);
210 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
5d60e500 211 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG)
69d1fe18 212 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
b6147490
GL		 213 msleep(10);
214}
215
216static void tmio_mmc_reset_work(struct work_struct *work)
217{
218 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
219 delayed_reset_work.work);
220 struct mmc_request *mrq;
221 unsigned long flags;
222
223 spin_lock_irqsave(&host->lock, flags);
224 mrq = host->mrq;
225
df3ef2d3
GL		 226 /*
227 * is request already finished? Since we use a non-blocking
228 * cancel_delayed_work(), it can happen, that a .set_ios() call preempts
229 * us, so, have to check for IS_ERR(host->mrq)
230 */
231 if (IS_ERR_OR_NULL(mrq)
b6147490
GL		 232 || time_is_after_jiffies(host->last_req_ts +
233 msecs_to_jiffies(2000))) {
234 spin_unlock_irqrestore(&host->lock, flags);
235 return;
236 }
237
238 dev_warn(&host->pdev->dev,
239 "timeout waiting for hardware interrupt (CMD%u)\n",
240 mrq->cmd->opcode);
241
242 if (host->data)
243 host->data->error = -ETIMEDOUT;
244 else if (host->cmd)
245 host->cmd->error = -ETIMEDOUT;
246 else
247 mrq->cmd->error = -ETIMEDOUT;
248
249 host->cmd = NULL;
250 host->data = NULL;
b6147490
GL		 251 host->force_pio = false;
252
253 spin_unlock_irqrestore(&host->lock, flags);
254
255 tmio_mmc_reset(host);
256
df3ef2d3
GL		 257 /* Ready for new calls */
258 host->mrq = NULL;
259
e3de2be7 260 tmio_mmc_abort_dma(host);
b6147490 261 mmc_request_done(host->mmc, mrq);
0369483e
UH		 262
263 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
264 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
b6147490
GL		 265}
266
df3ef2d3 267/* called with host->lock held, interrupts disabled */
b6147490
GL		 268static void tmio_mmc_finish_request(struct tmio_mmc_host *host)
269{
b9269fdd
GL		 270 struct mmc_request *mrq;
271 unsigned long flags;
b6147490 272
b9269fdd
GL		 273 spin_lock_irqsave(&host->lock, flags);
274
275 mrq = host->mrq;
276 if (IS_ERR_OR_NULL(mrq)) {
277 spin_unlock_irqrestore(&host->lock, flags);
b6147490 278 return;
b9269fdd 279 }
b6147490 280
b6147490
GL		 281 host->cmd = NULL;
282 host->data = NULL;
283 host->force_pio = false;
284
285 cancel_delayed_work(&host->delayed_reset_work);
286
df3ef2d3 287 host->mrq = NULL;
b9269fdd 288 spin_unlock_irqrestore(&host->lock, flags);
df3ef2d3 289
e3de2be7
GL		 290 if (mrq->cmd->error || (mrq->data && mrq->data->error))
291 tmio_mmc_abort_dma(host);
292
b6147490 293 mmc_request_done(host->mmc, mrq);
0369483e
UH		 294
295 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
296 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
b6147490
GL		 297}
298
b9269fdd
GL		 299static void tmio_mmc_done_work(struct work_struct *work)
300{
301 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
302 done);
303 tmio_mmc_finish_request(host);
304}
305
b6147490
GL		 306/* These are the bitmasks the tmio chip requires to implement the MMC response
307 * types. Note that R1 and R6 are the same in this scheme. */
308#define APP_CMD 0x0040
309#define RESP_NONE 0x0300
310#define RESP_R1 0x0400
311#define RESP_R1B 0x0500
312#define RESP_R2 0x0600
313#define RESP_R3 0x0700
314#define DATA_PRESENT 0x0800
315#define TRANSFER_READ 0x1000
316#define TRANSFER_MULTI 0x2000
317#define SECURITY_CMD 0x4000
b8d11962 318#define NO_CMD12_ISSUE 0x4000 /* TMIO_MMC_HAVE_CMD12_CTRL */
b6147490
GL		 319
320static int tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
321{
322 struct mmc_data *data = host->data;
323 int c = cmd->opcode;
e23cd53c 324 u32 irq_mask = TMIO_MASK_CMD;
b6147490 325
0f506a96
GL		 326 /* CMD12 is handled by hardware */
327 if (cmd->opcode == MMC_STOP_TRANSMISSION && !cmd->arg) {
b6147490
GL		 328 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001);
329 return 0;
330 }
331
332 switch (mmc_resp_type(cmd)) {
333 case MMC_RSP_NONE: c |= RESP_NONE; break;
334 case MMC_RSP_R1: c |= RESP_R1; break;
335 case MMC_RSP_R1B: c |= RESP_R1B; break;
336 case MMC_RSP_R2: c |= RESP_R2; break;
337 case MMC_RSP_R3: c |= RESP_R3; break;
338 default:
339 pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
340 return -EINVAL;
341 }
342
343 host->cmd = cmd;
344
345/* FIXME - this seems to be ok commented out but the spec suggest this bit
346 * should be set when issuing app commands.
347 * if(cmd->flags & MMC_FLAG_ACMD)
348 * c |= APP_CMD;
349 */
350 if (data) {
351 c |= DATA_PRESENT;
352 if (data->blocks > 1) {
353 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100);
354 c |= TRANSFER_MULTI;
b8d11962
SU		 355
356 /*
357 * Disable auto CMD12 at IO_RW_EXTENDED when
358 * multiple block transfer
359 */
360 if ((host->pdata->flags & TMIO_MMC_HAVE_CMD12_CTRL) &&
361 (cmd->opcode == SD_IO_RW_EXTENDED))
362 c |= NO_CMD12_ISSUE;
b6147490
GL		 363 }
364 if (data->flags & MMC_DATA_READ)
365 c |= TRANSFER_READ;
366 }
367
e23cd53c
GL		 368 if (!host->native_hotplug)
369 irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
370 tmio_mmc_enable_mmc_irqs(host, irq_mask);
b6147490
GL		 371
372 /* Fire off the command */
373 sd_ctrl_write32(host, CTL_ARG_REG, cmd->arg);
374 sd_ctrl_write16(host, CTL_SD_CMD, c);
375
376 return 0;
377}
378
379/*
380 * This chip always returns (at least?) as much data as you ask for.
381 * I'm unsure what happens if you ask for less than a block. This should be
25985edc 382 * looked into to ensure that a funny length read doesn't hose the controller.
b6147490
GL		 383 */
384static void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
385{
386 struct mmc_data *data = host->data;
387 void *sg_virt;
388 unsigned short *buf;
389 unsigned int count;
390 unsigned long flags;
391
392 if ((host->chan_tx || host->chan_rx) && !host->force_pio) {
393 pr_err("PIO IRQ in DMA mode!\n");
394 return;
395 } else if (!data) {
396 pr_debug("Spurious PIO IRQ\n");
397 return;
398 }
399
400 sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags);
401 buf = (unsigned short *)(sg_virt + host->sg_off);
402
403 count = host->sg_ptr->length - host->sg_off;
404 if (count > data->blksz)
405 count = data->blksz;
406
407 pr_debug("count: %08x offset: %08x flags %08x\n",
408 count, host->sg_off, data->flags);
409
410 /* Transfer the data */
411 if (data->flags & MMC_DATA_READ)
412 sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
413 else
414 sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
415
416 host->sg_off += count;
417
418 tmio_mmc_kunmap_atomic(host->sg_ptr, &flags, sg_virt);
419
420 if (host->sg_off == host->sg_ptr->length)
421 tmio_mmc_next_sg(host);
422
423 return;
424}
425
426static void tmio_mmc_check_bounce_buffer(struct tmio_mmc_host *host)
427{
428 if (host->sg_ptr == &host->bounce_sg) {
429 unsigned long flags;
430 void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags);
431 memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length);
432 tmio_mmc_kunmap_atomic(host->sg_orig, &flags, sg_vaddr);
433 }
434}
435
436/* needs to be called with host->lock held */
437void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
438{
439 struct mmc_data *data = host->data;
440 struct mmc_command *stop;
441
442 host->data = NULL;
443
444 if (!data) {
445 dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
446 return;
447 }
448 stop = data->stop;
449
450 /* FIXME - return correct transfer count on errors */
451 if (!data->error)
452 data->bytes_xfered = data->blocks * data->blksz;
453 else
454 data->bytes_xfered = 0;
455
456 pr_debug("Completed data request\n");
457
458 /*
459 * FIXME: other drivers allow an optional stop command of any given type
460 * which we dont do, as the chip can auto generate them.
461 * Perhaps we can be smarter about when to use auto CMD12 and
462 * only issue the auto request when we know this is the desired
463 * stop command, allowing fallback to the stop command the
464 * upper layers expect. For now, we do what works.
465 */
466
467 if (data->flags & MMC_DATA_READ) {
468 if (host->chan_rx && !host->force_pio)
469 tmio_mmc_check_bounce_buffer(host);
470 dev_dbg(&host->pdev->dev, "Complete Rx request %p\n",
471 host->mrq);
472 } else {
473 dev_dbg(&host->pdev->dev, "Complete Tx request %p\n",
474 host->mrq);
475 }
476
477 if (stop) {
0f506a96 478 if (stop->opcode == MMC_STOP_TRANSMISSION && !stop->arg)
b6147490
GL		 479 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000);
480 else
481 BUG();
482 }
483
b9269fdd 484 schedule_work(&host->done);
b6147490
GL		 485}
486
487static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
488{
489 struct mmc_data *data;
490 spin_lock(&host->lock);
491 data = host->data;
492
493 if (!data)
494 goto out;
495
496 if (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) {
81e888da
SU		 497 u32 status = sd_ctrl_read32(host, CTL_STATUS);
498 bool done = false;
499
b6147490
GL		 500 /*
501 * Has all data been written out yet? Testing on SuperH showed,
502 * that in most cases the first interrupt comes already with the
503 * BUSY status bit clear, but on some operations, like mount or
504 * in the beginning of a write / sync / umount, there is one
505 * DATAEND interrupt with the BUSY bit set, in this cases
506 * waiting for one more interrupt fixes the problem.
507 */
81e888da
SU		 508 if (host->pdata->flags & TMIO_MMC_HAS_IDLE_WAIT) {
509 if (status & TMIO_STAT_ILL_FUNC)
510 done = true;
511 } else {
512 if (!(status & TMIO_STAT_CMD_BUSY))
513 done = true;
514 }
515
516 if (done) {
b6147490
GL		 517 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
518 tasklet_schedule(&host->dma_complete);
519 }
520 } else if (host->chan_rx && (data->flags & MMC_DATA_READ) && !host->force_pio) {
521 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
522 tasklet_schedule(&host->dma_complete);
523 } else {
524 tmio_mmc_do_data_irq(host);
525 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_READOP | TMIO_MASK_WRITEOP);
526 }
527out:
528 spin_unlock(&host->lock);
529}
530
531static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
532 unsigned int stat)
533{
534 struct mmc_command *cmd = host->cmd;
535 int i, addr;
536
537 spin_lock(&host->lock);
538
539 if (!host->cmd) {
540 pr_debug("Spurious CMD irq\n");
541 goto out;
542 }
543
544 host->cmd = NULL;
545
546 /* This controller is sicker than the PXA one. Not only do we need to
547 * drop the top 8 bits of the first response word, we also need to
548 * modify the order of the response for short response command types.
549 */
550
551 for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
552 cmd->resp[i] = sd_ctrl_read32(host, addr);
553
554 if (cmd->flags & MMC_RSP_136) {
555 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
556 cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
557 cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
558 cmd->resp[3] <<= 8;
559 } else if (cmd->flags & MMC_RSP_R3) {
560 cmd->resp[0] = cmd->resp[3];
561 }
562
563 if (stat & TMIO_STAT_CMDTIMEOUT)
564 cmd->error = -ETIMEDOUT;
565 else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
566 cmd->error = -EILSEQ;
567
568 /* If there is data to handle we enable data IRQs here, and
569 * we will ultimatley finish the request in the data_end handler.
570 * If theres no data or we encountered an error, finish now.
571 */
572 if (host->data && !cmd->error) {
573 if (host->data->flags & MMC_DATA_READ) {
574 if (host->force_pio || !host->chan_rx)
575 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_READOP);
576 else
577 tasklet_schedule(&host->dma_issue);
578 } else {
579 if (host->force_pio || !host->chan_tx)
580 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
581 else
582 tasklet_schedule(&host->dma_issue);
583 }
584 } else {
b9269fdd 585 schedule_work(&host->done);
b6147490
GL		 586 }
587
588out:
589 spin_unlock(&host->lock);
590}
591
7729c7a2
SH		 592static void tmio_mmc_card_irq_status(struct tmio_mmc_host *host,
593 int *ireg, int *status)
b6147490 594{
7729c7a2
SH		 595 *status = sd_ctrl_read32(host, CTL_STATUS);
596 *ireg = *status & TMIO_MASK_IRQ & ~host->sdcard_irq_mask;
b6147490 597
7729c7a2
SH		 598 pr_debug_status(*status);
599 pr_debug_status(*ireg);
f83bfa75
SU		 600
601 /* Clear the status except the interrupt status */
602 sd_ctrl_write32(host, CTL_STATUS, TMIO_MASK_IRQ);
7729c7a2 603}
b6147490 604
7729c7a2
SH		 605static bool __tmio_mmc_card_detect_irq(struct tmio_mmc_host *host,
606 int ireg, int status)
607{
608 struct mmc_host *mmc = host->mmc;
b6147490 609
e312eb1e
PP		 610 /* Card insert / remove attempts */
611 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
612 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
613 TMIO_STAT_CARD_REMOVE);
71d111cd
GL		 614 if ((((ireg & TMIO_STAT_CARD_REMOVE) && mmc->card) ||
615 ((ireg & TMIO_STAT_CARD_INSERT) && !mmc->card)) &&
616 !work_pending(&mmc->detect.work))
b9269fdd 617 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
7729c7a2 618 return true;
b6147490
GL		 619 }
620
7729c7a2
SH		 621 return false;
622}
623
624irqreturn_t tmio_mmc_card_detect_irq(int irq, void *devid)
625{
626 unsigned int ireg, status;
627 struct tmio_mmc_host *host = devid;
b6147490 628
7729c7a2
SH		 629 tmio_mmc_card_irq_status(host, &ireg, &status);
630 __tmio_mmc_card_detect_irq(host, ireg, status);
631
632 return IRQ_HANDLED;
633}
634EXPORT_SYMBOL(tmio_mmc_card_detect_irq);
635
636static bool __tmio_mmc_sdcard_irq(struct tmio_mmc_host *host,
637 int ireg, int status)
638{
e312eb1e
PP		 639 /* Command completion */
640 if (ireg & (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT)) {
641 tmio_mmc_ack_mmc_irqs(host,
642 TMIO_STAT_CMDRESPEND |
643 TMIO_STAT_CMDTIMEOUT);
644 tmio_mmc_cmd_irq(host, status);
7729c7a2 645 return true;
e312eb1e 646 }
b6147490 647
e312eb1e
PP		 648 /* Data transfer */
649 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
650 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
651 tmio_mmc_pio_irq(host);
7729c7a2 652 return true;
e312eb1e 653 }
b6147490 654
e312eb1e
PP		 655 /* Data transfer completion */
656 if (ireg & TMIO_STAT_DATAEND) {
657 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_DATAEND);
658 tmio_mmc_data_irq(host);
7729c7a2 659 return true;
b6147490 660 }
e312eb1e 661
7729c7a2
SH		 662 return false;
663}
664
665irqreturn_t tmio_mmc_sdcard_irq(int irq, void *devid)
666{
667 unsigned int ireg, status;
668 struct tmio_mmc_host *host = devid;
669
670 tmio_mmc_card_irq_status(host, &ireg, &status);
671 __tmio_mmc_sdcard_irq(host, ireg, status);
672
673 return IRQ_HANDLED;
674}
675EXPORT_SYMBOL(tmio_mmc_sdcard_irq);
676
677irqreturn_t tmio_mmc_sdio_irq(int irq, void *devid)
678{
679 struct tmio_mmc_host *host = devid;
680 struct mmc_host *mmc = host->mmc;
681 struct tmio_mmc_data *pdata = host->pdata;
682 unsigned int ireg, status;
6b98757e 683 unsigned int sdio_status;
7729c7a2
SH		 684
685 if (!(pdata->flags & TMIO_MMC_SDIO_IRQ))
686 return IRQ_HANDLED;
687
688 status = sd_ctrl_read16(host, CTL_SDIO_STATUS);
689 ireg = status & TMIO_SDIO_MASK_ALL & ~host->sdcard_irq_mask;
690
6b98757e
SU		 691 sdio_status = status & ~TMIO_SDIO_MASK_ALL;
692 if (pdata->flags & TMIO_MMC_SDIO_STATUS_QUIRK)
693 sdio_status |= 6;
694
695 sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status);
7729c7a2
SH		 696
697 if (mmc->caps & MMC_CAP_SDIO_IRQ && ireg & TMIO_SDIO_STAT_IOIRQ)
698 mmc_signal_sdio_irq(mmc);
699
700 return IRQ_HANDLED;
701}
702EXPORT_SYMBOL(tmio_mmc_sdio_irq);
703
704irqreturn_t tmio_mmc_irq(int irq, void *devid)
705{
706 struct tmio_mmc_host *host = devid;
707 unsigned int ireg, status;
708
709 pr_debug("MMC IRQ begin\n");
710
711 tmio_mmc_card_irq_status(host, &ireg, &status);
712 if (__tmio_mmc_card_detect_irq(host, ireg, status))
713 return IRQ_HANDLED;
714 if (__tmio_mmc_sdcard_irq(host, ireg, status))
715 return IRQ_HANDLED;
716
717 tmio_mmc_sdio_irq(irq, devid);
b6147490 718
b6147490
GL		 719 return IRQ_HANDLED;
720}
8e7bfdb3 721EXPORT_SYMBOL(tmio_mmc_irq);
b6147490
GL		 722
723static int tmio_mmc_start_data(struct tmio_mmc_host *host,
724 struct mmc_data *data)
725{
726 struct tmio_mmc_data *pdata = host->pdata;
727
728 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
729 data->blksz, data->blocks);
730
731 /* Some hardware cannot perform 2 byte requests in 4 bit mode */
732 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
733 int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES;
734
735 if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) {
736 pr_err("%s: %d byte block unsupported in 4 bit mode\n",
737 mmc_hostname(host->mmc), data->blksz);
738 return -EINVAL;
739 }
740 }
741
742 tmio_mmc_init_sg(host, data);
743 host->data = data;
744
745 /* Set transfer length / blocksize */
746 sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
747 sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
748
749 tmio_mmc_start_dma(host, data);
750
751 return 0;
752}
753
754/* Process requests from the MMC layer */
755static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
756{
757 struct tmio_mmc_host *host = mmc_priv(mmc);
df3ef2d3 758 unsigned long flags;
b6147490
GL		 759 int ret;
760
df3ef2d3
GL		 761 spin_lock_irqsave(&host->lock, flags);
762
763 if (host->mrq) {
b6147490 764 pr_debug("request not null\n");
df3ef2d3
GL		 765 if (IS_ERR(host->mrq)) {
766 spin_unlock_irqrestore(&host->lock, flags);
767 mrq->cmd->error = -EAGAIN;
768 mmc_request_done(mmc, mrq);
769 return;
770 }
771 }
b6147490
GL		 772
773 host->last_req_ts = jiffies;
774 wmb();
775 host->mrq = mrq;
776
df3ef2d3
GL		 777 spin_unlock_irqrestore(&host->lock, flags);
778
0369483e
UH		 779 pm_runtime_get_sync(mmc_dev(mmc));
780
b6147490
GL		 781 if (mrq->data) {
782 ret = tmio_mmc_start_data(host, mrq->data);
783 if (ret)
784 goto fail;
785 }
786
787 ret = tmio_mmc_start_command(host, mrq->cmd);
788 if (!ret) {
789 schedule_delayed_work(&host->delayed_reset_work,
790 msecs_to_jiffies(2000));
791 return;
792 }
793
794fail:
b6147490 795 host->force_pio = false;
df3ef2d3 796 host->mrq = NULL;
b6147490
GL		 797 mrq->cmd->error = ret;
798 mmc_request_done(mmc, mrq);
0369483e
UH		 799
800 pm_runtime_mark_last_busy(mmc_dev(mmc));
801 pm_runtime_put_autosuspend(mmc_dev(mmc));
b6147490
GL		 802}
803
ae12d250 804static int tmio_mmc_clk_update(struct tmio_mmc_host *host)
8c102a96 805{
ae12d250 806 struct mmc_host *mmc = host->mmc;
8c102a96
GL		 807 struct tmio_mmc_data *pdata = host->pdata;
808 int ret;
809
810 if (!pdata->clk_enable)
811 return -ENOTSUPP;
812
813 ret = pdata->clk_enable(host->pdev, &mmc->f_max);
814 if (!ret)
815 mmc->f_min = mmc->f_max / 512;
816
817 return ret;
818}
819
619b08d4 820static void tmio_mmc_power_on(struct tmio_mmc_host *host, unsigned short vdd)
b958a67c
GL		 821{
822 struct mmc_host *mmc = host->mmc;
619b08d4
GL		 823 int ret = 0;
824
825 /* .set_ios() is returning void, so, no chance to report an error */
b958a67c 826
9d731e75
CB		 827 if (host->set_pwr)
828 host->set_pwr(host->pdev, 1);
829
619b08d4
GL		 830 if (!IS_ERR(mmc->supply.vmmc)) {
831 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
832 /*
833 * Attention: empiric value. With a b43 WiFi SDIO card this
834 * delay proved necessary for reliable card-insertion probing.
835 * 100us were not enough. Is this the same 140us delay, as in
836 * tmio_mmc_set_ios()?
837 */
838 udelay(200);
839 }
840 /*
841 * It seems, VccQ should be switched on after Vcc, this is also what the
842 * omap_hsmmc.c driver does.
843 */
844 if (!IS_ERR(mmc->supply.vqmmc) && !ret) {
6d1d6b47 845 ret = regulator_enable(mmc->supply.vqmmc);
619b08d4
GL		 846 udelay(200);
847 }
6d1d6b47
GL		 848
849 if (ret < 0)
850 dev_dbg(&host->pdev->dev, "Regulators failed to power up: %d\n",
851 ret);
619b08d4
GL		 852}
853
854static void tmio_mmc_power_off(struct tmio_mmc_host *host)
855{
856 struct mmc_host *mmc = host->mmc;
857
858 if (!IS_ERR(mmc->supply.vqmmc))
859 regulator_disable(mmc->supply.vqmmc);
860
b958a67c 861 if (!IS_ERR(mmc->supply.vmmc))
619b08d4 862 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
9d731e75
CB		 863
864 if (host->set_pwr)
865 host->set_pwr(host->pdev, 0);
b958a67c
GL		 866}
867
9ae4ed7d
UH		 868static void tmio_mmc_set_bus_width(struct tmio_mmc_host *host,
869 unsigned char bus_width)
870{
871 switch (bus_width) {
872 case MMC_BUS_WIDTH_1:
873 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0);
874 break;
875 case MMC_BUS_WIDTH_4:
876 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x00e0);
877 break;
878 }
879}
880
b6147490
GL		 881/* Set MMC clock / power.
882 * Note: This controller uses a simple divider scheme therefore it cannot
883 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
884 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
885 * slowest setting.
886 */
887static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
888{
889 struct tmio_mmc_host *host = mmc_priv(mmc);
4932bd64 890 struct device *dev = &host->pdev->dev;
df3ef2d3
GL		 891 unsigned long flags;
892
0369483e
UH		 893 pm_runtime_get_sync(mmc_dev(mmc));
894
b9269fdd
GL		 895 mutex_lock(&host->ios_lock);
896
df3ef2d3
GL		 897 spin_lock_irqsave(&host->lock, flags);
898 if (host->mrq) {
899 if (IS_ERR(host->mrq)) {
4932bd64 900 dev_dbg(dev,
df3ef2d3
GL		 901 "%s.%d: concurrent .set_ios(), clk %u, mode %u\n",
902 current->comm, task_pid_nr(current),
903 ios->clock, ios->power_mode);
904 host->mrq = ERR_PTR(-EINTR);
905 } else {
4932bd64 906 dev_dbg(dev,
df3ef2d3
GL		 907 "%s.%d: CMD%u active since %lu, now %lu!\n",
908 current->comm, task_pid_nr(current),
909 host->mrq->cmd->opcode, host->last_req_ts, jiffies);
910 }
911 spin_unlock_irqrestore(&host->lock, flags);
b9269fdd
GL		 912
913 mutex_unlock(&host->ios_lock);
df3ef2d3
GL		 914 return;
915 }
916
917 host->mrq = ERR_PTR(-EBUSY);
918
919 spin_unlock_irqrestore(&host->lock, flags);
b6147490 920
3b292bb0
UH		 921 switch (ios->power_mode) {
922 case MMC_POWER_OFF:
923 tmio_mmc_power_off(host);
924 tmio_mmc_clk_stop(host);
925 break;
926 case MMC_POWER_UP:
71d111cd 927 tmio_mmc_set_clock(host, ios->clock);
3b292bb0 928 tmio_mmc_power_on(host, ios->vdd);
5fd01579 929 tmio_mmc_clk_start(host);
9ae4ed7d 930 tmio_mmc_set_bus_width(host, ios->bus_width);
3b292bb0
UH		 931 break;
932 case MMC_POWER_ON:
933 tmio_mmc_set_clock(host, ios->clock);
934 tmio_mmc_clk_start(host);
935 tmio_mmc_set_bus_width(host, ios->bus_width);
936 break;
937 }
b6147490
GL		 938
939 /* Let things settle. delay taken from winCE driver */
940 udelay(140);
df3ef2d3
GL		 941 if (PTR_ERR(host->mrq) == -EINTR)
942 dev_dbg(&host->pdev->dev,
943 "%s.%d: IOS interrupted: clk %u, mode %u",
944 current->comm, task_pid_nr(current),
945 ios->clock, ios->power_mode);
946 host->mrq = NULL;
b9269fdd 947
ae12d250
UH		 948 host->clk_cache = ios->clock;
949
b9269fdd 950 mutex_unlock(&host->ios_lock);
0369483e
UH		 951
952 pm_runtime_mark_last_busy(mmc_dev(mmc));
953 pm_runtime_put_autosuspend(mmc_dev(mmc));
b6147490
GL		 954}
955
956static int tmio_mmc_get_ro(struct mmc_host *mmc)
957{
958 struct tmio_mmc_host *host = mmc_priv(mmc);
959 struct tmio_mmc_data *pdata = host->pdata;
3071cafb
GL		 960 int ret = mmc_gpio_get_ro(mmc);
961 if (ret >= 0)
962 return ret;
b6147490 963
0369483e
UH		 964 pm_runtime_get_sync(mmc_dev(mmc));
965 ret = !((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
966 (sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT));
967 pm_runtime_mark_last_busy(mmc_dev(mmc));
968 pm_runtime_put_autosuspend(mmc_dev(mmc));
969
970 return ret;
b6147490
GL		 971}
972
b6147490
GL		 973static const struct mmc_host_ops tmio_mmc_ops = {
974 .request = tmio_mmc_request,
975 .set_ios = tmio_mmc_set_ios,
976 .get_ro = tmio_mmc_get_ro,
2b63b341 977 .get_cd = mmc_gpio_get_cd,
b6147490
GL		 978 .enable_sdio_irq = tmio_mmc_enable_sdio_irq,
979};
980
05fae4a7 981static int tmio_mmc_init_ocr(struct tmio_mmc_host *host)
b958a67c
GL		 982{
983 struct tmio_mmc_data *pdata = host->pdata;
984 struct mmc_host *mmc = host->mmc;
985
986 mmc_regulator_get_supply(mmc);
987
05fae4a7 988 /* use ocr_mask if no regulator */
b958a67c 989 if (!mmc->ocr_avail)
05fae4a7
KM		 990 mmc->ocr_avail = pdata->ocr_mask;
991
992 /*
993 * try again.
994 * There is possibility that regulator has not been probed
995 */
996 if (!mmc->ocr_avail)
997 return -EPROBE_DEFER;
998
999 return 0;
b958a67c
GL		 1000}
1001
5a00a971
GL		 1002static void tmio_mmc_of_parse(struct platform_device *pdev,
1003 struct tmio_mmc_data *pdata)
1004{
1005 const struct device_node *np = pdev->dev.of_node;
1006 if (!np)
1007 return;
1008
1009 if (of_get_property(np, "toshiba,mmc-wrprotect-disable", NULL))
1010 pdata->flags |= TMIO_MMC_WRPROTECT_DISABLE;
1011}
1012
c3be1efd 1013int tmio_mmc_host_probe(struct tmio_mmc_host **host,
b6147490
GL		 1014 struct platform_device *pdev,
1015 struct tmio_mmc_data *pdata)
1016{
1017 struct tmio_mmc_host *_host;
1018 struct mmc_host *mmc;
1019 struct resource *res_ctl;
1020 int ret;
1021 u32 irq_mask = TMIO_MASK_CMD;
1022
5a00a971
GL		 1023 tmio_mmc_of_parse(pdev, pdata);
1024
7b952137
GL		 1025 if (!(pdata->flags & TMIO_MMC_HAS_IDLE_WAIT))
1026 pdata->write16_hook = NULL;
1027
b6147490
GL		 1028 res_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1029 if (!res_ctl)
1030 return -EINVAL;
1031
1032 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &pdev->dev);
1033 if (!mmc)
1034 return -ENOMEM;
1035
274a752b
SB		 1036 ret = mmc_of_parse(mmc);
1037 if (ret < 0)
1038 goto host_free;
5a00a971 1039
7311bef0 1040 pdata->dev = &pdev->dev;
b6147490
GL		 1041 _host = mmc_priv(mmc);
1042 _host->pdata = pdata;
1043 _host->mmc = mmc;
1044 _host->pdev = pdev;
1045 platform_set_drvdata(pdev, mmc);
1046
9d731e75 1047 _host->set_pwr = pdata->set_pwr;
b6147490
GL		 1048 _host->set_clk_div = pdata->set_clk_div;
1049
05fae4a7
KM		 1050 ret = tmio_mmc_init_ocr(_host);
1051 if (ret < 0)
1052 goto host_free;
1053
b6147490
GL		 1054 _host->ctl = ioremap(res_ctl->start, resource_size(res_ctl));
1055 if (!_host->ctl) {
1056 ret = -ENOMEM;
1057 goto host_free;
1058 }
1059
1060 mmc->ops = &tmio_mmc_ops;
5a00a971 1061 mmc->caps |= MMC_CAP_4_BIT_DATA | pdata->capabilities;
dd006b30 1062 mmc->caps2 |= pdata->capabilities2;
b6147490
GL		 1063 mmc->max_segs = 32;
1064 mmc->max_blk_size = 512;
1065 mmc->max_blk_count = (PAGE_CACHE_SIZE / mmc->max_blk_size) *
1066 mmc->max_segs;
1067 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1068 mmc->max_seg_size = mmc->max_req_size;
b6147490 1069
c8be24c2 1070 _host->native_hotplug = !(pdata->flags & TMIO_MMC_USE_GPIO_CD ||
2b1ac5c2 1071 mmc->caps & MMC_CAP_NEEDS_POLL ||
5a00a971
GL		 1072 mmc->caps & MMC_CAP_NONREMOVABLE ||
1073 mmc->slot.cd_irq >= 0);
2b1ac5c2 1074
ae12d250 1075 if (tmio_mmc_clk_update(_host) < 0) {
8c102a96
GL		 1076 mmc->f_max = pdata->hclk;
1077 mmc->f_min = mmc->f_max / 512;
1078 }
1079
cbb18b30 1080 /*
0369483e
UH		 1081 * While using internal tmio hardware logic for card detection, we need
1082 * to ensure it stays powered for it to work.
cbb18b30 1083 */
2b1ac5c2 1084 if (_host->native_hotplug)
cbb18b30
BH		 1085 pm_runtime_get_noresume(&pdev->dev);
1086
b6147490
GL		 1087 tmio_mmc_clk_stop(_host);
1088 tmio_mmc_reset(_host);
1089
54680fe7 1090 _host->sdcard_irq_mask = sd_ctrl_read32(_host, CTL_IRQ_MASK);
b6147490 1091 tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL);
e0337cc8
GL		 1092
1093 /* Unmask the IRQs we want to know about */
1094 if (!_host->chan_rx)
1095 irq_mask |= TMIO_MASK_READOP;
1096 if (!_host->chan_tx)
1097 irq_mask |= TMIO_MASK_WRITEOP;
1098 if (!_host->native_hotplug)
1099 irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
1100
1101 _host->sdcard_irq_mask &= ~irq_mask;
1102
7501c431
UH		 1103 _host->sdio_irq_enabled = false;
1104 if (pdata->flags & TMIO_MMC_SDIO_IRQ) {
1105 _host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
1106 sd_ctrl_write16(_host, CTL_SDIO_IRQ_MASK, _host->sdio_irq_mask);
1107 sd_ctrl_write16(_host, CTL_TRANSACTION_CTL, 0x0000);
1108 }
b6147490 1109
b6147490 1110 spin_lock_init(&_host->lock);
b9269fdd 1111 mutex_init(&_host->ios_lock);
b6147490
GL		 1112
1113 /* Init delayed work for request timeouts */
1114 INIT_DELAYED_WORK(&_host->delayed_reset_work, tmio_mmc_reset_work);
b9269fdd 1115 INIT_WORK(&_host->done, tmio_mmc_done_work);
b6147490
GL		 1116
1117 /* See if we also get DMA */
1118 tmio_mmc_request_dma(_host, pdata);
1119
0369483e
UH		 1120 pm_runtime_set_active(&pdev->dev);
1121 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1122 pm_runtime_use_autosuspend(&pdev->dev);
1123 pm_runtime_enable(&pdev->dev);
1124
8c102a96 1125 ret = mmc_add_host(mmc);
8c102a96
GL		 1126 if (ret < 0) {
1127 tmio_mmc_host_remove(_host);
1128 return ret;
1129 }
b6147490 1130
c419e611
RW		 1131 dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1132
c8be24c2 1133 if (pdata->flags & TMIO_MMC_USE_GPIO_CD) {
214fc309 1134 ret = mmc_gpio_request_cd(mmc, pdata->cd_gpio, 0);
c8be24c2
GL		 1135 if (ret < 0) {
1136 tmio_mmc_host_remove(_host);
1137 return ret;
1138 }
1139 }
1140
b6147490
GL		 1141 *host = _host;
1142
1143 return 0;
1144
b6147490
GL		 1145host_free:
1146 mmc_free_host(mmc);
1147
1148 return ret;
1149}
1150EXPORT_SYMBOL(tmio_mmc_host_probe);
1151
1152void tmio_mmc_host_remove(struct tmio_mmc_host *host)
1153{
e6ee7182 1154 struct platform_device *pdev = host->pdev;
c8be24c2
GL		 1155 struct mmc_host *mmc = host->mmc;
1156
2b1ac5c2 1157 if (!host->native_hotplug)
7311bef0
GL		 1158 pm_runtime_get_sync(&pdev->dev);
1159
c419e611
RW		 1160 dev_pm_qos_hide_latency_limit(&pdev->dev);
1161
c8be24c2 1162 mmc_remove_host(mmc);
b9269fdd 1163 cancel_work_sync(&host->done);
b6147490
GL		 1164 cancel_delayed_work_sync(&host->delayed_reset_work);
1165 tmio_mmc_release_dma(host);
e6ee7182 1166
e6ee7182
GL		 1167 pm_runtime_put_sync(&pdev->dev);
1168 pm_runtime_disable(&pdev->dev);
7311bef0
GL		 1169
1170 iounmap(host->ctl);
c8be24c2 1171 mmc_free_host(mmc);
b6147490
GL		 1172}
1173EXPORT_SYMBOL(tmio_mmc_host_remove);
1174
9ade7dbf 1175#ifdef CONFIG_PM
7311bef0
GL		 1176int tmio_mmc_host_runtime_suspend(struct device *dev)
1177{
ae12d250
UH		 1178 struct mmc_host *mmc = dev_get_drvdata(dev);
1179 struct tmio_mmc_host *host = mmc_priv(mmc);
1180
20e955c3
UH		 1181 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL);
1182
ae12d250
UH		 1183 if (host->clk_cache)
1184 tmio_mmc_clk_stop(host);
1185
1186 if (host->pdata->clk_disable)
1187 host->pdata->clk_disable(host->pdev);
1188
7311bef0
GL		 1189 return 0;
1190}
1191EXPORT_SYMBOL(tmio_mmc_host_runtime_suspend);
1192
1193int tmio_mmc_host_runtime_resume(struct device *dev)
1194{
1195 struct mmc_host *mmc = dev_get_drvdata(dev);
1196 struct tmio_mmc_host *host = mmc_priv(mmc);
7311bef0 1197
ae12d250
UH		 1198 tmio_mmc_reset(host);
1199 tmio_mmc_clk_update(host);
1200
1201 if (host->clk_cache) {
1202 tmio_mmc_set_clock(host, host->clk_cache);
1203 tmio_mmc_clk_start(host);
1204 }
1205
162f43e3 1206 tmio_mmc_enable_dma(host, true);
7311bef0 1207
7311bef0
GL		 1208 return 0;
1209}
1210EXPORT_SYMBOL(tmio_mmc_host_runtime_resume);
710dec95 1211#endif
7311bef0 1212
b6147490 1213MODULE_LICENSE("GPL v2");
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