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Commit | Line | Data |
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ce082596 JR |
1 | /* |
2 | * NAND Flash Controller Device Driver | |
3 | * Copyright © 2009-2010, Intel Corporation and its suppliers. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | * | |
18 | */ | |
ce082596 JR |
19 | #include <linux/interrupt.h> |
20 | #include <linux/delay.h> | |
84457949 | 21 | #include <linux/dma-mapping.h> |
ce082596 JR |
22 | #include <linux/wait.h> |
23 | #include <linux/mutex.h> | |
ce082596 JR |
24 | #include <linux/mtd/mtd.h> |
25 | #include <linux/module.h> | |
26 | ||
27 | #include "denali.h" | |
28 | ||
29 | MODULE_LICENSE("GPL"); | |
30 | ||
43914a2d MY |
31 | /* |
32 | * We define a module parameter that allows the user to override | |
ce082596 JR |
33 | * the hardware and decide what timing mode should be used. |
34 | */ | |
35 | #define NAND_DEFAULT_TIMINGS -1 | |
36 | ||
37 | static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; | |
38 | module_param(onfi_timing_mode, int, S_IRUGO); | |
8125450c MY |
39 | MODULE_PARM_DESC(onfi_timing_mode, |
40 | "Overrides default ONFI setting. -1 indicates use default timings"); | |
ce082596 JR |
41 | |
42 | #define DENALI_NAND_NAME "denali-nand" | |
43 | ||
43914a2d MY |
44 | /* |
45 | * We define a macro here that combines all interrupts this driver uses into | |
46 | * a single constant value, for convenience. | |
47 | */ | |
9589bf5b JI |
48 | #define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \ |
49 | INTR_STATUS__ECC_TRANSACTION_DONE | \ | |
50 | INTR_STATUS__ECC_ERR | \ | |
51 | INTR_STATUS__PROGRAM_FAIL | \ | |
52 | INTR_STATUS__LOAD_COMP | \ | |
53 | INTR_STATUS__PROGRAM_COMP | \ | |
54 | INTR_STATUS__TIME_OUT | \ | |
55 | INTR_STATUS__ERASE_FAIL | \ | |
56 | INTR_STATUS__RST_COMP | \ | |
57 | INTR_STATUS__ERASE_COMP) | |
ce082596 | 58 | |
43914a2d MY |
59 | /* |
60 | * indicates whether or not the internal value for the flash bank is | |
61 | * valid or not | |
62 | */ | |
5bac3acf | 63 | #define CHIP_SELECT_INVALID -1 |
ce082596 JR |
64 | |
65 | #define SUPPORT_8BITECC 1 | |
66 | ||
43914a2d MY |
67 | /* |
68 | * This macro divides two integers and rounds fractional values up | |
69 | * to the nearest integer value. | |
70 | */ | |
ce082596 JR |
71 | #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y))) |
72 | ||
43914a2d MY |
73 | /* |
74 | * this macro allows us to convert from an MTD structure to our own | |
ce082596 JR |
75 | * device context (denali) structure. |
76 | */ | |
442f201b BB |
77 | static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) |
78 | { | |
79 | return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand); | |
80 | } | |
ce082596 | 81 | |
43914a2d MY |
82 | /* |
83 | * These constants are defined by the driver to enable common driver | |
84 | * configuration options. | |
85 | */ | |
ce082596 JR |
86 | #define SPARE_ACCESS 0x41 |
87 | #define MAIN_ACCESS 0x42 | |
88 | #define MAIN_SPARE_ACCESS 0x43 | |
2902330e | 89 | #define PIPELINE_ACCESS 0x2000 |
ce082596 JR |
90 | |
91 | #define DENALI_READ 0 | |
92 | #define DENALI_WRITE 0x100 | |
93 | ||
94 | /* types of device accesses. We can issue commands and get status */ | |
95 | #define COMMAND_CYCLE 0 | |
96 | #define ADDR_CYCLE 1 | |
97 | #define STATUS_CYCLE 2 | |
98 | ||
43914a2d MY |
99 | /* |
100 | * this is a helper macro that allows us to | |
101 | * format the bank into the proper bits for the controller | |
102 | */ | |
ce082596 JR |
103 | #define BANK(x) ((x) << 24) |
104 | ||
ce082596 JR |
105 | /* forward declarations */ |
106 | static void clear_interrupts(struct denali_nand_info *denali); | |
bdca6dae CD |
107 | static uint32_t wait_for_irq(struct denali_nand_info *denali, |
108 | uint32_t irq_mask); | |
109 | static void denali_irq_enable(struct denali_nand_info *denali, | |
110 | uint32_t int_mask); | |
ce082596 JR |
111 | static uint32_t read_interrupt_status(struct denali_nand_info *denali); |
112 | ||
43914a2d MY |
113 | /* |
114 | * Certain operations for the denali NAND controller use an indexed mode to | |
115 | * read/write data. The operation is performed by writing the address value | |
116 | * of the command to the device memory followed by the data. This function | |
bdca6dae | 117 | * abstracts this common operation. |
43914a2d | 118 | */ |
bdca6dae CD |
119 | static void index_addr(struct denali_nand_info *denali, |
120 | uint32_t address, uint32_t data) | |
ce082596 | 121 | { |
24c3fa36 CD |
122 | iowrite32(address, denali->flash_mem); |
123 | iowrite32(data, denali->flash_mem + 0x10); | |
ce082596 JR |
124 | } |
125 | ||
126 | /* Perform an indexed read of the device */ | |
127 | static void index_addr_read_data(struct denali_nand_info *denali, | |
128 | uint32_t address, uint32_t *pdata) | |
129 | { | |
24c3fa36 | 130 | iowrite32(address, denali->flash_mem); |
ce082596 JR |
131 | *pdata = ioread32(denali->flash_mem + 0x10); |
132 | } | |
133 | ||
43914a2d MY |
134 | /* |
135 | * We need to buffer some data for some of the NAND core routines. | |
136 | * The operations manage buffering that data. | |
137 | */ | |
ce082596 JR |
138 | static void reset_buf(struct denali_nand_info *denali) |
139 | { | |
140 | denali->buf.head = denali->buf.tail = 0; | |
141 | } | |
142 | ||
143 | static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte) | |
144 | { | |
ce082596 JR |
145 | denali->buf.buf[denali->buf.tail++] = byte; |
146 | } | |
147 | ||
148 | /* reads the status of the device */ | |
149 | static void read_status(struct denali_nand_info *denali) | |
150 | { | |
5637b69d | 151 | uint32_t cmd; |
ce082596 JR |
152 | |
153 | /* initialize the data buffer to store status */ | |
154 | reset_buf(denali); | |
155 | ||
f0bc0c77 CD |
156 | cmd = ioread32(denali->flash_reg + WRITE_PROTECT); |
157 | if (cmd) | |
158 | write_byte_to_buf(denali, NAND_STATUS_WP); | |
159 | else | |
160 | write_byte_to_buf(denali, 0); | |
ce082596 JR |
161 | } |
162 | ||
163 | /* resets a specific device connected to the core */ | |
164 | static void reset_bank(struct denali_nand_info *denali) | |
165 | { | |
5637b69d | 166 | uint32_t irq_status; |
8125450c | 167 | uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT; |
ce082596 JR |
168 | |
169 | clear_interrupts(denali); | |
170 | ||
9589bf5b | 171 | iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET); |
ce082596 JR |
172 | |
173 | irq_status = wait_for_irq(denali, irq_mask); | |
5bac3acf | 174 | |
9589bf5b | 175 | if (irq_status & INTR_STATUS__TIME_OUT) |
84457949 | 176 | dev_err(denali->dev, "reset bank failed.\n"); |
ce082596 JR |
177 | } |
178 | ||
179 | /* Reset the flash controller */ | |
eda936ef | 180 | static uint16_t denali_nand_reset(struct denali_nand_info *denali) |
ce082596 | 181 | { |
93e3c8ad | 182 | int i; |
ce082596 | 183 | |
8125450c | 184 | for (i = 0; i < denali->max_banks; i++) |
9589bf5b JI |
185 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
186 | denali->flash_reg + INTR_STATUS(i)); | |
ce082596 | 187 | |
8125450c | 188 | for (i = 0; i < denali->max_banks; i++) { |
9589bf5b | 189 | iowrite32(1 << i, denali->flash_reg + DEVICE_RESET); |
8125450c | 190 | while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) & |
9589bf5b | 191 | (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT))) |
628bfd41 | 192 | cpu_relax(); |
9589bf5b JI |
193 | if (ioread32(denali->flash_reg + INTR_STATUS(i)) & |
194 | INTR_STATUS__TIME_OUT) | |
84457949 | 195 | dev_dbg(denali->dev, |
ce082596 JR |
196 | "NAND Reset operation timed out on bank %d\n", i); |
197 | } | |
198 | ||
c89eeda8 | 199 | for (i = 0; i < denali->max_banks; i++) |
9589bf5b | 200 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
8125450c | 201 | denali->flash_reg + INTR_STATUS(i)); |
ce082596 JR |
202 | |
203 | return PASS; | |
204 | } | |
205 | ||
43914a2d MY |
206 | /* |
207 | * this routine calculates the ONFI timing values for a given mode and | |
bdca6dae CD |
208 | * programs the clocking register accordingly. The mode is determined by |
209 | * the get_onfi_nand_para routine. | |
ce082596 | 210 | */ |
eda936ef | 211 | static void nand_onfi_timing_set(struct denali_nand_info *denali, |
bdca6dae | 212 | uint16_t mode) |
ce082596 JR |
213 | { |
214 | uint16_t Trea[6] = {40, 30, 25, 20, 20, 16}; | |
215 | uint16_t Trp[6] = {50, 25, 17, 15, 12, 10}; | |
216 | uint16_t Treh[6] = {30, 15, 15, 10, 10, 7}; | |
217 | uint16_t Trc[6] = {100, 50, 35, 30, 25, 20}; | |
218 | uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15}; | |
219 | uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5}; | |
220 | uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25}; | |
221 | uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70}; | |
222 | uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100}; | |
223 | uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100}; | |
224 | uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60}; | |
225 | uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15}; | |
226 | ||
ce082596 JR |
227 | uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid; |
228 | uint16_t dv_window = 0; | |
229 | uint16_t en_lo, en_hi; | |
230 | uint16_t acc_clks; | |
231 | uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; | |
232 | ||
ce082596 JR |
233 | en_lo = CEIL_DIV(Trp[mode], CLK_X); |
234 | en_hi = CEIL_DIV(Treh[mode], CLK_X); | |
235 | #if ONFI_BLOOM_TIME | |
236 | if ((en_hi * CLK_X) < (Treh[mode] + 2)) | |
237 | en_hi++; | |
238 | #endif | |
239 | ||
240 | if ((en_lo + en_hi) * CLK_X < Trc[mode]) | |
241 | en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X); | |
242 | ||
243 | if ((en_lo + en_hi) < CLK_MULTI) | |
244 | en_lo += CLK_MULTI - en_lo - en_hi; | |
245 | ||
246 | while (dv_window < 8) { | |
247 | data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode]; | |
248 | ||
249 | data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode]; | |
250 | ||
8125450c MY |
251 | data_invalid = data_invalid_rhoh < data_invalid_rloh ? |
252 | data_invalid_rhoh : data_invalid_rloh; | |
ce082596 JR |
253 | |
254 | dv_window = data_invalid - Trea[mode]; | |
255 | ||
256 | if (dv_window < 8) | |
257 | en_lo++; | |
258 | } | |
259 | ||
260 | acc_clks = CEIL_DIV(Trea[mode], CLK_X); | |
261 | ||
7d14ecd0 | 262 | while (acc_clks * CLK_X - Trea[mode] < 3) |
ce082596 JR |
263 | acc_clks++; |
264 | ||
7d14ecd0 | 265 | if (data_invalid - acc_clks * CLK_X < 2) |
84457949 | 266 | dev_warn(denali->dev, "%s, Line %d: Warning!\n", |
8125450c | 267 | __FILE__, __LINE__); |
ce082596 JR |
268 | |
269 | addr_2_data = CEIL_DIV(Tadl[mode], CLK_X); | |
270 | re_2_we = CEIL_DIV(Trhw[mode], CLK_X); | |
271 | re_2_re = CEIL_DIV(Trhz[mode], CLK_X); | |
272 | we_2_re = CEIL_DIV(Twhr[mode], CLK_X); | |
273 | cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X); | |
ce082596 JR |
274 | if (cs_cnt == 0) |
275 | cs_cnt = 1; | |
276 | ||
277 | if (Tcea[mode]) { | |
7d14ecd0 | 278 | while (cs_cnt * CLK_X + Trea[mode] < Tcea[mode]) |
ce082596 JR |
279 | cs_cnt++; |
280 | } | |
281 | ||
282 | #if MODE5_WORKAROUND | |
283 | if (mode == 5) | |
284 | acc_clks = 5; | |
285 | #endif | |
286 | ||
287 | /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */ | |
7d14ecd0 MY |
288 | if (ioread32(denali->flash_reg + MANUFACTURER_ID) == 0 && |
289 | ioread32(denali->flash_reg + DEVICE_ID) == 0x88) | |
ce082596 JR |
290 | acc_clks = 6; |
291 | ||
24c3fa36 CD |
292 | iowrite32(acc_clks, denali->flash_reg + ACC_CLKS); |
293 | iowrite32(re_2_we, denali->flash_reg + RE_2_WE); | |
294 | iowrite32(re_2_re, denali->flash_reg + RE_2_RE); | |
295 | iowrite32(we_2_re, denali->flash_reg + WE_2_RE); | |
296 | iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA); | |
297 | iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT); | |
298 | iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT); | |
299 | iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT); | |
ce082596 JR |
300 | } |
301 | ||
ce082596 JR |
302 | /* queries the NAND device to see what ONFI modes it supports. */ |
303 | static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) | |
304 | { | |
305 | int i; | |
43914a2d MY |
306 | |
307 | /* | |
308 | * we needn't to do a reset here because driver has already | |
4c03bbdf | 309 | * reset all the banks before |
43914a2d | 310 | */ |
ce082596 JR |
311 | if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
312 | ONFI_TIMING_MODE__VALUE)) | |
313 | return FAIL; | |
314 | ||
315 | for (i = 5; i > 0; i--) { | |
bdca6dae CD |
316 | if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
317 | (0x01 << i)) | |
ce082596 JR |
318 | break; |
319 | } | |
320 | ||
eda936ef | 321 | nand_onfi_timing_set(denali, i); |
ce082596 | 322 | |
43914a2d MY |
323 | /* |
324 | * By now, all the ONFI devices we know support the page cache | |
325 | * rw feature. So here we enable the pipeline_rw_ahead feature | |
326 | */ | |
ce082596 JR |
327 | /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */ |
328 | /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */ | |
329 | ||
330 | return PASS; | |
331 | } | |
332 | ||
4c03bbdf CD |
333 | static void get_samsung_nand_para(struct denali_nand_info *denali, |
334 | uint8_t device_id) | |
ce082596 | 335 | { |
4c03bbdf | 336 | if (device_id == 0xd3) { /* Samsung K9WAG08U1A */ |
ce082596 | 337 | /* Set timing register values according to datasheet */ |
24c3fa36 CD |
338 | iowrite32(5, denali->flash_reg + ACC_CLKS); |
339 | iowrite32(20, denali->flash_reg + RE_2_WE); | |
340 | iowrite32(12, denali->flash_reg + WE_2_RE); | |
341 | iowrite32(14, denali->flash_reg + ADDR_2_DATA); | |
342 | iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT); | |
343 | iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT); | |
344 | iowrite32(2, denali->flash_reg + CS_SETUP_CNT); | |
ce082596 | 345 | } |
ce082596 JR |
346 | } |
347 | ||
348 | static void get_toshiba_nand_para(struct denali_nand_info *denali) | |
349 | { | |
ce082596 JR |
350 | uint32_t tmp; |
351 | ||
43914a2d MY |
352 | /* |
353 | * Workaround to fix a controller bug which reports a wrong | |
354 | * spare area size for some kind of Toshiba NAND device | |
355 | */ | |
ce082596 JR |
356 | if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && |
357 | (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { | |
24c3fa36 | 358 | iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); |
ce082596 JR |
359 | tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) * |
360 | ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
24c3fa36 | 361 | iowrite32(tmp, |
bdca6dae | 362 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
ce082596 | 363 | #if SUPPORT_15BITECC |
24c3fa36 | 364 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 365 | #elif SUPPORT_8BITECC |
24c3fa36 | 366 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 JR |
367 | #endif |
368 | } | |
ce082596 JR |
369 | } |
370 | ||
ef41e1bb CD |
371 | static void get_hynix_nand_para(struct denali_nand_info *denali, |
372 | uint8_t device_id) | |
ce082596 | 373 | { |
ce082596 JR |
374 | uint32_t main_size, spare_size; |
375 | ||
ef41e1bb | 376 | switch (device_id) { |
ce082596 JR |
377 | case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */ |
378 | case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */ | |
24c3fa36 CD |
379 | iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK); |
380 | iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); | |
381 | iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
bdca6dae CD |
382 | main_size = 4096 * |
383 | ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
384 | spare_size = 224 * | |
385 | ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
24c3fa36 | 386 | iowrite32(main_size, |
bdca6dae | 387 | denali->flash_reg + LOGICAL_PAGE_DATA_SIZE); |
24c3fa36 | 388 | iowrite32(spare_size, |
bdca6dae | 389 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
24c3fa36 | 390 | iowrite32(0, denali->flash_reg + DEVICE_WIDTH); |
ce082596 | 391 | #if SUPPORT_15BITECC |
24c3fa36 | 392 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 393 | #elif SUPPORT_8BITECC |
24c3fa36 | 394 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 395 | #endif |
ce082596 JR |
396 | break; |
397 | default: | |
84457949 | 398 | dev_warn(denali->dev, |
789ccf17 | 399 | "Unknown Hynix NAND (Device ID: 0x%x).\n" |
8125450c MY |
400 | "Will use default parameter values instead.\n", |
401 | device_id); | |
ce082596 JR |
402 | } |
403 | } | |
404 | ||
43914a2d MY |
405 | /* |
406 | * determines how many NAND chips are connected to the controller. Note for | |
b292c341 | 407 | * Intel CE4100 devices we don't support more than one device. |
ce082596 JR |
408 | */ |
409 | static void find_valid_banks(struct denali_nand_info *denali) | |
410 | { | |
c89eeda8 | 411 | uint32_t id[denali->max_banks]; |
ce082596 JR |
412 | int i; |
413 | ||
414 | denali->total_used_banks = 1; | |
c89eeda8 | 415 | for (i = 0; i < denali->max_banks; i++) { |
3157d1ed MY |
416 | index_addr(denali, MODE_11 | (i << 24) | 0, 0x90); |
417 | index_addr(denali, MODE_11 | (i << 24) | 1, 0); | |
8125450c | 418 | index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]); |
ce082596 | 419 | |
84457949 | 420 | dev_dbg(denali->dev, |
ce082596 JR |
421 | "Return 1st ID for bank[%d]: %x\n", i, id[i]); |
422 | ||
423 | if (i == 0) { | |
424 | if (!(id[i] & 0x0ff)) | |
425 | break; /* WTF? */ | |
426 | } else { | |
427 | if ((id[i] & 0x0ff) == (id[0] & 0x0ff)) | |
428 | denali->total_used_banks++; | |
429 | else | |
430 | break; | |
431 | } | |
432 | } | |
433 | ||
345b1d3b | 434 | if (denali->platform == INTEL_CE4100) { |
43914a2d MY |
435 | /* |
436 | * Platform limitations of the CE4100 device limit | |
ce082596 | 437 | * users to a single chip solution for NAND. |
5bac3acf C |
438 | * Multichip support is not enabled. |
439 | */ | |
345b1d3b | 440 | if (denali->total_used_banks != 1) { |
84457949 | 441 | dev_err(denali->dev, |
8125450c | 442 | "Sorry, Intel CE4100 only supports a single NAND device.\n"); |
ce082596 JR |
443 | BUG(); |
444 | } | |
445 | } | |
84457949 | 446 | dev_dbg(denali->dev, |
ce082596 JR |
447 | "denali->total_used_banks: %d\n", denali->total_used_banks); |
448 | } | |
449 | ||
c89eeda8 JI |
450 | /* |
451 | * Use the configuration feature register to determine the maximum number of | |
452 | * banks that the hardware supports. | |
453 | */ | |
454 | static void detect_max_banks(struct denali_nand_info *denali) | |
455 | { | |
456 | uint32_t features = ioread32(denali->flash_reg + FEATURES); | |
271707b1 GM |
457 | /* |
458 | * Read the revision register, so we can calculate the max_banks | |
459 | * properly: the encoding changed from rev 5.0 to 5.1 | |
460 | */ | |
461 | u32 revision = MAKE_COMPARABLE_REVISION( | |
462 | ioread32(denali->flash_reg + REVISION)); | |
c89eeda8 | 463 | |
271707b1 GM |
464 | if (revision < REVISION_5_1) |
465 | denali->max_banks = 2 << (features & FEATURES__N_BANKS); | |
466 | else | |
467 | denali->max_banks = 1 << (features & FEATURES__N_BANKS); | |
c89eeda8 JI |
468 | } |
469 | ||
eda936ef | 470 | static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) |
ce082596 JR |
471 | { |
472 | uint16_t status = PASS; | |
d68a5c3d | 473 | uint32_t id_bytes[8], addr; |
93e3c8ad MY |
474 | uint8_t maf_id, device_id; |
475 | int i; | |
ce082596 | 476 | |
43914a2d MY |
477 | /* |
478 | * Use read id method to get device ID and other params. | |
479 | * For some NAND chips, controller can't report the correct | |
480 | * device ID by reading from DEVICE_ID register | |
481 | */ | |
3157d1ed MY |
482 | addr = MODE_11 | BANK(denali->flash_bank); |
483 | index_addr(denali, addr | 0, 0x90); | |
484 | index_addr(denali, addr | 1, 0); | |
d68a5c3d | 485 | for (i = 0; i < 8; i++) |
ef41e1bb CD |
486 | index_addr_read_data(denali, addr | 2, &id_bytes[i]); |
487 | maf_id = id_bytes[0]; | |
488 | device_id = id_bytes[1]; | |
ce082596 JR |
489 | |
490 | if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & | |
491 | ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ | |
492 | if (FAIL == get_onfi_nand_para(denali)) | |
493 | return FAIL; | |
ef41e1bb | 494 | } else if (maf_id == 0xEC) { /* Samsung NAND */ |
4c03bbdf | 495 | get_samsung_nand_para(denali, device_id); |
ef41e1bb | 496 | } else if (maf_id == 0x98) { /* Toshiba NAND */ |
ce082596 | 497 | get_toshiba_nand_para(denali); |
ef41e1bb CD |
498 | } else if (maf_id == 0xAD) { /* Hynix NAND */ |
499 | get_hynix_nand_para(denali, device_id); | |
ce082596 JR |
500 | } |
501 | ||
84457949 | 502 | dev_info(denali->dev, |
8125450c | 503 | "Dump timing register values:\n" |
7cfffac0 CD |
504 | "acc_clks: %d, re_2_we: %d, re_2_re: %d\n" |
505 | "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n" | |
ce082596 JR |
506 | "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", |
507 | ioread32(denali->flash_reg + ACC_CLKS), | |
508 | ioread32(denali->flash_reg + RE_2_WE), | |
7cfffac0 | 509 | ioread32(denali->flash_reg + RE_2_RE), |
ce082596 JR |
510 | ioread32(denali->flash_reg + WE_2_RE), |
511 | ioread32(denali->flash_reg + ADDR_2_DATA), | |
512 | ioread32(denali->flash_reg + RDWR_EN_LO_CNT), | |
513 | ioread32(denali->flash_reg + RDWR_EN_HI_CNT), | |
514 | ioread32(denali->flash_reg + CS_SETUP_CNT)); | |
515 | ||
ce082596 JR |
516 | find_valid_banks(denali); |
517 | ||
43914a2d MY |
518 | /* |
519 | * If the user specified to override the default timings | |
5bac3acf | 520 | * with a specific ONFI mode, we apply those changes here. |
ce082596 JR |
521 | */ |
522 | if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) | |
eda936ef | 523 | nand_onfi_timing_set(denali, onfi_timing_mode); |
ce082596 JR |
524 | |
525 | return status; | |
526 | } | |
527 | ||
eda936ef | 528 | static void denali_set_intr_modes(struct denali_nand_info *denali, |
ce082596 JR |
529 | uint16_t INT_ENABLE) |
530 | { | |
ce082596 | 531 | if (INT_ENABLE) |
24c3fa36 | 532 | iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE); |
ce082596 | 533 | else |
24c3fa36 | 534 | iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE); |
ce082596 JR |
535 | } |
536 | ||
43914a2d MY |
537 | /* |
538 | * validation function to verify that the controlling software is making | |
b292c341 | 539 | * a valid request |
ce082596 JR |
540 | */ |
541 | static inline bool is_flash_bank_valid(int flash_bank) | |
542 | { | |
7d14ecd0 | 543 | return flash_bank >= 0 && flash_bank < 4; |
ce082596 JR |
544 | } |
545 | ||
546 | static void denali_irq_init(struct denali_nand_info *denali) | |
547 | { | |
5637b69d | 548 | uint32_t int_mask; |
9589bf5b | 549 | int i; |
ce082596 JR |
550 | |
551 | /* Disable global interrupts */ | |
eda936ef | 552 | denali_set_intr_modes(denali, false); |
ce082596 JR |
553 | |
554 | int_mask = DENALI_IRQ_ALL; | |
555 | ||
556 | /* Clear all status bits */ | |
c89eeda8 | 557 | for (i = 0; i < denali->max_banks; ++i) |
9589bf5b | 558 | iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i)); |
ce082596 JR |
559 | |
560 | denali_irq_enable(denali, int_mask); | |
561 | } | |
562 | ||
563 | static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali) | |
564 | { | |
eda936ef | 565 | denali_set_intr_modes(denali, false); |
ce082596 JR |
566 | } |
567 | ||
bdca6dae CD |
568 | static void denali_irq_enable(struct denali_nand_info *denali, |
569 | uint32_t int_mask) | |
ce082596 | 570 | { |
9589bf5b JI |
571 | int i; |
572 | ||
c89eeda8 | 573 | for (i = 0; i < denali->max_banks; ++i) |
9589bf5b | 574 | iowrite32(int_mask, denali->flash_reg + INTR_EN(i)); |
ce082596 JR |
575 | } |
576 | ||
43914a2d MY |
577 | /* |
578 | * This function only returns when an interrupt that this driver cares about | |
5bac3acf | 579 | * occurs. This is to reduce the overhead of servicing interrupts |
ce082596 JR |
580 | */ |
581 | static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) | |
582 | { | |
a99d1796 | 583 | return read_interrupt_status(denali) & DENALI_IRQ_ALL; |
ce082596 JR |
584 | } |
585 | ||
586 | /* Interrupts are cleared by writing a 1 to the appropriate status bit */ | |
bdca6dae CD |
587 | static inline void clear_interrupt(struct denali_nand_info *denali, |
588 | uint32_t irq_mask) | |
ce082596 | 589 | { |
5637b69d | 590 | uint32_t intr_status_reg; |
ce082596 | 591 | |
9589bf5b | 592 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
ce082596 | 593 | |
24c3fa36 | 594 | iowrite32(irq_mask, denali->flash_reg + intr_status_reg); |
ce082596 JR |
595 | } |
596 | ||
597 | static void clear_interrupts(struct denali_nand_info *denali) | |
598 | { | |
5637b69d MY |
599 | uint32_t status; |
600 | ||
ce082596 JR |
601 | spin_lock_irq(&denali->irq_lock); |
602 | ||
603 | status = read_interrupt_status(denali); | |
8ae61ebd | 604 | clear_interrupt(denali, status); |
ce082596 | 605 | |
ce082596 JR |
606 | denali->irq_status = 0x0; |
607 | spin_unlock_irq(&denali->irq_lock); | |
608 | } | |
609 | ||
610 | static uint32_t read_interrupt_status(struct denali_nand_info *denali) | |
611 | { | |
5637b69d | 612 | uint32_t intr_status_reg; |
ce082596 | 613 | |
9589bf5b | 614 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
ce082596 JR |
615 | |
616 | return ioread32(denali->flash_reg + intr_status_reg); | |
617 | } | |
618 | ||
43914a2d MY |
619 | /* |
620 | * This is the interrupt service routine. It handles all interrupts | |
621 | * sent to this device. Note that on CE4100, this is a shared interrupt. | |
ce082596 JR |
622 | */ |
623 | static irqreturn_t denali_isr(int irq, void *dev_id) | |
624 | { | |
625 | struct denali_nand_info *denali = dev_id; | |
5637b69d | 626 | uint32_t irq_status; |
ce082596 JR |
627 | irqreturn_t result = IRQ_NONE; |
628 | ||
629 | spin_lock(&denali->irq_lock); | |
630 | ||
43914a2d | 631 | /* check to see if a valid NAND chip has been selected. */ |
345b1d3b | 632 | if (is_flash_bank_valid(denali->flash_bank)) { |
43914a2d MY |
633 | /* |
634 | * check to see if controller generated the interrupt, | |
635 | * since this is a shared interrupt | |
636 | */ | |
bdca6dae CD |
637 | irq_status = denali_irq_detected(denali); |
638 | if (irq_status != 0) { | |
ce082596 JR |
639 | /* handle interrupt */ |
640 | /* first acknowledge it */ | |
641 | clear_interrupt(denali, irq_status); | |
43914a2d MY |
642 | /* |
643 | * store the status in the device context for someone | |
644 | * to read | |
645 | */ | |
ce082596 JR |
646 | denali->irq_status |= irq_status; |
647 | /* notify anyone who cares that it happened */ | |
648 | complete(&denali->complete); | |
649 | /* tell the OS that we've handled this */ | |
650 | result = IRQ_HANDLED; | |
651 | } | |
652 | } | |
653 | spin_unlock(&denali->irq_lock); | |
654 | return result; | |
655 | } | |
656 | #define BANK(x) ((x) << 24) | |
657 | ||
658 | static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) | |
659 | { | |
5637b69d MY |
660 | unsigned long comp_res; |
661 | uint32_t intr_status; | |
ce082596 JR |
662 | unsigned long timeout = msecs_to_jiffies(1000); |
663 | ||
345b1d3b | 664 | do { |
bdca6dae CD |
665 | comp_res = |
666 | wait_for_completion_timeout(&denali->complete, timeout); | |
ce082596 JR |
667 | spin_lock_irq(&denali->irq_lock); |
668 | intr_status = denali->irq_status; | |
669 | ||
345b1d3b | 670 | if (intr_status & irq_mask) { |
ce082596 JR |
671 | denali->irq_status &= ~irq_mask; |
672 | spin_unlock_irq(&denali->irq_lock); | |
ce082596 JR |
673 | /* our interrupt was detected */ |
674 | break; | |
ce082596 | 675 | } |
8125450c MY |
676 | |
677 | /* | |
678 | * these are not the interrupts you are looking for - | |
679 | * need to wait again | |
680 | */ | |
681 | spin_unlock_irq(&denali->irq_lock); | |
ce082596 JR |
682 | } while (comp_res != 0); |
683 | ||
345b1d3b | 684 | if (comp_res == 0) { |
ce082596 | 685 | /* timeout */ |
2a0a288e | 686 | pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n", |
5bac3acf | 687 | intr_status, irq_mask); |
ce082596 JR |
688 | |
689 | intr_status = 0; | |
690 | } | |
691 | return intr_status; | |
692 | } | |
693 | ||
43914a2d MY |
694 | /* |
695 | * This helper function setups the registers for ECC and whether or not | |
696 | * the spare area will be transferred. | |
697 | */ | |
5bac3acf | 698 | static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, |
ce082596 JR |
699 | bool transfer_spare) |
700 | { | |
5637b69d | 701 | int ecc_en_flag, transfer_spare_flag; |
ce082596 JR |
702 | |
703 | /* set ECC, transfer spare bits if needed */ | |
704 | ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; | |
705 | transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0; | |
706 | ||
707 | /* Enable spare area/ECC per user's request. */ | |
24c3fa36 | 708 | iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE); |
8125450c | 709 | iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG); |
ce082596 JR |
710 | } |
711 | ||
43914a2d MY |
712 | /* |
713 | * sends a pipeline command operation to the controller. See the Denali NAND | |
b292c341 | 714 | * controller's user guide for more information (section 4.2.3.6). |
ce082596 | 715 | */ |
bdca6dae | 716 | static int denali_send_pipeline_cmd(struct denali_nand_info *denali, |
8125450c MY |
717 | bool ecc_en, bool transfer_spare, |
718 | int access_type, int op) | |
ce082596 JR |
719 | { |
720 | int status = PASS; | |
5637b69d MY |
721 | uint32_t page_count = 1; |
722 | uint32_t addr, cmd, irq_status, irq_mask; | |
ce082596 | 723 | |
a99d1796 | 724 | if (op == DENALI_READ) |
9589bf5b | 725 | irq_mask = INTR_STATUS__LOAD_COMP; |
a99d1796 CD |
726 | else if (op == DENALI_WRITE) |
727 | irq_mask = 0; | |
728 | else | |
729 | BUG(); | |
ce082596 JR |
730 | |
731 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); | |
732 | ||
5bac3acf | 733 | clear_interrupts(denali); |
ce082596 JR |
734 | |
735 | addr = BANK(denali->flash_bank) | denali->page; | |
736 | ||
345b1d3b | 737 | if (op == DENALI_WRITE && access_type != SPARE_ACCESS) { |
5bac3acf | 738 | cmd = MODE_01 | addr; |
24c3fa36 | 739 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 740 | } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) { |
ce082596 | 741 | /* read spare area */ |
5bac3acf | 742 | cmd = MODE_10 | addr; |
3157d1ed | 743 | index_addr(denali, cmd, access_type); |
ce082596 | 744 | |
5bac3acf | 745 | cmd = MODE_01 | addr; |
24c3fa36 | 746 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 747 | } else if (op == DENALI_READ) { |
ce082596 | 748 | /* setup page read request for access type */ |
5bac3acf | 749 | cmd = MODE_10 | addr; |
3157d1ed | 750 | index_addr(denali, cmd, access_type); |
ce082596 | 751 | |
43914a2d MY |
752 | /* |
753 | * page 33 of the NAND controller spec indicates we should not | |
754 | * use the pipeline commands in Spare area only mode. | |
755 | * So we don't. | |
ce082596 | 756 | */ |
345b1d3b | 757 | if (access_type == SPARE_ACCESS) { |
ce082596 | 758 | cmd = MODE_01 | addr; |
24c3fa36 | 759 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 760 | } else { |
3157d1ed | 761 | index_addr(denali, cmd, |
2902330e | 762 | PIPELINE_ACCESS | op | page_count); |
5bac3acf | 763 | |
43914a2d MY |
764 | /* |
765 | * wait for command to be accepted | |
bdca6dae | 766 | * can always use status0 bit as the |
43914a2d MY |
767 | * mask is identical for each bank. |
768 | */ | |
ce082596 JR |
769 | irq_status = wait_for_irq(denali, irq_mask); |
770 | ||
345b1d3b | 771 | if (irq_status == 0) { |
84457949 | 772 | dev_err(denali->dev, |
8125450c MY |
773 | "cmd, page, addr on timeout (0x%x, 0x%x, 0x%x)\n", |
774 | cmd, denali->page, addr); | |
ce082596 | 775 | status = FAIL; |
345b1d3b | 776 | } else { |
ce082596 | 777 | cmd = MODE_01 | addr; |
24c3fa36 | 778 | iowrite32(cmd, denali->flash_mem); |
ce082596 JR |
779 | } |
780 | } | |
781 | } | |
782 | return status; | |
783 | } | |
784 | ||
785 | /* helper function that simply writes a buffer to the flash */ | |
bdca6dae | 786 | static int write_data_to_flash_mem(struct denali_nand_info *denali, |
8125450c | 787 | const uint8_t *buf, int len) |
ce082596 | 788 | { |
93e3c8ad MY |
789 | uint32_t *buf32; |
790 | int i; | |
ce082596 | 791 | |
43914a2d MY |
792 | /* |
793 | * verify that the len is a multiple of 4. | |
794 | * see comment in read_data_from_flash_mem() | |
795 | */ | |
ce082596 JR |
796 | BUG_ON((len % 4) != 0); |
797 | ||
798 | /* write the data to the flash memory */ | |
799 | buf32 = (uint32_t *)buf; | |
800 | for (i = 0; i < len / 4; i++) | |
24c3fa36 | 801 | iowrite32(*buf32++, denali->flash_mem + 0x10); |
8125450c | 802 | return i * 4; /* intent is to return the number of bytes read */ |
ce082596 JR |
803 | } |
804 | ||
805 | /* helper function that simply reads a buffer from the flash */ | |
bdca6dae | 806 | static int read_data_from_flash_mem(struct denali_nand_info *denali, |
8125450c | 807 | uint8_t *buf, int len) |
ce082596 | 808 | { |
93e3c8ad MY |
809 | uint32_t *buf32; |
810 | int i; | |
ce082596 | 811 | |
43914a2d MY |
812 | /* |
813 | * we assume that len will be a multiple of 4, if not it would be nice | |
814 | * to know about it ASAP rather than have random failures... | |
815 | * This assumption is based on the fact that this function is designed | |
816 | * to be used to read flash pages, which are typically multiples of 4. | |
ce082596 | 817 | */ |
ce082596 JR |
818 | BUG_ON((len % 4) != 0); |
819 | ||
820 | /* transfer the data from the flash */ | |
821 | buf32 = (uint32_t *)buf; | |
822 | for (i = 0; i < len / 4; i++) | |
ce082596 | 823 | *buf32++ = ioread32(denali->flash_mem + 0x10); |
8125450c | 824 | return i * 4; /* intent is to return the number of bytes read */ |
ce082596 JR |
825 | } |
826 | ||
827 | /* writes OOB data to the device */ | |
828 | static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
829 | { | |
830 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
5637b69d | 831 | uint32_t irq_status; |
9589bf5b JI |
832 | uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP | |
833 | INTR_STATUS__PROGRAM_FAIL; | |
ce082596 JR |
834 | int status = 0; |
835 | ||
836 | denali->page = page; | |
837 | ||
5bac3acf | 838 | if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS, |
345b1d3b | 839 | DENALI_WRITE) == PASS) { |
ce082596 JR |
840 | write_data_to_flash_mem(denali, buf, mtd->oobsize); |
841 | ||
ce082596 JR |
842 | /* wait for operation to complete */ |
843 | irq_status = wait_for_irq(denali, irq_mask); | |
844 | ||
345b1d3b | 845 | if (irq_status == 0) { |
84457949 | 846 | dev_err(denali->dev, "OOB write failed\n"); |
ce082596 JR |
847 | status = -EIO; |
848 | } | |
345b1d3b | 849 | } else { |
84457949 | 850 | dev_err(denali->dev, "unable to send pipeline command\n"); |
5bac3acf | 851 | status = -EIO; |
ce082596 JR |
852 | } |
853 | return status; | |
854 | } | |
855 | ||
856 | /* reads OOB data from the device */ | |
857 | static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
858 | { | |
859 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
5637b69d MY |
860 | uint32_t irq_mask = INTR_STATUS__LOAD_COMP; |
861 | uint32_t irq_status, addr, cmd; | |
ce082596 JR |
862 | |
863 | denali->page = page; | |
864 | ||
5bac3acf | 865 | if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, |
345b1d3b | 866 | DENALI_READ) == PASS) { |
5bac3acf | 867 | read_data_from_flash_mem(denali, buf, mtd->oobsize); |
ce082596 | 868 | |
43914a2d MY |
869 | /* |
870 | * wait for command to be accepted | |
871 | * can always use status0 bit as the | |
872 | * mask is identical for each bank. | |
873 | */ | |
ce082596 JR |
874 | irq_status = wait_for_irq(denali, irq_mask); |
875 | ||
876 | if (irq_status == 0) | |
84457949 | 877 | dev_err(denali->dev, "page on OOB timeout %d\n", |
bdca6dae | 878 | denali->page); |
ce082596 | 879 | |
43914a2d MY |
880 | /* |
881 | * We set the device back to MAIN_ACCESS here as I observed | |
ce082596 JR |
882 | * instability with the controller if you do a block erase |
883 | * and the last transaction was a SPARE_ACCESS. Block erase | |
884 | * is reliable (according to the MTD test infrastructure) | |
5bac3acf | 885 | * if you are in MAIN_ACCESS. |
ce082596 JR |
886 | */ |
887 | addr = BANK(denali->flash_bank) | denali->page; | |
5bac3acf | 888 | cmd = MODE_10 | addr; |
3157d1ed | 889 | index_addr(denali, cmd, MAIN_ACCESS); |
ce082596 JR |
890 | } |
891 | } | |
892 | ||
43914a2d MY |
893 | /* |
894 | * this function examines buffers to see if they contain data that | |
ce082596 JR |
895 | * indicate that the buffer is part of an erased region of flash. |
896 | */ | |
919193ce | 897 | static bool is_erased(uint8_t *buf, int len) |
ce082596 | 898 | { |
5637b69d | 899 | int i; |
8125450c | 900 | |
ce082596 | 901 | for (i = 0; i < len; i++) |
ce082596 | 902 | if (buf[i] != 0xFF) |
ce082596 | 903 | return false; |
ce082596 JR |
904 | return true; |
905 | } | |
906 | #define ECC_SECTOR_SIZE 512 | |
907 | ||
908 | #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12) | |
909 | #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET)) | |
910 | #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK) | |
8ae61ebd CD |
911 | #define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE)) |
912 | #define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8) | |
ce082596 JR |
913 | #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO) |
914 | ||
5bac3acf | 915 | static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, |
3f91e94f | 916 | uint32_t irq_status, unsigned int *max_bitflips) |
ce082596 JR |
917 | { |
918 | bool check_erased_page = false; | |
3f91e94f | 919 | unsigned int bitflips = 0; |
ce082596 | 920 | |
9589bf5b | 921 | if (irq_status & INTR_STATUS__ECC_ERR) { |
ce082596 | 922 | /* read the ECC errors. we'll ignore them for now */ |
5637b69d MY |
923 | uint32_t err_address, err_correction_info, err_byte, |
924 | err_sector, err_device, err_correction_value; | |
8ae61ebd | 925 | denali_set_intr_modes(denali, false); |
ce082596 | 926 | |
345b1d3b | 927 | do { |
5bac3acf | 928 | err_address = ioread32(denali->flash_reg + |
ce082596 JR |
929 | ECC_ERROR_ADDRESS); |
930 | err_sector = ECC_SECTOR(err_address); | |
931 | err_byte = ECC_BYTE(err_address); | |
932 | ||
5bac3acf | 933 | err_correction_info = ioread32(denali->flash_reg + |
ce082596 | 934 | ERR_CORRECTION_INFO); |
5bac3acf | 935 | err_correction_value = |
ce082596 JR |
936 | ECC_CORRECTION_VALUE(err_correction_info); |
937 | err_device = ECC_ERR_DEVICE(err_correction_info); | |
938 | ||
345b1d3b | 939 | if (ECC_ERROR_CORRECTABLE(err_correction_info)) { |
43914a2d MY |
940 | /* |
941 | * If err_byte is larger than ECC_SECTOR_SIZE, | |
25985edc | 942 | * means error happened in OOB, so we ignore |
8ae61ebd CD |
943 | * it. It's no need for us to correct it |
944 | * err_device is represented the NAND error | |
945 | * bits are happened in if there are more | |
946 | * than one NAND connected. | |
43914a2d | 947 | */ |
8ae61ebd | 948 | if (err_byte < ECC_SECTOR_SIZE) { |
442f201b BB |
949 | struct mtd_info *mtd = |
950 | nand_to_mtd(&denali->nand); | |
8ae61ebd | 951 | int offset; |
8125450c | 952 | |
8ae61ebd CD |
953 | offset = (err_sector * |
954 | ECC_SECTOR_SIZE + | |
955 | err_byte) * | |
956 | denali->devnum + | |
957 | err_device; | |
ce082596 JR |
958 | /* correct the ECC error */ |
959 | buf[offset] ^= err_correction_value; | |
442f201b | 960 | mtd->ecc_stats.corrected++; |
3f91e94f | 961 | bitflips++; |
ce082596 | 962 | } |
345b1d3b | 963 | } else { |
43914a2d MY |
964 | /* |
965 | * if the error is not correctable, need to | |
bdca6dae CD |
966 | * look at the page to see if it is an erased |
967 | * page. if so, then it's not a real ECC error | |
43914a2d | 968 | */ |
ce082596 JR |
969 | check_erased_page = true; |
970 | } | |
ce082596 | 971 | } while (!ECC_LAST_ERR(err_correction_info)); |
43914a2d MY |
972 | /* |
973 | * Once handle all ecc errors, controller will triger | |
8ae61ebd CD |
974 | * a ECC_TRANSACTION_DONE interrupt, so here just wait |
975 | * for a while for this interrupt | |
43914a2d | 976 | */ |
8ae61ebd | 977 | while (!(read_interrupt_status(denali) & |
9589bf5b | 978 | INTR_STATUS__ECC_TRANSACTION_DONE)) |
8ae61ebd CD |
979 | cpu_relax(); |
980 | clear_interrupts(denali); | |
981 | denali_set_intr_modes(denali, true); | |
ce082596 | 982 | } |
3f91e94f | 983 | *max_bitflips = bitflips; |
ce082596 JR |
984 | return check_erased_page; |
985 | } | |
986 | ||
987 | /* programs the controller to either enable/disable DMA transfers */ | |
aadff49c | 988 | static void denali_enable_dma(struct denali_nand_info *denali, bool en) |
ce082596 | 989 | { |
5637b69d | 990 | iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE); |
ce082596 JR |
991 | ioread32(denali->flash_reg + DMA_ENABLE); |
992 | } | |
993 | ||
994 | /* setups the HW to perform the data DMA */ | |
aadff49c | 995 | static void denali_setup_dma(struct denali_nand_info *denali, int op) |
ce082596 | 996 | { |
5637b69d | 997 | uint32_t mode; |
ce082596 | 998 | const int page_count = 1; |
3157d1ed | 999 | uint32_t addr = denali->buf.dma_buf; |
ce082596 JR |
1000 | |
1001 | mode = MODE_10 | BANK(denali->flash_bank); | |
1002 | ||
1003 | /* DMA is a four step process */ | |
1004 | ||
1005 | /* 1. setup transfer type and # of pages */ | |
1006 | index_addr(denali, mode | denali->page, 0x2000 | op | page_count); | |
1007 | ||
1008 | /* 2. set memory high address bits 23:8 */ | |
3157d1ed | 1009 | index_addr(denali, mode | ((addr >> 16) << 8), 0x2200); |
ce082596 JR |
1010 | |
1011 | /* 3. set memory low address bits 23:8 */ | |
7c272ac5 | 1012 | index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300); |
ce082596 | 1013 | |
43914a2d | 1014 | /* 4. interrupt when complete, burst len = 64 bytes */ |
ce082596 JR |
1015 | index_addr(denali, mode | 0x14000, 0x2400); |
1016 | } | |
1017 | ||
43914a2d MY |
1018 | /* |
1019 | * writes a page. user specifies type, and this function handles the | |
1020 | * configuration details. | |
1021 | */ | |
fdbad98d | 1022 | static int write_page(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1023 | const uint8_t *buf, bool raw_xfer) |
1024 | { | |
1025 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ce082596 | 1026 | dma_addr_t addr = denali->buf.dma_buf; |
442f201b | 1027 | size_t size = mtd->writesize + mtd->oobsize; |
5637b69d | 1028 | uint32_t irq_status; |
9589bf5b JI |
1029 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP | |
1030 | INTR_STATUS__PROGRAM_FAIL; | |
ce082596 | 1031 | |
43914a2d MY |
1032 | /* |
1033 | * if it is a raw xfer, we want to disable ecc and send the spare area. | |
ce082596 JR |
1034 | * !raw_xfer - enable ecc |
1035 | * raw_xfer - transfer spare | |
1036 | */ | |
1037 | setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer); | |
1038 | ||
1039 | /* copy buffer into DMA buffer */ | |
1040 | memcpy(denali->buf.buf, buf, mtd->writesize); | |
1041 | ||
345b1d3b | 1042 | if (raw_xfer) { |
ce082596 | 1043 | /* transfer the data to the spare area */ |
5bac3acf C |
1044 | memcpy(denali->buf.buf + mtd->writesize, |
1045 | chip->oob_poi, | |
1046 | mtd->oobsize); | |
ce082596 JR |
1047 | } |
1048 | ||
84457949 | 1049 | dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE); |
ce082596 JR |
1050 | |
1051 | clear_interrupts(denali); | |
5bac3acf | 1052 | denali_enable_dma(denali, true); |
ce082596 | 1053 | |
aadff49c | 1054 | denali_setup_dma(denali, DENALI_WRITE); |
ce082596 JR |
1055 | |
1056 | /* wait for operation to complete */ | |
1057 | irq_status = wait_for_irq(denali, irq_mask); | |
1058 | ||
345b1d3b | 1059 | if (irq_status == 0) { |
8125450c MY |
1060 | dev_err(denali->dev, "timeout on write_page (type = %d)\n", |
1061 | raw_xfer); | |
c115add9 | 1062 | denali->status = NAND_STATUS_FAIL; |
ce082596 JR |
1063 | } |
1064 | ||
5bac3acf | 1065 | denali_enable_dma(denali, false); |
84457949 | 1066 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE); |
fdbad98d JW |
1067 | |
1068 | return 0; | |
ce082596 JR |
1069 | } |
1070 | ||
1071 | /* NAND core entry points */ | |
1072 | ||
43914a2d MY |
1073 | /* |
1074 | * this is the callback that the NAND core calls to write a page. Since | |
b292c341 CD |
1075 | * writing a page with ECC or without is similar, all the work is done |
1076 | * by write_page above. | |
43914a2d | 1077 | */ |
fdbad98d | 1078 | static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 | 1079 | const uint8_t *buf, int oob_required, int page) |
ce082596 | 1080 | { |
43914a2d MY |
1081 | /* |
1082 | * for regular page writes, we let HW handle all the ECC | |
1083 | * data written to the device. | |
1084 | */ | |
fdbad98d | 1085 | return write_page(mtd, chip, buf, false); |
ce082596 JR |
1086 | } |
1087 | ||
43914a2d MY |
1088 | /* |
1089 | * This is the callback that the NAND core calls to write a page without ECC. | |
25985edc | 1090 | * raw access is similar to ECC page writes, so all the work is done in the |
b292c341 | 1091 | * write_page() function above. |
ce082596 | 1092 | */ |
fdbad98d | 1093 | static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 BB |
1094 | const uint8_t *buf, int oob_required, |
1095 | int page) | |
ce082596 | 1096 | { |
43914a2d MY |
1097 | /* |
1098 | * for raw page writes, we want to disable ECC and simply write | |
1099 | * whatever data is in the buffer. | |
1100 | */ | |
fdbad98d | 1101 | return write_page(mtd, chip, buf, true); |
ce082596 JR |
1102 | } |
1103 | ||
5bac3acf | 1104 | static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1105 | int page) |
1106 | { | |
5bac3acf | 1107 | return write_oob_data(mtd, chip->oob_poi, page); |
ce082596 JR |
1108 | } |
1109 | ||
5bac3acf | 1110 | static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, |
5c2ffb11 | 1111 | int page) |
ce082596 JR |
1112 | { |
1113 | read_oob_data(mtd, chip->oob_poi, page); | |
1114 | ||
5c2ffb11 | 1115 | return 0; |
ce082596 JR |
1116 | } |
1117 | ||
1118 | static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1119 | uint8_t *buf, int oob_required, int page) |
ce082596 | 1120 | { |
3f91e94f | 1121 | unsigned int max_bitflips; |
ce082596 | 1122 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
ce082596 JR |
1123 | |
1124 | dma_addr_t addr = denali->buf.dma_buf; | |
442f201b | 1125 | size_t size = mtd->writesize + mtd->oobsize; |
ce082596 | 1126 | |
5637b69d | 1127 | uint32_t irq_status; |
9589bf5b JI |
1128 | uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE | |
1129 | INTR_STATUS__ECC_ERR; | |
ce082596 JR |
1130 | bool check_erased_page = false; |
1131 | ||
7d8a26fd | 1132 | if (page != denali->page) { |
8125450c MY |
1133 | dev_err(denali->dev, |
1134 | "IN %s: page %d is not equal to denali->page %d", | |
1135 | __func__, page, denali->page); | |
7d8a26fd CD |
1136 | BUG(); |
1137 | } | |
1138 | ||
ce082596 JR |
1139 | setup_ecc_for_xfer(denali, true, false); |
1140 | ||
aadff49c | 1141 | denali_enable_dma(denali, true); |
84457949 | 1142 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1143 | |
1144 | clear_interrupts(denali); | |
aadff49c | 1145 | denali_setup_dma(denali, DENALI_READ); |
ce082596 JR |
1146 | |
1147 | /* wait for operation to complete */ | |
1148 | irq_status = wait_for_irq(denali, irq_mask); | |
1149 | ||
84457949 | 1150 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1151 | |
1152 | memcpy(buf, denali->buf.buf, mtd->writesize); | |
5bac3acf | 1153 | |
3f91e94f | 1154 | check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips); |
aadff49c | 1155 | denali_enable_dma(denali, false); |
ce082596 | 1156 | |
345b1d3b | 1157 | if (check_erased_page) { |
442f201b | 1158 | read_oob_data(mtd, chip->oob_poi, denali->page); |
ce082596 JR |
1159 | |
1160 | /* check ECC failures that may have occurred on erased pages */ | |
345b1d3b | 1161 | if (check_erased_page) { |
442f201b BB |
1162 | if (!is_erased(buf, mtd->writesize)) |
1163 | mtd->ecc_stats.failed++; | |
1164 | if (!is_erased(buf, mtd->oobsize)) | |
1165 | mtd->ecc_stats.failed++; | |
5bac3acf | 1166 | } |
ce082596 | 1167 | } |
3f91e94f | 1168 | return max_bitflips; |
ce082596 JR |
1169 | } |
1170 | ||
1171 | static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1172 | uint8_t *buf, int oob_required, int page) |
ce082596 JR |
1173 | { |
1174 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ce082596 | 1175 | dma_addr_t addr = denali->buf.dma_buf; |
442f201b | 1176 | size_t size = mtd->writesize + mtd->oobsize; |
9589bf5b | 1177 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP; |
5bac3acf | 1178 | |
7d8a26fd | 1179 | if (page != denali->page) { |
8125450c MY |
1180 | dev_err(denali->dev, |
1181 | "IN %s: page %d is not equal to denali->page %d", | |
1182 | __func__, page, denali->page); | |
7d8a26fd CD |
1183 | BUG(); |
1184 | } | |
1185 | ||
ce082596 | 1186 | setup_ecc_for_xfer(denali, false, true); |
aadff49c | 1187 | denali_enable_dma(denali, true); |
ce082596 | 1188 | |
84457949 | 1189 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1190 | |
1191 | clear_interrupts(denali); | |
aadff49c | 1192 | denali_setup_dma(denali, DENALI_READ); |
ce082596 JR |
1193 | |
1194 | /* wait for operation to complete */ | |
ba5f2bc2 | 1195 | wait_for_irq(denali, irq_mask); |
ce082596 | 1196 | |
84457949 | 1197 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 | 1198 | |
aadff49c | 1199 | denali_enable_dma(denali, false); |
ce082596 JR |
1200 | |
1201 | memcpy(buf, denali->buf.buf, mtd->writesize); | |
1202 | memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize); | |
1203 | ||
1204 | return 0; | |
1205 | } | |
1206 | ||
1207 | static uint8_t denali_read_byte(struct mtd_info *mtd) | |
1208 | { | |
1209 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1210 | uint8_t result = 0xff; | |
1211 | ||
1212 | if (denali->buf.head < denali->buf.tail) | |
ce082596 | 1213 | result = denali->buf.buf[denali->buf.head++]; |
ce082596 | 1214 | |
ce082596 JR |
1215 | return result; |
1216 | } | |
1217 | ||
1218 | static void denali_select_chip(struct mtd_info *mtd, int chip) | |
1219 | { | |
1220 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
7cfffac0 | 1221 | |
ce082596 JR |
1222 | spin_lock_irq(&denali->irq_lock); |
1223 | denali->flash_bank = chip; | |
1224 | spin_unlock_irq(&denali->irq_lock); | |
1225 | } | |
1226 | ||
1227 | static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) | |
1228 | { | |
1229 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1230 | int status = denali->status; | |
8125450c | 1231 | |
ce082596 JR |
1232 | denali->status = 0; |
1233 | ||
ce082596 JR |
1234 | return status; |
1235 | } | |
1236 | ||
49c50b97 | 1237 | static int denali_erase(struct mtd_info *mtd, int page) |
ce082596 JR |
1238 | { |
1239 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1240 | ||
5637b69d | 1241 | uint32_t cmd, irq_status; |
ce082596 | 1242 | |
5bac3acf | 1243 | clear_interrupts(denali); |
ce082596 JR |
1244 | |
1245 | /* setup page read request for access type */ | |
1246 | cmd = MODE_10 | BANK(denali->flash_bank) | page; | |
3157d1ed | 1247 | index_addr(denali, cmd, 0x1); |
ce082596 JR |
1248 | |
1249 | /* wait for erase to complete or failure to occur */ | |
9589bf5b JI |
1250 | irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | |
1251 | INTR_STATUS__ERASE_FAIL); | |
ce082596 | 1252 | |
7d14ecd0 | 1253 | return irq_status & INTR_STATUS__ERASE_FAIL ? NAND_STATUS_FAIL : PASS; |
ce082596 JR |
1254 | } |
1255 | ||
5bac3acf | 1256 | static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, |
ce082596 JR |
1257 | int page) |
1258 | { | |
1259 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ef41e1bb CD |
1260 | uint32_t addr, id; |
1261 | int i; | |
ce082596 | 1262 | |
345b1d3b | 1263 | switch (cmd) { |
a99d1796 CD |
1264 | case NAND_CMD_PAGEPROG: |
1265 | break; | |
1266 | case NAND_CMD_STATUS: | |
1267 | read_status(denali); | |
1268 | break; | |
1269 | case NAND_CMD_READID: | |
42af8b58 | 1270 | case NAND_CMD_PARAM: |
a99d1796 | 1271 | reset_buf(denali); |
43914a2d MY |
1272 | /* |
1273 | * sometimes ManufactureId read from register is not right | |
ef41e1bb CD |
1274 | * e.g. some of Micron MT29F32G08QAA MLC NAND chips |
1275 | * So here we send READID cmd to NAND insteand | |
43914a2d | 1276 | */ |
3157d1ed MY |
1277 | addr = MODE_11 | BANK(denali->flash_bank); |
1278 | index_addr(denali, addr | 0, 0x90); | |
9c07d094 | 1279 | index_addr(denali, addr | 1, col); |
d68a5c3d | 1280 | for (i = 0; i < 8; i++) { |
8125450c | 1281 | index_addr_read_data(denali, addr | 2, &id); |
ef41e1bb | 1282 | write_byte_to_buf(denali, id); |
a99d1796 CD |
1283 | } |
1284 | break; | |
1285 | case NAND_CMD_READ0: | |
1286 | case NAND_CMD_SEQIN: | |
1287 | denali->page = page; | |
1288 | break; | |
1289 | case NAND_CMD_RESET: | |
1290 | reset_bank(denali); | |
1291 | break; | |
1292 | case NAND_CMD_READOOB: | |
1293 | /* TODO: Read OOB data */ | |
1294 | break; | |
1295 | default: | |
2a0a288e | 1296 | pr_err(": unsupported command received 0x%x\n", cmd); |
a99d1796 | 1297 | break; |
ce082596 JR |
1298 | } |
1299 | } | |
ce082596 JR |
1300 | /* end NAND core entry points */ |
1301 | ||
1302 | /* Initialization code to bring the device up to a known good state */ | |
1303 | static void denali_hw_init(struct denali_nand_info *denali) | |
1304 | { | |
43914a2d MY |
1305 | /* |
1306 | * tell driver how many bit controller will skip before | |
db9a3210 CD |
1307 | * writing ECC code in OOB, this register may be already |
1308 | * set by firmware. So we read this value out. | |
1309 | * if this value is 0, just let it be. | |
43914a2d | 1310 | */ |
db9a3210 CD |
1311 | denali->bbtskipbytes = ioread32(denali->flash_reg + |
1312 | SPARE_AREA_SKIP_BYTES); | |
bc27ede3 | 1313 | detect_max_banks(denali); |
eda936ef | 1314 | denali_nand_reset(denali); |
24c3fa36 CD |
1315 | iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED); |
1316 | iowrite32(CHIP_EN_DONT_CARE__FLAG, | |
bdca6dae | 1317 | denali->flash_reg + CHIP_ENABLE_DONT_CARE); |
ce082596 | 1318 | |
24c3fa36 | 1319 | iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER); |
ce082596 JR |
1320 | |
1321 | /* Should set value for these registers when init */ | |
24c3fa36 CD |
1322 | iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES); |
1323 | iowrite32(1, denali->flash_reg + ECC_ENABLE); | |
5eab6aaa CD |
1324 | denali_nand_timing_set(denali); |
1325 | denali_irq_init(denali); | |
ce082596 JR |
1326 | } |
1327 | ||
43914a2d MY |
1328 | /* |
1329 | * Althogh controller spec said SLC ECC is forceb to be 4bit, | |
db9a3210 CD |
1330 | * but denali controller in MRST only support 15bit and 8bit ECC |
1331 | * correction | |
43914a2d | 1332 | */ |
db9a3210 | 1333 | #define ECC_8BITS 14 |
db9a3210 | 1334 | #define ECC_15BITS 26 |
14fad62b BB |
1335 | |
1336 | static int denali_ooblayout_ecc(struct mtd_info *mtd, int section, | |
1337 | struct mtd_oob_region *oobregion) | |
1338 | { | |
1339 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1340 | struct nand_chip *chip = mtd_to_nand(mtd); | |
1341 | ||
1342 | if (section) | |
1343 | return -ERANGE; | |
1344 | ||
1345 | oobregion->offset = denali->bbtskipbytes; | |
1346 | oobregion->length = chip->ecc.total; | |
1347 | ||
1348 | return 0; | |
1349 | } | |
1350 | ||
1351 | static int denali_ooblayout_free(struct mtd_info *mtd, int section, | |
1352 | struct mtd_oob_region *oobregion) | |
1353 | { | |
1354 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1355 | struct nand_chip *chip = mtd_to_nand(mtd); | |
1356 | ||
1357 | if (section) | |
1358 | return -ERANGE; | |
1359 | ||
1360 | oobregion->offset = chip->ecc.total + denali->bbtskipbytes; | |
1361 | oobregion->length = mtd->oobsize - oobregion->offset; | |
1362 | ||
1363 | return 0; | |
1364 | } | |
1365 | ||
1366 | static const struct mtd_ooblayout_ops denali_ooblayout_ops = { | |
1367 | .ecc = denali_ooblayout_ecc, | |
1368 | .free = denali_ooblayout_free, | |
ce082596 JR |
1369 | }; |
1370 | ||
1371 | static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; | |
1372 | static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; | |
1373 | ||
1374 | static struct nand_bbt_descr bbt_main_descr = { | |
1375 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1376 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1377 | .offs = 8, | |
1378 | .len = 4, | |
1379 | .veroffs = 12, | |
1380 | .maxblocks = 4, | |
1381 | .pattern = bbt_pattern, | |
1382 | }; | |
1383 | ||
1384 | static struct nand_bbt_descr bbt_mirror_descr = { | |
1385 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1386 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1387 | .offs = 8, | |
1388 | .len = 4, | |
1389 | .veroffs = 12, | |
1390 | .maxblocks = 4, | |
1391 | .pattern = mirror_pattern, | |
1392 | }; | |
1393 | ||
421f91d2 | 1394 | /* initialize driver data structures */ |
8c519436 | 1395 | static void denali_drv_init(struct denali_nand_info *denali) |
ce082596 | 1396 | { |
43914a2d MY |
1397 | /* |
1398 | * the completion object will be used to notify | |
1399 | * the callee that the interrupt is done | |
1400 | */ | |
ce082596 JR |
1401 | init_completion(&denali->complete); |
1402 | ||
43914a2d MY |
1403 | /* |
1404 | * the spinlock will be used to synchronize the ISR with any | |
1405 | * element that might be access shared data (interrupt status) | |
1406 | */ | |
ce082596 JR |
1407 | spin_lock_init(&denali->irq_lock); |
1408 | ||
1409 | /* indicate that MTD has not selected a valid bank yet */ | |
1410 | denali->flash_bank = CHIP_SELECT_INVALID; | |
1411 | ||
1412 | /* initialize our irq_status variable to indicate no interrupts */ | |
1413 | denali->irq_status = 0; | |
1414 | } | |
1415 | ||
2a0a288e | 1416 | int denali_init(struct denali_nand_info *denali) |
ce082596 | 1417 | { |
442f201b | 1418 | struct mtd_info *mtd = nand_to_mtd(&denali->nand); |
2a0a288e | 1419 | int ret; |
ce082596 | 1420 | |
2a0a288e | 1421 | if (denali->platform == INTEL_CE4100) { |
43914a2d MY |
1422 | /* |
1423 | * Due to a silicon limitation, we can only support | |
5bac3acf C |
1424 | * ONFI timing mode 1 and below. |
1425 | */ | |
345b1d3b | 1426 | if (onfi_timing_mode < -1 || onfi_timing_mode > 1) { |
2a0a288e DN |
1427 | pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n"); |
1428 | return -EINVAL; | |
ce082596 JR |
1429 | } |
1430 | } | |
1431 | ||
e07caa36 HS |
1432 | /* allocate a temporary buffer for nand_scan_ident() */ |
1433 | denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE, | |
1434 | GFP_DMA | GFP_KERNEL); | |
1435 | if (!denali->buf.buf) | |
1436 | return -ENOMEM; | |
ce082596 | 1437 | |
442f201b | 1438 | mtd->dev.parent = denali->dev; |
ce082596 JR |
1439 | denali_hw_init(denali); |
1440 | denali_drv_init(denali); | |
1441 | ||
7ebb8d06 MY |
1442 | /* Request IRQ after all the hardware initialization is finished */ |
1443 | ret = devm_request_irq(denali->dev, denali->irq, denali_isr, | |
1444 | IRQF_SHARED, DENALI_NAND_NAME, denali); | |
1445 | if (ret) { | |
789ccf17 | 1446 | dev_err(denali->dev, "Unable to request IRQ\n"); |
7ebb8d06 | 1447 | return ret; |
ce082596 JR |
1448 | } |
1449 | ||
1450 | /* now that our ISR is registered, we can enable interrupts */ | |
eda936ef | 1451 | denali_set_intr_modes(denali, true); |
442f201b | 1452 | mtd->name = "denali-nand"; |
ce082596 JR |
1453 | |
1454 | /* register the driver with the NAND core subsystem */ | |
1455 | denali->nand.select_chip = denali_select_chip; | |
1456 | denali->nand.cmdfunc = denali_cmdfunc; | |
1457 | denali->nand.read_byte = denali_read_byte; | |
1458 | denali->nand.waitfunc = denali_waitfunc; | |
1459 | ||
43914a2d MY |
1460 | /* |
1461 | * scan for NAND devices attached to the controller | |
ce082596 | 1462 | * this is the first stage in a two step process to register |
43914a2d MY |
1463 | * with the nand subsystem |
1464 | */ | |
a227d4e4 MY |
1465 | ret = nand_scan_ident(mtd, denali->max_banks, NULL); |
1466 | if (ret) | |
5c0eb900 | 1467 | goto failed_req_irq; |
5bac3acf | 1468 | |
e07caa36 HS |
1469 | /* allocate the right size buffer now */ |
1470 | devm_kfree(denali->dev, denali->buf.buf); | |
1471 | denali->buf.buf = devm_kzalloc(denali->dev, | |
442f201b | 1472 | mtd->writesize + mtd->oobsize, |
e07caa36 HS |
1473 | GFP_KERNEL); |
1474 | if (!denali->buf.buf) { | |
1475 | ret = -ENOMEM; | |
1476 | goto failed_req_irq; | |
1477 | } | |
1478 | ||
1479 | /* Is 32-bit DMA supported? */ | |
1480 | ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32)); | |
1481 | if (ret) { | |
789ccf17 | 1482 | dev_err(denali->dev, "No usable DMA configuration\n"); |
e07caa36 HS |
1483 | goto failed_req_irq; |
1484 | } | |
1485 | ||
1486 | denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf, | |
442f201b | 1487 | mtd->writesize + mtd->oobsize, |
e07caa36 HS |
1488 | DMA_BIDIRECTIONAL); |
1489 | if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) { | |
789ccf17 | 1490 | dev_err(denali->dev, "Failed to map DMA buffer\n"); |
e07caa36 | 1491 | ret = -EIO; |
5c0eb900 | 1492 | goto failed_req_irq; |
66406524 CD |
1493 | } |
1494 | ||
43914a2d MY |
1495 | /* |
1496 | * support for multi nand | |
1497 | * MTD known nothing about multi nand, so we should tell it | |
1498 | * the real pagesize and anything necessery | |
08b9ab99 CD |
1499 | */ |
1500 | denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
01a1d524 MY |
1501 | denali->nand.chipsize <<= denali->devnum - 1; |
1502 | denali->nand.page_shift += denali->devnum - 1; | |
08b9ab99 CD |
1503 | denali->nand.pagemask = (denali->nand.chipsize >> |
1504 | denali->nand.page_shift) - 1; | |
01a1d524 | 1505 | denali->nand.bbt_erase_shift += denali->devnum - 1; |
08b9ab99 | 1506 | denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift; |
01a1d524 MY |
1507 | denali->nand.chip_shift += denali->devnum - 1; |
1508 | mtd->writesize <<= denali->devnum - 1; | |
1509 | mtd->oobsize <<= denali->devnum - 1; | |
1510 | mtd->erasesize <<= denali->devnum - 1; | |
442f201b | 1511 | mtd->size = denali->nand.numchips * denali->nand.chipsize; |
08b9ab99 CD |
1512 | denali->bbtskipbytes *= denali->devnum; |
1513 | ||
43914a2d MY |
1514 | /* |
1515 | * second stage of the NAND scan | |
5bac3acf | 1516 | * this stage requires information regarding ECC and |
43914a2d MY |
1517 | * bad block management. |
1518 | */ | |
ce082596 JR |
1519 | |
1520 | /* Bad block management */ | |
1521 | denali->nand.bbt_td = &bbt_main_descr; | |
1522 | denali->nand.bbt_md = &bbt_mirror_descr; | |
1523 | ||
1524 | /* skip the scan for now until we have OOB read and write support */ | |
bb9ebd4e | 1525 | denali->nand.bbt_options |= NAND_BBT_USE_FLASH; |
a40f7341 | 1526 | denali->nand.options |= NAND_SKIP_BBTSCAN; |
ce082596 JR |
1527 | denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; |
1528 | ||
d99d7282 GM |
1529 | /* no subpage writes on denali */ |
1530 | denali->nand.options |= NAND_NO_SUBPAGE_WRITE; | |
1531 | ||
43914a2d MY |
1532 | /* |
1533 | * Denali Controller only support 15bit and 8bit ECC in MRST, | |
db9a3210 CD |
1534 | * so just let controller do 15bit ECC for MLC and 8bit ECC for |
1535 | * SLC if possible. | |
1536 | * */ | |
1d0ed69d | 1537 | if (!nand_is_slc(&denali->nand) && |
442f201b BB |
1538 | (mtd->oobsize > (denali->bbtskipbytes + |
1539 | ECC_15BITS * (mtd->writesize / | |
db9a3210 CD |
1540 | ECC_SECTOR_SIZE)))) { |
1541 | /* if MLC OOB size is large enough, use 15bit ECC*/ | |
6a918bad | 1542 | denali->nand.ecc.strength = 15; |
db9a3210 | 1543 | denali->nand.ecc.bytes = ECC_15BITS; |
24c3fa36 | 1544 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
442f201b BB |
1545 | } else if (mtd->oobsize < (denali->bbtskipbytes + |
1546 | ECC_8BITS * (mtd->writesize / | |
db9a3210 | 1547 | ECC_SECTOR_SIZE))) { |
8125450c | 1548 | pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes"); |
5c0eb900 | 1549 | goto failed_req_irq; |
db9a3210 | 1550 | } else { |
6a918bad | 1551 | denali->nand.ecc.strength = 8; |
db9a3210 | 1552 | denali->nand.ecc.bytes = ECC_8BITS; |
24c3fa36 | 1553 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 JR |
1554 | } |
1555 | ||
14fad62b | 1556 | mtd_set_ooblayout(mtd, &denali_ooblayout_ops); |
08b9ab99 | 1557 | denali->nand.ecc.bytes *= denali->devnum; |
6a918bad | 1558 | denali->nand.ecc.strength *= denali->devnum; |
db9a3210 | 1559 | |
ce082596 | 1560 | /* override the default read operations */ |
08b9ab99 | 1561 | denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum; |
ce082596 JR |
1562 | denali->nand.ecc.read_page = denali_read_page; |
1563 | denali->nand.ecc.read_page_raw = denali_read_page_raw; | |
1564 | denali->nand.ecc.write_page = denali_write_page; | |
1565 | denali->nand.ecc.write_page_raw = denali_write_page_raw; | |
1566 | denali->nand.ecc.read_oob = denali_read_oob; | |
1567 | denali->nand.ecc.write_oob = denali_write_oob; | |
49c50b97 | 1568 | denali->nand.erase = denali_erase; |
ce082596 | 1569 | |
a227d4e4 MY |
1570 | ret = nand_scan_tail(mtd); |
1571 | if (ret) | |
5c0eb900 | 1572 | goto failed_req_irq; |
ce082596 | 1573 | |
442f201b | 1574 | ret = mtd_device_register(mtd, NULL, 0); |
ce082596 | 1575 | if (ret) { |
789ccf17 | 1576 | dev_err(denali->dev, "Failed to register MTD: %d\n", ret); |
5c0eb900 | 1577 | goto failed_req_irq; |
ce082596 JR |
1578 | } |
1579 | return 0; | |
1580 | ||
5c0eb900 | 1581 | failed_req_irq: |
2a0a288e DN |
1582 | denali_irq_cleanup(denali->irq, denali); |
1583 | ||
ce082596 JR |
1584 | return ret; |
1585 | } | |
2a0a288e | 1586 | EXPORT_SYMBOL(denali_init); |
ce082596 JR |
1587 | |
1588 | /* driver exit point */ | |
2a0a288e | 1589 | void denali_remove(struct denali_nand_info *denali) |
ce082596 | 1590 | { |
442f201b | 1591 | struct mtd_info *mtd = nand_to_mtd(&denali->nand); |
320092a0 BB |
1592 | /* |
1593 | * Pre-compute DMA buffer size to avoid any problems in case | |
1594 | * nand_release() ever changes in a way that mtd->writesize and | |
1595 | * mtd->oobsize are not reliable after this call. | |
1596 | */ | |
442f201b | 1597 | int bufsize = mtd->writesize + mtd->oobsize; |
320092a0 | 1598 | |
442f201b | 1599 | nand_release(mtd); |
2a0a288e | 1600 | denali_irq_cleanup(denali->irq, denali); |
320092a0 | 1601 | dma_unmap_single(denali->dev, denali->buf.dma_buf, bufsize, |
8125450c | 1602 | DMA_BIDIRECTIONAL); |
ce082596 | 1603 | } |
2a0a288e | 1604 | EXPORT_SYMBOL(denali_remove); |