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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand.c | |
3 | * | |
4 | * Overview: | |
5 | * This is the generic MTD driver for NAND flash devices. It should be | |
6 | * capable of working with almost all NAND chips currently available. | |
7 | * Basic support for AG-AND chips is provided. | |
61b03bd7 | 8 | * |
1da177e4 | 9 | * Additional technical information is available on |
8b2b403c | 10 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 11 | * |
1da177e4 | 12 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 13 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 14 | * |
ace4dfee | 15 | * Credits: |
61b03bd7 TG |
16 | * David Woodhouse for adding multichip support |
17 | * | |
1da177e4 LT |
18 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
19 | * rework for 2K page size chips | |
20 | * | |
ace4dfee | 21 | * TODO: |
1da177e4 LT |
22 | * Enable cached programming for 2k page size chips |
23 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
24 | * if we have HW ecc support. | |
25 | * The AG-AND chips have nice features for speed improvement, | |
26 | * which are not supported yet. Read / program 4 pages in one go. | |
c0b8ba7b | 27 | * BBT table is not serialized, has to be fixed |
1da177e4 | 28 | * |
1da177e4 LT |
29 | * This program is free software; you can redistribute it and/or modify |
30 | * it under the terms of the GNU General Public License version 2 as | |
31 | * published by the Free Software Foundation. | |
32 | * | |
33 | */ | |
34 | ||
552d9205 | 35 | #include <linux/module.h> |
1da177e4 LT |
36 | #include <linux/delay.h> |
37 | #include <linux/errno.h> | |
7aa65bfd | 38 | #include <linux/err.h> |
1da177e4 LT |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
41 | #include <linux/types.h> | |
42 | #include <linux/mtd/mtd.h> | |
43 | #include <linux/mtd/nand.h> | |
44 | #include <linux/mtd/nand_ecc.h> | |
193bd400 | 45 | #include <linux/mtd/nand_bch.h> |
1da177e4 LT |
46 | #include <linux/interrupt.h> |
47 | #include <linux/bitops.h> | |
8fe833c1 | 48 | #include <linux/leds.h> |
7351d3a5 | 49 | #include <linux/io.h> |
1da177e4 | 50 | #include <linux/mtd/partitions.h> |
1da177e4 LT |
51 | |
52 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 53 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
54 | .eccbytes = 3, |
55 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
56 | .oobfree = { |
57 | {.offset = 3, | |
58 | .length = 2}, | |
59 | {.offset = 6, | |
f8ac0414 | 60 | .length = 2} } |
1da177e4 LT |
61 | }; |
62 | ||
5bd34c09 | 63 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
64 | .eccbytes = 6, |
65 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
66 | .oobfree = { |
67 | {.offset = 8, | |
f8ac0414 | 68 | . length = 8} } |
1da177e4 LT |
69 | }; |
70 | ||
5bd34c09 | 71 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
72 | .eccbytes = 24, |
73 | .eccpos = { | |
e0c7d767 DW |
74 | 40, 41, 42, 43, 44, 45, 46, 47, |
75 | 48, 49, 50, 51, 52, 53, 54, 55, | |
76 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
77 | .oobfree = { |
78 | {.offset = 2, | |
f8ac0414 | 79 | .length = 38} } |
1da177e4 LT |
80 | }; |
81 | ||
81ec5364 TG |
82 | static struct nand_ecclayout nand_oob_128 = { |
83 | .eccbytes = 48, | |
84 | .eccpos = { | |
85 | 80, 81, 82, 83, 84, 85, 86, 87, | |
86 | 88, 89, 90, 91, 92, 93, 94, 95, | |
87 | 96, 97, 98, 99, 100, 101, 102, 103, | |
88 | 104, 105, 106, 107, 108, 109, 110, 111, | |
89 | 112, 113, 114, 115, 116, 117, 118, 119, | |
90 | 120, 121, 122, 123, 124, 125, 126, 127}, | |
91 | .oobfree = { | |
92 | {.offset = 2, | |
f8ac0414 | 93 | .length = 78} } |
81ec5364 TG |
94 | }; |
95 | ||
ace4dfee | 96 | static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, |
2c0a2bed | 97 | int new_state); |
1da177e4 | 98 | |
8593fbc6 TG |
99 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
100 | struct mtd_oob_ops *ops); | |
101 | ||
d470a97c | 102 | /* |
8e87d782 | 103 | * For devices which display every fart in the system on a separate LED. Is |
d470a97c TG |
104 | * compiled away when LED support is disabled. |
105 | */ | |
106 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
107 | ||
6fe5a6ac VS |
108 | static int check_offs_len(struct mtd_info *mtd, |
109 | loff_t ofs, uint64_t len) | |
110 | { | |
111 | struct nand_chip *chip = mtd->priv; | |
112 | int ret = 0; | |
113 | ||
114 | /* Start address must align on block boundary */ | |
115 | if (ofs & ((1 << chip->phys_erase_shift) - 1)) { | |
116 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__); | |
117 | ret = -EINVAL; | |
118 | } | |
119 | ||
120 | /* Length must align on block boundary */ | |
121 | if (len & ((1 << chip->phys_erase_shift) - 1)) { | |
122 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n", | |
123 | __func__); | |
124 | ret = -EINVAL; | |
125 | } | |
126 | ||
127 | /* Do not allow past end of device */ | |
128 | if (ofs + len > mtd->size) { | |
129 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n", | |
130 | __func__); | |
131 | ret = -EINVAL; | |
132 | } | |
133 | ||
134 | return ret; | |
135 | } | |
136 | ||
1da177e4 LT |
137 | /** |
138 | * nand_release_device - [GENERIC] release chip | |
139 | * @mtd: MTD device structure | |
61b03bd7 TG |
140 | * |
141 | * Deselect, release chip lock and wake up anyone waiting on the device | |
1da177e4 | 142 | */ |
e0c7d767 | 143 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 144 | { |
ace4dfee | 145 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
146 | |
147 | /* De-select the NAND device */ | |
ace4dfee | 148 | chip->select_chip(mtd, -1); |
0dfc6246 | 149 | |
a36ed299 | 150 | /* Release the controller and the chip */ |
ace4dfee TG |
151 | spin_lock(&chip->controller->lock); |
152 | chip->controller->active = NULL; | |
153 | chip->state = FL_READY; | |
154 | wake_up(&chip->controller->wq); | |
155 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
156 | } |
157 | ||
158 | /** | |
159 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
160 | * @mtd: MTD device structure | |
161 | * | |
162 | * Default read function for 8bit buswith | |
163 | */ | |
58dd8f2b | 164 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 165 | { |
ace4dfee TG |
166 | struct nand_chip *chip = mtd->priv; |
167 | return readb(chip->IO_ADDR_R); | |
1da177e4 LT |
168 | } |
169 | ||
1da177e4 LT |
170 | /** |
171 | * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip | |
172 | * @mtd: MTD device structure | |
173 | * | |
61b03bd7 | 174 | * Default read function for 16bit buswith with |
1da177e4 LT |
175 | * endianess conversion |
176 | */ | |
58dd8f2b | 177 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 178 | { |
ace4dfee TG |
179 | struct nand_chip *chip = mtd->priv; |
180 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); | |
1da177e4 LT |
181 | } |
182 | ||
1da177e4 LT |
183 | /** |
184 | * nand_read_word - [DEFAULT] read one word from the chip | |
185 | * @mtd: MTD device structure | |
186 | * | |
61b03bd7 | 187 | * Default read function for 16bit buswith without |
1da177e4 LT |
188 | * endianess conversion |
189 | */ | |
190 | static u16 nand_read_word(struct mtd_info *mtd) | |
191 | { | |
ace4dfee TG |
192 | struct nand_chip *chip = mtd->priv; |
193 | return readw(chip->IO_ADDR_R); | |
1da177e4 LT |
194 | } |
195 | ||
1da177e4 LT |
196 | /** |
197 | * nand_select_chip - [DEFAULT] control CE line | |
198 | * @mtd: MTD device structure | |
844d3b42 | 199 | * @chipnr: chipnumber to select, -1 for deselect |
1da177e4 LT |
200 | * |
201 | * Default select function for 1 chip devices. | |
202 | */ | |
ace4dfee | 203 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 204 | { |
ace4dfee TG |
205 | struct nand_chip *chip = mtd->priv; |
206 | ||
207 | switch (chipnr) { | |
1da177e4 | 208 | case -1: |
ace4dfee | 209 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
210 | break; |
211 | case 0: | |
1da177e4 LT |
212 | break; |
213 | ||
214 | default: | |
215 | BUG(); | |
216 | } | |
217 | } | |
218 | ||
219 | /** | |
220 | * nand_write_buf - [DEFAULT] write buffer to chip | |
221 | * @mtd: MTD device structure | |
222 | * @buf: data buffer | |
223 | * @len: number of bytes to write | |
224 | * | |
225 | * Default write function for 8bit buswith | |
226 | */ | |
58dd8f2b | 227 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
228 | { |
229 | int i; | |
ace4dfee | 230 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 231 | |
e0c7d767 | 232 | for (i = 0; i < len; i++) |
ace4dfee | 233 | writeb(buf[i], chip->IO_ADDR_W); |
1da177e4 LT |
234 | } |
235 | ||
236 | /** | |
61b03bd7 | 237 | * nand_read_buf - [DEFAULT] read chip data into buffer |
1da177e4 LT |
238 | * @mtd: MTD device structure |
239 | * @buf: buffer to store date | |
240 | * @len: number of bytes to read | |
241 | * | |
242 | * Default read function for 8bit buswith | |
243 | */ | |
58dd8f2b | 244 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
245 | { |
246 | int i; | |
ace4dfee | 247 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 248 | |
e0c7d767 | 249 | for (i = 0; i < len; i++) |
ace4dfee | 250 | buf[i] = readb(chip->IO_ADDR_R); |
1da177e4 LT |
251 | } |
252 | ||
253 | /** | |
61b03bd7 | 254 | * nand_verify_buf - [DEFAULT] Verify chip data against buffer |
1da177e4 LT |
255 | * @mtd: MTD device structure |
256 | * @buf: buffer containing the data to compare | |
257 | * @len: number of bytes to compare | |
258 | * | |
259 | * Default verify function for 8bit buswith | |
260 | */ | |
58dd8f2b | 261 | static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
262 | { |
263 | int i; | |
ace4dfee | 264 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 265 | |
e0c7d767 | 266 | for (i = 0; i < len; i++) |
ace4dfee | 267 | if (buf[i] != readb(chip->IO_ADDR_R)) |
1da177e4 | 268 | return -EFAULT; |
1da177e4 LT |
269 | return 0; |
270 | } | |
271 | ||
272 | /** | |
273 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
274 | * @mtd: MTD device structure | |
275 | * @buf: data buffer | |
276 | * @len: number of bytes to write | |
277 | * | |
278 | * Default write function for 16bit buswith | |
279 | */ | |
58dd8f2b | 280 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
281 | { |
282 | int i; | |
ace4dfee | 283 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
284 | u16 *p = (u16 *) buf; |
285 | len >>= 1; | |
61b03bd7 | 286 | |
e0c7d767 | 287 | for (i = 0; i < len; i++) |
ace4dfee | 288 | writew(p[i], chip->IO_ADDR_W); |
61b03bd7 | 289 | |
1da177e4 LT |
290 | } |
291 | ||
292 | /** | |
61b03bd7 | 293 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
1da177e4 LT |
294 | * @mtd: MTD device structure |
295 | * @buf: buffer to store date | |
296 | * @len: number of bytes to read | |
297 | * | |
298 | * Default read function for 16bit buswith | |
299 | */ | |
58dd8f2b | 300 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
301 | { |
302 | int i; | |
ace4dfee | 303 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
304 | u16 *p = (u16 *) buf; |
305 | len >>= 1; | |
306 | ||
e0c7d767 | 307 | for (i = 0; i < len; i++) |
ace4dfee | 308 | p[i] = readw(chip->IO_ADDR_R); |
1da177e4 LT |
309 | } |
310 | ||
311 | /** | |
61b03bd7 | 312 | * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer |
1da177e4 LT |
313 | * @mtd: MTD device structure |
314 | * @buf: buffer containing the data to compare | |
315 | * @len: number of bytes to compare | |
316 | * | |
317 | * Default verify function for 16bit buswith | |
318 | */ | |
58dd8f2b | 319 | static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
320 | { |
321 | int i; | |
ace4dfee | 322 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
323 | u16 *p = (u16 *) buf; |
324 | len >>= 1; | |
325 | ||
e0c7d767 | 326 | for (i = 0; i < len; i++) |
ace4dfee | 327 | if (p[i] != readw(chip->IO_ADDR_R)) |
1da177e4 LT |
328 | return -EFAULT; |
329 | ||
330 | return 0; | |
331 | } | |
332 | ||
333 | /** | |
334 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
335 | * @mtd: MTD device structure | |
336 | * @ofs: offset from device start | |
337 | * @getchip: 0, if the chip is already selected | |
338 | * | |
61b03bd7 | 339 | * Check, if the block is bad. |
1da177e4 LT |
340 | */ |
341 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
342 | { | |
343 | int page, chipnr, res = 0; | |
ace4dfee | 344 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
345 | u16 bad; |
346 | ||
5fb1549d | 347 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
348 | ofs += mtd->erasesize - mtd->writesize; |
349 | ||
1a12f46a TK |
350 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
351 | ||
1da177e4 | 352 | if (getchip) { |
ace4dfee | 353 | chipnr = (int)(ofs >> chip->chip_shift); |
1da177e4 | 354 | |
ace4dfee | 355 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 LT |
356 | |
357 | /* Select the NAND device */ | |
ace4dfee | 358 | chip->select_chip(mtd, chipnr); |
1a12f46a | 359 | } |
1da177e4 | 360 | |
ace4dfee TG |
361 | if (chip->options & NAND_BUSWIDTH_16) { |
362 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE, | |
1a12f46a | 363 | page); |
ace4dfee TG |
364 | bad = cpu_to_le16(chip->read_word(mtd)); |
365 | if (chip->badblockpos & 0x1) | |
49196f33 | 366 | bad >>= 8; |
e0b58d0a ML |
367 | else |
368 | bad &= 0xFF; | |
1da177e4 | 369 | } else { |
1a12f46a | 370 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page); |
e0b58d0a | 371 | bad = chip->read_byte(mtd); |
1da177e4 | 372 | } |
61b03bd7 | 373 | |
e0b58d0a ML |
374 | if (likely(chip->badblockbits == 8)) |
375 | res = bad != 0xFF; | |
376 | else | |
377 | res = hweight8(bad) < chip->badblockbits; | |
378 | ||
ace4dfee | 379 | if (getchip) |
1da177e4 | 380 | nand_release_device(mtd); |
61b03bd7 | 381 | |
1da177e4 LT |
382 | return res; |
383 | } | |
384 | ||
385 | /** | |
386 | * nand_default_block_markbad - [DEFAULT] mark a block bad | |
387 | * @mtd: MTD device structure | |
388 | * @ofs: offset from device start | |
389 | * | |
390 | * This is the default implementation, which can be overridden by | |
391 | * a hardware specific driver. | |
392 | */ | |
393 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
394 | { | |
ace4dfee | 395 | struct nand_chip *chip = mtd->priv; |
58dd8f2b | 396 | uint8_t buf[2] = { 0, 0 }; |
02ed70bb | 397 | int block, ret, i = 0; |
61b03bd7 | 398 | |
5fb1549d | 399 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
400 | ofs += mtd->erasesize - mtd->writesize; |
401 | ||
1da177e4 | 402 | /* Get block number */ |
4226b510 | 403 | block = (int)(ofs >> chip->bbt_erase_shift); |
ace4dfee TG |
404 | if (chip->bbt) |
405 | chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); | |
1da177e4 LT |
406 | |
407 | /* Do we have a flash based bad block table ? */ | |
bb9ebd4e | 408 | if (chip->bbt_options & NAND_BBT_USE_FLASH) |
f1a28c02 TG |
409 | ret = nand_update_bbt(mtd, ofs); |
410 | else { | |
c0b8ba7b | 411 | nand_get_device(chip, mtd, FL_WRITING); |
f1a28c02 | 412 | |
a0dc5529 BN |
413 | /* |
414 | * Write to first two pages if necessary. If we write to more | |
415 | * than one location, the first error encountered quits the | |
416 | * procedure. We write two bytes per location, so we dont have | |
417 | * to mess with 16 bit access. | |
02ed70bb BN |
418 | */ |
419 | do { | |
420 | chip->ops.len = chip->ops.ooblen = 2; | |
421 | chip->ops.datbuf = NULL; | |
422 | chip->ops.oobbuf = buf; | |
423 | chip->ops.ooboffs = chip->badblockpos & ~0x01; | |
424 | ||
425 | ret = nand_do_write_oob(mtd, ofs, &chip->ops); | |
426 | ||
02ed70bb BN |
427 | i++; |
428 | ofs += mtd->writesize; | |
5fb1549d | 429 | } while (!ret && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && |
02ed70bb BN |
430 | i < 2); |
431 | ||
c0b8ba7b | 432 | nand_release_device(mtd); |
f1a28c02 TG |
433 | } |
434 | if (!ret) | |
435 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 436 | |
f1a28c02 | 437 | return ret; |
1da177e4 LT |
438 | } |
439 | ||
61b03bd7 | 440 | /** |
1da177e4 LT |
441 | * nand_check_wp - [GENERIC] check if the chip is write protected |
442 | * @mtd: MTD device structure | |
61b03bd7 | 443 | * Check, if the device is write protected |
1da177e4 | 444 | * |
61b03bd7 | 445 | * The function expects, that the device is already selected |
1da177e4 | 446 | */ |
e0c7d767 | 447 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 448 | { |
ace4dfee | 449 | struct nand_chip *chip = mtd->priv; |
93edbad6 ML |
450 | |
451 | /* broken xD cards report WP despite being writable */ | |
452 | if (chip->options & NAND_BROKEN_XD) | |
453 | return 0; | |
454 | ||
1da177e4 | 455 | /* Check the WP bit */ |
ace4dfee TG |
456 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
457 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
458 | } |
459 | ||
460 | /** | |
461 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
462 | * @mtd: MTD device structure | |
463 | * @ofs: offset from device start | |
464 | * @getchip: 0, if the chip is already selected | |
465 | * @allowbbt: 1, if its allowed to access the bbt area | |
466 | * | |
467 | * Check, if the block is bad. Either by reading the bad block table or | |
468 | * calling of the scan function. | |
469 | */ | |
2c0a2bed TG |
470 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
471 | int allowbbt) | |
1da177e4 | 472 | { |
ace4dfee | 473 | struct nand_chip *chip = mtd->priv; |
61b03bd7 | 474 | |
ace4dfee TG |
475 | if (!chip->bbt) |
476 | return chip->block_bad(mtd, ofs, getchip); | |
61b03bd7 | 477 | |
1da177e4 | 478 | /* Return info from the table */ |
e0c7d767 | 479 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
480 | } |
481 | ||
2af7c653 SK |
482 | /** |
483 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
484 | * @mtd: MTD device structure | |
485 | * @timeo: Timeout | |
486 | * | |
487 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
488 | * context. | |
489 | */ | |
490 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
491 | { | |
492 | struct nand_chip *chip = mtd->priv; | |
493 | int i; | |
494 | ||
495 | /* Wait for the device to get ready */ | |
496 | for (i = 0; i < timeo; i++) { | |
497 | if (chip->dev_ready(mtd)) | |
498 | break; | |
499 | touch_softlockup_watchdog(); | |
500 | mdelay(1); | |
501 | } | |
502 | } | |
503 | ||
61b03bd7 | 504 | /* |
3b88775c TG |
505 | * Wait for the ready pin, after a command |
506 | * The timeout is catched later. | |
507 | */ | |
4b648b02 | 508 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 509 | { |
ace4dfee | 510 | struct nand_chip *chip = mtd->priv; |
e0c7d767 | 511 | unsigned long timeo = jiffies + 2; |
3b88775c | 512 | |
2af7c653 SK |
513 | /* 400ms timeout */ |
514 | if (in_interrupt() || oops_in_progress) | |
515 | return panic_nand_wait_ready(mtd, 400); | |
516 | ||
8fe833c1 | 517 | led_trigger_event(nand_led_trigger, LED_FULL); |
3b88775c TG |
518 | /* wait until command is processed or timeout occures */ |
519 | do { | |
ace4dfee | 520 | if (chip->dev_ready(mtd)) |
8fe833c1 | 521 | break; |
8446f1d3 | 522 | touch_softlockup_watchdog(); |
61b03bd7 | 523 | } while (time_before(jiffies, timeo)); |
8fe833c1 | 524 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c | 525 | } |
4b648b02 | 526 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 527 | |
1da177e4 LT |
528 | /** |
529 | * nand_command - [DEFAULT] Send command to NAND device | |
530 | * @mtd: MTD device structure | |
531 | * @command: the command to be sent | |
532 | * @column: the column address for this command, -1 if none | |
533 | * @page_addr: the page address for this command, -1 if none | |
534 | * | |
535 | * Send command to NAND device. This function is used for small page | |
536 | * devices (256/512 Bytes per page) | |
537 | */ | |
7abd3ef9 TG |
538 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
539 | int column, int page_addr) | |
1da177e4 | 540 | { |
ace4dfee | 541 | register struct nand_chip *chip = mtd->priv; |
7abd3ef9 | 542 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 543 | |
1da177e4 LT |
544 | /* |
545 | * Write out the command to the device. | |
546 | */ | |
547 | if (command == NAND_CMD_SEQIN) { | |
548 | int readcmd; | |
549 | ||
28318776 | 550 | if (column >= mtd->writesize) { |
1da177e4 | 551 | /* OOB area */ |
28318776 | 552 | column -= mtd->writesize; |
1da177e4 LT |
553 | readcmd = NAND_CMD_READOOB; |
554 | } else if (column < 256) { | |
555 | /* First 256 bytes --> READ0 */ | |
556 | readcmd = NAND_CMD_READ0; | |
557 | } else { | |
558 | column -= 256; | |
559 | readcmd = NAND_CMD_READ1; | |
560 | } | |
ace4dfee | 561 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 562 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 563 | } |
ace4dfee | 564 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 565 | |
7abd3ef9 TG |
566 | /* |
567 | * Address cycle, when necessary | |
568 | */ | |
569 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; | |
570 | /* Serially input address */ | |
571 | if (column != -1) { | |
572 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 573 | if (chip->options & NAND_BUSWIDTH_16) |
7abd3ef9 | 574 | column >>= 1; |
ace4dfee | 575 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
576 | ctrl &= ~NAND_CTRL_CHANGE; |
577 | } | |
578 | if (page_addr != -1) { | |
ace4dfee | 579 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 580 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 581 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 582 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
583 | if (chip->chipsize > (32 << 20)) |
584 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 585 | } |
ace4dfee | 586 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
587 | |
588 | /* | |
589 | * program and erase have their own busy handlers | |
1da177e4 | 590 | * status and sequential in needs no delay |
e0c7d767 | 591 | */ |
1da177e4 | 592 | switch (command) { |
61b03bd7 | 593 | |
1da177e4 LT |
594 | case NAND_CMD_PAGEPROG: |
595 | case NAND_CMD_ERASE1: | |
596 | case NAND_CMD_ERASE2: | |
597 | case NAND_CMD_SEQIN: | |
598 | case NAND_CMD_STATUS: | |
599 | return; | |
600 | ||
601 | case NAND_CMD_RESET: | |
ace4dfee | 602 | if (chip->dev_ready) |
1da177e4 | 603 | break; |
ace4dfee TG |
604 | udelay(chip->chip_delay); |
605 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 606 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
607 | chip->cmd_ctrl(mtd, |
608 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
609 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
610 | ; | |
1da177e4 LT |
611 | return; |
612 | ||
e0c7d767 | 613 | /* This applies to read commands */ |
1da177e4 | 614 | default: |
61b03bd7 | 615 | /* |
1da177e4 LT |
616 | * If we don't have access to the busy pin, we apply the given |
617 | * command delay | |
e0c7d767 | 618 | */ |
ace4dfee TG |
619 | if (!chip->dev_ready) { |
620 | udelay(chip->chip_delay); | |
1da177e4 | 621 | return; |
61b03bd7 | 622 | } |
1da177e4 | 623 | } |
1da177e4 LT |
624 | /* Apply this short delay always to ensure that we do wait tWB in |
625 | * any case on any machine. */ | |
e0c7d767 | 626 | ndelay(100); |
3b88775c TG |
627 | |
628 | nand_wait_ready(mtd); | |
1da177e4 LT |
629 | } |
630 | ||
631 | /** | |
632 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
633 | * @mtd: MTD device structure | |
634 | * @command: the command to be sent | |
635 | * @column: the column address for this command, -1 if none | |
636 | * @page_addr: the page address for this command, -1 if none | |
637 | * | |
7abd3ef9 TG |
638 | * Send command to NAND device. This is the version for the new large page |
639 | * devices We dont have the separate regions as we have in the small page | |
640 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 641 | */ |
7abd3ef9 TG |
642 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
643 | int column, int page_addr) | |
1da177e4 | 644 | { |
ace4dfee | 645 | register struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
646 | |
647 | /* Emulate NAND_CMD_READOOB */ | |
648 | if (command == NAND_CMD_READOOB) { | |
28318776 | 649 | column += mtd->writesize; |
1da177e4 LT |
650 | command = NAND_CMD_READ0; |
651 | } | |
61b03bd7 | 652 | |
7abd3ef9 | 653 | /* Command latch cycle */ |
ace4dfee | 654 | chip->cmd_ctrl(mtd, command & 0xff, |
7abd3ef9 | 655 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
656 | |
657 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 658 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
659 | |
660 | /* Serially input address */ | |
661 | if (column != -1) { | |
662 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 663 | if (chip->options & NAND_BUSWIDTH_16) |
1da177e4 | 664 | column >>= 1; |
ace4dfee | 665 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 666 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 667 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 668 | } |
1da177e4 | 669 | if (page_addr != -1) { |
ace4dfee TG |
670 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
671 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 672 | NAND_NCE | NAND_ALE); |
1da177e4 | 673 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
674 | if (chip->chipsize > (128 << 20)) |
675 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 676 | NAND_NCE | NAND_ALE); |
1da177e4 | 677 | } |
1da177e4 | 678 | } |
ace4dfee | 679 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
680 | |
681 | /* | |
682 | * program and erase have their own busy handlers | |
30f464b7 DM |
683 | * status, sequential in, and deplete1 need no delay |
684 | */ | |
1da177e4 | 685 | switch (command) { |
61b03bd7 | 686 | |
1da177e4 LT |
687 | case NAND_CMD_CACHEDPROG: |
688 | case NAND_CMD_PAGEPROG: | |
689 | case NAND_CMD_ERASE1: | |
690 | case NAND_CMD_ERASE2: | |
691 | case NAND_CMD_SEQIN: | |
7bc3312b | 692 | case NAND_CMD_RNDIN: |
1da177e4 | 693 | case NAND_CMD_STATUS: |
30f464b7 | 694 | case NAND_CMD_DEPLETE1: |
1da177e4 LT |
695 | return; |
696 | ||
e0c7d767 DW |
697 | /* |
698 | * read error status commands require only a short delay | |
699 | */ | |
30f464b7 DM |
700 | case NAND_CMD_STATUS_ERROR: |
701 | case NAND_CMD_STATUS_ERROR0: | |
702 | case NAND_CMD_STATUS_ERROR1: | |
703 | case NAND_CMD_STATUS_ERROR2: | |
704 | case NAND_CMD_STATUS_ERROR3: | |
ace4dfee | 705 | udelay(chip->chip_delay); |
30f464b7 | 706 | return; |
1da177e4 LT |
707 | |
708 | case NAND_CMD_RESET: | |
ace4dfee | 709 | if (chip->dev_ready) |
1da177e4 | 710 | break; |
ace4dfee | 711 | udelay(chip->chip_delay); |
12efdde3 TG |
712 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
713 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
714 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
715 | NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
716 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
717 | ; | |
1da177e4 LT |
718 | return; |
719 | ||
7bc3312b TG |
720 | case NAND_CMD_RNDOUT: |
721 | /* No ready / busy check necessary */ | |
722 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
723 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
724 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
725 | NAND_NCE | NAND_CTRL_CHANGE); | |
726 | return; | |
727 | ||
1da177e4 | 728 | case NAND_CMD_READ0: |
12efdde3 TG |
729 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
730 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
731 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
732 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 733 | |
e0c7d767 | 734 | /* This applies to read commands */ |
1da177e4 | 735 | default: |
61b03bd7 | 736 | /* |
1da177e4 LT |
737 | * If we don't have access to the busy pin, we apply the given |
738 | * command delay | |
e0c7d767 | 739 | */ |
ace4dfee TG |
740 | if (!chip->dev_ready) { |
741 | udelay(chip->chip_delay); | |
1da177e4 | 742 | return; |
61b03bd7 | 743 | } |
1da177e4 | 744 | } |
3b88775c | 745 | |
1da177e4 LT |
746 | /* Apply this short delay always to ensure that we do wait tWB in |
747 | * any case on any machine. */ | |
e0c7d767 | 748 | ndelay(100); |
3b88775c TG |
749 | |
750 | nand_wait_ready(mtd); | |
1da177e4 LT |
751 | } |
752 | ||
2af7c653 SK |
753 | /** |
754 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
755 | * @chip: the nand chip descriptor | |
756 | * @mtd: MTD device structure | |
757 | * @new_state: the state which is requested | |
758 | * | |
759 | * Used when in panic, no locks are taken. | |
760 | */ | |
761 | static void panic_nand_get_device(struct nand_chip *chip, | |
762 | struct mtd_info *mtd, int new_state) | |
763 | { | |
764 | /* Hardware controller shared among independend devices */ | |
765 | chip->controller->active = chip; | |
766 | chip->state = new_state; | |
767 | } | |
768 | ||
1da177e4 LT |
769 | /** |
770 | * nand_get_device - [GENERIC] Get chip for selected access | |
844d3b42 | 771 | * @chip: the nand chip descriptor |
1da177e4 | 772 | * @mtd: MTD device structure |
61b03bd7 | 773 | * @new_state: the state which is requested |
1da177e4 LT |
774 | * |
775 | * Get the device and lock it for exclusive access | |
776 | */ | |
2c0a2bed | 777 | static int |
ace4dfee | 778 | nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state) |
1da177e4 | 779 | { |
ace4dfee TG |
780 | spinlock_t *lock = &chip->controller->lock; |
781 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 782 | DECLARE_WAITQUEUE(wait, current); |
7351d3a5 | 783 | retry: |
0dfc6246 TG |
784 | spin_lock(lock); |
785 | ||
b8b3ee9a | 786 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
787 | if (!chip->controller->active) |
788 | chip->controller->active = chip; | |
a36ed299 | 789 | |
ace4dfee TG |
790 | if (chip->controller->active == chip && chip->state == FL_READY) { |
791 | chip->state = new_state; | |
0dfc6246 | 792 | spin_unlock(lock); |
962034f4 VW |
793 | return 0; |
794 | } | |
795 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
796 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
797 | chip->state = FL_PM_SUSPENDED; | |
798 | spin_unlock(lock); | |
799 | return 0; | |
6b0d9a84 | 800 | } |
0dfc6246 TG |
801 | } |
802 | set_current_state(TASK_UNINTERRUPTIBLE); | |
803 | add_wait_queue(wq, &wait); | |
804 | spin_unlock(lock); | |
805 | schedule(); | |
806 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
807 | goto retry; |
808 | } | |
809 | ||
2af7c653 SK |
810 | /** |
811 | * panic_nand_wait - [GENERIC] wait until the command is done | |
812 | * @mtd: MTD device structure | |
813 | * @chip: NAND chip structure | |
814 | * @timeo: Timeout | |
815 | * | |
816 | * Wait for command done. This is a helper function for nand_wait used when | |
817 | * we are in interrupt context. May happen when in panic and trying to write | |
b595076a | 818 | * an oops through mtdoops. |
2af7c653 SK |
819 | */ |
820 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
821 | unsigned long timeo) | |
822 | { | |
823 | int i; | |
824 | for (i = 0; i < timeo; i++) { | |
825 | if (chip->dev_ready) { | |
826 | if (chip->dev_ready(mtd)) | |
827 | break; | |
828 | } else { | |
829 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
830 | break; | |
831 | } | |
832 | mdelay(1); | |
f8ac0414 | 833 | } |
2af7c653 SK |
834 | } |
835 | ||
1da177e4 LT |
836 | /** |
837 | * nand_wait - [DEFAULT] wait until the command is done | |
838 | * @mtd: MTD device structure | |
844d3b42 | 839 | * @chip: NAND chip structure |
1da177e4 LT |
840 | * |
841 | * Wait for command done. This applies to erase and program only | |
61b03bd7 | 842 | * Erase can take up to 400ms and program up to 20ms according to |
1da177e4 | 843 | * general NAND and SmartMedia specs |
844d3b42 | 844 | */ |
7bc3312b | 845 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
846 | { |
847 | ||
e0c7d767 | 848 | unsigned long timeo = jiffies; |
7bc3312b | 849 | int status, state = chip->state; |
61b03bd7 | 850 | |
1da177e4 | 851 | if (state == FL_ERASING) |
e0c7d767 | 852 | timeo += (HZ * 400) / 1000; |
1da177e4 | 853 | else |
e0c7d767 | 854 | timeo += (HZ * 20) / 1000; |
1da177e4 | 855 | |
8fe833c1 RP |
856 | led_trigger_event(nand_led_trigger, LED_FULL); |
857 | ||
1da177e4 LT |
858 | /* Apply this short delay always to ensure that we do wait tWB in |
859 | * any case on any machine. */ | |
e0c7d767 | 860 | ndelay(100); |
1da177e4 | 861 | |
ace4dfee TG |
862 | if ((state == FL_ERASING) && (chip->options & NAND_IS_AND)) |
863 | chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); | |
61b03bd7 | 864 | else |
ace4dfee | 865 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 866 | |
2af7c653 SK |
867 | if (in_interrupt() || oops_in_progress) |
868 | panic_nand_wait(mtd, chip, timeo); | |
869 | else { | |
870 | while (time_before(jiffies, timeo)) { | |
871 | if (chip->dev_ready) { | |
872 | if (chip->dev_ready(mtd)) | |
873 | break; | |
874 | } else { | |
875 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
876 | break; | |
877 | } | |
878 | cond_resched(); | |
1da177e4 | 879 | } |
1da177e4 | 880 | } |
8fe833c1 RP |
881 | led_trigger_event(nand_led_trigger, LED_OFF); |
882 | ||
ace4dfee | 883 | status = (int)chip->read_byte(mtd); |
1da177e4 LT |
884 | return status; |
885 | } | |
886 | ||
7d70f334 | 887 | /** |
b6d676db | 888 | * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
7d70f334 | 889 | * |
b6d676db RD |
890 | * @mtd: mtd info |
891 | * @ofs: offset to start unlock from | |
892 | * @len: length to unlock | |
893 | * @invert: when = 0, unlock the range of blocks within the lower and | |
7d70f334 | 894 | * upper boundary address |
b6d676db | 895 | * when = 1, unlock the range of blocks outside the boundaries |
7d70f334 VS |
896 | * of the lower and upper boundary address |
897 | * | |
b6d676db | 898 | * return - unlock status |
7d70f334 VS |
899 | */ |
900 | static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, | |
901 | uint64_t len, int invert) | |
902 | { | |
903 | int ret = 0; | |
904 | int status, page; | |
905 | struct nand_chip *chip = mtd->priv; | |
906 | ||
907 | /* Submit address of first page to unlock */ | |
908 | page = ofs >> chip->page_shift; | |
909 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); | |
910 | ||
911 | /* Submit address of last page to unlock */ | |
912 | page = (ofs + len) >> chip->page_shift; | |
913 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, | |
914 | (page | invert) & chip->pagemask); | |
915 | ||
916 | /* Call wait ready function */ | |
917 | status = chip->waitfunc(mtd, chip); | |
7d70f334 VS |
918 | /* See if device thinks it succeeded */ |
919 | if (status & 0x01) { | |
920 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n", | |
921 | __func__, status); | |
922 | ret = -EIO; | |
923 | } | |
924 | ||
925 | return ret; | |
926 | } | |
927 | ||
928 | /** | |
b6d676db | 929 | * nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
7d70f334 | 930 | * |
b6d676db RD |
931 | * @mtd: mtd info |
932 | * @ofs: offset to start unlock from | |
933 | * @len: length to unlock | |
7d70f334 | 934 | * |
b6d676db | 935 | * return - unlock status |
7d70f334 VS |
936 | */ |
937 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
938 | { | |
939 | int ret = 0; | |
940 | int chipnr; | |
941 | struct nand_chip *chip = mtd->priv; | |
942 | ||
943 | DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n", | |
944 | __func__, (unsigned long long)ofs, len); | |
945 | ||
946 | if (check_offs_len(mtd, ofs, len)) | |
947 | ret = -EINVAL; | |
948 | ||
949 | /* Align to last block address if size addresses end of the device */ | |
950 | if (ofs + len == mtd->size) | |
951 | len -= mtd->erasesize; | |
952 | ||
953 | nand_get_device(chip, mtd, FL_UNLOCKING); | |
954 | ||
955 | /* Shift to get chip number */ | |
956 | chipnr = ofs >> chip->chip_shift; | |
957 | ||
958 | chip->select_chip(mtd, chipnr); | |
959 | ||
960 | /* Check, if it is write protected */ | |
961 | if (nand_check_wp(mtd)) { | |
962 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n", | |
963 | __func__); | |
964 | ret = -EIO; | |
965 | goto out; | |
966 | } | |
967 | ||
968 | ret = __nand_unlock(mtd, ofs, len, 0); | |
969 | ||
970 | out: | |
7d70f334 VS |
971 | nand_release_device(mtd); |
972 | ||
973 | return ret; | |
974 | } | |
7351d3a5 | 975 | EXPORT_SYMBOL(nand_unlock); |
7d70f334 VS |
976 | |
977 | /** | |
b6d676db | 978 | * nand_lock - [REPLACEABLE] locks all blocks present in the device |
7d70f334 | 979 | * |
b6d676db RD |
980 | * @mtd: mtd info |
981 | * @ofs: offset to start unlock from | |
982 | * @len: length to unlock | |
7d70f334 | 983 | * |
b6d676db | 984 | * return - lock status |
7d70f334 | 985 | * |
b6d676db RD |
986 | * This feature is not supported in many NAND parts. 'Micron' NAND parts |
987 | * do have this feature, but it allows only to lock all blocks, not for | |
7d70f334 VS |
988 | * specified range for block. |
989 | * | |
990 | * Implementing 'lock' feature by making use of 'unlock', for now. | |
991 | */ | |
992 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
993 | { | |
994 | int ret = 0; | |
995 | int chipnr, status, page; | |
996 | struct nand_chip *chip = mtd->priv; | |
997 | ||
998 | DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n", | |
999 | __func__, (unsigned long long)ofs, len); | |
1000 | ||
1001 | if (check_offs_len(mtd, ofs, len)) | |
1002 | ret = -EINVAL; | |
1003 | ||
1004 | nand_get_device(chip, mtd, FL_LOCKING); | |
1005 | ||
1006 | /* Shift to get chip number */ | |
1007 | chipnr = ofs >> chip->chip_shift; | |
1008 | ||
1009 | chip->select_chip(mtd, chipnr); | |
1010 | ||
1011 | /* Check, if it is write protected */ | |
1012 | if (nand_check_wp(mtd)) { | |
1013 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n", | |
1014 | __func__); | |
1015 | status = MTD_ERASE_FAILED; | |
1016 | ret = -EIO; | |
1017 | goto out; | |
1018 | } | |
1019 | ||
1020 | /* Submit address of first page to lock */ | |
1021 | page = ofs >> chip->page_shift; | |
1022 | chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); | |
1023 | ||
1024 | /* Call wait ready function */ | |
1025 | status = chip->waitfunc(mtd, chip); | |
7d70f334 VS |
1026 | /* See if device thinks it succeeded */ |
1027 | if (status & 0x01) { | |
1028 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n", | |
1029 | __func__, status); | |
1030 | ret = -EIO; | |
1031 | goto out; | |
1032 | } | |
1033 | ||
1034 | ret = __nand_unlock(mtd, ofs, len, 0x1); | |
1035 | ||
1036 | out: | |
7d70f334 VS |
1037 | nand_release_device(mtd); |
1038 | ||
1039 | return ret; | |
1040 | } | |
7351d3a5 | 1041 | EXPORT_SYMBOL(nand_lock); |
7d70f334 | 1042 | |
8593fbc6 TG |
1043 | /** |
1044 | * nand_read_page_raw - [Intern] read raw page data without ecc | |
1045 | * @mtd: mtd info structure | |
1046 | * @chip: nand chip info structure | |
1047 | * @buf: buffer to store read data | |
58475fb9 | 1048 | * @page: page number to read |
52ff49df DB |
1049 | * |
1050 | * Not for syndrome calculating ecc controllers, which use a special oob layout | |
8593fbc6 TG |
1051 | */ |
1052 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
46a8cf2d | 1053 | uint8_t *buf, int page) |
8593fbc6 TG |
1054 | { |
1055 | chip->read_buf(mtd, buf, mtd->writesize); | |
1056 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1057 | return 0; | |
1058 | } | |
1059 | ||
52ff49df DB |
1060 | /** |
1061 | * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc | |
1062 | * @mtd: mtd info structure | |
1063 | * @chip: nand chip info structure | |
1064 | * @buf: buffer to store read data | |
58475fb9 | 1065 | * @page: page number to read |
52ff49df DB |
1066 | * |
1067 | * We need a special oob layout and handling even when OOB isn't used. | |
1068 | */ | |
7351d3a5 FF |
1069 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, |
1070 | struct nand_chip *chip, | |
1071 | uint8_t *buf, int page) | |
52ff49df DB |
1072 | { |
1073 | int eccsize = chip->ecc.size; | |
1074 | int eccbytes = chip->ecc.bytes; | |
1075 | uint8_t *oob = chip->oob_poi; | |
1076 | int steps, size; | |
1077 | ||
1078 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1079 | chip->read_buf(mtd, buf, eccsize); | |
1080 | buf += eccsize; | |
1081 | ||
1082 | if (chip->ecc.prepad) { | |
1083 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1084 | oob += chip->ecc.prepad; | |
1085 | } | |
1086 | ||
1087 | chip->read_buf(mtd, oob, eccbytes); | |
1088 | oob += eccbytes; | |
1089 | ||
1090 | if (chip->ecc.postpad) { | |
1091 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1092 | oob += chip->ecc.postpad; | |
1093 | } | |
1094 | } | |
1095 | ||
1096 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1097 | if (size) | |
1098 | chip->read_buf(mtd, oob, size); | |
1099 | ||
1100 | return 0; | |
1101 | } | |
1102 | ||
1da177e4 | 1103 | /** |
d29ebdbe | 1104 | * nand_read_page_swecc - [REPLACABLE] software ecc based page read function |
f5bbdacc TG |
1105 | * @mtd: mtd info structure |
1106 | * @chip: nand chip info structure | |
1107 | * @buf: buffer to store read data | |
58475fb9 | 1108 | * @page: page number to read |
068e3c0a | 1109 | */ |
f5bbdacc | 1110 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
46a8cf2d | 1111 | uint8_t *buf, int page) |
1da177e4 | 1112 | { |
f5bbdacc TG |
1113 | int i, eccsize = chip->ecc.size; |
1114 | int eccbytes = chip->ecc.bytes; | |
1115 | int eccsteps = chip->ecc.steps; | |
1116 | uint8_t *p = buf; | |
4bf63fcb DW |
1117 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1118 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1119 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
f5bbdacc | 1120 | |
46a8cf2d | 1121 | chip->ecc.read_page_raw(mtd, chip, buf, page); |
f5bbdacc TG |
1122 | |
1123 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1124 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1125 | ||
1126 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 1127 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
1128 | |
1129 | eccsteps = chip->ecc.steps; | |
1130 | p = buf; | |
1131 | ||
1132 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1133 | int stat; | |
1134 | ||
1135 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
c32b8dcc | 1136 | if (stat < 0) |
f5bbdacc TG |
1137 | mtd->ecc_stats.failed++; |
1138 | else | |
1139 | mtd->ecc_stats.corrected += stat; | |
1140 | } | |
1141 | return 0; | |
22c60f5f | 1142 | } |
1da177e4 | 1143 | |
3d459559 AK |
1144 | /** |
1145 | * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function | |
1146 | * @mtd: mtd info structure | |
1147 | * @chip: nand chip info structure | |
17c1d2be AK |
1148 | * @data_offs: offset of requested data within the page |
1149 | * @readlen: data length | |
1150 | * @bufpoi: buffer to store read data | |
3d459559 | 1151 | */ |
7351d3a5 FF |
1152 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, |
1153 | uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi) | |
3d459559 AK |
1154 | { |
1155 | int start_step, end_step, num_steps; | |
1156 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1157 | uint8_t *p; | |
1158 | int data_col_addr, i, gaps = 0; | |
1159 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1160 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
7351d3a5 | 1161 | int index = 0; |
3d459559 AK |
1162 | |
1163 | /* Column address wihin the page aligned to ECC size (256bytes). */ | |
1164 | start_step = data_offs / chip->ecc.size; | |
1165 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1166 | num_steps = end_step - start_step + 1; | |
1167 | ||
1168 | /* Data size aligned to ECC ecc.size*/ | |
1169 | datafrag_len = num_steps * chip->ecc.size; | |
1170 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1171 | ||
1172 | data_col_addr = start_step * chip->ecc.size; | |
1173 | /* If we read not a page aligned data */ | |
1174 | if (data_col_addr != 0) | |
1175 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1176 | ||
1177 | p = bufpoi + data_col_addr; | |
1178 | chip->read_buf(mtd, p, datafrag_len); | |
1179 | ||
1180 | /* Calculate ECC */ | |
1181 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) | |
1182 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1183 | ||
1184 | /* The performance is faster if to position offsets | |
1185 | according to ecc.pos. Let make sure here that | |
1186 | there are no gaps in ecc positions */ | |
1187 | for (i = 0; i < eccfrag_len - 1; i++) { | |
1188 | if (eccpos[i + start_step * chip->ecc.bytes] + 1 != | |
1189 | eccpos[i + start_step * chip->ecc.bytes + 1]) { | |
1190 | gaps = 1; | |
1191 | break; | |
1192 | } | |
1193 | } | |
1194 | if (gaps) { | |
1195 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1196 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1197 | } else { | |
1198 | /* send the command to read the particular ecc bytes */ | |
1199 | /* take care about buswidth alignment in read_buf */ | |
7351d3a5 FF |
1200 | index = start_step * chip->ecc.bytes; |
1201 | ||
1202 | aligned_pos = eccpos[index] & ~(busw - 1); | |
3d459559 | 1203 | aligned_len = eccfrag_len; |
7351d3a5 | 1204 | if (eccpos[index] & (busw - 1)) |
3d459559 | 1205 | aligned_len++; |
7351d3a5 | 1206 | if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1)) |
3d459559 AK |
1207 | aligned_len++; |
1208 | ||
7351d3a5 FF |
1209 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, |
1210 | mtd->writesize + aligned_pos, -1); | |
3d459559 AK |
1211 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); |
1212 | } | |
1213 | ||
1214 | for (i = 0; i < eccfrag_len; i++) | |
7351d3a5 | 1215 | chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]]; |
3d459559 AK |
1216 | |
1217 | p = bufpoi + data_col_addr; | |
1218 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1219 | int stat; | |
1220 | ||
7351d3a5 FF |
1221 | stat = chip->ecc.correct(mtd, p, |
1222 | &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
12c8eb98 | 1223 | if (stat < 0) |
3d459559 AK |
1224 | mtd->ecc_stats.failed++; |
1225 | else | |
1226 | mtd->ecc_stats.corrected += stat; | |
1227 | } | |
1228 | return 0; | |
1229 | } | |
1230 | ||
068e3c0a | 1231 | /** |
d29ebdbe | 1232 | * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function |
f5bbdacc TG |
1233 | * @mtd: mtd info structure |
1234 | * @chip: nand chip info structure | |
1235 | * @buf: buffer to store read data | |
58475fb9 | 1236 | * @page: page number to read |
068e3c0a | 1237 | * |
f5bbdacc | 1238 | * Not for syndrome calculating ecc controllers which need a special oob layout |
068e3c0a | 1239 | */ |
f5bbdacc | 1240 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
46a8cf2d | 1241 | uint8_t *buf, int page) |
1da177e4 | 1242 | { |
f5bbdacc TG |
1243 | int i, eccsize = chip->ecc.size; |
1244 | int eccbytes = chip->ecc.bytes; | |
1245 | int eccsteps = chip->ecc.steps; | |
1246 | uint8_t *p = buf; | |
4bf63fcb DW |
1247 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1248 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1249 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
f5bbdacc TG |
1250 | |
1251 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1252 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1253 | chip->read_buf(mtd, p, eccsize); | |
1254 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1255 | } |
f75e5097 | 1256 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1257 | |
f5bbdacc | 1258 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 1259 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 1260 | |
f5bbdacc TG |
1261 | eccsteps = chip->ecc.steps; |
1262 | p = buf; | |
61b03bd7 | 1263 | |
f5bbdacc TG |
1264 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1265 | int stat; | |
1da177e4 | 1266 | |
f5bbdacc | 1267 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
c32b8dcc | 1268 | if (stat < 0) |
f5bbdacc TG |
1269 | mtd->ecc_stats.failed++; |
1270 | else | |
1271 | mtd->ecc_stats.corrected += stat; | |
1272 | } | |
1273 | return 0; | |
1274 | } | |
1da177e4 | 1275 | |
6e0cb135 SN |
1276 | /** |
1277 | * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first | |
1278 | * @mtd: mtd info structure | |
1279 | * @chip: nand chip info structure | |
1280 | * @buf: buffer to store read data | |
58475fb9 | 1281 | * @page: page number to read |
6e0cb135 SN |
1282 | * |
1283 | * Hardware ECC for large page chips, require OOB to be read first. | |
1284 | * For this ECC mode, the write_page method is re-used from ECC_HW. | |
1285 | * These methods read/write ECC from the OOB area, unlike the | |
1286 | * ECC_HW_SYNDROME support with multiple ECC steps, follows the | |
1287 | * "infix ECC" scheme and reads/writes ECC from the data area, by | |
1288 | * overwriting the NAND manufacturer bad block markings. | |
1289 | */ | |
1290 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1291 | struct nand_chip *chip, uint8_t *buf, int page) | |
1292 | { | |
1293 | int i, eccsize = chip->ecc.size; | |
1294 | int eccbytes = chip->ecc.bytes; | |
1295 | int eccsteps = chip->ecc.steps; | |
1296 | uint8_t *p = buf; | |
1297 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1298 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1299 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
1300 | ||
1301 | /* Read the OOB area first */ | |
1302 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1303 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1304 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1305 | ||
1306 | for (i = 0; i < chip->ecc.total; i++) | |
1307 | ecc_code[i] = chip->oob_poi[eccpos[i]]; | |
1308 | ||
1309 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1310 | int stat; | |
1311 | ||
1312 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1313 | chip->read_buf(mtd, p, eccsize); | |
1314 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1315 | ||
1316 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
1317 | if (stat < 0) | |
1318 | mtd->ecc_stats.failed++; | |
1319 | else | |
1320 | mtd->ecc_stats.corrected += stat; | |
1321 | } | |
1322 | return 0; | |
1323 | } | |
1324 | ||
f5bbdacc | 1325 | /** |
d29ebdbe | 1326 | * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read |
f5bbdacc TG |
1327 | * @mtd: mtd info structure |
1328 | * @chip: nand chip info structure | |
1329 | * @buf: buffer to store read data | |
58475fb9 | 1330 | * @page: page number to read |
f5bbdacc TG |
1331 | * |
1332 | * The hw generator calculates the error syndrome automatically. Therefor | |
f75e5097 | 1333 | * we need a special oob layout and handling. |
f5bbdacc TG |
1334 | */ |
1335 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
46a8cf2d | 1336 | uint8_t *buf, int page) |
f5bbdacc TG |
1337 | { |
1338 | int i, eccsize = chip->ecc.size; | |
1339 | int eccbytes = chip->ecc.bytes; | |
1340 | int eccsteps = chip->ecc.steps; | |
1341 | uint8_t *p = buf; | |
f75e5097 | 1342 | uint8_t *oob = chip->oob_poi; |
1da177e4 | 1343 | |
f5bbdacc TG |
1344 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1345 | int stat; | |
61b03bd7 | 1346 | |
f5bbdacc TG |
1347 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1348 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1349 | |
f5bbdacc TG |
1350 | if (chip->ecc.prepad) { |
1351 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1352 | oob += chip->ecc.prepad; | |
1353 | } | |
1da177e4 | 1354 | |
f5bbdacc TG |
1355 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1356 | chip->read_buf(mtd, oob, eccbytes); | |
1357 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1358 | |
c32b8dcc | 1359 | if (stat < 0) |
f5bbdacc | 1360 | mtd->ecc_stats.failed++; |
61b03bd7 | 1361 | else |
f5bbdacc | 1362 | mtd->ecc_stats.corrected += stat; |
61b03bd7 | 1363 | |
f5bbdacc | 1364 | oob += eccbytes; |
1da177e4 | 1365 | |
f5bbdacc TG |
1366 | if (chip->ecc.postpad) { |
1367 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1368 | oob += chip->ecc.postpad; | |
61b03bd7 | 1369 | } |
f5bbdacc | 1370 | } |
1da177e4 | 1371 | |
f5bbdacc | 1372 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1373 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1374 | if (i) |
1375 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1376 | |
f5bbdacc TG |
1377 | return 0; |
1378 | } | |
1da177e4 | 1379 | |
f5bbdacc | 1380 | /** |
8593fbc6 TG |
1381 | * nand_transfer_oob - [Internal] Transfer oob to client buffer |
1382 | * @chip: nand chip structure | |
844d3b42 | 1383 | * @oob: oob destination address |
8593fbc6 | 1384 | * @ops: oob ops structure |
7014568b | 1385 | * @len: size of oob to transfer |
8593fbc6 TG |
1386 | */ |
1387 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
7014568b | 1388 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1389 | { |
f8ac0414 | 1390 | switch (ops->mode) { |
8593fbc6 TG |
1391 | |
1392 | case MTD_OOB_PLACE: | |
1393 | case MTD_OOB_RAW: | |
1394 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); | |
1395 | return oob + len; | |
1396 | ||
1397 | case MTD_OOB_AUTO: { | |
1398 | struct nand_oobfree *free = chip->ecc.layout->oobfree; | |
7bc3312b TG |
1399 | uint32_t boffs = 0, roffs = ops->ooboffs; |
1400 | size_t bytes = 0; | |
8593fbc6 | 1401 | |
f8ac0414 | 1402 | for (; free->length && len; free++, len -= bytes) { |
7bc3312b TG |
1403 | /* Read request not from offset 0 ? */ |
1404 | if (unlikely(roffs)) { | |
1405 | if (roffs >= free->length) { | |
1406 | roffs -= free->length; | |
1407 | continue; | |
1408 | } | |
1409 | boffs = free->offset + roffs; | |
1410 | bytes = min_t(size_t, len, | |
1411 | (free->length - roffs)); | |
1412 | roffs = 0; | |
1413 | } else { | |
1414 | bytes = min_t(size_t, len, free->length); | |
1415 | boffs = free->offset; | |
1416 | } | |
1417 | memcpy(oob, chip->oob_poi + boffs, bytes); | |
8593fbc6 TG |
1418 | oob += bytes; |
1419 | } | |
1420 | return oob; | |
1421 | } | |
1422 | default: | |
1423 | BUG(); | |
1424 | } | |
1425 | return NULL; | |
1426 | } | |
1427 | ||
1428 | /** | |
1429 | * nand_do_read_ops - [Internal] Read data with ECC | |
f5bbdacc TG |
1430 | * |
1431 | * @mtd: MTD device structure | |
1432 | * @from: offset to read from | |
844d3b42 | 1433 | * @ops: oob ops structure |
f5bbdacc TG |
1434 | * |
1435 | * Internal function. Called with chip held. | |
1436 | */ | |
8593fbc6 TG |
1437 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1438 | struct mtd_oob_ops *ops) | |
f5bbdacc TG |
1439 | { |
1440 | int chipnr, page, realpage, col, bytes, aligned; | |
1441 | struct nand_chip *chip = mtd->priv; | |
1442 | struct mtd_ecc_stats stats; | |
1443 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
1444 | int sndcmd = 1; | |
1445 | int ret = 0; | |
8593fbc6 | 1446 | uint32_t readlen = ops->len; |
7014568b | 1447 | uint32_t oobreadlen = ops->ooblen; |
9aca334e ML |
1448 | uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ? |
1449 | mtd->oobavail : mtd->oobsize; | |
1450 | ||
8593fbc6 | 1451 | uint8_t *bufpoi, *oob, *buf; |
1da177e4 | 1452 | |
f5bbdacc | 1453 | stats = mtd->ecc_stats; |
1da177e4 | 1454 | |
f5bbdacc TG |
1455 | chipnr = (int)(from >> chip->chip_shift); |
1456 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 1457 | |
f5bbdacc TG |
1458 | realpage = (int)(from >> chip->page_shift); |
1459 | page = realpage & chip->pagemask; | |
1da177e4 | 1460 | |
f5bbdacc | 1461 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 1462 | |
8593fbc6 TG |
1463 | buf = ops->datbuf; |
1464 | oob = ops->oobbuf; | |
1465 | ||
f8ac0414 | 1466 | while (1) { |
f5bbdacc TG |
1467 | bytes = min(mtd->writesize - col, readlen); |
1468 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 1469 | |
f5bbdacc | 1470 | /* Is the current page in the buffer ? */ |
8593fbc6 | 1471 | if (realpage != chip->pagebuf || oob) { |
4bf63fcb | 1472 | bufpoi = aligned ? buf : chip->buffers->databuf; |
61b03bd7 | 1473 | |
f5bbdacc TG |
1474 | if (likely(sndcmd)) { |
1475 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); | |
1476 | sndcmd = 0; | |
1da177e4 | 1477 | } |
1da177e4 | 1478 | |
f5bbdacc | 1479 | /* Now read the page into the buffer */ |
956e944c | 1480 | if (unlikely(ops->mode == MTD_OOB_RAW)) |
46a8cf2d SN |
1481 | ret = chip->ecc.read_page_raw(mtd, chip, |
1482 | bufpoi, page); | |
3d459559 | 1483 | else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob) |
7351d3a5 FF |
1484 | ret = chip->ecc.read_subpage(mtd, chip, |
1485 | col, bytes, bufpoi); | |
956e944c | 1486 | else |
46a8cf2d SN |
1487 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
1488 | page); | |
f5bbdacc | 1489 | if (ret < 0) |
1da177e4 | 1490 | break; |
f5bbdacc TG |
1491 | |
1492 | /* Transfer not aligned data */ | |
1493 | if (!aligned) { | |
c1194c79 AB |
1494 | if (!NAND_SUBPAGE_READ(chip) && !oob && |
1495 | !(mtd->ecc_stats.failed - stats.failed)) | |
3d459559 | 1496 | chip->pagebuf = realpage; |
4bf63fcb | 1497 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1498 | } |
1499 | ||
8593fbc6 TG |
1500 | buf += bytes; |
1501 | ||
1502 | if (unlikely(oob)) { | |
9aca334e | 1503 | |
b64d39d8 ML |
1504 | int toread = min(oobreadlen, max_oobsize); |
1505 | ||
1506 | if (toread) { | |
1507 | oob = nand_transfer_oob(chip, | |
1508 | oob, ops, toread); | |
1509 | oobreadlen -= toread; | |
1510 | } | |
8593fbc6 TG |
1511 | } |
1512 | ||
f5bbdacc TG |
1513 | if (!(chip->options & NAND_NO_READRDY)) { |
1514 | /* | |
1515 | * Apply delay or wait for ready/busy pin. Do | |
1516 | * this before the AUTOINCR check, so no | |
1517 | * problems arise if a chip which does auto | |
1518 | * increment is marked as NOAUTOINCR by the | |
1519 | * board driver. | |
1520 | */ | |
1521 | if (!chip->dev_ready) | |
1522 | udelay(chip->chip_delay); | |
1523 | else | |
1524 | nand_wait_ready(mtd); | |
1da177e4 | 1525 | } |
8593fbc6 | 1526 | } else { |
4bf63fcb | 1527 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 TG |
1528 | buf += bytes; |
1529 | } | |
1da177e4 | 1530 | |
f5bbdacc | 1531 | readlen -= bytes; |
61b03bd7 | 1532 | |
f5bbdacc | 1533 | if (!readlen) |
61b03bd7 | 1534 | break; |
1da177e4 LT |
1535 | |
1536 | /* For subsequent reads align to page boundary. */ | |
1537 | col = 0; | |
1538 | /* Increment page address */ | |
1539 | realpage++; | |
1540 | ||
ace4dfee | 1541 | page = realpage & chip->pagemask; |
1da177e4 LT |
1542 | /* Check, if we cross a chip boundary */ |
1543 | if (!page) { | |
1544 | chipnr++; | |
ace4dfee TG |
1545 | chip->select_chip(mtd, -1); |
1546 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1547 | } |
f5bbdacc | 1548 | |
61b03bd7 TG |
1549 | /* Check, if the chip supports auto page increment |
1550 | * or if we have hit a block boundary. | |
e0c7d767 | 1551 | */ |
f5bbdacc | 1552 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) |
61b03bd7 | 1553 | sndcmd = 1; |
1da177e4 LT |
1554 | } |
1555 | ||
8593fbc6 | 1556 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
1557 | if (oob) |
1558 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 1559 | |
f5bbdacc TG |
1560 | if (ret) |
1561 | return ret; | |
1562 | ||
9a1fcdfd TG |
1563 | if (mtd->ecc_stats.failed - stats.failed) |
1564 | return -EBADMSG; | |
1565 | ||
1566 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
f5bbdacc TG |
1567 | } |
1568 | ||
1569 | /** | |
25985edc | 1570 | * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc |
f5bbdacc TG |
1571 | * @mtd: MTD device structure |
1572 | * @from: offset to read from | |
1573 | * @len: number of bytes to read | |
1574 | * @retlen: pointer to variable to store the number of read bytes | |
1575 | * @buf: the databuffer to put data | |
1576 | * | |
1577 | * Get hold of the chip and call nand_do_read | |
1578 | */ | |
1579 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1580 | size_t *retlen, uint8_t *buf) | |
1581 | { | |
8593fbc6 | 1582 | struct nand_chip *chip = mtd->priv; |
f5bbdacc TG |
1583 | int ret; |
1584 | ||
f5bbdacc TG |
1585 | /* Do not allow reads past end of device */ |
1586 | if ((from + len) > mtd->size) | |
1587 | return -EINVAL; | |
1588 | if (!len) | |
1589 | return 0; | |
1590 | ||
8593fbc6 | 1591 | nand_get_device(chip, mtd, FL_READING); |
f5bbdacc | 1592 | |
8593fbc6 TG |
1593 | chip->ops.len = len; |
1594 | chip->ops.datbuf = buf; | |
1595 | chip->ops.oobbuf = NULL; | |
1596 | ||
1597 | ret = nand_do_read_ops(mtd, from, &chip->ops); | |
f5bbdacc | 1598 | |
7fd5aecc RP |
1599 | *retlen = chip->ops.retlen; |
1600 | ||
f5bbdacc TG |
1601 | nand_release_device(mtd); |
1602 | ||
1603 | return ret; | |
1da177e4 LT |
1604 | } |
1605 | ||
7bc3312b TG |
1606 | /** |
1607 | * nand_read_oob_std - [REPLACABLE] the most common OOB data read function | |
1608 | * @mtd: mtd info structure | |
1609 | * @chip: nand chip info structure | |
1610 | * @page: page number to read | |
1611 | * @sndcmd: flag whether to issue read command or not | |
1612 | */ | |
1613 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1614 | int page, int sndcmd) | |
1615 | { | |
1616 | if (sndcmd) { | |
1617 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1618 | sndcmd = 0; | |
1619 | } | |
1620 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1621 | return sndcmd; | |
1622 | } | |
1623 | ||
1624 | /** | |
1625 | * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC | |
1626 | * with syndromes | |
1627 | * @mtd: mtd info structure | |
1628 | * @chip: nand chip info structure | |
1629 | * @page: page number to read | |
1630 | * @sndcmd: flag whether to issue read command or not | |
1631 | */ | |
1632 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1633 | int page, int sndcmd) | |
1634 | { | |
1635 | uint8_t *buf = chip->oob_poi; | |
1636 | int length = mtd->oobsize; | |
1637 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1638 | int eccsize = chip->ecc.size; | |
1639 | uint8_t *bufpoi = buf; | |
1640 | int i, toread, sndrnd = 0, pos; | |
1641 | ||
1642 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
1643 | for (i = 0; i < chip->ecc.steps; i++) { | |
1644 | if (sndrnd) { | |
1645 | pos = eccsize + i * (eccsize + chunk); | |
1646 | if (mtd->writesize > 512) | |
1647 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
1648 | else | |
1649 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
1650 | } else | |
1651 | sndrnd = 1; | |
1652 | toread = min_t(int, length, chunk); | |
1653 | chip->read_buf(mtd, bufpoi, toread); | |
1654 | bufpoi += toread; | |
1655 | length -= toread; | |
1656 | } | |
1657 | if (length > 0) | |
1658 | chip->read_buf(mtd, bufpoi, length); | |
1659 | ||
1660 | return 1; | |
1661 | } | |
1662 | ||
1663 | /** | |
1664 | * nand_write_oob_std - [REPLACABLE] the most common OOB data write function | |
1665 | * @mtd: mtd info structure | |
1666 | * @chip: nand chip info structure | |
1667 | * @page: page number to write | |
1668 | */ | |
1669 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1670 | int page) | |
1671 | { | |
1672 | int status = 0; | |
1673 | const uint8_t *buf = chip->oob_poi; | |
1674 | int length = mtd->oobsize; | |
1675 | ||
1676 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
1677 | chip->write_buf(mtd, buf, length); | |
1678 | /* Send command to program the OOB data */ | |
1679 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1680 | ||
1681 | status = chip->waitfunc(mtd, chip); | |
1682 | ||
0d420f9d | 1683 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b TG |
1684 | } |
1685 | ||
1686 | /** | |
1687 | * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC | |
1688 | * with syndrome - only for large page flash ! | |
1689 | * @mtd: mtd info structure | |
1690 | * @chip: nand chip info structure | |
1691 | * @page: page number to write | |
1692 | */ | |
1693 | static int nand_write_oob_syndrome(struct mtd_info *mtd, | |
1694 | struct nand_chip *chip, int page) | |
1695 | { | |
1696 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1697 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
1698 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
1699 | const uint8_t *bufpoi = chip->oob_poi; | |
1700 | ||
1701 | /* | |
1702 | * data-ecc-data-ecc ... ecc-oob | |
1703 | * or | |
1704 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
1705 | */ | |
1706 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
1707 | pos = steps * (eccsize + chunk); | |
1708 | steps = 0; | |
1709 | } else | |
8b0036ee | 1710 | pos = eccsize; |
7bc3312b TG |
1711 | |
1712 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
1713 | for (i = 0; i < steps; i++) { | |
1714 | if (sndcmd) { | |
1715 | if (mtd->writesize <= 512) { | |
1716 | uint32_t fill = 0xFFFFFFFF; | |
1717 | ||
1718 | len = eccsize; | |
1719 | while (len > 0) { | |
1720 | int num = min_t(int, len, 4); | |
1721 | chip->write_buf(mtd, (uint8_t *)&fill, | |
1722 | num); | |
1723 | len -= num; | |
1724 | } | |
1725 | } else { | |
1726 | pos = eccsize + i * (eccsize + chunk); | |
1727 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
1728 | } | |
1729 | } else | |
1730 | sndcmd = 1; | |
1731 | len = min_t(int, length, chunk); | |
1732 | chip->write_buf(mtd, bufpoi, len); | |
1733 | bufpoi += len; | |
1734 | length -= len; | |
1735 | } | |
1736 | if (length > 0) | |
1737 | chip->write_buf(mtd, bufpoi, length); | |
1738 | ||
1739 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1740 | status = chip->waitfunc(mtd, chip); | |
1741 | ||
1742 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
1743 | } | |
1744 | ||
1da177e4 | 1745 | /** |
8593fbc6 | 1746 | * nand_do_read_oob - [Intern] NAND read out-of-band |
1da177e4 LT |
1747 | * @mtd: MTD device structure |
1748 | * @from: offset to read from | |
8593fbc6 | 1749 | * @ops: oob operations description structure |
1da177e4 LT |
1750 | * |
1751 | * NAND read out-of-band data from the spare area | |
1752 | */ | |
8593fbc6 TG |
1753 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
1754 | struct mtd_oob_ops *ops) | |
1da177e4 | 1755 | { |
7bc3312b | 1756 | int page, realpage, chipnr, sndcmd = 1; |
ace4dfee | 1757 | struct nand_chip *chip = mtd->priv; |
7314e9e7 | 1758 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; |
7014568b VW |
1759 | int readlen = ops->ooblen; |
1760 | int len; | |
7bc3312b | 1761 | uint8_t *buf = ops->oobbuf; |
61b03bd7 | 1762 | |
20d8e248 | 1763 | DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n", |
1764 | __func__, (unsigned long long)from, readlen); | |
1da177e4 | 1765 | |
03736155 | 1766 | if (ops->mode == MTD_OOB_AUTO) |
7014568b | 1767 | len = chip->ecc.layout->oobavail; |
03736155 AH |
1768 | else |
1769 | len = mtd->oobsize; | |
1770 | ||
1771 | if (unlikely(ops->ooboffs >= len)) { | |
20d8e248 | 1772 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read " |
1773 | "outside oob\n", __func__); | |
03736155 AH |
1774 | return -EINVAL; |
1775 | } | |
1776 | ||
1777 | /* Do not allow reads past end of device */ | |
1778 | if (unlikely(from >= mtd->size || | |
1779 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
1780 | (from >> chip->page_shift)) * len)) { | |
20d8e248 | 1781 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end " |
1782 | "of device\n", __func__); | |
03736155 AH |
1783 | return -EINVAL; |
1784 | } | |
7014568b | 1785 | |
7314e9e7 | 1786 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 1787 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1788 | |
7314e9e7 TG |
1789 | /* Shift to get page */ |
1790 | realpage = (int)(from >> chip->page_shift); | |
1791 | page = realpage & chip->pagemask; | |
1da177e4 | 1792 | |
f8ac0414 | 1793 | while (1) { |
7bc3312b | 1794 | sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd); |
7014568b VW |
1795 | |
1796 | len = min(len, readlen); | |
1797 | buf = nand_transfer_oob(chip, buf, ops, len); | |
8593fbc6 | 1798 | |
7314e9e7 TG |
1799 | if (!(chip->options & NAND_NO_READRDY)) { |
1800 | /* | |
1801 | * Apply delay or wait for ready/busy pin. Do this | |
1802 | * before the AUTOINCR check, so no problems arise if a | |
1803 | * chip which does auto increment is marked as | |
1804 | * NOAUTOINCR by the board driver. | |
19870da7 | 1805 | */ |
ace4dfee TG |
1806 | if (!chip->dev_ready) |
1807 | udelay(chip->chip_delay); | |
19870da7 TG |
1808 | else |
1809 | nand_wait_ready(mtd); | |
7314e9e7 | 1810 | } |
19870da7 | 1811 | |
7014568b | 1812 | readlen -= len; |
0d420f9d SZ |
1813 | if (!readlen) |
1814 | break; | |
1815 | ||
7314e9e7 TG |
1816 | /* Increment page address */ |
1817 | realpage++; | |
1818 | ||
1819 | page = realpage & chip->pagemask; | |
1820 | /* Check, if we cross a chip boundary */ | |
1821 | if (!page) { | |
1822 | chipnr++; | |
1823 | chip->select_chip(mtd, -1); | |
1824 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1825 | } |
7314e9e7 TG |
1826 | |
1827 | /* Check, if the chip supports auto page increment | |
1828 | * or if we have hit a block boundary. | |
1829 | */ | |
1830 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) | |
1831 | sndcmd = 1; | |
1da177e4 LT |
1832 | } |
1833 | ||
7014568b | 1834 | ops->oobretlen = ops->ooblen; |
1da177e4 LT |
1835 | return 0; |
1836 | } | |
1837 | ||
1838 | /** | |
8593fbc6 | 1839 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
1da177e4 | 1840 | * @mtd: MTD device structure |
1da177e4 | 1841 | * @from: offset to read from |
8593fbc6 | 1842 | * @ops: oob operation description structure |
1da177e4 | 1843 | * |
8593fbc6 | 1844 | * NAND read data and/or out-of-band data |
1da177e4 | 1845 | */ |
8593fbc6 TG |
1846 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
1847 | struct mtd_oob_ops *ops) | |
1da177e4 | 1848 | { |
ace4dfee | 1849 | struct nand_chip *chip = mtd->priv; |
8593fbc6 TG |
1850 | int ret = -ENOTSUPP; |
1851 | ||
1852 | ops->retlen = 0; | |
1da177e4 LT |
1853 | |
1854 | /* Do not allow reads past end of device */ | |
7014568b | 1855 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
20d8e248 | 1856 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read " |
1857 | "beyond end of device\n", __func__); | |
1da177e4 LT |
1858 | return -EINVAL; |
1859 | } | |
1860 | ||
ace4dfee | 1861 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 | 1862 | |
f8ac0414 | 1863 | switch (ops->mode) { |
8593fbc6 TG |
1864 | case MTD_OOB_PLACE: |
1865 | case MTD_OOB_AUTO: | |
8593fbc6 | 1866 | case MTD_OOB_RAW: |
8593fbc6 | 1867 | break; |
1da177e4 | 1868 | |
8593fbc6 TG |
1869 | default: |
1870 | goto out; | |
1871 | } | |
1da177e4 | 1872 | |
8593fbc6 TG |
1873 | if (!ops->datbuf) |
1874 | ret = nand_do_read_oob(mtd, from, ops); | |
1875 | else | |
1876 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 1877 | |
7351d3a5 | 1878 | out: |
8593fbc6 TG |
1879 | nand_release_device(mtd); |
1880 | return ret; | |
1881 | } | |
61b03bd7 | 1882 | |
1da177e4 | 1883 | |
8593fbc6 TG |
1884 | /** |
1885 | * nand_write_page_raw - [Intern] raw page write function | |
1886 | * @mtd: mtd info structure | |
1887 | * @chip: nand chip info structure | |
1888 | * @buf: data buffer | |
52ff49df DB |
1889 | * |
1890 | * Not for syndrome calculating ecc controllers, which use a special oob layout | |
8593fbc6 TG |
1891 | */ |
1892 | static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1893 | const uint8_t *buf) | |
1894 | { | |
1895 | chip->write_buf(mtd, buf, mtd->writesize); | |
1896 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1da177e4 LT |
1897 | } |
1898 | ||
52ff49df DB |
1899 | /** |
1900 | * nand_write_page_raw_syndrome - [Intern] raw page write function | |
1901 | * @mtd: mtd info structure | |
1902 | * @chip: nand chip info structure | |
1903 | * @buf: data buffer | |
1904 | * | |
1905 | * We need a special oob layout and handling even when ECC isn't checked. | |
1906 | */ | |
7351d3a5 FF |
1907 | static void nand_write_page_raw_syndrome(struct mtd_info *mtd, |
1908 | struct nand_chip *chip, | |
1909 | const uint8_t *buf) | |
52ff49df DB |
1910 | { |
1911 | int eccsize = chip->ecc.size; | |
1912 | int eccbytes = chip->ecc.bytes; | |
1913 | uint8_t *oob = chip->oob_poi; | |
1914 | int steps, size; | |
1915 | ||
1916 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1917 | chip->write_buf(mtd, buf, eccsize); | |
1918 | buf += eccsize; | |
1919 | ||
1920 | if (chip->ecc.prepad) { | |
1921 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
1922 | oob += chip->ecc.prepad; | |
1923 | } | |
1924 | ||
1925 | chip->read_buf(mtd, oob, eccbytes); | |
1926 | oob += eccbytes; | |
1927 | ||
1928 | if (chip->ecc.postpad) { | |
1929 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
1930 | oob += chip->ecc.postpad; | |
1931 | } | |
1932 | } | |
1933 | ||
1934 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1935 | if (size) | |
1936 | chip->write_buf(mtd, oob, size); | |
1937 | } | |
9223a456 | 1938 | /** |
d29ebdbe | 1939 | * nand_write_page_swecc - [REPLACABLE] software ecc based page write function |
f75e5097 TG |
1940 | * @mtd: mtd info structure |
1941 | * @chip: nand chip info structure | |
1942 | * @buf: data buffer | |
9223a456 | 1943 | */ |
f75e5097 TG |
1944 | static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1945 | const uint8_t *buf) | |
9223a456 | 1946 | { |
f75e5097 TG |
1947 | int i, eccsize = chip->ecc.size; |
1948 | int eccbytes = chip->ecc.bytes; | |
1949 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1950 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1951 | const uint8_t *p = buf; |
8b099a39 | 1952 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1953 | |
8593fbc6 TG |
1954 | /* Software ecc calculation */ |
1955 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1956 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 1957 | |
8593fbc6 TG |
1958 | for (i = 0; i < chip->ecc.total; i++) |
1959 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 1960 | |
90424de8 | 1961 | chip->ecc.write_page_raw(mtd, chip, buf); |
f75e5097 | 1962 | } |
9223a456 | 1963 | |
f75e5097 | 1964 | /** |
d29ebdbe | 1965 | * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function |
f75e5097 TG |
1966 | * @mtd: mtd info structure |
1967 | * @chip: nand chip info structure | |
1968 | * @buf: data buffer | |
1969 | */ | |
1970 | static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, | |
1971 | const uint8_t *buf) | |
1972 | { | |
1973 | int i, eccsize = chip->ecc.size; | |
1974 | int eccbytes = chip->ecc.bytes; | |
1975 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1976 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1977 | const uint8_t *p = buf; |
8b099a39 | 1978 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1979 | |
f75e5097 TG |
1980 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1981 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 1982 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 1983 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
1984 | } |
1985 | ||
f75e5097 TG |
1986 | for (i = 0; i < chip->ecc.total; i++) |
1987 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
1988 | ||
1989 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
9223a456 TG |
1990 | } |
1991 | ||
61b03bd7 | 1992 | /** |
d29ebdbe | 1993 | * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write |
f75e5097 TG |
1994 | * @mtd: mtd info structure |
1995 | * @chip: nand chip info structure | |
1996 | * @buf: data buffer | |
1da177e4 | 1997 | * |
f75e5097 TG |
1998 | * The hw generator calculates the error syndrome automatically. Therefor |
1999 | * we need a special oob layout and handling. | |
2000 | */ | |
2001 | static void nand_write_page_syndrome(struct mtd_info *mtd, | |
2002 | struct nand_chip *chip, const uint8_t *buf) | |
1da177e4 | 2003 | { |
f75e5097 TG |
2004 | int i, eccsize = chip->ecc.size; |
2005 | int eccbytes = chip->ecc.bytes; | |
2006 | int eccsteps = chip->ecc.steps; | |
2007 | const uint8_t *p = buf; | |
2008 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 2009 | |
f75e5097 | 2010 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 2011 | |
f75e5097 TG |
2012 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
2013 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 2014 | |
f75e5097 TG |
2015 | if (chip->ecc.prepad) { |
2016 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2017 | oob += chip->ecc.prepad; | |
2018 | } | |
2019 | ||
2020 | chip->ecc.calculate(mtd, p, oob); | |
2021 | chip->write_buf(mtd, oob, eccbytes); | |
2022 | oob += eccbytes; | |
2023 | ||
2024 | if (chip->ecc.postpad) { | |
2025 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2026 | oob += chip->ecc.postpad; | |
1da177e4 | 2027 | } |
1da177e4 | 2028 | } |
f75e5097 TG |
2029 | |
2030 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2031 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2032 | if (i) |
2033 | chip->write_buf(mtd, oob, i); | |
2034 | } | |
2035 | ||
2036 | /** | |
956e944c | 2037 | * nand_write_page - [REPLACEABLE] write one page |
f75e5097 TG |
2038 | * @mtd: MTD device structure |
2039 | * @chip: NAND chip descriptor | |
2040 | * @buf: the data to write | |
2041 | * @page: page number to write | |
2042 | * @cached: cached programming | |
efbfe96c | 2043 | * @raw: use _raw version of write_page |
f75e5097 TG |
2044 | */ |
2045 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
956e944c | 2046 | const uint8_t *buf, int page, int cached, int raw) |
f75e5097 TG |
2047 | { |
2048 | int status; | |
2049 | ||
2050 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
2051 | ||
956e944c DW |
2052 | if (unlikely(raw)) |
2053 | chip->ecc.write_page_raw(mtd, chip, buf); | |
2054 | else | |
2055 | chip->ecc.write_page(mtd, chip, buf); | |
f75e5097 TG |
2056 | |
2057 | /* | |
2058 | * Cached progamming disabled for now, Not sure if its worth the | |
2059 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s) | |
2060 | */ | |
2061 | cached = 0; | |
2062 | ||
2063 | if (!cached || !(chip->options & NAND_CACHEPRG)) { | |
2064 | ||
2065 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 2066 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2067 | /* |
2068 | * See if operation failed and additional status checks are | |
2069 | * available | |
2070 | */ | |
2071 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2072 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
2073 | page); | |
2074 | ||
2075 | if (status & NAND_STATUS_FAIL) | |
2076 | return -EIO; | |
2077 | } else { | |
2078 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 2079 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2080 | } |
2081 | ||
2082 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE | |
2083 | /* Send command to read back the data */ | |
2084 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
2085 | ||
2086 | if (chip->verify_buf(mtd, buf, mtd->writesize)) | |
2087 | return -EIO; | |
2088 | #endif | |
2089 | return 0; | |
1da177e4 LT |
2090 | } |
2091 | ||
8593fbc6 TG |
2092 | /** |
2093 | * nand_fill_oob - [Internal] Transfer client buffer to oob | |
2094 | * @chip: nand chip structure | |
2095 | * @oob: oob data buffer | |
b6d676db | 2096 | * @len: oob data write length |
8593fbc6 TG |
2097 | * @ops: oob ops structure |
2098 | */ | |
782ce79a ML |
2099 | static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len, |
2100 | struct mtd_oob_ops *ops) | |
8593fbc6 | 2101 | { |
f8ac0414 | 2102 | switch (ops->mode) { |
8593fbc6 TG |
2103 | |
2104 | case MTD_OOB_PLACE: | |
2105 | case MTD_OOB_RAW: | |
2106 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); | |
2107 | return oob + len; | |
2108 | ||
2109 | case MTD_OOB_AUTO: { | |
2110 | struct nand_oobfree *free = chip->ecc.layout->oobfree; | |
7bc3312b TG |
2111 | uint32_t boffs = 0, woffs = ops->ooboffs; |
2112 | size_t bytes = 0; | |
8593fbc6 | 2113 | |
f8ac0414 | 2114 | for (; free->length && len; free++, len -= bytes) { |
7bc3312b TG |
2115 | /* Write request not from offset 0 ? */ |
2116 | if (unlikely(woffs)) { | |
2117 | if (woffs >= free->length) { | |
2118 | woffs -= free->length; | |
2119 | continue; | |
2120 | } | |
2121 | boffs = free->offset + woffs; | |
2122 | bytes = min_t(size_t, len, | |
2123 | (free->length - woffs)); | |
2124 | woffs = 0; | |
2125 | } else { | |
2126 | bytes = min_t(size_t, len, free->length); | |
2127 | boffs = free->offset; | |
2128 | } | |
8b0036ee | 2129 | memcpy(chip->oob_poi + boffs, oob, bytes); |
8593fbc6 TG |
2130 | oob += bytes; |
2131 | } | |
2132 | return oob; | |
2133 | } | |
2134 | default: | |
2135 | BUG(); | |
2136 | } | |
2137 | return NULL; | |
2138 | } | |
2139 | ||
f8ac0414 | 2140 | #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) |
1da177e4 LT |
2141 | |
2142 | /** | |
8593fbc6 | 2143 | * nand_do_write_ops - [Internal] NAND write with ECC |
1da177e4 LT |
2144 | * @mtd: MTD device structure |
2145 | * @to: offset to write to | |
8593fbc6 | 2146 | * @ops: oob operations description structure |
1da177e4 LT |
2147 | * |
2148 | * NAND write with ECC | |
2149 | */ | |
8593fbc6 TG |
2150 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2151 | struct mtd_oob_ops *ops) | |
1da177e4 | 2152 | { |
29072b96 | 2153 | int chipnr, realpage, page, blockmask, column; |
ace4dfee | 2154 | struct nand_chip *chip = mtd->priv; |
8593fbc6 | 2155 | uint32_t writelen = ops->len; |
782ce79a ML |
2156 | |
2157 | uint32_t oobwritelen = ops->ooblen; | |
2158 | uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ? | |
2159 | mtd->oobavail : mtd->oobsize; | |
2160 | ||
8593fbc6 TG |
2161 | uint8_t *oob = ops->oobbuf; |
2162 | uint8_t *buf = ops->datbuf; | |
29072b96 | 2163 | int ret, subpage; |
1da177e4 | 2164 | |
8593fbc6 | 2165 | ops->retlen = 0; |
29072b96 TG |
2166 | if (!writelen) |
2167 | return 0; | |
1da177e4 | 2168 | |
61b03bd7 | 2169 | /* reject writes, which are not page aligned */ |
8593fbc6 | 2170 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
20d8e248 | 2171 | printk(KERN_NOTICE "%s: Attempt to write not " |
2172 | "page aligned data\n", __func__); | |
1da177e4 LT |
2173 | return -EINVAL; |
2174 | } | |
2175 | ||
29072b96 TG |
2176 | column = to & (mtd->writesize - 1); |
2177 | subpage = column || (writelen & (mtd->writesize - 1)); | |
2178 | ||
2179 | if (subpage && oob) | |
2180 | return -EINVAL; | |
1da177e4 | 2181 | |
6a930961 TG |
2182 | chipnr = (int)(to >> chip->chip_shift); |
2183 | chip->select_chip(mtd, chipnr); | |
2184 | ||
1da177e4 LT |
2185 | /* Check, if it is write protected */ |
2186 | if (nand_check_wp(mtd)) | |
8593fbc6 | 2187 | return -EIO; |
1da177e4 | 2188 | |
f75e5097 TG |
2189 | realpage = (int)(to >> chip->page_shift); |
2190 | page = realpage & chip->pagemask; | |
2191 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
2192 | ||
2193 | /* Invalidate the page cache, when we write to the cached page */ | |
2194 | if (to <= (chip->pagebuf << chip->page_shift) && | |
8593fbc6 | 2195 | (chip->pagebuf << chip->page_shift) < (to + ops->len)) |
ace4dfee | 2196 | chip->pagebuf = -1; |
61b03bd7 | 2197 | |
7dcdcbef DW |
2198 | /* If we're not given explicit OOB data, let it be 0xFF */ |
2199 | if (likely(!oob)) | |
2200 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
61b03bd7 | 2201 | |
782ce79a | 2202 | /* Don't allow multipage oob writes with offset */ |
cdcf12b2 | 2203 | if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) |
782ce79a ML |
2204 | return -EINVAL; |
2205 | ||
f8ac0414 | 2206 | while (1) { |
29072b96 | 2207 | int bytes = mtd->writesize; |
f75e5097 | 2208 | int cached = writelen > bytes && page != blockmask; |
29072b96 TG |
2209 | uint8_t *wbuf = buf; |
2210 | ||
2211 | /* Partial page write ? */ | |
2212 | if (unlikely(column || writelen < (mtd->writesize - 1))) { | |
2213 | cached = 0; | |
2214 | bytes = min_t(int, bytes - column, (int) writelen); | |
2215 | chip->pagebuf = -1; | |
2216 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2217 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2218 | wbuf = chip->buffers->databuf; | |
2219 | } | |
1da177e4 | 2220 | |
782ce79a ML |
2221 | if (unlikely(oob)) { |
2222 | size_t len = min(oobwritelen, oobmaxlen); | |
2223 | oob = nand_fill_oob(chip, oob, len, ops); | |
2224 | oobwritelen -= len; | |
2225 | } | |
8593fbc6 | 2226 | |
29072b96 | 2227 | ret = chip->write_page(mtd, chip, wbuf, page, cached, |
956e944c | 2228 | (ops->mode == MTD_OOB_RAW)); |
f75e5097 TG |
2229 | if (ret) |
2230 | break; | |
2231 | ||
2232 | writelen -= bytes; | |
2233 | if (!writelen) | |
2234 | break; | |
2235 | ||
29072b96 | 2236 | column = 0; |
f75e5097 TG |
2237 | buf += bytes; |
2238 | realpage++; | |
2239 | ||
2240 | page = realpage & chip->pagemask; | |
2241 | /* Check, if we cross a chip boundary */ | |
2242 | if (!page) { | |
2243 | chipnr++; | |
2244 | chip->select_chip(mtd, -1); | |
2245 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2246 | } |
2247 | } | |
8593fbc6 | 2248 | |
8593fbc6 | 2249 | ops->retlen = ops->len - writelen; |
7014568b VW |
2250 | if (unlikely(oob)) |
2251 | ops->oobretlen = ops->ooblen; | |
1da177e4 LT |
2252 | return ret; |
2253 | } | |
2254 | ||
2af7c653 SK |
2255 | /** |
2256 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
2257 | * @mtd: MTD device structure | |
2258 | * @to: offset to write to | |
2259 | * @len: number of bytes to write | |
2260 | * @retlen: pointer to variable to store the number of written bytes | |
2261 | * @buf: the data to write | |
2262 | * | |
2263 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2264 | * may for example be called by mtdoops when writing an oops while in panic. | |
2265 | */ | |
2266 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2267 | size_t *retlen, const uint8_t *buf) | |
2268 | { | |
2269 | struct nand_chip *chip = mtd->priv; | |
2270 | int ret; | |
2271 | ||
2272 | /* Do not allow reads past end of device */ | |
2273 | if ((to + len) > mtd->size) | |
2274 | return -EINVAL; | |
2275 | if (!len) | |
2276 | return 0; | |
2277 | ||
2278 | /* Wait for the device to get ready. */ | |
2279 | panic_nand_wait(mtd, chip, 400); | |
2280 | ||
2281 | /* Grab the device. */ | |
2282 | panic_nand_get_device(chip, mtd, FL_WRITING); | |
2283 | ||
2284 | chip->ops.len = len; | |
2285 | chip->ops.datbuf = (uint8_t *)buf; | |
2286 | chip->ops.oobbuf = NULL; | |
2287 | ||
2288 | ret = nand_do_write_ops(mtd, to, &chip->ops); | |
2289 | ||
2290 | *retlen = chip->ops.retlen; | |
2291 | return ret; | |
2292 | } | |
2293 | ||
f75e5097 | 2294 | /** |
8593fbc6 | 2295 | * nand_write - [MTD Interface] NAND write with ECC |
f75e5097 | 2296 | * @mtd: MTD device structure |
f75e5097 TG |
2297 | * @to: offset to write to |
2298 | * @len: number of bytes to write | |
8593fbc6 TG |
2299 | * @retlen: pointer to variable to store the number of written bytes |
2300 | * @buf: the data to write | |
f75e5097 | 2301 | * |
8593fbc6 | 2302 | * NAND write with ECC |
f75e5097 | 2303 | */ |
8593fbc6 TG |
2304 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
2305 | size_t *retlen, const uint8_t *buf) | |
f75e5097 TG |
2306 | { |
2307 | struct nand_chip *chip = mtd->priv; | |
f75e5097 TG |
2308 | int ret; |
2309 | ||
8593fbc6 TG |
2310 | /* Do not allow reads past end of device */ |
2311 | if ((to + len) > mtd->size) | |
f75e5097 | 2312 | return -EINVAL; |
8593fbc6 TG |
2313 | if (!len) |
2314 | return 0; | |
f75e5097 | 2315 | |
7bc3312b | 2316 | nand_get_device(chip, mtd, FL_WRITING); |
f75e5097 | 2317 | |
8593fbc6 TG |
2318 | chip->ops.len = len; |
2319 | chip->ops.datbuf = (uint8_t *)buf; | |
2320 | chip->ops.oobbuf = NULL; | |
f75e5097 | 2321 | |
8593fbc6 | 2322 | ret = nand_do_write_ops(mtd, to, &chip->ops); |
f75e5097 | 2323 | |
7fd5aecc RP |
2324 | *retlen = chip->ops.retlen; |
2325 | ||
f75e5097 | 2326 | nand_release_device(mtd); |
8593fbc6 | 2327 | |
8593fbc6 | 2328 | return ret; |
f75e5097 | 2329 | } |
7314e9e7 | 2330 | |
1da177e4 | 2331 | /** |
8593fbc6 | 2332 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
1da177e4 LT |
2333 | * @mtd: MTD device structure |
2334 | * @to: offset to write to | |
8593fbc6 | 2335 | * @ops: oob operation description structure |
1da177e4 LT |
2336 | * |
2337 | * NAND write out-of-band | |
2338 | */ | |
8593fbc6 TG |
2339 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
2340 | struct mtd_oob_ops *ops) | |
1da177e4 | 2341 | { |
03736155 | 2342 | int chipnr, page, status, len; |
ace4dfee | 2343 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2344 | |
20d8e248 | 2345 | DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n", |
2346 | __func__, (unsigned int)to, (int)ops->ooblen); | |
1da177e4 | 2347 | |
03736155 AH |
2348 | if (ops->mode == MTD_OOB_AUTO) |
2349 | len = chip->ecc.layout->oobavail; | |
2350 | else | |
2351 | len = mtd->oobsize; | |
2352 | ||
1da177e4 | 2353 | /* Do not allow write past end of page */ |
03736155 | 2354 | if ((ops->ooboffs + ops->ooblen) > len) { |
20d8e248 | 2355 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write " |
2356 | "past end of page\n", __func__); | |
1da177e4 LT |
2357 | return -EINVAL; |
2358 | } | |
2359 | ||
03736155 | 2360 | if (unlikely(ops->ooboffs >= len)) { |
20d8e248 | 2361 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start " |
2362 | "write outside oob\n", __func__); | |
03736155 AH |
2363 | return -EINVAL; |
2364 | } | |
2365 | ||
775adc3d | 2366 | /* Do not allow write past end of device */ |
03736155 AH |
2367 | if (unlikely(to >= mtd->size || |
2368 | ops->ooboffs + ops->ooblen > | |
2369 | ((mtd->size >> chip->page_shift) - | |
2370 | (to >> chip->page_shift)) * len)) { | |
20d8e248 | 2371 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond " |
2372 | "end of device\n", __func__); | |
03736155 AH |
2373 | return -EINVAL; |
2374 | } | |
2375 | ||
7314e9e7 | 2376 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 2377 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2378 | |
7314e9e7 TG |
2379 | /* Shift to get page */ |
2380 | page = (int)(to >> chip->page_shift); | |
2381 | ||
2382 | /* | |
2383 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
2384 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
2385 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
2386 | * it in the doc2000 driver in August 1999. dwmw2. | |
2387 | */ | |
ace4dfee | 2388 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
2389 | |
2390 | /* Check, if it is write protected */ | |
2391 | if (nand_check_wp(mtd)) | |
8593fbc6 | 2392 | return -EROFS; |
61b03bd7 | 2393 | |
1da177e4 | 2394 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
2395 | if (page == chip->pagebuf) |
2396 | chip->pagebuf = -1; | |
1da177e4 | 2397 | |
7bc3312b | 2398 | memset(chip->oob_poi, 0xff, mtd->oobsize); |
782ce79a | 2399 | nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops); |
7bc3312b TG |
2400 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); |
2401 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
1da177e4 | 2402 | |
7bc3312b TG |
2403 | if (status) |
2404 | return status; | |
1da177e4 | 2405 | |
7014568b | 2406 | ops->oobretlen = ops->ooblen; |
1da177e4 | 2407 | |
7bc3312b | 2408 | return 0; |
8593fbc6 TG |
2409 | } |
2410 | ||
2411 | /** | |
2412 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
2413 | * @mtd: MTD device structure | |
844d3b42 | 2414 | * @to: offset to write to |
8593fbc6 TG |
2415 | * @ops: oob operation description structure |
2416 | */ | |
2417 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
2418 | struct mtd_oob_ops *ops) | |
2419 | { | |
8593fbc6 TG |
2420 | struct nand_chip *chip = mtd->priv; |
2421 | int ret = -ENOTSUPP; | |
2422 | ||
2423 | ops->retlen = 0; | |
2424 | ||
2425 | /* Do not allow writes past end of device */ | |
7014568b | 2426 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
20d8e248 | 2427 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond " |
2428 | "end of device\n", __func__); | |
8593fbc6 TG |
2429 | return -EINVAL; |
2430 | } | |
2431 | ||
7bc3312b | 2432 | nand_get_device(chip, mtd, FL_WRITING); |
8593fbc6 | 2433 | |
f8ac0414 | 2434 | switch (ops->mode) { |
8593fbc6 TG |
2435 | case MTD_OOB_PLACE: |
2436 | case MTD_OOB_AUTO: | |
8593fbc6 | 2437 | case MTD_OOB_RAW: |
8593fbc6 TG |
2438 | break; |
2439 | ||
2440 | default: | |
2441 | goto out; | |
2442 | } | |
2443 | ||
2444 | if (!ops->datbuf) | |
2445 | ret = nand_do_write_oob(mtd, to, ops); | |
2446 | else | |
2447 | ret = nand_do_write_ops(mtd, to, ops); | |
2448 | ||
7351d3a5 | 2449 | out: |
1da177e4 | 2450 | nand_release_device(mtd); |
1da177e4 LT |
2451 | return ret; |
2452 | } | |
2453 | ||
1da177e4 LT |
2454 | /** |
2455 | * single_erease_cmd - [GENERIC] NAND standard block erase command function | |
2456 | * @mtd: MTD device structure | |
2457 | * @page: the page address of the block which will be erased | |
2458 | * | |
2459 | * Standard erase command for NAND chips | |
2460 | */ | |
e0c7d767 | 2461 | static void single_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2462 | { |
ace4dfee | 2463 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2464 | /* Send commands to erase a block */ |
ace4dfee TG |
2465 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2466 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2467 | } |
2468 | ||
2469 | /** | |
2470 | * multi_erease_cmd - [GENERIC] AND specific block erase command function | |
2471 | * @mtd: MTD device structure | |
2472 | * @page: the page address of the block which will be erased | |
2473 | * | |
2474 | * AND multi block erase command function | |
2475 | * Erase 4 consecutive blocks | |
2476 | */ | |
e0c7d767 | 2477 | static void multi_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2478 | { |
ace4dfee | 2479 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2480 | /* Send commands to erase a block */ |
ace4dfee TG |
2481 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); |
2482 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
2483 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
2484 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); | |
2485 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2486 | } |
2487 | ||
2488 | /** | |
2489 | * nand_erase - [MTD Interface] erase block(s) | |
2490 | * @mtd: MTD device structure | |
2491 | * @instr: erase instruction | |
2492 | * | |
2493 | * Erase one ore more blocks | |
2494 | */ | |
e0c7d767 | 2495 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 2496 | { |
e0c7d767 | 2497 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 2498 | } |
61b03bd7 | 2499 | |
30f464b7 | 2500 | #define BBT_PAGE_MASK 0xffffff3f |
1da177e4 | 2501 | /** |
ace4dfee | 2502 | * nand_erase_nand - [Internal] erase block(s) |
1da177e4 LT |
2503 | * @mtd: MTD device structure |
2504 | * @instr: erase instruction | |
2505 | * @allowbbt: allow erasing the bbt area | |
2506 | * | |
2507 | * Erase one ore more blocks | |
2508 | */ | |
ace4dfee TG |
2509 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
2510 | int allowbbt) | |
1da177e4 | 2511 | { |
69423d99 | 2512 | int page, status, pages_per_block, ret, chipnr; |
ace4dfee | 2513 | struct nand_chip *chip = mtd->priv; |
f8ac0414 | 2514 | loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0}; |
ace4dfee | 2515 | unsigned int bbt_masked_page = 0xffffffff; |
69423d99 | 2516 | loff_t len; |
1da177e4 | 2517 | |
20d8e248 | 2518 | DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n", |
2519 | __func__, (unsigned long long)instr->addr, | |
2520 | (unsigned long long)instr->len); | |
1da177e4 | 2521 | |
6fe5a6ac | 2522 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 2523 | return -EINVAL; |
1da177e4 | 2524 | |
bb0eb217 | 2525 | instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN; |
1da177e4 LT |
2526 | |
2527 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 2528 | nand_get_device(chip, mtd, FL_ERASING); |
1da177e4 LT |
2529 | |
2530 | /* Shift to get first page */ | |
ace4dfee TG |
2531 | page = (int)(instr->addr >> chip->page_shift); |
2532 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
2533 | |
2534 | /* Calculate pages in each block */ | |
ace4dfee | 2535 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
2536 | |
2537 | /* Select the NAND device */ | |
ace4dfee | 2538 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2539 | |
1da177e4 LT |
2540 | /* Check, if it is write protected */ |
2541 | if (nand_check_wp(mtd)) { | |
20d8e248 | 2542 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n", |
2543 | __func__); | |
1da177e4 LT |
2544 | instr->state = MTD_ERASE_FAILED; |
2545 | goto erase_exit; | |
2546 | } | |
2547 | ||
ace4dfee TG |
2548 | /* |
2549 | * If BBT requires refresh, set the BBT page mask to see if the BBT | |
2550 | * should be rewritten. Otherwise the mask is set to 0xffffffff which | |
2551 | * can not be matched. This is also done when the bbt is actually | |
2552 | * erased to avoid recusrsive updates | |
2553 | */ | |
2554 | if (chip->options & BBT_AUTO_REFRESH && !allowbbt) | |
2555 | bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK; | |
30f464b7 | 2556 | |
1da177e4 LT |
2557 | /* Loop through the pages */ |
2558 | len = instr->len; | |
2559 | ||
2560 | instr->state = MTD_ERASING; | |
2561 | ||
2562 | while (len) { | |
ace4dfee TG |
2563 | /* |
2564 | * heck if we have a bad block, we do not erase bad blocks ! | |
2565 | */ | |
2566 | if (nand_block_checkbad(mtd, ((loff_t) page) << | |
2567 | chip->page_shift, 0, allowbbt)) { | |
20d8e248 | 2568 | printk(KERN_WARNING "%s: attempt to erase a bad block " |
2569 | "at page 0x%08x\n", __func__, page); | |
1da177e4 LT |
2570 | instr->state = MTD_ERASE_FAILED; |
2571 | goto erase_exit; | |
2572 | } | |
61b03bd7 | 2573 | |
ace4dfee TG |
2574 | /* |
2575 | * Invalidate the page cache, if we erase the block which | |
2576 | * contains the current cached page | |
2577 | */ | |
2578 | if (page <= chip->pagebuf && chip->pagebuf < | |
2579 | (page + pages_per_block)) | |
2580 | chip->pagebuf = -1; | |
1da177e4 | 2581 | |
ace4dfee | 2582 | chip->erase_cmd(mtd, page & chip->pagemask); |
61b03bd7 | 2583 | |
7bc3312b | 2584 | status = chip->waitfunc(mtd, chip); |
1da177e4 | 2585 | |
ace4dfee TG |
2586 | /* |
2587 | * See if operation failed and additional status checks are | |
2588 | * available | |
2589 | */ | |
2590 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2591 | status = chip->errstat(mtd, chip, FL_ERASING, | |
2592 | status, page); | |
068e3c0a | 2593 | |
1da177e4 | 2594 | /* See if block erase succeeded */ |
a4ab4c5d | 2595 | if (status & NAND_STATUS_FAIL) { |
20d8e248 | 2596 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, " |
2597 | "page 0x%08x\n", __func__, page); | |
1da177e4 | 2598 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
2599 | instr->fail_addr = |
2600 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
2601 | goto erase_exit; |
2602 | } | |
30f464b7 | 2603 | |
ace4dfee TG |
2604 | /* |
2605 | * If BBT requires refresh, set the BBT rewrite flag to the | |
2606 | * page being erased | |
2607 | */ | |
2608 | if (bbt_masked_page != 0xffffffff && | |
2609 | (page & BBT_PAGE_MASK) == bbt_masked_page) | |
69423d99 AH |
2610 | rewrite_bbt[chipnr] = |
2611 | ((loff_t)page << chip->page_shift); | |
61b03bd7 | 2612 | |
1da177e4 | 2613 | /* Increment page address and decrement length */ |
ace4dfee | 2614 | len -= (1 << chip->phys_erase_shift); |
1da177e4 LT |
2615 | page += pages_per_block; |
2616 | ||
2617 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 2618 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 2619 | chipnr++; |
ace4dfee TG |
2620 | chip->select_chip(mtd, -1); |
2621 | chip->select_chip(mtd, chipnr); | |
30f464b7 | 2622 | |
ace4dfee TG |
2623 | /* |
2624 | * If BBT requires refresh and BBT-PERCHIP, set the BBT | |
2625 | * page mask to see if this BBT should be rewritten | |
2626 | */ | |
2627 | if (bbt_masked_page != 0xffffffff && | |
2628 | (chip->bbt_td->options & NAND_BBT_PERCHIP)) | |
2629 | bbt_masked_page = chip->bbt_td->pages[chipnr] & | |
2630 | BBT_PAGE_MASK; | |
1da177e4 LT |
2631 | } |
2632 | } | |
2633 | instr->state = MTD_ERASE_DONE; | |
2634 | ||
7351d3a5 | 2635 | erase_exit: |
1da177e4 LT |
2636 | |
2637 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
2638 | |
2639 | /* Deselect and wake up anyone waiting on the device */ | |
2640 | nand_release_device(mtd); | |
2641 | ||
49defc01 DW |
2642 | /* Do call back function */ |
2643 | if (!ret) | |
2644 | mtd_erase_callback(instr); | |
2645 | ||
ace4dfee TG |
2646 | /* |
2647 | * If BBT requires refresh and erase was successful, rewrite any | |
2648 | * selected bad block tables | |
2649 | */ | |
2650 | if (bbt_masked_page == 0xffffffff || ret) | |
2651 | return ret; | |
2652 | ||
2653 | for (chipnr = 0; chipnr < chip->numchips; chipnr++) { | |
2654 | if (!rewrite_bbt[chipnr]) | |
2655 | continue; | |
2656 | /* update the BBT for chip */ | |
20d8e248 | 2657 | DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt " |
2658 | "(%d:0x%0llx 0x%0x)\n", __func__, chipnr, | |
2659 | rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]); | |
ace4dfee | 2660 | nand_update_bbt(mtd, rewrite_bbt[chipnr]); |
30f464b7 DM |
2661 | } |
2662 | ||
1da177e4 LT |
2663 | /* Return more or less happy */ |
2664 | return ret; | |
2665 | } | |
2666 | ||
2667 | /** | |
2668 | * nand_sync - [MTD Interface] sync | |
2669 | * @mtd: MTD device structure | |
2670 | * | |
2671 | * Sync is actually a wait for chip ready function | |
2672 | */ | |
e0c7d767 | 2673 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 2674 | { |
ace4dfee | 2675 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2676 | |
20d8e248 | 2677 | DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__); |
1da177e4 LT |
2678 | |
2679 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 2680 | nand_get_device(chip, mtd, FL_SYNCING); |
1da177e4 | 2681 | /* Release it and go back */ |
e0c7d767 | 2682 | nand_release_device(mtd); |
1da177e4 LT |
2683 | } |
2684 | ||
1da177e4 | 2685 | /** |
ace4dfee | 2686 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
1da177e4 | 2687 | * @mtd: MTD device structure |
844d3b42 | 2688 | * @offs: offset relative to mtd start |
1da177e4 | 2689 | */ |
ace4dfee | 2690 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 LT |
2691 | { |
2692 | /* Check for invalid offset */ | |
ace4dfee | 2693 | if (offs > mtd->size) |
1da177e4 | 2694 | return -EINVAL; |
61b03bd7 | 2695 | |
ace4dfee | 2696 | return nand_block_checkbad(mtd, offs, 1, 0); |
1da177e4 LT |
2697 | } |
2698 | ||
2699 | /** | |
ace4dfee | 2700 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
1da177e4 LT |
2701 | * @mtd: MTD device structure |
2702 | * @ofs: offset relative to mtd start | |
2703 | */ | |
e0c7d767 | 2704 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 2705 | { |
ace4dfee | 2706 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
2707 | int ret; |
2708 | ||
f8ac0414 FF |
2709 | ret = nand_block_isbad(mtd, ofs); |
2710 | if (ret) { | |
e0c7d767 | 2711 | /* If it was bad already, return success and do nothing. */ |
1da177e4 LT |
2712 | if (ret > 0) |
2713 | return 0; | |
e0c7d767 DW |
2714 | return ret; |
2715 | } | |
1da177e4 | 2716 | |
ace4dfee | 2717 | return chip->block_markbad(mtd, ofs); |
1da177e4 LT |
2718 | } |
2719 | ||
962034f4 VW |
2720 | /** |
2721 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
2722 | * @mtd: MTD device structure | |
2723 | */ | |
2724 | static int nand_suspend(struct mtd_info *mtd) | |
2725 | { | |
ace4dfee | 2726 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2727 | |
ace4dfee | 2728 | return nand_get_device(chip, mtd, FL_PM_SUSPENDED); |
962034f4 VW |
2729 | } |
2730 | ||
2731 | /** | |
2732 | * nand_resume - [MTD Interface] Resume the NAND flash | |
2733 | * @mtd: MTD device structure | |
2734 | */ | |
2735 | static void nand_resume(struct mtd_info *mtd) | |
2736 | { | |
ace4dfee | 2737 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2738 | |
ace4dfee | 2739 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
2740 | nand_release_device(mtd); |
2741 | else | |
20d8e248 | 2742 | printk(KERN_ERR "%s called for a chip which is not " |
2743 | "in suspended state\n", __func__); | |
962034f4 VW |
2744 | } |
2745 | ||
7aa65bfd TG |
2746 | /* |
2747 | * Set default functions | |
2748 | */ | |
ace4dfee | 2749 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 2750 | { |
1da177e4 | 2751 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
2752 | if (!chip->chip_delay) |
2753 | chip->chip_delay = 20; | |
1da177e4 LT |
2754 | |
2755 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
2756 | if (chip->cmdfunc == NULL) |
2757 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
2758 | |
2759 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
2760 | if (chip->waitfunc == NULL) |
2761 | chip->waitfunc = nand_wait; | |
2762 | ||
2763 | if (!chip->select_chip) | |
2764 | chip->select_chip = nand_select_chip; | |
2765 | if (!chip->read_byte) | |
2766 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; | |
2767 | if (!chip->read_word) | |
2768 | chip->read_word = nand_read_word; | |
2769 | if (!chip->block_bad) | |
2770 | chip->block_bad = nand_block_bad; | |
2771 | if (!chip->block_markbad) | |
2772 | chip->block_markbad = nand_default_block_markbad; | |
2773 | if (!chip->write_buf) | |
2774 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; | |
2775 | if (!chip->read_buf) | |
2776 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; | |
2777 | if (!chip->verify_buf) | |
2778 | chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; | |
2779 | if (!chip->scan_bbt) | |
2780 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
2781 | |
2782 | if (!chip->controller) { | |
2783 | chip->controller = &chip->hwcontrol; | |
2784 | spin_lock_init(&chip->controller->lock); | |
2785 | init_waitqueue_head(&chip->controller->wq); | |
2786 | } | |
2787 | ||
7aa65bfd TG |
2788 | } |
2789 | ||
d1e1f4e4 FF |
2790 | /* |
2791 | * sanitize ONFI strings so we can safely print them | |
2792 | */ | |
2793 | static void sanitize_string(uint8_t *s, size_t len) | |
2794 | { | |
2795 | ssize_t i; | |
2796 | ||
2797 | /* null terminate */ | |
2798 | s[len - 1] = 0; | |
2799 | ||
2800 | /* remove non printable chars */ | |
2801 | for (i = 0; i < len - 1; i++) { | |
2802 | if (s[i] < ' ' || s[i] > 127) | |
2803 | s[i] = '?'; | |
2804 | } | |
2805 | ||
2806 | /* remove trailing spaces */ | |
2807 | strim(s); | |
2808 | } | |
2809 | ||
2810 | static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) | |
2811 | { | |
2812 | int i; | |
2813 | while (len--) { | |
2814 | crc ^= *p++ << 8; | |
2815 | for (i = 0; i < 8; i++) | |
2816 | crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); | |
2817 | } | |
2818 | ||
2819 | return crc; | |
2820 | } | |
2821 | ||
6fb277ba FF |
2822 | /* |
2823 | * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise | |
2824 | */ | |
2825 | static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, | |
2826 | int busw) | |
2827 | { | |
2828 | struct nand_onfi_params *p = &chip->onfi_params; | |
2829 | int i; | |
2830 | int val; | |
2831 | ||
2832 | /* try ONFI for unknow chip or LP */ | |
2833 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); | |
2834 | if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || | |
2835 | chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') | |
2836 | return 0; | |
2837 | ||
2838 | printk(KERN_INFO "ONFI flash detected\n"); | |
2839 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); | |
2840 | for (i = 0; i < 3; i++) { | |
2841 | chip->read_buf(mtd, (uint8_t *)p, sizeof(*p)); | |
2842 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == | |
2843 | le16_to_cpu(p->crc)) { | |
2844 | printk(KERN_INFO "ONFI param page %d valid\n", i); | |
2845 | break; | |
2846 | } | |
2847 | } | |
2848 | ||
2849 | if (i == 3) | |
2850 | return 0; | |
2851 | ||
2852 | /* check version */ | |
2853 | val = le16_to_cpu(p->revision); | |
b7b1a29d BN |
2854 | if (val & (1 << 5)) |
2855 | chip->onfi_version = 23; | |
2856 | else if (val & (1 << 4)) | |
6fb277ba FF |
2857 | chip->onfi_version = 22; |
2858 | else if (val & (1 << 3)) | |
2859 | chip->onfi_version = 21; | |
2860 | else if (val & (1 << 2)) | |
2861 | chip->onfi_version = 20; | |
b7b1a29d | 2862 | else if (val & (1 << 1)) |
6fb277ba | 2863 | chip->onfi_version = 10; |
b7b1a29d BN |
2864 | else |
2865 | chip->onfi_version = 0; | |
2866 | ||
2867 | if (!chip->onfi_version) { | |
2868 | printk(KERN_INFO "%s: unsupported ONFI version: %d\n", | |
2869 | __func__, val); | |
2870 | return 0; | |
2871 | } | |
6fb277ba FF |
2872 | |
2873 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
2874 | sanitize_string(p->model, sizeof(p->model)); | |
2875 | if (!mtd->name) | |
2876 | mtd->name = p->model; | |
2877 | mtd->writesize = le32_to_cpu(p->byte_per_page); | |
2878 | mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize; | |
2879 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); | |
4ccb3b44 | 2880 | chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize; |
6fb277ba FF |
2881 | busw = 0; |
2882 | if (le16_to_cpu(p->features) & 1) | |
2883 | busw = NAND_BUSWIDTH_16; | |
2884 | ||
2885 | chip->options &= ~NAND_CHIPOPTIONS_MSK; | |
2886 | chip->options |= (NAND_NO_READRDY | | |
2887 | NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK; | |
2888 | ||
2889 | return 1; | |
2890 | } | |
2891 | ||
7aa65bfd | 2892 | /* |
ace4dfee | 2893 | * Get the flash and manufacturer id and lookup if the type is supported |
7aa65bfd TG |
2894 | */ |
2895 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 2896 | struct nand_chip *chip, |
7351d3a5 FF |
2897 | int busw, |
2898 | int *maf_id, int *dev_id, | |
5e81e88a | 2899 | struct nand_flash_dev *type) |
7aa65bfd | 2900 | { |
d1e1f4e4 | 2901 | int i, maf_idx; |
426c457a | 2902 | u8 id_data[8]; |
6fb277ba | 2903 | int ret; |
1da177e4 LT |
2904 | |
2905 | /* Select the device */ | |
ace4dfee | 2906 | chip->select_chip(mtd, 0); |
1da177e4 | 2907 | |
ef89a880 KB |
2908 | /* |
2909 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
2910 | * after power-up | |
2911 | */ | |
2912 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
2913 | ||
1da177e4 | 2914 | /* Send the command for reading device ID */ |
ace4dfee | 2915 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
2916 | |
2917 | /* Read manufacturer and device IDs */ | |
ace4dfee | 2918 | *maf_id = chip->read_byte(mtd); |
d1e1f4e4 | 2919 | *dev_id = chip->read_byte(mtd); |
1da177e4 | 2920 | |
ed8165c7 BD |
2921 | /* Try again to make sure, as some systems the bus-hold or other |
2922 | * interface concerns can cause random data which looks like a | |
2923 | * possibly credible NAND flash to appear. If the two results do | |
2924 | * not match, ignore the device completely. | |
2925 | */ | |
2926 | ||
2927 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
2928 | ||
d1e1f4e4 | 2929 | for (i = 0; i < 2; i++) |
426c457a | 2930 | id_data[i] = chip->read_byte(mtd); |
ed8165c7 | 2931 | |
d1e1f4e4 | 2932 | if (id_data[0] != *maf_id || id_data[1] != *dev_id) { |
ed8165c7 BD |
2933 | printk(KERN_INFO "%s: second ID read did not match " |
2934 | "%02x,%02x against %02x,%02x\n", __func__, | |
d1e1f4e4 | 2935 | *maf_id, *dev_id, id_data[0], id_data[1]); |
ed8165c7 BD |
2936 | return ERR_PTR(-ENODEV); |
2937 | } | |
2938 | ||
7aa65bfd | 2939 | if (!type) |
5e81e88a DW |
2940 | type = nand_flash_ids; |
2941 | ||
2942 | for (; type->name != NULL; type++) | |
d1e1f4e4 | 2943 | if (*dev_id == type->id) |
f8ac0414 | 2944 | break; |
5e81e88a | 2945 | |
d1e1f4e4 FF |
2946 | chip->onfi_version = 0; |
2947 | if (!type->name || !type->pagesize) { | |
6fb277ba FF |
2948 | /* Check is chip is ONFI compliant */ |
2949 | ret = nand_flash_detect_onfi(mtd, chip, busw); | |
2950 | if (ret) | |
2951 | goto ident_done; | |
d1e1f4e4 FF |
2952 | } |
2953 | ||
2954 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
2955 | ||
2956 | /* Read entire ID string */ | |
2957 | ||
2958 | for (i = 0; i < 8; i++) | |
2959 | id_data[i] = chip->read_byte(mtd); | |
2960 | ||
5e81e88a | 2961 | if (!type->name) |
7aa65bfd TG |
2962 | return ERR_PTR(-ENODEV); |
2963 | ||
ba0251fe TG |
2964 | if (!mtd->name) |
2965 | mtd->name = type->name; | |
2966 | ||
69423d99 | 2967 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd | 2968 | |
12a40a57 HS |
2969 | if (!type->pagesize && chip->init_size) { |
2970 | /* set the pagesize, oobsize, erasesize by the driver*/ | |
2971 | busw = chip->init_size(mtd, chip, id_data); | |
2972 | } else if (!type->pagesize) { | |
7aa65bfd | 2973 | int extid; |
29072b96 | 2974 | /* The 3rd id byte holds MLC / multichip data */ |
426c457a | 2975 | chip->cellinfo = id_data[2]; |
7aa65bfd | 2976 | /* The 4th id byte is the important one */ |
426c457a | 2977 | extid = id_data[3]; |
61b03bd7 | 2978 | |
426c457a KC |
2979 | /* |
2980 | * Field definitions are in the following datasheets: | |
2981 | * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) | |
34c5bf6c | 2982 | * New style (6 byte ID): Samsung K9GBG08U0M (p.40) |
426c457a KC |
2983 | * |
2984 | * Check for wraparound + Samsung ID + nonzero 6th byte | |
2985 | * to decide what to do. | |
2986 | */ | |
2987 | if (id_data[0] == id_data[6] && id_data[1] == id_data[7] && | |
2988 | id_data[0] == NAND_MFR_SAMSUNG && | |
cfe3fdad | 2989 | (chip->cellinfo & NAND_CI_CELLTYPE_MSK) && |
426c457a KC |
2990 | id_data[5] != 0x00) { |
2991 | /* Calc pagesize */ | |
2992 | mtd->writesize = 2048 << (extid & 0x03); | |
2993 | extid >>= 2; | |
2994 | /* Calc oobsize */ | |
34c5bf6c BN |
2995 | switch (extid & 0x03) { |
2996 | case 1: | |
2997 | mtd->oobsize = 128; | |
2998 | break; | |
2999 | case 2: | |
3000 | mtd->oobsize = 218; | |
3001 | break; | |
3002 | case 3: | |
3003 | mtd->oobsize = 400; | |
3004 | break; | |
3005 | default: | |
3006 | mtd->oobsize = 436; | |
3007 | break; | |
3008 | } | |
426c457a KC |
3009 | extid >>= 2; |
3010 | /* Calc blocksize */ | |
3011 | mtd->erasesize = (128 * 1024) << | |
3012 | (((extid >> 1) & 0x04) | (extid & 0x03)); | |
3013 | busw = 0; | |
3014 | } else { | |
3015 | /* Calc pagesize */ | |
3016 | mtd->writesize = 1024 << (extid & 0x03); | |
3017 | extid >>= 2; | |
3018 | /* Calc oobsize */ | |
3019 | mtd->oobsize = (8 << (extid & 0x01)) * | |
3020 | (mtd->writesize >> 9); | |
3021 | extid >>= 2; | |
3022 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
3023 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
3024 | extid >>= 2; | |
3025 | /* Get buswidth information */ | |
3026 | busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
3027 | } | |
7aa65bfd TG |
3028 | } else { |
3029 | /* | |
ace4dfee | 3030 | * Old devices have chip data hardcoded in the device id table |
7aa65bfd | 3031 | */ |
ba0251fe TG |
3032 | mtd->erasesize = type->erasesize; |
3033 | mtd->writesize = type->pagesize; | |
4cbb9b80 | 3034 | mtd->oobsize = mtd->writesize / 32; |
ba0251fe | 3035 | busw = type->options & NAND_BUSWIDTH_16; |
2173bae8 BN |
3036 | |
3037 | /* | |
3038 | * Check for Spansion/AMD ID + repeating 5th, 6th byte since | |
3039 | * some Spansion chips have erasesize that conflicts with size | |
3040 | * listed in nand_ids table | |
3041 | * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) | |
3042 | */ | |
3043 | if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && | |
3044 | id_data[5] == 0x00 && id_data[6] == 0x00 && | |
3045 | id_data[7] == 0x00 && mtd->writesize == 512) { | |
3046 | mtd->erasesize = 128 * 1024; | |
3047 | mtd->erasesize <<= ((id_data[3] & 0x03) << 1); | |
3048 | } | |
7aa65bfd | 3049 | } |
d1e1f4e4 FF |
3050 | /* Get chip options, preserve non chip based options */ |
3051 | chip->options &= ~NAND_CHIPOPTIONS_MSK; | |
3052 | chip->options |= type->options & NAND_CHIPOPTIONS_MSK; | |
3053 | ||
3054 | /* Check if chip is a not a samsung device. Do not clear the | |
3055 | * options for chips which are not having an extended id. | |
3056 | */ | |
3057 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) | |
3058 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; | |
3059 | ident_done: | |
3060 | ||
3061 | /* | |
3062 | * Set chip as a default. Board drivers can override it, if necessary | |
3063 | */ | |
3064 | chip->options |= NAND_NO_AUTOINCR; | |
1da177e4 | 3065 | |
7aa65bfd | 3066 | /* Try to identify manufacturer */ |
9a909867 | 3067 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
7aa65bfd TG |
3068 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
3069 | break; | |
3070 | } | |
0ea4a755 | 3071 | |
7aa65bfd TG |
3072 | /* |
3073 | * Check, if buswidth is correct. Hardware drivers should set | |
ace4dfee | 3074 | * chip correct ! |
7aa65bfd | 3075 | */ |
ace4dfee | 3076 | if (busw != (chip->options & NAND_BUSWIDTH_16)) { |
7aa65bfd TG |
3077 | printk(KERN_INFO "NAND device: Manufacturer ID:" |
3078 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, | |
d1e1f4e4 | 3079 | *dev_id, nand_manuf_ids[maf_idx].name, mtd->name); |
7aa65bfd | 3080 | printk(KERN_WARNING "NAND bus width %d instead %d bit\n", |
ace4dfee | 3081 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
7aa65bfd TG |
3082 | busw ? 16 : 8); |
3083 | return ERR_PTR(-EINVAL); | |
3084 | } | |
61b03bd7 | 3085 | |
7aa65bfd | 3086 | /* Calculate the address shift from the page size */ |
ace4dfee | 3087 | chip->page_shift = ffs(mtd->writesize) - 1; |
7aa65bfd | 3088 | /* Convert chipsize to number of pages per chip -1. */ |
ace4dfee | 3089 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 3090 | |
ace4dfee | 3091 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 3092 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
3093 | if (chip->chipsize & 0xffffffff) |
3094 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
7351d3a5 FF |
3095 | else { |
3096 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); | |
3097 | chip->chip_shift += 32 - 1; | |
3098 | } | |
1da177e4 | 3099 | |
26d9be11 AB |
3100 | chip->badblockbits = 8; |
3101 | ||
7aa65bfd | 3102 | /* Set the bad block position */ |
065a1ed8 | 3103 | if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16)) |
c7b28e25 | 3104 | chip->badblockpos = NAND_LARGE_BADBLOCK_POS; |
065a1ed8 BN |
3105 | else |
3106 | chip->badblockpos = NAND_SMALL_BADBLOCK_POS; | |
61b03bd7 | 3107 | |
b60b08b0 KC |
3108 | /* |
3109 | * Bad block marker is stored in the last page of each block | |
c7b28e25 BN |
3110 | * on Samsung and Hynix MLC devices; stored in first two pages |
3111 | * of each block on Micron devices with 2KiB pages and on | |
13ed7aed BN |
3112 | * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan |
3113 | * only the first page. | |
b60b08b0 KC |
3114 | */ |
3115 | if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) && | |
3116 | (*maf_id == NAND_MFR_SAMSUNG || | |
3117 | *maf_id == NAND_MFR_HYNIX)) | |
5fb1549d | 3118 | chip->bbt_options |= NAND_BBT_SCANLASTPAGE; |
c7b28e25 BN |
3119 | else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) && |
3120 | (*maf_id == NAND_MFR_SAMSUNG || | |
3121 | *maf_id == NAND_MFR_HYNIX || | |
13ed7aed | 3122 | *maf_id == NAND_MFR_TOSHIBA || |
c7b28e25 BN |
3123 | *maf_id == NAND_MFR_AMD)) || |
3124 | (mtd->writesize == 2048 && | |
3125 | *maf_id == NAND_MFR_MICRON)) | |
5fb1549d | 3126 | chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; |
c7b28e25 | 3127 | |
7aa65bfd | 3128 | /* Check for AND chips with 4 page planes */ |
ace4dfee TG |
3129 | if (chip->options & NAND_4PAGE_ARRAY) |
3130 | chip->erase_cmd = multi_erase_cmd; | |
7aa65bfd | 3131 | else |
ace4dfee | 3132 | chip->erase_cmd = single_erase_cmd; |
7aa65bfd TG |
3133 | |
3134 | /* Do not replace user supplied command function ! */ | |
ace4dfee TG |
3135 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
3136 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd TG |
3137 | |
3138 | printk(KERN_INFO "NAND device: Manufacturer ID:" | |
d1e1f4e4 FF |
3139 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id, |
3140 | nand_manuf_ids[maf_idx].name, | |
0b524fb9 | 3141 | chip->onfi_version ? chip->onfi_params.model : type->name); |
7aa65bfd TG |
3142 | |
3143 | return type; | |
3144 | } | |
3145 | ||
7aa65bfd | 3146 | /** |
3b85c321 DW |
3147 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
3148 | * @mtd: MTD device structure | |
3149 | * @maxchips: Number of chips to scan for | |
5e81e88a | 3150 | * @table: Alternative NAND ID table |
7aa65bfd | 3151 | * |
3b85c321 DW |
3152 | * This is the first phase of the normal nand_scan() function. It |
3153 | * reads the flash ID and sets up MTD fields accordingly. | |
7aa65bfd | 3154 | * |
3b85c321 | 3155 | * The mtd->owner field must be set to the module of the caller. |
7aa65bfd | 3156 | */ |
5e81e88a DW |
3157 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
3158 | struct nand_flash_dev *table) | |
7aa65bfd | 3159 | { |
d1e1f4e4 | 3160 | int i, busw, nand_maf_id, nand_dev_id; |
ace4dfee | 3161 | struct nand_chip *chip = mtd->priv; |
7aa65bfd TG |
3162 | struct nand_flash_dev *type; |
3163 | ||
7aa65bfd | 3164 | /* Get buswidth to select the correct functions */ |
ace4dfee | 3165 | busw = chip->options & NAND_BUSWIDTH_16; |
7aa65bfd | 3166 | /* Set the default functions */ |
ace4dfee | 3167 | nand_set_defaults(chip, busw); |
7aa65bfd TG |
3168 | |
3169 | /* Read the flash type */ | |
7351d3a5 FF |
3170 | type = nand_get_flash_type(mtd, chip, busw, |
3171 | &nand_maf_id, &nand_dev_id, table); | |
7aa65bfd TG |
3172 | |
3173 | if (IS_ERR(type)) { | |
b1c6e6db BD |
3174 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
3175 | printk(KERN_WARNING "No NAND device found.\n"); | |
ace4dfee | 3176 | chip->select_chip(mtd, -1); |
7aa65bfd | 3177 | return PTR_ERR(type); |
1da177e4 LT |
3178 | } |
3179 | ||
7aa65bfd | 3180 | /* Check for a chip array */ |
e0c7d767 | 3181 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 3182 | chip->select_chip(mtd, i); |
ef89a880 KB |
3183 | /* See comment in nand_get_flash_type for reset */ |
3184 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1da177e4 | 3185 | /* Send the command for reading device ID */ |
ace4dfee | 3186 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 3187 | /* Read manufacturer and device IDs */ |
ace4dfee | 3188 | if (nand_maf_id != chip->read_byte(mtd) || |
d1e1f4e4 | 3189 | nand_dev_id != chip->read_byte(mtd)) |
1da177e4 LT |
3190 | break; |
3191 | } | |
3192 | if (i > 1) | |
3193 | printk(KERN_INFO "%d NAND chips detected\n", i); | |
61b03bd7 | 3194 | |
1da177e4 | 3195 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
3196 | chip->numchips = i; |
3197 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 3198 | |
3b85c321 DW |
3199 | return 0; |
3200 | } | |
7351d3a5 | 3201 | EXPORT_SYMBOL(nand_scan_ident); |
3b85c321 DW |
3202 | |
3203 | ||
3204 | /** | |
3205 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
3206 | * @mtd: MTD device structure | |
3b85c321 DW |
3207 | * |
3208 | * This is the second phase of the normal nand_scan() function. It | |
3209 | * fills out all the uninitialized function pointers with the defaults | |
3210 | * and scans for a bad block table if appropriate. | |
3211 | */ | |
3212 | int nand_scan_tail(struct mtd_info *mtd) | |
3213 | { | |
3214 | int i; | |
3215 | struct nand_chip *chip = mtd->priv; | |
3216 | ||
4bf63fcb DW |
3217 | if (!(chip->options & NAND_OWN_BUFFERS)) |
3218 | chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); | |
3219 | if (!chip->buffers) | |
3220 | return -ENOMEM; | |
3221 | ||
7dcdcbef | 3222 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 3223 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 3224 | |
7aa65bfd TG |
3225 | /* |
3226 | * If no default placement scheme is given, select an appropriate one | |
3227 | */ | |
193bd400 | 3228 | if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) { |
61b03bd7 | 3229 | switch (mtd->oobsize) { |
1da177e4 | 3230 | case 8: |
5bd34c09 | 3231 | chip->ecc.layout = &nand_oob_8; |
1da177e4 LT |
3232 | break; |
3233 | case 16: | |
5bd34c09 | 3234 | chip->ecc.layout = &nand_oob_16; |
1da177e4 LT |
3235 | break; |
3236 | case 64: | |
5bd34c09 | 3237 | chip->ecc.layout = &nand_oob_64; |
1da177e4 | 3238 | break; |
81ec5364 TG |
3239 | case 128: |
3240 | chip->ecc.layout = &nand_oob_128; | |
3241 | break; | |
1da177e4 | 3242 | default: |
7aa65bfd TG |
3243 | printk(KERN_WARNING "No oob scheme defined for " |
3244 | "oobsize %d\n", mtd->oobsize); | |
1da177e4 LT |
3245 | BUG(); |
3246 | } | |
3247 | } | |
61b03bd7 | 3248 | |
956e944c DW |
3249 | if (!chip->write_page) |
3250 | chip->write_page = nand_write_page; | |
3251 | ||
61b03bd7 | 3252 | /* |
7aa65bfd TG |
3253 | * check ECC mode, default to software if 3byte/512byte hardware ECC is |
3254 | * selected and we have 256 byte pagesize fallback to software ECC | |
e0c7d767 | 3255 | */ |
956e944c | 3256 | |
ace4dfee | 3257 | switch (chip->ecc.mode) { |
6e0cb135 SN |
3258 | case NAND_ECC_HW_OOB_FIRST: |
3259 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
3260 | if (!chip->ecc.calculate || !chip->ecc.correct || | |
3261 | !chip->ecc.hwctl) { | |
3262 | printk(KERN_WARNING "No ECC functions supplied; " | |
3263 | "Hardware ECC not possible\n"); | |
3264 | BUG(); | |
3265 | } | |
3266 | if (!chip->ecc.read_page) | |
3267 | chip->ecc.read_page = nand_read_page_hwecc_oob_first; | |
3268 | ||
6dfc6d25 | 3269 | case NAND_ECC_HW: |
f5bbdacc TG |
3270 | /* Use standard hwecc read page function ? */ |
3271 | if (!chip->ecc.read_page) | |
3272 | chip->ecc.read_page = nand_read_page_hwecc; | |
f75e5097 TG |
3273 | if (!chip->ecc.write_page) |
3274 | chip->ecc.write_page = nand_write_page_hwecc; | |
52ff49df DB |
3275 | if (!chip->ecc.read_page_raw) |
3276 | chip->ecc.read_page_raw = nand_read_page_raw; | |
3277 | if (!chip->ecc.write_page_raw) | |
3278 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b TG |
3279 | if (!chip->ecc.read_oob) |
3280 | chip->ecc.read_oob = nand_read_oob_std; | |
3281 | if (!chip->ecc.write_oob) | |
3282 | chip->ecc.write_oob = nand_write_oob_std; | |
f5bbdacc | 3283 | |
6dfc6d25 | 3284 | case NAND_ECC_HW_SYNDROME: |
78b65179 SW |
3285 | if ((!chip->ecc.calculate || !chip->ecc.correct || |
3286 | !chip->ecc.hwctl) && | |
3287 | (!chip->ecc.read_page || | |
1c45f604 | 3288 | chip->ecc.read_page == nand_read_page_hwecc || |
78b65179 | 3289 | !chip->ecc.write_page || |
1c45f604 | 3290 | chip->ecc.write_page == nand_write_page_hwecc)) { |
6e0cb135 | 3291 | printk(KERN_WARNING "No ECC functions supplied; " |
6dfc6d25 TG |
3292 | "Hardware ECC not possible\n"); |
3293 | BUG(); | |
3294 | } | |
f75e5097 | 3295 | /* Use standard syndrome read/write page function ? */ |
f5bbdacc TG |
3296 | if (!chip->ecc.read_page) |
3297 | chip->ecc.read_page = nand_read_page_syndrome; | |
f75e5097 TG |
3298 | if (!chip->ecc.write_page) |
3299 | chip->ecc.write_page = nand_write_page_syndrome; | |
52ff49df DB |
3300 | if (!chip->ecc.read_page_raw) |
3301 | chip->ecc.read_page_raw = nand_read_page_raw_syndrome; | |
3302 | if (!chip->ecc.write_page_raw) | |
3303 | chip->ecc.write_page_raw = nand_write_page_raw_syndrome; | |
7bc3312b TG |
3304 | if (!chip->ecc.read_oob) |
3305 | chip->ecc.read_oob = nand_read_oob_syndrome; | |
3306 | if (!chip->ecc.write_oob) | |
3307 | chip->ecc.write_oob = nand_write_oob_syndrome; | |
f5bbdacc | 3308 | |
ace4dfee | 3309 | if (mtd->writesize >= chip->ecc.size) |
6dfc6d25 TG |
3310 | break; |
3311 | printk(KERN_WARNING "%d byte HW ECC not possible on " | |
3312 | "%d byte page size, fallback to SW ECC\n", | |
ace4dfee TG |
3313 | chip->ecc.size, mtd->writesize); |
3314 | chip->ecc.mode = NAND_ECC_SOFT; | |
61b03bd7 | 3315 | |
6dfc6d25 | 3316 | case NAND_ECC_SOFT: |
ace4dfee TG |
3317 | chip->ecc.calculate = nand_calculate_ecc; |
3318 | chip->ecc.correct = nand_correct_data; | |
f5bbdacc | 3319 | chip->ecc.read_page = nand_read_page_swecc; |
3d459559 | 3320 | chip->ecc.read_subpage = nand_read_subpage; |
f75e5097 | 3321 | chip->ecc.write_page = nand_write_page_swecc; |
52ff49df DB |
3322 | chip->ecc.read_page_raw = nand_read_page_raw; |
3323 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b TG |
3324 | chip->ecc.read_oob = nand_read_oob_std; |
3325 | chip->ecc.write_oob = nand_write_oob_std; | |
9a73290d SV |
3326 | if (!chip->ecc.size) |
3327 | chip->ecc.size = 256; | |
ace4dfee | 3328 | chip->ecc.bytes = 3; |
1da177e4 | 3329 | break; |
61b03bd7 | 3330 | |
193bd400 ID |
3331 | case NAND_ECC_SOFT_BCH: |
3332 | if (!mtd_nand_has_bch()) { | |
3333 | printk(KERN_WARNING "CONFIG_MTD_ECC_BCH not enabled\n"); | |
3334 | BUG(); | |
3335 | } | |
3336 | chip->ecc.calculate = nand_bch_calculate_ecc; | |
3337 | chip->ecc.correct = nand_bch_correct_data; | |
3338 | chip->ecc.read_page = nand_read_page_swecc; | |
3339 | chip->ecc.read_subpage = nand_read_subpage; | |
3340 | chip->ecc.write_page = nand_write_page_swecc; | |
3341 | chip->ecc.read_page_raw = nand_read_page_raw; | |
3342 | chip->ecc.write_page_raw = nand_write_page_raw; | |
3343 | chip->ecc.read_oob = nand_read_oob_std; | |
3344 | chip->ecc.write_oob = nand_write_oob_std; | |
3345 | /* | |
3346 | * Board driver should supply ecc.size and ecc.bytes values to | |
3347 | * select how many bits are correctable; see nand_bch_init() | |
3348 | * for details. | |
3349 | * Otherwise, default to 4 bits for large page devices | |
3350 | */ | |
3351 | if (!chip->ecc.size && (mtd->oobsize >= 64)) { | |
3352 | chip->ecc.size = 512; | |
3353 | chip->ecc.bytes = 7; | |
3354 | } | |
3355 | chip->ecc.priv = nand_bch_init(mtd, | |
3356 | chip->ecc.size, | |
3357 | chip->ecc.bytes, | |
3358 | &chip->ecc.layout); | |
3359 | if (!chip->ecc.priv) { | |
3360 | printk(KERN_WARNING "BCH ECC initialization failed!\n"); | |
3361 | BUG(); | |
3362 | } | |
3363 | break; | |
3364 | ||
61b03bd7 | 3365 | case NAND_ECC_NONE: |
7aa65bfd TG |
3366 | printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. " |
3367 | "This is not recommended !!\n"); | |
8593fbc6 TG |
3368 | chip->ecc.read_page = nand_read_page_raw; |
3369 | chip->ecc.write_page = nand_write_page_raw; | |
7bc3312b | 3370 | chip->ecc.read_oob = nand_read_oob_std; |
52ff49df DB |
3371 | chip->ecc.read_page_raw = nand_read_page_raw; |
3372 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b | 3373 | chip->ecc.write_oob = nand_write_oob_std; |
ace4dfee TG |
3374 | chip->ecc.size = mtd->writesize; |
3375 | chip->ecc.bytes = 0; | |
1da177e4 | 3376 | break; |
956e944c | 3377 | |
1da177e4 | 3378 | default: |
7aa65bfd | 3379 | printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n", |
ace4dfee | 3380 | chip->ecc.mode); |
61b03bd7 | 3381 | BUG(); |
1da177e4 | 3382 | } |
61b03bd7 | 3383 | |
5bd34c09 TG |
3384 | /* |
3385 | * The number of bytes available for a client to place data into | |
3386 | * the out of band area | |
3387 | */ | |
3388 | chip->ecc.layout->oobavail = 0; | |
81d19b04 DB |
3389 | for (i = 0; chip->ecc.layout->oobfree[i].length |
3390 | && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++) | |
5bd34c09 TG |
3391 | chip->ecc.layout->oobavail += |
3392 | chip->ecc.layout->oobfree[i].length; | |
1f92267c | 3393 | mtd->oobavail = chip->ecc.layout->oobavail; |
5bd34c09 | 3394 | |
7aa65bfd TG |
3395 | /* |
3396 | * Set the number of read / write steps for one page depending on ECC | |
3397 | * mode | |
3398 | */ | |
ace4dfee | 3399 | chip->ecc.steps = mtd->writesize / chip->ecc.size; |
f8ac0414 | 3400 | if (chip->ecc.steps * chip->ecc.size != mtd->writesize) { |
6dfc6d25 TG |
3401 | printk(KERN_WARNING "Invalid ecc parameters\n"); |
3402 | BUG(); | |
1da177e4 | 3403 | } |
f5bbdacc | 3404 | chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; |
61b03bd7 | 3405 | |
29072b96 TG |
3406 | /* |
3407 | * Allow subpage writes up to ecc.steps. Not possible for MLC | |
3408 | * FLASH. | |
3409 | */ | |
3410 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && | |
3411 | !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { | |
f8ac0414 | 3412 | switch (chip->ecc.steps) { |
29072b96 TG |
3413 | case 2: |
3414 | mtd->subpage_sft = 1; | |
3415 | break; | |
3416 | case 4: | |
3417 | case 8: | |
81ec5364 | 3418 | case 16: |
29072b96 TG |
3419 | mtd->subpage_sft = 2; |
3420 | break; | |
3421 | } | |
3422 | } | |
3423 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
3424 | ||
04bbd0ea | 3425 | /* Initialize state */ |
ace4dfee | 3426 | chip->state = FL_READY; |
1da177e4 LT |
3427 | |
3428 | /* De-select the device */ | |
ace4dfee | 3429 | chip->select_chip(mtd, -1); |
1da177e4 LT |
3430 | |
3431 | /* Invalidate the pagebuffer reference */ | |
ace4dfee | 3432 | chip->pagebuf = -1; |
1da177e4 LT |
3433 | |
3434 | /* Fill in remaining MTD driver data */ | |
3435 | mtd->type = MTD_NANDFLASH; | |
93edbad6 ML |
3436 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
3437 | MTD_CAP_NANDFLASH; | |
1da177e4 LT |
3438 | mtd->erase = nand_erase; |
3439 | mtd->point = NULL; | |
3440 | mtd->unpoint = NULL; | |
3441 | mtd->read = nand_read; | |
3442 | mtd->write = nand_write; | |
2af7c653 | 3443 | mtd->panic_write = panic_nand_write; |
1da177e4 LT |
3444 | mtd->read_oob = nand_read_oob; |
3445 | mtd->write_oob = nand_write_oob; | |
1da177e4 LT |
3446 | mtd->sync = nand_sync; |
3447 | mtd->lock = NULL; | |
3448 | mtd->unlock = NULL; | |
962034f4 VW |
3449 | mtd->suspend = nand_suspend; |
3450 | mtd->resume = nand_resume; | |
1da177e4 LT |
3451 | mtd->block_isbad = nand_block_isbad; |
3452 | mtd->block_markbad = nand_block_markbad; | |
cbcab65a | 3453 | mtd->writebufsize = mtd->writesize; |
1da177e4 | 3454 | |
5bd34c09 TG |
3455 | /* propagate ecc.layout to mtd_info */ |
3456 | mtd->ecclayout = chip->ecc.layout; | |
1da177e4 | 3457 | |
0040bf38 | 3458 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 3459 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 3460 | return 0; |
1da177e4 LT |
3461 | |
3462 | /* Build bad block table */ | |
ace4dfee | 3463 | return chip->scan_bbt(mtd); |
1da177e4 | 3464 | } |
7351d3a5 | 3465 | EXPORT_SYMBOL(nand_scan_tail); |
1da177e4 | 3466 | |
a6e6abd5 | 3467 | /* is_module_text_address() isn't exported, and it's mostly a pointless |
7351d3a5 FF |
3468 | * test if this is a module _anyway_ -- they'd have to try _really_ hard |
3469 | * to call us from in-kernel code if the core NAND support is modular. */ | |
3b85c321 DW |
3470 | #ifdef MODULE |
3471 | #define caller_is_module() (1) | |
3472 | #else | |
3473 | #define caller_is_module() \ | |
a6e6abd5 | 3474 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
3475 | #endif |
3476 | ||
3477 | /** | |
3478 | * nand_scan - [NAND Interface] Scan for the NAND device | |
3479 | * @mtd: MTD device structure | |
3480 | * @maxchips: Number of chips to scan for | |
3481 | * | |
3482 | * This fills out all the uninitialized function pointers | |
3483 | * with the defaults. | |
3484 | * The flash ID is read and the mtd/chip structures are | |
3485 | * filled with the appropriate values. | |
3486 | * The mtd->owner field must be set to the module of the caller | |
3487 | * | |
3488 | */ | |
3489 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
3490 | { | |
3491 | int ret; | |
3492 | ||
3493 | /* Many callers got this wrong, so check for it for a while... */ | |
3494 | if (!mtd->owner && caller_is_module()) { | |
20d8e248 | 3495 | printk(KERN_CRIT "%s called with NULL mtd->owner!\n", |
3496 | __func__); | |
3b85c321 DW |
3497 | BUG(); |
3498 | } | |
3499 | ||
5e81e88a | 3500 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
3501 | if (!ret) |
3502 | ret = nand_scan_tail(mtd); | |
3503 | return ret; | |
3504 | } | |
7351d3a5 | 3505 | EXPORT_SYMBOL(nand_scan); |
3b85c321 | 3506 | |
1da177e4 | 3507 | /** |
61b03bd7 | 3508 | * nand_release - [NAND Interface] Free resources held by the NAND device |
1da177e4 LT |
3509 | * @mtd: MTD device structure |
3510 | */ | |
e0c7d767 | 3511 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 3512 | { |
ace4dfee | 3513 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 3514 | |
193bd400 ID |
3515 | if (chip->ecc.mode == NAND_ECC_SOFT_BCH) |
3516 | nand_bch_free((struct nand_bch_control *)chip->ecc.priv); | |
3517 | ||
5ffcaf3d | 3518 | mtd_device_unregister(mtd); |
1da177e4 | 3519 | |
fa671646 | 3520 | /* Free bad block table memory */ |
ace4dfee | 3521 | kfree(chip->bbt); |
4bf63fcb DW |
3522 | if (!(chip->options & NAND_OWN_BUFFERS)) |
3523 | kfree(chip->buffers); | |
58373ff0 BN |
3524 | |
3525 | /* Free bad block descriptor memory */ | |
3526 | if (chip->badblock_pattern && chip->badblock_pattern->options | |
3527 | & NAND_BBT_DYNAMICSTRUCT) | |
3528 | kfree(chip->badblock_pattern); | |
1da177e4 | 3529 | } |
e0c7d767 | 3530 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 RP |
3531 | |
3532 | static int __init nand_base_init(void) | |
3533 | { | |
3534 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
3535 | return 0; | |
3536 | } | |
3537 | ||
3538 | static void __exit nand_base_exit(void) | |
3539 | { | |
3540 | led_trigger_unregister_simple(nand_led_trigger); | |
3541 | } | |
3542 | ||
3543 | module_init(nand_base_init); | |
3544 | module_exit(nand_base_exit); | |
3545 | ||
e0c7d767 | 3546 | MODULE_LICENSE("GPL"); |
7351d3a5 FF |
3547 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); |
3548 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
e0c7d767 | 3549 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |