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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand.c | |
3 | * | |
4 | * Overview: | |
5 | * This is the generic MTD driver for NAND flash devices. It should be | |
6 | * capable of working with almost all NAND chips currently available. | |
61b03bd7 | 7 | * |
1da177e4 | 8 | * Additional technical information is available on |
8b2b403c | 9 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 10 | * |
1da177e4 | 11 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 12 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 13 | * |
ace4dfee | 14 | * Credits: |
61b03bd7 TG |
15 | * David Woodhouse for adding multichip support |
16 | * | |
1da177e4 LT |
17 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
18 | * rework for 2K page size chips | |
19 | * | |
ace4dfee | 20 | * TODO: |
1da177e4 LT |
21 | * Enable cached programming for 2k page size chips |
22 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
7854d3f7 | 23 | * if we have HW ECC support. |
c0b8ba7b | 24 | * BBT table is not serialized, has to be fixed |
1da177e4 | 25 | * |
1da177e4 LT |
26 | * This program is free software; you can redistribute it and/or modify |
27 | * it under the terms of the GNU General Public License version 2 as | |
28 | * published by the Free Software Foundation. | |
29 | * | |
30 | */ | |
31 | ||
20171642 EG |
32 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
33 | ||
552d9205 | 34 | #include <linux/module.h> |
1da177e4 LT |
35 | #include <linux/delay.h> |
36 | #include <linux/errno.h> | |
7aa65bfd | 37 | #include <linux/err.h> |
1da177e4 LT |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
40 | #include <linux/types.h> | |
41 | #include <linux/mtd/mtd.h> | |
42 | #include <linux/mtd/nand.h> | |
43 | #include <linux/mtd/nand_ecc.h> | |
193bd400 | 44 | #include <linux/mtd/nand_bch.h> |
1da177e4 LT |
45 | #include <linux/interrupt.h> |
46 | #include <linux/bitops.h> | |
8fe833c1 | 47 | #include <linux/leds.h> |
7351d3a5 | 48 | #include <linux/io.h> |
1da177e4 | 49 | #include <linux/mtd/partitions.h> |
1da177e4 LT |
50 | |
51 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 52 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
53 | .eccbytes = 3, |
54 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
55 | .oobfree = { |
56 | {.offset = 3, | |
57 | .length = 2}, | |
58 | {.offset = 6, | |
f8ac0414 | 59 | .length = 2} } |
1da177e4 LT |
60 | }; |
61 | ||
5bd34c09 | 62 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
63 | .eccbytes = 6, |
64 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
65 | .oobfree = { |
66 | {.offset = 8, | |
f8ac0414 | 67 | . length = 8} } |
1da177e4 LT |
68 | }; |
69 | ||
5bd34c09 | 70 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
71 | .eccbytes = 24, |
72 | .eccpos = { | |
e0c7d767 DW |
73 | 40, 41, 42, 43, 44, 45, 46, 47, |
74 | 48, 49, 50, 51, 52, 53, 54, 55, | |
75 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
76 | .oobfree = { |
77 | {.offset = 2, | |
f8ac0414 | 78 | .length = 38} } |
1da177e4 LT |
79 | }; |
80 | ||
81ec5364 TG |
81 | static struct nand_ecclayout nand_oob_128 = { |
82 | .eccbytes = 48, | |
83 | .eccpos = { | |
84 | 80, 81, 82, 83, 84, 85, 86, 87, | |
85 | 88, 89, 90, 91, 92, 93, 94, 95, | |
86 | 96, 97, 98, 99, 100, 101, 102, 103, | |
87 | 104, 105, 106, 107, 108, 109, 110, 111, | |
88 | 112, 113, 114, 115, 116, 117, 118, 119, | |
89 | 120, 121, 122, 123, 124, 125, 126, 127}, | |
90 | .oobfree = { | |
91 | {.offset = 2, | |
f8ac0414 | 92 | .length = 78} } |
81ec5364 TG |
93 | }; |
94 | ||
6a8214aa | 95 | static int nand_get_device(struct mtd_info *mtd, int new_state); |
1da177e4 | 96 | |
8593fbc6 TG |
97 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
98 | struct mtd_oob_ops *ops); | |
99 | ||
d470a97c | 100 | /* |
8e87d782 | 101 | * For devices which display every fart in the system on a separate LED. Is |
d470a97c TG |
102 | * compiled away when LED support is disabled. |
103 | */ | |
104 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
105 | ||
6fe5a6ac VS |
106 | static int check_offs_len(struct mtd_info *mtd, |
107 | loff_t ofs, uint64_t len) | |
108 | { | |
109 | struct nand_chip *chip = mtd->priv; | |
110 | int ret = 0; | |
111 | ||
112 | /* Start address must align on block boundary */ | |
daae74ca | 113 | if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 114 | pr_debug("%s: unaligned address\n", __func__); |
6fe5a6ac VS |
115 | ret = -EINVAL; |
116 | } | |
117 | ||
118 | /* Length must align on block boundary */ | |
daae74ca | 119 | if (len & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 120 | pr_debug("%s: length not block aligned\n", __func__); |
6fe5a6ac VS |
121 | ret = -EINVAL; |
122 | } | |
123 | ||
6fe5a6ac VS |
124 | return ret; |
125 | } | |
126 | ||
1da177e4 LT |
127 | /** |
128 | * nand_release_device - [GENERIC] release chip | |
8b6e50c9 | 129 | * @mtd: MTD device structure |
61b03bd7 | 130 | * |
b0bb6903 | 131 | * Release chip lock and wake up anyone waiting on the device. |
1da177e4 | 132 | */ |
e0c7d767 | 133 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 134 | { |
ace4dfee | 135 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 136 | |
a36ed299 | 137 | /* Release the controller and the chip */ |
ace4dfee TG |
138 | spin_lock(&chip->controller->lock); |
139 | chip->controller->active = NULL; | |
140 | chip->state = FL_READY; | |
141 | wake_up(&chip->controller->wq); | |
142 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
143 | } |
144 | ||
145 | /** | |
146 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
8b6e50c9 | 147 | * @mtd: MTD device structure |
1da177e4 | 148 | * |
7854d3f7 | 149 | * Default read function for 8bit buswidth |
1da177e4 | 150 | */ |
58dd8f2b | 151 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 152 | { |
ace4dfee TG |
153 | struct nand_chip *chip = mtd->priv; |
154 | return readb(chip->IO_ADDR_R); | |
1da177e4 LT |
155 | } |
156 | ||
1da177e4 | 157 | /** |
064a7694 | 158 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
7854d3f7 | 159 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
8b6e50c9 | 160 | * @mtd: MTD device structure |
1da177e4 | 161 | * |
7854d3f7 BN |
162 | * Default read function for 16bit buswidth with endianness conversion. |
163 | * | |
1da177e4 | 164 | */ |
58dd8f2b | 165 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 166 | { |
ace4dfee TG |
167 | struct nand_chip *chip = mtd->priv; |
168 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); | |
1da177e4 LT |
169 | } |
170 | ||
1da177e4 LT |
171 | /** |
172 | * nand_read_word - [DEFAULT] read one word from the chip | |
8b6e50c9 | 173 | * @mtd: MTD device structure |
1da177e4 | 174 | * |
7854d3f7 | 175 | * Default read function for 16bit buswidth without endianness conversion. |
1da177e4 LT |
176 | */ |
177 | static u16 nand_read_word(struct mtd_info *mtd) | |
178 | { | |
ace4dfee TG |
179 | struct nand_chip *chip = mtd->priv; |
180 | return readw(chip->IO_ADDR_R); | |
1da177e4 LT |
181 | } |
182 | ||
1da177e4 LT |
183 | /** |
184 | * nand_select_chip - [DEFAULT] control CE line | |
8b6e50c9 BN |
185 | * @mtd: MTD device structure |
186 | * @chipnr: chipnumber to select, -1 for deselect | |
1da177e4 LT |
187 | * |
188 | * Default select function for 1 chip devices. | |
189 | */ | |
ace4dfee | 190 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 191 | { |
ace4dfee TG |
192 | struct nand_chip *chip = mtd->priv; |
193 | ||
194 | switch (chipnr) { | |
1da177e4 | 195 | case -1: |
ace4dfee | 196 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
197 | break; |
198 | case 0: | |
1da177e4 LT |
199 | break; |
200 | ||
201 | default: | |
202 | BUG(); | |
203 | } | |
204 | } | |
205 | ||
05f78359 UKK |
206 | /** |
207 | * nand_write_byte - [DEFAULT] write single byte to chip | |
208 | * @mtd: MTD device structure | |
209 | * @byte: value to write | |
210 | * | |
211 | * Default function to write a byte to I/O[7:0] | |
212 | */ | |
213 | static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) | |
214 | { | |
215 | struct nand_chip *chip = mtd->priv; | |
216 | ||
217 | chip->write_buf(mtd, &byte, 1); | |
218 | } | |
219 | ||
220 | /** | |
221 | * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16 | |
222 | * @mtd: MTD device structure | |
223 | * @byte: value to write | |
224 | * | |
225 | * Default function to write a byte to I/O[7:0] on a 16-bit wide chip. | |
226 | */ | |
227 | static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) | |
228 | { | |
229 | struct nand_chip *chip = mtd->priv; | |
230 | uint16_t word = byte; | |
231 | ||
232 | /* | |
233 | * It's not entirely clear what should happen to I/O[15:8] when writing | |
234 | * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads: | |
235 | * | |
236 | * When the host supports a 16-bit bus width, only data is | |
237 | * transferred at the 16-bit width. All address and command line | |
238 | * transfers shall use only the lower 8-bits of the data bus. During | |
239 | * command transfers, the host may place any value on the upper | |
240 | * 8-bits of the data bus. During address transfers, the host shall | |
241 | * set the upper 8-bits of the data bus to 00h. | |
242 | * | |
243 | * One user of the write_byte callback is nand_onfi_set_features. The | |
244 | * four parameters are specified to be written to I/O[7:0], but this is | |
245 | * neither an address nor a command transfer. Let's assume a 0 on the | |
246 | * upper I/O lines is OK. | |
247 | */ | |
248 | chip->write_buf(mtd, (uint8_t *)&word, 2); | |
249 | } | |
250 | ||
1da177e4 LT |
251 | /** |
252 | * nand_write_buf - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
253 | * @mtd: MTD device structure |
254 | * @buf: data buffer | |
255 | * @len: number of bytes to write | |
1da177e4 | 256 | * |
7854d3f7 | 257 | * Default write function for 8bit buswidth. |
1da177e4 | 258 | */ |
58dd8f2b | 259 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 260 | { |
ace4dfee | 261 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 262 | |
76413839 | 263 | iowrite8_rep(chip->IO_ADDR_W, buf, len); |
1da177e4 LT |
264 | } |
265 | ||
266 | /** | |
61b03bd7 | 267 | * nand_read_buf - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
268 | * @mtd: MTD device structure |
269 | * @buf: buffer to store date | |
270 | * @len: number of bytes to read | |
1da177e4 | 271 | * |
7854d3f7 | 272 | * Default read function for 8bit buswidth. |
1da177e4 | 273 | */ |
58dd8f2b | 274 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 275 | { |
ace4dfee | 276 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 277 | |
76413839 | 278 | ioread8_rep(chip->IO_ADDR_R, buf, len); |
1da177e4 LT |
279 | } |
280 | ||
1da177e4 LT |
281 | /** |
282 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
283 | * @mtd: MTD device structure |
284 | * @buf: data buffer | |
285 | * @len: number of bytes to write | |
1da177e4 | 286 | * |
7854d3f7 | 287 | * Default write function for 16bit buswidth. |
1da177e4 | 288 | */ |
58dd8f2b | 289 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 290 | { |
ace4dfee | 291 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 292 | u16 *p = (u16 *) buf; |
61b03bd7 | 293 | |
76413839 | 294 | iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); |
1da177e4 LT |
295 | } |
296 | ||
297 | /** | |
61b03bd7 | 298 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
299 | * @mtd: MTD device structure |
300 | * @buf: buffer to store date | |
301 | * @len: number of bytes to read | |
1da177e4 | 302 | * |
7854d3f7 | 303 | * Default read function for 16bit buswidth. |
1da177e4 | 304 | */ |
58dd8f2b | 305 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 306 | { |
ace4dfee | 307 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 308 | u16 *p = (u16 *) buf; |
1da177e4 | 309 | |
76413839 | 310 | ioread16_rep(chip->IO_ADDR_R, p, len >> 1); |
1da177e4 LT |
311 | } |
312 | ||
1da177e4 LT |
313 | /** |
314 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
8b6e50c9 BN |
315 | * @mtd: MTD device structure |
316 | * @ofs: offset from device start | |
317 | * @getchip: 0, if the chip is already selected | |
1da177e4 | 318 | * |
61b03bd7 | 319 | * Check, if the block is bad. |
1da177e4 LT |
320 | */ |
321 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
322 | { | |
cdbec050 | 323 | int page, chipnr, res = 0, i = 0; |
ace4dfee | 324 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
325 | u16 bad; |
326 | ||
5fb1549d | 327 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
328 | ofs += mtd->erasesize - mtd->writesize; |
329 | ||
1a12f46a TK |
330 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
331 | ||
1da177e4 | 332 | if (getchip) { |
ace4dfee | 333 | chipnr = (int)(ofs >> chip->chip_shift); |
1da177e4 | 334 | |
6a8214aa | 335 | nand_get_device(mtd, FL_READING); |
1da177e4 LT |
336 | |
337 | /* Select the NAND device */ | |
ace4dfee | 338 | chip->select_chip(mtd, chipnr); |
1a12f46a | 339 | } |
1da177e4 | 340 | |
cdbec050 BN |
341 | do { |
342 | if (chip->options & NAND_BUSWIDTH_16) { | |
343 | chip->cmdfunc(mtd, NAND_CMD_READOOB, | |
344 | chip->badblockpos & 0xFE, page); | |
345 | bad = cpu_to_le16(chip->read_word(mtd)); | |
346 | if (chip->badblockpos & 0x1) | |
347 | bad >>= 8; | |
348 | else | |
349 | bad &= 0xFF; | |
350 | } else { | |
351 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, | |
352 | page); | |
353 | bad = chip->read_byte(mtd); | |
354 | } | |
355 | ||
356 | if (likely(chip->badblockbits == 8)) | |
357 | res = bad != 0xFF; | |
e0b58d0a | 358 | else |
cdbec050 BN |
359 | res = hweight8(bad) < chip->badblockbits; |
360 | ofs += mtd->writesize; | |
361 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; | |
362 | i++; | |
363 | } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); | |
e0b58d0a | 364 | |
b0bb6903 HS |
365 | if (getchip) { |
366 | chip->select_chip(mtd, -1); | |
1da177e4 | 367 | nand_release_device(mtd); |
b0bb6903 | 368 | } |
61b03bd7 | 369 | |
1da177e4 LT |
370 | return res; |
371 | } | |
372 | ||
373 | /** | |
5a0edb25 | 374 | * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker |
8b6e50c9 BN |
375 | * @mtd: MTD device structure |
376 | * @ofs: offset from device start | |
1da177e4 | 377 | * |
8b6e50c9 | 378 | * This is the default implementation, which can be overridden by a hardware |
5a0edb25 BN |
379 | * specific driver. It provides the details for writing a bad block marker to a |
380 | * block. | |
381 | */ | |
382 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
383 | { | |
384 | struct nand_chip *chip = mtd->priv; | |
385 | struct mtd_oob_ops ops; | |
386 | uint8_t buf[2] = { 0, 0 }; | |
387 | int ret = 0, res, i = 0; | |
388 | ||
389 | ops.datbuf = NULL; | |
390 | ops.oobbuf = buf; | |
391 | ops.ooboffs = chip->badblockpos; | |
392 | if (chip->options & NAND_BUSWIDTH_16) { | |
393 | ops.ooboffs &= ~0x01; | |
394 | ops.len = ops.ooblen = 2; | |
395 | } else { | |
396 | ops.len = ops.ooblen = 1; | |
397 | } | |
398 | ops.mode = MTD_OPS_PLACE_OOB; | |
399 | ||
400 | /* Write to first/last page(s) if necessary */ | |
401 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) | |
402 | ofs += mtd->erasesize - mtd->writesize; | |
403 | do { | |
404 | res = nand_do_write_oob(mtd, ofs, &ops); | |
405 | if (!ret) | |
406 | ret = res; | |
407 | ||
408 | i++; | |
409 | ofs += mtd->writesize; | |
410 | } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); | |
411 | ||
412 | return ret; | |
413 | } | |
414 | ||
415 | /** | |
416 | * nand_block_markbad_lowlevel - mark a block bad | |
417 | * @mtd: MTD device structure | |
418 | * @ofs: offset from device start | |
419 | * | |
420 | * This function performs the generic NAND bad block marking steps (i.e., bad | |
421 | * block table(s) and/or marker(s)). We only allow the hardware driver to | |
422 | * specify how to write bad block markers to OOB (chip->block_markbad). | |
423 | * | |
b32843b7 | 424 | * We try operations in the following order: |
e2414f4c | 425 | * (1) erase the affected block, to allow OOB marker to be written cleanly |
b32843b7 BN |
426 | * (2) write bad block marker to OOB area of affected block (unless flag |
427 | * NAND_BBT_NO_OOB_BBM is present) | |
428 | * (3) update the BBT | |
429 | * Note that we retain the first error encountered in (2) or (3), finish the | |
e2414f4c | 430 | * procedures, and dump the error in the end. |
1da177e4 | 431 | */ |
5a0edb25 | 432 | static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 433 | { |
ace4dfee | 434 | struct nand_chip *chip = mtd->priv; |
b32843b7 | 435 | int res, ret = 0; |
61b03bd7 | 436 | |
b32843b7 | 437 | if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { |
00918429 BN |
438 | struct erase_info einfo; |
439 | ||
440 | /* Attempt erase before marking OOB */ | |
441 | memset(&einfo, 0, sizeof(einfo)); | |
442 | einfo.mtd = mtd; | |
443 | einfo.addr = ofs; | |
daae74ca | 444 | einfo.len = 1ULL << chip->phys_erase_shift; |
00918429 | 445 | nand_erase_nand(mtd, &einfo, 0); |
1da177e4 | 446 | |
b32843b7 | 447 | /* Write bad block marker to OOB */ |
6a8214aa | 448 | nand_get_device(mtd, FL_WRITING); |
5a0edb25 | 449 | ret = chip->block_markbad(mtd, ofs); |
c0b8ba7b | 450 | nand_release_device(mtd); |
f1a28c02 | 451 | } |
e2414f4c | 452 | |
b32843b7 BN |
453 | /* Mark block bad in BBT */ |
454 | if (chip->bbt) { | |
455 | res = nand_markbad_bbt(mtd, ofs); | |
e2414f4c BN |
456 | if (!ret) |
457 | ret = res; | |
458 | } | |
459 | ||
f1a28c02 TG |
460 | if (!ret) |
461 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 462 | |
f1a28c02 | 463 | return ret; |
1da177e4 LT |
464 | } |
465 | ||
61b03bd7 | 466 | /** |
1da177e4 | 467 | * nand_check_wp - [GENERIC] check if the chip is write protected |
8b6e50c9 | 468 | * @mtd: MTD device structure |
1da177e4 | 469 | * |
8b6e50c9 BN |
470 | * Check, if the device is write protected. The function expects, that the |
471 | * device is already selected. | |
1da177e4 | 472 | */ |
e0c7d767 | 473 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 474 | { |
ace4dfee | 475 | struct nand_chip *chip = mtd->priv; |
93edbad6 | 476 | |
8b6e50c9 | 477 | /* Broken xD cards report WP despite being writable */ |
93edbad6 ML |
478 | if (chip->options & NAND_BROKEN_XD) |
479 | return 0; | |
480 | ||
1da177e4 | 481 | /* Check the WP bit */ |
ace4dfee TG |
482 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
483 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
484 | } |
485 | ||
486 | /** | |
487 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
8b6e50c9 BN |
488 | * @mtd: MTD device structure |
489 | * @ofs: offset from device start | |
490 | * @getchip: 0, if the chip is already selected | |
491 | * @allowbbt: 1, if its allowed to access the bbt area | |
1da177e4 LT |
492 | * |
493 | * Check, if the block is bad. Either by reading the bad block table or | |
494 | * calling of the scan function. | |
495 | */ | |
2c0a2bed TG |
496 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
497 | int allowbbt) | |
1da177e4 | 498 | { |
ace4dfee | 499 | struct nand_chip *chip = mtd->priv; |
61b03bd7 | 500 | |
ace4dfee TG |
501 | if (!chip->bbt) |
502 | return chip->block_bad(mtd, ofs, getchip); | |
61b03bd7 | 503 | |
1da177e4 | 504 | /* Return info from the table */ |
e0c7d767 | 505 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
506 | } |
507 | ||
2af7c653 SK |
508 | /** |
509 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
8b6e50c9 BN |
510 | * @mtd: MTD device structure |
511 | * @timeo: Timeout | |
2af7c653 SK |
512 | * |
513 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
514 | * context. | |
515 | */ | |
516 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
517 | { | |
518 | struct nand_chip *chip = mtd->priv; | |
519 | int i; | |
520 | ||
521 | /* Wait for the device to get ready */ | |
522 | for (i = 0; i < timeo; i++) { | |
523 | if (chip->dev_ready(mtd)) | |
524 | break; | |
525 | touch_softlockup_watchdog(); | |
526 | mdelay(1); | |
527 | } | |
528 | } | |
529 | ||
7854d3f7 | 530 | /* Wait for the ready pin, after a command. The timeout is caught later. */ |
4b648b02 | 531 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 532 | { |
ace4dfee | 533 | struct nand_chip *chip = mtd->priv; |
ca6a2489 | 534 | unsigned long timeo = jiffies + msecs_to_jiffies(20); |
3b88775c | 535 | |
2af7c653 SK |
536 | /* 400ms timeout */ |
537 | if (in_interrupt() || oops_in_progress) | |
538 | return panic_nand_wait_ready(mtd, 400); | |
539 | ||
8fe833c1 | 540 | led_trigger_event(nand_led_trigger, LED_FULL); |
7854d3f7 | 541 | /* Wait until command is processed or timeout occurs */ |
3b88775c | 542 | do { |
ace4dfee | 543 | if (chip->dev_ready(mtd)) |
8fe833c1 | 544 | break; |
8446f1d3 | 545 | touch_softlockup_watchdog(); |
61b03bd7 | 546 | } while (time_before(jiffies, timeo)); |
8fe833c1 | 547 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c | 548 | } |
4b648b02 | 549 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 550 | |
1da177e4 LT |
551 | /** |
552 | * nand_command - [DEFAULT] Send command to NAND device | |
8b6e50c9 BN |
553 | * @mtd: MTD device structure |
554 | * @command: the command to be sent | |
555 | * @column: the column address for this command, -1 if none | |
556 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 557 | * |
8b6e50c9 | 558 | * Send command to NAND device. This function is used for small page devices |
51148f1f | 559 | * (512 Bytes per page). |
1da177e4 | 560 | */ |
7abd3ef9 TG |
561 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
562 | int column, int page_addr) | |
1da177e4 | 563 | { |
ace4dfee | 564 | register struct nand_chip *chip = mtd->priv; |
7abd3ef9 | 565 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 566 | |
8b6e50c9 | 567 | /* Write out the command to the device */ |
1da177e4 LT |
568 | if (command == NAND_CMD_SEQIN) { |
569 | int readcmd; | |
570 | ||
28318776 | 571 | if (column >= mtd->writesize) { |
1da177e4 | 572 | /* OOB area */ |
28318776 | 573 | column -= mtd->writesize; |
1da177e4 LT |
574 | readcmd = NAND_CMD_READOOB; |
575 | } else if (column < 256) { | |
576 | /* First 256 bytes --> READ0 */ | |
577 | readcmd = NAND_CMD_READ0; | |
578 | } else { | |
579 | column -= 256; | |
580 | readcmd = NAND_CMD_READ1; | |
581 | } | |
ace4dfee | 582 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 583 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 584 | } |
ace4dfee | 585 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 586 | |
8b6e50c9 | 587 | /* Address cycle, when necessary */ |
7abd3ef9 TG |
588 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; |
589 | /* Serially input address */ | |
590 | if (column != -1) { | |
591 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
592 | if (chip->options & NAND_BUSWIDTH_16 && |
593 | !nand_opcode_8bits(command)) | |
7abd3ef9 | 594 | column >>= 1; |
ace4dfee | 595 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
596 | ctrl &= ~NAND_CTRL_CHANGE; |
597 | } | |
598 | if (page_addr != -1) { | |
ace4dfee | 599 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 600 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 601 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 602 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
603 | if (chip->chipsize > (32 << 20)) |
604 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 605 | } |
ace4dfee | 606 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
607 | |
608 | /* | |
8b6e50c9 BN |
609 | * Program and erase have their own busy handlers status and sequential |
610 | * in needs no delay | |
e0c7d767 | 611 | */ |
1da177e4 | 612 | switch (command) { |
61b03bd7 | 613 | |
1da177e4 LT |
614 | case NAND_CMD_PAGEPROG: |
615 | case NAND_CMD_ERASE1: | |
616 | case NAND_CMD_ERASE2: | |
617 | case NAND_CMD_SEQIN: | |
618 | case NAND_CMD_STATUS: | |
619 | return; | |
620 | ||
621 | case NAND_CMD_RESET: | |
ace4dfee | 622 | if (chip->dev_ready) |
1da177e4 | 623 | break; |
ace4dfee TG |
624 | udelay(chip->chip_delay); |
625 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 626 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
627 | chip->cmd_ctrl(mtd, |
628 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
629 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
630 | ; | |
1da177e4 LT |
631 | return; |
632 | ||
e0c7d767 | 633 | /* This applies to read commands */ |
1da177e4 | 634 | default: |
61b03bd7 | 635 | /* |
1da177e4 LT |
636 | * If we don't have access to the busy pin, we apply the given |
637 | * command delay | |
e0c7d767 | 638 | */ |
ace4dfee TG |
639 | if (!chip->dev_ready) { |
640 | udelay(chip->chip_delay); | |
1da177e4 | 641 | return; |
61b03bd7 | 642 | } |
1da177e4 | 643 | } |
8b6e50c9 BN |
644 | /* |
645 | * Apply this short delay always to ensure that we do wait tWB in | |
646 | * any case on any machine. | |
647 | */ | |
e0c7d767 | 648 | ndelay(100); |
3b88775c TG |
649 | |
650 | nand_wait_ready(mtd); | |
1da177e4 LT |
651 | } |
652 | ||
653 | /** | |
654 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
8b6e50c9 BN |
655 | * @mtd: MTD device structure |
656 | * @command: the command to be sent | |
657 | * @column: the column address for this command, -1 if none | |
658 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 659 | * |
7abd3ef9 | 660 | * Send command to NAND device. This is the version for the new large page |
7854d3f7 BN |
661 | * devices. We don't have the separate regions as we have in the small page |
662 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 663 | */ |
7abd3ef9 TG |
664 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
665 | int column, int page_addr) | |
1da177e4 | 666 | { |
ace4dfee | 667 | register struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
668 | |
669 | /* Emulate NAND_CMD_READOOB */ | |
670 | if (command == NAND_CMD_READOOB) { | |
28318776 | 671 | column += mtd->writesize; |
1da177e4 LT |
672 | command = NAND_CMD_READ0; |
673 | } | |
61b03bd7 | 674 | |
7abd3ef9 | 675 | /* Command latch cycle */ |
fb066ada | 676 | chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
677 | |
678 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 679 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
680 | |
681 | /* Serially input address */ | |
682 | if (column != -1) { | |
683 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
684 | if (chip->options & NAND_BUSWIDTH_16 && |
685 | !nand_opcode_8bits(command)) | |
1da177e4 | 686 | column >>= 1; |
ace4dfee | 687 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 688 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 689 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 690 | } |
1da177e4 | 691 | if (page_addr != -1) { |
ace4dfee TG |
692 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
693 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 694 | NAND_NCE | NAND_ALE); |
1da177e4 | 695 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
696 | if (chip->chipsize > (128 << 20)) |
697 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 698 | NAND_NCE | NAND_ALE); |
1da177e4 | 699 | } |
1da177e4 | 700 | } |
ace4dfee | 701 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
702 | |
703 | /* | |
8b6e50c9 BN |
704 | * Program and erase have their own busy handlers status, sequential |
705 | * in, and deplete1 need no delay. | |
30f464b7 | 706 | */ |
1da177e4 | 707 | switch (command) { |
61b03bd7 | 708 | |
1da177e4 LT |
709 | case NAND_CMD_CACHEDPROG: |
710 | case NAND_CMD_PAGEPROG: | |
711 | case NAND_CMD_ERASE1: | |
712 | case NAND_CMD_ERASE2: | |
713 | case NAND_CMD_SEQIN: | |
7bc3312b | 714 | case NAND_CMD_RNDIN: |
1da177e4 | 715 | case NAND_CMD_STATUS: |
30f464b7 | 716 | return; |
1da177e4 LT |
717 | |
718 | case NAND_CMD_RESET: | |
ace4dfee | 719 | if (chip->dev_ready) |
1da177e4 | 720 | break; |
ace4dfee | 721 | udelay(chip->chip_delay); |
12efdde3 TG |
722 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
723 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
724 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
725 | NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
726 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
727 | ; | |
1da177e4 LT |
728 | return; |
729 | ||
7bc3312b TG |
730 | case NAND_CMD_RNDOUT: |
731 | /* No ready / busy check necessary */ | |
732 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
733 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
734 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
735 | NAND_NCE | NAND_CTRL_CHANGE); | |
736 | return; | |
737 | ||
1da177e4 | 738 | case NAND_CMD_READ0: |
12efdde3 TG |
739 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
740 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
741 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
742 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 743 | |
e0c7d767 | 744 | /* This applies to read commands */ |
1da177e4 | 745 | default: |
61b03bd7 | 746 | /* |
1da177e4 | 747 | * If we don't have access to the busy pin, we apply the given |
8b6e50c9 | 748 | * command delay. |
e0c7d767 | 749 | */ |
ace4dfee TG |
750 | if (!chip->dev_ready) { |
751 | udelay(chip->chip_delay); | |
1da177e4 | 752 | return; |
61b03bd7 | 753 | } |
1da177e4 | 754 | } |
3b88775c | 755 | |
8b6e50c9 BN |
756 | /* |
757 | * Apply this short delay always to ensure that we do wait tWB in | |
758 | * any case on any machine. | |
759 | */ | |
e0c7d767 | 760 | ndelay(100); |
3b88775c TG |
761 | |
762 | nand_wait_ready(mtd); | |
1da177e4 LT |
763 | } |
764 | ||
2af7c653 SK |
765 | /** |
766 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
767 | * @chip: the nand chip descriptor |
768 | * @mtd: MTD device structure | |
769 | * @new_state: the state which is requested | |
2af7c653 SK |
770 | * |
771 | * Used when in panic, no locks are taken. | |
772 | */ | |
773 | static void panic_nand_get_device(struct nand_chip *chip, | |
774 | struct mtd_info *mtd, int new_state) | |
775 | { | |
7854d3f7 | 776 | /* Hardware controller shared among independent devices */ |
2af7c653 SK |
777 | chip->controller->active = chip; |
778 | chip->state = new_state; | |
779 | } | |
780 | ||
1da177e4 LT |
781 | /** |
782 | * nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
783 | * @mtd: MTD device structure |
784 | * @new_state: the state which is requested | |
1da177e4 LT |
785 | * |
786 | * Get the device and lock it for exclusive access | |
787 | */ | |
2c0a2bed | 788 | static int |
6a8214aa | 789 | nand_get_device(struct mtd_info *mtd, int new_state) |
1da177e4 | 790 | { |
6a8214aa | 791 | struct nand_chip *chip = mtd->priv; |
ace4dfee TG |
792 | spinlock_t *lock = &chip->controller->lock; |
793 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 794 | DECLARE_WAITQUEUE(wait, current); |
7351d3a5 | 795 | retry: |
0dfc6246 TG |
796 | spin_lock(lock); |
797 | ||
b8b3ee9a | 798 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
799 | if (!chip->controller->active) |
800 | chip->controller->active = chip; | |
a36ed299 | 801 | |
ace4dfee TG |
802 | if (chip->controller->active == chip && chip->state == FL_READY) { |
803 | chip->state = new_state; | |
0dfc6246 | 804 | spin_unlock(lock); |
962034f4 VW |
805 | return 0; |
806 | } | |
807 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
808 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
809 | chip->state = FL_PM_SUSPENDED; | |
810 | spin_unlock(lock); | |
811 | return 0; | |
6b0d9a84 | 812 | } |
0dfc6246 TG |
813 | } |
814 | set_current_state(TASK_UNINTERRUPTIBLE); | |
815 | add_wait_queue(wq, &wait); | |
816 | spin_unlock(lock); | |
817 | schedule(); | |
818 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
819 | goto retry; |
820 | } | |
821 | ||
2af7c653 | 822 | /** |
8b6e50c9 BN |
823 | * panic_nand_wait - [GENERIC] wait until the command is done |
824 | * @mtd: MTD device structure | |
825 | * @chip: NAND chip structure | |
826 | * @timeo: timeout | |
2af7c653 SK |
827 | * |
828 | * Wait for command done. This is a helper function for nand_wait used when | |
829 | * we are in interrupt context. May happen when in panic and trying to write | |
b595076a | 830 | * an oops through mtdoops. |
2af7c653 SK |
831 | */ |
832 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
833 | unsigned long timeo) | |
834 | { | |
835 | int i; | |
836 | for (i = 0; i < timeo; i++) { | |
837 | if (chip->dev_ready) { | |
838 | if (chip->dev_ready(mtd)) | |
839 | break; | |
840 | } else { | |
841 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
842 | break; | |
843 | } | |
844 | mdelay(1); | |
f8ac0414 | 845 | } |
2af7c653 SK |
846 | } |
847 | ||
1da177e4 | 848 | /** |
8b6e50c9 BN |
849 | * nand_wait - [DEFAULT] wait until the command is done |
850 | * @mtd: MTD device structure | |
851 | * @chip: NAND chip structure | |
1da177e4 | 852 | * |
8b6e50c9 BN |
853 | * Wait for command done. This applies to erase and program only. Erase can |
854 | * take up to 400ms and program up to 20ms according to general NAND and | |
855 | * SmartMedia specs. | |
844d3b42 | 856 | */ |
7bc3312b | 857 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
858 | { |
859 | ||
7bc3312b | 860 | int status, state = chip->state; |
6d2559f8 | 861 | unsigned long timeo = (state == FL_ERASING ? 400 : 20); |
1da177e4 | 862 | |
8fe833c1 RP |
863 | led_trigger_event(nand_led_trigger, LED_FULL); |
864 | ||
8b6e50c9 BN |
865 | /* |
866 | * Apply this short delay always to ensure that we do wait tWB in any | |
867 | * case on any machine. | |
868 | */ | |
e0c7d767 | 869 | ndelay(100); |
1da177e4 | 870 | |
14c65786 | 871 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 872 | |
2af7c653 SK |
873 | if (in_interrupt() || oops_in_progress) |
874 | panic_nand_wait(mtd, chip, timeo); | |
875 | else { | |
6d2559f8 | 876 | timeo = jiffies + msecs_to_jiffies(timeo); |
2af7c653 SK |
877 | while (time_before(jiffies, timeo)) { |
878 | if (chip->dev_ready) { | |
879 | if (chip->dev_ready(mtd)) | |
880 | break; | |
881 | } else { | |
882 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
883 | break; | |
884 | } | |
885 | cond_resched(); | |
1da177e4 | 886 | } |
1da177e4 | 887 | } |
8fe833c1 RP |
888 | led_trigger_event(nand_led_trigger, LED_OFF); |
889 | ||
ace4dfee | 890 | status = (int)chip->read_byte(mtd); |
f251b8df MC |
891 | /* This can happen if in case of timeout or buggy dev_ready */ |
892 | WARN_ON(!(status & NAND_STATUS_READY)); | |
1da177e4 LT |
893 | return status; |
894 | } | |
895 | ||
7d70f334 | 896 | /** |
b6d676db | 897 | * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
898 | * @mtd: mtd info |
899 | * @ofs: offset to start unlock from | |
900 | * @len: length to unlock | |
8b6e50c9 BN |
901 | * @invert: when = 0, unlock the range of blocks within the lower and |
902 | * upper boundary address | |
903 | * when = 1, unlock the range of blocks outside the boundaries | |
904 | * of the lower and upper boundary address | |
7d70f334 | 905 | * |
8b6e50c9 | 906 | * Returs unlock status. |
7d70f334 VS |
907 | */ |
908 | static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, | |
909 | uint64_t len, int invert) | |
910 | { | |
911 | int ret = 0; | |
912 | int status, page; | |
913 | struct nand_chip *chip = mtd->priv; | |
914 | ||
915 | /* Submit address of first page to unlock */ | |
916 | page = ofs >> chip->page_shift; | |
917 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); | |
918 | ||
919 | /* Submit address of last page to unlock */ | |
920 | page = (ofs + len) >> chip->page_shift; | |
921 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, | |
922 | (page | invert) & chip->pagemask); | |
923 | ||
924 | /* Call wait ready function */ | |
925 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 926 | /* See if device thinks it succeeded */ |
74830966 | 927 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 928 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
929 | __func__, status); |
930 | ret = -EIO; | |
931 | } | |
932 | ||
933 | return ret; | |
934 | } | |
935 | ||
936 | /** | |
b6d676db | 937 | * nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
938 | * @mtd: mtd info |
939 | * @ofs: offset to start unlock from | |
940 | * @len: length to unlock | |
7d70f334 | 941 | * |
8b6e50c9 | 942 | * Returns unlock status. |
7d70f334 VS |
943 | */ |
944 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
945 | { | |
946 | int ret = 0; | |
947 | int chipnr; | |
948 | struct nand_chip *chip = mtd->priv; | |
949 | ||
289c0522 | 950 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
951 | __func__, (unsigned long long)ofs, len); |
952 | ||
953 | if (check_offs_len(mtd, ofs, len)) | |
954 | ret = -EINVAL; | |
955 | ||
956 | /* Align to last block address if size addresses end of the device */ | |
957 | if (ofs + len == mtd->size) | |
958 | len -= mtd->erasesize; | |
959 | ||
6a8214aa | 960 | nand_get_device(mtd, FL_UNLOCKING); |
7d70f334 VS |
961 | |
962 | /* Shift to get chip number */ | |
963 | chipnr = ofs >> chip->chip_shift; | |
964 | ||
965 | chip->select_chip(mtd, chipnr); | |
966 | ||
967 | /* Check, if it is write protected */ | |
968 | if (nand_check_wp(mtd)) { | |
289c0522 | 969 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
970 | __func__); |
971 | ret = -EIO; | |
972 | goto out; | |
973 | } | |
974 | ||
975 | ret = __nand_unlock(mtd, ofs, len, 0); | |
976 | ||
977 | out: | |
b0bb6903 | 978 | chip->select_chip(mtd, -1); |
7d70f334 VS |
979 | nand_release_device(mtd); |
980 | ||
981 | return ret; | |
982 | } | |
7351d3a5 | 983 | EXPORT_SYMBOL(nand_unlock); |
7d70f334 VS |
984 | |
985 | /** | |
b6d676db | 986 | * nand_lock - [REPLACEABLE] locks all blocks present in the device |
b6d676db RD |
987 | * @mtd: mtd info |
988 | * @ofs: offset to start unlock from | |
989 | * @len: length to unlock | |
7d70f334 | 990 | * |
8b6e50c9 BN |
991 | * This feature is not supported in many NAND parts. 'Micron' NAND parts do |
992 | * have this feature, but it allows only to lock all blocks, not for specified | |
993 | * range for block. Implementing 'lock' feature by making use of 'unlock', for | |
994 | * now. | |
7d70f334 | 995 | * |
8b6e50c9 | 996 | * Returns lock status. |
7d70f334 VS |
997 | */ |
998 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
999 | { | |
1000 | int ret = 0; | |
1001 | int chipnr, status, page; | |
1002 | struct nand_chip *chip = mtd->priv; | |
1003 | ||
289c0522 | 1004 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
1005 | __func__, (unsigned long long)ofs, len); |
1006 | ||
1007 | if (check_offs_len(mtd, ofs, len)) | |
1008 | ret = -EINVAL; | |
1009 | ||
6a8214aa | 1010 | nand_get_device(mtd, FL_LOCKING); |
7d70f334 VS |
1011 | |
1012 | /* Shift to get chip number */ | |
1013 | chipnr = ofs >> chip->chip_shift; | |
1014 | ||
1015 | chip->select_chip(mtd, chipnr); | |
1016 | ||
1017 | /* Check, if it is write protected */ | |
1018 | if (nand_check_wp(mtd)) { | |
289c0522 | 1019 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
1020 | __func__); |
1021 | status = MTD_ERASE_FAILED; | |
1022 | ret = -EIO; | |
1023 | goto out; | |
1024 | } | |
1025 | ||
1026 | /* Submit address of first page to lock */ | |
1027 | page = ofs >> chip->page_shift; | |
1028 | chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); | |
1029 | ||
1030 | /* Call wait ready function */ | |
1031 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 1032 | /* See if device thinks it succeeded */ |
74830966 | 1033 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 1034 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
1035 | __func__, status); |
1036 | ret = -EIO; | |
1037 | goto out; | |
1038 | } | |
1039 | ||
1040 | ret = __nand_unlock(mtd, ofs, len, 0x1); | |
1041 | ||
1042 | out: | |
b0bb6903 | 1043 | chip->select_chip(mtd, -1); |
7d70f334 VS |
1044 | nand_release_device(mtd); |
1045 | ||
1046 | return ret; | |
1047 | } | |
7351d3a5 | 1048 | EXPORT_SYMBOL(nand_lock); |
7d70f334 | 1049 | |
8593fbc6 | 1050 | /** |
7854d3f7 | 1051 | * nand_read_page_raw - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1052 | * @mtd: mtd info structure |
1053 | * @chip: nand chip info structure | |
1054 | * @buf: buffer to store read data | |
1fbb938d | 1055 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1056 | * @page: page number to read |
52ff49df | 1057 | * |
7854d3f7 | 1058 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 TG |
1059 | */ |
1060 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1061 | uint8_t *buf, int oob_required, int page) |
8593fbc6 TG |
1062 | { |
1063 | chip->read_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1064 | if (oob_required) |
1065 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
8593fbc6 TG |
1066 | return 0; |
1067 | } | |
1068 | ||
52ff49df | 1069 | /** |
7854d3f7 | 1070 | * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1071 | * @mtd: mtd info structure |
1072 | * @chip: nand chip info structure | |
1073 | * @buf: buffer to store read data | |
1fbb938d | 1074 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1075 | * @page: page number to read |
52ff49df DB |
1076 | * |
1077 | * We need a special oob layout and handling even when OOB isn't used. | |
1078 | */ | |
7351d3a5 | 1079 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
1080 | struct nand_chip *chip, uint8_t *buf, |
1081 | int oob_required, int page) | |
52ff49df DB |
1082 | { |
1083 | int eccsize = chip->ecc.size; | |
1084 | int eccbytes = chip->ecc.bytes; | |
1085 | uint8_t *oob = chip->oob_poi; | |
1086 | int steps, size; | |
1087 | ||
1088 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1089 | chip->read_buf(mtd, buf, eccsize); | |
1090 | buf += eccsize; | |
1091 | ||
1092 | if (chip->ecc.prepad) { | |
1093 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1094 | oob += chip->ecc.prepad; | |
1095 | } | |
1096 | ||
1097 | chip->read_buf(mtd, oob, eccbytes); | |
1098 | oob += eccbytes; | |
1099 | ||
1100 | if (chip->ecc.postpad) { | |
1101 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1102 | oob += chip->ecc.postpad; | |
1103 | } | |
1104 | } | |
1105 | ||
1106 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1107 | if (size) | |
1108 | chip->read_buf(mtd, oob, size); | |
1109 | ||
1110 | return 0; | |
1111 | } | |
1112 | ||
1da177e4 | 1113 | /** |
7854d3f7 | 1114 | * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function |
8b6e50c9 BN |
1115 | * @mtd: mtd info structure |
1116 | * @chip: nand chip info structure | |
1117 | * @buf: buffer to store read data | |
1fbb938d | 1118 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1119 | * @page: page number to read |
068e3c0a | 1120 | */ |
f5bbdacc | 1121 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1122 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1123 | { |
f5bbdacc TG |
1124 | int i, eccsize = chip->ecc.size; |
1125 | int eccbytes = chip->ecc.bytes; | |
1126 | int eccsteps = chip->ecc.steps; | |
1127 | uint8_t *p = buf; | |
4bf63fcb DW |
1128 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1129 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1130 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1131 | unsigned int max_bitflips = 0; |
f5bbdacc | 1132 | |
1fbb938d | 1133 | chip->ecc.read_page_raw(mtd, chip, buf, 1, page); |
f5bbdacc TG |
1134 | |
1135 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1136 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1137 | ||
1138 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 1139 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
1140 | |
1141 | eccsteps = chip->ecc.steps; | |
1142 | p = buf; | |
1143 | ||
1144 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1145 | int stat; | |
1146 | ||
1147 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
3f91e94f | 1148 | if (stat < 0) { |
f5bbdacc | 1149 | mtd->ecc_stats.failed++; |
3f91e94f | 1150 | } else { |
f5bbdacc | 1151 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1152 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1153 | } | |
f5bbdacc | 1154 | } |
3f91e94f | 1155 | return max_bitflips; |
22c60f5f | 1156 | } |
1da177e4 | 1157 | |
3d459559 | 1158 | /** |
837a6ba4 | 1159 | * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function |
8b6e50c9 BN |
1160 | * @mtd: mtd info structure |
1161 | * @chip: nand chip info structure | |
1162 | * @data_offs: offset of requested data within the page | |
1163 | * @readlen: data length | |
1164 | * @bufpoi: buffer to store read data | |
e004debd | 1165 | * @page: page number to read |
3d459559 | 1166 | */ |
7351d3a5 | 1167 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, |
e004debd HS |
1168 | uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, |
1169 | int page) | |
3d459559 AK |
1170 | { |
1171 | int start_step, end_step, num_steps; | |
1172 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1173 | uint8_t *p; | |
1174 | int data_col_addr, i, gaps = 0; | |
1175 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1176 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
4a4163ca | 1177 | int index; |
3f91e94f | 1178 | unsigned int max_bitflips = 0; |
3d459559 | 1179 | |
7854d3f7 | 1180 | /* Column address within the page aligned to ECC size (256bytes) */ |
3d459559 AK |
1181 | start_step = data_offs / chip->ecc.size; |
1182 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1183 | num_steps = end_step - start_step + 1; | |
4a4163ca | 1184 | index = start_step * chip->ecc.bytes; |
3d459559 | 1185 | |
8b6e50c9 | 1186 | /* Data size aligned to ECC ecc.size */ |
3d459559 AK |
1187 | datafrag_len = num_steps * chip->ecc.size; |
1188 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1189 | ||
1190 | data_col_addr = start_step * chip->ecc.size; | |
1191 | /* If we read not a page aligned data */ | |
1192 | if (data_col_addr != 0) | |
1193 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1194 | ||
1195 | p = bufpoi + data_col_addr; | |
1196 | chip->read_buf(mtd, p, datafrag_len); | |
1197 | ||
8b6e50c9 | 1198 | /* Calculate ECC */ |
3d459559 AK |
1199 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) |
1200 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1201 | ||
8b6e50c9 BN |
1202 | /* |
1203 | * The performance is faster if we position offsets according to | |
7854d3f7 | 1204 | * ecc.pos. Let's make sure that there are no gaps in ECC positions. |
8b6e50c9 | 1205 | */ |
3d459559 AK |
1206 | for (i = 0; i < eccfrag_len - 1; i++) { |
1207 | if (eccpos[i + start_step * chip->ecc.bytes] + 1 != | |
1208 | eccpos[i + start_step * chip->ecc.bytes + 1]) { | |
1209 | gaps = 1; | |
1210 | break; | |
1211 | } | |
1212 | } | |
1213 | if (gaps) { | |
1214 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1215 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1216 | } else { | |
8b6e50c9 | 1217 | /* |
7854d3f7 | 1218 | * Send the command to read the particular ECC bytes take care |
8b6e50c9 BN |
1219 | * about buswidth alignment in read_buf. |
1220 | */ | |
7351d3a5 | 1221 | aligned_pos = eccpos[index] & ~(busw - 1); |
3d459559 | 1222 | aligned_len = eccfrag_len; |
7351d3a5 | 1223 | if (eccpos[index] & (busw - 1)) |
3d459559 | 1224 | aligned_len++; |
7351d3a5 | 1225 | if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1)) |
3d459559 AK |
1226 | aligned_len++; |
1227 | ||
7351d3a5 FF |
1228 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, |
1229 | mtd->writesize + aligned_pos, -1); | |
3d459559 AK |
1230 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); |
1231 | } | |
1232 | ||
1233 | for (i = 0; i < eccfrag_len; i++) | |
7351d3a5 | 1234 | chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]]; |
3d459559 AK |
1235 | |
1236 | p = bufpoi + data_col_addr; | |
1237 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1238 | int stat; | |
1239 | ||
7351d3a5 FF |
1240 | stat = chip->ecc.correct(mtd, p, |
1241 | &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
3f91e94f | 1242 | if (stat < 0) { |
3d459559 | 1243 | mtd->ecc_stats.failed++; |
3f91e94f | 1244 | } else { |
3d459559 | 1245 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1246 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1247 | } | |
3d459559 | 1248 | } |
3f91e94f | 1249 | return max_bitflips; |
3d459559 AK |
1250 | } |
1251 | ||
068e3c0a | 1252 | /** |
7854d3f7 | 1253 | * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function |
8b6e50c9 BN |
1254 | * @mtd: mtd info structure |
1255 | * @chip: nand chip info structure | |
1256 | * @buf: buffer to store read data | |
1fbb938d | 1257 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1258 | * @page: page number to read |
068e3c0a | 1259 | * |
7854d3f7 | 1260 | * Not for syndrome calculating ECC controllers which need a special oob layout. |
068e3c0a | 1261 | */ |
f5bbdacc | 1262 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1263 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1264 | { |
f5bbdacc TG |
1265 | int i, eccsize = chip->ecc.size; |
1266 | int eccbytes = chip->ecc.bytes; | |
1267 | int eccsteps = chip->ecc.steps; | |
1268 | uint8_t *p = buf; | |
4bf63fcb DW |
1269 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1270 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1271 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1272 | unsigned int max_bitflips = 0; |
f5bbdacc TG |
1273 | |
1274 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1275 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1276 | chip->read_buf(mtd, p, eccsize); | |
1277 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1278 | } |
f75e5097 | 1279 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1280 | |
f5bbdacc | 1281 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 1282 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 1283 | |
f5bbdacc TG |
1284 | eccsteps = chip->ecc.steps; |
1285 | p = buf; | |
61b03bd7 | 1286 | |
f5bbdacc TG |
1287 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1288 | int stat; | |
1da177e4 | 1289 | |
f5bbdacc | 1290 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
3f91e94f | 1291 | if (stat < 0) { |
f5bbdacc | 1292 | mtd->ecc_stats.failed++; |
3f91e94f | 1293 | } else { |
f5bbdacc | 1294 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1295 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1296 | } | |
f5bbdacc | 1297 | } |
3f91e94f | 1298 | return max_bitflips; |
f5bbdacc | 1299 | } |
1da177e4 | 1300 | |
6e0cb135 | 1301 | /** |
7854d3f7 | 1302 | * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first |
8b6e50c9 BN |
1303 | * @mtd: mtd info structure |
1304 | * @chip: nand chip info structure | |
1305 | * @buf: buffer to store read data | |
1fbb938d | 1306 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1307 | * @page: page number to read |
6e0cb135 | 1308 | * |
8b6e50c9 BN |
1309 | * Hardware ECC for large page chips, require OOB to be read first. For this |
1310 | * ECC mode, the write_page method is re-used from ECC_HW. These methods | |
1311 | * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with | |
1312 | * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from | |
1313 | * the data area, by overwriting the NAND manufacturer bad block markings. | |
6e0cb135 SN |
1314 | */ |
1315 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1fbb938d | 1316 | struct nand_chip *chip, uint8_t *buf, int oob_required, int page) |
6e0cb135 SN |
1317 | { |
1318 | int i, eccsize = chip->ecc.size; | |
1319 | int eccbytes = chip->ecc.bytes; | |
1320 | int eccsteps = chip->ecc.steps; | |
1321 | uint8_t *p = buf; | |
1322 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1323 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1324 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
3f91e94f | 1325 | unsigned int max_bitflips = 0; |
6e0cb135 SN |
1326 | |
1327 | /* Read the OOB area first */ | |
1328 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1329 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1330 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1331 | ||
1332 | for (i = 0; i < chip->ecc.total; i++) | |
1333 | ecc_code[i] = chip->oob_poi[eccpos[i]]; | |
1334 | ||
1335 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1336 | int stat; | |
1337 | ||
1338 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1339 | chip->read_buf(mtd, p, eccsize); | |
1340 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1341 | ||
1342 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
3f91e94f | 1343 | if (stat < 0) { |
6e0cb135 | 1344 | mtd->ecc_stats.failed++; |
3f91e94f | 1345 | } else { |
6e0cb135 | 1346 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1347 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1348 | } | |
6e0cb135 | 1349 | } |
3f91e94f | 1350 | return max_bitflips; |
6e0cb135 SN |
1351 | } |
1352 | ||
f5bbdacc | 1353 | /** |
7854d3f7 | 1354 | * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read |
8b6e50c9 BN |
1355 | * @mtd: mtd info structure |
1356 | * @chip: nand chip info structure | |
1357 | * @buf: buffer to store read data | |
1fbb938d | 1358 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1359 | * @page: page number to read |
f5bbdacc | 1360 | * |
8b6e50c9 BN |
1361 | * The hw generator calculates the error syndrome automatically. Therefore we |
1362 | * need a special oob layout and handling. | |
f5bbdacc TG |
1363 | */ |
1364 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1365 | uint8_t *buf, int oob_required, int page) |
f5bbdacc TG |
1366 | { |
1367 | int i, eccsize = chip->ecc.size; | |
1368 | int eccbytes = chip->ecc.bytes; | |
1369 | int eccsteps = chip->ecc.steps; | |
1370 | uint8_t *p = buf; | |
f75e5097 | 1371 | uint8_t *oob = chip->oob_poi; |
3f91e94f | 1372 | unsigned int max_bitflips = 0; |
1da177e4 | 1373 | |
f5bbdacc TG |
1374 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1375 | int stat; | |
61b03bd7 | 1376 | |
f5bbdacc TG |
1377 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1378 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1379 | |
f5bbdacc TG |
1380 | if (chip->ecc.prepad) { |
1381 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1382 | oob += chip->ecc.prepad; | |
1383 | } | |
1da177e4 | 1384 | |
f5bbdacc TG |
1385 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1386 | chip->read_buf(mtd, oob, eccbytes); | |
1387 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1388 | |
3f91e94f | 1389 | if (stat < 0) { |
f5bbdacc | 1390 | mtd->ecc_stats.failed++; |
3f91e94f | 1391 | } else { |
f5bbdacc | 1392 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1393 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1394 | } | |
61b03bd7 | 1395 | |
f5bbdacc | 1396 | oob += eccbytes; |
1da177e4 | 1397 | |
f5bbdacc TG |
1398 | if (chip->ecc.postpad) { |
1399 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1400 | oob += chip->ecc.postpad; | |
61b03bd7 | 1401 | } |
f5bbdacc | 1402 | } |
1da177e4 | 1403 | |
f5bbdacc | 1404 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1405 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1406 | if (i) |
1407 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1408 | |
3f91e94f | 1409 | return max_bitflips; |
f5bbdacc | 1410 | } |
1da177e4 | 1411 | |
f5bbdacc | 1412 | /** |
7854d3f7 | 1413 | * nand_transfer_oob - [INTERN] Transfer oob to client buffer |
8b6e50c9 BN |
1414 | * @chip: nand chip structure |
1415 | * @oob: oob destination address | |
1416 | * @ops: oob ops structure | |
1417 | * @len: size of oob to transfer | |
8593fbc6 TG |
1418 | */ |
1419 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
7014568b | 1420 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1421 | { |
f8ac0414 | 1422 | switch (ops->mode) { |
8593fbc6 | 1423 | |
0612b9dd BN |
1424 | case MTD_OPS_PLACE_OOB: |
1425 | case MTD_OPS_RAW: | |
8593fbc6 TG |
1426 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); |
1427 | return oob + len; | |
1428 | ||
0612b9dd | 1429 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 1430 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
1431 | uint32_t boffs = 0, roffs = ops->ooboffs; |
1432 | size_t bytes = 0; | |
8593fbc6 | 1433 | |
f8ac0414 | 1434 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 1435 | /* Read request not from offset 0? */ |
7bc3312b TG |
1436 | if (unlikely(roffs)) { |
1437 | if (roffs >= free->length) { | |
1438 | roffs -= free->length; | |
1439 | continue; | |
1440 | } | |
1441 | boffs = free->offset + roffs; | |
1442 | bytes = min_t(size_t, len, | |
1443 | (free->length - roffs)); | |
1444 | roffs = 0; | |
1445 | } else { | |
1446 | bytes = min_t(size_t, len, free->length); | |
1447 | boffs = free->offset; | |
1448 | } | |
1449 | memcpy(oob, chip->oob_poi + boffs, bytes); | |
8593fbc6 TG |
1450 | oob += bytes; |
1451 | } | |
1452 | return oob; | |
1453 | } | |
1454 | default: | |
1455 | BUG(); | |
1456 | } | |
1457 | return NULL; | |
1458 | } | |
1459 | ||
ba84fb59 BN |
1460 | /** |
1461 | * nand_setup_read_retry - [INTERN] Set the READ RETRY mode | |
1462 | * @mtd: MTD device structure | |
1463 | * @retry_mode: the retry mode to use | |
1464 | * | |
1465 | * Some vendors supply a special command to shift the Vt threshold, to be used | |
1466 | * when there are too many bitflips in a page (i.e., ECC error). After setting | |
1467 | * a new threshold, the host should retry reading the page. | |
1468 | */ | |
1469 | static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) | |
1470 | { | |
1471 | struct nand_chip *chip = mtd->priv; | |
1472 | ||
1473 | pr_debug("setting READ RETRY mode %d\n", retry_mode); | |
1474 | ||
1475 | if (retry_mode >= chip->read_retries) | |
1476 | return -EINVAL; | |
1477 | ||
1478 | if (!chip->setup_read_retry) | |
1479 | return -EOPNOTSUPP; | |
1480 | ||
1481 | return chip->setup_read_retry(mtd, retry_mode); | |
1482 | } | |
1483 | ||
8593fbc6 | 1484 | /** |
7854d3f7 | 1485 | * nand_do_read_ops - [INTERN] Read data with ECC |
8b6e50c9 BN |
1486 | * @mtd: MTD device structure |
1487 | * @from: offset to read from | |
1488 | * @ops: oob ops structure | |
f5bbdacc TG |
1489 | * |
1490 | * Internal function. Called with chip held. | |
1491 | */ | |
8593fbc6 TG |
1492 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1493 | struct mtd_oob_ops *ops) | |
f5bbdacc | 1494 | { |
e47f3db4 | 1495 | int chipnr, page, realpage, col, bytes, aligned, oob_required; |
f5bbdacc | 1496 | struct nand_chip *chip = mtd->priv; |
f5bbdacc | 1497 | int ret = 0; |
8593fbc6 | 1498 | uint32_t readlen = ops->len; |
7014568b | 1499 | uint32_t oobreadlen = ops->ooblen; |
0612b9dd | 1500 | uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ? |
9aca334e ML |
1501 | mtd->oobavail : mtd->oobsize; |
1502 | ||
8593fbc6 | 1503 | uint8_t *bufpoi, *oob, *buf; |
edbc4540 | 1504 | unsigned int max_bitflips = 0; |
ba84fb59 | 1505 | int retry_mode = 0; |
b72f3dfb | 1506 | bool ecc_fail = false; |
1da177e4 | 1507 | |
f5bbdacc TG |
1508 | chipnr = (int)(from >> chip->chip_shift); |
1509 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 1510 | |
f5bbdacc TG |
1511 | realpage = (int)(from >> chip->page_shift); |
1512 | page = realpage & chip->pagemask; | |
1da177e4 | 1513 | |
f5bbdacc | 1514 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 1515 | |
8593fbc6 TG |
1516 | buf = ops->datbuf; |
1517 | oob = ops->oobbuf; | |
e47f3db4 | 1518 | oob_required = oob ? 1 : 0; |
8593fbc6 | 1519 | |
f8ac0414 | 1520 | while (1) { |
b72f3dfb BN |
1521 | unsigned int ecc_failures = mtd->ecc_stats.failed; |
1522 | ||
f5bbdacc TG |
1523 | bytes = min(mtd->writesize - col, readlen); |
1524 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 1525 | |
8b6e50c9 | 1526 | /* Is the current page in the buffer? */ |
8593fbc6 | 1527 | if (realpage != chip->pagebuf || oob) { |
4bf63fcb | 1528 | bufpoi = aligned ? buf : chip->buffers->databuf; |
61b03bd7 | 1529 | |
ba84fb59 | 1530 | read_retry: |
c00a0991 | 1531 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); |
1da177e4 | 1532 | |
edbc4540 MD |
1533 | /* |
1534 | * Now read the page into the buffer. Absent an error, | |
1535 | * the read methods return max bitflips per ecc step. | |
1536 | */ | |
0612b9dd | 1537 | if (unlikely(ops->mode == MTD_OPS_RAW)) |
1fbb938d | 1538 | ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, |
e47f3db4 BN |
1539 | oob_required, |
1540 | page); | |
a5ff4f10 JW |
1541 | else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && |
1542 | !oob) | |
7351d3a5 | 1543 | ret = chip->ecc.read_subpage(mtd, chip, |
e004debd HS |
1544 | col, bytes, bufpoi, |
1545 | page); | |
956e944c | 1546 | else |
46a8cf2d | 1547 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
e47f3db4 | 1548 | oob_required, page); |
6d77b9d0 BN |
1549 | if (ret < 0) { |
1550 | if (!aligned) | |
1551 | /* Invalidate page cache */ | |
1552 | chip->pagebuf = -1; | |
1da177e4 | 1553 | break; |
6d77b9d0 | 1554 | } |
f5bbdacc | 1555 | |
edbc4540 MD |
1556 | max_bitflips = max_t(unsigned int, max_bitflips, ret); |
1557 | ||
f5bbdacc TG |
1558 | /* Transfer not aligned data */ |
1559 | if (!aligned) { | |
a5ff4f10 | 1560 | if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && |
b72f3dfb | 1561 | !(mtd->ecc_stats.failed - ecc_failures) && |
edbc4540 | 1562 | (ops->mode != MTD_OPS_RAW)) { |
3d459559 | 1563 | chip->pagebuf = realpage; |
edbc4540 MD |
1564 | chip->pagebuf_bitflips = ret; |
1565 | } else { | |
6d77b9d0 BN |
1566 | /* Invalidate page cache */ |
1567 | chip->pagebuf = -1; | |
edbc4540 | 1568 | } |
4bf63fcb | 1569 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1570 | } |
1571 | ||
8593fbc6 | 1572 | if (unlikely(oob)) { |
b64d39d8 ML |
1573 | int toread = min(oobreadlen, max_oobsize); |
1574 | ||
1575 | if (toread) { | |
1576 | oob = nand_transfer_oob(chip, | |
1577 | oob, ops, toread); | |
1578 | oobreadlen -= toread; | |
1579 | } | |
8593fbc6 | 1580 | } |
5bc7c33c BN |
1581 | |
1582 | if (chip->options & NAND_NEED_READRDY) { | |
1583 | /* Apply delay or wait for ready/busy pin */ | |
1584 | if (!chip->dev_ready) | |
1585 | udelay(chip->chip_delay); | |
1586 | else | |
1587 | nand_wait_ready(mtd); | |
1588 | } | |
b72f3dfb | 1589 | |
ba84fb59 | 1590 | if (mtd->ecc_stats.failed - ecc_failures) { |
28fa65e6 | 1591 | if (retry_mode + 1 < chip->read_retries) { |
ba84fb59 BN |
1592 | retry_mode++; |
1593 | ret = nand_setup_read_retry(mtd, | |
1594 | retry_mode); | |
1595 | if (ret < 0) | |
1596 | break; | |
1597 | ||
1598 | /* Reset failures; retry */ | |
1599 | mtd->ecc_stats.failed = ecc_failures; | |
1600 | goto read_retry; | |
1601 | } else { | |
1602 | /* No more retry modes; real failure */ | |
1603 | ecc_fail = true; | |
1604 | } | |
1605 | } | |
1606 | ||
1607 | buf += bytes; | |
8593fbc6 | 1608 | } else { |
4bf63fcb | 1609 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 | 1610 | buf += bytes; |
edbc4540 MD |
1611 | max_bitflips = max_t(unsigned int, max_bitflips, |
1612 | chip->pagebuf_bitflips); | |
8593fbc6 | 1613 | } |
1da177e4 | 1614 | |
f5bbdacc | 1615 | readlen -= bytes; |
61b03bd7 | 1616 | |
ba84fb59 BN |
1617 | /* Reset to retry mode 0 */ |
1618 | if (retry_mode) { | |
1619 | ret = nand_setup_read_retry(mtd, 0); | |
1620 | if (ret < 0) | |
1621 | break; | |
1622 | retry_mode = 0; | |
1623 | } | |
1624 | ||
f5bbdacc | 1625 | if (!readlen) |
61b03bd7 | 1626 | break; |
1da177e4 | 1627 | |
8b6e50c9 | 1628 | /* For subsequent reads align to page boundary */ |
1da177e4 LT |
1629 | col = 0; |
1630 | /* Increment page address */ | |
1631 | realpage++; | |
1632 | ||
ace4dfee | 1633 | page = realpage & chip->pagemask; |
1da177e4 LT |
1634 | /* Check, if we cross a chip boundary */ |
1635 | if (!page) { | |
1636 | chipnr++; | |
ace4dfee TG |
1637 | chip->select_chip(mtd, -1); |
1638 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1639 | } |
1da177e4 | 1640 | } |
b0bb6903 | 1641 | chip->select_chip(mtd, -1); |
1da177e4 | 1642 | |
8593fbc6 | 1643 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
1644 | if (oob) |
1645 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 1646 | |
3f91e94f | 1647 | if (ret < 0) |
f5bbdacc TG |
1648 | return ret; |
1649 | ||
b72f3dfb | 1650 | if (ecc_fail) |
9a1fcdfd TG |
1651 | return -EBADMSG; |
1652 | ||
edbc4540 | 1653 | return max_bitflips; |
f5bbdacc TG |
1654 | } |
1655 | ||
1656 | /** | |
25985edc | 1657 | * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc |
8b6e50c9 BN |
1658 | * @mtd: MTD device structure |
1659 | * @from: offset to read from | |
1660 | * @len: number of bytes to read | |
1661 | * @retlen: pointer to variable to store the number of read bytes | |
1662 | * @buf: the databuffer to put data | |
f5bbdacc | 1663 | * |
8b6e50c9 | 1664 | * Get hold of the chip and call nand_do_read. |
f5bbdacc TG |
1665 | */ |
1666 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1667 | size_t *retlen, uint8_t *buf) | |
1668 | { | |
4a89ff88 | 1669 | struct mtd_oob_ops ops; |
f5bbdacc TG |
1670 | int ret; |
1671 | ||
6a8214aa | 1672 | nand_get_device(mtd, FL_READING); |
4a89ff88 BN |
1673 | ops.len = len; |
1674 | ops.datbuf = buf; | |
1675 | ops.oobbuf = NULL; | |
11041ae6 | 1676 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 1677 | ret = nand_do_read_ops(mtd, from, &ops); |
4a89ff88 | 1678 | *retlen = ops.retlen; |
f5bbdacc | 1679 | nand_release_device(mtd); |
f5bbdacc | 1680 | return ret; |
1da177e4 LT |
1681 | } |
1682 | ||
7bc3312b | 1683 | /** |
7854d3f7 | 1684 | * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function |
8b6e50c9 BN |
1685 | * @mtd: mtd info structure |
1686 | * @chip: nand chip info structure | |
1687 | * @page: page number to read | |
7bc3312b TG |
1688 | */ |
1689 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1690 | int page) |
7bc3312b | 1691 | { |
5c2ffb11 | 1692 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); |
7bc3312b | 1693 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
5c2ffb11 | 1694 | return 0; |
7bc3312b TG |
1695 | } |
1696 | ||
1697 | /** | |
7854d3f7 | 1698 | * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC |
7bc3312b | 1699 | * with syndromes |
8b6e50c9 BN |
1700 | * @mtd: mtd info structure |
1701 | * @chip: nand chip info structure | |
1702 | * @page: page number to read | |
7bc3312b TG |
1703 | */ |
1704 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1705 | int page) |
7bc3312b TG |
1706 | { |
1707 | uint8_t *buf = chip->oob_poi; | |
1708 | int length = mtd->oobsize; | |
1709 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1710 | int eccsize = chip->ecc.size; | |
1711 | uint8_t *bufpoi = buf; | |
1712 | int i, toread, sndrnd = 0, pos; | |
1713 | ||
1714 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
1715 | for (i = 0; i < chip->ecc.steps; i++) { | |
1716 | if (sndrnd) { | |
1717 | pos = eccsize + i * (eccsize + chunk); | |
1718 | if (mtd->writesize > 512) | |
1719 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
1720 | else | |
1721 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
1722 | } else | |
1723 | sndrnd = 1; | |
1724 | toread = min_t(int, length, chunk); | |
1725 | chip->read_buf(mtd, bufpoi, toread); | |
1726 | bufpoi += toread; | |
1727 | length -= toread; | |
1728 | } | |
1729 | if (length > 0) | |
1730 | chip->read_buf(mtd, bufpoi, length); | |
1731 | ||
5c2ffb11 | 1732 | return 0; |
7bc3312b TG |
1733 | } |
1734 | ||
1735 | /** | |
7854d3f7 | 1736 | * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function |
8b6e50c9 BN |
1737 | * @mtd: mtd info structure |
1738 | * @chip: nand chip info structure | |
1739 | * @page: page number to write | |
7bc3312b TG |
1740 | */ |
1741 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1742 | int page) | |
1743 | { | |
1744 | int status = 0; | |
1745 | const uint8_t *buf = chip->oob_poi; | |
1746 | int length = mtd->oobsize; | |
1747 | ||
1748 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
1749 | chip->write_buf(mtd, buf, length); | |
1750 | /* Send command to program the OOB data */ | |
1751 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1752 | ||
1753 | status = chip->waitfunc(mtd, chip); | |
1754 | ||
0d420f9d | 1755 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b TG |
1756 | } |
1757 | ||
1758 | /** | |
7854d3f7 | 1759 | * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC |
8b6e50c9 BN |
1760 | * with syndrome - only for large page flash |
1761 | * @mtd: mtd info structure | |
1762 | * @chip: nand chip info structure | |
1763 | * @page: page number to write | |
7bc3312b TG |
1764 | */ |
1765 | static int nand_write_oob_syndrome(struct mtd_info *mtd, | |
1766 | struct nand_chip *chip, int page) | |
1767 | { | |
1768 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1769 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
1770 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
1771 | const uint8_t *bufpoi = chip->oob_poi; | |
1772 | ||
1773 | /* | |
1774 | * data-ecc-data-ecc ... ecc-oob | |
1775 | * or | |
1776 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
1777 | */ | |
1778 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
1779 | pos = steps * (eccsize + chunk); | |
1780 | steps = 0; | |
1781 | } else | |
8b0036ee | 1782 | pos = eccsize; |
7bc3312b TG |
1783 | |
1784 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
1785 | for (i = 0; i < steps; i++) { | |
1786 | if (sndcmd) { | |
1787 | if (mtd->writesize <= 512) { | |
1788 | uint32_t fill = 0xFFFFFFFF; | |
1789 | ||
1790 | len = eccsize; | |
1791 | while (len > 0) { | |
1792 | int num = min_t(int, len, 4); | |
1793 | chip->write_buf(mtd, (uint8_t *)&fill, | |
1794 | num); | |
1795 | len -= num; | |
1796 | } | |
1797 | } else { | |
1798 | pos = eccsize + i * (eccsize + chunk); | |
1799 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
1800 | } | |
1801 | } else | |
1802 | sndcmd = 1; | |
1803 | len = min_t(int, length, chunk); | |
1804 | chip->write_buf(mtd, bufpoi, len); | |
1805 | bufpoi += len; | |
1806 | length -= len; | |
1807 | } | |
1808 | if (length > 0) | |
1809 | chip->write_buf(mtd, bufpoi, length); | |
1810 | ||
1811 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1812 | status = chip->waitfunc(mtd, chip); | |
1813 | ||
1814 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
1815 | } | |
1816 | ||
1da177e4 | 1817 | /** |
7854d3f7 | 1818 | * nand_do_read_oob - [INTERN] NAND read out-of-band |
8b6e50c9 BN |
1819 | * @mtd: MTD device structure |
1820 | * @from: offset to read from | |
1821 | * @ops: oob operations description structure | |
1da177e4 | 1822 | * |
8b6e50c9 | 1823 | * NAND read out-of-band data from the spare area. |
1da177e4 | 1824 | */ |
8593fbc6 TG |
1825 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
1826 | struct mtd_oob_ops *ops) | |
1da177e4 | 1827 | { |
c00a0991 | 1828 | int page, realpage, chipnr; |
ace4dfee | 1829 | struct nand_chip *chip = mtd->priv; |
041e4575 | 1830 | struct mtd_ecc_stats stats; |
7014568b VW |
1831 | int readlen = ops->ooblen; |
1832 | int len; | |
7bc3312b | 1833 | uint8_t *buf = ops->oobbuf; |
1951f2f7 | 1834 | int ret = 0; |
61b03bd7 | 1835 | |
289c0522 | 1836 | pr_debug("%s: from = 0x%08Lx, len = %i\n", |
20d8e248 | 1837 | __func__, (unsigned long long)from, readlen); |
1da177e4 | 1838 | |
041e4575 BN |
1839 | stats = mtd->ecc_stats; |
1840 | ||
0612b9dd | 1841 | if (ops->mode == MTD_OPS_AUTO_OOB) |
7014568b | 1842 | len = chip->ecc.layout->oobavail; |
03736155 AH |
1843 | else |
1844 | len = mtd->oobsize; | |
1845 | ||
1846 | if (unlikely(ops->ooboffs >= len)) { | |
289c0522 BN |
1847 | pr_debug("%s: attempt to start read outside oob\n", |
1848 | __func__); | |
03736155 AH |
1849 | return -EINVAL; |
1850 | } | |
1851 | ||
1852 | /* Do not allow reads past end of device */ | |
1853 | if (unlikely(from >= mtd->size || | |
1854 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
1855 | (from >> chip->page_shift)) * len)) { | |
289c0522 BN |
1856 | pr_debug("%s: attempt to read beyond end of device\n", |
1857 | __func__); | |
03736155 AH |
1858 | return -EINVAL; |
1859 | } | |
7014568b | 1860 | |
7314e9e7 | 1861 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 1862 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1863 | |
7314e9e7 TG |
1864 | /* Shift to get page */ |
1865 | realpage = (int)(from >> chip->page_shift); | |
1866 | page = realpage & chip->pagemask; | |
1da177e4 | 1867 | |
f8ac0414 | 1868 | while (1) { |
0612b9dd | 1869 | if (ops->mode == MTD_OPS_RAW) |
1951f2f7 | 1870 | ret = chip->ecc.read_oob_raw(mtd, chip, page); |
c46f6483 | 1871 | else |
1951f2f7 SL |
1872 | ret = chip->ecc.read_oob(mtd, chip, page); |
1873 | ||
1874 | if (ret < 0) | |
1875 | break; | |
7014568b VW |
1876 | |
1877 | len = min(len, readlen); | |
1878 | buf = nand_transfer_oob(chip, buf, ops, len); | |
8593fbc6 | 1879 | |
5bc7c33c BN |
1880 | if (chip->options & NAND_NEED_READRDY) { |
1881 | /* Apply delay or wait for ready/busy pin */ | |
1882 | if (!chip->dev_ready) | |
1883 | udelay(chip->chip_delay); | |
1884 | else | |
1885 | nand_wait_ready(mtd); | |
1886 | } | |
1887 | ||
7014568b | 1888 | readlen -= len; |
0d420f9d SZ |
1889 | if (!readlen) |
1890 | break; | |
1891 | ||
7314e9e7 TG |
1892 | /* Increment page address */ |
1893 | realpage++; | |
1894 | ||
1895 | page = realpage & chip->pagemask; | |
1896 | /* Check, if we cross a chip boundary */ | |
1897 | if (!page) { | |
1898 | chipnr++; | |
1899 | chip->select_chip(mtd, -1); | |
1900 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
1901 | } |
1902 | } | |
b0bb6903 | 1903 | chip->select_chip(mtd, -1); |
1da177e4 | 1904 | |
1951f2f7 SL |
1905 | ops->oobretlen = ops->ooblen - readlen; |
1906 | ||
1907 | if (ret < 0) | |
1908 | return ret; | |
041e4575 BN |
1909 | |
1910 | if (mtd->ecc_stats.failed - stats.failed) | |
1911 | return -EBADMSG; | |
1912 | ||
1913 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
1da177e4 LT |
1914 | } |
1915 | ||
1916 | /** | |
8593fbc6 | 1917 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
8b6e50c9 BN |
1918 | * @mtd: MTD device structure |
1919 | * @from: offset to read from | |
1920 | * @ops: oob operation description structure | |
1da177e4 | 1921 | * |
8b6e50c9 | 1922 | * NAND read data and/or out-of-band data. |
1da177e4 | 1923 | */ |
8593fbc6 TG |
1924 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
1925 | struct mtd_oob_ops *ops) | |
1da177e4 | 1926 | { |
8593fbc6 TG |
1927 | int ret = -ENOTSUPP; |
1928 | ||
1929 | ops->retlen = 0; | |
1da177e4 LT |
1930 | |
1931 | /* Do not allow reads past end of device */ | |
7014568b | 1932 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
289c0522 BN |
1933 | pr_debug("%s: attempt to read beyond end of device\n", |
1934 | __func__); | |
1da177e4 LT |
1935 | return -EINVAL; |
1936 | } | |
1937 | ||
6a8214aa | 1938 | nand_get_device(mtd, FL_READING); |
1da177e4 | 1939 | |
f8ac0414 | 1940 | switch (ops->mode) { |
0612b9dd BN |
1941 | case MTD_OPS_PLACE_OOB: |
1942 | case MTD_OPS_AUTO_OOB: | |
1943 | case MTD_OPS_RAW: | |
8593fbc6 | 1944 | break; |
1da177e4 | 1945 | |
8593fbc6 TG |
1946 | default: |
1947 | goto out; | |
1948 | } | |
1da177e4 | 1949 | |
8593fbc6 TG |
1950 | if (!ops->datbuf) |
1951 | ret = nand_do_read_oob(mtd, from, ops); | |
1952 | else | |
1953 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 1954 | |
7351d3a5 | 1955 | out: |
8593fbc6 TG |
1956 | nand_release_device(mtd); |
1957 | return ret; | |
1958 | } | |
61b03bd7 | 1959 | |
1da177e4 | 1960 | |
8593fbc6 | 1961 | /** |
7854d3f7 | 1962 | * nand_write_page_raw - [INTERN] raw page write function |
8b6e50c9 BN |
1963 | * @mtd: mtd info structure |
1964 | * @chip: nand chip info structure | |
1965 | * @buf: data buffer | |
1fbb938d | 1966 | * @oob_required: must write chip->oob_poi to OOB |
52ff49df | 1967 | * |
7854d3f7 | 1968 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 | 1969 | */ |
fdbad98d | 1970 | static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1971 | const uint8_t *buf, int oob_required) |
8593fbc6 TG |
1972 | { |
1973 | chip->write_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1974 | if (oob_required) |
1975 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
1976 | |
1977 | return 0; | |
1da177e4 LT |
1978 | } |
1979 | ||
52ff49df | 1980 | /** |
7854d3f7 | 1981 | * nand_write_page_raw_syndrome - [INTERN] raw page write function |
8b6e50c9 BN |
1982 | * @mtd: mtd info structure |
1983 | * @chip: nand chip info structure | |
1984 | * @buf: data buffer | |
1fbb938d | 1985 | * @oob_required: must write chip->oob_poi to OOB |
52ff49df DB |
1986 | * |
1987 | * We need a special oob layout and handling even when ECC isn't checked. | |
1988 | */ | |
fdbad98d | 1989 | static int nand_write_page_raw_syndrome(struct mtd_info *mtd, |
7351d3a5 | 1990 | struct nand_chip *chip, |
1fbb938d | 1991 | const uint8_t *buf, int oob_required) |
52ff49df DB |
1992 | { |
1993 | int eccsize = chip->ecc.size; | |
1994 | int eccbytes = chip->ecc.bytes; | |
1995 | uint8_t *oob = chip->oob_poi; | |
1996 | int steps, size; | |
1997 | ||
1998 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1999 | chip->write_buf(mtd, buf, eccsize); | |
2000 | buf += eccsize; | |
2001 | ||
2002 | if (chip->ecc.prepad) { | |
2003 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2004 | oob += chip->ecc.prepad; | |
2005 | } | |
2006 | ||
60c3bc1f | 2007 | chip->write_buf(mtd, oob, eccbytes); |
52ff49df DB |
2008 | oob += eccbytes; |
2009 | ||
2010 | if (chip->ecc.postpad) { | |
2011 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2012 | oob += chip->ecc.postpad; | |
2013 | } | |
2014 | } | |
2015 | ||
2016 | size = mtd->oobsize - (oob - chip->oob_poi); | |
2017 | if (size) | |
2018 | chip->write_buf(mtd, oob, size); | |
fdbad98d JW |
2019 | |
2020 | return 0; | |
52ff49df | 2021 | } |
9223a456 | 2022 | /** |
7854d3f7 | 2023 | * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function |
8b6e50c9 BN |
2024 | * @mtd: mtd info structure |
2025 | * @chip: nand chip info structure | |
2026 | * @buf: data buffer | |
1fbb938d | 2027 | * @oob_required: must write chip->oob_poi to OOB |
9223a456 | 2028 | */ |
fdbad98d | 2029 | static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 2030 | const uint8_t *buf, int oob_required) |
9223a456 | 2031 | { |
f75e5097 TG |
2032 | int i, eccsize = chip->ecc.size; |
2033 | int eccbytes = chip->ecc.bytes; | |
2034 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2035 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2036 | const uint8_t *p = buf; |
8b099a39 | 2037 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 2038 | |
7854d3f7 | 2039 | /* Software ECC calculation */ |
8593fbc6 TG |
2040 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
2041 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 2042 | |
8593fbc6 TG |
2043 | for (i = 0; i < chip->ecc.total; i++) |
2044 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 2045 | |
fdbad98d | 2046 | return chip->ecc.write_page_raw(mtd, chip, buf, 1); |
f75e5097 | 2047 | } |
9223a456 | 2048 | |
f75e5097 | 2049 | /** |
7854d3f7 | 2050 | * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function |
8b6e50c9 BN |
2051 | * @mtd: mtd info structure |
2052 | * @chip: nand chip info structure | |
2053 | * @buf: data buffer | |
1fbb938d | 2054 | * @oob_required: must write chip->oob_poi to OOB |
f75e5097 | 2055 | */ |
fdbad98d | 2056 | static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 2057 | const uint8_t *buf, int oob_required) |
f75e5097 TG |
2058 | { |
2059 | int i, eccsize = chip->ecc.size; | |
2060 | int eccbytes = chip->ecc.bytes; | |
2061 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2062 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2063 | const uint8_t *p = buf; |
8b099a39 | 2064 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 2065 | |
f75e5097 TG |
2066 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
2067 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 2068 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 2069 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
2070 | } |
2071 | ||
f75e5097 TG |
2072 | for (i = 0; i < chip->ecc.total; i++) |
2073 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
2074 | ||
2075 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
2076 | |
2077 | return 0; | |
9223a456 TG |
2078 | } |
2079 | ||
837a6ba4 GP |
2080 | |
2081 | /** | |
2082 | * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write | |
2083 | * @mtd: mtd info structure | |
2084 | * @chip: nand chip info structure | |
d6a95080 | 2085 | * @offset: column address of subpage within the page |
837a6ba4 | 2086 | * @data_len: data length |
d6a95080 | 2087 | * @buf: data buffer |
837a6ba4 GP |
2088 | * @oob_required: must write chip->oob_poi to OOB |
2089 | */ | |
2090 | static int nand_write_subpage_hwecc(struct mtd_info *mtd, | |
2091 | struct nand_chip *chip, uint32_t offset, | |
d6a95080 | 2092 | uint32_t data_len, const uint8_t *buf, |
837a6ba4 GP |
2093 | int oob_required) |
2094 | { | |
2095 | uint8_t *oob_buf = chip->oob_poi; | |
2096 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
2097 | int ecc_size = chip->ecc.size; | |
2098 | int ecc_bytes = chip->ecc.bytes; | |
2099 | int ecc_steps = chip->ecc.steps; | |
2100 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
2101 | uint32_t start_step = offset / ecc_size; | |
2102 | uint32_t end_step = (offset + data_len - 1) / ecc_size; | |
2103 | int oob_bytes = mtd->oobsize / ecc_steps; | |
2104 | int step, i; | |
2105 | ||
2106 | for (step = 0; step < ecc_steps; step++) { | |
2107 | /* configure controller for WRITE access */ | |
2108 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
2109 | ||
2110 | /* write data (untouched subpages already masked by 0xFF) */ | |
d6a95080 | 2111 | chip->write_buf(mtd, buf, ecc_size); |
837a6ba4 GP |
2112 | |
2113 | /* mask ECC of un-touched subpages by padding 0xFF */ | |
2114 | if ((step < start_step) || (step > end_step)) | |
2115 | memset(ecc_calc, 0xff, ecc_bytes); | |
2116 | else | |
d6a95080 | 2117 | chip->ecc.calculate(mtd, buf, ecc_calc); |
837a6ba4 GP |
2118 | |
2119 | /* mask OOB of un-touched subpages by padding 0xFF */ | |
2120 | /* if oob_required, preserve OOB metadata of written subpage */ | |
2121 | if (!oob_required || (step < start_step) || (step > end_step)) | |
2122 | memset(oob_buf, 0xff, oob_bytes); | |
2123 | ||
d6a95080 | 2124 | buf += ecc_size; |
837a6ba4 GP |
2125 | ecc_calc += ecc_bytes; |
2126 | oob_buf += oob_bytes; | |
2127 | } | |
2128 | ||
2129 | /* copy calculated ECC for whole page to chip->buffer->oob */ | |
2130 | /* this include masked-value(0xFF) for unwritten subpages */ | |
2131 | ecc_calc = chip->buffers->ecccalc; | |
2132 | for (i = 0; i < chip->ecc.total; i++) | |
2133 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
2134 | ||
2135 | /* write OOB buffer to NAND device */ | |
2136 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
2137 | ||
2138 | return 0; | |
2139 | } | |
2140 | ||
2141 | ||
61b03bd7 | 2142 | /** |
7854d3f7 | 2143 | * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write |
8b6e50c9 BN |
2144 | * @mtd: mtd info structure |
2145 | * @chip: nand chip info structure | |
2146 | * @buf: data buffer | |
1fbb938d | 2147 | * @oob_required: must write chip->oob_poi to OOB |
1da177e4 | 2148 | * |
8b6e50c9 BN |
2149 | * The hw generator calculates the error syndrome automatically. Therefore we |
2150 | * need a special oob layout and handling. | |
f75e5097 | 2151 | */ |
fdbad98d | 2152 | static int nand_write_page_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
2153 | struct nand_chip *chip, |
2154 | const uint8_t *buf, int oob_required) | |
1da177e4 | 2155 | { |
f75e5097 TG |
2156 | int i, eccsize = chip->ecc.size; |
2157 | int eccbytes = chip->ecc.bytes; | |
2158 | int eccsteps = chip->ecc.steps; | |
2159 | const uint8_t *p = buf; | |
2160 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 2161 | |
f75e5097 | 2162 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 2163 | |
f75e5097 TG |
2164 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
2165 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 2166 | |
f75e5097 TG |
2167 | if (chip->ecc.prepad) { |
2168 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2169 | oob += chip->ecc.prepad; | |
2170 | } | |
2171 | ||
2172 | chip->ecc.calculate(mtd, p, oob); | |
2173 | chip->write_buf(mtd, oob, eccbytes); | |
2174 | oob += eccbytes; | |
2175 | ||
2176 | if (chip->ecc.postpad) { | |
2177 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2178 | oob += chip->ecc.postpad; | |
1da177e4 | 2179 | } |
1da177e4 | 2180 | } |
f75e5097 TG |
2181 | |
2182 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2183 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2184 | if (i) |
2185 | chip->write_buf(mtd, oob, i); | |
fdbad98d JW |
2186 | |
2187 | return 0; | |
f75e5097 TG |
2188 | } |
2189 | ||
2190 | /** | |
956e944c | 2191 | * nand_write_page - [REPLACEABLE] write one page |
8b6e50c9 BN |
2192 | * @mtd: MTD device structure |
2193 | * @chip: NAND chip descriptor | |
837a6ba4 GP |
2194 | * @offset: address offset within the page |
2195 | * @data_len: length of actual data to be written | |
8b6e50c9 | 2196 | * @buf: the data to write |
1fbb938d | 2197 | * @oob_required: must write chip->oob_poi to OOB |
8b6e50c9 BN |
2198 | * @page: page number to write |
2199 | * @cached: cached programming | |
2200 | * @raw: use _raw version of write_page | |
f75e5097 TG |
2201 | */ |
2202 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
837a6ba4 GP |
2203 | uint32_t offset, int data_len, const uint8_t *buf, |
2204 | int oob_required, int page, int cached, int raw) | |
f75e5097 | 2205 | { |
837a6ba4 GP |
2206 | int status, subpage; |
2207 | ||
2208 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && | |
2209 | chip->ecc.write_subpage) | |
2210 | subpage = offset || (data_len < mtd->writesize); | |
2211 | else | |
2212 | subpage = 0; | |
f75e5097 TG |
2213 | |
2214 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
2215 | ||
956e944c | 2216 | if (unlikely(raw)) |
837a6ba4 GP |
2217 | status = chip->ecc.write_page_raw(mtd, chip, buf, |
2218 | oob_required); | |
2219 | else if (subpage) | |
2220 | status = chip->ecc.write_subpage(mtd, chip, offset, data_len, | |
2221 | buf, oob_required); | |
956e944c | 2222 | else |
fdbad98d JW |
2223 | status = chip->ecc.write_page(mtd, chip, buf, oob_required); |
2224 | ||
2225 | if (status < 0) | |
2226 | return status; | |
f75e5097 TG |
2227 | |
2228 | /* | |
7854d3f7 | 2229 | * Cached progamming disabled for now. Not sure if it's worth the |
8b6e50c9 | 2230 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s). |
f75e5097 TG |
2231 | */ |
2232 | cached = 0; | |
2233 | ||
3239a6cd | 2234 | if (!cached || !NAND_HAS_CACHEPROG(chip)) { |
f75e5097 TG |
2235 | |
2236 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 2237 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2238 | /* |
2239 | * See if operation failed and additional status checks are | |
8b6e50c9 | 2240 | * available. |
f75e5097 TG |
2241 | */ |
2242 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2243 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
2244 | page); | |
2245 | ||
2246 | if (status & NAND_STATUS_FAIL) | |
2247 | return -EIO; | |
2248 | } else { | |
2249 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 2250 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2251 | } |
2252 | ||
f75e5097 | 2253 | return 0; |
1da177e4 LT |
2254 | } |
2255 | ||
8593fbc6 | 2256 | /** |
7854d3f7 | 2257 | * nand_fill_oob - [INTERN] Transfer client buffer to oob |
f722013e | 2258 | * @mtd: MTD device structure |
8b6e50c9 BN |
2259 | * @oob: oob data buffer |
2260 | * @len: oob data write length | |
2261 | * @ops: oob ops structure | |
8593fbc6 | 2262 | */ |
f722013e TAA |
2263 | static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, |
2264 | struct mtd_oob_ops *ops) | |
8593fbc6 | 2265 | { |
f722013e TAA |
2266 | struct nand_chip *chip = mtd->priv; |
2267 | ||
2268 | /* | |
2269 | * Initialise to all 0xFF, to avoid the possibility of left over OOB | |
2270 | * data from a previous OOB read. | |
2271 | */ | |
2272 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
2273 | ||
f8ac0414 | 2274 | switch (ops->mode) { |
8593fbc6 | 2275 | |
0612b9dd BN |
2276 | case MTD_OPS_PLACE_OOB: |
2277 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2278 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); |
2279 | return oob + len; | |
2280 | ||
0612b9dd | 2281 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 2282 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
2283 | uint32_t boffs = 0, woffs = ops->ooboffs; |
2284 | size_t bytes = 0; | |
8593fbc6 | 2285 | |
f8ac0414 | 2286 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 2287 | /* Write request not from offset 0? */ |
7bc3312b TG |
2288 | if (unlikely(woffs)) { |
2289 | if (woffs >= free->length) { | |
2290 | woffs -= free->length; | |
2291 | continue; | |
2292 | } | |
2293 | boffs = free->offset + woffs; | |
2294 | bytes = min_t(size_t, len, | |
2295 | (free->length - woffs)); | |
2296 | woffs = 0; | |
2297 | } else { | |
2298 | bytes = min_t(size_t, len, free->length); | |
2299 | boffs = free->offset; | |
2300 | } | |
8b0036ee | 2301 | memcpy(chip->oob_poi + boffs, oob, bytes); |
8593fbc6 TG |
2302 | oob += bytes; |
2303 | } | |
2304 | return oob; | |
2305 | } | |
2306 | default: | |
2307 | BUG(); | |
2308 | } | |
2309 | return NULL; | |
2310 | } | |
2311 | ||
f8ac0414 | 2312 | #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) |
1da177e4 LT |
2313 | |
2314 | /** | |
7854d3f7 | 2315 | * nand_do_write_ops - [INTERN] NAND write with ECC |
8b6e50c9 BN |
2316 | * @mtd: MTD device structure |
2317 | * @to: offset to write to | |
2318 | * @ops: oob operations description structure | |
1da177e4 | 2319 | * |
8b6e50c9 | 2320 | * NAND write with ECC. |
1da177e4 | 2321 | */ |
8593fbc6 TG |
2322 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2323 | struct mtd_oob_ops *ops) | |
1da177e4 | 2324 | { |
29072b96 | 2325 | int chipnr, realpage, page, blockmask, column; |
ace4dfee | 2326 | struct nand_chip *chip = mtd->priv; |
8593fbc6 | 2327 | uint32_t writelen = ops->len; |
782ce79a ML |
2328 | |
2329 | uint32_t oobwritelen = ops->ooblen; | |
0612b9dd | 2330 | uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ? |
782ce79a ML |
2331 | mtd->oobavail : mtd->oobsize; |
2332 | ||
8593fbc6 TG |
2333 | uint8_t *oob = ops->oobbuf; |
2334 | uint8_t *buf = ops->datbuf; | |
837a6ba4 | 2335 | int ret; |
e47f3db4 | 2336 | int oob_required = oob ? 1 : 0; |
1da177e4 | 2337 | |
8593fbc6 | 2338 | ops->retlen = 0; |
29072b96 TG |
2339 | if (!writelen) |
2340 | return 0; | |
1da177e4 | 2341 | |
8b6e50c9 | 2342 | /* Reject writes, which are not page aligned */ |
8593fbc6 | 2343 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
d0370219 BN |
2344 | pr_notice("%s: attempt to write non page aligned data\n", |
2345 | __func__); | |
1da177e4 LT |
2346 | return -EINVAL; |
2347 | } | |
2348 | ||
29072b96 | 2349 | column = to & (mtd->writesize - 1); |
1da177e4 | 2350 | |
6a930961 TG |
2351 | chipnr = (int)(to >> chip->chip_shift); |
2352 | chip->select_chip(mtd, chipnr); | |
2353 | ||
1da177e4 | 2354 | /* Check, if it is write protected */ |
b0bb6903 HS |
2355 | if (nand_check_wp(mtd)) { |
2356 | ret = -EIO; | |
2357 | goto err_out; | |
2358 | } | |
1da177e4 | 2359 | |
f75e5097 TG |
2360 | realpage = (int)(to >> chip->page_shift); |
2361 | page = realpage & chip->pagemask; | |
2362 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
2363 | ||
2364 | /* Invalidate the page cache, when we write to the cached page */ | |
2365 | if (to <= (chip->pagebuf << chip->page_shift) && | |
8593fbc6 | 2366 | (chip->pagebuf << chip->page_shift) < (to + ops->len)) |
ace4dfee | 2367 | chip->pagebuf = -1; |
61b03bd7 | 2368 | |
782ce79a | 2369 | /* Don't allow multipage oob writes with offset */ |
b0bb6903 HS |
2370 | if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { |
2371 | ret = -EINVAL; | |
2372 | goto err_out; | |
2373 | } | |
782ce79a | 2374 | |
f8ac0414 | 2375 | while (1) { |
29072b96 | 2376 | int bytes = mtd->writesize; |
f75e5097 | 2377 | int cached = writelen > bytes && page != blockmask; |
29072b96 TG |
2378 | uint8_t *wbuf = buf; |
2379 | ||
8b6e50c9 | 2380 | /* Partial page write? */ |
29072b96 TG |
2381 | if (unlikely(column || writelen < (mtd->writesize - 1))) { |
2382 | cached = 0; | |
2383 | bytes = min_t(int, bytes - column, (int) writelen); | |
2384 | chip->pagebuf = -1; | |
2385 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2386 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2387 | wbuf = chip->buffers->databuf; | |
2388 | } | |
1da177e4 | 2389 | |
782ce79a ML |
2390 | if (unlikely(oob)) { |
2391 | size_t len = min(oobwritelen, oobmaxlen); | |
f722013e | 2392 | oob = nand_fill_oob(mtd, oob, len, ops); |
782ce79a | 2393 | oobwritelen -= len; |
f722013e TAA |
2394 | } else { |
2395 | /* We still need to erase leftover OOB data */ | |
2396 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
782ce79a | 2397 | } |
837a6ba4 GP |
2398 | ret = chip->write_page(mtd, chip, column, bytes, wbuf, |
2399 | oob_required, page, cached, | |
2400 | (ops->mode == MTD_OPS_RAW)); | |
f75e5097 TG |
2401 | if (ret) |
2402 | break; | |
2403 | ||
2404 | writelen -= bytes; | |
2405 | if (!writelen) | |
2406 | break; | |
2407 | ||
29072b96 | 2408 | column = 0; |
f75e5097 TG |
2409 | buf += bytes; |
2410 | realpage++; | |
2411 | ||
2412 | page = realpage & chip->pagemask; | |
2413 | /* Check, if we cross a chip boundary */ | |
2414 | if (!page) { | |
2415 | chipnr++; | |
2416 | chip->select_chip(mtd, -1); | |
2417 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2418 | } |
2419 | } | |
8593fbc6 | 2420 | |
8593fbc6 | 2421 | ops->retlen = ops->len - writelen; |
7014568b VW |
2422 | if (unlikely(oob)) |
2423 | ops->oobretlen = ops->ooblen; | |
b0bb6903 HS |
2424 | |
2425 | err_out: | |
2426 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
2427 | return ret; |
2428 | } | |
2429 | ||
2af7c653 SK |
2430 | /** |
2431 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
8b6e50c9 BN |
2432 | * @mtd: MTD device structure |
2433 | * @to: offset to write to | |
2434 | * @len: number of bytes to write | |
2435 | * @retlen: pointer to variable to store the number of written bytes | |
2436 | * @buf: the data to write | |
2af7c653 SK |
2437 | * |
2438 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2439 | * may for example be called by mtdoops when writing an oops while in panic. | |
2440 | */ | |
2441 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2442 | size_t *retlen, const uint8_t *buf) | |
2443 | { | |
2444 | struct nand_chip *chip = mtd->priv; | |
4a89ff88 | 2445 | struct mtd_oob_ops ops; |
2af7c653 SK |
2446 | int ret; |
2447 | ||
8b6e50c9 | 2448 | /* Wait for the device to get ready */ |
2af7c653 SK |
2449 | panic_nand_wait(mtd, chip, 400); |
2450 | ||
8b6e50c9 | 2451 | /* Grab the device */ |
2af7c653 SK |
2452 | panic_nand_get_device(chip, mtd, FL_WRITING); |
2453 | ||
4a89ff88 BN |
2454 | ops.len = len; |
2455 | ops.datbuf = (uint8_t *)buf; | |
2456 | ops.oobbuf = NULL; | |
11041ae6 | 2457 | ops.mode = MTD_OPS_PLACE_OOB; |
2af7c653 | 2458 | |
4a89ff88 | 2459 | ret = nand_do_write_ops(mtd, to, &ops); |
2af7c653 | 2460 | |
4a89ff88 | 2461 | *retlen = ops.retlen; |
2af7c653 SK |
2462 | return ret; |
2463 | } | |
2464 | ||
f75e5097 | 2465 | /** |
8593fbc6 | 2466 | * nand_write - [MTD Interface] NAND write with ECC |
8b6e50c9 BN |
2467 | * @mtd: MTD device structure |
2468 | * @to: offset to write to | |
2469 | * @len: number of bytes to write | |
2470 | * @retlen: pointer to variable to store the number of written bytes | |
2471 | * @buf: the data to write | |
f75e5097 | 2472 | * |
8b6e50c9 | 2473 | * NAND write with ECC. |
f75e5097 | 2474 | */ |
8593fbc6 TG |
2475 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
2476 | size_t *retlen, const uint8_t *buf) | |
f75e5097 | 2477 | { |
4a89ff88 | 2478 | struct mtd_oob_ops ops; |
f75e5097 TG |
2479 | int ret; |
2480 | ||
6a8214aa | 2481 | nand_get_device(mtd, FL_WRITING); |
4a89ff88 BN |
2482 | ops.len = len; |
2483 | ops.datbuf = (uint8_t *)buf; | |
2484 | ops.oobbuf = NULL; | |
11041ae6 | 2485 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 2486 | ret = nand_do_write_ops(mtd, to, &ops); |
4a89ff88 | 2487 | *retlen = ops.retlen; |
f75e5097 | 2488 | nand_release_device(mtd); |
8593fbc6 | 2489 | return ret; |
f75e5097 | 2490 | } |
7314e9e7 | 2491 | |
1da177e4 | 2492 | /** |
8593fbc6 | 2493 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
8b6e50c9 BN |
2494 | * @mtd: MTD device structure |
2495 | * @to: offset to write to | |
2496 | * @ops: oob operation description structure | |
1da177e4 | 2497 | * |
8b6e50c9 | 2498 | * NAND write out-of-band. |
1da177e4 | 2499 | */ |
8593fbc6 TG |
2500 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
2501 | struct mtd_oob_ops *ops) | |
1da177e4 | 2502 | { |
03736155 | 2503 | int chipnr, page, status, len; |
ace4dfee | 2504 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2505 | |
289c0522 | 2506 | pr_debug("%s: to = 0x%08x, len = %i\n", |
20d8e248 | 2507 | __func__, (unsigned int)to, (int)ops->ooblen); |
1da177e4 | 2508 | |
0612b9dd | 2509 | if (ops->mode == MTD_OPS_AUTO_OOB) |
03736155 AH |
2510 | len = chip->ecc.layout->oobavail; |
2511 | else | |
2512 | len = mtd->oobsize; | |
2513 | ||
1da177e4 | 2514 | /* Do not allow write past end of page */ |
03736155 | 2515 | if ((ops->ooboffs + ops->ooblen) > len) { |
289c0522 BN |
2516 | pr_debug("%s: attempt to write past end of page\n", |
2517 | __func__); | |
1da177e4 LT |
2518 | return -EINVAL; |
2519 | } | |
2520 | ||
03736155 | 2521 | if (unlikely(ops->ooboffs >= len)) { |
289c0522 BN |
2522 | pr_debug("%s: attempt to start write outside oob\n", |
2523 | __func__); | |
03736155 AH |
2524 | return -EINVAL; |
2525 | } | |
2526 | ||
775adc3d | 2527 | /* Do not allow write past end of device */ |
03736155 AH |
2528 | if (unlikely(to >= mtd->size || |
2529 | ops->ooboffs + ops->ooblen > | |
2530 | ((mtd->size >> chip->page_shift) - | |
2531 | (to >> chip->page_shift)) * len)) { | |
289c0522 BN |
2532 | pr_debug("%s: attempt to write beyond end of device\n", |
2533 | __func__); | |
03736155 AH |
2534 | return -EINVAL; |
2535 | } | |
2536 | ||
7314e9e7 | 2537 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 2538 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2539 | |
7314e9e7 TG |
2540 | /* Shift to get page */ |
2541 | page = (int)(to >> chip->page_shift); | |
2542 | ||
2543 | /* | |
2544 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
2545 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
2546 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
2547 | * it in the doc2000 driver in August 1999. dwmw2. | |
2548 | */ | |
ace4dfee | 2549 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
2550 | |
2551 | /* Check, if it is write protected */ | |
b0bb6903 HS |
2552 | if (nand_check_wp(mtd)) { |
2553 | chip->select_chip(mtd, -1); | |
8593fbc6 | 2554 | return -EROFS; |
b0bb6903 | 2555 | } |
61b03bd7 | 2556 | |
1da177e4 | 2557 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
2558 | if (page == chip->pagebuf) |
2559 | chip->pagebuf = -1; | |
1da177e4 | 2560 | |
f722013e | 2561 | nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); |
9ce244b3 | 2562 | |
0612b9dd | 2563 | if (ops->mode == MTD_OPS_RAW) |
9ce244b3 BN |
2564 | status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); |
2565 | else | |
2566 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
1da177e4 | 2567 | |
b0bb6903 HS |
2568 | chip->select_chip(mtd, -1); |
2569 | ||
7bc3312b TG |
2570 | if (status) |
2571 | return status; | |
1da177e4 | 2572 | |
7014568b | 2573 | ops->oobretlen = ops->ooblen; |
1da177e4 | 2574 | |
7bc3312b | 2575 | return 0; |
8593fbc6 TG |
2576 | } |
2577 | ||
2578 | /** | |
2579 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
8b6e50c9 BN |
2580 | * @mtd: MTD device structure |
2581 | * @to: offset to write to | |
2582 | * @ops: oob operation description structure | |
8593fbc6 TG |
2583 | */ |
2584 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
2585 | struct mtd_oob_ops *ops) | |
2586 | { | |
8593fbc6 TG |
2587 | int ret = -ENOTSUPP; |
2588 | ||
2589 | ops->retlen = 0; | |
2590 | ||
2591 | /* Do not allow writes past end of device */ | |
7014568b | 2592 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
289c0522 BN |
2593 | pr_debug("%s: attempt to write beyond end of device\n", |
2594 | __func__); | |
8593fbc6 TG |
2595 | return -EINVAL; |
2596 | } | |
2597 | ||
6a8214aa | 2598 | nand_get_device(mtd, FL_WRITING); |
8593fbc6 | 2599 | |
f8ac0414 | 2600 | switch (ops->mode) { |
0612b9dd BN |
2601 | case MTD_OPS_PLACE_OOB: |
2602 | case MTD_OPS_AUTO_OOB: | |
2603 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2604 | break; |
2605 | ||
2606 | default: | |
2607 | goto out; | |
2608 | } | |
2609 | ||
2610 | if (!ops->datbuf) | |
2611 | ret = nand_do_write_oob(mtd, to, ops); | |
2612 | else | |
2613 | ret = nand_do_write_ops(mtd, to, ops); | |
2614 | ||
7351d3a5 | 2615 | out: |
1da177e4 | 2616 | nand_release_device(mtd); |
1da177e4 LT |
2617 | return ret; |
2618 | } | |
2619 | ||
1da177e4 | 2620 | /** |
7854d3f7 | 2621 | * single_erase_cmd - [GENERIC] NAND standard block erase command function |
8b6e50c9 BN |
2622 | * @mtd: MTD device structure |
2623 | * @page: the page address of the block which will be erased | |
1da177e4 | 2624 | * |
8b6e50c9 | 2625 | * Standard erase command for NAND chips. |
1da177e4 | 2626 | */ |
e0c7d767 | 2627 | static void single_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2628 | { |
ace4dfee | 2629 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2630 | /* Send commands to erase a block */ |
ace4dfee TG |
2631 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2632 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2633 | } |
2634 | ||
1da177e4 LT |
2635 | /** |
2636 | * nand_erase - [MTD Interface] erase block(s) | |
8b6e50c9 BN |
2637 | * @mtd: MTD device structure |
2638 | * @instr: erase instruction | |
1da177e4 | 2639 | * |
8b6e50c9 | 2640 | * Erase one ore more blocks. |
1da177e4 | 2641 | */ |
e0c7d767 | 2642 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 2643 | { |
e0c7d767 | 2644 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 2645 | } |
61b03bd7 | 2646 | |
1da177e4 | 2647 | /** |
7854d3f7 | 2648 | * nand_erase_nand - [INTERN] erase block(s) |
8b6e50c9 BN |
2649 | * @mtd: MTD device structure |
2650 | * @instr: erase instruction | |
2651 | * @allowbbt: allow erasing the bbt area | |
1da177e4 | 2652 | * |
8b6e50c9 | 2653 | * Erase one ore more blocks. |
1da177e4 | 2654 | */ |
ace4dfee TG |
2655 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
2656 | int allowbbt) | |
1da177e4 | 2657 | { |
69423d99 | 2658 | int page, status, pages_per_block, ret, chipnr; |
ace4dfee | 2659 | struct nand_chip *chip = mtd->priv; |
69423d99 | 2660 | loff_t len; |
1da177e4 | 2661 | |
289c0522 BN |
2662 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
2663 | __func__, (unsigned long long)instr->addr, | |
2664 | (unsigned long long)instr->len); | |
1da177e4 | 2665 | |
6fe5a6ac | 2666 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 2667 | return -EINVAL; |
1da177e4 | 2668 | |
1da177e4 | 2669 | /* Grab the lock and see if the device is available */ |
6a8214aa | 2670 | nand_get_device(mtd, FL_ERASING); |
1da177e4 LT |
2671 | |
2672 | /* Shift to get first page */ | |
ace4dfee TG |
2673 | page = (int)(instr->addr >> chip->page_shift); |
2674 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
2675 | |
2676 | /* Calculate pages in each block */ | |
ace4dfee | 2677 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
2678 | |
2679 | /* Select the NAND device */ | |
ace4dfee | 2680 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2681 | |
1da177e4 LT |
2682 | /* Check, if it is write protected */ |
2683 | if (nand_check_wp(mtd)) { | |
289c0522 BN |
2684 | pr_debug("%s: device is write protected!\n", |
2685 | __func__); | |
1da177e4 LT |
2686 | instr->state = MTD_ERASE_FAILED; |
2687 | goto erase_exit; | |
2688 | } | |
2689 | ||
2690 | /* Loop through the pages */ | |
2691 | len = instr->len; | |
2692 | ||
2693 | instr->state = MTD_ERASING; | |
2694 | ||
2695 | while (len) { | |
12183a20 | 2696 | /* Check if we have a bad block, we do not erase bad blocks! */ |
ace4dfee TG |
2697 | if (nand_block_checkbad(mtd, ((loff_t) page) << |
2698 | chip->page_shift, 0, allowbbt)) { | |
d0370219 BN |
2699 | pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", |
2700 | __func__, page); | |
1da177e4 LT |
2701 | instr->state = MTD_ERASE_FAILED; |
2702 | goto erase_exit; | |
2703 | } | |
61b03bd7 | 2704 | |
ace4dfee TG |
2705 | /* |
2706 | * Invalidate the page cache, if we erase the block which | |
8b6e50c9 | 2707 | * contains the current cached page. |
ace4dfee TG |
2708 | */ |
2709 | if (page <= chip->pagebuf && chip->pagebuf < | |
2710 | (page + pages_per_block)) | |
2711 | chip->pagebuf = -1; | |
1da177e4 | 2712 | |
ace4dfee | 2713 | chip->erase_cmd(mtd, page & chip->pagemask); |
61b03bd7 | 2714 | |
7bc3312b | 2715 | status = chip->waitfunc(mtd, chip); |
1da177e4 | 2716 | |
ace4dfee TG |
2717 | /* |
2718 | * See if operation failed and additional status checks are | |
2719 | * available | |
2720 | */ | |
2721 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2722 | status = chip->errstat(mtd, chip, FL_ERASING, | |
2723 | status, page); | |
068e3c0a | 2724 | |
1da177e4 | 2725 | /* See if block erase succeeded */ |
a4ab4c5d | 2726 | if (status & NAND_STATUS_FAIL) { |
289c0522 BN |
2727 | pr_debug("%s: failed erase, page 0x%08x\n", |
2728 | __func__, page); | |
1da177e4 | 2729 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
2730 | instr->fail_addr = |
2731 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
2732 | goto erase_exit; |
2733 | } | |
30f464b7 | 2734 | |
1da177e4 | 2735 | /* Increment page address and decrement length */ |
daae74ca | 2736 | len -= (1ULL << chip->phys_erase_shift); |
1da177e4 LT |
2737 | page += pages_per_block; |
2738 | ||
2739 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 2740 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 2741 | chipnr++; |
ace4dfee TG |
2742 | chip->select_chip(mtd, -1); |
2743 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2744 | } |
2745 | } | |
2746 | instr->state = MTD_ERASE_DONE; | |
2747 | ||
7351d3a5 | 2748 | erase_exit: |
1da177e4 LT |
2749 | |
2750 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
2751 | |
2752 | /* Deselect and wake up anyone waiting on the device */ | |
b0bb6903 | 2753 | chip->select_chip(mtd, -1); |
1da177e4 LT |
2754 | nand_release_device(mtd); |
2755 | ||
49defc01 DW |
2756 | /* Do call back function */ |
2757 | if (!ret) | |
2758 | mtd_erase_callback(instr); | |
2759 | ||
1da177e4 LT |
2760 | /* Return more or less happy */ |
2761 | return ret; | |
2762 | } | |
2763 | ||
2764 | /** | |
2765 | * nand_sync - [MTD Interface] sync | |
8b6e50c9 | 2766 | * @mtd: MTD device structure |
1da177e4 | 2767 | * |
8b6e50c9 | 2768 | * Sync is actually a wait for chip ready function. |
1da177e4 | 2769 | */ |
e0c7d767 | 2770 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 2771 | { |
289c0522 | 2772 | pr_debug("%s: called\n", __func__); |
1da177e4 LT |
2773 | |
2774 | /* Grab the lock and see if the device is available */ | |
6a8214aa | 2775 | nand_get_device(mtd, FL_SYNCING); |
1da177e4 | 2776 | /* Release it and go back */ |
e0c7d767 | 2777 | nand_release_device(mtd); |
1da177e4 LT |
2778 | } |
2779 | ||
1da177e4 | 2780 | /** |
ace4dfee | 2781 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
8b6e50c9 BN |
2782 | * @mtd: MTD device structure |
2783 | * @offs: offset relative to mtd start | |
1da177e4 | 2784 | */ |
ace4dfee | 2785 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 | 2786 | { |
ace4dfee | 2787 | return nand_block_checkbad(mtd, offs, 1, 0); |
1da177e4 LT |
2788 | } |
2789 | ||
2790 | /** | |
ace4dfee | 2791 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
8b6e50c9 BN |
2792 | * @mtd: MTD device structure |
2793 | * @ofs: offset relative to mtd start | |
1da177e4 | 2794 | */ |
e0c7d767 | 2795 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 2796 | { |
1da177e4 LT |
2797 | int ret; |
2798 | ||
f8ac0414 FF |
2799 | ret = nand_block_isbad(mtd, ofs); |
2800 | if (ret) { | |
8b6e50c9 | 2801 | /* If it was bad already, return success and do nothing */ |
1da177e4 LT |
2802 | if (ret > 0) |
2803 | return 0; | |
e0c7d767 DW |
2804 | return ret; |
2805 | } | |
1da177e4 | 2806 | |
5a0edb25 | 2807 | return nand_block_markbad_lowlevel(mtd, ofs); |
1da177e4 LT |
2808 | } |
2809 | ||
7db03ecc HS |
2810 | /** |
2811 | * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand | |
2812 | * @mtd: MTD device structure | |
2813 | * @chip: nand chip info structure | |
2814 | * @addr: feature address. | |
2815 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
2816 | */ | |
2817 | static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, | |
2818 | int addr, uint8_t *subfeature_param) | |
2819 | { | |
2820 | int status; | |
05f78359 | 2821 | int i; |
7db03ecc | 2822 | |
d914c932 DM |
2823 | if (!chip->onfi_version || |
2824 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
2825 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
2826 | return -EINVAL; |
2827 | ||
2828 | chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); | |
05f78359 UKK |
2829 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
2830 | chip->write_byte(mtd, subfeature_param[i]); | |
2831 | ||
7db03ecc HS |
2832 | status = chip->waitfunc(mtd, chip); |
2833 | if (status & NAND_STATUS_FAIL) | |
2834 | return -EIO; | |
2835 | return 0; | |
2836 | } | |
2837 | ||
2838 | /** | |
2839 | * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand | |
2840 | * @mtd: MTD device structure | |
2841 | * @chip: nand chip info structure | |
2842 | * @addr: feature address. | |
2843 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
2844 | */ | |
2845 | static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, | |
2846 | int addr, uint8_t *subfeature_param) | |
2847 | { | |
05f78359 UKK |
2848 | int i; |
2849 | ||
d914c932 DM |
2850 | if (!chip->onfi_version || |
2851 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
2852 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
2853 | return -EINVAL; |
2854 | ||
2855 | /* clear the sub feature parameters */ | |
2856 | memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN); | |
2857 | ||
2858 | chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1); | |
05f78359 UKK |
2859 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
2860 | *subfeature_param++ = chip->read_byte(mtd); | |
7db03ecc HS |
2861 | return 0; |
2862 | } | |
2863 | ||
962034f4 VW |
2864 | /** |
2865 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
8b6e50c9 | 2866 | * @mtd: MTD device structure |
962034f4 VW |
2867 | */ |
2868 | static int nand_suspend(struct mtd_info *mtd) | |
2869 | { | |
6a8214aa | 2870 | return nand_get_device(mtd, FL_PM_SUSPENDED); |
962034f4 VW |
2871 | } |
2872 | ||
2873 | /** | |
2874 | * nand_resume - [MTD Interface] Resume the NAND flash | |
8b6e50c9 | 2875 | * @mtd: MTD device structure |
962034f4 VW |
2876 | */ |
2877 | static void nand_resume(struct mtd_info *mtd) | |
2878 | { | |
ace4dfee | 2879 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2880 | |
ace4dfee | 2881 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
2882 | nand_release_device(mtd); |
2883 | else | |
d0370219 BN |
2884 | pr_err("%s called for a chip which is not in suspended state\n", |
2885 | __func__); | |
962034f4 VW |
2886 | } |
2887 | ||
8b6e50c9 | 2888 | /* Set default functions */ |
ace4dfee | 2889 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 2890 | { |
1da177e4 | 2891 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
2892 | if (!chip->chip_delay) |
2893 | chip->chip_delay = 20; | |
1da177e4 LT |
2894 | |
2895 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
2896 | if (chip->cmdfunc == NULL) |
2897 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
2898 | |
2899 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
2900 | if (chip->waitfunc == NULL) |
2901 | chip->waitfunc = nand_wait; | |
2902 | ||
2903 | if (!chip->select_chip) | |
2904 | chip->select_chip = nand_select_chip; | |
68e80780 | 2905 | |
4204cccd HS |
2906 | /* set for ONFI nand */ |
2907 | if (!chip->onfi_set_features) | |
2908 | chip->onfi_set_features = nand_onfi_set_features; | |
2909 | if (!chip->onfi_get_features) | |
2910 | chip->onfi_get_features = nand_onfi_get_features; | |
2911 | ||
68e80780 BN |
2912 | /* If called twice, pointers that depend on busw may need to be reset */ |
2913 | if (!chip->read_byte || chip->read_byte == nand_read_byte) | |
ace4dfee TG |
2914 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; |
2915 | if (!chip->read_word) | |
2916 | chip->read_word = nand_read_word; | |
2917 | if (!chip->block_bad) | |
2918 | chip->block_bad = nand_block_bad; | |
2919 | if (!chip->block_markbad) | |
2920 | chip->block_markbad = nand_default_block_markbad; | |
68e80780 | 2921 | if (!chip->write_buf || chip->write_buf == nand_write_buf) |
ace4dfee | 2922 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; |
05f78359 UKK |
2923 | if (!chip->write_byte || chip->write_byte == nand_write_byte) |
2924 | chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; | |
68e80780 | 2925 | if (!chip->read_buf || chip->read_buf == nand_read_buf) |
ace4dfee | 2926 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; |
ace4dfee TG |
2927 | if (!chip->scan_bbt) |
2928 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
2929 | |
2930 | if (!chip->controller) { | |
2931 | chip->controller = &chip->hwcontrol; | |
2932 | spin_lock_init(&chip->controller->lock); | |
2933 | init_waitqueue_head(&chip->controller->wq); | |
2934 | } | |
2935 | ||
7aa65bfd TG |
2936 | } |
2937 | ||
8b6e50c9 | 2938 | /* Sanitize ONFI strings so we can safely print them */ |
d1e1f4e4 FF |
2939 | static void sanitize_string(uint8_t *s, size_t len) |
2940 | { | |
2941 | ssize_t i; | |
2942 | ||
8b6e50c9 | 2943 | /* Null terminate */ |
d1e1f4e4 FF |
2944 | s[len - 1] = 0; |
2945 | ||
8b6e50c9 | 2946 | /* Remove non printable chars */ |
d1e1f4e4 FF |
2947 | for (i = 0; i < len - 1; i++) { |
2948 | if (s[i] < ' ' || s[i] > 127) | |
2949 | s[i] = '?'; | |
2950 | } | |
2951 | ||
8b6e50c9 | 2952 | /* Remove trailing spaces */ |
d1e1f4e4 FF |
2953 | strim(s); |
2954 | } | |
2955 | ||
2956 | static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) | |
2957 | { | |
2958 | int i; | |
2959 | while (len--) { | |
2960 | crc ^= *p++ << 8; | |
2961 | for (i = 0; i < 8; i++) | |
2962 | crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); | |
2963 | } | |
2964 | ||
2965 | return crc; | |
2966 | } | |
2967 | ||
6dcbe0cd HS |
2968 | /* Parse the Extended Parameter Page. */ |
2969 | static int nand_flash_detect_ext_param_page(struct mtd_info *mtd, | |
2970 | struct nand_chip *chip, struct nand_onfi_params *p) | |
2971 | { | |
2972 | struct onfi_ext_param_page *ep; | |
2973 | struct onfi_ext_section *s; | |
2974 | struct onfi_ext_ecc_info *ecc; | |
2975 | uint8_t *cursor; | |
2976 | int ret = -EINVAL; | |
2977 | int len; | |
2978 | int i; | |
2979 | ||
2980 | len = le16_to_cpu(p->ext_param_page_length) * 16; | |
2981 | ep = kmalloc(len, GFP_KERNEL); | |
5cb13271 BN |
2982 | if (!ep) |
2983 | return -ENOMEM; | |
6dcbe0cd HS |
2984 | |
2985 | /* Send our own NAND_CMD_PARAM. */ | |
2986 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); | |
2987 | ||
2988 | /* Use the Change Read Column command to skip the ONFI param pages. */ | |
2989 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, | |
2990 | sizeof(*p) * p->num_of_param_pages , -1); | |
2991 | ||
2992 | /* Read out the Extended Parameter Page. */ | |
2993 | chip->read_buf(mtd, (uint8_t *)ep, len); | |
2994 | if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2) | |
2995 | != le16_to_cpu(ep->crc))) { | |
2996 | pr_debug("fail in the CRC.\n"); | |
2997 | goto ext_out; | |
2998 | } | |
2999 | ||
3000 | /* | |
3001 | * Check the signature. | |
3002 | * Do not strictly follow the ONFI spec, maybe changed in future. | |
3003 | */ | |
3004 | if (strncmp(ep->sig, "EPPS", 4)) { | |
3005 | pr_debug("The signature is invalid.\n"); | |
3006 | goto ext_out; | |
3007 | } | |
3008 | ||
3009 | /* find the ECC section. */ | |
3010 | cursor = (uint8_t *)(ep + 1); | |
3011 | for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) { | |
3012 | s = ep->sections + i; | |
3013 | if (s->type == ONFI_SECTION_TYPE_2) | |
3014 | break; | |
3015 | cursor += s->length * 16; | |
3016 | } | |
3017 | if (i == ONFI_EXT_SECTION_MAX) { | |
3018 | pr_debug("We can not find the ECC section.\n"); | |
3019 | goto ext_out; | |
3020 | } | |
3021 | ||
3022 | /* get the info we want. */ | |
3023 | ecc = (struct onfi_ext_ecc_info *)cursor; | |
3024 | ||
4ae7d228 BN |
3025 | if (!ecc->codeword_size) { |
3026 | pr_debug("Invalid codeword size\n"); | |
3027 | goto ext_out; | |
6dcbe0cd HS |
3028 | } |
3029 | ||
4ae7d228 BN |
3030 | chip->ecc_strength_ds = ecc->ecc_bits; |
3031 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
5cb13271 | 3032 | ret = 0; |
6dcbe0cd HS |
3033 | |
3034 | ext_out: | |
3035 | kfree(ep); | |
3036 | return ret; | |
3037 | } | |
3038 | ||
8429bb39 BN |
3039 | static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode) |
3040 | { | |
3041 | struct nand_chip *chip = mtd->priv; | |
3042 | uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; | |
3043 | ||
3044 | return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, | |
3045 | feature); | |
3046 | } | |
3047 | ||
3048 | /* | |
3049 | * Configure chip properties from Micron vendor-specific ONFI table | |
3050 | */ | |
3051 | static void nand_onfi_detect_micron(struct nand_chip *chip, | |
3052 | struct nand_onfi_params *p) | |
3053 | { | |
3054 | struct nand_onfi_vendor_micron *micron = (void *)p->vendor; | |
3055 | ||
3056 | if (le16_to_cpu(p->vendor_revision) < 1) | |
3057 | return; | |
3058 | ||
3059 | chip->read_retries = micron->read_retry_options; | |
3060 | chip->setup_read_retry = nand_setup_read_retry_micron; | |
3061 | } | |
3062 | ||
6fb277ba | 3063 | /* |
8b6e50c9 | 3064 | * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. |
6fb277ba FF |
3065 | */ |
3066 | static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, | |
08c248fb | 3067 | int *busw) |
6fb277ba FF |
3068 | { |
3069 | struct nand_onfi_params *p = &chip->onfi_params; | |
bd9c6e99 | 3070 | int i, j; |
6fb277ba FF |
3071 | int val; |
3072 | ||
7854d3f7 | 3073 | /* Try ONFI for unknown chip or LP */ |
6fb277ba FF |
3074 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); |
3075 | if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || | |
3076 | chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') | |
3077 | return 0; | |
3078 | ||
6fb277ba FF |
3079 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); |
3080 | for (i = 0; i < 3; i++) { | |
bd9c6e99 BN |
3081 | for (j = 0; j < sizeof(*p); j++) |
3082 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
6fb277ba FF |
3083 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == |
3084 | le16_to_cpu(p->crc)) { | |
6fb277ba FF |
3085 | break; |
3086 | } | |
3087 | } | |
3088 | ||
c7f23a70 BN |
3089 | if (i == 3) { |
3090 | pr_err("Could not find valid ONFI parameter page; aborting\n"); | |
6fb277ba | 3091 | return 0; |
c7f23a70 | 3092 | } |
6fb277ba | 3093 | |
8b6e50c9 | 3094 | /* Check version */ |
6fb277ba | 3095 | val = le16_to_cpu(p->revision); |
b7b1a29d BN |
3096 | if (val & (1 << 5)) |
3097 | chip->onfi_version = 23; | |
3098 | else if (val & (1 << 4)) | |
6fb277ba FF |
3099 | chip->onfi_version = 22; |
3100 | else if (val & (1 << 3)) | |
3101 | chip->onfi_version = 21; | |
3102 | else if (val & (1 << 2)) | |
3103 | chip->onfi_version = 20; | |
b7b1a29d | 3104 | else if (val & (1 << 1)) |
6fb277ba | 3105 | chip->onfi_version = 10; |
b7b1a29d BN |
3106 | |
3107 | if (!chip->onfi_version) { | |
20171642 | 3108 | pr_info("unsupported ONFI version: %d\n", val); |
b7b1a29d BN |
3109 | return 0; |
3110 | } | |
6fb277ba FF |
3111 | |
3112 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3113 | sanitize_string(p->model, sizeof(p->model)); | |
3114 | if (!mtd->name) | |
3115 | mtd->name = p->model; | |
4355b70c | 3116 | |
6fb277ba | 3117 | mtd->writesize = le32_to_cpu(p->byte_per_page); |
4355b70c BN |
3118 | |
3119 | /* | |
3120 | * pages_per_block and blocks_per_lun may not be a power-of-2 size | |
3121 | * (don't ask me who thought of this...). MTD assumes that these | |
3122 | * dimensions will be power-of-2, so just truncate the remaining area. | |
3123 | */ | |
3124 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3125 | mtd->erasesize *= mtd->writesize; | |
3126 | ||
6fb277ba | 3127 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); |
4355b70c BN |
3128 | |
3129 | /* See erasesize comment */ | |
3130 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
63795755 | 3131 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; |
13fbd179 | 3132 | chip->bits_per_cell = p->bits_per_cell; |
e2985fc1 HS |
3133 | |
3134 | if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) | |
08c248fb | 3135 | *busw = NAND_BUSWIDTH_16; |
e2985fc1 HS |
3136 | else |
3137 | *busw = 0; | |
6fb277ba | 3138 | |
10c86bab HS |
3139 | if (p->ecc_bits != 0xff) { |
3140 | chip->ecc_strength_ds = p->ecc_bits; | |
3141 | chip->ecc_step_ds = 512; | |
6dcbe0cd HS |
3142 | } else if (chip->onfi_version >= 21 && |
3143 | (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) { | |
3144 | ||
3145 | /* | |
3146 | * The nand_flash_detect_ext_param_page() uses the | |
3147 | * Change Read Column command which maybe not supported | |
3148 | * by the chip->cmdfunc. So try to update the chip->cmdfunc | |
3149 | * now. We do not replace user supplied command function. | |
3150 | */ | |
3151 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) | |
3152 | chip->cmdfunc = nand_command_lp; | |
3153 | ||
3154 | /* The Extended Parameter Page is supported since ONFI 2.1. */ | |
3155 | if (nand_flash_detect_ext_param_page(mtd, chip, p)) | |
c7f23a70 BN |
3156 | pr_warn("Failed to detect ONFI extended param page\n"); |
3157 | } else { | |
3158 | pr_warn("Could not retrieve ONFI ECC requirements\n"); | |
10c86bab HS |
3159 | } |
3160 | ||
8429bb39 BN |
3161 | if (p->jedec_id == NAND_MFR_MICRON) |
3162 | nand_onfi_detect_micron(chip, p); | |
3163 | ||
6fb277ba FF |
3164 | return 1; |
3165 | } | |
3166 | ||
91361818 HS |
3167 | /* |
3168 | * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise. | |
3169 | */ | |
3170 | static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip, | |
3171 | int *busw) | |
3172 | { | |
3173 | struct nand_jedec_params *p = &chip->jedec_params; | |
3174 | struct jedec_ecc_info *ecc; | |
3175 | int val; | |
3176 | int i, j; | |
3177 | ||
3178 | /* Try JEDEC for unknown chip or LP */ | |
3179 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1); | |
3180 | if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' || | |
3181 | chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' || | |
3182 | chip->read_byte(mtd) != 'C') | |
3183 | return 0; | |
3184 | ||
3185 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1); | |
3186 | for (i = 0; i < 3; i++) { | |
3187 | for (j = 0; j < sizeof(*p); j++) | |
3188 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
3189 | ||
3190 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) == | |
3191 | le16_to_cpu(p->crc)) | |
3192 | break; | |
3193 | } | |
3194 | ||
3195 | if (i == 3) { | |
3196 | pr_err("Could not find valid JEDEC parameter page; aborting\n"); | |
3197 | return 0; | |
3198 | } | |
3199 | ||
3200 | /* Check version */ | |
3201 | val = le16_to_cpu(p->revision); | |
3202 | if (val & (1 << 2)) | |
3203 | chip->jedec_version = 10; | |
3204 | else if (val & (1 << 1)) | |
3205 | chip->jedec_version = 1; /* vendor specific version */ | |
3206 | ||
3207 | if (!chip->jedec_version) { | |
3208 | pr_info("unsupported JEDEC version: %d\n", val); | |
3209 | return 0; | |
3210 | } | |
3211 | ||
3212 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3213 | sanitize_string(p->model, sizeof(p->model)); | |
3214 | if (!mtd->name) | |
3215 | mtd->name = p->model; | |
3216 | ||
3217 | mtd->writesize = le32_to_cpu(p->byte_per_page); | |
3218 | ||
3219 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3220 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3221 | mtd->erasesize *= mtd->writesize; | |
3222 | ||
3223 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); | |
3224 | ||
3225 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3226 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
3227 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; | |
3228 | chip->bits_per_cell = p->bits_per_cell; | |
3229 | ||
3230 | if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) | |
3231 | *busw = NAND_BUSWIDTH_16; | |
3232 | else | |
3233 | *busw = 0; | |
3234 | ||
3235 | /* ECC info */ | |
3236 | ecc = &p->ecc_info[0]; | |
3237 | ||
3238 | if (ecc->codeword_size >= 9) { | |
3239 | chip->ecc_strength_ds = ecc->ecc_bits; | |
3240 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
3241 | } else { | |
3242 | pr_warn("Invalid codeword size\n"); | |
3243 | } | |
3244 | ||
3245 | return 1; | |
3246 | } | |
3247 | ||
e3b88bd6 BN |
3248 | /* |
3249 | * nand_id_has_period - Check if an ID string has a given wraparound period | |
3250 | * @id_data: the ID string | |
3251 | * @arrlen: the length of the @id_data array | |
3252 | * @period: the period of repitition | |
3253 | * | |
3254 | * Check if an ID string is repeated within a given sequence of bytes at | |
3255 | * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a | |
d4d4f1bf | 3256 | * period of 3). This is a helper function for nand_id_len(). Returns non-zero |
e3b88bd6 BN |
3257 | * if the repetition has a period of @period; otherwise, returns zero. |
3258 | */ | |
3259 | static int nand_id_has_period(u8 *id_data, int arrlen, int period) | |
3260 | { | |
3261 | int i, j; | |
3262 | for (i = 0; i < period; i++) | |
3263 | for (j = i + period; j < arrlen; j += period) | |
3264 | if (id_data[i] != id_data[j]) | |
3265 | return 0; | |
3266 | return 1; | |
3267 | } | |
3268 | ||
3269 | /* | |
3270 | * nand_id_len - Get the length of an ID string returned by CMD_READID | |
3271 | * @id_data: the ID string | |
3272 | * @arrlen: the length of the @id_data array | |
3273 | ||
3274 | * Returns the length of the ID string, according to known wraparound/trailing | |
3275 | * zero patterns. If no pattern exists, returns the length of the array. | |
3276 | */ | |
3277 | static int nand_id_len(u8 *id_data, int arrlen) | |
3278 | { | |
3279 | int last_nonzero, period; | |
3280 | ||
3281 | /* Find last non-zero byte */ | |
3282 | for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) | |
3283 | if (id_data[last_nonzero]) | |
3284 | break; | |
3285 | ||
3286 | /* All zeros */ | |
3287 | if (last_nonzero < 0) | |
3288 | return 0; | |
3289 | ||
3290 | /* Calculate wraparound period */ | |
3291 | for (period = 1; period < arrlen; period++) | |
3292 | if (nand_id_has_period(id_data, arrlen, period)) | |
3293 | break; | |
3294 | ||
3295 | /* There's a repeated pattern */ | |
3296 | if (period < arrlen) | |
3297 | return period; | |
3298 | ||
3299 | /* There are trailing zeros */ | |
3300 | if (last_nonzero < arrlen - 1) | |
3301 | return last_nonzero + 1; | |
3302 | ||
3303 | /* No pattern detected */ | |
3304 | return arrlen; | |
3305 | } | |
3306 | ||
7db906b7 HS |
3307 | /* Extract the bits of per cell from the 3rd byte of the extended ID */ |
3308 | static int nand_get_bits_per_cell(u8 cellinfo) | |
3309 | { | |
3310 | int bits; | |
3311 | ||
3312 | bits = cellinfo & NAND_CI_CELLTYPE_MSK; | |
3313 | bits >>= NAND_CI_CELLTYPE_SHIFT; | |
3314 | return bits + 1; | |
3315 | } | |
3316 | ||
fc09bbc0 BN |
3317 | /* |
3318 | * Many new NAND share similar device ID codes, which represent the size of the | |
3319 | * chip. The rest of the parameters must be decoded according to generic or | |
3320 | * manufacturer-specific "extended ID" decoding patterns. | |
3321 | */ | |
3322 | static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, | |
3323 | u8 id_data[8], int *busw) | |
3324 | { | |
e3b88bd6 | 3325 | int extid, id_len; |
fc09bbc0 | 3326 | /* The 3rd id byte holds MLC / multichip data */ |
7db906b7 | 3327 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
fc09bbc0 BN |
3328 | /* The 4th id byte is the important one */ |
3329 | extid = id_data[3]; | |
3330 | ||
e3b88bd6 BN |
3331 | id_len = nand_id_len(id_data, 8); |
3332 | ||
fc09bbc0 BN |
3333 | /* |
3334 | * Field definitions are in the following datasheets: | |
3335 | * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) | |
af451af4 | 3336 | * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) |
73ca392f | 3337 | * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) |
fc09bbc0 | 3338 | * |
af451af4 BN |
3339 | * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung |
3340 | * ID to decide what to do. | |
fc09bbc0 | 3341 | */ |
af451af4 | 3342 | if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && |
1d0ed69d | 3343 | !nand_is_slc(chip) && id_data[5] != 0x00) { |
fc09bbc0 BN |
3344 | /* Calc pagesize */ |
3345 | mtd->writesize = 2048 << (extid & 0x03); | |
3346 | extid >>= 2; | |
3347 | /* Calc oobsize */ | |
e2d3a35e | 3348 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { |
fc09bbc0 BN |
3349 | case 1: |
3350 | mtd->oobsize = 128; | |
3351 | break; | |
3352 | case 2: | |
3353 | mtd->oobsize = 218; | |
3354 | break; | |
3355 | case 3: | |
3356 | mtd->oobsize = 400; | |
3357 | break; | |
e2d3a35e | 3358 | case 4: |
fc09bbc0 BN |
3359 | mtd->oobsize = 436; |
3360 | break; | |
e2d3a35e BN |
3361 | case 5: |
3362 | mtd->oobsize = 512; | |
3363 | break; | |
3364 | case 6: | |
e2d3a35e BN |
3365 | mtd->oobsize = 640; |
3366 | break; | |
94d04e82 HS |
3367 | case 7: |
3368 | default: /* Other cases are "reserved" (unknown) */ | |
3369 | mtd->oobsize = 1024; | |
3370 | break; | |
fc09bbc0 BN |
3371 | } |
3372 | extid >>= 2; | |
3373 | /* Calc blocksize */ | |
3374 | mtd->erasesize = (128 * 1024) << | |
3375 | (((extid >> 1) & 0x04) | (extid & 0x03)); | |
3376 | *busw = 0; | |
73ca392f | 3377 | } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && |
1d0ed69d | 3378 | !nand_is_slc(chip)) { |
73ca392f BN |
3379 | unsigned int tmp; |
3380 | ||
3381 | /* Calc pagesize */ | |
3382 | mtd->writesize = 2048 << (extid & 0x03); | |
3383 | extid >>= 2; | |
3384 | /* Calc oobsize */ | |
3385 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { | |
3386 | case 0: | |
3387 | mtd->oobsize = 128; | |
3388 | break; | |
3389 | case 1: | |
3390 | mtd->oobsize = 224; | |
3391 | break; | |
3392 | case 2: | |
3393 | mtd->oobsize = 448; | |
3394 | break; | |
3395 | case 3: | |
3396 | mtd->oobsize = 64; | |
3397 | break; | |
3398 | case 4: | |
3399 | mtd->oobsize = 32; | |
3400 | break; | |
3401 | case 5: | |
3402 | mtd->oobsize = 16; | |
3403 | break; | |
3404 | default: | |
3405 | mtd->oobsize = 640; | |
3406 | break; | |
3407 | } | |
3408 | extid >>= 2; | |
3409 | /* Calc blocksize */ | |
3410 | tmp = ((extid >> 1) & 0x04) | (extid & 0x03); | |
3411 | if (tmp < 0x03) | |
3412 | mtd->erasesize = (128 * 1024) << tmp; | |
3413 | else if (tmp == 0x03) | |
3414 | mtd->erasesize = 768 * 1024; | |
3415 | else | |
3416 | mtd->erasesize = (64 * 1024) << tmp; | |
3417 | *busw = 0; | |
fc09bbc0 BN |
3418 | } else { |
3419 | /* Calc pagesize */ | |
3420 | mtd->writesize = 1024 << (extid & 0x03); | |
3421 | extid >>= 2; | |
3422 | /* Calc oobsize */ | |
3423 | mtd->oobsize = (8 << (extid & 0x01)) * | |
3424 | (mtd->writesize >> 9); | |
3425 | extid >>= 2; | |
3426 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
3427 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
3428 | extid >>= 2; | |
3429 | /* Get buswidth information */ | |
3430 | *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
60c67382 BN |
3431 | |
3432 | /* | |
3433 | * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per | |
3434 | * 512B page. For Toshiba SLC, we decode the 5th/6th byte as | |
3435 | * follows: | |
3436 | * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, | |
3437 | * 110b -> 24nm | |
3438 | * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC | |
3439 | */ | |
3440 | if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA && | |
1d0ed69d | 3441 | nand_is_slc(chip) && |
60c67382 BN |
3442 | (id_data[5] & 0x7) == 0x6 /* 24nm */ && |
3443 | !(id_data[4] & 0x80) /* !BENAND */) { | |
3444 | mtd->oobsize = 32 * mtd->writesize >> 9; | |
3445 | } | |
3446 | ||
fc09bbc0 BN |
3447 | } |
3448 | } | |
3449 | ||
f23a481c BN |
3450 | /* |
3451 | * Old devices have chip data hardcoded in the device ID table. nand_decode_id | |
3452 | * decodes a matching ID table entry and assigns the MTD size parameters for | |
3453 | * the chip. | |
3454 | */ | |
3455 | static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, | |
3456 | struct nand_flash_dev *type, u8 id_data[8], | |
3457 | int *busw) | |
3458 | { | |
3459 | int maf_id = id_data[0]; | |
3460 | ||
3461 | mtd->erasesize = type->erasesize; | |
3462 | mtd->writesize = type->pagesize; | |
3463 | mtd->oobsize = mtd->writesize / 32; | |
3464 | *busw = type->options & NAND_BUSWIDTH_16; | |
3465 | ||
1c195e90 HS |
3466 | /* All legacy ID NAND are small-page, SLC */ |
3467 | chip->bits_per_cell = 1; | |
3468 | ||
f23a481c BN |
3469 | /* |
3470 | * Check for Spansion/AMD ID + repeating 5th, 6th byte since | |
3471 | * some Spansion chips have erasesize that conflicts with size | |
3472 | * listed in nand_ids table. | |
3473 | * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) | |
3474 | */ | |
3475 | if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 | |
3476 | && id_data[6] == 0x00 && id_data[7] == 0x00 | |
3477 | && mtd->writesize == 512) { | |
3478 | mtd->erasesize = 128 * 1024; | |
3479 | mtd->erasesize <<= ((id_data[3] & 0x03) << 1); | |
3480 | } | |
3481 | } | |
3482 | ||
7e74c2d7 BN |
3483 | /* |
3484 | * Set the bad block marker/indicator (BBM/BBI) patterns according to some | |
3485 | * heuristic patterns using various detected parameters (e.g., manufacturer, | |
3486 | * page size, cell-type information). | |
3487 | */ | |
3488 | static void nand_decode_bbm_options(struct mtd_info *mtd, | |
3489 | struct nand_chip *chip, u8 id_data[8]) | |
3490 | { | |
3491 | int maf_id = id_data[0]; | |
3492 | ||
3493 | /* Set the bad block position */ | |
3494 | if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) | |
3495 | chip->badblockpos = NAND_LARGE_BADBLOCK_POS; | |
3496 | else | |
3497 | chip->badblockpos = NAND_SMALL_BADBLOCK_POS; | |
3498 | ||
3499 | /* | |
3500 | * Bad block marker is stored in the last page of each block on Samsung | |
3501 | * and Hynix MLC devices; stored in first two pages of each block on | |
3502 | * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, | |
3503 | * AMD/Spansion, and Macronix. All others scan only the first page. | |
3504 | */ | |
1d0ed69d | 3505 | if (!nand_is_slc(chip) && |
7e74c2d7 BN |
3506 | (maf_id == NAND_MFR_SAMSUNG || |
3507 | maf_id == NAND_MFR_HYNIX)) | |
3508 | chip->bbt_options |= NAND_BBT_SCANLASTPAGE; | |
1d0ed69d | 3509 | else if ((nand_is_slc(chip) && |
7e74c2d7 BN |
3510 | (maf_id == NAND_MFR_SAMSUNG || |
3511 | maf_id == NAND_MFR_HYNIX || | |
3512 | maf_id == NAND_MFR_TOSHIBA || | |
3513 | maf_id == NAND_MFR_AMD || | |
3514 | maf_id == NAND_MFR_MACRONIX)) || | |
3515 | (mtd->writesize == 2048 && | |
3516 | maf_id == NAND_MFR_MICRON)) | |
3517 | chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; | |
3518 | } | |
3519 | ||
ec6e87e3 HS |
3520 | static inline bool is_full_id_nand(struct nand_flash_dev *type) |
3521 | { | |
3522 | return type->id_len; | |
3523 | } | |
3524 | ||
3525 | static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, | |
3526 | struct nand_flash_dev *type, u8 *id_data, int *busw) | |
3527 | { | |
3528 | if (!strncmp(type->id, id_data, type->id_len)) { | |
3529 | mtd->writesize = type->pagesize; | |
3530 | mtd->erasesize = type->erasesize; | |
3531 | mtd->oobsize = type->oobsize; | |
3532 | ||
7db906b7 | 3533 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
ec6e87e3 HS |
3534 | chip->chipsize = (uint64_t)type->chipsize << 20; |
3535 | chip->options |= type->options; | |
57219342 HS |
3536 | chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); |
3537 | chip->ecc_step_ds = NAND_ECC_STEP(type); | |
ec6e87e3 HS |
3538 | |
3539 | *busw = type->options & NAND_BUSWIDTH_16; | |
3540 | ||
092b6a1d CZ |
3541 | if (!mtd->name) |
3542 | mtd->name = type->name; | |
3543 | ||
ec6e87e3 HS |
3544 | return true; |
3545 | } | |
3546 | return false; | |
3547 | } | |
3548 | ||
7aa65bfd | 3549 | /* |
8b6e50c9 | 3550 | * Get the flash and manufacturer id and lookup if the type is supported. |
7aa65bfd TG |
3551 | */ |
3552 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 3553 | struct nand_chip *chip, |
7351d3a5 | 3554 | int *maf_id, int *dev_id, |
5e81e88a | 3555 | struct nand_flash_dev *type) |
7aa65bfd | 3556 | { |
bb77082f | 3557 | int busw; |
d1e1f4e4 | 3558 | int i, maf_idx; |
426c457a | 3559 | u8 id_data[8]; |
1da177e4 LT |
3560 | |
3561 | /* Select the device */ | |
ace4dfee | 3562 | chip->select_chip(mtd, 0); |
1da177e4 | 3563 | |
ef89a880 KB |
3564 | /* |
3565 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
8b6e50c9 | 3566 | * after power-up. |
ef89a880 KB |
3567 | */ |
3568 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
3569 | ||
1da177e4 | 3570 | /* Send the command for reading device ID */ |
ace4dfee | 3571 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
3572 | |
3573 | /* Read manufacturer and device IDs */ | |
ace4dfee | 3574 | *maf_id = chip->read_byte(mtd); |
d1e1f4e4 | 3575 | *dev_id = chip->read_byte(mtd); |
1da177e4 | 3576 | |
8b6e50c9 BN |
3577 | /* |
3578 | * Try again to make sure, as some systems the bus-hold or other | |
ed8165c7 BD |
3579 | * interface concerns can cause random data which looks like a |
3580 | * possibly credible NAND flash to appear. If the two results do | |
3581 | * not match, ignore the device completely. | |
3582 | */ | |
3583 | ||
3584 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
3585 | ||
4aef9b78 BN |
3586 | /* Read entire ID string */ |
3587 | for (i = 0; i < 8; i++) | |
426c457a | 3588 | id_data[i] = chip->read_byte(mtd); |
ed8165c7 | 3589 | |
d1e1f4e4 | 3590 | if (id_data[0] != *maf_id || id_data[1] != *dev_id) { |
20171642 | 3591 | pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", |
d0370219 | 3592 | *maf_id, *dev_id, id_data[0], id_data[1]); |
ed8165c7 BD |
3593 | return ERR_PTR(-ENODEV); |
3594 | } | |
3595 | ||
7aa65bfd | 3596 | if (!type) |
5e81e88a DW |
3597 | type = nand_flash_ids; |
3598 | ||
ec6e87e3 HS |
3599 | for (; type->name != NULL; type++) { |
3600 | if (is_full_id_nand(type)) { | |
3601 | if (find_full_id_nand(mtd, chip, type, id_data, &busw)) | |
3602 | goto ident_done; | |
3603 | } else if (*dev_id == type->dev_id) { | |
3604 | break; | |
3605 | } | |
3606 | } | |
5e81e88a | 3607 | |
d1e1f4e4 FF |
3608 | chip->onfi_version = 0; |
3609 | if (!type->name || !type->pagesize) { | |
6fb277ba | 3610 | /* Check is chip is ONFI compliant */ |
47450b35 | 3611 | if (nand_flash_detect_onfi(mtd, chip, &busw)) |
6fb277ba | 3612 | goto ident_done; |
91361818 HS |
3613 | |
3614 | /* Check if the chip is JEDEC compliant */ | |
3615 | if (nand_flash_detect_jedec(mtd, chip, &busw)) | |
3616 | goto ident_done; | |
d1e1f4e4 FF |
3617 | } |
3618 | ||
5e81e88a | 3619 | if (!type->name) |
7aa65bfd TG |
3620 | return ERR_PTR(-ENODEV); |
3621 | ||
ba0251fe TG |
3622 | if (!mtd->name) |
3623 | mtd->name = type->name; | |
3624 | ||
69423d99 | 3625 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd | 3626 | |
12a40a57 | 3627 | if (!type->pagesize && chip->init_size) { |
8b6e50c9 | 3628 | /* Set the pagesize, oobsize, erasesize by the driver */ |
12a40a57 HS |
3629 | busw = chip->init_size(mtd, chip, id_data); |
3630 | } else if (!type->pagesize) { | |
fc09bbc0 BN |
3631 | /* Decode parameters from extended ID */ |
3632 | nand_decode_ext_id(mtd, chip, id_data, &busw); | |
7aa65bfd | 3633 | } else { |
f23a481c | 3634 | nand_decode_id(mtd, chip, type, id_data, &busw); |
7aa65bfd | 3635 | } |
bf7a01bf BN |
3636 | /* Get chip options */ |
3637 | chip->options |= type->options; | |
d1e1f4e4 | 3638 | |
8b6e50c9 BN |
3639 | /* |
3640 | * Check if chip is not a Samsung device. Do not clear the | |
3641 | * options for chips which do not have an extended id. | |
d1e1f4e4 FF |
3642 | */ |
3643 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) | |
3644 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; | |
3645 | ident_done: | |
3646 | ||
7aa65bfd | 3647 | /* Try to identify manufacturer */ |
9a909867 | 3648 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
7aa65bfd TG |
3649 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
3650 | break; | |
3651 | } | |
0ea4a755 | 3652 | |
64b37b2a MC |
3653 | if (chip->options & NAND_BUSWIDTH_AUTO) { |
3654 | WARN_ON(chip->options & NAND_BUSWIDTH_16); | |
3655 | chip->options |= busw; | |
3656 | nand_set_defaults(chip, busw); | |
3657 | } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { | |
3658 | /* | |
3659 | * Check, if buswidth is correct. Hardware drivers should set | |
3660 | * chip correct! | |
3661 | */ | |
20171642 EG |
3662 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
3663 | *maf_id, *dev_id); | |
3664 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name); | |
3665 | pr_warn("bus width %d instead %d bit\n", | |
d0370219 BN |
3666 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
3667 | busw ? 16 : 8); | |
7aa65bfd TG |
3668 | return ERR_PTR(-EINVAL); |
3669 | } | |
61b03bd7 | 3670 | |
7e74c2d7 BN |
3671 | nand_decode_bbm_options(mtd, chip, id_data); |
3672 | ||
7aa65bfd | 3673 | /* Calculate the address shift from the page size */ |
ace4dfee | 3674 | chip->page_shift = ffs(mtd->writesize) - 1; |
8b6e50c9 | 3675 | /* Convert chipsize to number of pages per chip -1 */ |
ace4dfee | 3676 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 3677 | |
ace4dfee | 3678 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 3679 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
3680 | if (chip->chipsize & 0xffffffff) |
3681 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
7351d3a5 FF |
3682 | else { |
3683 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); | |
3684 | chip->chip_shift += 32 - 1; | |
3685 | } | |
1da177e4 | 3686 | |
26d9be11 | 3687 | chip->badblockbits = 8; |
14c65786 | 3688 | chip->erase_cmd = single_erase_cmd; |
7aa65bfd | 3689 | |
8b6e50c9 | 3690 | /* Do not replace user supplied command function! */ |
ace4dfee TG |
3691 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
3692 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd | 3693 | |
20171642 EG |
3694 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
3695 | *maf_id, *dev_id); | |
ffdac6cd HS |
3696 | |
3697 | if (chip->onfi_version) | |
3698 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3699 | chip->onfi_params.model); | |
3700 | else if (chip->jedec_version) | |
3701 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3702 | chip->jedec_params.model); | |
3703 | else | |
3704 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3705 | type->name); | |
3706 | ||
20171642 | 3707 | pr_info("%dMiB, %s, page size: %d, OOB size: %d\n", |
3723e93c HS |
3708 | (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", |
3709 | mtd->writesize, mtd->oobsize); | |
7aa65bfd TG |
3710 | return type; |
3711 | } | |
3712 | ||
7aa65bfd | 3713 | /** |
3b85c321 | 3714 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
8b6e50c9 BN |
3715 | * @mtd: MTD device structure |
3716 | * @maxchips: number of chips to scan for | |
3717 | * @table: alternative NAND ID table | |
7aa65bfd | 3718 | * |
8b6e50c9 BN |
3719 | * This is the first phase of the normal nand_scan() function. It reads the |
3720 | * flash ID and sets up MTD fields accordingly. | |
7aa65bfd | 3721 | * |
3b85c321 | 3722 | * The mtd->owner field must be set to the module of the caller. |
7aa65bfd | 3723 | */ |
5e81e88a DW |
3724 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
3725 | struct nand_flash_dev *table) | |
7aa65bfd | 3726 | { |
bb77082f | 3727 | int i, nand_maf_id, nand_dev_id; |
ace4dfee | 3728 | struct nand_chip *chip = mtd->priv; |
7aa65bfd TG |
3729 | struct nand_flash_dev *type; |
3730 | ||
7aa65bfd | 3731 | /* Set the default functions */ |
bb77082f | 3732 | nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); |
7aa65bfd TG |
3733 | |
3734 | /* Read the flash type */ | |
bb77082f CZ |
3735 | type = nand_get_flash_type(mtd, chip, &nand_maf_id, |
3736 | &nand_dev_id, table); | |
7aa65bfd TG |
3737 | |
3738 | if (IS_ERR(type)) { | |
b1c6e6db | 3739 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
d0370219 | 3740 | pr_warn("No NAND device found\n"); |
ace4dfee | 3741 | chip->select_chip(mtd, -1); |
7aa65bfd | 3742 | return PTR_ERR(type); |
1da177e4 LT |
3743 | } |
3744 | ||
07300164 HS |
3745 | chip->select_chip(mtd, -1); |
3746 | ||
7aa65bfd | 3747 | /* Check for a chip array */ |
e0c7d767 | 3748 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 3749 | chip->select_chip(mtd, i); |
ef89a880 KB |
3750 | /* See comment in nand_get_flash_type for reset */ |
3751 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1da177e4 | 3752 | /* Send the command for reading device ID */ |
ace4dfee | 3753 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 3754 | /* Read manufacturer and device IDs */ |
ace4dfee | 3755 | if (nand_maf_id != chip->read_byte(mtd) || |
07300164 HS |
3756 | nand_dev_id != chip->read_byte(mtd)) { |
3757 | chip->select_chip(mtd, -1); | |
1da177e4 | 3758 | break; |
07300164 HS |
3759 | } |
3760 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
3761 | } |
3762 | if (i > 1) | |
20171642 | 3763 | pr_info("%d chips detected\n", i); |
61b03bd7 | 3764 | |
1da177e4 | 3765 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
3766 | chip->numchips = i; |
3767 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 3768 | |
3b85c321 DW |
3769 | return 0; |
3770 | } | |
7351d3a5 | 3771 | EXPORT_SYMBOL(nand_scan_ident); |
3b85c321 DW |
3772 | |
3773 | ||
3774 | /** | |
3775 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
8b6e50c9 | 3776 | * @mtd: MTD device structure |
3b85c321 | 3777 | * |
8b6e50c9 BN |
3778 | * This is the second phase of the normal nand_scan() function. It fills out |
3779 | * all the uninitialized function pointers with the defaults and scans for a | |
3780 | * bad block table if appropriate. | |
3b85c321 DW |
3781 | */ |
3782 | int nand_scan_tail(struct mtd_info *mtd) | |
3783 | { | |
3784 | int i; | |
3785 | struct nand_chip *chip = mtd->priv; | |
97de79e0 | 3786 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
f02ea4e6 | 3787 | struct nand_buffers *nbuf; |
3b85c321 | 3788 | |
e2414f4c BN |
3789 | /* New bad blocks should be marked in OOB, flash-based BBT, or both */ |
3790 | BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && | |
3791 | !(chip->bbt_options & NAND_BBT_USE_FLASH)); | |
3792 | ||
f02ea4e6 HS |
3793 | if (!(chip->options & NAND_OWN_BUFFERS)) { |
3794 | nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize | |
3795 | + mtd->oobsize * 3, GFP_KERNEL); | |
3796 | if (!nbuf) | |
3797 | return -ENOMEM; | |
3798 | nbuf->ecccalc = (uint8_t *)(nbuf + 1); | |
3799 | nbuf->ecccode = nbuf->ecccalc + mtd->oobsize; | |
3800 | nbuf->databuf = nbuf->ecccode + mtd->oobsize; | |
3801 | ||
3802 | chip->buffers = nbuf; | |
3803 | } else { | |
3804 | if (!chip->buffers) | |
3805 | return -ENOMEM; | |
3806 | } | |
4bf63fcb | 3807 | |
7dcdcbef | 3808 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 3809 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 3810 | |
7aa65bfd | 3811 | /* |
8b6e50c9 | 3812 | * If no default placement scheme is given, select an appropriate one. |
7aa65bfd | 3813 | */ |
97de79e0 | 3814 | if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) { |
61b03bd7 | 3815 | switch (mtd->oobsize) { |
1da177e4 | 3816 | case 8: |
97de79e0 | 3817 | ecc->layout = &nand_oob_8; |
1da177e4 LT |
3818 | break; |
3819 | case 16: | |
97de79e0 | 3820 | ecc->layout = &nand_oob_16; |
1da177e4 LT |
3821 | break; |
3822 | case 64: | |
97de79e0 | 3823 | ecc->layout = &nand_oob_64; |
1da177e4 | 3824 | break; |
81ec5364 | 3825 | case 128: |
97de79e0 | 3826 | ecc->layout = &nand_oob_128; |
81ec5364 | 3827 | break; |
1da177e4 | 3828 | default: |
d0370219 BN |
3829 | pr_warn("No oob scheme defined for oobsize %d\n", |
3830 | mtd->oobsize); | |
1da177e4 LT |
3831 | BUG(); |
3832 | } | |
3833 | } | |
61b03bd7 | 3834 | |
956e944c DW |
3835 | if (!chip->write_page) |
3836 | chip->write_page = nand_write_page; | |
3837 | ||
61b03bd7 | 3838 | /* |
8b6e50c9 | 3839 | * Check ECC mode, default to software if 3byte/512byte hardware ECC is |
7aa65bfd | 3840 | * selected and we have 256 byte pagesize fallback to software ECC |
e0c7d767 | 3841 | */ |
956e944c | 3842 | |
97de79e0 | 3843 | switch (ecc->mode) { |
6e0cb135 SN |
3844 | case NAND_ECC_HW_OOB_FIRST: |
3845 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
97de79e0 | 3846 | if (!ecc->calculate || !ecc->correct || !ecc->hwctl) { |
9a4d4d69 | 3847 | pr_warn("No ECC functions supplied; " |
d0370219 | 3848 | "hardware ECC not possible\n"); |
6e0cb135 SN |
3849 | BUG(); |
3850 | } | |
97de79e0 HS |
3851 | if (!ecc->read_page) |
3852 | ecc->read_page = nand_read_page_hwecc_oob_first; | |
6e0cb135 | 3853 | |
6dfc6d25 | 3854 | case NAND_ECC_HW: |
8b6e50c9 | 3855 | /* Use standard hwecc read page function? */ |
97de79e0 HS |
3856 | if (!ecc->read_page) |
3857 | ecc->read_page = nand_read_page_hwecc; | |
3858 | if (!ecc->write_page) | |
3859 | ecc->write_page = nand_write_page_hwecc; | |
3860 | if (!ecc->read_page_raw) | |
3861 | ecc->read_page_raw = nand_read_page_raw; | |
3862 | if (!ecc->write_page_raw) | |
3863 | ecc->write_page_raw = nand_write_page_raw; | |
3864 | if (!ecc->read_oob) | |
3865 | ecc->read_oob = nand_read_oob_std; | |
3866 | if (!ecc->write_oob) | |
3867 | ecc->write_oob = nand_write_oob_std; | |
3868 | if (!ecc->read_subpage) | |
3869 | ecc->read_subpage = nand_read_subpage; | |
3870 | if (!ecc->write_subpage) | |
3871 | ecc->write_subpage = nand_write_subpage_hwecc; | |
f5bbdacc | 3872 | |
6dfc6d25 | 3873 | case NAND_ECC_HW_SYNDROME: |
97de79e0 HS |
3874 | if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && |
3875 | (!ecc->read_page || | |
3876 | ecc->read_page == nand_read_page_hwecc || | |
3877 | !ecc->write_page || | |
3878 | ecc->write_page == nand_write_page_hwecc)) { | |
9a4d4d69 | 3879 | pr_warn("No ECC functions supplied; " |
d0370219 | 3880 | "hardware ECC not possible\n"); |
6dfc6d25 TG |
3881 | BUG(); |
3882 | } | |
8b6e50c9 | 3883 | /* Use standard syndrome read/write page function? */ |
97de79e0 HS |
3884 | if (!ecc->read_page) |
3885 | ecc->read_page = nand_read_page_syndrome; | |
3886 | if (!ecc->write_page) | |
3887 | ecc->write_page = nand_write_page_syndrome; | |
3888 | if (!ecc->read_page_raw) | |
3889 | ecc->read_page_raw = nand_read_page_raw_syndrome; | |
3890 | if (!ecc->write_page_raw) | |
3891 | ecc->write_page_raw = nand_write_page_raw_syndrome; | |
3892 | if (!ecc->read_oob) | |
3893 | ecc->read_oob = nand_read_oob_syndrome; | |
3894 | if (!ecc->write_oob) | |
3895 | ecc->write_oob = nand_write_oob_syndrome; | |
3896 | ||
3897 | if (mtd->writesize >= ecc->size) { | |
3898 | if (!ecc->strength) { | |
e2788c98 MD |
3899 | pr_warn("Driver must set ecc.strength when using hardware ECC\n"); |
3900 | BUG(); | |
3901 | } | |
6dfc6d25 | 3902 | break; |
e2788c98 | 3903 | } |
9a4d4d69 | 3904 | pr_warn("%d byte HW ECC not possible on " |
d0370219 | 3905 | "%d byte page size, fallback to SW ECC\n", |
97de79e0 HS |
3906 | ecc->size, mtd->writesize); |
3907 | ecc->mode = NAND_ECC_SOFT; | |
61b03bd7 | 3908 | |
6dfc6d25 | 3909 | case NAND_ECC_SOFT: |
97de79e0 HS |
3910 | ecc->calculate = nand_calculate_ecc; |
3911 | ecc->correct = nand_correct_data; | |
3912 | ecc->read_page = nand_read_page_swecc; | |
3913 | ecc->read_subpage = nand_read_subpage; | |
3914 | ecc->write_page = nand_write_page_swecc; | |
3915 | ecc->read_page_raw = nand_read_page_raw; | |
3916 | ecc->write_page_raw = nand_write_page_raw; | |
3917 | ecc->read_oob = nand_read_oob_std; | |
3918 | ecc->write_oob = nand_write_oob_std; | |
3919 | if (!ecc->size) | |
3920 | ecc->size = 256; | |
3921 | ecc->bytes = 3; | |
3922 | ecc->strength = 1; | |
1da177e4 | 3923 | break; |
61b03bd7 | 3924 | |
193bd400 ID |
3925 | case NAND_ECC_SOFT_BCH: |
3926 | if (!mtd_nand_has_bch()) { | |
148256fa | 3927 | pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n"); |
193bd400 ID |
3928 | BUG(); |
3929 | } | |
97de79e0 HS |
3930 | ecc->calculate = nand_bch_calculate_ecc; |
3931 | ecc->correct = nand_bch_correct_data; | |
3932 | ecc->read_page = nand_read_page_swecc; | |
3933 | ecc->read_subpage = nand_read_subpage; | |
3934 | ecc->write_page = nand_write_page_swecc; | |
3935 | ecc->read_page_raw = nand_read_page_raw; | |
3936 | ecc->write_page_raw = nand_write_page_raw; | |
3937 | ecc->read_oob = nand_read_oob_std; | |
3938 | ecc->write_oob = nand_write_oob_std; | |
193bd400 ID |
3939 | /* |
3940 | * Board driver should supply ecc.size and ecc.bytes values to | |
3941 | * select how many bits are correctable; see nand_bch_init() | |
8b6e50c9 BN |
3942 | * for details. Otherwise, default to 4 bits for large page |
3943 | * devices. | |
193bd400 | 3944 | */ |
97de79e0 HS |
3945 | if (!ecc->size && (mtd->oobsize >= 64)) { |
3946 | ecc->size = 512; | |
3947 | ecc->bytes = 7; | |
193bd400 | 3948 | } |
97de79e0 HS |
3949 | ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes, |
3950 | &ecc->layout); | |
3951 | if (!ecc->priv) { | |
9a4d4d69 | 3952 | pr_warn("BCH ECC initialization failed!\n"); |
193bd400 ID |
3953 | BUG(); |
3954 | } | |
97de79e0 | 3955 | ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size); |
193bd400 ID |
3956 | break; |
3957 | ||
61b03bd7 | 3958 | case NAND_ECC_NONE: |
9a4d4d69 | 3959 | pr_warn("NAND_ECC_NONE selected by board driver. " |
d0370219 | 3960 | "This is not recommended!\n"); |
97de79e0 HS |
3961 | ecc->read_page = nand_read_page_raw; |
3962 | ecc->write_page = nand_write_page_raw; | |
3963 | ecc->read_oob = nand_read_oob_std; | |
3964 | ecc->read_page_raw = nand_read_page_raw; | |
3965 | ecc->write_page_raw = nand_write_page_raw; | |
3966 | ecc->write_oob = nand_write_oob_std; | |
3967 | ecc->size = mtd->writesize; | |
3968 | ecc->bytes = 0; | |
3969 | ecc->strength = 0; | |
1da177e4 | 3970 | break; |
956e944c | 3971 | |
1da177e4 | 3972 | default: |
97de79e0 | 3973 | pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode); |
61b03bd7 | 3974 | BUG(); |
1da177e4 | 3975 | } |
61b03bd7 | 3976 | |
9ce244b3 | 3977 | /* For many systems, the standard OOB write also works for raw */ |
97de79e0 HS |
3978 | if (!ecc->read_oob_raw) |
3979 | ecc->read_oob_raw = ecc->read_oob; | |
3980 | if (!ecc->write_oob_raw) | |
3981 | ecc->write_oob_raw = ecc->write_oob; | |
9ce244b3 | 3982 | |
5bd34c09 TG |
3983 | /* |
3984 | * The number of bytes available for a client to place data into | |
8b6e50c9 | 3985 | * the out of band area. |
5bd34c09 | 3986 | */ |
97de79e0 HS |
3987 | ecc->layout->oobavail = 0; |
3988 | for (i = 0; ecc->layout->oobfree[i].length | |
3989 | && i < ARRAY_SIZE(ecc->layout->oobfree); i++) | |
3990 | ecc->layout->oobavail += ecc->layout->oobfree[i].length; | |
3991 | mtd->oobavail = ecc->layout->oobavail; | |
5bd34c09 | 3992 | |
7aa65bfd TG |
3993 | /* |
3994 | * Set the number of read / write steps for one page depending on ECC | |
8b6e50c9 | 3995 | * mode. |
7aa65bfd | 3996 | */ |
97de79e0 HS |
3997 | ecc->steps = mtd->writesize / ecc->size; |
3998 | if (ecc->steps * ecc->size != mtd->writesize) { | |
9a4d4d69 | 3999 | pr_warn("Invalid ECC parameters\n"); |
6dfc6d25 | 4000 | BUG(); |
1da177e4 | 4001 | } |
97de79e0 | 4002 | ecc->total = ecc->steps * ecc->bytes; |
61b03bd7 | 4003 | |
8b6e50c9 | 4004 | /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ |
1d0ed69d | 4005 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { |
97de79e0 | 4006 | switch (ecc->steps) { |
29072b96 TG |
4007 | case 2: |
4008 | mtd->subpage_sft = 1; | |
4009 | break; | |
4010 | case 4: | |
4011 | case 8: | |
81ec5364 | 4012 | case 16: |
29072b96 TG |
4013 | mtd->subpage_sft = 2; |
4014 | break; | |
4015 | } | |
4016 | } | |
4017 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
4018 | ||
04bbd0ea | 4019 | /* Initialize state */ |
ace4dfee | 4020 | chip->state = FL_READY; |
1da177e4 | 4021 | |
1da177e4 | 4022 | /* Invalidate the pagebuffer reference */ |
ace4dfee | 4023 | chip->pagebuf = -1; |
1da177e4 | 4024 | |
a5ff4f10 | 4025 | /* Large page NAND with SOFT_ECC should support subpage reads */ |
97de79e0 | 4026 | if ((ecc->mode == NAND_ECC_SOFT) && (chip->page_shift > 9)) |
a5ff4f10 JW |
4027 | chip->options |= NAND_SUBPAGE_READ; |
4028 | ||
1da177e4 | 4029 | /* Fill in remaining MTD driver data */ |
963d1c28 | 4030 | mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH; |
93edbad6 ML |
4031 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
4032 | MTD_CAP_NANDFLASH; | |
3c3c10bb AB |
4033 | mtd->_erase = nand_erase; |
4034 | mtd->_point = NULL; | |
4035 | mtd->_unpoint = NULL; | |
4036 | mtd->_read = nand_read; | |
4037 | mtd->_write = nand_write; | |
4038 | mtd->_panic_write = panic_nand_write; | |
4039 | mtd->_read_oob = nand_read_oob; | |
4040 | mtd->_write_oob = nand_write_oob; | |
4041 | mtd->_sync = nand_sync; | |
4042 | mtd->_lock = NULL; | |
4043 | mtd->_unlock = NULL; | |
4044 | mtd->_suspend = nand_suspend; | |
4045 | mtd->_resume = nand_resume; | |
4046 | mtd->_block_isbad = nand_block_isbad; | |
4047 | mtd->_block_markbad = nand_block_markbad; | |
cbcab65a | 4048 | mtd->writebufsize = mtd->writesize; |
1da177e4 | 4049 | |
6a918bad | 4050 | /* propagate ecc info to mtd_info */ |
97de79e0 HS |
4051 | mtd->ecclayout = ecc->layout; |
4052 | mtd->ecc_strength = ecc->strength; | |
4053 | mtd->ecc_step_size = ecc->size; | |
ea3b2ea2 SL |
4054 | /* |
4055 | * Initialize bitflip_threshold to its default prior scan_bbt() call. | |
4056 | * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be | |
4057 | * properly set. | |
4058 | */ | |
4059 | if (!mtd->bitflip_threshold) | |
4060 | mtd->bitflip_threshold = mtd->ecc_strength; | |
1da177e4 | 4061 | |
0040bf38 | 4062 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 4063 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 4064 | return 0; |
1da177e4 LT |
4065 | |
4066 | /* Build bad block table */ | |
ace4dfee | 4067 | return chip->scan_bbt(mtd); |
1da177e4 | 4068 | } |
7351d3a5 | 4069 | EXPORT_SYMBOL(nand_scan_tail); |
1da177e4 | 4070 | |
8b6e50c9 BN |
4071 | /* |
4072 | * is_module_text_address() isn't exported, and it's mostly a pointless | |
7351d3a5 | 4073 | * test if this is a module _anyway_ -- they'd have to try _really_ hard |
8b6e50c9 BN |
4074 | * to call us from in-kernel code if the core NAND support is modular. |
4075 | */ | |
3b85c321 DW |
4076 | #ifdef MODULE |
4077 | #define caller_is_module() (1) | |
4078 | #else | |
4079 | #define caller_is_module() \ | |
a6e6abd5 | 4080 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
4081 | #endif |
4082 | ||
4083 | /** | |
4084 | * nand_scan - [NAND Interface] Scan for the NAND device | |
8b6e50c9 BN |
4085 | * @mtd: MTD device structure |
4086 | * @maxchips: number of chips to scan for | |
3b85c321 | 4087 | * |
8b6e50c9 BN |
4088 | * This fills out all the uninitialized function pointers with the defaults. |
4089 | * The flash ID is read and the mtd/chip structures are filled with the | |
4090 | * appropriate values. The mtd->owner field must be set to the module of the | |
4091 | * caller. | |
3b85c321 DW |
4092 | */ |
4093 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
4094 | { | |
4095 | int ret; | |
4096 | ||
4097 | /* Many callers got this wrong, so check for it for a while... */ | |
4098 | if (!mtd->owner && caller_is_module()) { | |
d0370219 | 4099 | pr_crit("%s called with NULL mtd->owner!\n", __func__); |
3b85c321 DW |
4100 | BUG(); |
4101 | } | |
4102 | ||
5e81e88a | 4103 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
4104 | if (!ret) |
4105 | ret = nand_scan_tail(mtd); | |
4106 | return ret; | |
4107 | } | |
7351d3a5 | 4108 | EXPORT_SYMBOL(nand_scan); |
3b85c321 | 4109 | |
1da177e4 | 4110 | /** |
61b03bd7 | 4111 | * nand_release - [NAND Interface] Free resources held by the NAND device |
8b6e50c9 BN |
4112 | * @mtd: MTD device structure |
4113 | */ | |
e0c7d767 | 4114 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 4115 | { |
ace4dfee | 4116 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 4117 | |
193bd400 ID |
4118 | if (chip->ecc.mode == NAND_ECC_SOFT_BCH) |
4119 | nand_bch_free((struct nand_bch_control *)chip->ecc.priv); | |
4120 | ||
5ffcaf3d | 4121 | mtd_device_unregister(mtd); |
1da177e4 | 4122 | |
fa671646 | 4123 | /* Free bad block table memory */ |
ace4dfee | 4124 | kfree(chip->bbt); |
4bf63fcb DW |
4125 | if (!(chip->options & NAND_OWN_BUFFERS)) |
4126 | kfree(chip->buffers); | |
58373ff0 BN |
4127 | |
4128 | /* Free bad block descriptor memory */ | |
4129 | if (chip->badblock_pattern && chip->badblock_pattern->options | |
4130 | & NAND_BBT_DYNAMICSTRUCT) | |
4131 | kfree(chip->badblock_pattern); | |
1da177e4 | 4132 | } |
e0c7d767 | 4133 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 RP |
4134 | |
4135 | static int __init nand_base_init(void) | |
4136 | { | |
4137 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
4138 | return 0; | |
4139 | } | |
4140 | ||
4141 | static void __exit nand_base_exit(void) | |
4142 | { | |
4143 | led_trigger_unregister_simple(nand_led_trigger); | |
4144 | } | |
4145 | ||
4146 | module_init(nand_base_init); | |
4147 | module_exit(nand_base_exit); | |
4148 | ||
e0c7d767 | 4149 | MODULE_LICENSE("GPL"); |
7351d3a5 FF |
4150 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); |
4151 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
e0c7d767 | 4152 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |