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mtd: make ofpart buildable as a separate module
[mirror_ubuntu-zesty-kernel.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
61b03bd7 8 *
1da177e4 9 * Additional technical information is available on
8b2b403c 10 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 11 *
1da177e4 12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 14 *
ace4dfee 15 * Credits:
61b03bd7
TG		 16 * David Woodhouse for adding multichip support
17 *
1da177e4
LT		 18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
ace4dfee 21 * TODO:
1da177e4
LT		 22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 24 * if we have HW ECC support.
1da177e4
LT		 25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
c0b8ba7b 27 * BBT table is not serialized, has to be fixed
1da177e4 28 *
1da177e4
LT		 29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
552d9205 35#include <linux/module.h>
1da177e4
LT		 36#include <linux/delay.h>
37#include <linux/errno.h>
7aa65bfd 38#include <linux/err.h>
1da177e4
LT		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
193bd400 45#include <linux/mtd/nand_bch.h>
1da177e4
LT		 46#include <linux/interrupt.h>
47#include <linux/bitops.h>
8fe833c1 48#include <linux/leds.h>
7351d3a5 49#include <linux/io.h>
1da177e4 50#include <linux/mtd/partitions.h>
1da177e4
LT		 51
52/* Define default oob placement schemes for large and small page devices */
5bd34c09 53static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 54 .eccbytes = 3,
55 .eccpos = {0, 1, 2},
5bd34c09
TG		 56 .oobfree = {
57 {.offset = 3,
58 .length = 2},
59 {.offset = 6,
f8ac0414 60 .length = 2} }
1da177e4
LT		 61};
62
5bd34c09 63static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 64 .eccbytes = 6,
65 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 66 .oobfree = {
67 {.offset = 8,
f8ac0414 68 . length = 8} }
1da177e4
LT		 69};
70
5bd34c09 71static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 72 .eccbytes = 24,
73 .eccpos = {
e0c7d767
DW		 74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 77 .oobfree = {
78 {.offset = 2,
f8ac0414 79 .length = 38} }
1da177e4
LT		 80};
81
81ec5364
TG		 82static struct nand_ecclayout nand_oob_128 = {
83 .eccbytes = 48,
84 .eccpos = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
91 .oobfree = {
92 {.offset = 2,
f8ac0414 93 .length = 78} }
81ec5364
TG		 94};
95
ace4dfee 96static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
2c0a2bed 97 int new_state);
1da177e4 98
8593fbc6
TG		 99static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
100 struct mtd_oob_ops *ops);
101
d470a97c 102/*
8e87d782 103 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 104 * compiled away when LED support is disabled.
105 */
106DEFINE_LED_TRIGGER(nand_led_trigger);
107
6fe5a6ac
VS		 108static int check_offs_len(struct mtd_info *mtd,
109 loff_t ofs, uint64_t len)
110{
111 struct nand_chip *chip = mtd->priv;
112 int ret = 0;
113
114 /* Start address must align on block boundary */
115 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
116 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
117 ret = -EINVAL;
118 }
119
120 /* Length must align on block boundary */
121 if (len & ((1 << chip->phys_erase_shift) - 1)) {
122 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
123 __func__);
124 ret = -EINVAL;
125 }
126
127 /* Do not allow past end of device */
128 if (ofs + len > mtd->size) {
129 DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
130 __func__);
131 ret = -EINVAL;
132 }
133
134 return ret;
135}
136
1da177e4
LT		 137/**
138 * nand_release_device - [GENERIC] release chip
8b6e50c9 139 * @mtd: MTD device structure
61b03bd7 140 *
8b6e50c9 141 * Deselect, release chip lock and wake up anyone waiting on the device.
1da177e4 142 */
e0c7d767 143static void nand_release_device(struct mtd_info *mtd)
1da177e4 144{
ace4dfee 145 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 146
147 /* De-select the NAND device */
ace4dfee 148 chip->select_chip(mtd, -1);
0dfc6246 149
a36ed299 150 /* Release the controller and the chip */
ace4dfee
TG		 151 spin_lock(&chip->controller->lock);
152 chip->controller->active = NULL;
153 chip->state = FL_READY;
154 wake_up(&chip->controller->wq);
155 spin_unlock(&chip->controller->lock);
1da177e4
LT		 156}
157
158/**
159 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 160 * @mtd: MTD device structure
1da177e4 161 *
7854d3f7 162 * Default read function for 8bit buswidth
1da177e4 163 */
58dd8f2b 164static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 165{
ace4dfee
TG		 166 struct nand_chip *chip = mtd->priv;
167 return readb(chip->IO_ADDR_R);
1da177e4
LT		 168}
169
1da177e4
LT		 170/**
171 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
7854d3f7 172 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 173 * @mtd: MTD device structure
1da177e4 174 *
7854d3f7
BN		 175 * Default read function for 16bit buswidth with endianness conversion.
176 *
1da177e4 177 */
58dd8f2b 178static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 179{
ace4dfee
TG		 180 struct nand_chip *chip = mtd->priv;
181 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 182}
183
1da177e4
LT		 184/**
185 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 186 * @mtd: MTD device structure
1da177e4 187 *
7854d3f7 188 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 189 */
190static u16 nand_read_word(struct mtd_info *mtd)
191{
ace4dfee
TG		 192 struct nand_chip *chip = mtd->priv;
193 return readw(chip->IO_ADDR_R);
1da177e4
LT		 194}
195
1da177e4
LT		 196/**
197 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 198 * @mtd: MTD device structure
199 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 200 *
201 * Default select function for 1 chip devices.
202 */
ace4dfee 203static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 204{
ace4dfee
TG		 205 struct nand_chip *chip = mtd->priv;
206
207 switch (chipnr) {
1da177e4 208 case -1:
ace4dfee 209 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 210 break;
211 case 0:
1da177e4
LT		 212 break;
213
214 default:
215 BUG();
216 }
217}
218
219/**
220 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 221 * @mtd: MTD device structure
222 * @buf: data buffer
223 * @len: number of bytes to write
1da177e4 224 *
7854d3f7 225 * Default write function for 8bit buswidth.
1da177e4 226 */
58dd8f2b 227static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 228{
229 int i;
ace4dfee 230 struct nand_chip *chip = mtd->priv;
1da177e4 231
e0c7d767 232 for (i = 0; i < len; i++)
ace4dfee 233 writeb(buf[i], chip->IO_ADDR_W);
1da177e4
LT		 234}
235
236/**
61b03bd7 237 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 238 * @mtd: MTD device structure
239 * @buf: buffer to store date
240 * @len: number of bytes to read
1da177e4 241 *
7854d3f7 242 * Default read function for 8bit buswidth.
1da177e4 243 */
58dd8f2b 244static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 245{
246 int i;
ace4dfee 247 struct nand_chip *chip = mtd->priv;
1da177e4 248
e0c7d767 249 for (i = 0; i < len; i++)
ace4dfee 250 buf[i] = readb(chip->IO_ADDR_R);
1da177e4
LT		 251}
252
253/**
61b03bd7 254 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
8b6e50c9
BN		 255 * @mtd: MTD device structure
256 * @buf: buffer containing the data to compare
257 * @len: number of bytes to compare
1da177e4 258 *
7854d3f7 259 * Default verify function for 8bit buswidth.
1da177e4 260 */
58dd8f2b 261static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 262{
263 int i;
ace4dfee 264 struct nand_chip *chip = mtd->priv;
1da177e4 265
e0c7d767 266 for (i = 0; i < len; i++)
ace4dfee 267 if (buf[i] != readb(chip->IO_ADDR_R))
1da177e4 268 return -EFAULT;
1da177e4
LT		 269 return 0;
270}
271
272/**
273 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 274 * @mtd: MTD device structure
275 * @buf: data buffer
276 * @len: number of bytes to write
1da177e4 277 *
7854d3f7 278 * Default write function for 16bit buswidth.
1da177e4 279 */
58dd8f2b 280static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 281{
282 int i;
ace4dfee 283 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 284 u16 *p = (u16 *) buf;
285 len >>= 1;
61b03bd7 286
e0c7d767 287 for (i = 0; i < len; i++)
ace4dfee 288 writew(p[i], chip->IO_ADDR_W);
61b03bd7 289
1da177e4
LT		 290}
291
292/**
61b03bd7 293 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 294 * @mtd: MTD device structure
295 * @buf: buffer to store date
296 * @len: number of bytes to read
1da177e4 297 *
7854d3f7 298 * Default read function for 16bit buswidth.
1da177e4 299 */
58dd8f2b 300static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 301{
302 int i;
ace4dfee 303 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 304 u16 *p = (u16 *) buf;
305 len >>= 1;
306
e0c7d767 307 for (i = 0; i < len; i++)
ace4dfee 308 p[i] = readw(chip->IO_ADDR_R);
1da177e4
LT		 309}
310
311/**
61b03bd7 312 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
8b6e50c9
BN		 313 * @mtd: MTD device structure
314 * @buf: buffer containing the data to compare
315 * @len: number of bytes to compare
1da177e4 316 *
7854d3f7 317 * Default verify function for 16bit buswidth.
1da177e4 318 */
58dd8f2b 319static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 320{
321 int i;
ace4dfee 322 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 323 u16 *p = (u16 *) buf;
324 len >>= 1;
325
e0c7d767 326 for (i = 0; i < len; i++)
ace4dfee 327 if (p[i] != readw(chip->IO_ADDR_R))
1da177e4
LT		 328 return -EFAULT;
329
330 return 0;
331}
332
333/**
334 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 335 * @mtd: MTD device structure
336 * @ofs: offset from device start
337 * @getchip: 0, if the chip is already selected
1da177e4 338 *
61b03bd7 339 * Check, if the block is bad.
1da177e4
LT		 340 */
341static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
342{
343 int page, chipnr, res = 0;
ace4dfee 344 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 345 u16 bad;
346
5fb1549d 347 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 348 ofs += mtd->erasesize - mtd->writesize;
349
1a12f46a
TK		 350 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
351
1da177e4 352 if (getchip) {
ace4dfee 353 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 354
ace4dfee 355 nand_get_device(chip, mtd, FL_READING);
1da177e4
LT		 356
357 /* Select the NAND device */
ace4dfee 358 chip->select_chip(mtd, chipnr);
1a12f46a 359 }
1da177e4 360
ace4dfee
TG		 361 if (chip->options & NAND_BUSWIDTH_16) {
362 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
1a12f46a 363 page);
ace4dfee
TG		 364 bad = cpu_to_le16(chip->read_word(mtd));
365 if (chip->badblockpos & 0x1)
49196f33 366 bad >>= 8;
e0b58d0a
ML		 367 else
368 bad &= 0xFF;
1da177e4 369 } else {
1a12f46a 370 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
e0b58d0a 371 bad = chip->read_byte(mtd);
1da177e4 372 }
61b03bd7 373
e0b58d0a
ML		 374 if (likely(chip->badblockbits == 8))
375 res = bad != 0xFF;
376 else
377 res = hweight8(bad) < chip->badblockbits;
378
ace4dfee 379 if (getchip)
1da177e4 380 nand_release_device(mtd);
61b03bd7 381
1da177e4
LT		 382 return res;
383}
384
385/**
386 * nand_default_block_markbad - [DEFAULT] mark a block bad
8b6e50c9
BN		 387 * @mtd: MTD device structure
388 * @ofs: offset from device start
1da177e4 389 *
8b6e50c9
BN		 390 * This is the default implementation, which can be overridden by a hardware
391 * specific driver.
1da177e4
LT		 392*/
393static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
394{
ace4dfee 395 struct nand_chip *chip = mtd->priv;
58dd8f2b 396 uint8_t buf[2] = { 0, 0 };
02ed70bb 397 int block, ret, i = 0;
61b03bd7 398
5fb1549d 399 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 400 ofs += mtd->erasesize - mtd->writesize;
401
1da177e4 402 /* Get block number */
4226b510 403 block = (int)(ofs >> chip->bbt_erase_shift);
ace4dfee
TG		 404 if (chip->bbt)
405 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4 406
8b6e50c9 407 /* Do we have a flash based bad block table? */
bb9ebd4e 408 if (chip->bbt_options & NAND_BBT_USE_FLASH)
f1a28c02
TG		 409 ret = nand_update_bbt(mtd, ofs);
410 else {
c0b8ba7b 411 nand_get_device(chip, mtd, FL_WRITING);
f1a28c02 412
a0dc5529
BN		 413 /*
414 * Write to first two pages if necessary. If we write to more
415 * than one location, the first error encountered quits the
416 * procedure. We write two bytes per location, so we dont have
417 * to mess with 16 bit access.
02ed70bb
BN		 418 */
419 do {
420 chip->ops.len = chip->ops.ooblen = 2;
421 chip->ops.datbuf = NULL;
422 chip->ops.oobbuf = buf;
423 chip->ops.ooboffs = chip->badblockpos & ~0x01;
424
425 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
426
02ed70bb
BN		 427 i++;
428 ofs += mtd->writesize;
5fb1549d 429 } while (!ret && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) &&
02ed70bb
BN		 430 i < 2);
431
c0b8ba7b 432 nand_release_device(mtd);
f1a28c02
TG		 433 }
434 if (!ret)
435 mtd->ecc_stats.badblocks++;
c0b8ba7b 436
f1a28c02 437 return ret;
1da177e4
LT		 438}
439
61b03bd7 440/**
1da177e4 441 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 442 * @mtd: MTD device structure
1da177e4 443 *
8b6e50c9
BN		 444 * Check, if the device is write protected. The function expects, that the
445 * device is already selected.
1da177e4 446 */
e0c7d767 447static int nand_check_wp(struct mtd_info *mtd)
1da177e4 448{
ace4dfee 449 struct nand_chip *chip = mtd->priv;
93edbad6 450
8b6e50c9 451 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 452 if (chip->options & NAND_BROKEN_XD)
453 return 0;
454
1da177e4 455 /* Check the WP bit */
ace4dfee
TG		 456 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
457 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 458}
459
460/**
461 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 462 * @mtd: MTD device structure
463 * @ofs: offset from device start
464 * @getchip: 0, if the chip is already selected
465 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 466 *
467 * Check, if the block is bad. Either by reading the bad block table or
468 * calling of the scan function.
469 */
2c0a2bed
TG		 470static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
471 int allowbbt)
1da177e4 472{
ace4dfee 473 struct nand_chip *chip = mtd->priv;
61b03bd7 474
ace4dfee
TG		 475 if (!chip->bbt)
476 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 477
1da177e4 478 /* Return info from the table */
e0c7d767 479 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 480}
481
2af7c653
SK		 482/**
483 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 484 * @mtd: MTD device structure
485 * @timeo: Timeout
2af7c653
SK		 486 *
487 * Helper function for nand_wait_ready used when needing to wait in interrupt
488 * context.
489 */
490static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
491{
492 struct nand_chip *chip = mtd->priv;
493 int i;
494
495 /* Wait for the device to get ready */
496 for (i = 0; i < timeo; i++) {
497 if (chip->dev_ready(mtd))
498 break;
499 touch_softlockup_watchdog();
500 mdelay(1);
501 }
502}
503
7854d3f7 504/* Wait for the ready pin, after a command. The timeout is caught later. */
4b648b02 505void nand_wait_ready(struct mtd_info *mtd)
3b88775c 506{
ace4dfee 507 struct nand_chip *chip = mtd->priv;
e0c7d767 508 unsigned long timeo = jiffies + 2;
3b88775c 509
2af7c653
SK		 510 /* 400ms timeout */
511 if (in_interrupt() || oops_in_progress)
512 return panic_nand_wait_ready(mtd, 400);
513
8fe833c1 514 led_trigger_event(nand_led_trigger, LED_FULL);
7854d3f7 515 /* Wait until command is processed or timeout occurs */
3b88775c 516 do {
ace4dfee 517 if (chip->dev_ready(mtd))
8fe833c1 518 break;
8446f1d3 519 touch_softlockup_watchdog();
61b03bd7 520 } while (time_before(jiffies, timeo));
8fe833c1 521 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 522}
4b648b02 523EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 524
1da177e4
LT		 525/**
526 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 527 * @mtd: MTD device structure
528 * @command: the command to be sent
529 * @column: the column address for this command, -1 if none
530 * @page_addr: the page address for this command, -1 if none
1da177e4 531 *
8b6e50c9
BN		 532 * Send command to NAND device. This function is used for small page devices
533 * (256/512 Bytes per page).
1da177e4 534 */
7abd3ef9
TG		 535static void nand_command(struct mtd_info *mtd, unsigned int command,
536 int column, int page_addr)
1da177e4 537{
ace4dfee 538 register struct nand_chip *chip = mtd->priv;
7abd3ef9 539 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 540
8b6e50c9 541 /* Write out the command to the device */
1da177e4
LT		 542 if (command == NAND_CMD_SEQIN) {
543 int readcmd;
544
28318776 545 if (column >= mtd->writesize) {
1da177e4 546 /* OOB area */
28318776 547 column -= mtd->writesize;
1da177e4
LT		 548 readcmd = NAND_CMD_READOOB;
549 } else if (column < 256) {
550 /* First 256 bytes --> READ0 */
551 readcmd = NAND_CMD_READ0;
552 } else {
553 column -= 256;
554 readcmd = NAND_CMD_READ1;
555 }
ace4dfee 556 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 557 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 558 }
ace4dfee 559 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 560
8b6e50c9 561 /* Address cycle, when necessary */
7abd3ef9
TG		 562 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
563 /* Serially input address */
564 if (column != -1) {
565 /* Adjust columns for 16 bit buswidth */
ace4dfee 566 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 567 column >>= 1;
ace4dfee 568 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 569 ctrl &= ~NAND_CTRL_CHANGE;
570 }
571 if (page_addr != -1) {
ace4dfee 572 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 573 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 574 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 575 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 576 if (chip->chipsize > (32 << 20))
577 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 578 }
ace4dfee 579 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 580
581 /*
8b6e50c9
BN		 582 * Program and erase have their own busy handlers status and sequential
583 * in needs no delay
e0c7d767 584 */
1da177e4 585 switch (command) {
61b03bd7 586
1da177e4
LT		 587 case NAND_CMD_PAGEPROG:
588 case NAND_CMD_ERASE1:
589 case NAND_CMD_ERASE2:
590 case NAND_CMD_SEQIN:
591 case NAND_CMD_STATUS:
592 return;
593
594 case NAND_CMD_RESET:
ace4dfee 595 if (chip->dev_ready)
1da177e4 596 break;
ace4dfee
TG		 597 udelay(chip->chip_delay);
598 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 599 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 600 chip->cmd_ctrl(mtd,
601 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 602 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
603 ;
1da177e4
LT		 604 return;
605
e0c7d767 606 /* This applies to read commands */
1da177e4 607 default:
61b03bd7 608 /*
1da177e4
LT		 609 * If we don't have access to the busy pin, we apply the given
610 * command delay
e0c7d767 611 */
ace4dfee
TG		 612 if (!chip->dev_ready) {
613 udelay(chip->chip_delay);
1da177e4 614 return;
61b03bd7 615 }
1da177e4 616 }
8b6e50c9
BN		 617 /*
618 * Apply this short delay always to ensure that we do wait tWB in
619 * any case on any machine.
620 */
e0c7d767 621 ndelay(100);
3b88775c
TG		 622
623 nand_wait_ready(mtd);
1da177e4
LT		 624}
625
626/**
627 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 628 * @mtd: MTD device structure
629 * @command: the command to be sent
630 * @column: the column address for this command, -1 if none
631 * @page_addr: the page address for this command, -1 if none
1da177e4 632 *
7abd3ef9 633 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 634 * devices. We don't have the separate regions as we have in the small page
635 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 636 */
7abd3ef9
TG		 637static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
638 int column, int page_addr)
1da177e4 639{
ace4dfee 640 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 641
642 /* Emulate NAND_CMD_READOOB */
643 if (command == NAND_CMD_READOOB) {
28318776 644 column += mtd->writesize;
1da177e4
LT		 645 command = NAND_CMD_READ0;
646 }
61b03bd7 647
7abd3ef9 648 /* Command latch cycle */
ace4dfee 649 chip->cmd_ctrl(mtd, command & 0xff,
7abd3ef9 650 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 651
652 if (column != -1 || page_addr != -1) {
7abd3ef9 653 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 654
655 /* Serially input address */
656 if (column != -1) {
657 /* Adjust columns for 16 bit buswidth */
ace4dfee 658 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 659 column >>= 1;
ace4dfee 660 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 661 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 662 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 663 }
1da177e4 664 if (page_addr != -1) {
ace4dfee
TG		 665 chip->cmd_ctrl(mtd, page_addr, ctrl);
666 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 667 NAND_NCE | NAND_ALE);
1da177e4 668 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 669 if (chip->chipsize > (128 << 20))
670 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 671 NAND_NCE | NAND_ALE);
1da177e4 672 }
1da177e4 673 }
ace4dfee 674 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 675
676 /*
8b6e50c9
BN		 677 * Program and erase have their own busy handlers status, sequential
678 * in, and deplete1 need no delay.
30f464b7 679 */
1da177e4 680 switch (command) {
61b03bd7 681
1da177e4
LT		 682 case NAND_CMD_CACHEDPROG:
683 case NAND_CMD_PAGEPROG:
684 case NAND_CMD_ERASE1:
685 case NAND_CMD_ERASE2:
686 case NAND_CMD_SEQIN:
7bc3312b 687 case NAND_CMD_RNDIN:
1da177e4 688 case NAND_CMD_STATUS:
30f464b7 689 case NAND_CMD_DEPLETE1:
1da177e4
LT		 690 return;
691
30f464b7
DM		 692 case NAND_CMD_STATUS_ERROR:
693 case NAND_CMD_STATUS_ERROR0:
694 case NAND_CMD_STATUS_ERROR1:
695 case NAND_CMD_STATUS_ERROR2:
696 case NAND_CMD_STATUS_ERROR3:
8b6e50c9 697 /* Read error status commands require only a short delay */
ace4dfee 698 udelay(chip->chip_delay);
30f464b7 699 return;
1da177e4
LT		 700
701 case NAND_CMD_RESET:
ace4dfee 702 if (chip->dev_ready)
1da177e4 703 break;
ace4dfee 704 udelay(chip->chip_delay);
12efdde3
TG		 705 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
706 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
707 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
708 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 709 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
710 ;
1da177e4
LT		 711 return;
712
7bc3312b
TG		 713 case NAND_CMD_RNDOUT:
714 /* No ready / busy check necessary */
715 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
716 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
717 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
718 NAND_NCE | NAND_CTRL_CHANGE);
719 return;
720
1da177e4 721 case NAND_CMD_READ0:
12efdde3
TG		 722 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
723 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
724 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
725 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 726
e0c7d767 727 /* This applies to read commands */
1da177e4 728 default:
61b03bd7 729 /*
1da177e4 730 * If we don't have access to the busy pin, we apply the given
8b6e50c9 731 * command delay.
e0c7d767 732 */
ace4dfee
TG		 733 if (!chip->dev_ready) {
734 udelay(chip->chip_delay);
1da177e4 735 return;
61b03bd7 736 }
1da177e4 737 }
3b88775c 738
8b6e50c9
BN		 739 /*
740 * Apply this short delay always to ensure that we do wait tWB in
741 * any case on any machine.
742 */
e0c7d767 743 ndelay(100);
3b88775c
TG		 744
745 nand_wait_ready(mtd);
1da177e4
LT		 746}
747
2af7c653
SK		 748/**
749 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 750 * @chip: the nand chip descriptor
751 * @mtd: MTD device structure
752 * @new_state: the state which is requested
2af7c653
SK		 753 *
754 * Used when in panic, no locks are taken.
755 */
756static void panic_nand_get_device(struct nand_chip *chip,
757 struct mtd_info *mtd, int new_state)
758{
7854d3f7 759 /* Hardware controller shared among independent devices */
2af7c653
SK		 760 chip->controller->active = chip;
761 chip->state = new_state;
762}
763
1da177e4
LT		 764/**
765 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 766 * @chip: the nand chip descriptor
767 * @mtd: MTD device structure
768 * @new_state: the state which is requested
1da177e4
LT		 769 *
770 * Get the device and lock it for exclusive access
771 */
2c0a2bed 772static int
ace4dfee 773nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
1da177e4 774{
ace4dfee
TG		 775 spinlock_t *lock = &chip->controller->lock;
776 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 777 DECLARE_WAITQUEUE(wait, current);
7351d3a5 778retry:
0dfc6246
TG		 779 spin_lock(lock);
780
b8b3ee9a 781 /* Hardware controller shared among independent devices */
ace4dfee
TG		 782 if (!chip->controller->active)
783 chip->controller->active = chip;
a36ed299 784
ace4dfee
TG		 785 if (chip->controller->active == chip && chip->state == FL_READY) {
786 chip->state = new_state;
0dfc6246 787 spin_unlock(lock);
962034f4
VW		 788 return 0;
789 }
790 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 791 if (chip->controller->active->state == FL_PM_SUSPENDED) {
792 chip->state = FL_PM_SUSPENDED;
793 spin_unlock(lock);
794 return 0;
6b0d9a84 795 }
0dfc6246
TG		 796 }
797 set_current_state(TASK_UNINTERRUPTIBLE);
798 add_wait_queue(wq, &wait);
799 spin_unlock(lock);
800 schedule();
801 remove_wait_queue(wq, &wait);
1da177e4
LT		 802 goto retry;
803}
804
2af7c653 805/**
8b6e50c9
BN		 806 * panic_nand_wait - [GENERIC] wait until the command is done
807 * @mtd: MTD device structure
808 * @chip: NAND chip structure
809 * @timeo: timeout
2af7c653
SK		 810 *
811 * Wait for command done. This is a helper function for nand_wait used when
812 * we are in interrupt context. May happen when in panic and trying to write
b595076a 813 * an oops through mtdoops.
2af7c653
SK		 814 */
815static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
816 unsigned long timeo)
817{
818 int i;
819 for (i = 0; i < timeo; i++) {
820 if (chip->dev_ready) {
821 if (chip->dev_ready(mtd))
822 break;
823 } else {
824 if (chip->read_byte(mtd) & NAND_STATUS_READY)
825 break;
826 }
827 mdelay(1);
f8ac0414 828 }
2af7c653
SK		 829}
830
1da177e4 831/**
8b6e50c9
BN		 832 * nand_wait - [DEFAULT] wait until the command is done
833 * @mtd: MTD device structure
834 * @chip: NAND chip structure
1da177e4 835 *
8b6e50c9
BN		 836 * Wait for command done. This applies to erase and program only. Erase can
837 * take up to 400ms and program up to 20ms according to general NAND and
838 * SmartMedia specs.
844d3b42 839 */
7bc3312b 840static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 841{
842
e0c7d767 843 unsigned long timeo = jiffies;
7bc3312b 844 int status, state = chip->state;
61b03bd7 845
1da177e4 846 if (state == FL_ERASING)
e0c7d767 847 timeo += (HZ * 400) / 1000;
1da177e4 848 else
e0c7d767 849 timeo += (HZ * 20) / 1000;
1da177e4 850
8fe833c1
RP		 851 led_trigger_event(nand_led_trigger, LED_FULL);
852
8b6e50c9
BN		 853 /*
854 * Apply this short delay always to ensure that we do wait tWB in any
855 * case on any machine.
856 */
e0c7d767 857 ndelay(100);
1da177e4 858
ace4dfee
TG		 859 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
860 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
61b03bd7 861 else
ace4dfee 862 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 863
2af7c653
SK		 864 if (in_interrupt() || oops_in_progress)
865 panic_nand_wait(mtd, chip, timeo);
866 else {
867 while (time_before(jiffies, timeo)) {
868 if (chip->dev_ready) {
869 if (chip->dev_ready(mtd))
870 break;
871 } else {
872 if (chip->read_byte(mtd) & NAND_STATUS_READY)
873 break;
874 }
875 cond_resched();
1da177e4 876 }
1da177e4 877 }
8fe833c1
RP		 878 led_trigger_event(nand_led_trigger, LED_OFF);
879
ace4dfee 880 status = (int)chip->read_byte(mtd);
1da177e4
LT		 881 return status;
882}
883
7d70f334 884/**
b6d676db 885 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 886 * @mtd: mtd info
887 * @ofs: offset to start unlock from
888 * @len: length to unlock
8b6e50c9
BN		 889 * @invert: when = 0, unlock the range of blocks within the lower and
890 * upper boundary address
891 * when = 1, unlock the range of blocks outside the boundaries
892 * of the lower and upper boundary address
7d70f334 893 *
8b6e50c9 894 * Returs unlock status.
7d70f334
VS		 895 */
896static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
897 uint64_t len, int invert)
898{
899 int ret = 0;
900 int status, page;
901 struct nand_chip *chip = mtd->priv;
902
903 /* Submit address of first page to unlock */
904 page = ofs >> chip->page_shift;
905 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
906
907 /* Submit address of last page to unlock */
908 page = (ofs + len) >> chip->page_shift;
909 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
910 (page | invert) & chip->pagemask);
911
912 /* Call wait ready function */
913 status = chip->waitfunc(mtd, chip);
7d70f334
VS		 914 /* See if device thinks it succeeded */
915 if (status & 0x01) {
916 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
917 __func__, status);
918 ret = -EIO;
919 }
920
921 return ret;
922}
923
924/**
b6d676db 925 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 926 * @mtd: mtd info
927 * @ofs: offset to start unlock from
928 * @len: length to unlock
7d70f334 929 *
8b6e50c9 930 * Returns unlock status.
7d70f334
VS		 931 */
932int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
933{
934 int ret = 0;
935 int chipnr;
936 struct nand_chip *chip = mtd->priv;
937
938 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
939 __func__, (unsigned long long)ofs, len);
940
941 if (check_offs_len(mtd, ofs, len))
942 ret = -EINVAL;
943
944 /* Align to last block address if size addresses end of the device */
945 if (ofs + len == mtd->size)
946 len -= mtd->erasesize;
947
948 nand_get_device(chip, mtd, FL_UNLOCKING);
949
950 /* Shift to get chip number */
951 chipnr = ofs >> chip->chip_shift;
952
953 chip->select_chip(mtd, chipnr);
954
955 /* Check, if it is write protected */
956 if (nand_check_wp(mtd)) {
957 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
958 __func__);
959 ret = -EIO;
960 goto out;
961 }
962
963 ret = __nand_unlock(mtd, ofs, len, 0);
964
965out:
7d70f334
VS		 966 nand_release_device(mtd);
967
968 return ret;
969}
7351d3a5 970EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 971
972/**
b6d676db 973 * nand_lock - [REPLACEABLE] locks all blocks present in the device
b6d676db
RD		 974 * @mtd: mtd info
975 * @ofs: offset to start unlock from
976 * @len: length to unlock
7d70f334 977 *
8b6e50c9
BN		 978 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
979 * have this feature, but it allows only to lock all blocks, not for specified
980 * range for block. Implementing 'lock' feature by making use of 'unlock', for
981 * now.
7d70f334 982 *
8b6e50c9 983 * Returns lock status.
7d70f334
VS		 984 */
985int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
986{
987 int ret = 0;
988 int chipnr, status, page;
989 struct nand_chip *chip = mtd->priv;
990
991 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
992 __func__, (unsigned long long)ofs, len);
993
994 if (check_offs_len(mtd, ofs, len))
995 ret = -EINVAL;
996
997 nand_get_device(chip, mtd, FL_LOCKING);
998
999 /* Shift to get chip number */
1000 chipnr = ofs >> chip->chip_shift;
1001
1002 chip->select_chip(mtd, chipnr);
1003
1004 /* Check, if it is write protected */
1005 if (nand_check_wp(mtd)) {
1006 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
1007 __func__);
1008 status = MTD_ERASE_FAILED;
1009 ret = -EIO;
1010 goto out;
1011 }
1012
1013 /* Submit address of first page to lock */
1014 page = ofs >> chip->page_shift;
1015 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1016
1017 /* Call wait ready function */
1018 status = chip->waitfunc(mtd, chip);
7d70f334
VS		 1019 /* See if device thinks it succeeded */
1020 if (status & 0x01) {
1021 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
1022 __func__, status);
1023 ret = -EIO;
1024 goto out;
1025 }
1026
1027 ret = __nand_unlock(mtd, ofs, len, 0x1);
1028
1029out:
7d70f334
VS		 1030 nand_release_device(mtd);
1031
1032 return ret;
1033}
7351d3a5 1034EXPORT_SYMBOL(nand_lock);
7d70f334 1035
8593fbc6 1036/**
7854d3f7 1037 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1038 * @mtd: mtd info structure
1039 * @chip: nand chip info structure
1040 * @buf: buffer to store read data
1041 * @page: page number to read
52ff49df 1042 *
7854d3f7 1043 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1044 */
1045static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1046 uint8_t *buf, int page)
8593fbc6
TG		 1047{
1048 chip->read_buf(mtd, buf, mtd->writesize);
1049 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1050 return 0;
1051}
1052
52ff49df 1053/**
7854d3f7 1054 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1055 * @mtd: mtd info structure
1056 * @chip: nand chip info structure
1057 * @buf: buffer to store read data
1058 * @page: page number to read
52ff49df
DB		 1059 *
1060 * We need a special oob layout and handling even when OOB isn't used.
1061 */
7351d3a5
FF		 1062static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1063 struct nand_chip *chip,
1064 uint8_t *buf, int page)
52ff49df
DB		 1065{
1066 int eccsize = chip->ecc.size;
1067 int eccbytes = chip->ecc.bytes;
1068 uint8_t *oob = chip->oob_poi;
1069 int steps, size;
1070
1071 for (steps = chip->ecc.steps; steps > 0; steps--) {
1072 chip->read_buf(mtd, buf, eccsize);
1073 buf += eccsize;
1074
1075 if (chip->ecc.prepad) {
1076 chip->read_buf(mtd, oob, chip->ecc.prepad);
1077 oob += chip->ecc.prepad;
1078 }
1079
1080 chip->read_buf(mtd, oob, eccbytes);
1081 oob += eccbytes;
1082
1083 if (chip->ecc.postpad) {
1084 chip->read_buf(mtd, oob, chip->ecc.postpad);
1085 oob += chip->ecc.postpad;
1086 }
1087 }
1088
1089 size = mtd->oobsize - (oob - chip->oob_poi);
1090 if (size)
1091 chip->read_buf(mtd, oob, size);
1092
1093 return 0;
1094}
1095
1da177e4 1096/**
7854d3f7 1097 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1098 * @mtd: mtd info structure
1099 * @chip: nand chip info structure
1100 * @buf: buffer to store read data
1101 * @page: page number to read
068e3c0a 1102 */
f5bbdacc 1103static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1104 uint8_t *buf, int page)
1da177e4 1105{
f5bbdacc
TG		 1106 int i, eccsize = chip->ecc.size;
1107 int eccbytes = chip->ecc.bytes;
1108 int eccsteps = chip->ecc.steps;
1109 uint8_t *p = buf;
4bf63fcb
DW		 1110 uint8_t *ecc_calc = chip->buffers->ecccalc;
1111 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1112 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc 1113
46a8cf2d 1114 chip->ecc.read_page_raw(mtd, chip, buf, page);
f5bbdacc
TG		 1115
1116 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1117 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1118
1119 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1120 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1121
1122 eccsteps = chip->ecc.steps;
1123 p = buf;
1124
1125 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1126 int stat;
1127
1128 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1129 if (stat < 0)
f5bbdacc
TG		 1130 mtd->ecc_stats.failed++;
1131 else
1132 mtd->ecc_stats.corrected += stat;
1133 }
1134 return 0;
22c60f5f 1135}
1da177e4 1136
3d459559 1137/**
7854d3f7 1138 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
8b6e50c9
BN		 1139 * @mtd: mtd info structure
1140 * @chip: nand chip info structure
1141 * @data_offs: offset of requested data within the page
1142 * @readlen: data length
1143 * @bufpoi: buffer to store read data
3d459559 1144 */
7351d3a5
FF		 1145static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1146 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
3d459559
AK		 1147{
1148 int start_step, end_step, num_steps;
1149 uint32_t *eccpos = chip->ecc.layout->eccpos;
1150 uint8_t *p;
1151 int data_col_addr, i, gaps = 0;
1152 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1153 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
7351d3a5 1154 int index = 0;
3d459559 1155
7854d3f7 1156 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1157 start_step = data_offs / chip->ecc.size;
1158 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1159 num_steps = end_step - start_step + 1;
1160
8b6e50c9 1161 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1162 datafrag_len = num_steps * chip->ecc.size;
1163 eccfrag_len = num_steps * chip->ecc.bytes;
1164
1165 data_col_addr = start_step * chip->ecc.size;
1166 /* If we read not a page aligned data */
1167 if (data_col_addr != 0)
1168 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1169
1170 p = bufpoi + data_col_addr;
1171 chip->read_buf(mtd, p, datafrag_len);
1172
8b6e50c9 1173 /* Calculate ECC */
3d459559
AK		 1174 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1175 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1176
8b6e50c9
BN		 1177 /*
1178 * The performance is faster if we position offsets according to
7854d3f7 1179 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1180 */
3d459559
AK		 1181 for (i = 0; i < eccfrag_len - 1; i++) {
1182 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1183 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1184 gaps = 1;
1185 break;
1186 }
1187 }
1188 if (gaps) {
1189 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1190 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1191 } else {
8b6e50c9 1192 /*
7854d3f7 1193 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1194 * about buswidth alignment in read_buf.
1195 */
7351d3a5
FF		 1196 index = start_step * chip->ecc.bytes;
1197
1198 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1199 aligned_len = eccfrag_len;
7351d3a5 1200 if (eccpos[index] & (busw - 1))
3d459559 1201 aligned_len++;
7351d3a5 1202 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1203 aligned_len++;
1204
7351d3a5
FF		 1205 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1206 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1207 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1208 }
1209
1210 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1211 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1212
1213 p = bufpoi + data_col_addr;
1214 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1215 int stat;
1216
7351d3a5
FF		 1217 stat = chip->ecc.correct(mtd, p,
1218 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
12c8eb98 1219 if (stat < 0)
3d459559
AK		 1220 mtd->ecc_stats.failed++;
1221 else
1222 mtd->ecc_stats.corrected += stat;
1223 }
1224 return 0;
1225}
1226
068e3c0a 1227/**
7854d3f7 1228 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1229 * @mtd: mtd info structure
1230 * @chip: nand chip info structure
1231 * @buf: buffer to store read data
1232 * @page: page number to read
068e3c0a 1233 *
7854d3f7 1234 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1235 */
f5bbdacc 1236static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1237 uint8_t *buf, int page)
1da177e4 1238{
f5bbdacc
TG		 1239 int i, eccsize = chip->ecc.size;
1240 int eccbytes = chip->ecc.bytes;
1241 int eccsteps = chip->ecc.steps;
1242 uint8_t *p = buf;
4bf63fcb
DW		 1243 uint8_t *ecc_calc = chip->buffers->ecccalc;
1244 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1245 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc
TG		 1246
1247 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1248 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1249 chip->read_buf(mtd, p, eccsize);
1250 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1251 }
f75e5097 1252 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1253
f5bbdacc 1254 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1255 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1256
f5bbdacc
TG		 1257 eccsteps = chip->ecc.steps;
1258 p = buf;
61b03bd7 1259
f5bbdacc
TG		 1260 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1261 int stat;
1da177e4 1262
f5bbdacc 1263 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1264 if (stat < 0)
f5bbdacc
TG		 1265 mtd->ecc_stats.failed++;
1266 else
1267 mtd->ecc_stats.corrected += stat;
1268 }
1269 return 0;
1270}
1da177e4 1271
6e0cb135 1272/**
7854d3f7 1273 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1274 * @mtd: mtd info structure
1275 * @chip: nand chip info structure
1276 * @buf: buffer to store read data
1277 * @page: page number to read
6e0cb135 1278 *
8b6e50c9
BN		 1279 * Hardware ECC for large page chips, require OOB to be read first. For this
1280 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1281 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1282 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1283 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1284 */
1285static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1286 struct nand_chip *chip, uint8_t *buf, int page)
1287{
1288 int i, eccsize = chip->ecc.size;
1289 int eccbytes = chip->ecc.bytes;
1290 int eccsteps = chip->ecc.steps;
1291 uint8_t *p = buf;
1292 uint8_t *ecc_code = chip->buffers->ecccode;
1293 uint32_t *eccpos = chip->ecc.layout->eccpos;
1294 uint8_t *ecc_calc = chip->buffers->ecccalc;
1295
1296 /* Read the OOB area first */
1297 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1298 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1299 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1300
1301 for (i = 0; i < chip->ecc.total; i++)
1302 ecc_code[i] = chip->oob_poi[eccpos[i]];
1303
1304 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1305 int stat;
1306
1307 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1308 chip->read_buf(mtd, p, eccsize);
1309 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1310
1311 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1312 if (stat < 0)
1313 mtd->ecc_stats.failed++;
1314 else
1315 mtd->ecc_stats.corrected += stat;
1316 }
1317 return 0;
1318}
1319
f5bbdacc 1320/**
7854d3f7 1321 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1322 * @mtd: mtd info structure
1323 * @chip: nand chip info structure
1324 * @buf: buffer to store read data
1325 * @page: page number to read
f5bbdacc 1326 *
8b6e50c9
BN		 1327 * The hw generator calculates the error syndrome automatically. Therefore we
1328 * need a special oob layout and handling.
f5bbdacc
TG		 1329 */
1330static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1331 uint8_t *buf, int page)
f5bbdacc
TG		 1332{
1333 int i, eccsize = chip->ecc.size;
1334 int eccbytes = chip->ecc.bytes;
1335 int eccsteps = chip->ecc.steps;
1336 uint8_t *p = buf;
f75e5097 1337 uint8_t *oob = chip->oob_poi;
1da177e4 1338
f5bbdacc
TG		 1339 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1340 int stat;
61b03bd7 1341
f5bbdacc
TG		 1342 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1343 chip->read_buf(mtd, p, eccsize);
1da177e4 1344
f5bbdacc
TG		 1345 if (chip->ecc.prepad) {
1346 chip->read_buf(mtd, oob, chip->ecc.prepad);
1347 oob += chip->ecc.prepad;
1348 }
1da177e4 1349
f5bbdacc
TG		 1350 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1351 chip->read_buf(mtd, oob, eccbytes);
1352 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1353
c32b8dcc 1354 if (stat < 0)
f5bbdacc 1355 mtd->ecc_stats.failed++;
61b03bd7 1356 else
f5bbdacc 1357 mtd->ecc_stats.corrected += stat;
61b03bd7 1358
f5bbdacc 1359 oob += eccbytes;
1da177e4 1360
f5bbdacc
TG		 1361 if (chip->ecc.postpad) {
1362 chip->read_buf(mtd, oob, chip->ecc.postpad);
1363 oob += chip->ecc.postpad;
61b03bd7 1364 }
f5bbdacc 1365 }
1da177e4 1366
f5bbdacc 1367 /* Calculate remaining oob bytes */
7e4178f9 1368 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1369 if (i)
1370 chip->read_buf(mtd, oob, i);
61b03bd7 1371
f5bbdacc
TG		 1372 return 0;
1373}
1da177e4 1374
f5bbdacc 1375/**
7854d3f7 1376 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
8b6e50c9
BN		 1377 * @chip: nand chip structure
1378 * @oob: oob destination address
1379 * @ops: oob ops structure
1380 * @len: size of oob to transfer
8593fbc6
TG		 1381 */
1382static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1383 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1384{
f8ac0414 1385 switch (ops->mode) {
8593fbc6
TG		 1386
1387 case MTD_OOB_PLACE:
1388 case MTD_OOB_RAW:
1389 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1390 return oob + len;
1391
1392 case MTD_OOB_AUTO: {
1393 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1394 uint32_t boffs = 0, roffs = ops->ooboffs;
1395 size_t bytes = 0;
8593fbc6 1396
f8ac0414 1397 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 1398 /* Read request not from offset 0? */
7bc3312b
TG		 1399 if (unlikely(roffs)) {
1400 if (roffs >= free->length) {
1401 roffs -= free->length;
1402 continue;
1403 }
1404 boffs = free->offset + roffs;
1405 bytes = min_t(size_t, len,
1406 (free->length - roffs));
1407 roffs = 0;
1408 } else {
1409 bytes = min_t(size_t, len, free->length);
1410 boffs = free->offset;
1411 }
1412 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1413 oob += bytes;
1414 }
1415 return oob;
1416 }
1417 default:
1418 BUG();
1419 }
1420 return NULL;
1421}
1422
1423/**
7854d3f7 1424 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1425 * @mtd: MTD device structure
1426 * @from: offset to read from
1427 * @ops: oob ops structure
f5bbdacc
TG		 1428 *
1429 * Internal function. Called with chip held.
1430 */
8593fbc6
TG		 1431static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1432 struct mtd_oob_ops *ops)
f5bbdacc
TG		 1433{
1434 int chipnr, page, realpage, col, bytes, aligned;
1435 struct nand_chip *chip = mtd->priv;
1436 struct mtd_ecc_stats stats;
1437 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1438 int sndcmd = 1;
1439 int ret = 0;
8593fbc6 1440 uint32_t readlen = ops->len;
7014568b 1441 uint32_t oobreadlen = ops->ooblen;
9aca334e
ML		 1442 uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1443 mtd->oobavail : mtd->oobsize;
1444
8593fbc6 1445 uint8_t *bufpoi, *oob, *buf;
1da177e4 1446
f5bbdacc 1447 stats = mtd->ecc_stats;
1da177e4 1448
f5bbdacc
TG		 1449 chipnr = (int)(from >> chip->chip_shift);
1450 chip->select_chip(mtd, chipnr);
61b03bd7 1451
f5bbdacc
TG		 1452 realpage = (int)(from >> chip->page_shift);
1453 page = realpage & chip->pagemask;
1da177e4 1454
f5bbdacc 1455 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1456
8593fbc6
TG		 1457 buf = ops->datbuf;
1458 oob = ops->oobbuf;
1459
f8ac0414 1460 while (1) {
f5bbdacc
TG		 1461 bytes = min(mtd->writesize - col, readlen);
1462 aligned = (bytes == mtd->writesize);
61b03bd7 1463
8b6e50c9 1464 /* Is the current page in the buffer? */
8593fbc6 1465 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1466 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1467
f5bbdacc
TG		 1468 if (likely(sndcmd)) {
1469 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1470 sndcmd = 0;
1da177e4 1471 }
1da177e4 1472
f5bbdacc 1473 /* Now read the page into the buffer */
956e944c 1474 if (unlikely(ops->mode == MTD_OOB_RAW))
46a8cf2d
SN		 1475 ret = chip->ecc.read_page_raw(mtd, chip,
1476 bufpoi, page);
3d459559 1477 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
7351d3a5
FF		 1478 ret = chip->ecc.read_subpage(mtd, chip,
1479 col, bytes, bufpoi);
956e944c 1480 else
46a8cf2d
SN		 1481 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1482 page);
f5bbdacc 1483 if (ret < 0)
1da177e4 1484 break;
f5bbdacc
TG		 1485
1486 /* Transfer not aligned data */
1487 if (!aligned) {
c1194c79
AB		 1488 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1489 !(mtd->ecc_stats.failed - stats.failed))
3d459559 1490 chip->pagebuf = realpage;
4bf63fcb 1491 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1492 }
1493
8593fbc6
TG		 1494 buf += bytes;
1495
1496 if (unlikely(oob)) {
9aca334e 1497
b64d39d8
ML		 1498 int toread = min(oobreadlen, max_oobsize);
1499
1500 if (toread) {
1501 oob = nand_transfer_oob(chip,
1502 oob, ops, toread);
1503 oobreadlen -= toread;
1504 }
8593fbc6
TG		 1505 }
1506
f5bbdacc
TG		 1507 if (!(chip->options & NAND_NO_READRDY)) {
1508 /*
1509 * Apply delay or wait for ready/busy pin. Do
1510 * this before the AUTOINCR check, so no
1511 * problems arise if a chip which does auto
1512 * increment is marked as NOAUTOINCR by the
1513 * board driver.
1514 */
1515 if (!chip->dev_ready)
1516 udelay(chip->chip_delay);
1517 else
1518 nand_wait_ready(mtd);
1da177e4 1519 }
8593fbc6 1520 } else {
4bf63fcb 1521 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6
TG		 1522 buf += bytes;
1523 }
1da177e4 1524
f5bbdacc 1525 readlen -= bytes;
61b03bd7 1526
f5bbdacc 1527 if (!readlen)
61b03bd7 1528 break;
1da177e4 1529
8b6e50c9 1530 /* For subsequent reads align to page boundary */
1da177e4
LT		 1531 col = 0;
1532 /* Increment page address */
1533 realpage++;
1534
ace4dfee 1535 page = realpage & chip->pagemask;
1da177e4
LT		 1536 /* Check, if we cross a chip boundary */
1537 if (!page) {
1538 chipnr++;
ace4dfee
TG		 1539 chip->select_chip(mtd, -1);
1540 chip->select_chip(mtd, chipnr);
1da177e4 1541 }
f5bbdacc 1542
8b6e50c9
BN		 1543 /*
1544 * Check, if the chip supports auto page increment or if we
1545 * have hit a block boundary.
e0c7d767 1546 */
f5bbdacc 1547 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
61b03bd7 1548 sndcmd = 1;
1da177e4
LT		 1549 }
1550
8593fbc6 1551 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1552 if (oob)
1553 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1554
f5bbdacc
TG		 1555 if (ret)
1556 return ret;
1557
9a1fcdfd
TG		 1558 if (mtd->ecc_stats.failed - stats.failed)
1559 return -EBADMSG;
1560
1561 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
f5bbdacc
TG		 1562}
1563
1564/**
25985edc 1565 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 1566 * @mtd: MTD device structure
1567 * @from: offset to read from
1568 * @len: number of bytes to read
1569 * @retlen: pointer to variable to store the number of read bytes
1570 * @buf: the databuffer to put data
f5bbdacc 1571 *
8b6e50c9 1572 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 1573 */
1574static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1575 size_t *retlen, uint8_t *buf)
1576{
8593fbc6 1577 struct nand_chip *chip = mtd->priv;
f5bbdacc
TG		 1578 int ret;
1579
f5bbdacc
TG		 1580 /* Do not allow reads past end of device */
1581 if ((from + len) > mtd->size)
1582 return -EINVAL;
1583 if (!len)
1584 return 0;
1585
8593fbc6 1586 nand_get_device(chip, mtd, FL_READING);
f5bbdacc 1587
8593fbc6
TG		 1588 chip->ops.len = len;
1589 chip->ops.datbuf = buf;
1590 chip->ops.oobbuf = NULL;
1591
1592 ret = nand_do_read_ops(mtd, from, &chip->ops);
f5bbdacc 1593
7fd5aecc
RP		 1594 *retlen = chip->ops.retlen;
1595
f5bbdacc
TG		 1596 nand_release_device(mtd);
1597
1598 return ret;
1da177e4
LT		 1599}
1600
7bc3312b 1601/**
7854d3f7 1602 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 1603 * @mtd: mtd info structure
1604 * @chip: nand chip info structure
1605 * @page: page number to read
1606 * @sndcmd: flag whether to issue read command or not
7bc3312b
TG		 1607 */
1608static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1609 int page, int sndcmd)
1610{
1611 if (sndcmd) {
1612 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1613 sndcmd = 0;
1614 }
1615 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1616 return sndcmd;
1617}
1618
1619/**
7854d3f7 1620 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 1621 * with syndromes
8b6e50c9
BN		 1622 * @mtd: mtd info structure
1623 * @chip: nand chip info structure
1624 * @page: page number to read
1625 * @sndcmd: flag whether to issue read command or not
7bc3312b
TG		 1626 */
1627static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1628 int page, int sndcmd)
1629{
1630 uint8_t *buf = chip->oob_poi;
1631 int length = mtd->oobsize;
1632 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1633 int eccsize = chip->ecc.size;
1634 uint8_t *bufpoi = buf;
1635 int i, toread, sndrnd = 0, pos;
1636
1637 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1638 for (i = 0; i < chip->ecc.steps; i++) {
1639 if (sndrnd) {
1640 pos = eccsize + i * (eccsize + chunk);
1641 if (mtd->writesize > 512)
1642 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1643 else
1644 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1645 } else
1646 sndrnd = 1;
1647 toread = min_t(int, length, chunk);
1648 chip->read_buf(mtd, bufpoi, toread);
1649 bufpoi += toread;
1650 length -= toread;
1651 }
1652 if (length > 0)
1653 chip->read_buf(mtd, bufpoi, length);
1654
1655 return 1;
1656}
1657
1658/**
7854d3f7 1659 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 1660 * @mtd: mtd info structure
1661 * @chip: nand chip info structure
1662 * @page: page number to write
7bc3312b
TG		 1663 */
1664static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1665 int page)
1666{
1667 int status = 0;
1668 const uint8_t *buf = chip->oob_poi;
1669 int length = mtd->oobsize;
1670
1671 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1672 chip->write_buf(mtd, buf, length);
1673 /* Send command to program the OOB data */
1674 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1675
1676 status = chip->waitfunc(mtd, chip);
1677
0d420f9d 1678 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1679}
1680
1681/**
7854d3f7 1682 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 1683 * with syndrome - only for large page flash
1684 * @mtd: mtd info structure
1685 * @chip: nand chip info structure
1686 * @page: page number to write
7bc3312b
TG		 1687 */
1688static int nand_write_oob_syndrome(struct mtd_info *mtd,
1689 struct nand_chip *chip, int page)
1690{
1691 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1692 int eccsize = chip->ecc.size, length = mtd->oobsize;
1693 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1694 const uint8_t *bufpoi = chip->oob_poi;
1695
1696 /*
1697 * data-ecc-data-ecc ... ecc-oob
1698 * or
1699 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1700 */
1701 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1702 pos = steps * (eccsize + chunk);
1703 steps = 0;
1704 } else
8b0036ee 1705 pos = eccsize;
7bc3312b
TG		 1706
1707 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1708 for (i = 0; i < steps; i++) {
1709 if (sndcmd) {
1710 if (mtd->writesize <= 512) {
1711 uint32_t fill = 0xFFFFFFFF;
1712
1713 len = eccsize;
1714 while (len > 0) {
1715 int num = min_t(int, len, 4);
1716 chip->write_buf(mtd, (uint8_t *)&fill,
1717 num);
1718 len -= num;
1719 }
1720 } else {
1721 pos = eccsize + i * (eccsize + chunk);
1722 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1723 }
1724 } else
1725 sndcmd = 1;
1726 len = min_t(int, length, chunk);
1727 chip->write_buf(mtd, bufpoi, len);
1728 bufpoi += len;
1729 length -= len;
1730 }
1731 if (length > 0)
1732 chip->write_buf(mtd, bufpoi, length);
1733
1734 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1735 status = chip->waitfunc(mtd, chip);
1736
1737 return status & NAND_STATUS_FAIL ? -EIO : 0;
1738}
1739
1da177e4 1740/**
7854d3f7 1741 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 1742 * @mtd: MTD device structure
1743 * @from: offset to read from
1744 * @ops: oob operations description structure
1da177e4 1745 *
8b6e50c9 1746 * NAND read out-of-band data from the spare area.
1da177e4 1747 */
8593fbc6
TG		 1748static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1749 struct mtd_oob_ops *ops)
1da177e4 1750{
7bc3312b 1751 int page, realpage, chipnr, sndcmd = 1;
ace4dfee 1752 struct nand_chip *chip = mtd->priv;
7314e9e7 1753 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
7014568b
VW		 1754 int readlen = ops->ooblen;
1755 int len;
7bc3312b 1756 uint8_t *buf = ops->oobbuf;
61b03bd7 1757
20d8e248 1758 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1759 __func__, (unsigned long long)from, readlen);
1da177e4 1760
03736155 1761 if (ops->mode == MTD_OOB_AUTO)
7014568b 1762 len = chip->ecc.layout->oobavail;
03736155
AH		 1763 else
1764 len = mtd->oobsize;
1765
1766 if (unlikely(ops->ooboffs >= len)) {
20d8e248 1767 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1768 "outside oob\n", __func__);
03736155
AH		 1769 return -EINVAL;
1770 }
1771
1772 /* Do not allow reads past end of device */
1773 if (unlikely(from >= mtd->size ||
1774 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1775 (from >> chip->page_shift)) * len)) {
20d8e248 1776 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1777 "of device\n", __func__);
03736155
AH		 1778 return -EINVAL;
1779 }
7014568b 1780
7314e9e7 1781 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1782 chip->select_chip(mtd, chipnr);
1da177e4 1783
7314e9e7
TG		 1784 /* Shift to get page */
1785 realpage = (int)(from >> chip->page_shift);
1786 page = realpage & chip->pagemask;
1da177e4 1787
f8ac0414 1788 while (1) {
7bc3312b 1789 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
7014568b
VW		 1790
1791 len = min(len, readlen);
1792 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1793
7314e9e7
TG		 1794 if (!(chip->options & NAND_NO_READRDY)) {
1795 /*
1796 * Apply delay or wait for ready/busy pin. Do this
1797 * before the AUTOINCR check, so no problems arise if a
1798 * chip which does auto increment is marked as
1799 * NOAUTOINCR by the board driver.
19870da7 1800 */
ace4dfee
TG		 1801 if (!chip->dev_ready)
1802 udelay(chip->chip_delay);
19870da7
TG		 1803 else
1804 nand_wait_ready(mtd);
7314e9e7 1805 }
19870da7 1806
7014568b 1807 readlen -= len;
0d420f9d
SZ		 1808 if (!readlen)
1809 break;
1810
7314e9e7
TG		 1811 /* Increment page address */
1812 realpage++;
1813
1814 page = realpage & chip->pagemask;
1815 /* Check, if we cross a chip boundary */
1816 if (!page) {
1817 chipnr++;
1818 chip->select_chip(mtd, -1);
1819 chip->select_chip(mtd, chipnr);
1da177e4 1820 }
7314e9e7 1821
8b6e50c9
BN		 1822 /*
1823 * Check, if the chip supports auto page increment or if we
1824 * have hit a block boundary.
7314e9e7
TG		 1825 */
1826 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1827 sndcmd = 1;
1da177e4
LT		 1828 }
1829
7014568b 1830 ops->oobretlen = ops->ooblen;
1da177e4
LT		 1831 return 0;
1832}
1833
1834/**
8593fbc6 1835 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 1836 * @mtd: MTD device structure
1837 * @from: offset to read from
1838 * @ops: oob operation description structure
1da177e4 1839 *
8b6e50c9 1840 * NAND read data and/or out-of-band data.
1da177e4 1841 */
8593fbc6
TG		 1842static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1843 struct mtd_oob_ops *ops)
1da177e4 1844{
ace4dfee 1845 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1846 int ret = -ENOTSUPP;
1847
1848 ops->retlen = 0;
1da177e4
LT		 1849
1850 /* Do not allow reads past end of device */
7014568b 1851 if (ops->datbuf && (from + ops->len) > mtd->size) {
20d8e248 1852 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1853 "beyond end of device\n", __func__);
1da177e4
LT		 1854 return -EINVAL;
1855 }
1856
ace4dfee 1857 nand_get_device(chip, mtd, FL_READING);
1da177e4 1858
f8ac0414 1859 switch (ops->mode) {
8593fbc6
TG		 1860 case MTD_OOB_PLACE:
1861 case MTD_OOB_AUTO:
8593fbc6 1862 case MTD_OOB_RAW:
8593fbc6 1863 break;
1da177e4 1864
8593fbc6
TG		 1865 default:
1866 goto out;
1867 }
1da177e4 1868
8593fbc6
TG		 1869 if (!ops->datbuf)
1870 ret = nand_do_read_oob(mtd, from, ops);
1871 else
1872 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1873
7351d3a5 1874out:
8593fbc6
TG		 1875 nand_release_device(mtd);
1876 return ret;
1877}
61b03bd7 1878
1da177e4 1879
8593fbc6 1880/**
7854d3f7 1881 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 1882 * @mtd: mtd info structure
1883 * @chip: nand chip info structure
1884 * @buf: data buffer
52ff49df 1885 *
7854d3f7 1886 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1887 */
1888static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1889 const uint8_t *buf)
1890{
1891 chip->write_buf(mtd, buf, mtd->writesize);
1892 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4
LT		 1893}
1894
52ff49df 1895/**
7854d3f7 1896 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 1897 * @mtd: mtd info structure
1898 * @chip: nand chip info structure
1899 * @buf: data buffer
52ff49df
DB		 1900 *
1901 * We need a special oob layout and handling even when ECC isn't checked.
1902 */
7351d3a5
FF		 1903static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1904 struct nand_chip *chip,
1905 const uint8_t *buf)
52ff49df
DB		 1906{
1907 int eccsize = chip->ecc.size;
1908 int eccbytes = chip->ecc.bytes;
1909 uint8_t *oob = chip->oob_poi;
1910 int steps, size;
1911
1912 for (steps = chip->ecc.steps; steps > 0; steps--) {
1913 chip->write_buf(mtd, buf, eccsize);
1914 buf += eccsize;
1915
1916 if (chip->ecc.prepad) {
1917 chip->write_buf(mtd, oob, chip->ecc.prepad);
1918 oob += chip->ecc.prepad;
1919 }
1920
1921 chip->read_buf(mtd, oob, eccbytes);
1922 oob += eccbytes;
1923
1924 if (chip->ecc.postpad) {
1925 chip->write_buf(mtd, oob, chip->ecc.postpad);
1926 oob += chip->ecc.postpad;
1927 }
1928 }
1929
1930 size = mtd->oobsize - (oob - chip->oob_poi);
1931 if (size)
1932 chip->write_buf(mtd, oob, size);
1933}
9223a456 1934/**
7854d3f7 1935 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 1936 * @mtd: mtd info structure
1937 * @chip: nand chip info structure
1938 * @buf: data buffer
9223a456 1939 */
f75e5097
TG		 1940static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1941 const uint8_t *buf)
9223a456 1942{
f75e5097
TG		 1943 int i, eccsize = chip->ecc.size;
1944 int eccbytes = chip->ecc.bytes;
1945 int eccsteps = chip->ecc.steps;
4bf63fcb 1946 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1947 const uint8_t *p = buf;
8b099a39 1948 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1949
7854d3f7 1950 /* Software ECC calculation */
8593fbc6
TG		 1951 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1952 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1953
8593fbc6
TG		 1954 for (i = 0; i < chip->ecc.total; i++)
1955 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1956
90424de8 1957 chip->ecc.write_page_raw(mtd, chip, buf);
f75e5097 1958}
9223a456 1959
f75e5097 1960/**
7854d3f7 1961 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 1962 * @mtd: mtd info structure
1963 * @chip: nand chip info structure
1964 * @buf: data buffer
f75e5097
TG		 1965 */
1966static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1967 const uint8_t *buf)
1968{
1969 int i, eccsize = chip->ecc.size;
1970 int eccbytes = chip->ecc.bytes;
1971 int eccsteps = chip->ecc.steps;
4bf63fcb 1972 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1973 const uint8_t *p = buf;
8b099a39 1974 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1975
f75e5097
TG		 1976 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1977 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 1978 chip->write_buf(mtd, p, eccsize);
f75e5097 1979 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 1980 }
1981
f75e5097
TG		 1982 for (i = 0; i < chip->ecc.total; i++)
1983 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1984
1985 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
9223a456
TG		 1986}
1987
61b03bd7 1988/**
7854d3f7 1989 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 1990 * @mtd: mtd info structure
1991 * @chip: nand chip info structure
1992 * @buf: data buffer
1da177e4 1993 *
8b6e50c9
BN		 1994 * The hw generator calculates the error syndrome automatically. Therefore we
1995 * need a special oob layout and handling.
f75e5097
TG		 1996 */
1997static void nand_write_page_syndrome(struct mtd_info *mtd,
1998 struct nand_chip *chip, const uint8_t *buf)
1da177e4 1999{
f75e5097
TG		 2000 int i, eccsize = chip->ecc.size;
2001 int eccbytes = chip->ecc.bytes;
2002 int eccsteps = chip->ecc.steps;
2003 const uint8_t *p = buf;
2004 uint8_t *oob = chip->oob_poi;
1da177e4 2005
f75e5097 2006 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2007
f75e5097
TG		 2008 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2009 chip->write_buf(mtd, p, eccsize);
61b03bd7 2010
f75e5097
TG		 2011 if (chip->ecc.prepad) {
2012 chip->write_buf(mtd, oob, chip->ecc.prepad);
2013 oob += chip->ecc.prepad;
2014 }
2015
2016 chip->ecc.calculate(mtd, p, oob);
2017 chip->write_buf(mtd, oob, eccbytes);
2018 oob += eccbytes;
2019
2020 if (chip->ecc.postpad) {
2021 chip->write_buf(mtd, oob, chip->ecc.postpad);
2022 oob += chip->ecc.postpad;
1da177e4 2023 }
1da177e4 2024 }
f75e5097
TG		 2025
2026 /* Calculate remaining oob bytes */
7e4178f9 2027 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2028 if (i)
2029 chip->write_buf(mtd, oob, i);
2030}
2031
2032/**
956e944c 2033 * nand_write_page - [REPLACEABLE] write one page
8b6e50c9
BN		 2034 * @mtd: MTD device structure
2035 * @chip: NAND chip descriptor
2036 * @buf: the data to write
2037 * @page: page number to write
2038 * @cached: cached programming
2039 * @raw: use _raw version of write_page
f75e5097
TG		 2040 */
2041static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
956e944c 2042 const uint8_t *buf, int page, int cached, int raw)
f75e5097
TG		 2043{
2044 int status;
2045
2046 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2047
956e944c
DW		 2048 if (unlikely(raw))
2049 chip->ecc.write_page_raw(mtd, chip, buf);
2050 else
2051 chip->ecc.write_page(mtd, chip, buf);
f75e5097
TG		 2052
2053 /*
7854d3f7 2054 * Cached progamming disabled for now. Not sure if it's worth the
8b6e50c9 2055 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
f75e5097
TG		 2056 */
2057 cached = 0;
2058
2059 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2060
2061 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2062 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2063 /*
2064 * See if operation failed and additional status checks are
8b6e50c9 2065 * available.
f75e5097
TG		 2066 */
2067 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2068 status = chip->errstat(mtd, chip, FL_WRITING, status,
2069 page);
2070
2071 if (status & NAND_STATUS_FAIL)
2072 return -EIO;
2073 } else {
2074 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2075 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2076 }
2077
2078#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2079 /* Send command to read back the data */
2080 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2081
2082 if (chip->verify_buf(mtd, buf, mtd->writesize))
2083 return -EIO;
2084#endif
2085 return 0;
1da177e4
LT		 2086}
2087
8593fbc6 2088/**
7854d3f7 2089 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2090 * @mtd: MTD device structure
8b6e50c9
BN		 2091 * @oob: oob data buffer
2092 * @len: oob data write length
2093 * @ops: oob ops structure
8593fbc6 2094 */
f722013e
TAA		 2095static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2096 struct mtd_oob_ops *ops)
8593fbc6 2097{
f722013e
TAA		 2098 struct nand_chip *chip = mtd->priv;
2099
2100 /*
2101 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2102 * data from a previous OOB read.
2103 */
2104 memset(chip->oob_poi, 0xff, mtd->oobsize);
2105
f8ac0414 2106 switch (ops->mode) {
8593fbc6
TG		 2107
2108 case MTD_OOB_PLACE:
2109 case MTD_OOB_RAW:
2110 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2111 return oob + len;
2112
2113 case MTD_OOB_AUTO: {
2114 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2115 uint32_t boffs = 0, woffs = ops->ooboffs;
2116 size_t bytes = 0;
8593fbc6 2117
f8ac0414 2118 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 2119 /* Write request not from offset 0? */
7bc3312b
TG		 2120 if (unlikely(woffs)) {
2121 if (woffs >= free->length) {
2122 woffs -= free->length;
2123 continue;
2124 }
2125 boffs = free->offset + woffs;
2126 bytes = min_t(size_t, len,
2127 (free->length - woffs));
2128 woffs = 0;
2129 } else {
2130 bytes = min_t(size_t, len, free->length);
2131 boffs = free->offset;
2132 }
8b0036ee 2133 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2134 oob += bytes;
2135 }
2136 return oob;
2137 }
2138 default:
2139 BUG();
2140 }
2141 return NULL;
2142}
2143
f8ac0414 2144#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2145
2146/**
7854d3f7 2147 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2148 * @mtd: MTD device structure
2149 * @to: offset to write to
2150 * @ops: oob operations description structure
1da177e4 2151 *
8b6e50c9 2152 * NAND write with ECC.
1da177e4 2153 */
8593fbc6
TG		 2154static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2155 struct mtd_oob_ops *ops)
1da177e4 2156{
29072b96 2157 int chipnr, realpage, page, blockmask, column;
ace4dfee 2158 struct nand_chip *chip = mtd->priv;
8593fbc6 2159 uint32_t writelen = ops->len;
782ce79a
ML		 2160
2161 uint32_t oobwritelen = ops->ooblen;
2162 uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
2163 mtd->oobavail : mtd->oobsize;
2164
8593fbc6
TG		 2165 uint8_t *oob = ops->oobbuf;
2166 uint8_t *buf = ops->datbuf;
29072b96 2167 int ret, subpage;
1da177e4 2168
8593fbc6 2169 ops->retlen = 0;
29072b96
TG		 2170 if (!writelen)
2171 return 0;
1da177e4 2172
8b6e50c9 2173 /* Reject writes, which are not page aligned */
8593fbc6 2174 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
20d8e248 2175 printk(KERN_NOTICE "%s: Attempt to write not "
2176 "page aligned data\n", __func__);
1da177e4
LT		 2177 return -EINVAL;
2178 }
2179
29072b96
TG		 2180 column = to & (mtd->writesize - 1);
2181 subpage = column || (writelen & (mtd->writesize - 1));
2182
2183 if (subpage && oob)
2184 return -EINVAL;
1da177e4 2185
6a930961
TG		 2186 chipnr = (int)(to >> chip->chip_shift);
2187 chip->select_chip(mtd, chipnr);
2188
1da177e4
LT		 2189 /* Check, if it is write protected */
2190 if (nand_check_wp(mtd))
8593fbc6 2191 return -EIO;
1da177e4 2192
f75e5097
TG		 2193 realpage = (int)(to >> chip->page_shift);
2194 page = realpage & chip->pagemask;
2195 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2196
2197 /* Invalidate the page cache, when we write to the cached page */
2198 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2199 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2200 chip->pagebuf = -1;
61b03bd7 2201
782ce79a 2202 /* Don't allow multipage oob writes with offset */
cdcf12b2 2203 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
782ce79a
ML		 2204 return -EINVAL;
2205
f8ac0414 2206 while (1) {
29072b96 2207 int bytes = mtd->writesize;
f75e5097 2208 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2209 uint8_t *wbuf = buf;
2210
8b6e50c9 2211 /* Partial page write? */
29072b96
TG		 2212 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2213 cached = 0;
2214 bytes = min_t(int, bytes - column, (int) writelen);
2215 chip->pagebuf = -1;
2216 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2217 memcpy(&chip->buffers->databuf[column], buf, bytes);
2218 wbuf = chip->buffers->databuf;
2219 }
1da177e4 2220
782ce79a
ML		 2221 if (unlikely(oob)) {
2222 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2223 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2224 oobwritelen -= len;
f722013e
TAA		 2225 } else {
2226 /* We still need to erase leftover OOB data */
2227 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2228 }
8593fbc6 2229
29072b96 2230 ret = chip->write_page(mtd, chip, wbuf, page, cached,
956e944c 2231 (ops->mode == MTD_OOB_RAW));
f75e5097
TG		 2232 if (ret)
2233 break;
2234
2235 writelen -= bytes;
2236 if (!writelen)
2237 break;
2238
29072b96 2239 column = 0;
f75e5097
TG		 2240 buf += bytes;
2241 realpage++;
2242
2243 page = realpage & chip->pagemask;
2244 /* Check, if we cross a chip boundary */
2245 if (!page) {
2246 chipnr++;
2247 chip->select_chip(mtd, -1);
2248 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2249 }
2250 }
8593fbc6 2251
8593fbc6 2252 ops->retlen = ops->len - writelen;
7014568b
VW		 2253 if (unlikely(oob))
2254 ops->oobretlen = ops->ooblen;
1da177e4
LT		 2255 return ret;
2256}
2257
2af7c653
SK		 2258/**
2259 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2260 * @mtd: MTD device structure
2261 * @to: offset to write to
2262 * @len: number of bytes to write
2263 * @retlen: pointer to variable to store the number of written bytes
2264 * @buf: the data to write
2af7c653
SK		 2265 *
2266 * NAND write with ECC. Used when performing writes in interrupt context, this
2267 * may for example be called by mtdoops when writing an oops while in panic.
2268 */
2269static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2270 size_t *retlen, const uint8_t *buf)
2271{
2272 struct nand_chip *chip = mtd->priv;
2273 int ret;
2274
2275 /* Do not allow reads past end of device */
2276 if ((to + len) > mtd->size)
2277 return -EINVAL;
2278 if (!len)
2279 return 0;
2280
8b6e50c9 2281 /* Wait for the device to get ready */
2af7c653
SK		 2282 panic_nand_wait(mtd, chip, 400);
2283
8b6e50c9 2284 /* Grab the device */
2af7c653
SK		 2285 panic_nand_get_device(chip, mtd, FL_WRITING);
2286
2287 chip->ops.len = len;
2288 chip->ops.datbuf = (uint8_t *)buf;
2289 chip->ops.oobbuf = NULL;
2290
2291 ret = nand_do_write_ops(mtd, to, &chip->ops);
2292
2293 *retlen = chip->ops.retlen;
2294 return ret;
2295}
2296
f75e5097 2297/**
8593fbc6 2298 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2299 * @mtd: MTD device structure
2300 * @to: offset to write to
2301 * @len: number of bytes to write
2302 * @retlen: pointer to variable to store the number of written bytes
2303 * @buf: the data to write
f75e5097 2304 *
8b6e50c9 2305 * NAND write with ECC.
f75e5097 2306 */
8593fbc6
TG		 2307static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2308 size_t *retlen, const uint8_t *buf)
f75e5097
TG		 2309{
2310 struct nand_chip *chip = mtd->priv;
f75e5097
TG		 2311 int ret;
2312
8593fbc6
TG		 2313 /* Do not allow reads past end of device */
2314 if ((to + len) > mtd->size)
f75e5097 2315 return -EINVAL;
8593fbc6
TG		 2316 if (!len)
2317 return 0;
f75e5097 2318
7bc3312b 2319 nand_get_device(chip, mtd, FL_WRITING);
f75e5097 2320
8593fbc6
TG		 2321 chip->ops.len = len;
2322 chip->ops.datbuf = (uint8_t *)buf;
2323 chip->ops.oobbuf = NULL;
f75e5097 2324
8593fbc6 2325 ret = nand_do_write_ops(mtd, to, &chip->ops);
f75e5097 2326
7fd5aecc
RP		 2327 *retlen = chip->ops.retlen;
2328
f75e5097 2329 nand_release_device(mtd);
8593fbc6 2330
8593fbc6 2331 return ret;
f75e5097 2332}
7314e9e7 2333
1da177e4 2334/**
8593fbc6 2335 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2336 * @mtd: MTD device structure
2337 * @to: offset to write to
2338 * @ops: oob operation description structure
1da177e4 2339 *
8b6e50c9 2340 * NAND write out-of-band.
1da177e4 2341 */
8593fbc6
TG		 2342static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2343 struct mtd_oob_ops *ops)
1da177e4 2344{
03736155 2345 int chipnr, page, status, len;
ace4dfee 2346 struct nand_chip *chip = mtd->priv;
1da177e4 2347
20d8e248 2348 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2349 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2350
03736155
AH		 2351 if (ops->mode == MTD_OOB_AUTO)
2352 len = chip->ecc.layout->oobavail;
2353 else
2354 len = mtd->oobsize;
2355
1da177e4 2356 /* Do not allow write past end of page */
03736155 2357 if ((ops->ooboffs + ops->ooblen) > len) {
20d8e248 2358 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2359 "past end of page\n", __func__);
1da177e4
LT		 2360 return -EINVAL;
2361 }
2362
03736155 2363 if (unlikely(ops->ooboffs >= len)) {
20d8e248 2364 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2365 "write outside oob\n", __func__);
03736155
AH		 2366 return -EINVAL;
2367 }
2368
775adc3d 2369 /* Do not allow write past end of device */
03736155
AH		 2370 if (unlikely(to >= mtd->size ||
2371 ops->ooboffs + ops->ooblen >
2372 ((mtd->size >> chip->page_shift) -
2373 (to >> chip->page_shift)) * len)) {
20d8e248 2374 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2375 "end of device\n", __func__);
03736155
AH		 2376 return -EINVAL;
2377 }
2378
7314e9e7 2379 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2380 chip->select_chip(mtd, chipnr);
1da177e4 2381
7314e9e7
TG		 2382 /* Shift to get page */
2383 page = (int)(to >> chip->page_shift);
2384
2385 /*
2386 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2387 * of my DiskOnChip 2000 test units) will clear the whole data page too
2388 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2389 * it in the doc2000 driver in August 1999. dwmw2.
2390 */
ace4dfee 2391 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2392
2393 /* Check, if it is write protected */
2394 if (nand_check_wp(mtd))
8593fbc6 2395 return -EROFS;
61b03bd7 2396
1da177e4 2397 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2398 if (page == chip->pagebuf)
2399 chip->pagebuf = -1;
1da177e4 2400
f722013e 2401 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
7bc3312b 2402 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2403
7bc3312b
TG		 2404 if (status)
2405 return status;
1da177e4 2406
7014568b 2407 ops->oobretlen = ops->ooblen;
1da177e4 2408
7bc3312b 2409 return 0;
8593fbc6
TG		 2410}
2411
2412/**
2413 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2414 * @mtd: MTD device structure
2415 * @to: offset to write to
2416 * @ops: oob operation description structure
8593fbc6
TG		 2417 */
2418static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2419 struct mtd_oob_ops *ops)
2420{
8593fbc6
TG		 2421 struct nand_chip *chip = mtd->priv;
2422 int ret = -ENOTSUPP;
2423
2424 ops->retlen = 0;
2425
2426 /* Do not allow writes past end of device */
7014568b 2427 if (ops->datbuf && (to + ops->len) > mtd->size) {
20d8e248 2428 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2429 "end of device\n", __func__);
8593fbc6
TG		 2430 return -EINVAL;
2431 }
2432
7bc3312b 2433 nand_get_device(chip, mtd, FL_WRITING);
8593fbc6 2434
f8ac0414 2435 switch (ops->mode) {
8593fbc6
TG		 2436 case MTD_OOB_PLACE:
2437 case MTD_OOB_AUTO:
8593fbc6 2438 case MTD_OOB_RAW:
8593fbc6
TG		 2439 break;
2440
2441 default:
2442 goto out;
2443 }
2444
2445 if (!ops->datbuf)
2446 ret = nand_do_write_oob(mtd, to, ops);
2447 else
2448 ret = nand_do_write_ops(mtd, to, ops);
2449
7351d3a5 2450out:
1da177e4 2451 nand_release_device(mtd);
1da177e4
LT		 2452 return ret;
2453}
2454
1da177e4 2455/**
7854d3f7 2456 * single_erase_cmd - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2457 * @mtd: MTD device structure
2458 * @page: the page address of the block which will be erased
1da177e4 2459 *
8b6e50c9 2460 * Standard erase command for NAND chips.
1da177e4 2461 */
e0c7d767 2462static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2463{
ace4dfee 2464 struct nand_chip *chip = mtd->priv;
1da177e4 2465 /* Send commands to erase a block */
ace4dfee
TG		 2466 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2467 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2468}
2469
2470/**
7854d3f7 2471 * multi_erase_cmd - [GENERIC] AND specific block erase command function
8b6e50c9
BN		 2472 * @mtd: MTD device structure
2473 * @page: the page address of the block which will be erased
1da177e4 2474 *
8b6e50c9 2475 * AND multi block erase command function. Erase 4 consecutive blocks.
1da177e4 2476 */
e0c7d767 2477static void multi_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2478{
ace4dfee 2479 struct nand_chip *chip = mtd->priv;
1da177e4 2480 /* Send commands to erase a block */
ace4dfee
TG		 2481 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2482 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2483 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2484 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2485 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2486}
2487
2488/**
2489 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 2490 * @mtd: MTD device structure
2491 * @instr: erase instruction
1da177e4 2492 *
8b6e50c9 2493 * Erase one ore more blocks.
1da177e4 2494 */
e0c7d767 2495static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2496{
e0c7d767 2497 return nand_erase_nand(mtd, instr, 0);
1da177e4 2498}
61b03bd7 2499
30f464b7 2500#define BBT_PAGE_MASK 0xffffff3f
1da177e4 2501/**
7854d3f7 2502 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 2503 * @mtd: MTD device structure
2504 * @instr: erase instruction
2505 * @allowbbt: allow erasing the bbt area
1da177e4 2506 *
8b6e50c9 2507 * Erase one ore more blocks.
1da177e4 2508 */
ace4dfee
TG		 2509int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2510 int allowbbt)
1da177e4 2511{
69423d99 2512 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2513 struct nand_chip *chip = mtd->priv;
f8ac0414 2514 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
ace4dfee 2515 unsigned int bbt_masked_page = 0xffffffff;
69423d99 2516 loff_t len;
1da177e4 2517
20d8e248 2518 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2519 __func__, (unsigned long long)instr->addr,
2520 (unsigned long long)instr->len);
1da177e4 2521
6fe5a6ac 2522 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2523 return -EINVAL;
1da177e4 2524
bb0eb217 2525 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
1da177e4
LT		 2526
2527 /* Grab the lock and see if the device is available */
ace4dfee 2528 nand_get_device(chip, mtd, FL_ERASING);
1da177e4
LT		 2529
2530 /* Shift to get first page */
ace4dfee
TG		 2531 page = (int)(instr->addr >> chip->page_shift);
2532 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2533
2534 /* Calculate pages in each block */
ace4dfee 2535 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2536
2537 /* Select the NAND device */
ace4dfee 2538 chip->select_chip(mtd, chipnr);
1da177e4 2539
1da177e4
LT		 2540 /* Check, if it is write protected */
2541 if (nand_check_wp(mtd)) {
20d8e248 2542 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2543 __func__);
1da177e4
LT		 2544 instr->state = MTD_ERASE_FAILED;
2545 goto erase_exit;
2546 }
2547
ace4dfee
TG		 2548 /*
2549 * If BBT requires refresh, set the BBT page mask to see if the BBT
2550 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2551 * can not be matched. This is also done when the bbt is actually
7854d3f7 2552 * erased to avoid recursive updates.
ace4dfee
TG		 2553 */
2554 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2555 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
30f464b7 2556
1da177e4
LT		 2557 /* Loop through the pages */
2558 len = instr->len;
2559
2560 instr->state = MTD_ERASING;
2561
2562 while (len) {
8b6e50c9 2563 /* Heck if we have a bad block, we do not erase bad blocks! */
ace4dfee
TG		 2564 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2565 chip->page_shift, 0, allowbbt)) {
20d8e248 2566 printk(KERN_WARNING "%s: attempt to erase a bad block "
2567 "at page 0x%08x\n", __func__, page);
1da177e4
LT		 2568 instr->state = MTD_ERASE_FAILED;
2569 goto erase_exit;
2570 }
61b03bd7 2571
ace4dfee
TG		 2572 /*
2573 * Invalidate the page cache, if we erase the block which
8b6e50c9 2574 * contains the current cached page.
ace4dfee
TG		 2575 */
2576 if (page <= chip->pagebuf && chip->pagebuf <
2577 (page + pages_per_block))
2578 chip->pagebuf = -1;
1da177e4 2579
ace4dfee 2580 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2581
7bc3312b 2582 status = chip->waitfunc(mtd, chip);
1da177e4 2583
ace4dfee
TG		 2584 /*
2585 * See if operation failed and additional status checks are
2586 * available
2587 */
2588 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2589 status = chip->errstat(mtd, chip, FL_ERASING,
2590 status, page);
068e3c0a 2591
1da177e4 2592 /* See if block erase succeeded */
a4ab4c5d 2593 if (status & NAND_STATUS_FAIL) {
20d8e248 2594 DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2595 "page 0x%08x\n", __func__, page);
1da177e4 2596 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2597 instr->fail_addr =
2598 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2599 goto erase_exit;
2600 }
30f464b7 2601
ace4dfee
TG		 2602 /*
2603 * If BBT requires refresh, set the BBT rewrite flag to the
8b6e50c9 2604 * page being erased.
ace4dfee
TG		 2605 */
2606 if (bbt_masked_page != 0xffffffff &&
2607 (page & BBT_PAGE_MASK) == bbt_masked_page)
69423d99
AH		 2608 rewrite_bbt[chipnr] =
2609 ((loff_t)page << chip->page_shift);
61b03bd7 2610
1da177e4 2611 /* Increment page address and decrement length */
ace4dfee 2612 len -= (1 << chip->phys_erase_shift);
1da177e4
LT		 2613 page += pages_per_block;
2614
2615 /* Check, if we cross a chip boundary */
ace4dfee 2616 if (len && !(page & chip->pagemask)) {
1da177e4 2617 chipnr++;
ace4dfee
TG		 2618 chip->select_chip(mtd, -1);
2619 chip->select_chip(mtd, chipnr);
30f464b7 2620
ace4dfee
TG		 2621 /*
2622 * If BBT requires refresh and BBT-PERCHIP, set the BBT
8b6e50c9 2623 * page mask to see if this BBT should be rewritten.
ace4dfee
TG		 2624 */
2625 if (bbt_masked_page != 0xffffffff &&
2626 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2627 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2628 BBT_PAGE_MASK;
1da177e4
LT		 2629 }
2630 }
2631 instr->state = MTD_ERASE_DONE;
2632
7351d3a5 2633erase_exit:
1da177e4
LT		 2634
2635 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2636
2637 /* Deselect and wake up anyone waiting on the device */
2638 nand_release_device(mtd);
2639
49defc01
DW		 2640 /* Do call back function */
2641 if (!ret)
2642 mtd_erase_callback(instr);
2643
ace4dfee
TG		 2644 /*
2645 * If BBT requires refresh and erase was successful, rewrite any
8b6e50c9 2646 * selected bad block tables.
ace4dfee
TG		 2647 */
2648 if (bbt_masked_page == 0xffffffff || ret)
2649 return ret;
2650
2651 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2652 if (!rewrite_bbt[chipnr])
2653 continue;
8b6e50c9 2654 /* Update the BBT for chip */
20d8e248 2655 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2656 "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2657 rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
ace4dfee 2658 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
30f464b7
DM		 2659 }
2660
1da177e4
LT		 2661 /* Return more or less happy */
2662 return ret;
2663}
2664
2665/**
2666 * nand_sync - [MTD Interface] sync
8b6e50c9 2667 * @mtd: MTD device structure
1da177e4 2668 *
8b6e50c9 2669 * Sync is actually a wait for chip ready function.
1da177e4 2670 */
e0c7d767 2671static void nand_sync(struct mtd_info *mtd)
1da177e4 2672{
ace4dfee 2673 struct nand_chip *chip = mtd->priv;
1da177e4 2674
20d8e248 2675 DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
1da177e4
LT		 2676
2677 /* Grab the lock and see if the device is available */
ace4dfee 2678 nand_get_device(chip, mtd, FL_SYNCING);
1da177e4 2679 /* Release it and go back */
e0c7d767 2680 nand_release_device(mtd);
1da177e4
LT		 2681}
2682
1da177e4 2683/**
ace4dfee 2684 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 2685 * @mtd: MTD device structure
2686 * @offs: offset relative to mtd start
1da177e4 2687 */
ace4dfee 2688static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4
LT		 2689{
2690 /* Check for invalid offset */
ace4dfee 2691 if (offs > mtd->size)
1da177e4 2692 return -EINVAL;
61b03bd7 2693
ace4dfee 2694 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2695}
2696
2697/**
ace4dfee 2698 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 2699 * @mtd: MTD device structure
2700 * @ofs: offset relative to mtd start
1da177e4 2701 */
e0c7d767 2702static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2703{
ace4dfee 2704 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2705 int ret;
2706
f8ac0414
FF		 2707 ret = nand_block_isbad(mtd, ofs);
2708 if (ret) {
8b6e50c9 2709 /* If it was bad already, return success and do nothing */
1da177e4
LT		 2710 if (ret > 0)
2711 return 0;
e0c7d767
DW		 2712 return ret;
2713 }
1da177e4 2714
ace4dfee 2715 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 2716}
2717
962034f4
VW		 2718/**
2719 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 2720 * @mtd: MTD device structure
962034f4
VW		 2721 */
2722static int nand_suspend(struct mtd_info *mtd)
2723{
ace4dfee 2724 struct nand_chip *chip = mtd->priv;
962034f4 2725
ace4dfee 2726 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
962034f4
VW		 2727}
2728
2729/**
2730 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 2731 * @mtd: MTD device structure
962034f4
VW		 2732 */
2733static void nand_resume(struct mtd_info *mtd)
2734{
ace4dfee 2735 struct nand_chip *chip = mtd->priv;
962034f4 2736
ace4dfee 2737 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2738 nand_release_device(mtd);
2739 else
20d8e248 2740 printk(KERN_ERR "%s called for a chip which is not "
2741 "in suspended state\n", __func__);
962034f4
VW		 2742}
2743
8b6e50c9 2744/* Set default functions */
ace4dfee 2745static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2746{
1da177e4 2747 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2748 if (!chip->chip_delay)
2749 chip->chip_delay = 20;
1da177e4
LT		 2750
2751 /* check, if a user supplied command function given */
ace4dfee
TG		 2752 if (chip->cmdfunc == NULL)
2753 chip->cmdfunc = nand_command;
1da177e4
LT		 2754
2755 /* check, if a user supplied wait function given */
ace4dfee
TG		 2756 if (chip->waitfunc == NULL)
2757 chip->waitfunc = nand_wait;
2758
2759 if (!chip->select_chip)
2760 chip->select_chip = nand_select_chip;
2761 if (!chip->read_byte)
2762 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2763 if (!chip->read_word)
2764 chip->read_word = nand_read_word;
2765 if (!chip->block_bad)
2766 chip->block_bad = nand_block_bad;
2767 if (!chip->block_markbad)
2768 chip->block_markbad = nand_default_block_markbad;
2769 if (!chip->write_buf)
2770 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2771 if (!chip->read_buf)
2772 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2773 if (!chip->verify_buf)
2774 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2775 if (!chip->scan_bbt)
2776 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2777
2778 if (!chip->controller) {
2779 chip->controller = &chip->hwcontrol;
2780 spin_lock_init(&chip->controller->lock);
2781 init_waitqueue_head(&chip->controller->wq);
2782 }
2783
7aa65bfd
TG		 2784}
2785
8b6e50c9 2786/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 2787static void sanitize_string(uint8_t *s, size_t len)
2788{
2789 ssize_t i;
2790
8b6e50c9 2791 /* Null terminate */
d1e1f4e4
FF		 2792 s[len - 1] = 0;
2793
8b6e50c9 2794 /* Remove non printable chars */
d1e1f4e4
FF		 2795 for (i = 0; i < len - 1; i++) {
2796 if (s[i] < ' ' || s[i] > 127)
2797 s[i] = '?';
2798 }
2799
8b6e50c9 2800 /* Remove trailing spaces */
d1e1f4e4
FF		 2801 strim(s);
2802}
2803
2804static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2805{
2806 int i;
2807 while (len--) {
2808 crc ^= *p++ << 8;
2809 for (i = 0; i < 8; i++)
2810 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2811 }
2812
2813 return crc;
2814}
2815
6fb277ba 2816/*
8b6e50c9 2817 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba
FF		 2818 */
2819static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2820 int busw)
2821{
2822 struct nand_onfi_params *p = &chip->onfi_params;
2823 int i;
2824 int val;
2825
7854d3f7 2826 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 2827 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2828 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2829 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2830 return 0;
2831
2832 printk(KERN_INFO "ONFI flash detected\n");
2833 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2834 for (i = 0; i < 3; i++) {
2835 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2836 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2837 le16_to_cpu(p->crc)) {
2838 printk(KERN_INFO "ONFI param page %d valid\n", i);
2839 break;
2840 }
2841 }
2842
2843 if (i == 3)
2844 return 0;
2845
8b6e50c9 2846 /* Check version */
6fb277ba 2847 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 2848 if (val & (1 << 5))
2849 chip->onfi_version = 23;
2850 else if (val & (1 << 4))
6fb277ba
FF		 2851 chip->onfi_version = 22;
2852 else if (val & (1 << 3))
2853 chip->onfi_version = 21;
2854 else if (val & (1 << 2))
2855 chip->onfi_version = 20;
b7b1a29d 2856 else if (val & (1 << 1))
6fb277ba 2857 chip->onfi_version = 10;
b7b1a29d
BN		 2858 else
2859 chip->onfi_version = 0;
2860
2861 if (!chip->onfi_version) {
2862 printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
2863 __func__, val);
2864 return 0;
2865 }
6fb277ba
FF		 2866
2867 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2868 sanitize_string(p->model, sizeof(p->model));
2869 if (!mtd->name)
2870 mtd->name = p->model;
2871 mtd->writesize = le32_to_cpu(p->byte_per_page);
2872 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2873 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
4ccb3b44 2874 chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
6fb277ba
FF		 2875 busw = 0;
2876 if (le16_to_cpu(p->features) & 1)
2877 busw = NAND_BUSWIDTH_16;
2878
2879 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2880 chip->options |= (NAND_NO_READRDY |
2881 NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2882
2883 return 1;
2884}
2885
7aa65bfd 2886/*
8b6e50c9 2887 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd
TG		 2888 */
2889static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 2890 struct nand_chip *chip,
7351d3a5
FF		 2891 int busw,
2892 int *maf_id, int *dev_id,
5e81e88a 2893 struct nand_flash_dev *type)
7aa65bfd 2894{
d1e1f4e4 2895 int i, maf_idx;
426c457a 2896 u8 id_data[8];
6fb277ba 2897 int ret;
1da177e4
LT		 2898
2899 /* Select the device */
ace4dfee 2900 chip->select_chip(mtd, 0);
1da177e4 2901
ef89a880
KB		 2902 /*
2903 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 2904 * after power-up.
ef89a880
KB		 2905 */
2906 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2907
1da177e4 2908 /* Send the command for reading device ID */
ace4dfee 2909 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 2910
2911 /* Read manufacturer and device IDs */
ace4dfee 2912 *maf_id = chip->read_byte(mtd);
d1e1f4e4 2913 *dev_id = chip->read_byte(mtd);
1da177e4 2914
8b6e50c9
BN		 2915 /*
2916 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 2917 * interface concerns can cause random data which looks like a
2918 * possibly credible NAND flash to appear. If the two results do
2919 * not match, ignore the device completely.
2920 */
2921
2922 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2923
d1e1f4e4 2924 for (i = 0; i < 2; i++)
426c457a 2925 id_data[i] = chip->read_byte(mtd);
ed8165c7 2926
d1e1f4e4 2927 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
ed8165c7
BD		 2928 printk(KERN_INFO "%s: second ID read did not match "
2929 "%02x,%02x against %02x,%02x\n", __func__,
d1e1f4e4 2930 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 2931 return ERR_PTR(-ENODEV);
2932 }
2933
7aa65bfd 2934 if (!type)
5e81e88a
DW		 2935 type = nand_flash_ids;
2936
2937 for (; type->name != NULL; type++)
d1e1f4e4 2938 if (*dev_id == type->id)
f8ac0414 2939 break;
5e81e88a 2940
d1e1f4e4
FF		 2941 chip->onfi_version = 0;
2942 if (!type->name || !type->pagesize) {
6fb277ba
FF		 2943 /* Check is chip is ONFI compliant */
2944 ret = nand_flash_detect_onfi(mtd, chip, busw);
2945 if (ret)
2946 goto ident_done;
d1e1f4e4
FF		 2947 }
2948
2949 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2950
2951 /* Read entire ID string */
2952
2953 for (i = 0; i < 8; i++)
2954 id_data[i] = chip->read_byte(mtd);
2955
5e81e88a 2956 if (!type->name)
7aa65bfd
TG		 2957 return ERR_PTR(-ENODEV);
2958
ba0251fe
TG		 2959 if (!mtd->name)
2960 mtd->name = type->name;
2961
69423d99 2962 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 2963
12a40a57 2964 if (!type->pagesize && chip->init_size) {
8b6e50c9 2965 /* Set the pagesize, oobsize, erasesize by the driver */
12a40a57
HS		 2966 busw = chip->init_size(mtd, chip, id_data);
2967 } else if (!type->pagesize) {
7aa65bfd 2968 int extid;
29072b96 2969 /* The 3rd id byte holds MLC / multichip data */
426c457a 2970 chip->cellinfo = id_data[2];
7aa65bfd 2971 /* The 4th id byte is the important one */
426c457a 2972 extid = id_data[3];
61b03bd7 2973
426c457a
KC		 2974 /*
2975 * Field definitions are in the following datasheets:
2976 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
34c5bf6c 2977 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
426c457a
KC		 2978 *
2979 * Check for wraparound + Samsung ID + nonzero 6th byte
2980 * to decide what to do.
2981 */
2982 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
2983 id_data[0] == NAND_MFR_SAMSUNG &&
cfe3fdad 2984 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
426c457a
KC		 2985 id_data[5] != 0x00) {
2986 /* Calc pagesize */
2987 mtd->writesize = 2048 << (extid & 0x03);
2988 extid >>= 2;
2989 /* Calc oobsize */
34c5bf6c
BN		 2990 switch (extid & 0x03) {
2991 case 1:
2992 mtd->oobsize = 128;
2993 break;
2994 case 2:
2995 mtd->oobsize = 218;
2996 break;
2997 case 3:
2998 mtd->oobsize = 400;
2999 break;
3000 default:
3001 mtd->oobsize = 436;
3002 break;
3003 }
426c457a
KC		 3004 extid >>= 2;
3005 /* Calc blocksize */
3006 mtd->erasesize = (128 * 1024) <<
3007 (((extid >> 1) & 0x04) | (extid & 0x03));
3008 busw = 0;
3009 } else {
3010 /* Calc pagesize */
3011 mtd->writesize = 1024 << (extid & 0x03);
3012 extid >>= 2;
3013 /* Calc oobsize */
3014 mtd->oobsize = (8 << (extid & 0x01)) *
3015 (mtd->writesize >> 9);
3016 extid >>= 2;
3017 /* Calc blocksize. Blocksize is multiples of 64KiB */
3018 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3019 extid >>= 2;
3020 /* Get buswidth information */
3021 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3022 }
7aa65bfd
TG		 3023 } else {
3024 /*
8b6e50c9 3025 * Old devices have chip data hardcoded in the device id table.
7aa65bfd 3026 */
ba0251fe
TG		 3027 mtd->erasesize = type->erasesize;
3028 mtd->writesize = type->pagesize;
4cbb9b80 3029 mtd->oobsize = mtd->writesize / 32;
ba0251fe 3030 busw = type->options & NAND_BUSWIDTH_16;
2173bae8
BN		 3031
3032 /*
3033 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3034 * some Spansion chips have erasesize that conflicts with size
8b6e50c9 3035 * listed in nand_ids table.
2173bae8
BN		 3036 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3037 */
3038 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3039 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3040 id_data[7] == 0x00 && mtd->writesize == 512) {
3041 mtd->erasesize = 128 * 1024;
3042 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3043 }
7aa65bfd 3044 }
d1e1f4e4
FF		 3045 /* Get chip options, preserve non chip based options */
3046 chip->options &= ~NAND_CHIPOPTIONS_MSK;
3047 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3048
8b6e50c9
BN		 3049 /*
3050 * Check if chip is not a Samsung device. Do not clear the
3051 * options for chips which do not have an extended id.
d1e1f4e4
FF		 3052 */
3053 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3054 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3055ident_done:
3056
3057 /*
8b6e50c9 3058 * Set chip as a default. Board drivers can override it, if necessary.
d1e1f4e4
FF		 3059 */
3060 chip->options |= NAND_NO_AUTOINCR;
1da177e4 3061
7aa65bfd 3062 /* Try to identify manufacturer */
9a909867 3063 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3064 if (nand_manuf_ids[maf_idx].id == *maf_id)
3065 break;
3066 }
0ea4a755 3067
7aa65bfd
TG		 3068 /*
3069 * Check, if buswidth is correct. Hardware drivers should set
8b6e50c9 3070 * chip correct!
7aa65bfd 3071 */
ace4dfee 3072 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
7aa65bfd
TG		 3073 printk(KERN_INFO "NAND device: Manufacturer ID:"
3074 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
d1e1f4e4 3075 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
7aa65bfd 3076 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
ace4dfee 3077 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
7aa65bfd
TG		 3078 busw ? 16 : 8);
3079 return ERR_PTR(-EINVAL);
3080 }
61b03bd7 3081
7aa65bfd 3082 /* Calculate the address shift from the page size */
ace4dfee 3083 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3084 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3085 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3086
ace4dfee 3087 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3088 ffs(mtd->erasesize) - 1;
69423d99
AH		 3089 if (chip->chipsize & 0xffffffff)
3090 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3091 else {
3092 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3093 chip->chip_shift += 32 - 1;
3094 }
1da177e4 3095
26d9be11
AB		 3096 chip->badblockbits = 8;
3097
7aa65bfd 3098 /* Set the bad block position */
065a1ed8 3099 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
c7b28e25 3100 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
065a1ed8
BN		 3101 else
3102 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
61b03bd7 3103
b60b08b0
KC		 3104 /*
3105 * Bad block marker is stored in the last page of each block
c7b28e25
BN		 3106 * on Samsung and Hynix MLC devices; stored in first two pages
3107 * of each block on Micron devices with 2KiB pages and on
13ed7aed
BN		 3108 * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
3109 * only the first page.
b60b08b0
KC		 3110 */
3111 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3112 (*maf_id == NAND_MFR_SAMSUNG ||
3113 *maf_id == NAND_MFR_HYNIX))
5fb1549d 3114 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
c7b28e25
BN		 3115 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3116 (*maf_id == NAND_MFR_SAMSUNG ||
3117 *maf_id == NAND_MFR_HYNIX ||
13ed7aed 3118 *maf_id == NAND_MFR_TOSHIBA ||
c7b28e25
BN		 3119 *maf_id == NAND_MFR_AMD)) ||
3120 (mtd->writesize == 2048 &&
3121 *maf_id == NAND_MFR_MICRON))
5fb1549d 3122 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
c7b28e25 3123
7aa65bfd 3124 /* Check for AND chips with 4 page planes */
ace4dfee
TG		 3125 if (chip->options & NAND_4PAGE_ARRAY)
3126 chip->erase_cmd = multi_erase_cmd;
7aa65bfd 3127 else
ace4dfee 3128 chip->erase_cmd = single_erase_cmd;
7aa65bfd 3129
8b6e50c9 3130 /* Do not replace user supplied command function! */
ace4dfee
TG		 3131 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3132 chip->cmdfunc = nand_command_lp;
7aa65bfd
TG		 3133
3134 printk(KERN_INFO "NAND device: Manufacturer ID:"
d1e1f4e4
FF		 3135 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3136 nand_manuf_ids[maf_idx].name,
0b524fb9 3137 chip->onfi_version ? chip->onfi_params.model : type->name);
7aa65bfd
TG		 3138
3139 return type;
3140}
3141
7aa65bfd 3142/**
3b85c321 3143 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3144 * @mtd: MTD device structure
3145 * @maxchips: number of chips to scan for
3146 * @table: alternative NAND ID table
7aa65bfd 3147 *
8b6e50c9
BN		 3148 * This is the first phase of the normal nand_scan() function. It reads the
3149 * flash ID and sets up MTD fields accordingly.
7aa65bfd 3150 *
3b85c321 3151 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3152 */
5e81e88a
DW		 3153int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3154 struct nand_flash_dev *table)
7aa65bfd 3155{
d1e1f4e4 3156 int i, busw, nand_maf_id, nand_dev_id;
ace4dfee 3157 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 3158 struct nand_flash_dev *type;
3159
7aa65bfd 3160 /* Get buswidth to select the correct functions */
ace4dfee 3161 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 3162 /* Set the default functions */
ace4dfee 3163 nand_set_defaults(chip, busw);
7aa65bfd
TG		 3164
3165 /* Read the flash type */
7351d3a5
FF		 3166 type = nand_get_flash_type(mtd, chip, busw,
3167 &nand_maf_id, &nand_dev_id, table);
7aa65bfd
TG		 3168
3169 if (IS_ERR(type)) {
b1c6e6db
BD		 3170 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3171 printk(KERN_WARNING "No NAND device found.\n");
ace4dfee 3172 chip->select_chip(mtd, -1);
7aa65bfd 3173 return PTR_ERR(type);
1da177e4
LT		 3174 }
3175
7aa65bfd 3176 /* Check for a chip array */
e0c7d767 3177 for (i = 1; i < maxchips; i++) {
ace4dfee 3178 chip->select_chip(mtd, i);
ef89a880
KB		 3179 /* See comment in nand_get_flash_type for reset */
3180 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3181 /* Send the command for reading device ID */
ace4dfee 3182 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3183 /* Read manufacturer and device IDs */
ace4dfee 3184 if (nand_maf_id != chip->read_byte(mtd) ||
d1e1f4e4 3185 nand_dev_id != chip->read_byte(mtd))
1da177e4
LT		 3186 break;
3187 }
3188 if (i > 1)
3189 printk(KERN_INFO "%d NAND chips detected\n", i);
61b03bd7 3190
1da177e4 3191 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3192 chip->numchips = i;
3193 mtd->size = i * chip->chipsize;
7aa65bfd 3194
3b85c321
DW		 3195 return 0;
3196}
7351d3a5 3197EXPORT_SYMBOL(nand_scan_ident);
3b85c321
DW		 3198
3199
3200/**
3201 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 3202 * @mtd: MTD device structure
3b85c321 3203 *
8b6e50c9
BN		 3204 * This is the second phase of the normal nand_scan() function. It fills out
3205 * all the uninitialized function pointers with the defaults and scans for a
3206 * bad block table if appropriate.
3b85c321
DW		 3207 */
3208int nand_scan_tail(struct mtd_info *mtd)
3209{
3210 int i;
3211 struct nand_chip *chip = mtd->priv;
3212
4bf63fcb
DW		 3213 if (!(chip->options & NAND_OWN_BUFFERS))
3214 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3215 if (!chip->buffers)
3216 return -ENOMEM;
3217
7dcdcbef 3218 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3219 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3220
7aa65bfd 3221 /*
8b6e50c9 3222 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 3223 */
193bd400 3224 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 3225 switch (mtd->oobsize) {
1da177e4 3226 case 8:
5bd34c09 3227 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 3228 break;
3229 case 16:
5bd34c09 3230 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 3231 break;
3232 case 64:
5bd34c09 3233 chip->ecc.layout = &nand_oob_64;
1da177e4 3234 break;
81ec5364
TG		 3235 case 128:
3236 chip->ecc.layout = &nand_oob_128;
3237 break;
1da177e4 3238 default:
7aa65bfd
TG		 3239 printk(KERN_WARNING "No oob scheme defined for "
3240 "oobsize %d\n", mtd->oobsize);
1da177e4
LT		 3241 BUG();
3242 }
3243 }
61b03bd7 3244
956e944c
DW		 3245 if (!chip->write_page)
3246 chip->write_page = nand_write_page;
3247
61b03bd7 3248 /*
8b6e50c9 3249 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 3250 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3251 */
956e944c 3252
ace4dfee 3253 switch (chip->ecc.mode) {
6e0cb135
SN		 3254 case NAND_ECC_HW_OOB_FIRST:
3255 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3256 if (!chip->ecc.calculate || !chip->ecc.correct ||
3257 !chip->ecc.hwctl) {
3258 printk(KERN_WARNING "No ECC functions supplied; "
3259 "Hardware ECC not possible\n");
3260 BUG();
3261 }
3262 if (!chip->ecc.read_page)
3263 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3264
6dfc6d25 3265 case NAND_ECC_HW:
8b6e50c9 3266 /* Use standard hwecc read page function? */
f5bbdacc
TG		 3267 if (!chip->ecc.read_page)
3268 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 3269 if (!chip->ecc.write_page)
3270 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 3271 if (!chip->ecc.read_page_raw)
3272 chip->ecc.read_page_raw = nand_read_page_raw;
3273 if (!chip->ecc.write_page_raw)
3274 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3275 if (!chip->ecc.read_oob)
3276 chip->ecc.read_oob = nand_read_oob_std;
3277 if (!chip->ecc.write_oob)
3278 chip->ecc.write_oob = nand_write_oob_std;
f5bbdacc 3279
6dfc6d25 3280 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 3281 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3282 !chip->ecc.hwctl) &&
3283 (!chip->ecc.read_page ||
1c45f604 3284 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 3285 !chip->ecc.write_page ||
1c45f604 3286 chip->ecc.write_page == nand_write_page_hwecc)) {
6e0cb135 3287 printk(KERN_WARNING "No ECC functions supplied; "
6dfc6d25
TG		 3288 "Hardware ECC not possible\n");
3289 BUG();
3290 }
8b6e50c9 3291 /* Use standard syndrome read/write page function? */
f5bbdacc
TG		 3292 if (!chip->ecc.read_page)
3293 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 3294 if (!chip->ecc.write_page)
3295 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 3296 if (!chip->ecc.read_page_raw)
3297 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3298 if (!chip->ecc.write_page_raw)
3299 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 3300 if (!chip->ecc.read_oob)
3301 chip->ecc.read_oob = nand_read_oob_syndrome;
3302 if (!chip->ecc.write_oob)
3303 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 3304
ace4dfee 3305 if (mtd->writesize >= chip->ecc.size)
6dfc6d25
TG		 3306 break;
3307 printk(KERN_WARNING "%d byte HW ECC not possible on "
3308 "%d byte page size, fallback to SW ECC\n",
ace4dfee
TG		 3309 chip->ecc.size, mtd->writesize);
3310 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 3311
6dfc6d25 3312 case NAND_ECC_SOFT:
ace4dfee
TG		 3313 chip->ecc.calculate = nand_calculate_ecc;
3314 chip->ecc.correct = nand_correct_data;
f5bbdacc 3315 chip->ecc.read_page = nand_read_page_swecc;
3d459559 3316 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 3317 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 3318 chip->ecc.read_page_raw = nand_read_page_raw;
3319 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3320 chip->ecc.read_oob = nand_read_oob_std;
3321 chip->ecc.write_oob = nand_write_oob_std;
9a73290d
SV		 3322 if (!chip->ecc.size)
3323 chip->ecc.size = 256;
ace4dfee 3324 chip->ecc.bytes = 3;
1da177e4 3325 break;
61b03bd7 3326
193bd400
ID		 3327 case NAND_ECC_SOFT_BCH:
3328 if (!mtd_nand_has_bch()) {
3329 printk(KERN_WARNING "CONFIG_MTD_ECC_BCH not enabled\n");
3330 BUG();
3331 }
3332 chip->ecc.calculate = nand_bch_calculate_ecc;
3333 chip->ecc.correct = nand_bch_correct_data;
3334 chip->ecc.read_page = nand_read_page_swecc;
3335 chip->ecc.read_subpage = nand_read_subpage;
3336 chip->ecc.write_page = nand_write_page_swecc;
3337 chip->ecc.read_page_raw = nand_read_page_raw;
3338 chip->ecc.write_page_raw = nand_write_page_raw;
3339 chip->ecc.read_oob = nand_read_oob_std;
3340 chip->ecc.write_oob = nand_write_oob_std;
3341 /*
3342 * Board driver should supply ecc.size and ecc.bytes values to
3343 * select how many bits are correctable; see nand_bch_init()
8b6e50c9
BN		 3344 * for details. Otherwise, default to 4 bits for large page
3345 * devices.
193bd400
ID		 3346 */
3347 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3348 chip->ecc.size = 512;
3349 chip->ecc.bytes = 7;
3350 }
3351 chip->ecc.priv = nand_bch_init(mtd,
3352 chip->ecc.size,
3353 chip->ecc.bytes,
3354 &chip->ecc.layout);
3355 if (!chip->ecc.priv) {
3356 printk(KERN_WARNING "BCH ECC initialization failed!\n");
3357 BUG();
3358 }
3359 break;
3360
61b03bd7 3361 case NAND_ECC_NONE:
7aa65bfd
TG		 3362 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3363 "This is not recommended !!\n");
8593fbc6
TG		 3364 chip->ecc.read_page = nand_read_page_raw;
3365 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 3366 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 3367 chip->ecc.read_page_raw = nand_read_page_raw;
3368 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 3369 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 3370 chip->ecc.size = mtd->writesize;
3371 chip->ecc.bytes = 0;
1da177e4 3372 break;
956e944c 3373
1da177e4 3374 default:
7aa65bfd 3375 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
ace4dfee 3376 chip->ecc.mode);
61b03bd7 3377 BUG();
1da177e4 3378 }
61b03bd7 3379
5bd34c09
TG		 3380 /*
3381 * The number of bytes available for a client to place data into
8b6e50c9 3382 * the out of band area.
5bd34c09
TG		 3383 */
3384 chip->ecc.layout->oobavail = 0;
81d19b04
DB		 3385 for (i = 0; chip->ecc.layout->oobfree[i].length
3386 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
5bd34c09
TG		 3387 chip->ecc.layout->oobavail +=
3388 chip->ecc.layout->oobfree[i].length;
1f92267c 3389 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 3390
7aa65bfd
TG		 3391 /*
3392 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 3393 * mode.
7aa65bfd 3394 */
ace4dfee 3395 chip->ecc.steps = mtd->writesize / chip->ecc.size;
f8ac0414 3396 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
7854d3f7 3397 printk(KERN_WARNING "Invalid ECC parameters\n");
6dfc6d25 3398 BUG();
1da177e4 3399 }
f5bbdacc 3400 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 3401
8b6e50c9 3402 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
29072b96
TG		 3403 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3404 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
f8ac0414 3405 switch (chip->ecc.steps) {
29072b96
TG		 3406 case 2:
3407 mtd->subpage_sft = 1;
3408 break;
3409 case 4:
3410 case 8:
81ec5364 3411 case 16:
29072b96
TG		 3412 mtd->subpage_sft = 2;
3413 break;
3414 }
3415 }
3416 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3417
04bbd0ea 3418 /* Initialize state */
ace4dfee 3419 chip->state = FL_READY;
1da177e4
LT		 3420
3421 /* De-select the device */
ace4dfee 3422 chip->select_chip(mtd, -1);
1da177e4
LT		 3423
3424 /* Invalidate the pagebuffer reference */
ace4dfee 3425 chip->pagebuf = -1;
1da177e4
LT		 3426
3427 /* Fill in remaining MTD driver data */
3428 mtd->type = MTD_NANDFLASH;
93edbad6
ML		 3429 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3430 MTD_CAP_NANDFLASH;
1da177e4
LT		 3431 mtd->erase = nand_erase;
3432 mtd->point = NULL;
3433 mtd->unpoint = NULL;
3434 mtd->read = nand_read;
3435 mtd->write = nand_write;
2af7c653 3436 mtd->panic_write = panic_nand_write;
1da177e4
LT		 3437 mtd->read_oob = nand_read_oob;
3438 mtd->write_oob = nand_write_oob;
1da177e4
LT		 3439 mtd->sync = nand_sync;
3440 mtd->lock = NULL;
3441 mtd->unlock = NULL;
962034f4
VW		 3442 mtd->suspend = nand_suspend;
3443 mtd->resume = nand_resume;
1da177e4
LT		 3444 mtd->block_isbad = nand_block_isbad;
3445 mtd->block_markbad = nand_block_markbad;
cbcab65a 3446 mtd->writebufsize = mtd->writesize;
1da177e4 3447
5bd34c09
TG		 3448 /* propagate ecc.layout to mtd_info */
3449 mtd->ecclayout = chip->ecc.layout;
1da177e4 3450
0040bf38 3451 /* Check, if we should skip the bad block table scan */
ace4dfee 3452 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 3453 return 0;
1da177e4
LT		 3454
3455 /* Build bad block table */
ace4dfee 3456 return chip->scan_bbt(mtd);
1da177e4 3457}
7351d3a5 3458EXPORT_SYMBOL(nand_scan_tail);
1da177e4 3459
8b6e50c9
BN		 3460/*
3461 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 3462 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 3463 * to call us from in-kernel code if the core NAND support is modular.
3464 */
3b85c321
DW		 3465#ifdef MODULE
3466#define caller_is_module() (1)
3467#else
3468#define caller_is_module() \
a6e6abd5 3469 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 3470#endif
3471
3472/**
3473 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3474 * @mtd: MTD device structure
3475 * @maxchips: number of chips to scan for
3b85c321 3476 *
8b6e50c9
BN		 3477 * This fills out all the uninitialized function pointers with the defaults.
3478 * The flash ID is read and the mtd/chip structures are filled with the
3479 * appropriate values. The mtd->owner field must be set to the module of the
3480 * caller.
3b85c321
DW		 3481 */
3482int nand_scan(struct mtd_info *mtd, int maxchips)
3483{
3484 int ret;
3485
3486 /* Many callers got this wrong, so check for it for a while... */
3487 if (!mtd->owner && caller_is_module()) {
20d8e248 3488 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3489 __func__);
3b85c321
DW		 3490 BUG();
3491 }
3492
5e81e88a 3493 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 3494 if (!ret)
3495 ret = nand_scan_tail(mtd);
3496 return ret;
3497}
7351d3a5 3498EXPORT_SYMBOL(nand_scan);
3b85c321 3499
1da177e4 3500/**
61b03bd7 3501 * nand_release - [NAND Interface] Free resources held by the NAND device
8b6e50c9
BN		 3502 * @mtd: MTD device structure
3503 */
e0c7d767 3504void nand_release(struct mtd_info *mtd)
1da177e4 3505{
ace4dfee 3506 struct nand_chip *chip = mtd->priv;
1da177e4 3507
193bd400
ID		 3508 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3509 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3510
5ffcaf3d 3511 mtd_device_unregister(mtd);
1da177e4 3512
fa671646 3513 /* Free bad block table memory */
ace4dfee 3514 kfree(chip->bbt);
4bf63fcb
DW		 3515 if (!(chip->options & NAND_OWN_BUFFERS))
3516 kfree(chip->buffers);
58373ff0
BN		 3517
3518 /* Free bad block descriptor memory */
3519 if (chip->badblock_pattern && chip->badblock_pattern->options
3520 & NAND_BBT_DYNAMICSTRUCT)
3521 kfree(chip->badblock_pattern);
1da177e4 3522}
e0c7d767 3523EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 3524
3525static int __init nand_base_init(void)
3526{
3527 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3528 return 0;
3529}
3530
3531static void __exit nand_base_exit(void)
3532{
3533 led_trigger_unregister_simple(nand_led_trigger);
3534}
3535
3536module_init(nand_base_init);
3537module_exit(nand_base_exit);
3538
e0c7d767 3539MODULE_LICENSE("GPL");
7351d3a5
FF		 3540MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3541MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 3542MODULE_DESCRIPTION("Generic NAND flash driver code");
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