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Commit | Line | Data |
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b199489d | 1 | /* |
8eabdd1e HS |
2 | * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with |
3 | * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c | |
4 | * | |
5 | * Copyright (C) 2005, Intec Automation Inc. | |
6 | * Copyright (C) 2014, Freescale Semiconductor, Inc. | |
b199489d HS |
7 | * |
8 | * This code is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/err.h> | |
14 | #include <linux/errno.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/mutex.h> | |
18 | #include <linux/math64.h> | |
19 | ||
20 | #include <linux/mtd/cfi.h> | |
21 | #include <linux/mtd/mtd.h> | |
22 | #include <linux/of_platform.h> | |
23 | #include <linux/spi/flash.h> | |
24 | #include <linux/mtd/spi-nor.h> | |
25 | ||
26 | /* Define max times to check status register before we give up. */ | |
27 | #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */ | |
28 | ||
d928a259 HS |
29 | #define SPI_NOR_MAX_ID_LEN 6 |
30 | ||
31 | struct flash_info { | |
06bb6f5a RM |
32 | char *name; |
33 | ||
d928a259 HS |
34 | /* |
35 | * This array stores the ID bytes. | |
36 | * The first three bytes are the JEDIC ID. | |
37 | * JEDEC ID zero means "no ID" (mostly older chips). | |
38 | */ | |
39 | u8 id[SPI_NOR_MAX_ID_LEN]; | |
40 | u8 id_len; | |
41 | ||
42 | /* The size listed here is what works with SPINOR_OP_SE, which isn't | |
43 | * necessarily called a "sector" by the vendor. | |
44 | */ | |
45 | unsigned sector_size; | |
46 | u16 n_sectors; | |
47 | ||
48 | u16 page_size; | |
49 | u16 addr_width; | |
50 | ||
51 | u16 flags; | |
52 | #define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */ | |
53 | #define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */ | |
54 | #define SST_WRITE 0x04 /* use SST byte programming */ | |
55 | #define SPI_NOR_NO_FR 0x08 /* Can't do fastread */ | |
56 | #define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */ | |
57 | #define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */ | |
58 | #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */ | |
59 | #define USE_FSR 0x80 /* use flag status register */ | |
60 | }; | |
61 | ||
62 | #define JEDEC_MFR(info) ((info)->id[0]) | |
b199489d | 63 | |
06bb6f5a | 64 | static const struct flash_info *spi_nor_match_id(const char *name); |
70f3ce05 | 65 | |
b199489d HS |
66 | /* |
67 | * Read the status register, returning its value in the location | |
68 | * Return the status register value. | |
69 | * Returns negative if error occurred. | |
70 | */ | |
71 | static int read_sr(struct spi_nor *nor) | |
72 | { | |
73 | int ret; | |
74 | u8 val; | |
75 | ||
b02e7f3e | 76 | ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); |
b199489d HS |
77 | if (ret < 0) { |
78 | pr_err("error %d reading SR\n", (int) ret); | |
79 | return ret; | |
80 | } | |
81 | ||
82 | return val; | |
83 | } | |
84 | ||
c14dedde | 85 | /* |
86 | * Read the flag status register, returning its value in the location | |
87 | * Return the status register value. | |
88 | * Returns negative if error occurred. | |
89 | */ | |
90 | static int read_fsr(struct spi_nor *nor) | |
91 | { | |
92 | int ret; | |
93 | u8 val; | |
94 | ||
95 | ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1); | |
96 | if (ret < 0) { | |
97 | pr_err("error %d reading FSR\n", ret); | |
98 | return ret; | |
99 | } | |
100 | ||
101 | return val; | |
102 | } | |
103 | ||
b199489d HS |
104 | /* |
105 | * Read configuration register, returning its value in the | |
106 | * location. Return the configuration register value. | |
107 | * Returns negative if error occured. | |
108 | */ | |
109 | static int read_cr(struct spi_nor *nor) | |
110 | { | |
111 | int ret; | |
112 | u8 val; | |
113 | ||
b02e7f3e | 114 | ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1); |
b199489d HS |
115 | if (ret < 0) { |
116 | dev_err(nor->dev, "error %d reading CR\n", ret); | |
117 | return ret; | |
118 | } | |
119 | ||
120 | return val; | |
121 | } | |
122 | ||
123 | /* | |
124 | * Dummy Cycle calculation for different type of read. | |
125 | * It can be used to support more commands with | |
126 | * different dummy cycle requirements. | |
127 | */ | |
128 | static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor) | |
129 | { | |
130 | switch (nor->flash_read) { | |
131 | case SPI_NOR_FAST: | |
132 | case SPI_NOR_DUAL: | |
133 | case SPI_NOR_QUAD: | |
0b78a2cf | 134 | return 8; |
b199489d HS |
135 | case SPI_NOR_NORMAL: |
136 | return 0; | |
137 | } | |
138 | return 0; | |
139 | } | |
140 | ||
141 | /* | |
142 | * Write status register 1 byte | |
143 | * Returns negative if error occurred. | |
144 | */ | |
145 | static inline int write_sr(struct spi_nor *nor, u8 val) | |
146 | { | |
147 | nor->cmd_buf[0] = val; | |
f9f3ce83 | 148 | return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1); |
b199489d HS |
149 | } |
150 | ||
151 | /* | |
152 | * Set write enable latch with Write Enable command. | |
153 | * Returns negative if error occurred. | |
154 | */ | |
155 | static inline int write_enable(struct spi_nor *nor) | |
156 | { | |
f9f3ce83 | 157 | return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0); |
b199489d HS |
158 | } |
159 | ||
160 | /* | |
161 | * Send write disble instruction to the chip. | |
162 | */ | |
163 | static inline int write_disable(struct spi_nor *nor) | |
164 | { | |
f9f3ce83 | 165 | return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0); |
b199489d HS |
166 | } |
167 | ||
168 | static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) | |
169 | { | |
170 | return mtd->priv; | |
171 | } | |
172 | ||
173 | /* Enable/disable 4-byte addressing mode. */ | |
06bb6f5a | 174 | static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info, |
d928a259 | 175 | int enable) |
b199489d HS |
176 | { |
177 | int status; | |
178 | bool need_wren = false; | |
179 | u8 cmd; | |
180 | ||
d928a259 | 181 | switch (JEDEC_MFR(info)) { |
b199489d HS |
182 | case CFI_MFR_ST: /* Micron, actually */ |
183 | /* Some Micron need WREN command; all will accept it */ | |
184 | need_wren = true; | |
185 | case CFI_MFR_MACRONIX: | |
186 | case 0xEF /* winbond */: | |
187 | if (need_wren) | |
188 | write_enable(nor); | |
189 | ||
b02e7f3e | 190 | cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; |
f9f3ce83 | 191 | status = nor->write_reg(nor, cmd, NULL, 0); |
b199489d HS |
192 | if (need_wren) |
193 | write_disable(nor); | |
194 | ||
195 | return status; | |
196 | default: | |
197 | /* Spansion style */ | |
198 | nor->cmd_buf[0] = enable << 7; | |
f9f3ce83 | 199 | return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1); |
b199489d HS |
200 | } |
201 | } | |
51983b7d | 202 | static inline int spi_nor_sr_ready(struct spi_nor *nor) |
b199489d | 203 | { |
51983b7d BN |
204 | int sr = read_sr(nor); |
205 | if (sr < 0) | |
206 | return sr; | |
207 | else | |
208 | return !(sr & SR_WIP); | |
209 | } | |
b199489d | 210 | |
51983b7d BN |
211 | static inline int spi_nor_fsr_ready(struct spi_nor *nor) |
212 | { | |
213 | int fsr = read_fsr(nor); | |
214 | if (fsr < 0) | |
215 | return fsr; | |
216 | else | |
217 | return fsr & FSR_READY; | |
218 | } | |
b199489d | 219 | |
51983b7d BN |
220 | static int spi_nor_ready(struct spi_nor *nor) |
221 | { | |
222 | int sr, fsr; | |
223 | sr = spi_nor_sr_ready(nor); | |
224 | if (sr < 0) | |
225 | return sr; | |
226 | fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; | |
227 | if (fsr < 0) | |
228 | return fsr; | |
229 | return sr && fsr; | |
b199489d HS |
230 | } |
231 | ||
b94ed087 BN |
232 | /* |
233 | * Service routine to read status register until ready, or timeout occurs. | |
234 | * Returns non-zero if error. | |
235 | */ | |
51983b7d | 236 | static int spi_nor_wait_till_ready(struct spi_nor *nor) |
c14dedde | 237 | { |
238 | unsigned long deadline; | |
a95ce92e | 239 | int timeout = 0, ret; |
c14dedde | 240 | |
241 | deadline = jiffies + MAX_READY_WAIT_JIFFIES; | |
242 | ||
a95ce92e BN |
243 | while (!timeout) { |
244 | if (time_after_eq(jiffies, deadline)) | |
245 | timeout = 1; | |
c14dedde | 246 | |
51983b7d BN |
247 | ret = spi_nor_ready(nor); |
248 | if (ret < 0) | |
249 | return ret; | |
250 | if (ret) | |
251 | return 0; | |
a95ce92e BN |
252 | |
253 | cond_resched(); | |
254 | } | |
255 | ||
256 | dev_err(nor->dev, "flash operation timed out\n"); | |
c14dedde | 257 | |
258 | return -ETIMEDOUT; | |
259 | } | |
260 | ||
b199489d HS |
261 | /* |
262 | * Erase the whole flash memory | |
263 | * | |
264 | * Returns 0 if successful, non-zero otherwise. | |
265 | */ | |
266 | static int erase_chip(struct spi_nor *nor) | |
267 | { | |
19763671 | 268 | dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); |
b199489d | 269 | |
f9f3ce83 | 270 | return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0); |
b199489d HS |
271 | } |
272 | ||
273 | static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops) | |
274 | { | |
275 | int ret = 0; | |
276 | ||
277 | mutex_lock(&nor->lock); | |
278 | ||
279 | if (nor->prepare) { | |
280 | ret = nor->prepare(nor, ops); | |
281 | if (ret) { | |
282 | dev_err(nor->dev, "failed in the preparation.\n"); | |
283 | mutex_unlock(&nor->lock); | |
284 | return ret; | |
285 | } | |
286 | } | |
287 | return ret; | |
288 | } | |
289 | ||
290 | static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops) | |
291 | { | |
292 | if (nor->unprepare) | |
293 | nor->unprepare(nor, ops); | |
294 | mutex_unlock(&nor->lock); | |
295 | } | |
296 | ||
297 | /* | |
298 | * Erase an address range on the nor chip. The address range may extend | |
299 | * one or more erase sectors. Return an error is there is a problem erasing. | |
300 | */ | |
301 | static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) | |
302 | { | |
303 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
304 | u32 addr, len; | |
305 | uint32_t rem; | |
306 | int ret; | |
307 | ||
308 | dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, | |
309 | (long long)instr->len); | |
310 | ||
311 | div_u64_rem(instr->len, mtd->erasesize, &rem); | |
312 | if (rem) | |
313 | return -EINVAL; | |
314 | ||
315 | addr = instr->addr; | |
316 | len = instr->len; | |
317 | ||
318 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE); | |
319 | if (ret) | |
320 | return ret; | |
321 | ||
322 | /* whole-chip erase? */ | |
323 | if (len == mtd->size) { | |
05241aea BN |
324 | write_enable(nor); |
325 | ||
b199489d HS |
326 | if (erase_chip(nor)) { |
327 | ret = -EIO; | |
328 | goto erase_err; | |
329 | } | |
330 | ||
dfa9c0cb BN |
331 | ret = spi_nor_wait_till_ready(nor); |
332 | if (ret) | |
333 | goto erase_err; | |
334 | ||
b199489d | 335 | /* REVISIT in some cases we could speed up erasing large regions |
b02e7f3e | 336 | * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up |
b199489d HS |
337 | * to use "small sector erase", but that's not always optimal. |
338 | */ | |
339 | ||
340 | /* "sector"-at-a-time erase */ | |
341 | } else { | |
342 | while (len) { | |
05241aea BN |
343 | write_enable(nor); |
344 | ||
b199489d HS |
345 | if (nor->erase(nor, addr)) { |
346 | ret = -EIO; | |
347 | goto erase_err; | |
348 | } | |
349 | ||
350 | addr += mtd->erasesize; | |
351 | len -= mtd->erasesize; | |
dfa9c0cb BN |
352 | |
353 | ret = spi_nor_wait_till_ready(nor); | |
354 | if (ret) | |
355 | goto erase_err; | |
b199489d HS |
356 | } |
357 | } | |
358 | ||
05241aea BN |
359 | write_disable(nor); |
360 | ||
b199489d HS |
361 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); |
362 | ||
363 | instr->state = MTD_ERASE_DONE; | |
364 | mtd_erase_callback(instr); | |
365 | ||
366 | return ret; | |
367 | ||
368 | erase_err: | |
369 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); | |
370 | instr->state = MTD_ERASE_FAILED; | |
371 | return ret; | |
372 | } | |
373 | ||
8cc7f33a | 374 | static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) |
b199489d | 375 | { |
19763671 | 376 | struct mtd_info *mtd = &nor->mtd; |
b199489d HS |
377 | uint32_t offset = ofs; |
378 | uint8_t status_old, status_new; | |
379 | int ret = 0; | |
380 | ||
b199489d HS |
381 | status_old = read_sr(nor); |
382 | ||
383 | if (offset < mtd->size - (mtd->size / 2)) | |
384 | status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0; | |
385 | else if (offset < mtd->size - (mtd->size / 4)) | |
386 | status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1; | |
387 | else if (offset < mtd->size - (mtd->size / 8)) | |
388 | status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0; | |
389 | else if (offset < mtd->size - (mtd->size / 16)) | |
390 | status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2; | |
391 | else if (offset < mtd->size - (mtd->size / 32)) | |
392 | status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0; | |
393 | else if (offset < mtd->size - (mtd->size / 64)) | |
394 | status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1; | |
395 | else | |
396 | status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0; | |
397 | ||
398 | /* Only modify protection if it will not unlock other areas */ | |
399 | if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) > | |
400 | (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) { | |
401 | write_enable(nor); | |
402 | ret = write_sr(nor, status_new); | |
b199489d HS |
403 | } |
404 | ||
b199489d HS |
405 | return ret; |
406 | } | |
407 | ||
8cc7f33a | 408 | static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) |
b199489d | 409 | { |
19763671 | 410 | struct mtd_info *mtd = &nor->mtd; |
b199489d HS |
411 | uint32_t offset = ofs; |
412 | uint8_t status_old, status_new; | |
413 | int ret = 0; | |
414 | ||
b199489d HS |
415 | status_old = read_sr(nor); |
416 | ||
417 | if (offset+len > mtd->size - (mtd->size / 64)) | |
418 | status_new = status_old & ~(SR_BP2 | SR_BP1 | SR_BP0); | |
419 | else if (offset+len > mtd->size - (mtd->size / 32)) | |
420 | status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0; | |
421 | else if (offset+len > mtd->size - (mtd->size / 16)) | |
422 | status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1; | |
423 | else if (offset+len > mtd->size - (mtd->size / 8)) | |
424 | status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0; | |
425 | else if (offset+len > mtd->size - (mtd->size / 4)) | |
426 | status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2; | |
427 | else if (offset+len > mtd->size - (mtd->size / 2)) | |
428 | status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0; | |
429 | else | |
430 | status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1; | |
431 | ||
432 | /* Only modify protection if it will not lock other areas */ | |
433 | if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) < | |
434 | (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) { | |
435 | write_enable(nor); | |
436 | ret = write_sr(nor, status_new); | |
b199489d HS |
437 | } |
438 | ||
8cc7f33a BN |
439 | return ret; |
440 | } | |
441 | ||
442 | static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
443 | { | |
444 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
445 | int ret; | |
446 | ||
447 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK); | |
448 | if (ret) | |
449 | return ret; | |
450 | ||
451 | ret = nor->flash_lock(nor, ofs, len); | |
452 | ||
b199489d HS |
453 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK); |
454 | return ret; | |
455 | } | |
456 | ||
8cc7f33a BN |
457 | static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
458 | { | |
459 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
460 | int ret; | |
461 | ||
462 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK); | |
463 | if (ret) | |
464 | return ret; | |
465 | ||
466 | ret = nor->flash_unlock(nor, ofs, len); | |
467 | ||
468 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK); | |
469 | return ret; | |
470 | } | |
471 | ||
09ffafb6 | 472 | /* Used when the "_ext_id" is two bytes at most */ |
b199489d | 473 | #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
09ffafb6 HS |
474 | .id = { \ |
475 | ((_jedec_id) >> 16) & 0xff, \ | |
476 | ((_jedec_id) >> 8) & 0xff, \ | |
477 | (_jedec_id) & 0xff, \ | |
478 | ((_ext_id) >> 8) & 0xff, \ | |
479 | (_ext_id) & 0xff, \ | |
480 | }, \ | |
481 | .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ | |
b199489d HS |
482 | .sector_size = (_sector_size), \ |
483 | .n_sectors = (_n_sectors), \ | |
484 | .page_size = 256, \ | |
06bb6f5a | 485 | .flags = (_flags), |
b199489d | 486 | |
6d7604e5 | 487 | #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
6d7604e5 HS |
488 | .id = { \ |
489 | ((_jedec_id) >> 16) & 0xff, \ | |
490 | ((_jedec_id) >> 8) & 0xff, \ | |
491 | (_jedec_id) & 0xff, \ | |
492 | ((_ext_id) >> 16) & 0xff, \ | |
493 | ((_ext_id) >> 8) & 0xff, \ | |
494 | (_ext_id) & 0xff, \ | |
495 | }, \ | |
496 | .id_len = 6, \ | |
497 | .sector_size = (_sector_size), \ | |
498 | .n_sectors = (_n_sectors), \ | |
499 | .page_size = 256, \ | |
06bb6f5a | 500 | .flags = (_flags), |
6d7604e5 | 501 | |
b199489d | 502 | #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \ |
b199489d HS |
503 | .sector_size = (_sector_size), \ |
504 | .n_sectors = (_n_sectors), \ | |
505 | .page_size = (_page_size), \ | |
506 | .addr_width = (_addr_width), \ | |
06bb6f5a | 507 | .flags = (_flags), |
b199489d HS |
508 | |
509 | /* NOTE: double check command sets and memory organization when you add | |
510 | * more nor chips. This current list focusses on newer chips, which | |
511 | * have been converging on command sets which including JEDEC ID. | |
c19900ed RM |
512 | * |
513 | * All newly added entries should describe *hardware* and should use SECT_4K | |
514 | * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage | |
515 | * scenarios excluding small sectors there is config option that can be | |
516 | * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS. | |
517 | * For historical (and compatibility) reasons (before we got above config) some | |
518 | * old entries may be missing 4K flag. | |
b199489d | 519 | */ |
06bb6f5a | 520 | static const struct flash_info spi_nor_ids[] = { |
b199489d HS |
521 | /* Atmel -- some are (confusingly) marketed as "DataFlash" */ |
522 | { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) }, | |
523 | { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, | |
524 | ||
525 | { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) }, | |
526 | { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, | |
527 | { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) }, | |
528 | ||
529 | { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) }, | |
530 | { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, | |
531 | { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) }, | |
532 | { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, | |
533 | ||
534 | { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, | |
535 | ||
536 | /* EON -- en25xxx */ | |
537 | { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, | |
538 | { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, | |
539 | { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) }, | |
540 | { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) }, | |
541 | { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, | |
a41595b3 | 542 | { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) }, |
b199489d | 543 | { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) }, |
c19900ed | 544 | { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, |
b199489d HS |
545 | |
546 | /* ESMT */ | |
547 | { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) }, | |
548 | ||
549 | /* Everspin */ | |
550 | { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
551 | { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
552 | ||
ce56ce7d RL |
553 | /* Fujitsu */ |
554 | { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) }, | |
555 | ||
b199489d HS |
556 | /* GigaDevice */ |
557 | { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) }, | |
558 | { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) }, | |
fcc87a95 | 559 | { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) }, |
b199489d HS |
560 | |
561 | /* Intel/Numonyx -- xxxs33b */ | |
562 | { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) }, | |
563 | { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, | |
564 | { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, | |
565 | ||
b79c332f GJ |
566 | /* ISSI */ |
567 | { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) }, | |
568 | ||
b199489d | 569 | /* Macronix */ |
660b5b07 | 570 | { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) }, |
b199489d HS |
571 | { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, |
572 | { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, | |
573 | { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, | |
574 | { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, | |
575 | { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) }, | |
576 | { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) }, | |
577 | { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) }, | |
81a1209c | 578 | { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) }, |
b199489d HS |
579 | { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, |
580 | { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, | |
581 | { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) }, | |
582 | { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, | |
583 | { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) }, | |
584 | { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) }, | |
585 | ||
586 | /* Micron */ | |
548cd3ab | 587 | { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, |
0db7fae2 | 588 | { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, |
2a06c7b1 | 589 | { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, |
548cd3ab BH |
590 | { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, |
591 | { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, | |
592 | { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, | |
593 | { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, | |
594 | { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, | |
595 | { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, | |
b199489d HS |
596 | |
597 | /* PMC */ | |
598 | { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) }, | |
599 | { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) }, | |
600 | { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) }, | |
601 | ||
602 | /* Spansion -- single (large) sector size only, at least | |
603 | * for the chips listed here (without boot sectors). | |
604 | */ | |
9ab86995 | 605 | { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
0f12a27b | 606 | { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
b199489d HS |
607 | { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) }, |
608 | { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
609 | { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
610 | { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, | |
611 | { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, | |
612 | { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, | |
c19900ed | 613 | { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, |
c1752086 JG |
614 | { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
615 | { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
b199489d HS |
616 | { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, |
617 | { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, | |
618 | { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, | |
619 | { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, | |
620 | { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, | |
621 | { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, | |
622 | { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) }, | |
623 | { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, | |
c19900ed | 624 | { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) }, |
413780d7 | 625 | { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, |
b4d97f02 | 626 | { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K) }, |
b199489d HS |
627 | |
628 | /* SST -- large erase sizes are "overlays", "sectors" are 4K */ | |
629 | { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, | |
630 | { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, | |
631 | { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, | |
632 | { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, | |
633 | { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, | |
634 | { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, | |
635 | { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, | |
636 | { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, | |
a1d97ef9 | 637 | { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) }, |
b199489d | 638 | { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, |
f02985b7 | 639 | { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, |
b199489d HS |
640 | |
641 | /* ST Microelectronics -- newer production may have feature updates */ | |
642 | { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, | |
643 | { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, | |
644 | { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, | |
645 | { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, | |
646 | { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, | |
647 | { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, | |
648 | { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, | |
649 | { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, | |
650 | { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, | |
b199489d HS |
651 | |
652 | { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) }, | |
653 | { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) }, | |
654 | { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) }, | |
655 | { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) }, | |
656 | { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) }, | |
657 | { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) }, | |
658 | { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) }, | |
659 | { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) }, | |
660 | { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) }, | |
661 | ||
662 | { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) }, | |
663 | { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) }, | |
664 | { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) }, | |
665 | ||
666 | { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) }, | |
667 | { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) }, | |
668 | { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, | |
669 | ||
670 | { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) }, | |
671 | { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) }, | |
672 | { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) }, | |
673 | { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) }, | |
674 | { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, | |
f2fabe16 | 675 | { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) }, |
b199489d HS |
676 | |
677 | /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ | |
40d19ab6 | 678 | { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) }, |
b199489d HS |
679 | { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, |
680 | { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, | |
681 | { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, | |
682 | { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, | |
683 | { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, | |
684 | { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, | |
685 | { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, | |
686 | { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) }, | |
687 | { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, | |
688 | { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, | |
e88e567f | 689 | { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K) }, |
b199489d HS |
690 | { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, |
691 | { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, | |
692 | { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, | |
693 | { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) }, | |
694 | ||
695 | /* Catalyst / On Semiconductor -- non-JEDEC */ | |
696 | { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
697 | { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
698 | { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
699 | { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
700 | { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
701 | { }, | |
702 | }; | |
703 | ||
06bb6f5a | 704 | static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) |
b199489d HS |
705 | { |
706 | int tmp; | |
09ffafb6 | 707 | u8 id[SPI_NOR_MAX_ID_LEN]; |
06bb6f5a | 708 | const struct flash_info *info; |
b199489d | 709 | |
09ffafb6 | 710 | tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); |
b199489d HS |
711 | if (tmp < 0) { |
712 | dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp); | |
713 | return ERR_PTR(tmp); | |
714 | } | |
b199489d HS |
715 | |
716 | for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) { | |
06bb6f5a | 717 | info = &spi_nor_ids[tmp]; |
09ffafb6 HS |
718 | if (info->id_len) { |
719 | if (!memcmp(info->id, id, info->id_len)) | |
b199489d HS |
720 | return &spi_nor_ids[tmp]; |
721 | } | |
722 | } | |
09ffafb6 HS |
723 | dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %2x, %2x\n", |
724 | id[0], id[1], id[2]); | |
b199489d HS |
725 | return ERR_PTR(-ENODEV); |
726 | } | |
727 | ||
b199489d HS |
728 | static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, |
729 | size_t *retlen, u_char *buf) | |
730 | { | |
731 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
732 | int ret; | |
733 | ||
734 | dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); | |
735 | ||
736 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ); | |
737 | if (ret) | |
738 | return ret; | |
739 | ||
740 | ret = nor->read(nor, from, len, retlen, buf); | |
741 | ||
742 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ); | |
743 | return ret; | |
744 | } | |
745 | ||
746 | static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, | |
747 | size_t *retlen, const u_char *buf) | |
748 | { | |
749 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
750 | size_t actual; | |
751 | int ret; | |
752 | ||
753 | dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); | |
754 | ||
755 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE); | |
756 | if (ret) | |
757 | return ret; | |
758 | ||
b199489d HS |
759 | write_enable(nor); |
760 | ||
761 | nor->sst_write_second = false; | |
762 | ||
763 | actual = to % 2; | |
764 | /* Start write from odd address. */ | |
765 | if (actual) { | |
b02e7f3e | 766 | nor->program_opcode = SPINOR_OP_BP; |
b199489d HS |
767 | |
768 | /* write one byte. */ | |
769 | nor->write(nor, to, 1, retlen, buf); | |
b94ed087 | 770 | ret = spi_nor_wait_till_ready(nor); |
b199489d HS |
771 | if (ret) |
772 | goto time_out; | |
773 | } | |
774 | to += actual; | |
775 | ||
776 | /* Write out most of the data here. */ | |
777 | for (; actual < len - 1; actual += 2) { | |
b02e7f3e | 778 | nor->program_opcode = SPINOR_OP_AAI_WP; |
b199489d HS |
779 | |
780 | /* write two bytes. */ | |
781 | nor->write(nor, to, 2, retlen, buf + actual); | |
b94ed087 | 782 | ret = spi_nor_wait_till_ready(nor); |
b199489d HS |
783 | if (ret) |
784 | goto time_out; | |
785 | to += 2; | |
786 | nor->sst_write_second = true; | |
787 | } | |
788 | nor->sst_write_second = false; | |
789 | ||
790 | write_disable(nor); | |
b94ed087 | 791 | ret = spi_nor_wait_till_ready(nor); |
b199489d HS |
792 | if (ret) |
793 | goto time_out; | |
794 | ||
795 | /* Write out trailing byte if it exists. */ | |
796 | if (actual != len) { | |
797 | write_enable(nor); | |
798 | ||
b02e7f3e | 799 | nor->program_opcode = SPINOR_OP_BP; |
b199489d HS |
800 | nor->write(nor, to, 1, retlen, buf + actual); |
801 | ||
b94ed087 | 802 | ret = spi_nor_wait_till_ready(nor); |
b199489d HS |
803 | if (ret) |
804 | goto time_out; | |
805 | write_disable(nor); | |
806 | } | |
807 | time_out: | |
808 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE); | |
809 | return ret; | |
810 | } | |
811 | ||
812 | /* | |
813 | * Write an address range to the nor chip. Data must be written in | |
814 | * FLASH_PAGESIZE chunks. The address range may be any size provided | |
815 | * it is within the physical boundaries. | |
816 | */ | |
817 | static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, | |
818 | size_t *retlen, const u_char *buf) | |
819 | { | |
820 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
821 | u32 page_offset, page_size, i; | |
822 | int ret; | |
823 | ||
824 | dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); | |
825 | ||
826 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE); | |
827 | if (ret) | |
828 | return ret; | |
829 | ||
b199489d HS |
830 | write_enable(nor); |
831 | ||
832 | page_offset = to & (nor->page_size - 1); | |
833 | ||
834 | /* do all the bytes fit onto one page? */ | |
835 | if (page_offset + len <= nor->page_size) { | |
836 | nor->write(nor, to, len, retlen, buf); | |
837 | } else { | |
838 | /* the size of data remaining on the first page */ | |
839 | page_size = nor->page_size - page_offset; | |
840 | nor->write(nor, to, page_size, retlen, buf); | |
841 | ||
842 | /* write everything in nor->page_size chunks */ | |
843 | for (i = page_size; i < len; i += page_size) { | |
844 | page_size = len - i; | |
845 | if (page_size > nor->page_size) | |
846 | page_size = nor->page_size; | |
847 | ||
b94ed087 | 848 | ret = spi_nor_wait_till_ready(nor); |
1d61dcb3 BN |
849 | if (ret) |
850 | goto write_err; | |
851 | ||
b199489d HS |
852 | write_enable(nor); |
853 | ||
854 | nor->write(nor, to + i, page_size, retlen, buf + i); | |
855 | } | |
856 | } | |
857 | ||
dfa9c0cb | 858 | ret = spi_nor_wait_till_ready(nor); |
b199489d HS |
859 | write_err: |
860 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE); | |
1d61dcb3 | 861 | return ret; |
b199489d HS |
862 | } |
863 | ||
864 | static int macronix_quad_enable(struct spi_nor *nor) | |
865 | { | |
866 | int ret, val; | |
867 | ||
868 | val = read_sr(nor); | |
869 | write_enable(nor); | |
870 | ||
fd725234 | 871 | write_sr(nor, val | SR_QUAD_EN_MX); |
b199489d | 872 | |
b94ed087 | 873 | if (spi_nor_wait_till_ready(nor)) |
b199489d HS |
874 | return 1; |
875 | ||
876 | ret = read_sr(nor); | |
877 | if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) { | |
878 | dev_err(nor->dev, "Macronix Quad bit not set\n"); | |
879 | return -EINVAL; | |
880 | } | |
881 | ||
882 | return 0; | |
883 | } | |
884 | ||
885 | /* | |
886 | * Write status Register and configuration register with 2 bytes | |
887 | * The first byte will be written to the status register, while the | |
888 | * second byte will be written to the configuration register. | |
889 | * Return negative if error occured. | |
890 | */ | |
891 | static int write_sr_cr(struct spi_nor *nor, u16 val) | |
892 | { | |
893 | nor->cmd_buf[0] = val & 0xff; | |
894 | nor->cmd_buf[1] = (val >> 8); | |
895 | ||
f9f3ce83 | 896 | return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2); |
b199489d HS |
897 | } |
898 | ||
899 | static int spansion_quad_enable(struct spi_nor *nor) | |
900 | { | |
901 | int ret; | |
902 | int quad_en = CR_QUAD_EN_SPAN << 8; | |
903 | ||
904 | write_enable(nor); | |
905 | ||
906 | ret = write_sr_cr(nor, quad_en); | |
907 | if (ret < 0) { | |
908 | dev_err(nor->dev, | |
909 | "error while writing configuration register\n"); | |
910 | return -EINVAL; | |
911 | } | |
912 | ||
913 | /* read back and check it */ | |
914 | ret = read_cr(nor); | |
915 | if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) { | |
916 | dev_err(nor->dev, "Spansion Quad bit not set\n"); | |
917 | return -EINVAL; | |
918 | } | |
919 | ||
920 | return 0; | |
921 | } | |
922 | ||
548cd3ab BH |
923 | static int micron_quad_enable(struct spi_nor *nor) |
924 | { | |
925 | int ret; | |
926 | u8 val; | |
927 | ||
928 | ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1); | |
929 | if (ret < 0) { | |
930 | dev_err(nor->dev, "error %d reading EVCR\n", ret); | |
931 | return ret; | |
932 | } | |
933 | ||
934 | write_enable(nor); | |
935 | ||
936 | /* set EVCR, enable quad I/O */ | |
937 | nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON; | |
f9f3ce83 | 938 | ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1); |
548cd3ab BH |
939 | if (ret < 0) { |
940 | dev_err(nor->dev, "error while writing EVCR register\n"); | |
941 | return ret; | |
942 | } | |
943 | ||
944 | ret = spi_nor_wait_till_ready(nor); | |
945 | if (ret) | |
946 | return ret; | |
947 | ||
948 | /* read EVCR and check it */ | |
949 | ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1); | |
950 | if (ret < 0) { | |
951 | dev_err(nor->dev, "error %d reading EVCR\n", ret); | |
952 | return ret; | |
953 | } | |
954 | if (val & EVCR_QUAD_EN_MICRON) { | |
955 | dev_err(nor->dev, "Micron EVCR Quad bit not clear\n"); | |
956 | return -EINVAL; | |
957 | } | |
958 | ||
959 | return 0; | |
960 | } | |
961 | ||
06bb6f5a | 962 | static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info) |
b199489d HS |
963 | { |
964 | int status; | |
965 | ||
d928a259 | 966 | switch (JEDEC_MFR(info)) { |
b199489d HS |
967 | case CFI_MFR_MACRONIX: |
968 | status = macronix_quad_enable(nor); | |
969 | if (status) { | |
970 | dev_err(nor->dev, "Macronix quad-read not enabled\n"); | |
971 | return -EINVAL; | |
972 | } | |
973 | return status; | |
548cd3ab BH |
974 | case CFI_MFR_ST: |
975 | status = micron_quad_enable(nor); | |
976 | if (status) { | |
977 | dev_err(nor->dev, "Micron quad-read not enabled\n"); | |
978 | return -EINVAL; | |
979 | } | |
980 | return status; | |
b199489d HS |
981 | default: |
982 | status = spansion_quad_enable(nor); | |
983 | if (status) { | |
984 | dev_err(nor->dev, "Spansion quad-read not enabled\n"); | |
985 | return -EINVAL; | |
986 | } | |
987 | return status; | |
988 | } | |
989 | } | |
990 | ||
991 | static int spi_nor_check(struct spi_nor *nor) | |
992 | { | |
993 | if (!nor->dev || !nor->read || !nor->write || | |
994 | !nor->read_reg || !nor->write_reg || !nor->erase) { | |
995 | pr_err("spi-nor: please fill all the necessary fields!\n"); | |
996 | return -EINVAL; | |
997 | } | |
998 | ||
b199489d HS |
999 | return 0; |
1000 | } | |
1001 | ||
70f3ce05 | 1002 | int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) |
b199489d | 1003 | { |
06bb6f5a | 1004 | const struct flash_info *info = NULL; |
b199489d | 1005 | struct device *dev = nor->dev; |
19763671 | 1006 | struct mtd_info *mtd = &nor->mtd; |
11bff0b7 | 1007 | struct device_node *np = nor->flash_node; |
b199489d HS |
1008 | int ret; |
1009 | int i; | |
1010 | ||
1011 | ret = spi_nor_check(nor); | |
1012 | if (ret) | |
1013 | return ret; | |
1014 | ||
43163022 | 1015 | if (name) |
06bb6f5a | 1016 | info = spi_nor_match_id(name); |
43163022 | 1017 | /* Try to auto-detect if chip name wasn't specified or not found */ |
06bb6f5a RM |
1018 | if (!info) |
1019 | info = spi_nor_read_id(nor); | |
1020 | if (IS_ERR_OR_NULL(info)) | |
70f3ce05 BH |
1021 | return -ENOENT; |
1022 | ||
58c81957 RM |
1023 | /* |
1024 | * If caller has specified name of flash model that can normally be | |
1025 | * detected using JEDEC, let's verify it. | |
1026 | */ | |
1027 | if (name && info->id_len) { | |
06bb6f5a | 1028 | const struct flash_info *jinfo; |
b199489d | 1029 | |
06bb6f5a RM |
1030 | jinfo = spi_nor_read_id(nor); |
1031 | if (IS_ERR(jinfo)) { | |
1032 | return PTR_ERR(jinfo); | |
1033 | } else if (jinfo != info) { | |
b199489d HS |
1034 | /* |
1035 | * JEDEC knows better, so overwrite platform ID. We | |
1036 | * can't trust partitions any longer, but we'll let | |
1037 | * mtd apply them anyway, since some partitions may be | |
1038 | * marked read-only, and we don't want to lose that | |
1039 | * information, even if it's not 100% accurate. | |
1040 | */ | |
1041 | dev_warn(dev, "found %s, expected %s\n", | |
06bb6f5a RM |
1042 | jinfo->name, info->name); |
1043 | info = jinfo; | |
b199489d HS |
1044 | } |
1045 | } | |
1046 | ||
1047 | mutex_init(&nor->lock); | |
1048 | ||
1049 | /* | |
1050 | * Atmel, SST and Intel/Numonyx serial nor tend to power | |
1051 | * up with the software protection bits set | |
1052 | */ | |
1053 | ||
d928a259 HS |
1054 | if (JEDEC_MFR(info) == CFI_MFR_ATMEL || |
1055 | JEDEC_MFR(info) == CFI_MFR_INTEL || | |
1056 | JEDEC_MFR(info) == CFI_MFR_SST) { | |
b199489d HS |
1057 | write_enable(nor); |
1058 | write_sr(nor, 0); | |
1059 | } | |
1060 | ||
32f1b7c8 | 1061 | if (!mtd->name) |
b199489d | 1062 | mtd->name = dev_name(dev); |
c9ec3900 | 1063 | mtd->priv = nor; |
b199489d HS |
1064 | mtd->type = MTD_NORFLASH; |
1065 | mtd->writesize = 1; | |
1066 | mtd->flags = MTD_CAP_NORFLASH; | |
1067 | mtd->size = info->sector_size * info->n_sectors; | |
1068 | mtd->_erase = spi_nor_erase; | |
1069 | mtd->_read = spi_nor_read; | |
1070 | ||
1071 | /* nor protection support for STmicro chips */ | |
d928a259 | 1072 | if (JEDEC_MFR(info) == CFI_MFR_ST) { |
8cc7f33a BN |
1073 | nor->flash_lock = stm_lock; |
1074 | nor->flash_unlock = stm_unlock; | |
1075 | } | |
1076 | ||
1077 | if (nor->flash_lock && nor->flash_unlock) { | |
b199489d HS |
1078 | mtd->_lock = spi_nor_lock; |
1079 | mtd->_unlock = spi_nor_unlock; | |
1080 | } | |
1081 | ||
1082 | /* sst nor chips use AAI word program */ | |
1083 | if (info->flags & SST_WRITE) | |
1084 | mtd->_write = sst_write; | |
1085 | else | |
1086 | mtd->_write = spi_nor_write; | |
1087 | ||
51983b7d BN |
1088 | if (info->flags & USE_FSR) |
1089 | nor->flags |= SNOR_F_USE_FSR; | |
c14dedde | 1090 | |
57cf26c1 | 1091 | #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS |
b199489d HS |
1092 | /* prefer "small sector" erase if possible */ |
1093 | if (info->flags & SECT_4K) { | |
b02e7f3e | 1094 | nor->erase_opcode = SPINOR_OP_BE_4K; |
b199489d HS |
1095 | mtd->erasesize = 4096; |
1096 | } else if (info->flags & SECT_4K_PMC) { | |
b02e7f3e | 1097 | nor->erase_opcode = SPINOR_OP_BE_4K_PMC; |
b199489d | 1098 | mtd->erasesize = 4096; |
57cf26c1 RM |
1099 | } else |
1100 | #endif | |
1101 | { | |
b02e7f3e | 1102 | nor->erase_opcode = SPINOR_OP_SE; |
b199489d HS |
1103 | mtd->erasesize = info->sector_size; |
1104 | } | |
1105 | ||
1106 | if (info->flags & SPI_NOR_NO_ERASE) | |
1107 | mtd->flags |= MTD_NO_ERASE; | |
1108 | ||
1109 | mtd->dev.parent = dev; | |
1110 | nor->page_size = info->page_size; | |
1111 | mtd->writebufsize = nor->page_size; | |
1112 | ||
1113 | if (np) { | |
1114 | /* If we were instantiated by DT, use it */ | |
1115 | if (of_property_read_bool(np, "m25p,fast-read")) | |
1116 | nor->flash_read = SPI_NOR_FAST; | |
1117 | else | |
1118 | nor->flash_read = SPI_NOR_NORMAL; | |
1119 | } else { | |
1120 | /* If we weren't instantiated by DT, default to fast-read */ | |
1121 | nor->flash_read = SPI_NOR_FAST; | |
1122 | } | |
1123 | ||
1124 | /* Some devices cannot do fast-read, no matter what DT tells us */ | |
1125 | if (info->flags & SPI_NOR_NO_FR) | |
1126 | nor->flash_read = SPI_NOR_NORMAL; | |
1127 | ||
1128 | /* Quad/Dual-read mode takes precedence over fast/normal */ | |
1129 | if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) { | |
d928a259 | 1130 | ret = set_quad_mode(nor, info); |
b199489d HS |
1131 | if (ret) { |
1132 | dev_err(dev, "quad mode not supported\n"); | |
1133 | return ret; | |
1134 | } | |
1135 | nor->flash_read = SPI_NOR_QUAD; | |
1136 | } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) { | |
1137 | nor->flash_read = SPI_NOR_DUAL; | |
1138 | } | |
1139 | ||
1140 | /* Default commands */ | |
1141 | switch (nor->flash_read) { | |
1142 | case SPI_NOR_QUAD: | |
58b89a1f | 1143 | nor->read_opcode = SPINOR_OP_READ_1_1_4; |
b199489d HS |
1144 | break; |
1145 | case SPI_NOR_DUAL: | |
58b89a1f | 1146 | nor->read_opcode = SPINOR_OP_READ_1_1_2; |
b199489d HS |
1147 | break; |
1148 | case SPI_NOR_FAST: | |
58b89a1f | 1149 | nor->read_opcode = SPINOR_OP_READ_FAST; |
b199489d HS |
1150 | break; |
1151 | case SPI_NOR_NORMAL: | |
58b89a1f | 1152 | nor->read_opcode = SPINOR_OP_READ; |
b199489d HS |
1153 | break; |
1154 | default: | |
1155 | dev_err(dev, "No Read opcode defined\n"); | |
1156 | return -EINVAL; | |
1157 | } | |
1158 | ||
b02e7f3e | 1159 | nor->program_opcode = SPINOR_OP_PP; |
b199489d HS |
1160 | |
1161 | if (info->addr_width) | |
1162 | nor->addr_width = info->addr_width; | |
1163 | else if (mtd->size > 0x1000000) { | |
1164 | /* enable 4-byte addressing if the device exceeds 16MiB */ | |
1165 | nor->addr_width = 4; | |
d928a259 | 1166 | if (JEDEC_MFR(info) == CFI_MFR_AMD) { |
b199489d HS |
1167 | /* Dedicated 4-byte command set */ |
1168 | switch (nor->flash_read) { | |
1169 | case SPI_NOR_QUAD: | |
58b89a1f | 1170 | nor->read_opcode = SPINOR_OP_READ4_1_1_4; |
b199489d HS |
1171 | break; |
1172 | case SPI_NOR_DUAL: | |
58b89a1f | 1173 | nor->read_opcode = SPINOR_OP_READ4_1_1_2; |
b199489d HS |
1174 | break; |
1175 | case SPI_NOR_FAST: | |
58b89a1f | 1176 | nor->read_opcode = SPINOR_OP_READ4_FAST; |
b199489d HS |
1177 | break; |
1178 | case SPI_NOR_NORMAL: | |
58b89a1f | 1179 | nor->read_opcode = SPINOR_OP_READ4; |
b199489d HS |
1180 | break; |
1181 | } | |
b02e7f3e | 1182 | nor->program_opcode = SPINOR_OP_PP_4B; |
b199489d | 1183 | /* No small sector erase for 4-byte command set */ |
b02e7f3e | 1184 | nor->erase_opcode = SPINOR_OP_SE_4B; |
b199489d HS |
1185 | mtd->erasesize = info->sector_size; |
1186 | } else | |
d928a259 | 1187 | set_4byte(nor, info, 1); |
b199489d HS |
1188 | } else { |
1189 | nor->addr_width = 3; | |
1190 | } | |
1191 | ||
1192 | nor->read_dummy = spi_nor_read_dummy_cycles(nor); | |
1193 | ||
06bb6f5a | 1194 | dev_info(dev, "%s (%lld Kbytes)\n", info->name, |
b199489d HS |
1195 | (long long)mtd->size >> 10); |
1196 | ||
1197 | dev_dbg(dev, | |
1198 | "mtd .name = %s, .size = 0x%llx (%lldMiB), " | |
1199 | ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", | |
1200 | mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20), | |
1201 | mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions); | |
1202 | ||
1203 | if (mtd->numeraseregions) | |
1204 | for (i = 0; i < mtd->numeraseregions; i++) | |
1205 | dev_dbg(dev, | |
1206 | "mtd.eraseregions[%d] = { .offset = 0x%llx, " | |
1207 | ".erasesize = 0x%.8x (%uKiB), " | |
1208 | ".numblocks = %d }\n", | |
1209 | i, (long long)mtd->eraseregions[i].offset, | |
1210 | mtd->eraseregions[i].erasesize, | |
1211 | mtd->eraseregions[i].erasesize / 1024, | |
1212 | mtd->eraseregions[i].numblocks); | |
1213 | return 0; | |
1214 | } | |
b61834b0 | 1215 | EXPORT_SYMBOL_GPL(spi_nor_scan); |
b199489d | 1216 | |
06bb6f5a | 1217 | static const struct flash_info *spi_nor_match_id(const char *name) |
0d8c11c0 | 1218 | { |
06bb6f5a | 1219 | const struct flash_info *id = spi_nor_ids; |
0d8c11c0 | 1220 | |
2ff46e6f | 1221 | while (id->name) { |
0d8c11c0 HS |
1222 | if (!strcmp(name, id->name)) |
1223 | return id; | |
1224 | id++; | |
1225 | } | |
1226 | return NULL; | |
1227 | } | |
1228 | ||
b199489d HS |
1229 | MODULE_LICENSE("GPL"); |
1230 | MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>"); | |
1231 | MODULE_AUTHOR("Mike Lavender"); | |
1232 | MODULE_DESCRIPTION("framework for SPI NOR"); |