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Commit | Line | Data |
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6b7c5b94 | 1 | /* |
294aedcf | 2 | * Copyright (C) 2005 - 2010 ServerEngines |
6b7c5b94 SP |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
11 | * linux-drivers@serverengines.com | |
12 | * | |
13 | * ServerEngines | |
14 | * 209 N. Fair Oaks Ave | |
15 | * Sunnyvale, CA 94085 | |
16 | */ | |
17 | ||
18 | #include "be.h" | |
8788fdc2 | 19 | #include "be_cmds.h" |
65f71b8b | 20 | #include <asm/div64.h> |
6b7c5b94 SP |
21 | |
22 | MODULE_VERSION(DRV_VER); | |
23 | MODULE_DEVICE_TABLE(pci, be_dev_ids); | |
24 | MODULE_DESCRIPTION(DRV_DESC " " DRV_VER); | |
25 | MODULE_AUTHOR("ServerEngines Corporation"); | |
26 | MODULE_LICENSE("GPL"); | |
27 | ||
28 | static unsigned int rx_frag_size = 2048; | |
ba343c77 | 29 | static unsigned int num_vfs; |
6b7c5b94 | 30 | module_param(rx_frag_size, uint, S_IRUGO); |
ba343c77 | 31 | module_param(num_vfs, uint, S_IRUGO); |
6b7c5b94 | 32 | MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data."); |
ba343c77 | 33 | MODULE_PARM_DESC(num_vfs, "Number of PCI VFs to initialize"); |
6b7c5b94 | 34 | |
3abcdeda SP |
35 | static bool multi_rxq = true; |
36 | module_param(multi_rxq, bool, S_IRUGO | S_IWUSR); | |
37 | MODULE_PARM_DESC(multi_rxq, "Multi Rx Queue support. Enabled by default"); | |
38 | ||
6b7c5b94 | 39 | static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = { |
c4ca2374 | 40 | { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) }, |
59fd5d87 | 41 | { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) }, |
c4ca2374 AK |
42 | { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) }, |
43 | { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) }, | |
6b7c5b94 SP |
44 | { 0 } |
45 | }; | |
46 | MODULE_DEVICE_TABLE(pci, be_dev_ids); | |
7c185276 AK |
47 | /* UE Status Low CSR */ |
48 | static char *ue_status_low_desc[] = { | |
49 | "CEV", | |
50 | "CTX", | |
51 | "DBUF", | |
52 | "ERX", | |
53 | "Host", | |
54 | "MPU", | |
55 | "NDMA", | |
56 | "PTC ", | |
57 | "RDMA ", | |
58 | "RXF ", | |
59 | "RXIPS ", | |
60 | "RXULP0 ", | |
61 | "RXULP1 ", | |
62 | "RXULP2 ", | |
63 | "TIM ", | |
64 | "TPOST ", | |
65 | "TPRE ", | |
66 | "TXIPS ", | |
67 | "TXULP0 ", | |
68 | "TXULP1 ", | |
69 | "UC ", | |
70 | "WDMA ", | |
71 | "TXULP2 ", | |
72 | "HOST1 ", | |
73 | "P0_OB_LINK ", | |
74 | "P1_OB_LINK ", | |
75 | "HOST_GPIO ", | |
76 | "MBOX ", | |
77 | "AXGMAC0", | |
78 | "AXGMAC1", | |
79 | "JTAG", | |
80 | "MPU_INTPEND" | |
81 | }; | |
82 | /* UE Status High CSR */ | |
83 | static char *ue_status_hi_desc[] = { | |
84 | "LPCMEMHOST", | |
85 | "MGMT_MAC", | |
86 | "PCS0ONLINE", | |
87 | "MPU_IRAM", | |
88 | "PCS1ONLINE", | |
89 | "PCTL0", | |
90 | "PCTL1", | |
91 | "PMEM", | |
92 | "RR", | |
93 | "TXPB", | |
94 | "RXPP", | |
95 | "XAUI", | |
96 | "TXP", | |
97 | "ARM", | |
98 | "IPC", | |
99 | "HOST2", | |
100 | "HOST3", | |
101 | "HOST4", | |
102 | "HOST5", | |
103 | "HOST6", | |
104 | "HOST7", | |
105 | "HOST8", | |
106 | "HOST9", | |
107 | "NETC" | |
108 | "Unknown", | |
109 | "Unknown", | |
110 | "Unknown", | |
111 | "Unknown", | |
112 | "Unknown", | |
113 | "Unknown", | |
114 | "Unknown", | |
115 | "Unknown" | |
116 | }; | |
6b7c5b94 | 117 | |
3abcdeda SP |
118 | static inline bool be_multi_rxq(struct be_adapter *adapter) |
119 | { | |
120 | return (adapter->num_rx_qs > 1); | |
121 | } | |
122 | ||
6b7c5b94 SP |
123 | static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q) |
124 | { | |
125 | struct be_dma_mem *mem = &q->dma_mem; | |
126 | if (mem->va) | |
127 | pci_free_consistent(adapter->pdev, mem->size, | |
128 | mem->va, mem->dma); | |
129 | } | |
130 | ||
131 | static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q, | |
132 | u16 len, u16 entry_size) | |
133 | { | |
134 | struct be_dma_mem *mem = &q->dma_mem; | |
135 | ||
136 | memset(q, 0, sizeof(*q)); | |
137 | q->len = len; | |
138 | q->entry_size = entry_size; | |
139 | mem->size = len * entry_size; | |
140 | mem->va = pci_alloc_consistent(adapter->pdev, mem->size, &mem->dma); | |
141 | if (!mem->va) | |
142 | return -1; | |
143 | memset(mem->va, 0, mem->size); | |
144 | return 0; | |
145 | } | |
146 | ||
8788fdc2 | 147 | static void be_intr_set(struct be_adapter *adapter, bool enable) |
6b7c5b94 | 148 | { |
8788fdc2 | 149 | u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET; |
6b7c5b94 SP |
150 | u32 reg = ioread32(addr); |
151 | u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; | |
5f0b849e | 152 | |
cf588477 SP |
153 | if (adapter->eeh_err) |
154 | return; | |
155 | ||
5f0b849e | 156 | if (!enabled && enable) |
6b7c5b94 | 157 | reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; |
5f0b849e | 158 | else if (enabled && !enable) |
6b7c5b94 | 159 | reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; |
5f0b849e | 160 | else |
6b7c5b94 | 161 | return; |
5f0b849e | 162 | |
6b7c5b94 SP |
163 | iowrite32(reg, addr); |
164 | } | |
165 | ||
8788fdc2 | 166 | static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted) |
6b7c5b94 SP |
167 | { |
168 | u32 val = 0; | |
169 | val |= qid & DB_RQ_RING_ID_MASK; | |
170 | val |= posted << DB_RQ_NUM_POSTED_SHIFT; | |
f3eb62d2 SP |
171 | |
172 | wmb(); | |
8788fdc2 | 173 | iowrite32(val, adapter->db + DB_RQ_OFFSET); |
6b7c5b94 SP |
174 | } |
175 | ||
8788fdc2 | 176 | static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted) |
6b7c5b94 SP |
177 | { |
178 | u32 val = 0; | |
179 | val |= qid & DB_TXULP_RING_ID_MASK; | |
180 | val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT; | |
f3eb62d2 SP |
181 | |
182 | wmb(); | |
8788fdc2 | 183 | iowrite32(val, adapter->db + DB_TXULP1_OFFSET); |
6b7c5b94 SP |
184 | } |
185 | ||
8788fdc2 | 186 | static void be_eq_notify(struct be_adapter *adapter, u16 qid, |
6b7c5b94 SP |
187 | bool arm, bool clear_int, u16 num_popped) |
188 | { | |
189 | u32 val = 0; | |
190 | val |= qid & DB_EQ_RING_ID_MASK; | |
cf588477 SP |
191 | |
192 | if (adapter->eeh_err) | |
193 | return; | |
194 | ||
6b7c5b94 SP |
195 | if (arm) |
196 | val |= 1 << DB_EQ_REARM_SHIFT; | |
197 | if (clear_int) | |
198 | val |= 1 << DB_EQ_CLR_SHIFT; | |
199 | val |= 1 << DB_EQ_EVNT_SHIFT; | |
200 | val |= num_popped << DB_EQ_NUM_POPPED_SHIFT; | |
8788fdc2 | 201 | iowrite32(val, adapter->db + DB_EQ_OFFSET); |
6b7c5b94 SP |
202 | } |
203 | ||
8788fdc2 | 204 | void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped) |
6b7c5b94 SP |
205 | { |
206 | u32 val = 0; | |
207 | val |= qid & DB_CQ_RING_ID_MASK; | |
cf588477 SP |
208 | |
209 | if (adapter->eeh_err) | |
210 | return; | |
211 | ||
6b7c5b94 SP |
212 | if (arm) |
213 | val |= 1 << DB_CQ_REARM_SHIFT; | |
214 | val |= num_popped << DB_CQ_NUM_POPPED_SHIFT; | |
8788fdc2 | 215 | iowrite32(val, adapter->db + DB_CQ_OFFSET); |
6b7c5b94 SP |
216 | } |
217 | ||
6b7c5b94 SP |
218 | static int be_mac_addr_set(struct net_device *netdev, void *p) |
219 | { | |
220 | struct be_adapter *adapter = netdev_priv(netdev); | |
221 | struct sockaddr *addr = p; | |
222 | int status = 0; | |
223 | ||
ca9e4988 AK |
224 | if (!is_valid_ether_addr(addr->sa_data)) |
225 | return -EADDRNOTAVAIL; | |
226 | ||
ba343c77 SB |
227 | /* MAC addr configuration will be done in hardware for VFs |
228 | * by their corresponding PFs. Just copy to netdev addr here | |
229 | */ | |
230 | if (!be_physfn(adapter)) | |
231 | goto netdev_addr; | |
232 | ||
a65027e4 SP |
233 | status = be_cmd_pmac_del(adapter, adapter->if_handle, adapter->pmac_id); |
234 | if (status) | |
235 | return status; | |
6b7c5b94 | 236 | |
a65027e4 SP |
237 | status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data, |
238 | adapter->if_handle, &adapter->pmac_id); | |
ba343c77 | 239 | netdev_addr: |
6b7c5b94 SP |
240 | if (!status) |
241 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
242 | ||
243 | return status; | |
244 | } | |
245 | ||
b31c50a7 | 246 | void netdev_stats_update(struct be_adapter *adapter) |
6b7c5b94 | 247 | { |
3abcdeda | 248 | struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats_cmd.va); |
6b7c5b94 SP |
249 | struct be_rxf_stats *rxf_stats = &hw_stats->rxf; |
250 | struct be_port_rxf_stats *port_stats = | |
251 | &rxf_stats->port[adapter->port_num]; | |
78122a52 | 252 | struct net_device_stats *dev_stats = &adapter->netdev->stats; |
68110868 | 253 | struct be_erx_stats *erx_stats = &hw_stats->erx; |
3abcdeda SP |
254 | struct be_rx_obj *rxo; |
255 | int i; | |
6b7c5b94 | 256 | |
3abcdeda SP |
257 | memset(dev_stats, 0, sizeof(*dev_stats)); |
258 | for_all_rx_queues(adapter, rxo, i) { | |
259 | dev_stats->rx_packets += rx_stats(rxo)->rx_pkts; | |
260 | dev_stats->rx_bytes += rx_stats(rxo)->rx_bytes; | |
261 | dev_stats->multicast += rx_stats(rxo)->rx_mcast_pkts; | |
262 | /* no space in linux buffers: best possible approximation */ | |
263 | dev_stats->rx_dropped += | |
264 | erx_stats->rx_drops_no_fragments[rxo->q.id]; | |
265 | } | |
266 | ||
267 | dev_stats->tx_packets = tx_stats(adapter)->be_tx_pkts; | |
268 | dev_stats->tx_bytes = tx_stats(adapter)->be_tx_bytes; | |
6b7c5b94 SP |
269 | |
270 | /* bad pkts received */ | |
271 | dev_stats->rx_errors = port_stats->rx_crc_errors + | |
272 | port_stats->rx_alignment_symbol_errors + | |
273 | port_stats->rx_in_range_errors + | |
68110868 SP |
274 | port_stats->rx_out_range_errors + |
275 | port_stats->rx_frame_too_long + | |
276 | port_stats->rx_dropped_too_small + | |
277 | port_stats->rx_dropped_too_short + | |
278 | port_stats->rx_dropped_header_too_small + | |
279 | port_stats->rx_dropped_tcp_length + | |
280 | port_stats->rx_dropped_runt + | |
281 | port_stats->rx_tcp_checksum_errs + | |
282 | port_stats->rx_ip_checksum_errs + | |
283 | port_stats->rx_udp_checksum_errs; | |
284 | ||
6b7c5b94 SP |
285 | /* detailed rx errors */ |
286 | dev_stats->rx_length_errors = port_stats->rx_in_range_errors + | |
68110868 SP |
287 | port_stats->rx_out_range_errors + |
288 | port_stats->rx_frame_too_long; | |
289 | ||
6b7c5b94 SP |
290 | dev_stats->rx_crc_errors = port_stats->rx_crc_errors; |
291 | ||
292 | /* frame alignment errors */ | |
293 | dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors; | |
68110868 | 294 | |
6b7c5b94 SP |
295 | /* receiver fifo overrun */ |
296 | /* drops_no_pbuf is no per i/f, it's per BE card */ | |
297 | dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow + | |
298 | port_stats->rx_input_fifo_overflow + | |
299 | rxf_stats->rx_drops_no_pbuf; | |
6b7c5b94 SP |
300 | } |
301 | ||
8788fdc2 | 302 | void be_link_status_update(struct be_adapter *adapter, bool link_up) |
6b7c5b94 | 303 | { |
6b7c5b94 SP |
304 | struct net_device *netdev = adapter->netdev; |
305 | ||
6b7c5b94 | 306 | /* If link came up or went down */ |
a8f447bd | 307 | if (adapter->link_up != link_up) { |
0dffc83e | 308 | adapter->link_speed = -1; |
a8f447bd | 309 | if (link_up) { |
6b7c5b94 SP |
310 | netif_start_queue(netdev); |
311 | netif_carrier_on(netdev); | |
312 | printk(KERN_INFO "%s: Link up\n", netdev->name); | |
a8f447bd SP |
313 | } else { |
314 | netif_stop_queue(netdev); | |
315 | netif_carrier_off(netdev); | |
316 | printk(KERN_INFO "%s: Link down\n", netdev->name); | |
6b7c5b94 | 317 | } |
a8f447bd | 318 | adapter->link_up = link_up; |
6b7c5b94 | 319 | } |
6b7c5b94 SP |
320 | } |
321 | ||
322 | /* Update the EQ delay n BE based on the RX frags consumed / sec */ | |
3abcdeda | 323 | static void be_rx_eqd_update(struct be_adapter *adapter, struct be_rx_obj *rxo) |
6b7c5b94 | 324 | { |
3abcdeda SP |
325 | struct be_eq_obj *rx_eq = &rxo->rx_eq; |
326 | struct be_rx_stats *stats = &rxo->stats; | |
4097f663 SP |
327 | ulong now = jiffies; |
328 | u32 eqd; | |
329 | ||
330 | if (!rx_eq->enable_aic) | |
331 | return; | |
332 | ||
333 | /* Wrapped around */ | |
334 | if (time_before(now, stats->rx_fps_jiffies)) { | |
335 | stats->rx_fps_jiffies = now; | |
336 | return; | |
337 | } | |
6b7c5b94 SP |
338 | |
339 | /* Update once a second */ | |
4097f663 | 340 | if ((now - stats->rx_fps_jiffies) < HZ) |
6b7c5b94 SP |
341 | return; |
342 | ||
3abcdeda | 343 | stats->rx_fps = (stats->rx_frags - stats->prev_rx_frags) / |
4097f663 | 344 | ((now - stats->rx_fps_jiffies) / HZ); |
6b7c5b94 | 345 | |
4097f663 | 346 | stats->rx_fps_jiffies = now; |
3abcdeda SP |
347 | stats->prev_rx_frags = stats->rx_frags; |
348 | eqd = stats->rx_fps / 110000; | |
6b7c5b94 SP |
349 | eqd = eqd << 3; |
350 | if (eqd > rx_eq->max_eqd) | |
351 | eqd = rx_eq->max_eqd; | |
352 | if (eqd < rx_eq->min_eqd) | |
353 | eqd = rx_eq->min_eqd; | |
354 | if (eqd < 10) | |
355 | eqd = 0; | |
356 | if (eqd != rx_eq->cur_eqd) | |
8788fdc2 | 357 | be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd); |
6b7c5b94 SP |
358 | |
359 | rx_eq->cur_eqd = eqd; | |
360 | } | |
361 | ||
65f71b8b SH |
362 | static u32 be_calc_rate(u64 bytes, unsigned long ticks) |
363 | { | |
364 | u64 rate = bytes; | |
365 | ||
366 | do_div(rate, ticks / HZ); | |
367 | rate <<= 3; /* bytes/sec -> bits/sec */ | |
368 | do_div(rate, 1000000ul); /* MB/Sec */ | |
369 | ||
370 | return rate; | |
371 | } | |
372 | ||
4097f663 SP |
373 | static void be_tx_rate_update(struct be_adapter *adapter) |
374 | { | |
3abcdeda | 375 | struct be_tx_stats *stats = tx_stats(adapter); |
4097f663 SP |
376 | ulong now = jiffies; |
377 | ||
378 | /* Wrapped around? */ | |
379 | if (time_before(now, stats->be_tx_jiffies)) { | |
380 | stats->be_tx_jiffies = now; | |
381 | return; | |
382 | } | |
383 | ||
384 | /* Update tx rate once in two seconds */ | |
385 | if ((now - stats->be_tx_jiffies) > 2 * HZ) { | |
65f71b8b SH |
386 | stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes |
387 | - stats->be_tx_bytes_prev, | |
388 | now - stats->be_tx_jiffies); | |
4097f663 SP |
389 | stats->be_tx_jiffies = now; |
390 | stats->be_tx_bytes_prev = stats->be_tx_bytes; | |
391 | } | |
392 | } | |
393 | ||
6b7c5b94 | 394 | static void be_tx_stats_update(struct be_adapter *adapter, |
91992e44 | 395 | u32 wrb_cnt, u32 copied, u32 gso_segs, bool stopped) |
6b7c5b94 | 396 | { |
3abcdeda | 397 | struct be_tx_stats *stats = tx_stats(adapter); |
6b7c5b94 SP |
398 | stats->be_tx_reqs++; |
399 | stats->be_tx_wrbs += wrb_cnt; | |
400 | stats->be_tx_bytes += copied; | |
91992e44 | 401 | stats->be_tx_pkts += (gso_segs ? gso_segs : 1); |
6b7c5b94 SP |
402 | if (stopped) |
403 | stats->be_tx_stops++; | |
6b7c5b94 SP |
404 | } |
405 | ||
406 | /* Determine number of WRB entries needed to xmit data in an skb */ | |
407 | static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy) | |
408 | { | |
ebc8d2ab DM |
409 | int cnt = (skb->len > skb->data_len); |
410 | ||
411 | cnt += skb_shinfo(skb)->nr_frags; | |
412 | ||
6b7c5b94 SP |
413 | /* to account for hdr wrb */ |
414 | cnt++; | |
415 | if (cnt & 1) { | |
416 | /* add a dummy to make it an even num */ | |
417 | cnt++; | |
418 | *dummy = true; | |
419 | } else | |
420 | *dummy = false; | |
421 | BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT); | |
422 | return cnt; | |
423 | } | |
424 | ||
425 | static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len) | |
426 | { | |
427 | wrb->frag_pa_hi = upper_32_bits(addr); | |
428 | wrb->frag_pa_lo = addr & 0xFFFFFFFF; | |
429 | wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK; | |
430 | } | |
431 | ||
cc4ce020 SK |
432 | static void wrb_fill_hdr(struct be_adapter *adapter, struct be_eth_hdr_wrb *hdr, |
433 | struct sk_buff *skb, u32 wrb_cnt, u32 len) | |
6b7c5b94 | 434 | { |
cc4ce020 SK |
435 | u8 vlan_prio = 0; |
436 | u16 vlan_tag = 0; | |
437 | ||
6b7c5b94 SP |
438 | memset(hdr, 0, sizeof(*hdr)); |
439 | ||
440 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1); | |
441 | ||
49e4b847 | 442 | if (skb_is_gso(skb)) { |
6b7c5b94 SP |
443 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1); |
444 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss, | |
445 | hdr, skb_shinfo(skb)->gso_size); | |
49e4b847 AK |
446 | if (skb_is_gso_v6(skb)) |
447 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso6, hdr, 1); | |
6b7c5b94 SP |
448 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
449 | if (is_tcp_pkt(skb)) | |
450 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1); | |
451 | else if (is_udp_pkt(skb)) | |
452 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1); | |
453 | } | |
454 | ||
cc4ce020 | 455 | if (adapter->vlan_grp && vlan_tx_tag_present(skb)) { |
6b7c5b94 | 456 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1); |
cc4ce020 SK |
457 | vlan_tag = vlan_tx_tag_get(skb); |
458 | vlan_prio = (vlan_tag & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; | |
459 | /* If vlan priority provided by OS is NOT in available bmap */ | |
460 | if (!(adapter->vlan_prio_bmap & (1 << vlan_prio))) | |
461 | vlan_tag = (vlan_tag & ~VLAN_PRIO_MASK) | | |
462 | adapter->recommended_prio; | |
463 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag, hdr, vlan_tag); | |
6b7c5b94 SP |
464 | } |
465 | ||
466 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1); | |
467 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1); | |
468 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt); | |
469 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len); | |
470 | } | |
471 | ||
7101e111 SP |
472 | static void unmap_tx_frag(struct pci_dev *pdev, struct be_eth_wrb *wrb, |
473 | bool unmap_single) | |
474 | { | |
475 | dma_addr_t dma; | |
476 | ||
477 | be_dws_le_to_cpu(wrb, sizeof(*wrb)); | |
478 | ||
479 | dma = (u64)wrb->frag_pa_hi << 32 | (u64)wrb->frag_pa_lo; | |
b681ee77 | 480 | if (wrb->frag_len) { |
7101e111 SP |
481 | if (unmap_single) |
482 | pci_unmap_single(pdev, dma, wrb->frag_len, | |
483 | PCI_DMA_TODEVICE); | |
484 | else | |
485 | pci_unmap_page(pdev, dma, wrb->frag_len, | |
486 | PCI_DMA_TODEVICE); | |
487 | } | |
488 | } | |
6b7c5b94 SP |
489 | |
490 | static int make_tx_wrbs(struct be_adapter *adapter, | |
491 | struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb) | |
492 | { | |
7101e111 SP |
493 | dma_addr_t busaddr; |
494 | int i, copied = 0; | |
6b7c5b94 SP |
495 | struct pci_dev *pdev = adapter->pdev; |
496 | struct sk_buff *first_skb = skb; | |
497 | struct be_queue_info *txq = &adapter->tx_obj.q; | |
498 | struct be_eth_wrb *wrb; | |
499 | struct be_eth_hdr_wrb *hdr; | |
7101e111 SP |
500 | bool map_single = false; |
501 | u16 map_head; | |
6b7c5b94 | 502 | |
6b7c5b94 SP |
503 | hdr = queue_head_node(txq); |
504 | queue_head_inc(txq); | |
7101e111 | 505 | map_head = txq->head; |
6b7c5b94 | 506 | |
ebc8d2ab | 507 | if (skb->len > skb->data_len) { |
e743d313 | 508 | int len = skb_headlen(skb); |
a73b796e AD |
509 | busaddr = pci_map_single(pdev, skb->data, len, |
510 | PCI_DMA_TODEVICE); | |
7101e111 SP |
511 | if (pci_dma_mapping_error(pdev, busaddr)) |
512 | goto dma_err; | |
513 | map_single = true; | |
ebc8d2ab DM |
514 | wrb = queue_head_node(txq); |
515 | wrb_fill(wrb, busaddr, len); | |
516 | be_dws_cpu_to_le(wrb, sizeof(*wrb)); | |
517 | queue_head_inc(txq); | |
518 | copied += len; | |
519 | } | |
6b7c5b94 | 520 | |
ebc8d2ab DM |
521 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
522 | struct skb_frag_struct *frag = | |
523 | &skb_shinfo(skb)->frags[i]; | |
a73b796e AD |
524 | busaddr = pci_map_page(pdev, frag->page, |
525 | frag->page_offset, | |
526 | frag->size, PCI_DMA_TODEVICE); | |
7101e111 SP |
527 | if (pci_dma_mapping_error(pdev, busaddr)) |
528 | goto dma_err; | |
ebc8d2ab DM |
529 | wrb = queue_head_node(txq); |
530 | wrb_fill(wrb, busaddr, frag->size); | |
531 | be_dws_cpu_to_le(wrb, sizeof(*wrb)); | |
532 | queue_head_inc(txq); | |
533 | copied += frag->size; | |
6b7c5b94 SP |
534 | } |
535 | ||
536 | if (dummy_wrb) { | |
537 | wrb = queue_head_node(txq); | |
538 | wrb_fill(wrb, 0, 0); | |
539 | be_dws_cpu_to_le(wrb, sizeof(*wrb)); | |
540 | queue_head_inc(txq); | |
541 | } | |
542 | ||
cc4ce020 | 543 | wrb_fill_hdr(adapter, hdr, first_skb, wrb_cnt, copied); |
6b7c5b94 SP |
544 | be_dws_cpu_to_le(hdr, sizeof(*hdr)); |
545 | ||
546 | return copied; | |
7101e111 SP |
547 | dma_err: |
548 | txq->head = map_head; | |
549 | while (copied) { | |
550 | wrb = queue_head_node(txq); | |
551 | unmap_tx_frag(pdev, wrb, map_single); | |
552 | map_single = false; | |
553 | copied -= wrb->frag_len; | |
554 | queue_head_inc(txq); | |
555 | } | |
556 | return 0; | |
6b7c5b94 SP |
557 | } |
558 | ||
61357325 | 559 | static netdev_tx_t be_xmit(struct sk_buff *skb, |
b31c50a7 | 560 | struct net_device *netdev) |
6b7c5b94 SP |
561 | { |
562 | struct be_adapter *adapter = netdev_priv(netdev); | |
563 | struct be_tx_obj *tx_obj = &adapter->tx_obj; | |
564 | struct be_queue_info *txq = &tx_obj->q; | |
565 | u32 wrb_cnt = 0, copied = 0; | |
566 | u32 start = txq->head; | |
567 | bool dummy_wrb, stopped = false; | |
568 | ||
569 | wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb); | |
570 | ||
571 | copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb); | |
c190e3c8 AK |
572 | if (copied) { |
573 | /* record the sent skb in the sent_skb table */ | |
574 | BUG_ON(tx_obj->sent_skb_list[start]); | |
575 | tx_obj->sent_skb_list[start] = skb; | |
576 | ||
577 | /* Ensure txq has space for the next skb; Else stop the queue | |
578 | * *BEFORE* ringing the tx doorbell, so that we serialze the | |
579 | * tx compls of the current transmit which'll wake up the queue | |
580 | */ | |
7101e111 | 581 | atomic_add(wrb_cnt, &txq->used); |
c190e3c8 AK |
582 | if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >= |
583 | txq->len) { | |
584 | netif_stop_queue(netdev); | |
585 | stopped = true; | |
586 | } | |
6b7c5b94 | 587 | |
c190e3c8 | 588 | be_txq_notify(adapter, txq->id, wrb_cnt); |
6b7c5b94 | 589 | |
91992e44 AK |
590 | be_tx_stats_update(adapter, wrb_cnt, copied, |
591 | skb_shinfo(skb)->gso_segs, stopped); | |
c190e3c8 AK |
592 | } else { |
593 | txq->head = start; | |
594 | dev_kfree_skb_any(skb); | |
6b7c5b94 | 595 | } |
6b7c5b94 SP |
596 | return NETDEV_TX_OK; |
597 | } | |
598 | ||
599 | static int be_change_mtu(struct net_device *netdev, int new_mtu) | |
600 | { | |
601 | struct be_adapter *adapter = netdev_priv(netdev); | |
602 | if (new_mtu < BE_MIN_MTU || | |
34a89b8c AK |
603 | new_mtu > (BE_MAX_JUMBO_FRAME_SIZE - |
604 | (ETH_HLEN + ETH_FCS_LEN))) { | |
6b7c5b94 SP |
605 | dev_info(&adapter->pdev->dev, |
606 | "MTU must be between %d and %d bytes\n", | |
34a89b8c AK |
607 | BE_MIN_MTU, |
608 | (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN))); | |
6b7c5b94 SP |
609 | return -EINVAL; |
610 | } | |
611 | dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n", | |
612 | netdev->mtu, new_mtu); | |
613 | netdev->mtu = new_mtu; | |
614 | return 0; | |
615 | } | |
616 | ||
617 | /* | |
82903e4b AK |
618 | * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE. |
619 | * If the user configures more, place BE in vlan promiscuous mode. | |
6b7c5b94 | 620 | */ |
1da87b7f | 621 | static int be_vid_config(struct be_adapter *adapter, bool vf, u32 vf_num) |
6b7c5b94 | 622 | { |
6b7c5b94 SP |
623 | u16 vtag[BE_NUM_VLANS_SUPPORTED]; |
624 | u16 ntags = 0, i; | |
82903e4b | 625 | int status = 0; |
1da87b7f AK |
626 | u32 if_handle; |
627 | ||
628 | if (vf) { | |
629 | if_handle = adapter->vf_cfg[vf_num].vf_if_handle; | |
630 | vtag[0] = cpu_to_le16(adapter->vf_cfg[vf_num].vf_vlan_tag); | |
631 | status = be_cmd_vlan_config(adapter, if_handle, vtag, 1, 1, 0); | |
632 | } | |
6b7c5b94 | 633 | |
82903e4b | 634 | if (adapter->vlans_added <= adapter->max_vlans) { |
6b7c5b94 | 635 | /* Construct VLAN Table to give to HW */ |
b738127d | 636 | for (i = 0; i < VLAN_N_VID; i++) { |
6b7c5b94 SP |
637 | if (adapter->vlan_tag[i]) { |
638 | vtag[ntags] = cpu_to_le16(i); | |
639 | ntags++; | |
640 | } | |
641 | } | |
b31c50a7 SP |
642 | status = be_cmd_vlan_config(adapter, adapter->if_handle, |
643 | vtag, ntags, 1, 0); | |
6b7c5b94 | 644 | } else { |
b31c50a7 SP |
645 | status = be_cmd_vlan_config(adapter, adapter->if_handle, |
646 | NULL, 0, 1, 1); | |
6b7c5b94 | 647 | } |
1da87b7f | 648 | |
b31c50a7 | 649 | return status; |
6b7c5b94 SP |
650 | } |
651 | ||
652 | static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp) | |
653 | { | |
654 | struct be_adapter *adapter = netdev_priv(netdev); | |
6b7c5b94 | 655 | |
6b7c5b94 | 656 | adapter->vlan_grp = grp; |
6b7c5b94 SP |
657 | } |
658 | ||
659 | static void be_vlan_add_vid(struct net_device *netdev, u16 vid) | |
660 | { | |
661 | struct be_adapter *adapter = netdev_priv(netdev); | |
662 | ||
1da87b7f | 663 | adapter->vlans_added++; |
ba343c77 SB |
664 | if (!be_physfn(adapter)) |
665 | return; | |
666 | ||
6b7c5b94 | 667 | adapter->vlan_tag[vid] = 1; |
82903e4b | 668 | if (adapter->vlans_added <= (adapter->max_vlans + 1)) |
1da87b7f | 669 | be_vid_config(adapter, false, 0); |
6b7c5b94 SP |
670 | } |
671 | ||
672 | static void be_vlan_rem_vid(struct net_device *netdev, u16 vid) | |
673 | { | |
674 | struct be_adapter *adapter = netdev_priv(netdev); | |
675 | ||
1da87b7f AK |
676 | adapter->vlans_added--; |
677 | vlan_group_set_device(adapter->vlan_grp, vid, NULL); | |
678 | ||
ba343c77 SB |
679 | if (!be_physfn(adapter)) |
680 | return; | |
681 | ||
6b7c5b94 | 682 | adapter->vlan_tag[vid] = 0; |
82903e4b | 683 | if (adapter->vlans_added <= adapter->max_vlans) |
1da87b7f | 684 | be_vid_config(adapter, false, 0); |
6b7c5b94 SP |
685 | } |
686 | ||
24307eef | 687 | static void be_set_multicast_list(struct net_device *netdev) |
6b7c5b94 SP |
688 | { |
689 | struct be_adapter *adapter = netdev_priv(netdev); | |
6b7c5b94 | 690 | |
24307eef | 691 | if (netdev->flags & IFF_PROMISC) { |
8788fdc2 | 692 | be_cmd_promiscuous_config(adapter, adapter->port_num, 1); |
24307eef SP |
693 | adapter->promiscuous = true; |
694 | goto done; | |
6b7c5b94 SP |
695 | } |
696 | ||
24307eef SP |
697 | /* BE was previously in promiscous mode; disable it */ |
698 | if (adapter->promiscuous) { | |
699 | adapter->promiscuous = false; | |
8788fdc2 | 700 | be_cmd_promiscuous_config(adapter, adapter->port_num, 0); |
6b7c5b94 SP |
701 | } |
702 | ||
e7b909a6 | 703 | /* Enable multicast promisc if num configured exceeds what we support */ |
4cd24eaf JP |
704 | if (netdev->flags & IFF_ALLMULTI || |
705 | netdev_mc_count(netdev) > BE_MAX_MC) { | |
0ddf477b | 706 | be_cmd_multicast_set(adapter, adapter->if_handle, NULL, |
e7b909a6 | 707 | &adapter->mc_cmd_mem); |
24307eef | 708 | goto done; |
6b7c5b94 | 709 | } |
6b7c5b94 | 710 | |
0ddf477b | 711 | be_cmd_multicast_set(adapter, adapter->if_handle, netdev, |
f31e50a8 | 712 | &adapter->mc_cmd_mem); |
24307eef SP |
713 | done: |
714 | return; | |
6b7c5b94 SP |
715 | } |
716 | ||
ba343c77 SB |
717 | static int be_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) |
718 | { | |
719 | struct be_adapter *adapter = netdev_priv(netdev); | |
720 | int status; | |
721 | ||
722 | if (!adapter->sriov_enabled) | |
723 | return -EPERM; | |
724 | ||
725 | if (!is_valid_ether_addr(mac) || (vf >= num_vfs)) | |
726 | return -EINVAL; | |
727 | ||
64600ea5 AK |
728 | if (adapter->vf_cfg[vf].vf_pmac_id != BE_INVALID_PMAC_ID) |
729 | status = be_cmd_pmac_del(adapter, | |
730 | adapter->vf_cfg[vf].vf_if_handle, | |
731 | adapter->vf_cfg[vf].vf_pmac_id); | |
ba343c77 | 732 | |
64600ea5 AK |
733 | status = be_cmd_pmac_add(adapter, mac, |
734 | adapter->vf_cfg[vf].vf_if_handle, | |
735 | &adapter->vf_cfg[vf].vf_pmac_id); | |
736 | ||
737 | if (status) | |
ba343c77 SB |
738 | dev_err(&adapter->pdev->dev, "MAC %pM set on VF %d Failed\n", |
739 | mac, vf); | |
64600ea5 AK |
740 | else |
741 | memcpy(adapter->vf_cfg[vf].vf_mac_addr, mac, ETH_ALEN); | |
742 | ||
ba343c77 SB |
743 | return status; |
744 | } | |
745 | ||
64600ea5 AK |
746 | static int be_get_vf_config(struct net_device *netdev, int vf, |
747 | struct ifla_vf_info *vi) | |
748 | { | |
749 | struct be_adapter *adapter = netdev_priv(netdev); | |
750 | ||
751 | if (!adapter->sriov_enabled) | |
752 | return -EPERM; | |
753 | ||
754 | if (vf >= num_vfs) | |
755 | return -EINVAL; | |
756 | ||
757 | vi->vf = vf; | |
e1d18735 | 758 | vi->tx_rate = adapter->vf_cfg[vf].vf_tx_rate; |
1da87b7f | 759 | vi->vlan = adapter->vf_cfg[vf].vf_vlan_tag; |
64600ea5 AK |
760 | vi->qos = 0; |
761 | memcpy(&vi->mac, adapter->vf_cfg[vf].vf_mac_addr, ETH_ALEN); | |
762 | ||
763 | return 0; | |
764 | } | |
765 | ||
1da87b7f AK |
766 | static int be_set_vf_vlan(struct net_device *netdev, |
767 | int vf, u16 vlan, u8 qos) | |
768 | { | |
769 | struct be_adapter *adapter = netdev_priv(netdev); | |
770 | int status = 0; | |
771 | ||
772 | if (!adapter->sriov_enabled) | |
773 | return -EPERM; | |
774 | ||
775 | if ((vf >= num_vfs) || (vlan > 4095)) | |
776 | return -EINVAL; | |
777 | ||
778 | if (vlan) { | |
779 | adapter->vf_cfg[vf].vf_vlan_tag = vlan; | |
780 | adapter->vlans_added++; | |
781 | } else { | |
782 | adapter->vf_cfg[vf].vf_vlan_tag = 0; | |
783 | adapter->vlans_added--; | |
784 | } | |
785 | ||
786 | status = be_vid_config(adapter, true, vf); | |
787 | ||
788 | if (status) | |
789 | dev_info(&adapter->pdev->dev, | |
790 | "VLAN %d config on VF %d failed\n", vlan, vf); | |
791 | return status; | |
792 | } | |
793 | ||
e1d18735 AK |
794 | static int be_set_vf_tx_rate(struct net_device *netdev, |
795 | int vf, int rate) | |
796 | { | |
797 | struct be_adapter *adapter = netdev_priv(netdev); | |
798 | int status = 0; | |
799 | ||
800 | if (!adapter->sriov_enabled) | |
801 | return -EPERM; | |
802 | ||
803 | if ((vf >= num_vfs) || (rate < 0)) | |
804 | return -EINVAL; | |
805 | ||
806 | if (rate > 10000) | |
807 | rate = 10000; | |
808 | ||
809 | adapter->vf_cfg[vf].vf_tx_rate = rate; | |
810 | status = be_cmd_set_qos(adapter, rate / 10, vf); | |
811 | ||
812 | if (status) | |
813 | dev_info(&adapter->pdev->dev, | |
814 | "tx rate %d on VF %d failed\n", rate, vf); | |
815 | return status; | |
816 | } | |
817 | ||
3abcdeda | 818 | static void be_rx_rate_update(struct be_rx_obj *rxo) |
6b7c5b94 | 819 | { |
3abcdeda | 820 | struct be_rx_stats *stats = &rxo->stats; |
4097f663 | 821 | ulong now = jiffies; |
6b7c5b94 | 822 | |
4097f663 | 823 | /* Wrapped around */ |
3abcdeda SP |
824 | if (time_before(now, stats->rx_jiffies)) { |
825 | stats->rx_jiffies = now; | |
4097f663 SP |
826 | return; |
827 | } | |
6b7c5b94 SP |
828 | |
829 | /* Update the rate once in two seconds */ | |
3abcdeda | 830 | if ((now - stats->rx_jiffies) < 2 * HZ) |
6b7c5b94 SP |
831 | return; |
832 | ||
3abcdeda SP |
833 | stats->rx_rate = be_calc_rate(stats->rx_bytes - stats->rx_bytes_prev, |
834 | now - stats->rx_jiffies); | |
835 | stats->rx_jiffies = now; | |
836 | stats->rx_bytes_prev = stats->rx_bytes; | |
6b7c5b94 SP |
837 | } |
838 | ||
3abcdeda | 839 | static void be_rx_stats_update(struct be_rx_obj *rxo, |
1ef78abe | 840 | u32 pktsize, u16 numfrags, u8 pkt_type) |
4097f663 | 841 | { |
3abcdeda | 842 | struct be_rx_stats *stats = &rxo->stats; |
1ef78abe | 843 | |
3abcdeda SP |
844 | stats->rx_compl++; |
845 | stats->rx_frags += numfrags; | |
846 | stats->rx_bytes += pktsize; | |
847 | stats->rx_pkts++; | |
1ef78abe | 848 | if (pkt_type == BE_MULTICAST_PACKET) |
3abcdeda | 849 | stats->rx_mcast_pkts++; |
4097f663 SP |
850 | } |
851 | ||
c6ce2f4b | 852 | static inline bool csum_passed(struct be_eth_rx_compl *rxcp) |
728a9972 | 853 | { |
c6ce2f4b | 854 | u8 l4_cksm, ipv6, ipcksm; |
728a9972 AK |
855 | |
856 | l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp); | |
857 | ipcksm = AMAP_GET_BITS(struct amap_eth_rx_compl, ipcksm, rxcp); | |
c6ce2f4b | 858 | ipv6 = AMAP_GET_BITS(struct amap_eth_rx_compl, ip_version, rxcp); |
728a9972 | 859 | |
c6ce2f4b SK |
860 | /* Ignore ipcksm for ipv6 pkts */ |
861 | return l4_cksm && (ipcksm || ipv6); | |
728a9972 AK |
862 | } |
863 | ||
6b7c5b94 | 864 | static struct be_rx_page_info * |
3abcdeda SP |
865 | get_rx_page_info(struct be_adapter *adapter, |
866 | struct be_rx_obj *rxo, | |
867 | u16 frag_idx) | |
6b7c5b94 SP |
868 | { |
869 | struct be_rx_page_info *rx_page_info; | |
3abcdeda | 870 | struct be_queue_info *rxq = &rxo->q; |
6b7c5b94 | 871 | |
3abcdeda | 872 | rx_page_info = &rxo->page_info_tbl[frag_idx]; |
6b7c5b94 SP |
873 | BUG_ON(!rx_page_info->page); |
874 | ||
205859a2 | 875 | if (rx_page_info->last_page_user) { |
fac6da5b | 876 | pci_unmap_page(adapter->pdev, dma_unmap_addr(rx_page_info, bus), |
6b7c5b94 | 877 | adapter->big_page_size, PCI_DMA_FROMDEVICE); |
205859a2 AK |
878 | rx_page_info->last_page_user = false; |
879 | } | |
6b7c5b94 SP |
880 | |
881 | atomic_dec(&rxq->used); | |
882 | return rx_page_info; | |
883 | } | |
884 | ||
885 | /* Throwaway the data in the Rx completion */ | |
886 | static void be_rx_compl_discard(struct be_adapter *adapter, | |
3abcdeda SP |
887 | struct be_rx_obj *rxo, |
888 | struct be_eth_rx_compl *rxcp) | |
6b7c5b94 | 889 | { |
3abcdeda | 890 | struct be_queue_info *rxq = &rxo->q; |
6b7c5b94 SP |
891 | struct be_rx_page_info *page_info; |
892 | u16 rxq_idx, i, num_rcvd; | |
893 | ||
894 | rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp); | |
895 | num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp); | |
896 | ||
897 | for (i = 0; i < num_rcvd; i++) { | |
3abcdeda | 898 | page_info = get_rx_page_info(adapter, rxo, rxq_idx); |
6b7c5b94 SP |
899 | put_page(page_info->page); |
900 | memset(page_info, 0, sizeof(*page_info)); | |
901 | index_inc(&rxq_idx, rxq->len); | |
902 | } | |
903 | } | |
904 | ||
905 | /* | |
906 | * skb_fill_rx_data forms a complete skb for an ether frame | |
907 | * indicated by rxcp. | |
908 | */ | |
3abcdeda | 909 | static void skb_fill_rx_data(struct be_adapter *adapter, struct be_rx_obj *rxo, |
89420424 SP |
910 | struct sk_buff *skb, struct be_eth_rx_compl *rxcp, |
911 | u16 num_rcvd) | |
6b7c5b94 | 912 | { |
3abcdeda | 913 | struct be_queue_info *rxq = &rxo->q; |
6b7c5b94 | 914 | struct be_rx_page_info *page_info; |
89420424 | 915 | u16 rxq_idx, i, j; |
fa77406a | 916 | u32 pktsize, hdr_len, curr_frag_len, size; |
6b7c5b94 | 917 | u8 *start; |
1ef78abe | 918 | u8 pkt_type; |
6b7c5b94 SP |
919 | |
920 | rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp); | |
921 | pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp); | |
1ef78abe | 922 | pkt_type = AMAP_GET_BITS(struct amap_eth_rx_compl, cast_enc, rxcp); |
6b7c5b94 | 923 | |
3abcdeda | 924 | page_info = get_rx_page_info(adapter, rxo, rxq_idx); |
6b7c5b94 SP |
925 | |
926 | start = page_address(page_info->page) + page_info->page_offset; | |
927 | prefetch(start); | |
928 | ||
929 | /* Copy data in the first descriptor of this completion */ | |
930 | curr_frag_len = min(pktsize, rx_frag_size); | |
931 | ||
932 | /* Copy the header portion into skb_data */ | |
933 | hdr_len = min((u32)BE_HDR_LEN, curr_frag_len); | |
934 | memcpy(skb->data, start, hdr_len); | |
935 | skb->len = curr_frag_len; | |
936 | if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */ | |
937 | /* Complete packet has now been moved to data */ | |
938 | put_page(page_info->page); | |
939 | skb->data_len = 0; | |
940 | skb->tail += curr_frag_len; | |
941 | } else { | |
942 | skb_shinfo(skb)->nr_frags = 1; | |
943 | skb_shinfo(skb)->frags[0].page = page_info->page; | |
944 | skb_shinfo(skb)->frags[0].page_offset = | |
945 | page_info->page_offset + hdr_len; | |
946 | skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len; | |
947 | skb->data_len = curr_frag_len - hdr_len; | |
948 | skb->tail += hdr_len; | |
949 | } | |
205859a2 | 950 | page_info->page = NULL; |
6b7c5b94 SP |
951 | |
952 | if (pktsize <= rx_frag_size) { | |
953 | BUG_ON(num_rcvd != 1); | |
76fbb429 | 954 | goto done; |
6b7c5b94 SP |
955 | } |
956 | ||
957 | /* More frags present for this completion */ | |
fa77406a | 958 | size = pktsize; |
bd46cb6c | 959 | for (i = 1, j = 0; i < num_rcvd; i++) { |
fa77406a | 960 | size -= curr_frag_len; |
6b7c5b94 | 961 | index_inc(&rxq_idx, rxq->len); |
3abcdeda | 962 | page_info = get_rx_page_info(adapter, rxo, rxq_idx); |
6b7c5b94 | 963 | |
fa77406a | 964 | curr_frag_len = min(size, rx_frag_size); |
6b7c5b94 | 965 | |
bd46cb6c AK |
966 | /* Coalesce all frags from the same physical page in one slot */ |
967 | if (page_info->page_offset == 0) { | |
968 | /* Fresh page */ | |
969 | j++; | |
970 | skb_shinfo(skb)->frags[j].page = page_info->page; | |
971 | skb_shinfo(skb)->frags[j].page_offset = | |
972 | page_info->page_offset; | |
973 | skb_shinfo(skb)->frags[j].size = 0; | |
974 | skb_shinfo(skb)->nr_frags++; | |
975 | } else { | |
976 | put_page(page_info->page); | |
977 | } | |
978 | ||
979 | skb_shinfo(skb)->frags[j].size += curr_frag_len; | |
6b7c5b94 SP |
980 | skb->len += curr_frag_len; |
981 | skb->data_len += curr_frag_len; | |
6b7c5b94 | 982 | |
205859a2 | 983 | page_info->page = NULL; |
6b7c5b94 | 984 | } |
bd46cb6c | 985 | BUG_ON(j > MAX_SKB_FRAGS); |
6b7c5b94 | 986 | |
76fbb429 | 987 | done: |
3abcdeda | 988 | be_rx_stats_update(rxo, pktsize, num_rcvd, pkt_type); |
6b7c5b94 SP |
989 | } |
990 | ||
5be93b9a | 991 | /* Process the RX completion indicated by rxcp when GRO is disabled */ |
6b7c5b94 | 992 | static void be_rx_compl_process(struct be_adapter *adapter, |
3abcdeda | 993 | struct be_rx_obj *rxo, |
6b7c5b94 SP |
994 | struct be_eth_rx_compl *rxcp) |
995 | { | |
996 | struct sk_buff *skb; | |
dcb9b564 | 997 | u32 vlanf, vid; |
89420424 | 998 | u16 num_rcvd; |
dcb9b564 | 999 | u8 vtm; |
6b7c5b94 | 1000 | |
89420424 SP |
1001 | num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp); |
1002 | /* Is it a flush compl that has no data */ | |
1003 | if (unlikely(num_rcvd == 0)) | |
1004 | return; | |
1005 | ||
89d71a66 | 1006 | skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN); |
a058a632 | 1007 | if (unlikely(!skb)) { |
6b7c5b94 SP |
1008 | if (net_ratelimit()) |
1009 | dev_warn(&adapter->pdev->dev, "skb alloc failed\n"); | |
3abcdeda | 1010 | be_rx_compl_discard(adapter, rxo, rxcp); |
6b7c5b94 SP |
1011 | return; |
1012 | } | |
1013 | ||
3abcdeda | 1014 | skb_fill_rx_data(adapter, rxo, skb, rxcp, num_rcvd); |
6b7c5b94 | 1015 | |
c6ce2f4b | 1016 | if (likely(adapter->rx_csum && csum_passed(rxcp))) |
728a9972 | 1017 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
c6ce2f4b SK |
1018 | else |
1019 | skb_checksum_none_assert(skb); | |
6b7c5b94 SP |
1020 | |
1021 | skb->truesize = skb->len + sizeof(struct sk_buff); | |
1022 | skb->protocol = eth_type_trans(skb, adapter->netdev); | |
6b7c5b94 | 1023 | |
a058a632 SP |
1024 | vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp); |
1025 | vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp); | |
1026 | ||
1027 | /* vlanf could be wrongly set in some cards. | |
1028 | * ignore if vtm is not set */ | |
3486be29 | 1029 | if ((adapter->function_mode & 0x400) && !vtm) |
a058a632 SP |
1030 | vlanf = 0; |
1031 | ||
1032 | if (unlikely(vlanf)) { | |
82903e4b | 1033 | if (!adapter->vlan_grp || adapter->vlans_added == 0) { |
6b7c5b94 SP |
1034 | kfree_skb(skb); |
1035 | return; | |
1036 | } | |
1037 | vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp); | |
9cae9e4f | 1038 | vid = swab16(vid); |
6b7c5b94 SP |
1039 | vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid); |
1040 | } else { | |
1041 | netif_receive_skb(skb); | |
1042 | } | |
6b7c5b94 SP |
1043 | } |
1044 | ||
5be93b9a AK |
1045 | /* Process the RX completion indicated by rxcp when GRO is enabled */ |
1046 | static void be_rx_compl_process_gro(struct be_adapter *adapter, | |
3abcdeda SP |
1047 | struct be_rx_obj *rxo, |
1048 | struct be_eth_rx_compl *rxcp) | |
6b7c5b94 SP |
1049 | { |
1050 | struct be_rx_page_info *page_info; | |
5be93b9a | 1051 | struct sk_buff *skb = NULL; |
3abcdeda SP |
1052 | struct be_queue_info *rxq = &rxo->q; |
1053 | struct be_eq_obj *eq_obj = &rxo->rx_eq; | |
6b7c5b94 | 1054 | u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len; |
bd46cb6c | 1055 | u16 i, rxq_idx = 0, vid, j; |
dcb9b564 | 1056 | u8 vtm; |
1ef78abe | 1057 | u8 pkt_type; |
6b7c5b94 SP |
1058 | |
1059 | num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp); | |
89420424 SP |
1060 | /* Is it a flush compl that has no data */ |
1061 | if (unlikely(num_rcvd == 0)) | |
1062 | return; | |
1063 | ||
6b7c5b94 SP |
1064 | pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp); |
1065 | vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp); | |
1066 | rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp); | |
dcb9b564 | 1067 | vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp); |
1ef78abe | 1068 | pkt_type = AMAP_GET_BITS(struct amap_eth_rx_compl, cast_enc, rxcp); |
dcb9b564 AK |
1069 | |
1070 | /* vlanf could be wrongly set in some cards. | |
1071 | * ignore if vtm is not set */ | |
3486be29 | 1072 | if ((adapter->function_mode & 0x400) && !vtm) |
dcb9b564 | 1073 | vlanf = 0; |
6b7c5b94 | 1074 | |
5be93b9a AK |
1075 | skb = napi_get_frags(&eq_obj->napi); |
1076 | if (!skb) { | |
3abcdeda | 1077 | be_rx_compl_discard(adapter, rxo, rxcp); |
5be93b9a AK |
1078 | return; |
1079 | } | |
1080 | ||
6b7c5b94 | 1081 | remaining = pkt_size; |
bd46cb6c | 1082 | for (i = 0, j = -1; i < num_rcvd; i++) { |
3abcdeda | 1083 | page_info = get_rx_page_info(adapter, rxo, rxq_idx); |
6b7c5b94 SP |
1084 | |
1085 | curr_frag_len = min(remaining, rx_frag_size); | |
1086 | ||
bd46cb6c AK |
1087 | /* Coalesce all frags from the same physical page in one slot */ |
1088 | if (i == 0 || page_info->page_offset == 0) { | |
1089 | /* First frag or Fresh page */ | |
1090 | j++; | |
5be93b9a AK |
1091 | skb_shinfo(skb)->frags[j].page = page_info->page; |
1092 | skb_shinfo(skb)->frags[j].page_offset = | |
1093 | page_info->page_offset; | |
1094 | skb_shinfo(skb)->frags[j].size = 0; | |
bd46cb6c AK |
1095 | } else { |
1096 | put_page(page_info->page); | |
1097 | } | |
5be93b9a | 1098 | skb_shinfo(skb)->frags[j].size += curr_frag_len; |
6b7c5b94 | 1099 | |
bd46cb6c | 1100 | remaining -= curr_frag_len; |
6b7c5b94 | 1101 | index_inc(&rxq_idx, rxq->len); |
6b7c5b94 SP |
1102 | memset(page_info, 0, sizeof(*page_info)); |
1103 | } | |
bd46cb6c | 1104 | BUG_ON(j > MAX_SKB_FRAGS); |
6b7c5b94 | 1105 | |
5be93b9a AK |
1106 | skb_shinfo(skb)->nr_frags = j + 1; |
1107 | skb->len = pkt_size; | |
1108 | skb->data_len = pkt_size; | |
1109 | skb->truesize += pkt_size; | |
1110 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1111 | ||
6b7c5b94 | 1112 | if (likely(!vlanf)) { |
5be93b9a | 1113 | napi_gro_frags(&eq_obj->napi); |
6b7c5b94 SP |
1114 | } else { |
1115 | vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp); | |
9cae9e4f | 1116 | vid = swab16(vid); |
6b7c5b94 | 1117 | |
82903e4b | 1118 | if (!adapter->vlan_grp || adapter->vlans_added == 0) |
6b7c5b94 SP |
1119 | return; |
1120 | ||
5be93b9a | 1121 | vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, vid); |
6b7c5b94 SP |
1122 | } |
1123 | ||
3abcdeda | 1124 | be_rx_stats_update(rxo, pkt_size, num_rcvd, pkt_type); |
6b7c5b94 SP |
1125 | } |
1126 | ||
3abcdeda | 1127 | static struct be_eth_rx_compl *be_rx_compl_get(struct be_rx_obj *rxo) |
6b7c5b94 | 1128 | { |
3abcdeda | 1129 | struct be_eth_rx_compl *rxcp = queue_tail_node(&rxo->cq); |
6b7c5b94 SP |
1130 | |
1131 | if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0) | |
1132 | return NULL; | |
1133 | ||
f3eb62d2 | 1134 | rmb(); |
6b7c5b94 SP |
1135 | be_dws_le_to_cpu(rxcp, sizeof(*rxcp)); |
1136 | ||
3abcdeda | 1137 | queue_tail_inc(&rxo->cq); |
6b7c5b94 SP |
1138 | return rxcp; |
1139 | } | |
1140 | ||
a7a0ef31 SP |
1141 | /* To reset the valid bit, we need to reset the whole word as |
1142 | * when walking the queue the valid entries are little-endian | |
1143 | * and invalid entries are host endian | |
1144 | */ | |
1145 | static inline void be_rx_compl_reset(struct be_eth_rx_compl *rxcp) | |
1146 | { | |
1147 | rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0; | |
1148 | } | |
1149 | ||
6b7c5b94 SP |
1150 | static inline struct page *be_alloc_pages(u32 size) |
1151 | { | |
1152 | gfp_t alloc_flags = GFP_ATOMIC; | |
1153 | u32 order = get_order(size); | |
1154 | if (order > 0) | |
1155 | alloc_flags |= __GFP_COMP; | |
1156 | return alloc_pages(alloc_flags, order); | |
1157 | } | |
1158 | ||
1159 | /* | |
1160 | * Allocate a page, split it to fragments of size rx_frag_size and post as | |
1161 | * receive buffers to BE | |
1162 | */ | |
3abcdeda | 1163 | static void be_post_rx_frags(struct be_rx_obj *rxo) |
6b7c5b94 | 1164 | { |
3abcdeda SP |
1165 | struct be_adapter *adapter = rxo->adapter; |
1166 | struct be_rx_page_info *page_info_tbl = rxo->page_info_tbl; | |
26d92f92 | 1167 | struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL; |
3abcdeda | 1168 | struct be_queue_info *rxq = &rxo->q; |
6b7c5b94 SP |
1169 | struct page *pagep = NULL; |
1170 | struct be_eth_rx_d *rxd; | |
1171 | u64 page_dmaaddr = 0, frag_dmaaddr; | |
1172 | u32 posted, page_offset = 0; | |
1173 | ||
3abcdeda | 1174 | page_info = &rxo->page_info_tbl[rxq->head]; |
6b7c5b94 SP |
1175 | for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) { |
1176 | if (!pagep) { | |
1177 | pagep = be_alloc_pages(adapter->big_page_size); | |
1178 | if (unlikely(!pagep)) { | |
3abcdeda | 1179 | rxo->stats.rx_post_fail++; |
6b7c5b94 SP |
1180 | break; |
1181 | } | |
1182 | page_dmaaddr = pci_map_page(adapter->pdev, pagep, 0, | |
1183 | adapter->big_page_size, | |
1184 | PCI_DMA_FROMDEVICE); | |
1185 | page_info->page_offset = 0; | |
1186 | } else { | |
1187 | get_page(pagep); | |
1188 | page_info->page_offset = page_offset + rx_frag_size; | |
1189 | } | |
1190 | page_offset = page_info->page_offset; | |
1191 | page_info->page = pagep; | |
fac6da5b | 1192 | dma_unmap_addr_set(page_info, bus, page_dmaaddr); |
6b7c5b94 SP |
1193 | frag_dmaaddr = page_dmaaddr + page_info->page_offset; |
1194 | ||
1195 | rxd = queue_head_node(rxq); | |
1196 | rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF); | |
1197 | rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr)); | |
6b7c5b94 SP |
1198 | |
1199 | /* Any space left in the current big page for another frag? */ | |
1200 | if ((page_offset + rx_frag_size + rx_frag_size) > | |
1201 | adapter->big_page_size) { | |
1202 | pagep = NULL; | |
1203 | page_info->last_page_user = true; | |
1204 | } | |
26d92f92 SP |
1205 | |
1206 | prev_page_info = page_info; | |
1207 | queue_head_inc(rxq); | |
6b7c5b94 SP |
1208 | page_info = &page_info_tbl[rxq->head]; |
1209 | } | |
1210 | if (pagep) | |
26d92f92 | 1211 | prev_page_info->last_page_user = true; |
6b7c5b94 SP |
1212 | |
1213 | if (posted) { | |
6b7c5b94 | 1214 | atomic_add(posted, &rxq->used); |
8788fdc2 | 1215 | be_rxq_notify(adapter, rxq->id, posted); |
ea1dae11 SP |
1216 | } else if (atomic_read(&rxq->used) == 0) { |
1217 | /* Let be_worker replenish when memory is available */ | |
3abcdeda | 1218 | rxo->rx_post_starved = true; |
6b7c5b94 | 1219 | } |
6b7c5b94 SP |
1220 | } |
1221 | ||
5fb379ee | 1222 | static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq) |
6b7c5b94 | 1223 | { |
6b7c5b94 SP |
1224 | struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq); |
1225 | ||
1226 | if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0) | |
1227 | return NULL; | |
1228 | ||
f3eb62d2 | 1229 | rmb(); |
6b7c5b94 SP |
1230 | be_dws_le_to_cpu(txcp, sizeof(*txcp)); |
1231 | ||
1232 | txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0; | |
1233 | ||
1234 | queue_tail_inc(tx_cq); | |
1235 | return txcp; | |
1236 | } | |
1237 | ||
1238 | static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index) | |
1239 | { | |
1240 | struct be_queue_info *txq = &adapter->tx_obj.q; | |
a73b796e | 1241 | struct be_eth_wrb *wrb; |
6b7c5b94 SP |
1242 | struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list; |
1243 | struct sk_buff *sent_skb; | |
ec43b1a6 SP |
1244 | u16 cur_index, num_wrbs = 1; /* account for hdr wrb */ |
1245 | bool unmap_skb_hdr = true; | |
6b7c5b94 | 1246 | |
ec43b1a6 | 1247 | sent_skb = sent_skbs[txq->tail]; |
6b7c5b94 | 1248 | BUG_ON(!sent_skb); |
ec43b1a6 SP |
1249 | sent_skbs[txq->tail] = NULL; |
1250 | ||
1251 | /* skip header wrb */ | |
a73b796e | 1252 | queue_tail_inc(txq); |
6b7c5b94 | 1253 | |
ec43b1a6 | 1254 | do { |
6b7c5b94 | 1255 | cur_index = txq->tail; |
a73b796e | 1256 | wrb = queue_tail_node(txq); |
ec43b1a6 | 1257 | unmap_tx_frag(adapter->pdev, wrb, (unmap_skb_hdr && |
e743d313 | 1258 | skb_headlen(sent_skb))); |
ec43b1a6 SP |
1259 | unmap_skb_hdr = false; |
1260 | ||
6b7c5b94 SP |
1261 | num_wrbs++; |
1262 | queue_tail_inc(txq); | |
ec43b1a6 | 1263 | } while (cur_index != last_index); |
6b7c5b94 SP |
1264 | |
1265 | atomic_sub(num_wrbs, &txq->used); | |
a73b796e | 1266 | |
6b7c5b94 SP |
1267 | kfree_skb(sent_skb); |
1268 | } | |
1269 | ||
859b1e4e SP |
1270 | static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj) |
1271 | { | |
1272 | struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q); | |
1273 | ||
1274 | if (!eqe->evt) | |
1275 | return NULL; | |
1276 | ||
f3eb62d2 | 1277 | rmb(); |
859b1e4e SP |
1278 | eqe->evt = le32_to_cpu(eqe->evt); |
1279 | queue_tail_inc(&eq_obj->q); | |
1280 | return eqe; | |
1281 | } | |
1282 | ||
1283 | static int event_handle(struct be_adapter *adapter, | |
1284 | struct be_eq_obj *eq_obj) | |
1285 | { | |
1286 | struct be_eq_entry *eqe; | |
1287 | u16 num = 0; | |
1288 | ||
1289 | while ((eqe = event_get(eq_obj)) != NULL) { | |
1290 | eqe->evt = 0; | |
1291 | num++; | |
1292 | } | |
1293 | ||
1294 | /* Deal with any spurious interrupts that come | |
1295 | * without events | |
1296 | */ | |
1297 | be_eq_notify(adapter, eq_obj->q.id, true, true, num); | |
1298 | if (num) | |
1299 | napi_schedule(&eq_obj->napi); | |
1300 | ||
1301 | return num; | |
1302 | } | |
1303 | ||
1304 | /* Just read and notify events without processing them. | |
1305 | * Used at the time of destroying event queues */ | |
1306 | static void be_eq_clean(struct be_adapter *adapter, | |
1307 | struct be_eq_obj *eq_obj) | |
1308 | { | |
1309 | struct be_eq_entry *eqe; | |
1310 | u16 num = 0; | |
1311 | ||
1312 | while ((eqe = event_get(eq_obj)) != NULL) { | |
1313 | eqe->evt = 0; | |
1314 | num++; | |
1315 | } | |
1316 | ||
1317 | if (num) | |
1318 | be_eq_notify(adapter, eq_obj->q.id, false, true, num); | |
1319 | } | |
1320 | ||
3abcdeda | 1321 | static void be_rx_q_clean(struct be_adapter *adapter, struct be_rx_obj *rxo) |
6b7c5b94 SP |
1322 | { |
1323 | struct be_rx_page_info *page_info; | |
3abcdeda SP |
1324 | struct be_queue_info *rxq = &rxo->q; |
1325 | struct be_queue_info *rx_cq = &rxo->cq; | |
6b7c5b94 SP |
1326 | struct be_eth_rx_compl *rxcp; |
1327 | u16 tail; | |
1328 | ||
1329 | /* First cleanup pending rx completions */ | |
3abcdeda SP |
1330 | while ((rxcp = be_rx_compl_get(rxo)) != NULL) { |
1331 | be_rx_compl_discard(adapter, rxo, rxcp); | |
a7a0ef31 | 1332 | be_rx_compl_reset(rxcp); |
8788fdc2 | 1333 | be_cq_notify(adapter, rx_cq->id, true, 1); |
6b7c5b94 SP |
1334 | } |
1335 | ||
1336 | /* Then free posted rx buffer that were not used */ | |
1337 | tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len; | |
cdab23b7 | 1338 | for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) { |
3abcdeda | 1339 | page_info = get_rx_page_info(adapter, rxo, tail); |
6b7c5b94 SP |
1340 | put_page(page_info->page); |
1341 | memset(page_info, 0, sizeof(*page_info)); | |
1342 | } | |
1343 | BUG_ON(atomic_read(&rxq->used)); | |
1344 | } | |
1345 | ||
a8e9179a | 1346 | static void be_tx_compl_clean(struct be_adapter *adapter) |
6b7c5b94 | 1347 | { |
a8e9179a | 1348 | struct be_queue_info *tx_cq = &adapter->tx_obj.cq; |
6b7c5b94 | 1349 | struct be_queue_info *txq = &adapter->tx_obj.q; |
a8e9179a SP |
1350 | struct be_eth_tx_compl *txcp; |
1351 | u16 end_idx, cmpl = 0, timeo = 0; | |
b03388d6 SP |
1352 | struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list; |
1353 | struct sk_buff *sent_skb; | |
1354 | bool dummy_wrb; | |
a8e9179a SP |
1355 | |
1356 | /* Wait for a max of 200ms for all the tx-completions to arrive. */ | |
1357 | do { | |
1358 | while ((txcp = be_tx_compl_get(tx_cq))) { | |
1359 | end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl, | |
1360 | wrb_index, txcp); | |
1361 | be_tx_compl_process(adapter, end_idx); | |
1362 | cmpl++; | |
1363 | } | |
1364 | if (cmpl) { | |
1365 | be_cq_notify(adapter, tx_cq->id, false, cmpl); | |
1366 | cmpl = 0; | |
1367 | } | |
1368 | ||
1369 | if (atomic_read(&txq->used) == 0 || ++timeo > 200) | |
1370 | break; | |
1371 | ||
1372 | mdelay(1); | |
1373 | } while (true); | |
1374 | ||
1375 | if (atomic_read(&txq->used)) | |
1376 | dev_err(&adapter->pdev->dev, "%d pending tx-completions\n", | |
1377 | atomic_read(&txq->used)); | |
b03388d6 SP |
1378 | |
1379 | /* free posted tx for which compls will never arrive */ | |
1380 | while (atomic_read(&txq->used)) { | |
1381 | sent_skb = sent_skbs[txq->tail]; | |
1382 | end_idx = txq->tail; | |
1383 | index_adv(&end_idx, | |
1384 | wrb_cnt_for_skb(sent_skb, &dummy_wrb) - 1, txq->len); | |
1385 | be_tx_compl_process(adapter, end_idx); | |
1386 | } | |
6b7c5b94 SP |
1387 | } |
1388 | ||
5fb379ee SP |
1389 | static void be_mcc_queues_destroy(struct be_adapter *adapter) |
1390 | { | |
1391 | struct be_queue_info *q; | |
5fb379ee | 1392 | |
8788fdc2 | 1393 | q = &adapter->mcc_obj.q; |
5fb379ee | 1394 | if (q->created) |
8788fdc2 | 1395 | be_cmd_q_destroy(adapter, q, QTYPE_MCCQ); |
5fb379ee SP |
1396 | be_queue_free(adapter, q); |
1397 | ||
8788fdc2 | 1398 | q = &adapter->mcc_obj.cq; |
5fb379ee | 1399 | if (q->created) |
8788fdc2 | 1400 | be_cmd_q_destroy(adapter, q, QTYPE_CQ); |
5fb379ee SP |
1401 | be_queue_free(adapter, q); |
1402 | } | |
1403 | ||
1404 | /* Must be called only after TX qs are created as MCC shares TX EQ */ | |
1405 | static int be_mcc_queues_create(struct be_adapter *adapter) | |
1406 | { | |
1407 | struct be_queue_info *q, *cq; | |
5fb379ee SP |
1408 | |
1409 | /* Alloc MCC compl queue */ | |
8788fdc2 | 1410 | cq = &adapter->mcc_obj.cq; |
5fb379ee | 1411 | if (be_queue_alloc(adapter, cq, MCC_CQ_LEN, |
efd2e40a | 1412 | sizeof(struct be_mcc_compl))) |
5fb379ee SP |
1413 | goto err; |
1414 | ||
1415 | /* Ask BE to create MCC compl queue; share TX's eq */ | |
8788fdc2 | 1416 | if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0)) |
5fb379ee SP |
1417 | goto mcc_cq_free; |
1418 | ||
1419 | /* Alloc MCC queue */ | |
8788fdc2 | 1420 | q = &adapter->mcc_obj.q; |
5fb379ee SP |
1421 | if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb))) |
1422 | goto mcc_cq_destroy; | |
1423 | ||
1424 | /* Ask BE to create MCC queue */ | |
8788fdc2 | 1425 | if (be_cmd_mccq_create(adapter, q, cq)) |
5fb379ee SP |
1426 | goto mcc_q_free; |
1427 | ||
1428 | return 0; | |
1429 | ||
1430 | mcc_q_free: | |
1431 | be_queue_free(adapter, q); | |
1432 | mcc_cq_destroy: | |
8788fdc2 | 1433 | be_cmd_q_destroy(adapter, cq, QTYPE_CQ); |
5fb379ee SP |
1434 | mcc_cq_free: |
1435 | be_queue_free(adapter, cq); | |
1436 | err: | |
1437 | return -1; | |
1438 | } | |
1439 | ||
6b7c5b94 SP |
1440 | static void be_tx_queues_destroy(struct be_adapter *adapter) |
1441 | { | |
1442 | struct be_queue_info *q; | |
1443 | ||
1444 | q = &adapter->tx_obj.q; | |
a8e9179a | 1445 | if (q->created) |
8788fdc2 | 1446 | be_cmd_q_destroy(adapter, q, QTYPE_TXQ); |
6b7c5b94 SP |
1447 | be_queue_free(adapter, q); |
1448 | ||
1449 | q = &adapter->tx_obj.cq; | |
1450 | if (q->created) | |
8788fdc2 | 1451 | be_cmd_q_destroy(adapter, q, QTYPE_CQ); |
6b7c5b94 SP |
1452 | be_queue_free(adapter, q); |
1453 | ||
859b1e4e SP |
1454 | /* Clear any residual events */ |
1455 | be_eq_clean(adapter, &adapter->tx_eq); | |
1456 | ||
6b7c5b94 SP |
1457 | q = &adapter->tx_eq.q; |
1458 | if (q->created) | |
8788fdc2 | 1459 | be_cmd_q_destroy(adapter, q, QTYPE_EQ); |
6b7c5b94 SP |
1460 | be_queue_free(adapter, q); |
1461 | } | |
1462 | ||
1463 | static int be_tx_queues_create(struct be_adapter *adapter) | |
1464 | { | |
1465 | struct be_queue_info *eq, *q, *cq; | |
1466 | ||
1467 | adapter->tx_eq.max_eqd = 0; | |
1468 | adapter->tx_eq.min_eqd = 0; | |
1469 | adapter->tx_eq.cur_eqd = 96; | |
1470 | adapter->tx_eq.enable_aic = false; | |
1471 | /* Alloc Tx Event queue */ | |
1472 | eq = &adapter->tx_eq.q; | |
1473 | if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry))) | |
1474 | return -1; | |
1475 | ||
1476 | /* Ask BE to create Tx Event queue */ | |
8788fdc2 | 1477 | if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd)) |
6b7c5b94 | 1478 | goto tx_eq_free; |
ba343c77 SB |
1479 | adapter->base_eq_id = adapter->tx_eq.q.id; |
1480 | ||
6b7c5b94 SP |
1481 | /* Alloc TX eth compl queue */ |
1482 | cq = &adapter->tx_obj.cq; | |
1483 | if (be_queue_alloc(adapter, cq, TX_CQ_LEN, | |
1484 | sizeof(struct be_eth_tx_compl))) | |
1485 | goto tx_eq_destroy; | |
1486 | ||
1487 | /* Ask BE to create Tx eth compl queue */ | |
8788fdc2 | 1488 | if (be_cmd_cq_create(adapter, cq, eq, false, false, 3)) |
6b7c5b94 SP |
1489 | goto tx_cq_free; |
1490 | ||
1491 | /* Alloc TX eth queue */ | |
1492 | q = &adapter->tx_obj.q; | |
1493 | if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb))) | |
1494 | goto tx_cq_destroy; | |
1495 | ||
1496 | /* Ask BE to create Tx eth queue */ | |
8788fdc2 | 1497 | if (be_cmd_txq_create(adapter, q, cq)) |
6b7c5b94 SP |
1498 | goto tx_q_free; |
1499 | return 0; | |
1500 | ||
1501 | tx_q_free: | |
1502 | be_queue_free(adapter, q); | |
1503 | tx_cq_destroy: | |
8788fdc2 | 1504 | be_cmd_q_destroy(adapter, cq, QTYPE_CQ); |
6b7c5b94 SP |
1505 | tx_cq_free: |
1506 | be_queue_free(adapter, cq); | |
1507 | tx_eq_destroy: | |
8788fdc2 | 1508 | be_cmd_q_destroy(adapter, eq, QTYPE_EQ); |
6b7c5b94 SP |
1509 | tx_eq_free: |
1510 | be_queue_free(adapter, eq); | |
1511 | return -1; | |
1512 | } | |
1513 | ||
1514 | static void be_rx_queues_destroy(struct be_adapter *adapter) | |
1515 | { | |
1516 | struct be_queue_info *q; | |
3abcdeda SP |
1517 | struct be_rx_obj *rxo; |
1518 | int i; | |
1519 | ||
1520 | for_all_rx_queues(adapter, rxo, i) { | |
1521 | q = &rxo->q; | |
1522 | if (q->created) { | |
1523 | be_cmd_q_destroy(adapter, q, QTYPE_RXQ); | |
1524 | /* After the rxq is invalidated, wait for a grace time | |
1525 | * of 1ms for all dma to end and the flush compl to | |
1526 | * arrive | |
1527 | */ | |
1528 | mdelay(1); | |
1529 | be_rx_q_clean(adapter, rxo); | |
1530 | } | |
1531 | be_queue_free(adapter, q); | |
1532 | ||
1533 | q = &rxo->cq; | |
1534 | if (q->created) | |
1535 | be_cmd_q_destroy(adapter, q, QTYPE_CQ); | |
1536 | be_queue_free(adapter, q); | |
1537 | ||
1538 | /* Clear any residual events */ | |
1539 | q = &rxo->rx_eq.q; | |
1540 | if (q->created) { | |
1541 | be_eq_clean(adapter, &rxo->rx_eq); | |
1542 | be_cmd_q_destroy(adapter, q, QTYPE_EQ); | |
1543 | } | |
1544 | be_queue_free(adapter, q); | |
6b7c5b94 | 1545 | } |
6b7c5b94 SP |
1546 | } |
1547 | ||
1548 | static int be_rx_queues_create(struct be_adapter *adapter) | |
1549 | { | |
1550 | struct be_queue_info *eq, *q, *cq; | |
3abcdeda SP |
1551 | struct be_rx_obj *rxo; |
1552 | int rc, i; | |
6b7c5b94 | 1553 | |
6b7c5b94 | 1554 | adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE; |
3abcdeda SP |
1555 | for_all_rx_queues(adapter, rxo, i) { |
1556 | rxo->adapter = adapter; | |
1557 | rxo->rx_eq.max_eqd = BE_MAX_EQD; | |
1558 | rxo->rx_eq.enable_aic = true; | |
1559 | ||
1560 | /* EQ */ | |
1561 | eq = &rxo->rx_eq.q; | |
1562 | rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN, | |
1563 | sizeof(struct be_eq_entry)); | |
1564 | if (rc) | |
1565 | goto err; | |
1566 | ||
1567 | rc = be_cmd_eq_create(adapter, eq, rxo->rx_eq.cur_eqd); | |
1568 | if (rc) | |
1569 | goto err; | |
1570 | ||
1571 | /* CQ */ | |
1572 | cq = &rxo->cq; | |
1573 | rc = be_queue_alloc(adapter, cq, RX_CQ_LEN, | |
1574 | sizeof(struct be_eth_rx_compl)); | |
1575 | if (rc) | |
1576 | goto err; | |
1577 | ||
1578 | rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3); | |
1579 | if (rc) | |
1580 | goto err; | |
1581 | ||
1582 | /* Rx Q */ | |
1583 | q = &rxo->q; | |
1584 | rc = be_queue_alloc(adapter, q, RX_Q_LEN, | |
1585 | sizeof(struct be_eth_rx_d)); | |
1586 | if (rc) | |
1587 | goto err; | |
1588 | ||
1589 | rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size, | |
1590 | BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle, | |
1591 | (i > 0) ? 1 : 0/* rss enable */, &rxo->rss_id); | |
1592 | if (rc) | |
1593 | goto err; | |
1594 | } | |
1595 | ||
1596 | if (be_multi_rxq(adapter)) { | |
1597 | u8 rsstable[MAX_RSS_QS]; | |
1598 | ||
1599 | for_all_rss_queues(adapter, rxo, i) | |
1600 | rsstable[i] = rxo->rss_id; | |
1601 | ||
1602 | rc = be_cmd_rss_config(adapter, rsstable, | |
1603 | adapter->num_rx_qs - 1); | |
1604 | if (rc) | |
1605 | goto err; | |
1606 | } | |
6b7c5b94 SP |
1607 | |
1608 | return 0; | |
3abcdeda SP |
1609 | err: |
1610 | be_rx_queues_destroy(adapter); | |
1611 | return -1; | |
6b7c5b94 | 1612 | } |
6b7c5b94 | 1613 | |
b628bde2 SP |
1614 | /* There are 8 evt ids per func. Retruns the evt id's bit number */ |
1615 | static inline int be_evt_bit_get(struct be_adapter *adapter, u32 eq_id) | |
1616 | { | |
ba343c77 | 1617 | return eq_id - adapter->base_eq_id; |
b628bde2 SP |
1618 | } |
1619 | ||
6b7c5b94 SP |
1620 | static irqreturn_t be_intx(int irq, void *dev) |
1621 | { | |
1622 | struct be_adapter *adapter = dev; | |
3abcdeda SP |
1623 | struct be_rx_obj *rxo; |
1624 | int isr, i; | |
6b7c5b94 | 1625 | |
8788fdc2 | 1626 | isr = ioread32(adapter->csr + CEV_ISR0_OFFSET + |
55bdeed9 | 1627 | (adapter->tx_eq.q.id/ 8) * CEV_ISR_SIZE); |
c001c213 | 1628 | if (!isr) |
8788fdc2 | 1629 | return IRQ_NONE; |
6b7c5b94 | 1630 | |
3abcdeda SP |
1631 | if ((1 << be_evt_bit_get(adapter, adapter->tx_eq.q.id) & isr)) |
1632 | event_handle(adapter, &adapter->tx_eq); | |
1633 | ||
1634 | for_all_rx_queues(adapter, rxo, i) { | |
1635 | if ((1 << be_evt_bit_get(adapter, rxo->rx_eq.q.id) & isr)) | |
1636 | event_handle(adapter, &rxo->rx_eq); | |
1637 | } | |
c001c213 | 1638 | |
8788fdc2 | 1639 | return IRQ_HANDLED; |
6b7c5b94 SP |
1640 | } |
1641 | ||
1642 | static irqreturn_t be_msix_rx(int irq, void *dev) | |
1643 | { | |
3abcdeda SP |
1644 | struct be_rx_obj *rxo = dev; |
1645 | struct be_adapter *adapter = rxo->adapter; | |
6b7c5b94 | 1646 | |
3abcdeda | 1647 | event_handle(adapter, &rxo->rx_eq); |
6b7c5b94 SP |
1648 | |
1649 | return IRQ_HANDLED; | |
1650 | } | |
1651 | ||
5fb379ee | 1652 | static irqreturn_t be_msix_tx_mcc(int irq, void *dev) |
6b7c5b94 SP |
1653 | { |
1654 | struct be_adapter *adapter = dev; | |
1655 | ||
8788fdc2 | 1656 | event_handle(adapter, &adapter->tx_eq); |
6b7c5b94 SP |
1657 | |
1658 | return IRQ_HANDLED; | |
1659 | } | |
1660 | ||
3abcdeda | 1661 | static inline bool do_gro(struct be_adapter *adapter, struct be_rx_obj *rxo, |
6b7c5b94 SP |
1662 | struct be_eth_rx_compl *rxcp) |
1663 | { | |
1664 | int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp); | |
1665 | int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp); | |
1666 | ||
1667 | if (err) | |
3abcdeda | 1668 | rxo->stats.rxcp_err++; |
6b7c5b94 | 1669 | |
5be93b9a | 1670 | return (tcp_frame && !err) ? true : false; |
6b7c5b94 SP |
1671 | } |
1672 | ||
49b05221 | 1673 | static int be_poll_rx(struct napi_struct *napi, int budget) |
6b7c5b94 SP |
1674 | { |
1675 | struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi); | |
3abcdeda SP |
1676 | struct be_rx_obj *rxo = container_of(rx_eq, struct be_rx_obj, rx_eq); |
1677 | struct be_adapter *adapter = rxo->adapter; | |
1678 | struct be_queue_info *rx_cq = &rxo->cq; | |
6b7c5b94 SP |
1679 | struct be_eth_rx_compl *rxcp; |
1680 | u32 work_done; | |
1681 | ||
3abcdeda | 1682 | rxo->stats.rx_polls++; |
6b7c5b94 | 1683 | for (work_done = 0; work_done < budget; work_done++) { |
3abcdeda | 1684 | rxcp = be_rx_compl_get(rxo); |
6b7c5b94 SP |
1685 | if (!rxcp) |
1686 | break; | |
1687 | ||
3abcdeda SP |
1688 | if (do_gro(adapter, rxo, rxcp)) |
1689 | be_rx_compl_process_gro(adapter, rxo, rxcp); | |
6b7c5b94 | 1690 | else |
3abcdeda | 1691 | be_rx_compl_process(adapter, rxo, rxcp); |
a7a0ef31 SP |
1692 | |
1693 | be_rx_compl_reset(rxcp); | |
6b7c5b94 SP |
1694 | } |
1695 | ||
6b7c5b94 | 1696 | /* Refill the queue */ |
3abcdeda SP |
1697 | if (atomic_read(&rxo->q.used) < RX_FRAGS_REFILL_WM) |
1698 | be_post_rx_frags(rxo); | |
6b7c5b94 SP |
1699 | |
1700 | /* All consumed */ | |
1701 | if (work_done < budget) { | |
1702 | napi_complete(napi); | |
8788fdc2 | 1703 | be_cq_notify(adapter, rx_cq->id, true, work_done); |
6b7c5b94 SP |
1704 | } else { |
1705 | /* More to be consumed; continue with interrupts disabled */ | |
8788fdc2 | 1706 | be_cq_notify(adapter, rx_cq->id, false, work_done); |
6b7c5b94 SP |
1707 | } |
1708 | return work_done; | |
1709 | } | |
1710 | ||
f31e50a8 SP |
1711 | /* As TX and MCC share the same EQ check for both TX and MCC completions. |
1712 | * For TX/MCC we don't honour budget; consume everything | |
1713 | */ | |
1714 | static int be_poll_tx_mcc(struct napi_struct *napi, int budget) | |
6b7c5b94 | 1715 | { |
f31e50a8 SP |
1716 | struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi); |
1717 | struct be_adapter *adapter = | |
1718 | container_of(tx_eq, struct be_adapter, tx_eq); | |
5fb379ee SP |
1719 | struct be_queue_info *txq = &adapter->tx_obj.q; |
1720 | struct be_queue_info *tx_cq = &adapter->tx_obj.cq; | |
6b7c5b94 | 1721 | struct be_eth_tx_compl *txcp; |
f31e50a8 | 1722 | int tx_compl = 0, mcc_compl, status = 0; |
6b7c5b94 SP |
1723 | u16 end_idx; |
1724 | ||
5fb379ee | 1725 | while ((txcp = be_tx_compl_get(tx_cq))) { |
6b7c5b94 | 1726 | end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl, |
f31e50a8 | 1727 | wrb_index, txcp); |
6b7c5b94 | 1728 | be_tx_compl_process(adapter, end_idx); |
f31e50a8 | 1729 | tx_compl++; |
6b7c5b94 SP |
1730 | } |
1731 | ||
f31e50a8 SP |
1732 | mcc_compl = be_process_mcc(adapter, &status); |
1733 | ||
1734 | napi_complete(napi); | |
1735 | ||
1736 | if (mcc_compl) { | |
1737 | struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; | |
1738 | be_cq_notify(adapter, mcc_obj->cq.id, true, mcc_compl); | |
1739 | } | |
1740 | ||
1741 | if (tx_compl) { | |
1742 | be_cq_notify(adapter, adapter->tx_obj.cq.id, true, tx_compl); | |
5fb379ee SP |
1743 | |
1744 | /* As Tx wrbs have been freed up, wake up netdev queue if | |
1745 | * it was stopped due to lack of tx wrbs. | |
1746 | */ | |
1747 | if (netif_queue_stopped(adapter->netdev) && | |
6b7c5b94 | 1748 | atomic_read(&txq->used) < txq->len / 2) { |
5fb379ee SP |
1749 | netif_wake_queue(adapter->netdev); |
1750 | } | |
1751 | ||
3abcdeda SP |
1752 | tx_stats(adapter)->be_tx_events++; |
1753 | tx_stats(adapter)->be_tx_compl += tx_compl; | |
6b7c5b94 | 1754 | } |
6b7c5b94 SP |
1755 | |
1756 | return 1; | |
1757 | } | |
1758 | ||
d053de91 | 1759 | void be_detect_dump_ue(struct be_adapter *adapter) |
7c185276 AK |
1760 | { |
1761 | u32 ue_status_lo, ue_status_hi, ue_status_lo_mask, ue_status_hi_mask; | |
1762 | u32 i; | |
1763 | ||
1764 | pci_read_config_dword(adapter->pdev, | |
1765 | PCICFG_UE_STATUS_LOW, &ue_status_lo); | |
1766 | pci_read_config_dword(adapter->pdev, | |
1767 | PCICFG_UE_STATUS_HIGH, &ue_status_hi); | |
1768 | pci_read_config_dword(adapter->pdev, | |
1769 | PCICFG_UE_STATUS_LOW_MASK, &ue_status_lo_mask); | |
1770 | pci_read_config_dword(adapter->pdev, | |
1771 | PCICFG_UE_STATUS_HI_MASK, &ue_status_hi_mask); | |
1772 | ||
1773 | ue_status_lo = (ue_status_lo & (~ue_status_lo_mask)); | |
1774 | ue_status_hi = (ue_status_hi & (~ue_status_hi_mask)); | |
1775 | ||
d053de91 AK |
1776 | if (ue_status_lo || ue_status_hi) { |
1777 | adapter->ue_detected = true; | |
1778 | dev_err(&adapter->pdev->dev, "UE Detected!!\n"); | |
1779 | } | |
1780 | ||
7c185276 AK |
1781 | if (ue_status_lo) { |
1782 | for (i = 0; ue_status_lo; ue_status_lo >>= 1, i++) { | |
1783 | if (ue_status_lo & 1) | |
1784 | dev_err(&adapter->pdev->dev, | |
1785 | "UE: %s bit set\n", ue_status_low_desc[i]); | |
1786 | } | |
1787 | } | |
1788 | if (ue_status_hi) { | |
1789 | for (i = 0; ue_status_hi; ue_status_hi >>= 1, i++) { | |
1790 | if (ue_status_hi & 1) | |
1791 | dev_err(&adapter->pdev->dev, | |
1792 | "UE: %s bit set\n", ue_status_hi_desc[i]); | |
1793 | } | |
1794 | } | |
1795 | ||
1796 | } | |
1797 | ||
ea1dae11 SP |
1798 | static void be_worker(struct work_struct *work) |
1799 | { | |
1800 | struct be_adapter *adapter = | |
1801 | container_of(work, struct be_adapter, work.work); | |
3abcdeda SP |
1802 | struct be_rx_obj *rxo; |
1803 | int i; | |
ea1dae11 | 1804 | |
f203af70 SK |
1805 | /* when interrupts are not yet enabled, just reap any pending |
1806 | * mcc completions */ | |
1807 | if (!netif_running(adapter->netdev)) { | |
1808 | int mcc_compl, status = 0; | |
1809 | ||
1810 | mcc_compl = be_process_mcc(adapter, &status); | |
1811 | ||
1812 | if (mcc_compl) { | |
1813 | struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; | |
1814 | be_cq_notify(adapter, mcc_obj->cq.id, false, mcc_compl); | |
1815 | } | |
1816 | goto reschedule; | |
1817 | } | |
1818 | ||
0fc48c37 | 1819 | if (!adapter->stats_ioctl_sent) |
3abcdeda | 1820 | be_cmd_get_stats(adapter, &adapter->stats_cmd); |
ea1dae11 | 1821 | |
4097f663 | 1822 | be_tx_rate_update(adapter); |
4097f663 | 1823 | |
3abcdeda SP |
1824 | for_all_rx_queues(adapter, rxo, i) { |
1825 | be_rx_rate_update(rxo); | |
1826 | be_rx_eqd_update(adapter, rxo); | |
1827 | ||
1828 | if (rxo->rx_post_starved) { | |
1829 | rxo->rx_post_starved = false; | |
1830 | be_post_rx_frags(rxo); | |
1831 | } | |
ea1dae11 | 1832 | } |
3abcdeda | 1833 | |
d053de91 AK |
1834 | if (!adapter->ue_detected) |
1835 | be_detect_dump_ue(adapter); | |
ea1dae11 | 1836 | |
f203af70 | 1837 | reschedule: |
ea1dae11 SP |
1838 | schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000)); |
1839 | } | |
1840 | ||
8d56ff11 SP |
1841 | static void be_msix_disable(struct be_adapter *adapter) |
1842 | { | |
1843 | if (adapter->msix_enabled) { | |
1844 | pci_disable_msix(adapter->pdev); | |
1845 | adapter->msix_enabled = false; | |
1846 | } | |
1847 | } | |
1848 | ||
3abcdeda SP |
1849 | static int be_num_rxqs_get(struct be_adapter *adapter) |
1850 | { | |
1851 | if (multi_rxq && (adapter->function_caps & BE_FUNCTION_CAPS_RSS) && | |
1852 | !adapter->sriov_enabled && !(adapter->function_mode & 0x400)) { | |
1853 | return 1 + MAX_RSS_QS; /* one default non-RSS queue */ | |
1854 | } else { | |
1855 | dev_warn(&adapter->pdev->dev, | |
1856 | "No support for multiple RX queues\n"); | |
1857 | return 1; | |
1858 | } | |
1859 | } | |
1860 | ||
6b7c5b94 SP |
1861 | static void be_msix_enable(struct be_adapter *adapter) |
1862 | { | |
3abcdeda | 1863 | #define BE_MIN_MSIX_VECTORS (1 + 1) /* Rx + Tx */ |
6b7c5b94 SP |
1864 | int i, status; |
1865 | ||
3abcdeda SP |
1866 | adapter->num_rx_qs = be_num_rxqs_get(adapter); |
1867 | ||
1868 | for (i = 0; i < (adapter->num_rx_qs + 1); i++) | |
6b7c5b94 SP |
1869 | adapter->msix_entries[i].entry = i; |
1870 | ||
1871 | status = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
3abcdeda SP |
1872 | adapter->num_rx_qs + 1); |
1873 | if (status == 0) { | |
1874 | goto done; | |
1875 | } else if (status >= BE_MIN_MSIX_VECTORS) { | |
1876 | if (pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
1877 | status) == 0) { | |
1878 | adapter->num_rx_qs = status - 1; | |
1879 | dev_warn(&adapter->pdev->dev, | |
1880 | "Could alloc only %d MSIx vectors. " | |
1881 | "Using %d RX Qs\n", status, adapter->num_rx_qs); | |
1882 | goto done; | |
1883 | } | |
1884 | } | |
1885 | return; | |
1886 | done: | |
1887 | adapter->msix_enabled = true; | |
6b7c5b94 SP |
1888 | } |
1889 | ||
ba343c77 SB |
1890 | static void be_sriov_enable(struct be_adapter *adapter) |
1891 | { | |
344dbf10 | 1892 | be_check_sriov_fn_type(adapter); |
6dedec81 | 1893 | #ifdef CONFIG_PCI_IOV |
ba343c77 | 1894 | if (be_physfn(adapter) && num_vfs) { |
6dedec81 AK |
1895 | int status; |
1896 | ||
ba343c77 SB |
1897 | status = pci_enable_sriov(adapter->pdev, num_vfs); |
1898 | adapter->sriov_enabled = status ? false : true; | |
1899 | } | |
1900 | #endif | |
ba343c77 SB |
1901 | } |
1902 | ||
1903 | static void be_sriov_disable(struct be_adapter *adapter) | |
1904 | { | |
1905 | #ifdef CONFIG_PCI_IOV | |
1906 | if (adapter->sriov_enabled) { | |
1907 | pci_disable_sriov(adapter->pdev); | |
1908 | adapter->sriov_enabled = false; | |
1909 | } | |
1910 | #endif | |
1911 | } | |
1912 | ||
6b7c5b94 SP |
1913 | static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id) |
1914 | { | |
b628bde2 SP |
1915 | return adapter->msix_entries[ |
1916 | be_evt_bit_get(adapter, eq_id)].vector; | |
6b7c5b94 SP |
1917 | } |
1918 | ||
b628bde2 SP |
1919 | static int be_request_irq(struct be_adapter *adapter, |
1920 | struct be_eq_obj *eq_obj, | |
3abcdeda | 1921 | void *handler, char *desc, void *context) |
6b7c5b94 SP |
1922 | { |
1923 | struct net_device *netdev = adapter->netdev; | |
b628bde2 SP |
1924 | int vec; |
1925 | ||
1926 | sprintf(eq_obj->desc, "%s-%s", netdev->name, desc); | |
1927 | vec = be_msix_vec_get(adapter, eq_obj->q.id); | |
3abcdeda | 1928 | return request_irq(vec, handler, 0, eq_obj->desc, context); |
b628bde2 SP |
1929 | } |
1930 | ||
3abcdeda SP |
1931 | static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj, |
1932 | void *context) | |
b628bde2 SP |
1933 | { |
1934 | int vec = be_msix_vec_get(adapter, eq_obj->q.id); | |
3abcdeda | 1935 | free_irq(vec, context); |
b628bde2 | 1936 | } |
6b7c5b94 | 1937 | |
b628bde2 SP |
1938 | static int be_msix_register(struct be_adapter *adapter) |
1939 | { | |
3abcdeda SP |
1940 | struct be_rx_obj *rxo; |
1941 | int status, i; | |
1942 | char qname[10]; | |
b628bde2 | 1943 | |
3abcdeda SP |
1944 | status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx", |
1945 | adapter); | |
6b7c5b94 SP |
1946 | if (status) |
1947 | goto err; | |
1948 | ||
3abcdeda SP |
1949 | for_all_rx_queues(adapter, rxo, i) { |
1950 | sprintf(qname, "rxq%d", i); | |
1951 | status = be_request_irq(adapter, &rxo->rx_eq, be_msix_rx, | |
1952 | qname, rxo); | |
1953 | if (status) | |
1954 | goto err_msix; | |
1955 | } | |
b628bde2 | 1956 | |
6b7c5b94 | 1957 | return 0; |
b628bde2 | 1958 | |
3abcdeda SP |
1959 | err_msix: |
1960 | be_free_irq(adapter, &adapter->tx_eq, adapter); | |
1961 | ||
1962 | for (i--, rxo = &adapter->rx_obj[i]; i >= 0; i--, rxo--) | |
1963 | be_free_irq(adapter, &rxo->rx_eq, rxo); | |
1964 | ||
6b7c5b94 SP |
1965 | err: |
1966 | dev_warn(&adapter->pdev->dev, | |
1967 | "MSIX Request IRQ failed - err %d\n", status); | |
1968 | pci_disable_msix(adapter->pdev); | |
1969 | adapter->msix_enabled = false; | |
1970 | return status; | |
1971 | } | |
1972 | ||
1973 | static int be_irq_register(struct be_adapter *adapter) | |
1974 | { | |
1975 | struct net_device *netdev = adapter->netdev; | |
1976 | int status; | |
1977 | ||
1978 | if (adapter->msix_enabled) { | |
1979 | status = be_msix_register(adapter); | |
1980 | if (status == 0) | |
1981 | goto done; | |
ba343c77 SB |
1982 | /* INTx is not supported for VF */ |
1983 | if (!be_physfn(adapter)) | |
1984 | return status; | |
6b7c5b94 SP |
1985 | } |
1986 | ||
1987 | /* INTx */ | |
1988 | netdev->irq = adapter->pdev->irq; | |
1989 | status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name, | |
1990 | adapter); | |
1991 | if (status) { | |
1992 | dev_err(&adapter->pdev->dev, | |
1993 | "INTx request IRQ failed - err %d\n", status); | |
1994 | return status; | |
1995 | } | |
1996 | done: | |
1997 | adapter->isr_registered = true; | |
1998 | return 0; | |
1999 | } | |
2000 | ||
2001 | static void be_irq_unregister(struct be_adapter *adapter) | |
2002 | { | |
2003 | struct net_device *netdev = adapter->netdev; | |
3abcdeda SP |
2004 | struct be_rx_obj *rxo; |
2005 | int i; | |
6b7c5b94 SP |
2006 | |
2007 | if (!adapter->isr_registered) | |
2008 | return; | |
2009 | ||
2010 | /* INTx */ | |
2011 | if (!adapter->msix_enabled) { | |
2012 | free_irq(netdev->irq, adapter); | |
2013 | goto done; | |
2014 | } | |
2015 | ||
2016 | /* MSIx */ | |
3abcdeda SP |
2017 | be_free_irq(adapter, &adapter->tx_eq, adapter); |
2018 | ||
2019 | for_all_rx_queues(adapter, rxo, i) | |
2020 | be_free_irq(adapter, &rxo->rx_eq, rxo); | |
2021 | ||
6b7c5b94 SP |
2022 | done: |
2023 | adapter->isr_registered = false; | |
6b7c5b94 SP |
2024 | } |
2025 | ||
889cd4b2 SP |
2026 | static int be_close(struct net_device *netdev) |
2027 | { | |
2028 | struct be_adapter *adapter = netdev_priv(netdev); | |
3abcdeda | 2029 | struct be_rx_obj *rxo; |
889cd4b2 | 2030 | struct be_eq_obj *tx_eq = &adapter->tx_eq; |
3abcdeda | 2031 | int vec, i; |
889cd4b2 | 2032 | |
889cd4b2 SP |
2033 | be_async_mcc_disable(adapter); |
2034 | ||
2035 | netif_stop_queue(netdev); | |
2036 | netif_carrier_off(netdev); | |
2037 | adapter->link_up = false; | |
2038 | ||
2039 | be_intr_set(adapter, false); | |
2040 | ||
2041 | if (adapter->msix_enabled) { | |
2042 | vec = be_msix_vec_get(adapter, tx_eq->q.id); | |
2043 | synchronize_irq(vec); | |
3abcdeda SP |
2044 | |
2045 | for_all_rx_queues(adapter, rxo, i) { | |
2046 | vec = be_msix_vec_get(adapter, rxo->rx_eq.q.id); | |
2047 | synchronize_irq(vec); | |
2048 | } | |
889cd4b2 SP |
2049 | } else { |
2050 | synchronize_irq(netdev->irq); | |
2051 | } | |
2052 | be_irq_unregister(adapter); | |
2053 | ||
3abcdeda SP |
2054 | for_all_rx_queues(adapter, rxo, i) |
2055 | napi_disable(&rxo->rx_eq.napi); | |
2056 | ||
889cd4b2 SP |
2057 | napi_disable(&tx_eq->napi); |
2058 | ||
2059 | /* Wait for all pending tx completions to arrive so that | |
2060 | * all tx skbs are freed. | |
2061 | */ | |
2062 | be_tx_compl_clean(adapter); | |
2063 | ||
2064 | return 0; | |
2065 | } | |
2066 | ||
6b7c5b94 SP |
2067 | static int be_open(struct net_device *netdev) |
2068 | { | |
2069 | struct be_adapter *adapter = netdev_priv(netdev); | |
6b7c5b94 | 2070 | struct be_eq_obj *tx_eq = &adapter->tx_eq; |
3abcdeda | 2071 | struct be_rx_obj *rxo; |
a8f447bd | 2072 | bool link_up; |
3abcdeda | 2073 | int status, i; |
0388f251 SB |
2074 | u8 mac_speed; |
2075 | u16 link_speed; | |
5fb379ee | 2076 | |
3abcdeda SP |
2077 | for_all_rx_queues(adapter, rxo, i) { |
2078 | be_post_rx_frags(rxo); | |
2079 | napi_enable(&rxo->rx_eq.napi); | |
2080 | } | |
5fb379ee SP |
2081 | napi_enable(&tx_eq->napi); |
2082 | ||
2083 | be_irq_register(adapter); | |
2084 | ||
8788fdc2 | 2085 | be_intr_set(adapter, true); |
5fb379ee SP |
2086 | |
2087 | /* The evt queues are created in unarmed state; arm them */ | |
3abcdeda SP |
2088 | for_all_rx_queues(adapter, rxo, i) { |
2089 | be_eq_notify(adapter, rxo->rx_eq.q.id, true, false, 0); | |
2090 | be_cq_notify(adapter, rxo->cq.id, true, 0); | |
2091 | } | |
8788fdc2 | 2092 | be_eq_notify(adapter, tx_eq->q.id, true, false, 0); |
5fb379ee | 2093 | |
7a1e9b20 SP |
2094 | /* Now that interrupts are on we can process async mcc */ |
2095 | be_async_mcc_enable(adapter); | |
2096 | ||
0388f251 SB |
2097 | status = be_cmd_link_status_query(adapter, &link_up, &mac_speed, |
2098 | &link_speed); | |
a8f447bd | 2099 | if (status) |
889cd4b2 | 2100 | goto err; |
a8f447bd | 2101 | be_link_status_update(adapter, link_up); |
5fb379ee | 2102 | |
889cd4b2 | 2103 | if (be_physfn(adapter)) { |
1da87b7f | 2104 | status = be_vid_config(adapter, false, 0); |
889cd4b2 SP |
2105 | if (status) |
2106 | goto err; | |
4f2aa89c | 2107 | |
ba343c77 SB |
2108 | status = be_cmd_set_flow_control(adapter, |
2109 | adapter->tx_fc, adapter->rx_fc); | |
2110 | if (status) | |
889cd4b2 | 2111 | goto err; |
ba343c77 | 2112 | } |
4f2aa89c | 2113 | |
889cd4b2 SP |
2114 | return 0; |
2115 | err: | |
2116 | be_close(adapter->netdev); | |
2117 | return -EIO; | |
5fb379ee SP |
2118 | } |
2119 | ||
71d8d1b5 AK |
2120 | static int be_setup_wol(struct be_adapter *adapter, bool enable) |
2121 | { | |
2122 | struct be_dma_mem cmd; | |
2123 | int status = 0; | |
2124 | u8 mac[ETH_ALEN]; | |
2125 | ||
2126 | memset(mac, 0, ETH_ALEN); | |
2127 | ||
2128 | cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config); | |
2129 | cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma); | |
2130 | if (cmd.va == NULL) | |
2131 | return -1; | |
2132 | memset(cmd.va, 0, cmd.size); | |
2133 | ||
2134 | if (enable) { | |
2135 | status = pci_write_config_dword(adapter->pdev, | |
2136 | PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK); | |
2137 | if (status) { | |
2138 | dev_err(&adapter->pdev->dev, | |
2381a55c | 2139 | "Could not enable Wake-on-lan\n"); |
71d8d1b5 AK |
2140 | pci_free_consistent(adapter->pdev, cmd.size, cmd.va, |
2141 | cmd.dma); | |
2142 | return status; | |
2143 | } | |
2144 | status = be_cmd_enable_magic_wol(adapter, | |
2145 | adapter->netdev->dev_addr, &cmd); | |
2146 | pci_enable_wake(adapter->pdev, PCI_D3hot, 1); | |
2147 | pci_enable_wake(adapter->pdev, PCI_D3cold, 1); | |
2148 | } else { | |
2149 | status = be_cmd_enable_magic_wol(adapter, mac, &cmd); | |
2150 | pci_enable_wake(adapter->pdev, PCI_D3hot, 0); | |
2151 | pci_enable_wake(adapter->pdev, PCI_D3cold, 0); | |
2152 | } | |
2153 | ||
2154 | pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); | |
2155 | return status; | |
2156 | } | |
2157 | ||
6d87f5c3 AK |
2158 | /* |
2159 | * Generate a seed MAC address from the PF MAC Address using jhash. | |
2160 | * MAC Address for VFs are assigned incrementally starting from the seed. | |
2161 | * These addresses are programmed in the ASIC by the PF and the VF driver | |
2162 | * queries for the MAC address during its probe. | |
2163 | */ | |
2164 | static inline int be_vf_eth_addr_config(struct be_adapter *adapter) | |
2165 | { | |
2166 | u32 vf = 0; | |
3abcdeda | 2167 | int status = 0; |
6d87f5c3 AK |
2168 | u8 mac[ETH_ALEN]; |
2169 | ||
2170 | be_vf_eth_addr_generate(adapter, mac); | |
2171 | ||
2172 | for (vf = 0; vf < num_vfs; vf++) { | |
2173 | status = be_cmd_pmac_add(adapter, mac, | |
2174 | adapter->vf_cfg[vf].vf_if_handle, | |
2175 | &adapter->vf_cfg[vf].vf_pmac_id); | |
2176 | if (status) | |
2177 | dev_err(&adapter->pdev->dev, | |
2178 | "Mac address add failed for VF %d\n", vf); | |
2179 | else | |
2180 | memcpy(adapter->vf_cfg[vf].vf_mac_addr, mac, ETH_ALEN); | |
2181 | ||
2182 | mac[5] += 1; | |
2183 | } | |
2184 | return status; | |
2185 | } | |
2186 | ||
2187 | static inline void be_vf_eth_addr_rem(struct be_adapter *adapter) | |
2188 | { | |
2189 | u32 vf; | |
2190 | ||
2191 | for (vf = 0; vf < num_vfs; vf++) { | |
2192 | if (adapter->vf_cfg[vf].vf_pmac_id != BE_INVALID_PMAC_ID) | |
2193 | be_cmd_pmac_del(adapter, | |
2194 | adapter->vf_cfg[vf].vf_if_handle, | |
2195 | adapter->vf_cfg[vf].vf_pmac_id); | |
2196 | } | |
2197 | } | |
2198 | ||
5fb379ee SP |
2199 | static int be_setup(struct be_adapter *adapter) |
2200 | { | |
5fb379ee | 2201 | struct net_device *netdev = adapter->netdev; |
ba343c77 | 2202 | u32 cap_flags, en_flags, vf = 0; |
6b7c5b94 | 2203 | int status; |
ba343c77 SB |
2204 | u8 mac[ETH_ALEN]; |
2205 | ||
2206 | cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST; | |
6b7c5b94 | 2207 | |
ba343c77 SB |
2208 | if (be_physfn(adapter)) { |
2209 | cap_flags |= BE_IF_FLAGS_MCAST_PROMISCUOUS | | |
2210 | BE_IF_FLAGS_PROMISCUOUS | | |
2211 | BE_IF_FLAGS_PASS_L3L4_ERRORS; | |
2212 | en_flags |= BE_IF_FLAGS_PASS_L3L4_ERRORS; | |
3abcdeda SP |
2213 | |
2214 | if (be_multi_rxq(adapter)) { | |
2215 | cap_flags |= BE_IF_FLAGS_RSS; | |
2216 | en_flags |= BE_IF_FLAGS_RSS; | |
2217 | } | |
ba343c77 | 2218 | } |
73d540f2 SP |
2219 | |
2220 | status = be_cmd_if_create(adapter, cap_flags, en_flags, | |
2221 | netdev->dev_addr, false/* pmac_invalid */, | |
ba343c77 | 2222 | &adapter->if_handle, &adapter->pmac_id, 0); |
6b7c5b94 SP |
2223 | if (status != 0) |
2224 | goto do_none; | |
2225 | ||
ba343c77 SB |
2226 | if (be_physfn(adapter)) { |
2227 | while (vf < num_vfs) { | |
2228 | cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED | |
2229 | | BE_IF_FLAGS_BROADCAST; | |
2230 | status = be_cmd_if_create(adapter, cap_flags, en_flags, | |
64600ea5 AK |
2231 | mac, true, |
2232 | &adapter->vf_cfg[vf].vf_if_handle, | |
ba343c77 SB |
2233 | NULL, vf+1); |
2234 | if (status) { | |
2235 | dev_err(&adapter->pdev->dev, | |
2236 | "Interface Create failed for VF %d\n", vf); | |
2237 | goto if_destroy; | |
2238 | } | |
64600ea5 | 2239 | adapter->vf_cfg[vf].vf_pmac_id = BE_INVALID_PMAC_ID; |
ba343c77 | 2240 | vf++; |
84e5b9f7 | 2241 | } |
ba343c77 SB |
2242 | } else if (!be_physfn(adapter)) { |
2243 | status = be_cmd_mac_addr_query(adapter, mac, | |
2244 | MAC_ADDRESS_TYPE_NETWORK, false, adapter->if_handle); | |
2245 | if (!status) { | |
2246 | memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN); | |
2247 | memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN); | |
2248 | } | |
2249 | } | |
2250 | ||
6b7c5b94 SP |
2251 | status = be_tx_queues_create(adapter); |
2252 | if (status != 0) | |
2253 | goto if_destroy; | |
2254 | ||
2255 | status = be_rx_queues_create(adapter); | |
2256 | if (status != 0) | |
2257 | goto tx_qs_destroy; | |
2258 | ||
5fb379ee SP |
2259 | status = be_mcc_queues_create(adapter); |
2260 | if (status != 0) | |
2261 | goto rx_qs_destroy; | |
6b7c5b94 | 2262 | |
6d87f5c3 AK |
2263 | if (be_physfn(adapter)) { |
2264 | status = be_vf_eth_addr_config(adapter); | |
2265 | if (status) | |
2266 | goto mcc_q_destroy; | |
2267 | } | |
2268 | ||
0dffc83e AK |
2269 | adapter->link_speed = -1; |
2270 | ||
6b7c5b94 SP |
2271 | return 0; |
2272 | ||
6d87f5c3 AK |
2273 | mcc_q_destroy: |
2274 | if (be_physfn(adapter)) | |
2275 | be_vf_eth_addr_rem(adapter); | |
2276 | be_mcc_queues_destroy(adapter); | |
5fb379ee SP |
2277 | rx_qs_destroy: |
2278 | be_rx_queues_destroy(adapter); | |
6b7c5b94 SP |
2279 | tx_qs_destroy: |
2280 | be_tx_queues_destroy(adapter); | |
2281 | if_destroy: | |
ba343c77 | 2282 | for (vf = 0; vf < num_vfs; vf++) |
64600ea5 AK |
2283 | if (adapter->vf_cfg[vf].vf_if_handle) |
2284 | be_cmd_if_destroy(adapter, | |
2285 | adapter->vf_cfg[vf].vf_if_handle); | |
8788fdc2 | 2286 | be_cmd_if_destroy(adapter, adapter->if_handle); |
6b7c5b94 SP |
2287 | do_none: |
2288 | return status; | |
2289 | } | |
2290 | ||
5fb379ee SP |
2291 | static int be_clear(struct be_adapter *adapter) |
2292 | { | |
6d87f5c3 AK |
2293 | if (be_physfn(adapter)) |
2294 | be_vf_eth_addr_rem(adapter); | |
2295 | ||
1a8887d8 | 2296 | be_mcc_queues_destroy(adapter); |
5fb379ee SP |
2297 | be_rx_queues_destroy(adapter); |
2298 | be_tx_queues_destroy(adapter); | |
2299 | ||
8788fdc2 | 2300 | be_cmd_if_destroy(adapter, adapter->if_handle); |
5fb379ee | 2301 | |
2243e2e9 SP |
2302 | /* tell fw we're done with firing cmds */ |
2303 | be_cmd_fw_clean(adapter); | |
5fb379ee SP |
2304 | return 0; |
2305 | } | |
2306 | ||
6b7c5b94 | 2307 | |
84517482 | 2308 | #define FW_FILE_HDR_SIGN "ServerEngines Corp. " |
fa9a6fed | 2309 | static bool be_flash_redboot(struct be_adapter *adapter, |
3f0d4560 AK |
2310 | const u8 *p, u32 img_start, int image_size, |
2311 | int hdr_size) | |
fa9a6fed SB |
2312 | { |
2313 | u32 crc_offset; | |
2314 | u8 flashed_crc[4]; | |
2315 | int status; | |
3f0d4560 AK |
2316 | |
2317 | crc_offset = hdr_size + img_start + image_size - 4; | |
2318 | ||
fa9a6fed | 2319 | p += crc_offset; |
3f0d4560 AK |
2320 | |
2321 | status = be_cmd_get_flash_crc(adapter, flashed_crc, | |
f510fc64 | 2322 | (image_size - 4)); |
fa9a6fed SB |
2323 | if (status) { |
2324 | dev_err(&adapter->pdev->dev, | |
2325 | "could not get crc from flash, not flashing redboot\n"); | |
2326 | return false; | |
2327 | } | |
2328 | ||
2329 | /*update redboot only if crc does not match*/ | |
2330 | if (!memcmp(flashed_crc, p, 4)) | |
2331 | return false; | |
2332 | else | |
2333 | return true; | |
fa9a6fed SB |
2334 | } |
2335 | ||
3f0d4560 | 2336 | static int be_flash_data(struct be_adapter *adapter, |
84517482 | 2337 | const struct firmware *fw, |
3f0d4560 AK |
2338 | struct be_dma_mem *flash_cmd, int num_of_images) |
2339 | ||
84517482 | 2340 | { |
3f0d4560 AK |
2341 | int status = 0, i, filehdr_size = 0; |
2342 | u32 total_bytes = 0, flash_op; | |
84517482 AK |
2343 | int num_bytes; |
2344 | const u8 *p = fw->data; | |
2345 | struct be_cmd_write_flashrom *req = flash_cmd->va; | |
3f0d4560 | 2346 | struct flash_comp *pflashcomp; |
9fe96934 | 2347 | int num_comp; |
3f0d4560 | 2348 | |
9fe96934 | 2349 | struct flash_comp gen3_flash_types[9] = { |
3f0d4560 AK |
2350 | { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE, |
2351 | FLASH_IMAGE_MAX_SIZE_g3}, | |
2352 | { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT, | |
2353 | FLASH_REDBOOT_IMAGE_MAX_SIZE_g3}, | |
2354 | { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS, | |
2355 | FLASH_BIOS_IMAGE_MAX_SIZE_g3}, | |
2356 | { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS, | |
2357 | FLASH_BIOS_IMAGE_MAX_SIZE_g3}, | |
2358 | { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS, | |
2359 | FLASH_BIOS_IMAGE_MAX_SIZE_g3}, | |
2360 | { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP, | |
2361 | FLASH_IMAGE_MAX_SIZE_g3}, | |
2362 | { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE, | |
2363 | FLASH_IMAGE_MAX_SIZE_g3}, | |
2364 | { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP, | |
9fe96934 SB |
2365 | FLASH_IMAGE_MAX_SIZE_g3}, |
2366 | { FLASH_NCSI_START_g3, IMG_TYPE_NCSI_FW, | |
2367 | FLASH_NCSI_IMAGE_MAX_SIZE_g3} | |
3f0d4560 AK |
2368 | }; |
2369 | struct flash_comp gen2_flash_types[8] = { | |
2370 | { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE, | |
2371 | FLASH_IMAGE_MAX_SIZE_g2}, | |
2372 | { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT, | |
2373 | FLASH_REDBOOT_IMAGE_MAX_SIZE_g2}, | |
2374 | { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS, | |
2375 | FLASH_BIOS_IMAGE_MAX_SIZE_g2}, | |
2376 | { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS, | |
2377 | FLASH_BIOS_IMAGE_MAX_SIZE_g2}, | |
2378 | { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS, | |
2379 | FLASH_BIOS_IMAGE_MAX_SIZE_g2}, | |
2380 | { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP, | |
2381 | FLASH_IMAGE_MAX_SIZE_g2}, | |
2382 | { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE, | |
2383 | FLASH_IMAGE_MAX_SIZE_g2}, | |
2384 | { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP, | |
2385 | FLASH_IMAGE_MAX_SIZE_g2} | |
2386 | }; | |
2387 | ||
2388 | if (adapter->generation == BE_GEN3) { | |
2389 | pflashcomp = gen3_flash_types; | |
2390 | filehdr_size = sizeof(struct flash_file_hdr_g3); | |
9fe96934 | 2391 | num_comp = 9; |
3f0d4560 AK |
2392 | } else { |
2393 | pflashcomp = gen2_flash_types; | |
2394 | filehdr_size = sizeof(struct flash_file_hdr_g2); | |
9fe96934 | 2395 | num_comp = 8; |
84517482 | 2396 | } |
9fe96934 SB |
2397 | for (i = 0; i < num_comp; i++) { |
2398 | if ((pflashcomp[i].optype == IMG_TYPE_NCSI_FW) && | |
2399 | memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0) | |
2400 | continue; | |
3f0d4560 AK |
2401 | if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) && |
2402 | (!be_flash_redboot(adapter, fw->data, | |
2403 | pflashcomp[i].offset, pflashcomp[i].size, | |
2404 | filehdr_size))) | |
2405 | continue; | |
2406 | p = fw->data; | |
2407 | p += filehdr_size + pflashcomp[i].offset | |
2408 | + (num_of_images * sizeof(struct image_hdr)); | |
2409 | if (p + pflashcomp[i].size > fw->data + fw->size) | |
84517482 | 2410 | return -1; |
3f0d4560 AK |
2411 | total_bytes = pflashcomp[i].size; |
2412 | while (total_bytes) { | |
2413 | if (total_bytes > 32*1024) | |
2414 | num_bytes = 32*1024; | |
2415 | else | |
2416 | num_bytes = total_bytes; | |
2417 | total_bytes -= num_bytes; | |
2418 | ||
2419 | if (!total_bytes) | |
2420 | flash_op = FLASHROM_OPER_FLASH; | |
2421 | else | |
2422 | flash_op = FLASHROM_OPER_SAVE; | |
2423 | memcpy(req->params.data_buf, p, num_bytes); | |
2424 | p += num_bytes; | |
2425 | status = be_cmd_write_flashrom(adapter, flash_cmd, | |
2426 | pflashcomp[i].optype, flash_op, num_bytes); | |
2427 | if (status) { | |
2428 | dev_err(&adapter->pdev->dev, | |
2429 | "cmd to write to flash rom failed.\n"); | |
2430 | return -1; | |
2431 | } | |
2432 | yield(); | |
84517482 | 2433 | } |
84517482 | 2434 | } |
84517482 AK |
2435 | return 0; |
2436 | } | |
2437 | ||
3f0d4560 AK |
2438 | static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr) |
2439 | { | |
2440 | if (fhdr == NULL) | |
2441 | return 0; | |
2442 | if (fhdr->build[0] == '3') | |
2443 | return BE_GEN3; | |
2444 | else if (fhdr->build[0] == '2') | |
2445 | return BE_GEN2; | |
2446 | else | |
2447 | return 0; | |
2448 | } | |
2449 | ||
84517482 AK |
2450 | int be_load_fw(struct be_adapter *adapter, u8 *func) |
2451 | { | |
2452 | char fw_file[ETHTOOL_FLASH_MAX_FILENAME]; | |
2453 | const struct firmware *fw; | |
3f0d4560 AK |
2454 | struct flash_file_hdr_g2 *fhdr; |
2455 | struct flash_file_hdr_g3 *fhdr3; | |
2456 | struct image_hdr *img_hdr_ptr = NULL; | |
84517482 | 2457 | struct be_dma_mem flash_cmd; |
8b93b710 | 2458 | int status, i = 0, num_imgs = 0; |
84517482 | 2459 | const u8 *p; |
84517482 | 2460 | |
84517482 AK |
2461 | strcpy(fw_file, func); |
2462 | ||
2463 | status = request_firmware(&fw, fw_file, &adapter->pdev->dev); | |
2464 | if (status) | |
2465 | goto fw_exit; | |
2466 | ||
2467 | p = fw->data; | |
3f0d4560 | 2468 | fhdr = (struct flash_file_hdr_g2 *) p; |
84517482 AK |
2469 | dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file); |
2470 | ||
84517482 AK |
2471 | flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024; |
2472 | flash_cmd.va = pci_alloc_consistent(adapter->pdev, flash_cmd.size, | |
2473 | &flash_cmd.dma); | |
2474 | if (!flash_cmd.va) { | |
2475 | status = -ENOMEM; | |
2476 | dev_err(&adapter->pdev->dev, | |
2477 | "Memory allocation failure while flashing\n"); | |
2478 | goto fw_exit; | |
2479 | } | |
2480 | ||
3f0d4560 AK |
2481 | if ((adapter->generation == BE_GEN3) && |
2482 | (get_ufigen_type(fhdr) == BE_GEN3)) { | |
2483 | fhdr3 = (struct flash_file_hdr_g3 *) fw->data; | |
8b93b710 AK |
2484 | num_imgs = le32_to_cpu(fhdr3->num_imgs); |
2485 | for (i = 0; i < num_imgs; i++) { | |
3f0d4560 AK |
2486 | img_hdr_ptr = (struct image_hdr *) (fw->data + |
2487 | (sizeof(struct flash_file_hdr_g3) + | |
8b93b710 AK |
2488 | i * sizeof(struct image_hdr))); |
2489 | if (le32_to_cpu(img_hdr_ptr->imageid) == 1) | |
2490 | status = be_flash_data(adapter, fw, &flash_cmd, | |
2491 | num_imgs); | |
3f0d4560 AK |
2492 | } |
2493 | } else if ((adapter->generation == BE_GEN2) && | |
2494 | (get_ufigen_type(fhdr) == BE_GEN2)) { | |
2495 | status = be_flash_data(adapter, fw, &flash_cmd, 0); | |
2496 | } else { | |
2497 | dev_err(&adapter->pdev->dev, | |
2498 | "UFI and Interface are not compatible for flashing\n"); | |
2499 | status = -1; | |
84517482 AK |
2500 | } |
2501 | ||
2502 | pci_free_consistent(adapter->pdev, flash_cmd.size, flash_cmd.va, | |
2503 | flash_cmd.dma); | |
2504 | if (status) { | |
2505 | dev_err(&adapter->pdev->dev, "Firmware load error\n"); | |
2506 | goto fw_exit; | |
2507 | } | |
2508 | ||
af901ca1 | 2509 | dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n"); |
84517482 AK |
2510 | |
2511 | fw_exit: | |
2512 | release_firmware(fw); | |
2513 | return status; | |
2514 | } | |
2515 | ||
6b7c5b94 SP |
2516 | static struct net_device_ops be_netdev_ops = { |
2517 | .ndo_open = be_open, | |
2518 | .ndo_stop = be_close, | |
2519 | .ndo_start_xmit = be_xmit, | |
6b7c5b94 SP |
2520 | .ndo_set_rx_mode = be_set_multicast_list, |
2521 | .ndo_set_mac_address = be_mac_addr_set, | |
2522 | .ndo_change_mtu = be_change_mtu, | |
2523 | .ndo_validate_addr = eth_validate_addr, | |
2524 | .ndo_vlan_rx_register = be_vlan_register, | |
2525 | .ndo_vlan_rx_add_vid = be_vlan_add_vid, | |
2526 | .ndo_vlan_rx_kill_vid = be_vlan_rem_vid, | |
64600ea5 | 2527 | .ndo_set_vf_mac = be_set_vf_mac, |
1da87b7f | 2528 | .ndo_set_vf_vlan = be_set_vf_vlan, |
e1d18735 | 2529 | .ndo_set_vf_tx_rate = be_set_vf_tx_rate, |
64600ea5 | 2530 | .ndo_get_vf_config = be_get_vf_config |
6b7c5b94 SP |
2531 | }; |
2532 | ||
2533 | static void be_netdev_init(struct net_device *netdev) | |
2534 | { | |
2535 | struct be_adapter *adapter = netdev_priv(netdev); | |
3abcdeda SP |
2536 | struct be_rx_obj *rxo; |
2537 | int i; | |
6b7c5b94 SP |
2538 | |
2539 | netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO | | |
583e3f34 | 2540 | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_HW_CSUM | |
49e4b847 | 2541 | NETIF_F_GRO | NETIF_F_TSO6; |
6b7c5b94 | 2542 | |
51c59870 AK |
2543 | netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_HW_CSUM; |
2544 | ||
6b7c5b94 SP |
2545 | netdev->flags |= IFF_MULTICAST; |
2546 | ||
728a9972 AK |
2547 | adapter->rx_csum = true; |
2548 | ||
9e90c961 AK |
2549 | /* Default settings for Rx and Tx flow control */ |
2550 | adapter->rx_fc = true; | |
2551 | adapter->tx_fc = true; | |
2552 | ||
c190e3c8 AK |
2553 | netif_set_gso_max_size(netdev, 65535); |
2554 | ||
6b7c5b94 SP |
2555 | BE_SET_NETDEV_OPS(netdev, &be_netdev_ops); |
2556 | ||
2557 | SET_ETHTOOL_OPS(netdev, &be_ethtool_ops); | |
2558 | ||
3abcdeda SP |
2559 | for_all_rx_queues(adapter, rxo, i) |
2560 | netif_napi_add(netdev, &rxo->rx_eq.napi, be_poll_rx, | |
2561 | BE_NAPI_WEIGHT); | |
2562 | ||
5fb379ee | 2563 | netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc, |
6b7c5b94 SP |
2564 | BE_NAPI_WEIGHT); |
2565 | ||
6b7c5b94 SP |
2566 | netif_stop_queue(netdev); |
2567 | } | |
2568 | ||
2569 | static void be_unmap_pci_bars(struct be_adapter *adapter) | |
2570 | { | |
8788fdc2 SP |
2571 | if (adapter->csr) |
2572 | iounmap(adapter->csr); | |
2573 | if (adapter->db) | |
2574 | iounmap(adapter->db); | |
ba343c77 | 2575 | if (adapter->pcicfg && be_physfn(adapter)) |
8788fdc2 | 2576 | iounmap(adapter->pcicfg); |
6b7c5b94 SP |
2577 | } |
2578 | ||
2579 | static int be_map_pci_bars(struct be_adapter *adapter) | |
2580 | { | |
2581 | u8 __iomem *addr; | |
ba343c77 | 2582 | int pcicfg_reg, db_reg; |
6b7c5b94 | 2583 | |
ba343c77 SB |
2584 | if (be_physfn(adapter)) { |
2585 | addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2), | |
2586 | pci_resource_len(adapter->pdev, 2)); | |
2587 | if (addr == NULL) | |
2588 | return -ENOMEM; | |
2589 | adapter->csr = addr; | |
2590 | } | |
6b7c5b94 | 2591 | |
ba343c77 | 2592 | if (adapter->generation == BE_GEN2) { |
7b139c83 | 2593 | pcicfg_reg = 1; |
ba343c77 SB |
2594 | db_reg = 4; |
2595 | } else { | |
7b139c83 | 2596 | pcicfg_reg = 0; |
ba343c77 SB |
2597 | if (be_physfn(adapter)) |
2598 | db_reg = 4; | |
2599 | else | |
2600 | db_reg = 0; | |
2601 | } | |
2602 | addr = ioremap_nocache(pci_resource_start(adapter->pdev, db_reg), | |
2603 | pci_resource_len(adapter->pdev, db_reg)); | |
6b7c5b94 SP |
2604 | if (addr == NULL) |
2605 | goto pci_map_err; | |
ba343c77 SB |
2606 | adapter->db = addr; |
2607 | ||
2608 | if (be_physfn(adapter)) { | |
2609 | addr = ioremap_nocache( | |
2610 | pci_resource_start(adapter->pdev, pcicfg_reg), | |
2611 | pci_resource_len(adapter->pdev, pcicfg_reg)); | |
2612 | if (addr == NULL) | |
2613 | goto pci_map_err; | |
2614 | adapter->pcicfg = addr; | |
2615 | } else | |
2616 | adapter->pcicfg = adapter->db + SRIOV_VF_PCICFG_OFFSET; | |
6b7c5b94 SP |
2617 | |
2618 | return 0; | |
2619 | pci_map_err: | |
2620 | be_unmap_pci_bars(adapter); | |
2621 | return -ENOMEM; | |
2622 | } | |
2623 | ||
2624 | ||
2625 | static void be_ctrl_cleanup(struct be_adapter *adapter) | |
2626 | { | |
8788fdc2 | 2627 | struct be_dma_mem *mem = &adapter->mbox_mem_alloced; |
6b7c5b94 SP |
2628 | |
2629 | be_unmap_pci_bars(adapter); | |
2630 | ||
2631 | if (mem->va) | |
2632 | pci_free_consistent(adapter->pdev, mem->size, | |
2633 | mem->va, mem->dma); | |
e7b909a6 SP |
2634 | |
2635 | mem = &adapter->mc_cmd_mem; | |
2636 | if (mem->va) | |
2637 | pci_free_consistent(adapter->pdev, mem->size, | |
2638 | mem->va, mem->dma); | |
6b7c5b94 SP |
2639 | } |
2640 | ||
6b7c5b94 SP |
2641 | static int be_ctrl_init(struct be_adapter *adapter) |
2642 | { | |
8788fdc2 SP |
2643 | struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced; |
2644 | struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem; | |
e7b909a6 | 2645 | struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem; |
6b7c5b94 | 2646 | int status; |
6b7c5b94 SP |
2647 | |
2648 | status = be_map_pci_bars(adapter); | |
2649 | if (status) | |
e7b909a6 | 2650 | goto done; |
6b7c5b94 SP |
2651 | |
2652 | mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16; | |
2653 | mbox_mem_alloc->va = pci_alloc_consistent(adapter->pdev, | |
2654 | mbox_mem_alloc->size, &mbox_mem_alloc->dma); | |
2655 | if (!mbox_mem_alloc->va) { | |
e7b909a6 SP |
2656 | status = -ENOMEM; |
2657 | goto unmap_pci_bars; | |
6b7c5b94 | 2658 | } |
e7b909a6 | 2659 | |
6b7c5b94 SP |
2660 | mbox_mem_align->size = sizeof(struct be_mcc_mailbox); |
2661 | mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16); | |
2662 | mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16); | |
2663 | memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox)); | |
e7b909a6 SP |
2664 | |
2665 | mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config); | |
2666 | mc_cmd_mem->va = pci_alloc_consistent(adapter->pdev, mc_cmd_mem->size, | |
2667 | &mc_cmd_mem->dma); | |
2668 | if (mc_cmd_mem->va == NULL) { | |
2669 | status = -ENOMEM; | |
2670 | goto free_mbox; | |
2671 | } | |
2672 | memset(mc_cmd_mem->va, 0, mc_cmd_mem->size); | |
2673 | ||
8788fdc2 SP |
2674 | spin_lock_init(&adapter->mbox_lock); |
2675 | spin_lock_init(&adapter->mcc_lock); | |
2676 | spin_lock_init(&adapter->mcc_cq_lock); | |
a8f447bd | 2677 | |
dd131e76 | 2678 | init_completion(&adapter->flash_compl); |
cf588477 | 2679 | pci_save_state(adapter->pdev); |
6b7c5b94 | 2680 | return 0; |
e7b909a6 SP |
2681 | |
2682 | free_mbox: | |
2683 | pci_free_consistent(adapter->pdev, mbox_mem_alloc->size, | |
2684 | mbox_mem_alloc->va, mbox_mem_alloc->dma); | |
2685 | ||
2686 | unmap_pci_bars: | |
2687 | be_unmap_pci_bars(adapter); | |
2688 | ||
2689 | done: | |
2690 | return status; | |
6b7c5b94 SP |
2691 | } |
2692 | ||
2693 | static void be_stats_cleanup(struct be_adapter *adapter) | |
2694 | { | |
3abcdeda | 2695 | struct be_dma_mem *cmd = &adapter->stats_cmd; |
6b7c5b94 SP |
2696 | |
2697 | if (cmd->va) | |
2698 | pci_free_consistent(adapter->pdev, cmd->size, | |
2699 | cmd->va, cmd->dma); | |
2700 | } | |
2701 | ||
2702 | static int be_stats_init(struct be_adapter *adapter) | |
2703 | { | |
3abcdeda | 2704 | struct be_dma_mem *cmd = &adapter->stats_cmd; |
6b7c5b94 SP |
2705 | |
2706 | cmd->size = sizeof(struct be_cmd_req_get_stats); | |
2707 | cmd->va = pci_alloc_consistent(adapter->pdev, cmd->size, &cmd->dma); | |
2708 | if (cmd->va == NULL) | |
2709 | return -1; | |
d291b9af | 2710 | memset(cmd->va, 0, cmd->size); |
6b7c5b94 SP |
2711 | return 0; |
2712 | } | |
2713 | ||
2714 | static void __devexit be_remove(struct pci_dev *pdev) | |
2715 | { | |
2716 | struct be_adapter *adapter = pci_get_drvdata(pdev); | |
8d56ff11 | 2717 | |
6b7c5b94 SP |
2718 | if (!adapter) |
2719 | return; | |
2720 | ||
f203af70 SK |
2721 | cancel_delayed_work_sync(&adapter->work); |
2722 | ||
6b7c5b94 SP |
2723 | unregister_netdev(adapter->netdev); |
2724 | ||
5fb379ee SP |
2725 | be_clear(adapter); |
2726 | ||
6b7c5b94 SP |
2727 | be_stats_cleanup(adapter); |
2728 | ||
2729 | be_ctrl_cleanup(adapter); | |
2730 | ||
ba343c77 SB |
2731 | be_sriov_disable(adapter); |
2732 | ||
8d56ff11 | 2733 | be_msix_disable(adapter); |
6b7c5b94 SP |
2734 | |
2735 | pci_set_drvdata(pdev, NULL); | |
2736 | pci_release_regions(pdev); | |
2737 | pci_disable_device(pdev); | |
2738 | ||
2739 | free_netdev(adapter->netdev); | |
2740 | } | |
2741 | ||
2243e2e9 | 2742 | static int be_get_config(struct be_adapter *adapter) |
6b7c5b94 | 2743 | { |
6b7c5b94 | 2744 | int status; |
2243e2e9 | 2745 | u8 mac[ETH_ALEN]; |
6b7c5b94 | 2746 | |
2243e2e9 | 2747 | status = be_cmd_get_fw_ver(adapter, adapter->fw_ver); |
6b7c5b94 SP |
2748 | if (status) |
2749 | return status; | |
2750 | ||
3abcdeda SP |
2751 | status = be_cmd_query_fw_cfg(adapter, &adapter->port_num, |
2752 | &adapter->function_mode, &adapter->function_caps); | |
43a04fdc SP |
2753 | if (status) |
2754 | return status; | |
2755 | ||
2243e2e9 | 2756 | memset(mac, 0, ETH_ALEN); |
ba343c77 SB |
2757 | |
2758 | if (be_physfn(adapter)) { | |
2759 | status = be_cmd_mac_addr_query(adapter, mac, | |
2243e2e9 | 2760 | MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0); |
ca9e4988 | 2761 | |
ba343c77 SB |
2762 | if (status) |
2763 | return status; | |
ca9e4988 | 2764 | |
ba343c77 SB |
2765 | if (!is_valid_ether_addr(mac)) |
2766 | return -EADDRNOTAVAIL; | |
2767 | ||
2768 | memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN); | |
2769 | memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN); | |
2770 | } | |
6b7c5b94 | 2771 | |
3486be29 | 2772 | if (adapter->function_mode & 0x400) |
82903e4b AK |
2773 | adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4; |
2774 | else | |
2775 | adapter->max_vlans = BE_NUM_VLANS_SUPPORTED; | |
2776 | ||
2243e2e9 | 2777 | return 0; |
6b7c5b94 SP |
2778 | } |
2779 | ||
2780 | static int __devinit be_probe(struct pci_dev *pdev, | |
2781 | const struct pci_device_id *pdev_id) | |
2782 | { | |
2783 | int status = 0; | |
2784 | struct be_adapter *adapter; | |
2785 | struct net_device *netdev; | |
6b7c5b94 SP |
2786 | |
2787 | status = pci_enable_device(pdev); | |
2788 | if (status) | |
2789 | goto do_none; | |
2790 | ||
2791 | status = pci_request_regions(pdev, DRV_NAME); | |
2792 | if (status) | |
2793 | goto disable_dev; | |
2794 | pci_set_master(pdev); | |
2795 | ||
2796 | netdev = alloc_etherdev(sizeof(struct be_adapter)); | |
2797 | if (netdev == NULL) { | |
2798 | status = -ENOMEM; | |
2799 | goto rel_reg; | |
2800 | } | |
2801 | adapter = netdev_priv(netdev); | |
7b139c83 AK |
2802 | |
2803 | switch (pdev->device) { | |
2804 | case BE_DEVICE_ID1: | |
2805 | case OC_DEVICE_ID1: | |
2806 | adapter->generation = BE_GEN2; | |
2807 | break; | |
2808 | case BE_DEVICE_ID2: | |
2809 | case OC_DEVICE_ID2: | |
2810 | adapter->generation = BE_GEN3; | |
2811 | break; | |
2812 | default: | |
2813 | adapter->generation = 0; | |
2814 | } | |
2815 | ||
6b7c5b94 SP |
2816 | adapter->pdev = pdev; |
2817 | pci_set_drvdata(pdev, adapter); | |
2818 | adapter->netdev = netdev; | |
2243e2e9 | 2819 | SET_NETDEV_DEV(netdev, &pdev->dev); |
6b7c5b94 | 2820 | |
e930438c | 2821 | status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); |
6b7c5b94 SP |
2822 | if (!status) { |
2823 | netdev->features |= NETIF_F_HIGHDMA; | |
2824 | } else { | |
e930438c | 2825 | status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
6b7c5b94 SP |
2826 | if (status) { |
2827 | dev_err(&pdev->dev, "Could not set PCI DMA Mask\n"); | |
2828 | goto free_netdev; | |
2829 | } | |
2830 | } | |
2831 | ||
ba343c77 SB |
2832 | be_sriov_enable(adapter); |
2833 | ||
6b7c5b94 SP |
2834 | status = be_ctrl_init(adapter); |
2835 | if (status) | |
2836 | goto free_netdev; | |
2837 | ||
2243e2e9 | 2838 | /* sync up with fw's ready state */ |
ba343c77 SB |
2839 | if (be_physfn(adapter)) { |
2840 | status = be_cmd_POST(adapter); | |
2841 | if (status) | |
2842 | goto ctrl_clean; | |
ba343c77 | 2843 | } |
6b7c5b94 | 2844 | |
2243e2e9 SP |
2845 | /* tell fw we're ready to fire cmds */ |
2846 | status = be_cmd_fw_init(adapter); | |
6b7c5b94 | 2847 | if (status) |
2243e2e9 SP |
2848 | goto ctrl_clean; |
2849 | ||
556ae191 SB |
2850 | if (be_physfn(adapter)) { |
2851 | status = be_cmd_reset_function(adapter); | |
2852 | if (status) | |
2853 | goto ctrl_clean; | |
2854 | } | |
2855 | ||
2243e2e9 SP |
2856 | status = be_stats_init(adapter); |
2857 | if (status) | |
2858 | goto ctrl_clean; | |
2859 | ||
2860 | status = be_get_config(adapter); | |
6b7c5b94 SP |
2861 | if (status) |
2862 | goto stats_clean; | |
6b7c5b94 | 2863 | |
3abcdeda SP |
2864 | be_msix_enable(adapter); |
2865 | ||
6b7c5b94 | 2866 | INIT_DELAYED_WORK(&adapter->work, be_worker); |
6b7c5b94 | 2867 | |
5fb379ee SP |
2868 | status = be_setup(adapter); |
2869 | if (status) | |
3abcdeda | 2870 | goto msix_disable; |
2243e2e9 | 2871 | |
3abcdeda | 2872 | be_netdev_init(netdev); |
6b7c5b94 SP |
2873 | status = register_netdev(netdev); |
2874 | if (status != 0) | |
5fb379ee | 2875 | goto unsetup; |
63a76944 | 2876 | netif_carrier_off(netdev); |
6b7c5b94 | 2877 | |
c4ca2374 | 2878 | dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num); |
f203af70 | 2879 | schedule_delayed_work(&adapter->work, msecs_to_jiffies(100)); |
6b7c5b94 SP |
2880 | return 0; |
2881 | ||
5fb379ee SP |
2882 | unsetup: |
2883 | be_clear(adapter); | |
3abcdeda SP |
2884 | msix_disable: |
2885 | be_msix_disable(adapter); | |
6b7c5b94 SP |
2886 | stats_clean: |
2887 | be_stats_cleanup(adapter); | |
2888 | ctrl_clean: | |
2889 | be_ctrl_cleanup(adapter); | |
2890 | free_netdev: | |
ba343c77 | 2891 | be_sriov_disable(adapter); |
6b7c5b94 | 2892 | free_netdev(adapter->netdev); |
8d56ff11 | 2893 | pci_set_drvdata(pdev, NULL); |
6b7c5b94 SP |
2894 | rel_reg: |
2895 | pci_release_regions(pdev); | |
2896 | disable_dev: | |
2897 | pci_disable_device(pdev); | |
2898 | do_none: | |
c4ca2374 | 2899 | dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev)); |
6b7c5b94 SP |
2900 | return status; |
2901 | } | |
2902 | ||
2903 | static int be_suspend(struct pci_dev *pdev, pm_message_t state) | |
2904 | { | |
2905 | struct be_adapter *adapter = pci_get_drvdata(pdev); | |
2906 | struct net_device *netdev = adapter->netdev; | |
2907 | ||
71d8d1b5 AK |
2908 | if (adapter->wol) |
2909 | be_setup_wol(adapter, true); | |
2910 | ||
6b7c5b94 SP |
2911 | netif_device_detach(netdev); |
2912 | if (netif_running(netdev)) { | |
2913 | rtnl_lock(); | |
2914 | be_close(netdev); | |
2915 | rtnl_unlock(); | |
2916 | } | |
9e90c961 | 2917 | be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc); |
9b0365f1 | 2918 | be_clear(adapter); |
6b7c5b94 SP |
2919 | |
2920 | pci_save_state(pdev); | |
2921 | pci_disable_device(pdev); | |
2922 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
2923 | return 0; | |
2924 | } | |
2925 | ||
2926 | static int be_resume(struct pci_dev *pdev) | |
2927 | { | |
2928 | int status = 0; | |
2929 | struct be_adapter *adapter = pci_get_drvdata(pdev); | |
2930 | struct net_device *netdev = adapter->netdev; | |
2931 | ||
2932 | netif_device_detach(netdev); | |
2933 | ||
2934 | status = pci_enable_device(pdev); | |
2935 | if (status) | |
2936 | return status; | |
2937 | ||
2938 | pci_set_power_state(pdev, 0); | |
2939 | pci_restore_state(pdev); | |
2940 | ||
2243e2e9 SP |
2941 | /* tell fw we're ready to fire cmds */ |
2942 | status = be_cmd_fw_init(adapter); | |
2943 | if (status) | |
2944 | return status; | |
2945 | ||
9b0365f1 | 2946 | be_setup(adapter); |
6b7c5b94 SP |
2947 | if (netif_running(netdev)) { |
2948 | rtnl_lock(); | |
2949 | be_open(netdev); | |
2950 | rtnl_unlock(); | |
2951 | } | |
2952 | netif_device_attach(netdev); | |
71d8d1b5 AK |
2953 | |
2954 | if (adapter->wol) | |
2955 | be_setup_wol(adapter, false); | |
6b7c5b94 SP |
2956 | return 0; |
2957 | } | |
2958 | ||
82456b03 SP |
2959 | /* |
2960 | * An FLR will stop BE from DMAing any data. | |
2961 | */ | |
2962 | static void be_shutdown(struct pci_dev *pdev) | |
2963 | { | |
2964 | struct be_adapter *adapter = pci_get_drvdata(pdev); | |
2965 | struct net_device *netdev = adapter->netdev; | |
2966 | ||
2967 | netif_device_detach(netdev); | |
2968 | ||
2969 | be_cmd_reset_function(adapter); | |
2970 | ||
2971 | if (adapter->wol) | |
2972 | be_setup_wol(adapter, true); | |
2973 | ||
2974 | pci_disable_device(pdev); | |
82456b03 SP |
2975 | } |
2976 | ||
cf588477 SP |
2977 | static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev, |
2978 | pci_channel_state_t state) | |
2979 | { | |
2980 | struct be_adapter *adapter = pci_get_drvdata(pdev); | |
2981 | struct net_device *netdev = adapter->netdev; | |
2982 | ||
2983 | dev_err(&adapter->pdev->dev, "EEH error detected\n"); | |
2984 | ||
2985 | adapter->eeh_err = true; | |
2986 | ||
2987 | netif_device_detach(netdev); | |
2988 | ||
2989 | if (netif_running(netdev)) { | |
2990 | rtnl_lock(); | |
2991 | be_close(netdev); | |
2992 | rtnl_unlock(); | |
2993 | } | |
2994 | be_clear(adapter); | |
2995 | ||
2996 | if (state == pci_channel_io_perm_failure) | |
2997 | return PCI_ERS_RESULT_DISCONNECT; | |
2998 | ||
2999 | pci_disable_device(pdev); | |
3000 | ||
3001 | return PCI_ERS_RESULT_NEED_RESET; | |
3002 | } | |
3003 | ||
3004 | static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev) | |
3005 | { | |
3006 | struct be_adapter *adapter = pci_get_drvdata(pdev); | |
3007 | int status; | |
3008 | ||
3009 | dev_info(&adapter->pdev->dev, "EEH reset\n"); | |
3010 | adapter->eeh_err = false; | |
3011 | ||
3012 | status = pci_enable_device(pdev); | |
3013 | if (status) | |
3014 | return PCI_ERS_RESULT_DISCONNECT; | |
3015 | ||
3016 | pci_set_master(pdev); | |
3017 | pci_set_power_state(pdev, 0); | |
3018 | pci_restore_state(pdev); | |
3019 | ||
3020 | /* Check if card is ok and fw is ready */ | |
3021 | status = be_cmd_POST(adapter); | |
3022 | if (status) | |
3023 | return PCI_ERS_RESULT_DISCONNECT; | |
3024 | ||
3025 | return PCI_ERS_RESULT_RECOVERED; | |
3026 | } | |
3027 | ||
3028 | static void be_eeh_resume(struct pci_dev *pdev) | |
3029 | { | |
3030 | int status = 0; | |
3031 | struct be_adapter *adapter = pci_get_drvdata(pdev); | |
3032 | struct net_device *netdev = adapter->netdev; | |
3033 | ||
3034 | dev_info(&adapter->pdev->dev, "EEH resume\n"); | |
3035 | ||
3036 | pci_save_state(pdev); | |
3037 | ||
3038 | /* tell fw we're ready to fire cmds */ | |
3039 | status = be_cmd_fw_init(adapter); | |
3040 | if (status) | |
3041 | goto err; | |
3042 | ||
3043 | status = be_setup(adapter); | |
3044 | if (status) | |
3045 | goto err; | |
3046 | ||
3047 | if (netif_running(netdev)) { | |
3048 | status = be_open(netdev); | |
3049 | if (status) | |
3050 | goto err; | |
3051 | } | |
3052 | netif_device_attach(netdev); | |
3053 | return; | |
3054 | err: | |
3055 | dev_err(&adapter->pdev->dev, "EEH resume failed\n"); | |
cf588477 SP |
3056 | } |
3057 | ||
3058 | static struct pci_error_handlers be_eeh_handlers = { | |
3059 | .error_detected = be_eeh_err_detected, | |
3060 | .slot_reset = be_eeh_reset, | |
3061 | .resume = be_eeh_resume, | |
3062 | }; | |
3063 | ||
6b7c5b94 SP |
3064 | static struct pci_driver be_driver = { |
3065 | .name = DRV_NAME, | |
3066 | .id_table = be_dev_ids, | |
3067 | .probe = be_probe, | |
3068 | .remove = be_remove, | |
3069 | .suspend = be_suspend, | |
cf588477 | 3070 | .resume = be_resume, |
82456b03 | 3071 | .shutdown = be_shutdown, |
cf588477 | 3072 | .err_handler = &be_eeh_handlers |
6b7c5b94 SP |
3073 | }; |
3074 | ||
3075 | static int __init be_init_module(void) | |
3076 | { | |
8e95a202 JP |
3077 | if (rx_frag_size != 8192 && rx_frag_size != 4096 && |
3078 | rx_frag_size != 2048) { | |
6b7c5b94 SP |
3079 | printk(KERN_WARNING DRV_NAME |
3080 | " : Module param rx_frag_size must be 2048/4096/8192." | |
3081 | " Using 2048\n"); | |
3082 | rx_frag_size = 2048; | |
3083 | } | |
6b7c5b94 | 3084 | |
ba343c77 SB |
3085 | if (num_vfs > 32) { |
3086 | printk(KERN_WARNING DRV_NAME | |
3087 | " : Module param num_vfs must not be greater than 32." | |
3088 | "Using 32\n"); | |
3089 | num_vfs = 32; | |
3090 | } | |
3091 | ||
6b7c5b94 SP |
3092 | return pci_register_driver(&be_driver); |
3093 | } | |
3094 | module_init(be_init_module); | |
3095 | ||
3096 | static void __exit be_exit_module(void) | |
3097 | { | |
3098 | pci_unregister_driver(&be_driver); | |
3099 | } | |
3100 | module_exit(be_exit_module); |