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de0c62db DK |
1 | /* bnx2x_ethtool.c: Broadcom Everest network driver. |
2 | * | |
3 | * Copyright (c) 2007-2010 Broadcom Corporation | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> | |
10 | * Written by: Eliezer Tamir | |
11 | * Based on code from Michael Chan's bnx2 driver | |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
13 | * Slowpath and fastpath rework by Vladislav Zolotarov | |
14 | * Statistics and Link management by Yitchak Gertner | |
15 | * | |
16 | */ | |
17 | #include <linux/ethtool.h> | |
18 | #include <linux/netdevice.h> | |
19 | #include <linux/types.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/crc32.h> | |
22 | ||
23 | ||
24 | #include "bnx2x.h" | |
25 | #include "bnx2x_cmn.h" | |
26 | #include "bnx2x_dump.h" | |
27 | ||
de0c62db DK |
28 | static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
29 | { | |
30 | struct bnx2x *bp = netdev_priv(dev); | |
a22f0788 YR |
31 | int cfg_idx = bnx2x_get_link_cfg_idx(bp); |
32 | /* Dual Media boards present all available port types */ | |
33 | cmd->supported = bp->port.supported[cfg_idx] | | |
34 | (bp->port.supported[cfg_idx ^ 1] & | |
35 | (SUPPORTED_TP | SUPPORTED_FIBRE)); | |
36 | cmd->advertising = bp->port.advertising[cfg_idx]; | |
de0c62db DK |
37 | |
38 | if ((bp->state == BNX2X_STATE_OPEN) && | |
39 | !(bp->flags & MF_FUNC_DIS) && | |
40 | (bp->link_vars.link_up)) { | |
41 | cmd->speed = bp->link_vars.line_speed; | |
42 | cmd->duplex = bp->link_vars.duplex; | |
de0c62db | 43 | } else { |
f2e0899f | 44 | |
a22f0788 YR |
45 | cmd->speed = bp->link_params.req_line_speed[cfg_idx]; |
46 | cmd->duplex = bp->link_params.req_duplex[cfg_idx]; | |
de0c62db | 47 | } |
f2e0899f DK |
48 | if (IS_MF(bp)) { |
49 | u16 vn_max_rate = ((bp->mf_config[BP_VN(bp)] & | |
50 | FUNC_MF_CFG_MAX_BW_MASK) >> FUNC_MF_CFG_MAX_BW_SHIFT) * | |
51 | 100; | |
52 | ||
53 | if (vn_max_rate < cmd->speed) | |
54 | cmd->speed = vn_max_rate; | |
55 | } | |
de0c62db | 56 | |
a22f0788 YR |
57 | if (bp->port.supported[cfg_idx] & SUPPORTED_TP) |
58 | cmd->port = PORT_TP; | |
59 | else if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE) | |
60 | cmd->port = PORT_FIBRE; | |
61 | else | |
62 | BNX2X_ERR("XGXS PHY Failure detected\n"); | |
63 | ||
de0c62db DK |
64 | cmd->phy_address = bp->mdio.prtad; |
65 | cmd->transceiver = XCVR_INTERNAL; | |
66 | ||
a22f0788 | 67 | if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) |
de0c62db DK |
68 | cmd->autoneg = AUTONEG_ENABLE; |
69 | else | |
70 | cmd->autoneg = AUTONEG_DISABLE; | |
71 | ||
72 | cmd->maxtxpkt = 0; | |
73 | cmd->maxrxpkt = 0; | |
74 | ||
75 | DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n" | |
76 | DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n" | |
77 | DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n" | |
78 | DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n", | |
79 | cmd->cmd, cmd->supported, cmd->advertising, cmd->speed, | |
80 | cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, | |
81 | cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); | |
82 | ||
83 | return 0; | |
84 | } | |
85 | ||
86 | static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
87 | { | |
88 | struct bnx2x *bp = netdev_priv(dev); | |
a22f0788 | 89 | u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; |
de0c62db | 90 | |
fb3bff17 | 91 | if (IS_MF(bp)) |
de0c62db DK |
92 | return 0; |
93 | ||
94 | DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n" | |
95 | DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n" | |
96 | DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n" | |
97 | DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n", | |
98 | cmd->cmd, cmd->supported, cmd->advertising, cmd->speed, | |
99 | cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, | |
100 | cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); | |
101 | ||
a22f0788 YR |
102 | cfg_idx = bnx2x_get_link_cfg_idx(bp); |
103 | old_multi_phy_config = bp->link_params.multi_phy_config; | |
104 | switch (cmd->port) { | |
105 | case PORT_TP: | |
106 | if (bp->port.supported[cfg_idx] & SUPPORTED_TP) | |
107 | break; /* no port change */ | |
108 | ||
109 | if (!(bp->port.supported[0] & SUPPORTED_TP || | |
110 | bp->port.supported[1] & SUPPORTED_TP)) { | |
111 | DP(NETIF_MSG_LINK, "Unsupported port type\n"); | |
112 | return -EINVAL; | |
113 | } | |
114 | bp->link_params.multi_phy_config &= | |
115 | ~PORT_HW_CFG_PHY_SELECTION_MASK; | |
116 | if (bp->link_params.multi_phy_config & | |
117 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) | |
118 | bp->link_params.multi_phy_config |= | |
119 | PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; | |
120 | else | |
121 | bp->link_params.multi_phy_config |= | |
122 | PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; | |
123 | break; | |
124 | case PORT_FIBRE: | |
125 | if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE) | |
126 | break; /* no port change */ | |
127 | ||
128 | if (!(bp->port.supported[0] & SUPPORTED_FIBRE || | |
129 | bp->port.supported[1] & SUPPORTED_FIBRE)) { | |
130 | DP(NETIF_MSG_LINK, "Unsupported port type\n"); | |
131 | return -EINVAL; | |
132 | } | |
133 | bp->link_params.multi_phy_config &= | |
134 | ~PORT_HW_CFG_PHY_SELECTION_MASK; | |
135 | if (bp->link_params.multi_phy_config & | |
136 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) | |
137 | bp->link_params.multi_phy_config |= | |
138 | PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; | |
139 | else | |
140 | bp->link_params.multi_phy_config |= | |
141 | PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; | |
142 | break; | |
143 | default: | |
144 | DP(NETIF_MSG_LINK, "Unsupported port type\n"); | |
145 | return -EINVAL; | |
146 | } | |
147 | /* Save new config in case command complete successuly */ | |
148 | new_multi_phy_config = bp->link_params.multi_phy_config; | |
149 | /* Get the new cfg_idx */ | |
150 | cfg_idx = bnx2x_get_link_cfg_idx(bp); | |
151 | /* Restore old config in case command failed */ | |
152 | bp->link_params.multi_phy_config = old_multi_phy_config; | |
153 | DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx); | |
154 | ||
de0c62db | 155 | if (cmd->autoneg == AUTONEG_ENABLE) { |
a22f0788 | 156 | if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { |
de0c62db DK |
157 | DP(NETIF_MSG_LINK, "Autoneg not supported\n"); |
158 | return -EINVAL; | |
159 | } | |
160 | ||
161 | /* advertise the requested speed and duplex if supported */ | |
a22f0788 | 162 | cmd->advertising &= bp->port.supported[cfg_idx]; |
de0c62db | 163 | |
a22f0788 YR |
164 | bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; |
165 | bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL; | |
166 | bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg | | |
de0c62db DK |
167 | cmd->advertising); |
168 | ||
169 | } else { /* forced speed */ | |
170 | /* advertise the requested speed and duplex if supported */ | |
a22f0788 YR |
171 | u32 speed = cmd->speed; |
172 | speed |= (cmd->speed_hi << 16); | |
173 | switch (speed) { | |
de0c62db DK |
174 | case SPEED_10: |
175 | if (cmd->duplex == DUPLEX_FULL) { | |
a22f0788 | 176 | if (!(bp->port.supported[cfg_idx] & |
de0c62db DK |
177 | SUPPORTED_10baseT_Full)) { |
178 | DP(NETIF_MSG_LINK, | |
179 | "10M full not supported\n"); | |
180 | return -EINVAL; | |
181 | } | |
182 | ||
183 | advertising = (ADVERTISED_10baseT_Full | | |
184 | ADVERTISED_TP); | |
185 | } else { | |
a22f0788 | 186 | if (!(bp->port.supported[cfg_idx] & |
de0c62db DK |
187 | SUPPORTED_10baseT_Half)) { |
188 | DP(NETIF_MSG_LINK, | |
189 | "10M half not supported\n"); | |
190 | return -EINVAL; | |
191 | } | |
192 | ||
193 | advertising = (ADVERTISED_10baseT_Half | | |
194 | ADVERTISED_TP); | |
195 | } | |
196 | break; | |
197 | ||
198 | case SPEED_100: | |
199 | if (cmd->duplex == DUPLEX_FULL) { | |
a22f0788 | 200 | if (!(bp->port.supported[cfg_idx] & |
de0c62db DK |
201 | SUPPORTED_100baseT_Full)) { |
202 | DP(NETIF_MSG_LINK, | |
203 | "100M full not supported\n"); | |
204 | return -EINVAL; | |
205 | } | |
206 | ||
207 | advertising = (ADVERTISED_100baseT_Full | | |
208 | ADVERTISED_TP); | |
209 | } else { | |
a22f0788 | 210 | if (!(bp->port.supported[cfg_idx] & |
de0c62db DK |
211 | SUPPORTED_100baseT_Half)) { |
212 | DP(NETIF_MSG_LINK, | |
213 | "100M half not supported\n"); | |
214 | return -EINVAL; | |
215 | } | |
216 | ||
217 | advertising = (ADVERTISED_100baseT_Half | | |
218 | ADVERTISED_TP); | |
219 | } | |
220 | break; | |
221 | ||
222 | case SPEED_1000: | |
223 | if (cmd->duplex != DUPLEX_FULL) { | |
224 | DP(NETIF_MSG_LINK, "1G half not supported\n"); | |
225 | return -EINVAL; | |
226 | } | |
227 | ||
a22f0788 YR |
228 | if (!(bp->port.supported[cfg_idx] & |
229 | SUPPORTED_1000baseT_Full)) { | |
de0c62db DK |
230 | DP(NETIF_MSG_LINK, "1G full not supported\n"); |
231 | return -EINVAL; | |
232 | } | |
233 | ||
234 | advertising = (ADVERTISED_1000baseT_Full | | |
235 | ADVERTISED_TP); | |
236 | break; | |
237 | ||
238 | case SPEED_2500: | |
239 | if (cmd->duplex != DUPLEX_FULL) { | |
240 | DP(NETIF_MSG_LINK, | |
241 | "2.5G half not supported\n"); | |
242 | return -EINVAL; | |
243 | } | |
244 | ||
a22f0788 YR |
245 | if (!(bp->port.supported[cfg_idx] |
246 | & SUPPORTED_2500baseX_Full)) { | |
de0c62db DK |
247 | DP(NETIF_MSG_LINK, |
248 | "2.5G full not supported\n"); | |
249 | return -EINVAL; | |
250 | } | |
251 | ||
252 | advertising = (ADVERTISED_2500baseX_Full | | |
253 | ADVERTISED_TP); | |
254 | break; | |
255 | ||
256 | case SPEED_10000: | |
257 | if (cmd->duplex != DUPLEX_FULL) { | |
258 | DP(NETIF_MSG_LINK, "10G half not supported\n"); | |
259 | return -EINVAL; | |
260 | } | |
261 | ||
a22f0788 YR |
262 | if (!(bp->port.supported[cfg_idx] |
263 | & SUPPORTED_10000baseT_Full)) { | |
de0c62db DK |
264 | DP(NETIF_MSG_LINK, "10G full not supported\n"); |
265 | return -EINVAL; | |
266 | } | |
267 | ||
268 | advertising = (ADVERTISED_10000baseT_Full | | |
269 | ADVERTISED_FIBRE); | |
270 | break; | |
271 | ||
272 | default: | |
a22f0788 | 273 | DP(NETIF_MSG_LINK, "Unsupported speed %d\n", speed); |
de0c62db DK |
274 | return -EINVAL; |
275 | } | |
276 | ||
a22f0788 YR |
277 | bp->link_params.req_line_speed[cfg_idx] = speed; |
278 | bp->link_params.req_duplex[cfg_idx] = cmd->duplex; | |
279 | bp->port.advertising[cfg_idx] = advertising; | |
de0c62db DK |
280 | } |
281 | ||
282 | DP(NETIF_MSG_LINK, "req_line_speed %d\n" | |
283 | DP_LEVEL " req_duplex %d advertising 0x%x\n", | |
a22f0788 YR |
284 | bp->link_params.req_line_speed[cfg_idx], |
285 | bp->link_params.req_duplex[cfg_idx], | |
286 | bp->port.advertising[cfg_idx]); | |
de0c62db | 287 | |
a22f0788 YR |
288 | /* Set new config */ |
289 | bp->link_params.multi_phy_config = new_multi_phy_config; | |
de0c62db DK |
290 | if (netif_running(dev)) { |
291 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
292 | bnx2x_link_set(bp); | |
293 | } | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
298 | #define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE) | |
299 | #define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE) | |
f2e0899f | 300 | #define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE) |
de0c62db DK |
301 | |
302 | static int bnx2x_get_regs_len(struct net_device *dev) | |
303 | { | |
304 | struct bnx2x *bp = netdev_priv(dev); | |
305 | int regdump_len = 0; | |
306 | int i; | |
307 | ||
308 | if (CHIP_IS_E1(bp)) { | |
309 | for (i = 0; i < REGS_COUNT; i++) | |
310 | if (IS_E1_ONLINE(reg_addrs[i].info)) | |
311 | regdump_len += reg_addrs[i].size; | |
312 | ||
313 | for (i = 0; i < WREGS_COUNT_E1; i++) | |
314 | if (IS_E1_ONLINE(wreg_addrs_e1[i].info)) | |
315 | regdump_len += wreg_addrs_e1[i].size * | |
316 | (1 + wreg_addrs_e1[i].read_regs_count); | |
317 | ||
f2e0899f | 318 | } else if (CHIP_IS_E1H(bp)) { |
de0c62db DK |
319 | for (i = 0; i < REGS_COUNT; i++) |
320 | if (IS_E1H_ONLINE(reg_addrs[i].info)) | |
321 | regdump_len += reg_addrs[i].size; | |
322 | ||
323 | for (i = 0; i < WREGS_COUNT_E1H; i++) | |
324 | if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info)) | |
325 | regdump_len += wreg_addrs_e1h[i].size * | |
326 | (1 + wreg_addrs_e1h[i].read_regs_count); | |
f2e0899f DK |
327 | } else if (CHIP_IS_E2(bp)) { |
328 | for (i = 0; i < REGS_COUNT; i++) | |
329 | if (IS_E2_ONLINE(reg_addrs[i].info)) | |
330 | regdump_len += reg_addrs[i].size; | |
331 | ||
332 | for (i = 0; i < WREGS_COUNT_E2; i++) | |
333 | if (IS_E2_ONLINE(wreg_addrs_e2[i].info)) | |
334 | regdump_len += wreg_addrs_e2[i].size * | |
335 | (1 + wreg_addrs_e2[i].read_regs_count); | |
de0c62db DK |
336 | } |
337 | regdump_len *= 4; | |
338 | regdump_len += sizeof(struct dump_hdr); | |
339 | ||
340 | return regdump_len; | |
341 | } | |
342 | ||
f2e0899f DK |
343 | static inline void bnx2x_read_pages_regs_e2(struct bnx2x *bp, u32 *p) |
344 | { | |
345 | u32 i, j, k, n; | |
346 | ||
347 | for (i = 0; i < PAGE_MODE_VALUES_E2; i++) { | |
348 | for (j = 0; j < PAGE_WRITE_REGS_E2; j++) { | |
349 | REG_WR(bp, page_write_regs_e2[j], page_vals_e2[i]); | |
350 | for (k = 0; k < PAGE_READ_REGS_E2; k++) | |
351 | if (IS_E2_ONLINE(page_read_regs_e2[k].info)) | |
352 | for (n = 0; n < | |
353 | page_read_regs_e2[k].size; n++) | |
354 | *p++ = REG_RD(bp, | |
355 | page_read_regs_e2[k].addr + n*4); | |
356 | } | |
357 | } | |
358 | } | |
359 | ||
de0c62db DK |
360 | static void bnx2x_get_regs(struct net_device *dev, |
361 | struct ethtool_regs *regs, void *_p) | |
362 | { | |
363 | u32 *p = _p, i, j; | |
364 | struct bnx2x *bp = netdev_priv(dev); | |
365 | struct dump_hdr dump_hdr = {0}; | |
366 | ||
367 | regs->version = 0; | |
368 | memset(p, 0, regs->len); | |
369 | ||
370 | if (!netif_running(bp->dev)) | |
371 | return; | |
372 | ||
373 | dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1; | |
374 | dump_hdr.dump_sign = dump_sign_all; | |
375 | dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR); | |
376 | dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR); | |
377 | dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR); | |
378 | dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR); | |
f2e0899f DK |
379 | |
380 | if (CHIP_IS_E1(bp)) | |
381 | dump_hdr.info = RI_E1_ONLINE; | |
382 | else if (CHIP_IS_E1H(bp)) | |
383 | dump_hdr.info = RI_E1H_ONLINE; | |
384 | else if (CHIP_IS_E2(bp)) | |
385 | dump_hdr.info = RI_E2_ONLINE | | |
386 | (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP); | |
de0c62db DK |
387 | |
388 | memcpy(p, &dump_hdr, sizeof(struct dump_hdr)); | |
389 | p += dump_hdr.hdr_size + 1; | |
390 | ||
391 | if (CHIP_IS_E1(bp)) { | |
392 | for (i = 0; i < REGS_COUNT; i++) | |
393 | if (IS_E1_ONLINE(reg_addrs[i].info)) | |
394 | for (j = 0; j < reg_addrs[i].size; j++) | |
395 | *p++ = REG_RD(bp, | |
396 | reg_addrs[i].addr + j*4); | |
397 | ||
f2e0899f | 398 | } else if (CHIP_IS_E1H(bp)) { |
de0c62db DK |
399 | for (i = 0; i < REGS_COUNT; i++) |
400 | if (IS_E1H_ONLINE(reg_addrs[i].info)) | |
401 | for (j = 0; j < reg_addrs[i].size; j++) | |
402 | *p++ = REG_RD(bp, | |
403 | reg_addrs[i].addr + j*4); | |
f2e0899f DK |
404 | |
405 | } else if (CHIP_IS_E2(bp)) { | |
406 | for (i = 0; i < REGS_COUNT; i++) | |
407 | if (IS_E2_ONLINE(reg_addrs[i].info)) | |
408 | for (j = 0; j < reg_addrs[i].size; j++) | |
409 | *p++ = REG_RD(bp, | |
410 | reg_addrs[i].addr + j*4); | |
411 | ||
412 | bnx2x_read_pages_regs_e2(bp, p); | |
de0c62db DK |
413 | } |
414 | } | |
415 | ||
f2e0899f | 416 | #define PHY_FW_VER_LEN 20 |
de0c62db DK |
417 | |
418 | static void bnx2x_get_drvinfo(struct net_device *dev, | |
419 | struct ethtool_drvinfo *info) | |
420 | { | |
421 | struct bnx2x *bp = netdev_priv(dev); | |
422 | u8 phy_fw_ver[PHY_FW_VER_LEN]; | |
423 | ||
424 | strcpy(info->driver, DRV_MODULE_NAME); | |
425 | strcpy(info->version, DRV_MODULE_VERSION); | |
426 | ||
427 | phy_fw_ver[0] = '\0'; | |
428 | if (bp->port.pmf) { | |
429 | bnx2x_acquire_phy_lock(bp); | |
430 | bnx2x_get_ext_phy_fw_version(&bp->link_params, | |
431 | (bp->state != BNX2X_STATE_CLOSED), | |
432 | phy_fw_ver, PHY_FW_VER_LEN); | |
433 | bnx2x_release_phy_lock(bp); | |
434 | } | |
435 | ||
436 | strncpy(info->fw_version, bp->fw_ver, 32); | |
437 | snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver), | |
438 | "bc %d.%d.%d%s%s", | |
439 | (bp->common.bc_ver & 0xff0000) >> 16, | |
440 | (bp->common.bc_ver & 0xff00) >> 8, | |
441 | (bp->common.bc_ver & 0xff), | |
442 | ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver); | |
443 | strcpy(info->bus_info, pci_name(bp->pdev)); | |
444 | info->n_stats = BNX2X_NUM_STATS; | |
445 | info->testinfo_len = BNX2X_NUM_TESTS; | |
446 | info->eedump_len = bp->common.flash_size; | |
447 | info->regdump_len = bnx2x_get_regs_len(dev); | |
448 | } | |
449 | ||
450 | static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
451 | { | |
452 | struct bnx2x *bp = netdev_priv(dev); | |
453 | ||
454 | if (bp->flags & NO_WOL_FLAG) { | |
455 | wol->supported = 0; | |
456 | wol->wolopts = 0; | |
457 | } else { | |
458 | wol->supported = WAKE_MAGIC; | |
459 | if (bp->wol) | |
460 | wol->wolopts = WAKE_MAGIC; | |
461 | else | |
462 | wol->wolopts = 0; | |
463 | } | |
464 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
465 | } | |
466 | ||
467 | static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
468 | { | |
469 | struct bnx2x *bp = netdev_priv(dev); | |
470 | ||
471 | if (wol->wolopts & ~WAKE_MAGIC) | |
472 | return -EINVAL; | |
473 | ||
474 | if (wol->wolopts & WAKE_MAGIC) { | |
475 | if (bp->flags & NO_WOL_FLAG) | |
476 | return -EINVAL; | |
477 | ||
478 | bp->wol = 1; | |
479 | } else | |
480 | bp->wol = 0; | |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
485 | static u32 bnx2x_get_msglevel(struct net_device *dev) | |
486 | { | |
487 | struct bnx2x *bp = netdev_priv(dev); | |
488 | ||
489 | return bp->msg_enable; | |
490 | } | |
491 | ||
492 | static void bnx2x_set_msglevel(struct net_device *dev, u32 level) | |
493 | { | |
494 | struct bnx2x *bp = netdev_priv(dev); | |
495 | ||
496 | if (capable(CAP_NET_ADMIN)) | |
497 | bp->msg_enable = level; | |
498 | } | |
499 | ||
500 | static int bnx2x_nway_reset(struct net_device *dev) | |
501 | { | |
502 | struct bnx2x *bp = netdev_priv(dev); | |
503 | ||
504 | if (!bp->port.pmf) | |
505 | return 0; | |
506 | ||
507 | if (netif_running(dev)) { | |
508 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
509 | bnx2x_link_set(bp); | |
510 | } | |
511 | ||
512 | return 0; | |
513 | } | |
514 | ||
515 | static u32 bnx2x_get_link(struct net_device *dev) | |
516 | { | |
517 | struct bnx2x *bp = netdev_priv(dev); | |
518 | ||
f2e0899f | 519 | if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) |
de0c62db DK |
520 | return 0; |
521 | ||
522 | return bp->link_vars.link_up; | |
523 | } | |
524 | ||
525 | static int bnx2x_get_eeprom_len(struct net_device *dev) | |
526 | { | |
527 | struct bnx2x *bp = netdev_priv(dev); | |
528 | ||
529 | return bp->common.flash_size; | |
530 | } | |
531 | ||
532 | static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) | |
533 | { | |
534 | int port = BP_PORT(bp); | |
535 | int count, i; | |
536 | u32 val = 0; | |
537 | ||
538 | /* adjust timeout for emulation/FPGA */ | |
539 | count = NVRAM_TIMEOUT_COUNT; | |
540 | if (CHIP_REV_IS_SLOW(bp)) | |
541 | count *= 100; | |
542 | ||
543 | /* request access to nvram interface */ | |
544 | REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, | |
545 | (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); | |
546 | ||
547 | for (i = 0; i < count*10; i++) { | |
548 | val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); | |
549 | if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) | |
550 | break; | |
551 | ||
552 | udelay(5); | |
553 | } | |
554 | ||
555 | if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { | |
556 | DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n"); | |
557 | return -EBUSY; | |
558 | } | |
559 | ||
560 | return 0; | |
561 | } | |
562 | ||
563 | static int bnx2x_release_nvram_lock(struct bnx2x *bp) | |
564 | { | |
565 | int port = BP_PORT(bp); | |
566 | int count, i; | |
567 | u32 val = 0; | |
568 | ||
569 | /* adjust timeout for emulation/FPGA */ | |
570 | count = NVRAM_TIMEOUT_COUNT; | |
571 | if (CHIP_REV_IS_SLOW(bp)) | |
572 | count *= 100; | |
573 | ||
574 | /* relinquish nvram interface */ | |
575 | REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, | |
576 | (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); | |
577 | ||
578 | for (i = 0; i < count*10; i++) { | |
579 | val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); | |
580 | if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) | |
581 | break; | |
582 | ||
583 | udelay(5); | |
584 | } | |
585 | ||
586 | if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { | |
587 | DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n"); | |
588 | return -EBUSY; | |
589 | } | |
590 | ||
591 | return 0; | |
592 | } | |
593 | ||
594 | static void bnx2x_enable_nvram_access(struct bnx2x *bp) | |
595 | { | |
596 | u32 val; | |
597 | ||
598 | val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); | |
599 | ||
600 | /* enable both bits, even on read */ | |
601 | REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, | |
602 | (val | MCPR_NVM_ACCESS_ENABLE_EN | | |
603 | MCPR_NVM_ACCESS_ENABLE_WR_EN)); | |
604 | } | |
605 | ||
606 | static void bnx2x_disable_nvram_access(struct bnx2x *bp) | |
607 | { | |
608 | u32 val; | |
609 | ||
610 | val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); | |
611 | ||
612 | /* disable both bits, even after read */ | |
613 | REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, | |
614 | (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | | |
615 | MCPR_NVM_ACCESS_ENABLE_WR_EN))); | |
616 | } | |
617 | ||
618 | static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, | |
619 | u32 cmd_flags) | |
620 | { | |
621 | int count, i, rc; | |
622 | u32 val; | |
623 | ||
624 | /* build the command word */ | |
625 | cmd_flags |= MCPR_NVM_COMMAND_DOIT; | |
626 | ||
627 | /* need to clear DONE bit separately */ | |
628 | REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); | |
629 | ||
630 | /* address of the NVRAM to read from */ | |
631 | REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, | |
632 | (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); | |
633 | ||
634 | /* issue a read command */ | |
635 | REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); | |
636 | ||
637 | /* adjust timeout for emulation/FPGA */ | |
638 | count = NVRAM_TIMEOUT_COUNT; | |
639 | if (CHIP_REV_IS_SLOW(bp)) | |
640 | count *= 100; | |
641 | ||
642 | /* wait for completion */ | |
643 | *ret_val = 0; | |
644 | rc = -EBUSY; | |
645 | for (i = 0; i < count; i++) { | |
646 | udelay(5); | |
647 | val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); | |
648 | ||
649 | if (val & MCPR_NVM_COMMAND_DONE) { | |
650 | val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); | |
651 | /* we read nvram data in cpu order | |
652 | * but ethtool sees it as an array of bytes | |
653 | * converting to big-endian will do the work */ | |
654 | *ret_val = cpu_to_be32(val); | |
655 | rc = 0; | |
656 | break; | |
657 | } | |
658 | } | |
659 | ||
660 | return rc; | |
661 | } | |
662 | ||
663 | static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, | |
664 | int buf_size) | |
665 | { | |
666 | int rc; | |
667 | u32 cmd_flags; | |
668 | __be32 val; | |
669 | ||
670 | if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { | |
671 | DP(BNX2X_MSG_NVM, | |
672 | "Invalid parameter: offset 0x%x buf_size 0x%x\n", | |
673 | offset, buf_size); | |
674 | return -EINVAL; | |
675 | } | |
676 | ||
677 | if (offset + buf_size > bp->common.flash_size) { | |
678 | DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +" | |
679 | " buf_size (0x%x) > flash_size (0x%x)\n", | |
680 | offset, buf_size, bp->common.flash_size); | |
681 | return -EINVAL; | |
682 | } | |
683 | ||
684 | /* request access to nvram interface */ | |
685 | rc = bnx2x_acquire_nvram_lock(bp); | |
686 | if (rc) | |
687 | return rc; | |
688 | ||
689 | /* enable access to nvram interface */ | |
690 | bnx2x_enable_nvram_access(bp); | |
691 | ||
692 | /* read the first word(s) */ | |
693 | cmd_flags = MCPR_NVM_COMMAND_FIRST; | |
694 | while ((buf_size > sizeof(u32)) && (rc == 0)) { | |
695 | rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); | |
696 | memcpy(ret_buf, &val, 4); | |
697 | ||
698 | /* advance to the next dword */ | |
699 | offset += sizeof(u32); | |
700 | ret_buf += sizeof(u32); | |
701 | buf_size -= sizeof(u32); | |
702 | cmd_flags = 0; | |
703 | } | |
704 | ||
705 | if (rc == 0) { | |
706 | cmd_flags |= MCPR_NVM_COMMAND_LAST; | |
707 | rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); | |
708 | memcpy(ret_buf, &val, 4); | |
709 | } | |
710 | ||
711 | /* disable access to nvram interface */ | |
712 | bnx2x_disable_nvram_access(bp); | |
713 | bnx2x_release_nvram_lock(bp); | |
714 | ||
715 | return rc; | |
716 | } | |
717 | ||
718 | static int bnx2x_get_eeprom(struct net_device *dev, | |
719 | struct ethtool_eeprom *eeprom, u8 *eebuf) | |
720 | { | |
721 | struct bnx2x *bp = netdev_priv(dev); | |
722 | int rc; | |
723 | ||
724 | if (!netif_running(dev)) | |
725 | return -EAGAIN; | |
726 | ||
727 | DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" | |
728 | DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", | |
729 | eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, | |
730 | eeprom->len, eeprom->len); | |
731 | ||
732 | /* parameters already validated in ethtool_get_eeprom */ | |
733 | ||
734 | rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); | |
735 | ||
736 | return rc; | |
737 | } | |
738 | ||
739 | static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, | |
740 | u32 cmd_flags) | |
741 | { | |
742 | int count, i, rc; | |
743 | ||
744 | /* build the command word */ | |
745 | cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; | |
746 | ||
747 | /* need to clear DONE bit separately */ | |
748 | REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); | |
749 | ||
750 | /* write the data */ | |
751 | REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); | |
752 | ||
753 | /* address of the NVRAM to write to */ | |
754 | REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, | |
755 | (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); | |
756 | ||
757 | /* issue the write command */ | |
758 | REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); | |
759 | ||
760 | /* adjust timeout for emulation/FPGA */ | |
761 | count = NVRAM_TIMEOUT_COUNT; | |
762 | if (CHIP_REV_IS_SLOW(bp)) | |
763 | count *= 100; | |
764 | ||
765 | /* wait for completion */ | |
766 | rc = -EBUSY; | |
767 | for (i = 0; i < count; i++) { | |
768 | udelay(5); | |
769 | val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); | |
770 | if (val & MCPR_NVM_COMMAND_DONE) { | |
771 | rc = 0; | |
772 | break; | |
773 | } | |
774 | } | |
775 | ||
776 | return rc; | |
777 | } | |
778 | ||
779 | #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) | |
780 | ||
781 | static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, | |
782 | int buf_size) | |
783 | { | |
784 | int rc; | |
785 | u32 cmd_flags; | |
786 | u32 align_offset; | |
787 | __be32 val; | |
788 | ||
789 | if (offset + buf_size > bp->common.flash_size) { | |
790 | DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +" | |
791 | " buf_size (0x%x) > flash_size (0x%x)\n", | |
792 | offset, buf_size, bp->common.flash_size); | |
793 | return -EINVAL; | |
794 | } | |
795 | ||
796 | /* request access to nvram interface */ | |
797 | rc = bnx2x_acquire_nvram_lock(bp); | |
798 | if (rc) | |
799 | return rc; | |
800 | ||
801 | /* enable access to nvram interface */ | |
802 | bnx2x_enable_nvram_access(bp); | |
803 | ||
804 | cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); | |
805 | align_offset = (offset & ~0x03); | |
806 | rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags); | |
807 | ||
808 | if (rc == 0) { | |
809 | val &= ~(0xff << BYTE_OFFSET(offset)); | |
810 | val |= (*data_buf << BYTE_OFFSET(offset)); | |
811 | ||
812 | /* nvram data is returned as an array of bytes | |
813 | * convert it back to cpu order */ | |
814 | val = be32_to_cpu(val); | |
815 | ||
816 | rc = bnx2x_nvram_write_dword(bp, align_offset, val, | |
817 | cmd_flags); | |
818 | } | |
819 | ||
820 | /* disable access to nvram interface */ | |
821 | bnx2x_disable_nvram_access(bp); | |
822 | bnx2x_release_nvram_lock(bp); | |
823 | ||
824 | return rc; | |
825 | } | |
826 | ||
827 | static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, | |
828 | int buf_size) | |
829 | { | |
830 | int rc; | |
831 | u32 cmd_flags; | |
832 | u32 val; | |
833 | u32 written_so_far; | |
834 | ||
835 | if (buf_size == 1) /* ethtool */ | |
836 | return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); | |
837 | ||
838 | if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { | |
839 | DP(BNX2X_MSG_NVM, | |
840 | "Invalid parameter: offset 0x%x buf_size 0x%x\n", | |
841 | offset, buf_size); | |
842 | return -EINVAL; | |
843 | } | |
844 | ||
845 | if (offset + buf_size > bp->common.flash_size) { | |
846 | DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +" | |
847 | " buf_size (0x%x) > flash_size (0x%x)\n", | |
848 | offset, buf_size, bp->common.flash_size); | |
849 | return -EINVAL; | |
850 | } | |
851 | ||
852 | /* request access to nvram interface */ | |
853 | rc = bnx2x_acquire_nvram_lock(bp); | |
854 | if (rc) | |
855 | return rc; | |
856 | ||
857 | /* enable access to nvram interface */ | |
858 | bnx2x_enable_nvram_access(bp); | |
859 | ||
860 | written_so_far = 0; | |
861 | cmd_flags = MCPR_NVM_COMMAND_FIRST; | |
862 | while ((written_so_far < buf_size) && (rc == 0)) { | |
863 | if (written_so_far == (buf_size - sizeof(u32))) | |
864 | cmd_flags |= MCPR_NVM_COMMAND_LAST; | |
865 | else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0) | |
866 | cmd_flags |= MCPR_NVM_COMMAND_LAST; | |
867 | else if ((offset % NVRAM_PAGE_SIZE) == 0) | |
868 | cmd_flags |= MCPR_NVM_COMMAND_FIRST; | |
869 | ||
870 | memcpy(&val, data_buf, 4); | |
871 | ||
872 | rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); | |
873 | ||
874 | /* advance to the next dword */ | |
875 | offset += sizeof(u32); | |
876 | data_buf += sizeof(u32); | |
877 | written_so_far += sizeof(u32); | |
878 | cmd_flags = 0; | |
879 | } | |
880 | ||
881 | /* disable access to nvram interface */ | |
882 | bnx2x_disable_nvram_access(bp); | |
883 | bnx2x_release_nvram_lock(bp); | |
884 | ||
885 | return rc; | |
886 | } | |
887 | ||
888 | static int bnx2x_set_eeprom(struct net_device *dev, | |
889 | struct ethtool_eeprom *eeprom, u8 *eebuf) | |
890 | { | |
891 | struct bnx2x *bp = netdev_priv(dev); | |
892 | int port = BP_PORT(bp); | |
893 | int rc = 0; | |
e10bc84d | 894 | u32 ext_phy_config; |
de0c62db DK |
895 | if (!netif_running(dev)) |
896 | return -EAGAIN; | |
897 | ||
898 | DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" | |
899 | DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", | |
900 | eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, | |
901 | eeprom->len, eeprom->len); | |
902 | ||
903 | /* parameters already validated in ethtool_set_eeprom */ | |
904 | ||
905 | /* PHY eeprom can be accessed only by the PMF */ | |
906 | if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && | |
907 | !bp->port.pmf) | |
908 | return -EINVAL; | |
909 | ||
e10bc84d YR |
910 | ext_phy_config = |
911 | SHMEM_RD(bp, | |
912 | dev_info.port_hw_config[port].external_phy_config); | |
913 | ||
de0c62db DK |
914 | if (eeprom->magic == 0x50485950) { |
915 | /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ | |
916 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
917 | ||
918 | bnx2x_acquire_phy_lock(bp); | |
919 | rc |= bnx2x_link_reset(&bp->link_params, | |
920 | &bp->link_vars, 0); | |
e10bc84d | 921 | if (XGXS_EXT_PHY_TYPE(ext_phy_config) == |
de0c62db DK |
922 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) |
923 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, | |
924 | MISC_REGISTERS_GPIO_HIGH, port); | |
925 | bnx2x_release_phy_lock(bp); | |
926 | bnx2x_link_report(bp); | |
927 | ||
928 | } else if (eeprom->magic == 0x50485952) { | |
929 | /* 'PHYR' (0x50485952): re-init link after FW upgrade */ | |
930 | if (bp->state == BNX2X_STATE_OPEN) { | |
931 | bnx2x_acquire_phy_lock(bp); | |
932 | rc |= bnx2x_link_reset(&bp->link_params, | |
933 | &bp->link_vars, 1); | |
934 | ||
935 | rc |= bnx2x_phy_init(&bp->link_params, | |
936 | &bp->link_vars); | |
937 | bnx2x_release_phy_lock(bp); | |
938 | bnx2x_calc_fc_adv(bp); | |
939 | } | |
940 | } else if (eeprom->magic == 0x53985943) { | |
941 | /* 'PHYC' (0x53985943): PHY FW upgrade completed */ | |
e10bc84d | 942 | if (XGXS_EXT_PHY_TYPE(ext_phy_config) == |
de0c62db | 943 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { |
de0c62db DK |
944 | |
945 | /* DSP Remove Download Mode */ | |
946 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, | |
947 | MISC_REGISTERS_GPIO_LOW, port); | |
948 | ||
949 | bnx2x_acquire_phy_lock(bp); | |
950 | ||
e10bc84d YR |
951 | bnx2x_sfx7101_sp_sw_reset(bp, |
952 | &bp->link_params.phy[EXT_PHY1]); | |
de0c62db DK |
953 | |
954 | /* wait 0.5 sec to allow it to run */ | |
955 | msleep(500); | |
956 | bnx2x_ext_phy_hw_reset(bp, port); | |
957 | msleep(500); | |
958 | bnx2x_release_phy_lock(bp); | |
959 | } | |
960 | } else | |
961 | rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); | |
962 | ||
963 | return rc; | |
964 | } | |
f85582f8 | 965 | |
de0c62db DK |
966 | static int bnx2x_get_coalesce(struct net_device *dev, |
967 | struct ethtool_coalesce *coal) | |
968 | { | |
969 | struct bnx2x *bp = netdev_priv(dev); | |
970 | ||
971 | memset(coal, 0, sizeof(struct ethtool_coalesce)); | |
972 | ||
973 | coal->rx_coalesce_usecs = bp->rx_ticks; | |
974 | coal->tx_coalesce_usecs = bp->tx_ticks; | |
975 | ||
976 | return 0; | |
977 | } | |
978 | ||
979 | static int bnx2x_set_coalesce(struct net_device *dev, | |
980 | struct ethtool_coalesce *coal) | |
981 | { | |
982 | struct bnx2x *bp = netdev_priv(dev); | |
983 | ||
984 | bp->rx_ticks = (u16)coal->rx_coalesce_usecs; | |
985 | if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) | |
986 | bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; | |
987 | ||
988 | bp->tx_ticks = (u16)coal->tx_coalesce_usecs; | |
989 | if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) | |
990 | bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; | |
991 | ||
992 | if (netif_running(dev)) | |
993 | bnx2x_update_coalesce(bp); | |
994 | ||
995 | return 0; | |
996 | } | |
997 | ||
998 | static void bnx2x_get_ringparam(struct net_device *dev, | |
999 | struct ethtool_ringparam *ering) | |
1000 | { | |
1001 | struct bnx2x *bp = netdev_priv(dev); | |
1002 | ||
1003 | ering->rx_max_pending = MAX_RX_AVAIL; | |
1004 | ering->rx_mini_max_pending = 0; | |
1005 | ering->rx_jumbo_max_pending = 0; | |
1006 | ||
25141580 DK |
1007 | if (bp->rx_ring_size) |
1008 | ering->rx_pending = bp->rx_ring_size; | |
1009 | else | |
1010 | if (bp->state == BNX2X_STATE_OPEN && bp->num_queues) | |
1011 | ering->rx_pending = MAX_RX_AVAIL/bp->num_queues; | |
1012 | else | |
1013 | ering->rx_pending = MAX_RX_AVAIL; | |
1014 | ||
de0c62db DK |
1015 | ering->rx_mini_pending = 0; |
1016 | ering->rx_jumbo_pending = 0; | |
1017 | ||
1018 | ering->tx_max_pending = MAX_TX_AVAIL; | |
1019 | ering->tx_pending = bp->tx_ring_size; | |
1020 | } | |
1021 | ||
1022 | static int bnx2x_set_ringparam(struct net_device *dev, | |
1023 | struct ethtool_ringparam *ering) | |
1024 | { | |
1025 | struct bnx2x *bp = netdev_priv(dev); | |
1026 | int rc = 0; | |
1027 | ||
1028 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { | |
1029 | printk(KERN_ERR "Handling parity error recovery. Try again later\n"); | |
1030 | return -EAGAIN; | |
1031 | } | |
1032 | ||
1033 | if ((ering->rx_pending > MAX_RX_AVAIL) || | |
25141580 | 1034 | (ering->rx_pending < MIN_RX_AVAIL) || |
de0c62db DK |
1035 | (ering->tx_pending > MAX_TX_AVAIL) || |
1036 | (ering->tx_pending <= MAX_SKB_FRAGS + 4)) | |
1037 | return -EINVAL; | |
1038 | ||
1039 | bp->rx_ring_size = ering->rx_pending; | |
1040 | bp->tx_ring_size = ering->tx_pending; | |
1041 | ||
1042 | if (netif_running(dev)) { | |
1043 | bnx2x_nic_unload(bp, UNLOAD_NORMAL); | |
1044 | rc = bnx2x_nic_load(bp, LOAD_NORMAL); | |
1045 | } | |
1046 | ||
1047 | return rc; | |
1048 | } | |
1049 | ||
1050 | static void bnx2x_get_pauseparam(struct net_device *dev, | |
1051 | struct ethtool_pauseparam *epause) | |
1052 | { | |
1053 | struct bnx2x *bp = netdev_priv(dev); | |
a22f0788 YR |
1054 | int cfg_idx = bnx2x_get_link_cfg_idx(bp); |
1055 | epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == | |
1056 | BNX2X_FLOW_CTRL_AUTO); | |
de0c62db DK |
1057 | |
1058 | epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) == | |
1059 | BNX2X_FLOW_CTRL_RX); | |
1060 | epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) == | |
1061 | BNX2X_FLOW_CTRL_TX); | |
1062 | ||
1063 | DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n" | |
1064 | DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n", | |
1065 | epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); | |
1066 | } | |
1067 | ||
1068 | static int bnx2x_set_pauseparam(struct net_device *dev, | |
1069 | struct ethtool_pauseparam *epause) | |
1070 | { | |
1071 | struct bnx2x *bp = netdev_priv(dev); | |
a22f0788 | 1072 | u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); |
fb3bff17 | 1073 | if (IS_MF(bp)) |
de0c62db DK |
1074 | return 0; |
1075 | ||
1076 | DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n" | |
1077 | DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n", | |
1078 | epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); | |
1079 | ||
a22f0788 | 1080 | bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; |
de0c62db DK |
1081 | |
1082 | if (epause->rx_pause) | |
a22f0788 | 1083 | bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; |
de0c62db DK |
1084 | |
1085 | if (epause->tx_pause) | |
a22f0788 | 1086 | bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; |
de0c62db | 1087 | |
a22f0788 YR |
1088 | if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) |
1089 | bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; | |
de0c62db DK |
1090 | |
1091 | if (epause->autoneg) { | |
a22f0788 | 1092 | if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { |
de0c62db DK |
1093 | DP(NETIF_MSG_LINK, "autoneg not supported\n"); |
1094 | return -EINVAL; | |
1095 | } | |
1096 | ||
a22f0788 YR |
1097 | if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { |
1098 | bp->link_params.req_flow_ctrl[cfg_idx] = | |
1099 | BNX2X_FLOW_CTRL_AUTO; | |
1100 | } | |
de0c62db DK |
1101 | } |
1102 | ||
1103 | DP(NETIF_MSG_LINK, | |
a22f0788 | 1104 | "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); |
de0c62db DK |
1105 | |
1106 | if (netif_running(dev)) { | |
1107 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
1108 | bnx2x_link_set(bp); | |
1109 | } | |
1110 | ||
1111 | return 0; | |
1112 | } | |
1113 | ||
1114 | static int bnx2x_set_flags(struct net_device *dev, u32 data) | |
1115 | { | |
1116 | struct bnx2x *bp = netdev_priv(dev); | |
1117 | int changed = 0; | |
1118 | int rc = 0; | |
1119 | ||
de0c62db DK |
1120 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
1121 | printk(KERN_ERR "Handling parity error recovery. Try again later\n"); | |
1122 | return -EAGAIN; | |
1123 | } | |
1124 | ||
9bcc0893 | 1125 | if (!(data & ETH_FLAG_RXVLAN)) |
ec37a48d | 1126 | return -EINVAL; |
9bcc0893 HZ |
1127 | |
1128 | if ((data & ETH_FLAG_LRO) && bp->rx_csum && bp->disable_tpa) | |
1129 | return -EINVAL; | |
1130 | ||
1131 | rc = ethtool_op_set_flags(dev, data, ETH_FLAG_LRO | ETH_FLAG_RXVLAN | | |
1132 | ETH_FLAG_TXVLAN | ETH_FLAG_RXHASH); | |
1133 | if (rc) | |
1134 | return rc; | |
1135 | ||
de0c62db DK |
1136 | /* TPA requires Rx CSUM offloading */ |
1137 | if ((data & ETH_FLAG_LRO) && bp->rx_csum) { | |
9bcc0893 HZ |
1138 | if (!(bp->flags & TPA_ENABLE_FLAG)) { |
1139 | bp->flags |= TPA_ENABLE_FLAG; | |
1140 | changed = 1; | |
1141 | } | |
1142 | } else if (bp->flags & TPA_ENABLE_FLAG) { | |
de0c62db DK |
1143 | dev->features &= ~NETIF_F_LRO; |
1144 | bp->flags &= ~TPA_ENABLE_FLAG; | |
1145 | changed = 1; | |
1146 | } | |
1147 | ||
de0c62db DK |
1148 | if (changed && netif_running(dev)) { |
1149 | bnx2x_nic_unload(bp, UNLOAD_NORMAL); | |
1150 | rc = bnx2x_nic_load(bp, LOAD_NORMAL); | |
1151 | } | |
1152 | ||
1153 | return rc; | |
1154 | } | |
1155 | ||
1156 | static u32 bnx2x_get_rx_csum(struct net_device *dev) | |
1157 | { | |
1158 | struct bnx2x *bp = netdev_priv(dev); | |
1159 | ||
1160 | return bp->rx_csum; | |
1161 | } | |
1162 | ||
1163 | static int bnx2x_set_rx_csum(struct net_device *dev, u32 data) | |
1164 | { | |
1165 | struct bnx2x *bp = netdev_priv(dev); | |
1166 | int rc = 0; | |
1167 | ||
1168 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { | |
1169 | printk(KERN_ERR "Handling parity error recovery. Try again later\n"); | |
1170 | return -EAGAIN; | |
1171 | } | |
1172 | ||
1173 | bp->rx_csum = data; | |
1174 | ||
1175 | /* Disable TPA, when Rx CSUM is disabled. Otherwise all | |
1176 | TPA'ed packets will be discarded due to wrong TCP CSUM */ | |
1177 | if (!data) { | |
1178 | u32 flags = ethtool_op_get_flags(dev); | |
1179 | ||
1180 | rc = bnx2x_set_flags(dev, (flags & ~ETH_FLAG_LRO)); | |
1181 | } | |
1182 | ||
1183 | return rc; | |
1184 | } | |
1185 | ||
1186 | static int bnx2x_set_tso(struct net_device *dev, u32 data) | |
1187 | { | |
1188 | if (data) { | |
1189 | dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN); | |
1190 | dev->features |= NETIF_F_TSO6; | |
1191 | } else { | |
1192 | dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN); | |
1193 | dev->features &= ~NETIF_F_TSO6; | |
1194 | } | |
1195 | ||
1196 | return 0; | |
1197 | } | |
1198 | ||
1199 | static const struct { | |
1200 | char string[ETH_GSTRING_LEN]; | |
1201 | } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = { | |
1202 | { "register_test (offline)" }, | |
1203 | { "memory_test (offline)" }, | |
1204 | { "loopback_test (offline)" }, | |
1205 | { "nvram_test (online)" }, | |
1206 | { "interrupt_test (online)" }, | |
1207 | { "link_test (online)" }, | |
1208 | { "idle check (online)" } | |
1209 | }; | |
1210 | ||
1211 | static int bnx2x_test_registers(struct bnx2x *bp) | |
1212 | { | |
1213 | int idx, i, rc = -ENODEV; | |
1214 | u32 wr_val = 0; | |
1215 | int port = BP_PORT(bp); | |
1216 | static const struct { | |
1217 | u32 offset0; | |
1218 | u32 offset1; | |
1219 | u32 mask; | |
1220 | } reg_tbl[] = { | |
1221 | /* 0 */ { BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, | |
1222 | { DORQ_REG_DB_ADDR0, 4, 0xffffffff }, | |
1223 | { HC_REG_AGG_INT_0, 4, 0x000003ff }, | |
1224 | { PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, | |
1225 | { PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, | |
1226 | { PRS_REG_CID_PORT_0, 4, 0x00ffffff }, | |
1227 | { PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, | |
1228 | { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, | |
1229 | { PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, | |
1230 | { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, | |
1231 | /* 10 */ { PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, | |
1232 | { QM_REG_CONNNUM_0, 4, 0x000fffff }, | |
1233 | { TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, | |
1234 | { SRC_REG_KEYRSS0_0, 40, 0xffffffff }, | |
1235 | { SRC_REG_KEYRSS0_7, 40, 0xffffffff }, | |
1236 | { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, | |
1237 | { XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, | |
1238 | { XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, | |
1239 | { NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, | |
1240 | { NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, | |
1241 | /* 20 */ { NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, | |
1242 | { NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, | |
1243 | { NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, | |
1244 | { NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, | |
1245 | { NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, | |
1246 | { NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, | |
1247 | { NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, | |
1248 | { NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, | |
1249 | { NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, | |
1250 | { NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, | |
1251 | /* 30 */ { NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, | |
1252 | { NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, | |
1253 | { NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, | |
1254 | { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 }, | |
1255 | { NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, | |
1256 | { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, | |
1257 | { NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, | |
1258 | ||
1259 | { 0xffffffff, 0, 0x00000000 } | |
1260 | }; | |
1261 | ||
1262 | if (!netif_running(bp->dev)) | |
1263 | return rc; | |
1264 | ||
1265 | /* Repeat the test twice: | |
1266 | First by writing 0x00000000, second by writing 0xffffffff */ | |
1267 | for (idx = 0; idx < 2; idx++) { | |
1268 | ||
1269 | switch (idx) { | |
1270 | case 0: | |
1271 | wr_val = 0; | |
1272 | break; | |
1273 | case 1: | |
1274 | wr_val = 0xffffffff; | |
1275 | break; | |
1276 | } | |
1277 | ||
1278 | for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { | |
1279 | u32 offset, mask, save_val, val; | |
f2e0899f DK |
1280 | if (CHIP_IS_E2(bp) && |
1281 | reg_tbl[i].offset0 == HC_REG_AGG_INT_0) | |
1282 | continue; | |
de0c62db DK |
1283 | |
1284 | offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; | |
1285 | mask = reg_tbl[i].mask; | |
1286 | ||
1287 | save_val = REG_RD(bp, offset); | |
1288 | ||
1289 | REG_WR(bp, offset, (wr_val & mask)); | |
f85582f8 | 1290 | |
de0c62db DK |
1291 | val = REG_RD(bp, offset); |
1292 | ||
1293 | /* Restore the original register's value */ | |
1294 | REG_WR(bp, offset, save_val); | |
1295 | ||
1296 | /* verify value is as expected */ | |
1297 | if ((val & mask) != (wr_val & mask)) { | |
1298 | DP(NETIF_MSG_PROBE, | |
1299 | "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", | |
1300 | offset, val, wr_val, mask); | |
1301 | goto test_reg_exit; | |
1302 | } | |
1303 | } | |
1304 | } | |
1305 | ||
1306 | rc = 0; | |
1307 | ||
1308 | test_reg_exit: | |
1309 | return rc; | |
1310 | } | |
1311 | ||
1312 | static int bnx2x_test_memory(struct bnx2x *bp) | |
1313 | { | |
1314 | int i, j, rc = -ENODEV; | |
1315 | u32 val; | |
1316 | static const struct { | |
1317 | u32 offset; | |
1318 | int size; | |
1319 | } mem_tbl[] = { | |
1320 | { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, | |
1321 | { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, | |
1322 | { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, | |
1323 | { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, | |
1324 | { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, | |
1325 | { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, | |
1326 | { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, | |
1327 | ||
1328 | { 0xffffffff, 0 } | |
1329 | }; | |
1330 | static const struct { | |
1331 | char *name; | |
1332 | u32 offset; | |
1333 | u32 e1_mask; | |
1334 | u32 e1h_mask; | |
f2e0899f | 1335 | u32 e2_mask; |
de0c62db | 1336 | } prty_tbl[] = { |
f2e0899f DK |
1337 | { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0x3ffc0, 0, 0 }, |
1338 | { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0x2, 0x2, 0 }, | |
1339 | { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0, 0, 0 }, | |
1340 | { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0x3ffc0, 0, 0 }, | |
1341 | { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0x3ffc0, 0, 0 }, | |
1342 | { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x3ffc1, 0, 0 }, | |
1343 | ||
1344 | { NULL, 0xffffffff, 0, 0, 0 } | |
de0c62db DK |
1345 | }; |
1346 | ||
1347 | if (!netif_running(bp->dev)) | |
1348 | return rc; | |
1349 | ||
f2e0899f DK |
1350 | /* pre-Check the parity status */ |
1351 | for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { | |
1352 | val = REG_RD(bp, prty_tbl[i].offset); | |
1353 | if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) || | |
1354 | (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) || | |
1355 | (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) { | |
1356 | DP(NETIF_MSG_HW, | |
1357 | "%s is 0x%x\n", prty_tbl[i].name, val); | |
1358 | goto test_mem_exit; | |
1359 | } | |
1360 | } | |
1361 | ||
de0c62db DK |
1362 | /* Go through all the memories */ |
1363 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) | |
1364 | for (j = 0; j < mem_tbl[i].size; j++) | |
1365 | REG_RD(bp, mem_tbl[i].offset + j*4); | |
1366 | ||
1367 | /* Check the parity status */ | |
1368 | for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { | |
1369 | val = REG_RD(bp, prty_tbl[i].offset); | |
1370 | if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) || | |
f2e0899f DK |
1371 | (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) || |
1372 | (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) { | |
de0c62db DK |
1373 | DP(NETIF_MSG_HW, |
1374 | "%s is 0x%x\n", prty_tbl[i].name, val); | |
1375 | goto test_mem_exit; | |
1376 | } | |
1377 | } | |
1378 | ||
1379 | rc = 0; | |
1380 | ||
1381 | test_mem_exit: | |
1382 | return rc; | |
1383 | } | |
1384 | ||
a22f0788 | 1385 | static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) |
de0c62db | 1386 | { |
f2e0899f | 1387 | int cnt = 1400; |
de0c62db DK |
1388 | |
1389 | if (link_up) | |
a22f0788 | 1390 | while (bnx2x_link_test(bp, is_serdes) && cnt--) |
de0c62db DK |
1391 | msleep(10); |
1392 | } | |
1393 | ||
1394 | static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up) | |
1395 | { | |
1396 | unsigned int pkt_size, num_pkts, i; | |
1397 | struct sk_buff *skb; | |
1398 | unsigned char *packet; | |
1399 | struct bnx2x_fastpath *fp_rx = &bp->fp[0]; | |
1400 | struct bnx2x_fastpath *fp_tx = &bp->fp[0]; | |
1401 | u16 tx_start_idx, tx_idx; | |
1402 | u16 rx_start_idx, rx_idx; | |
1403 | u16 pkt_prod, bd_prod; | |
1404 | struct sw_tx_bd *tx_buf; | |
1405 | struct eth_tx_start_bd *tx_start_bd; | |
f2e0899f DK |
1406 | struct eth_tx_parse_bd_e1x *pbd_e1x = NULL; |
1407 | struct eth_tx_parse_bd_e2 *pbd_e2 = NULL; | |
de0c62db DK |
1408 | dma_addr_t mapping; |
1409 | union eth_rx_cqe *cqe; | |
1410 | u8 cqe_fp_flags; | |
1411 | struct sw_rx_bd *rx_buf; | |
1412 | u16 len; | |
1413 | int rc = -ENODEV; | |
1414 | ||
1415 | /* check the loopback mode */ | |
1416 | switch (loopback_mode) { | |
1417 | case BNX2X_PHY_LOOPBACK: | |
de6eae1f | 1418 | if (bp->link_params.loopback_mode != LOOPBACK_XGXS) |
de0c62db DK |
1419 | return -EINVAL; |
1420 | break; | |
1421 | case BNX2X_MAC_LOOPBACK: | |
1422 | bp->link_params.loopback_mode = LOOPBACK_BMAC; | |
1423 | bnx2x_phy_init(&bp->link_params, &bp->link_vars); | |
1424 | break; | |
1425 | default: | |
1426 | return -EINVAL; | |
1427 | } | |
1428 | ||
1429 | /* prepare the loopback packet */ | |
1430 | pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? | |
1431 | bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); | |
1432 | skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size); | |
1433 | if (!skb) { | |
1434 | rc = -ENOMEM; | |
1435 | goto test_loopback_exit; | |
1436 | } | |
1437 | packet = skb_put(skb, pkt_size); | |
1438 | memcpy(packet, bp->dev->dev_addr, ETH_ALEN); | |
1439 | memset(packet + ETH_ALEN, 0, ETH_ALEN); | |
1440 | memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); | |
1441 | for (i = ETH_HLEN; i < pkt_size; i++) | |
1442 | packet[i] = (unsigned char) (i & 0xff); | |
1443 | ||
1444 | /* send the loopback packet */ | |
1445 | num_pkts = 0; | |
1446 | tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb); | |
1447 | rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); | |
1448 | ||
1449 | pkt_prod = fp_tx->tx_pkt_prod++; | |
1450 | tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)]; | |
1451 | tx_buf->first_bd = fp_tx->tx_bd_prod; | |
1452 | tx_buf->skb = skb; | |
1453 | tx_buf->flags = 0; | |
1454 | ||
1455 | bd_prod = TX_BD(fp_tx->tx_bd_prod); | |
1456 | tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd; | |
1457 | mapping = dma_map_single(&bp->pdev->dev, skb->data, | |
1458 | skb_headlen(skb), DMA_TO_DEVICE); | |
1459 | tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); | |
1460 | tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); | |
1461 | tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ | |
1462 | tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); | |
523224a3 | 1463 | tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); |
de0c62db | 1464 | tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; |
523224a3 DK |
1465 | SET_FLAG(tx_start_bd->general_data, |
1466 | ETH_TX_START_BD_ETH_ADDR_TYPE, | |
1467 | UNICAST_ADDRESS); | |
1468 | SET_FLAG(tx_start_bd->general_data, | |
1469 | ETH_TX_START_BD_HDR_NBDS, | |
1470 | 1); | |
de0c62db DK |
1471 | |
1472 | /* turn on parsing and get a BD */ | |
1473 | bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); | |
f85582f8 | 1474 | |
523224a3 | 1475 | pbd_e1x = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e1x; |
f2e0899f | 1476 | pbd_e2 = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e2; |
de0c62db | 1477 | |
f2e0899f | 1478 | memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); |
523224a3 | 1479 | memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); |
de0c62db DK |
1480 | |
1481 | wmb(); | |
1482 | ||
1483 | fp_tx->tx_db.data.prod += 2; | |
1484 | barrier(); | |
1485 | DOORBELL(bp, fp_tx->index, fp_tx->tx_db.raw); | |
1486 | ||
1487 | mmiowb(); | |
1488 | ||
1489 | num_pkts++; | |
1490 | fp_tx->tx_bd_prod += 2; /* start + pbd */ | |
1491 | ||
1492 | udelay(100); | |
1493 | ||
1494 | tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb); | |
1495 | if (tx_idx != tx_start_idx + num_pkts) | |
1496 | goto test_loopback_exit; | |
1497 | ||
f2e0899f DK |
1498 | /* Unlike HC IGU won't generate an interrupt for status block |
1499 | * updates that have been performed while interrupts were | |
1500 | * disabled. | |
1501 | */ | |
1502 | if (bp->common.int_block == INT_BLOCK_IGU) | |
1503 | bnx2x_tx_int(fp_tx); | |
1504 | ||
de0c62db DK |
1505 | rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); |
1506 | if (rx_idx != rx_start_idx + num_pkts) | |
1507 | goto test_loopback_exit; | |
1508 | ||
1509 | cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; | |
1510 | cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; | |
1511 | if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) | |
1512 | goto test_loopback_rx_exit; | |
1513 | ||
1514 | len = le16_to_cpu(cqe->fast_path_cqe.pkt_len); | |
1515 | if (len != pkt_size) | |
1516 | goto test_loopback_rx_exit; | |
1517 | ||
1518 | rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; | |
1519 | skb = rx_buf->skb; | |
1520 | skb_reserve(skb, cqe->fast_path_cqe.placement_offset); | |
1521 | for (i = ETH_HLEN; i < pkt_size; i++) | |
1522 | if (*(skb->data + i) != (unsigned char) (i & 0xff)) | |
1523 | goto test_loopback_rx_exit; | |
1524 | ||
1525 | rc = 0; | |
1526 | ||
1527 | test_loopback_rx_exit: | |
1528 | ||
1529 | fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); | |
1530 | fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); | |
1531 | fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); | |
1532 | fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); | |
1533 | ||
1534 | /* Update producers */ | |
1535 | bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, | |
1536 | fp_rx->rx_sge_prod); | |
1537 | ||
1538 | test_loopback_exit: | |
1539 | bp->link_params.loopback_mode = LOOPBACK_NONE; | |
1540 | ||
1541 | return rc; | |
1542 | } | |
1543 | ||
1544 | static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up) | |
1545 | { | |
1546 | int rc = 0, res; | |
1547 | ||
1548 | if (BP_NOMCP(bp)) | |
1549 | return rc; | |
1550 | ||
1551 | if (!netif_running(bp->dev)) | |
1552 | return BNX2X_LOOPBACK_FAILED; | |
1553 | ||
1554 | bnx2x_netif_stop(bp, 1); | |
1555 | bnx2x_acquire_phy_lock(bp); | |
1556 | ||
1557 | res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up); | |
1558 | if (res) { | |
1559 | DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res); | |
1560 | rc |= BNX2X_PHY_LOOPBACK_FAILED; | |
1561 | } | |
1562 | ||
1563 | res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up); | |
1564 | if (res) { | |
1565 | DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res); | |
1566 | rc |= BNX2X_MAC_LOOPBACK_FAILED; | |
1567 | } | |
1568 | ||
1569 | bnx2x_release_phy_lock(bp); | |
1570 | bnx2x_netif_start(bp); | |
1571 | ||
1572 | return rc; | |
1573 | } | |
1574 | ||
1575 | #define CRC32_RESIDUAL 0xdebb20e3 | |
1576 | ||
1577 | static int bnx2x_test_nvram(struct bnx2x *bp) | |
1578 | { | |
1579 | static const struct { | |
1580 | int offset; | |
1581 | int size; | |
1582 | } nvram_tbl[] = { | |
1583 | { 0, 0x14 }, /* bootstrap */ | |
1584 | { 0x14, 0xec }, /* dir */ | |
1585 | { 0x100, 0x350 }, /* manuf_info */ | |
1586 | { 0x450, 0xf0 }, /* feature_info */ | |
1587 | { 0x640, 0x64 }, /* upgrade_key_info */ | |
1588 | { 0x6a4, 0x64 }, | |
1589 | { 0x708, 0x70 }, /* manuf_key_info */ | |
1590 | { 0x778, 0x70 }, | |
1591 | { 0, 0 } | |
1592 | }; | |
1593 | __be32 buf[0x350 / 4]; | |
1594 | u8 *data = (u8 *)buf; | |
1595 | int i, rc; | |
1596 | u32 magic, crc; | |
1597 | ||
1598 | if (BP_NOMCP(bp)) | |
1599 | return 0; | |
1600 | ||
1601 | rc = bnx2x_nvram_read(bp, 0, data, 4); | |
1602 | if (rc) { | |
1603 | DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc); | |
1604 | goto test_nvram_exit; | |
1605 | } | |
1606 | ||
1607 | magic = be32_to_cpu(buf[0]); | |
1608 | if (magic != 0x669955aa) { | |
1609 | DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic); | |
1610 | rc = -ENODEV; | |
1611 | goto test_nvram_exit; | |
1612 | } | |
1613 | ||
1614 | for (i = 0; nvram_tbl[i].size; i++) { | |
1615 | ||
1616 | rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data, | |
1617 | nvram_tbl[i].size); | |
1618 | if (rc) { | |
1619 | DP(NETIF_MSG_PROBE, | |
1620 | "nvram_tbl[%d] read data (rc %d)\n", i, rc); | |
1621 | goto test_nvram_exit; | |
1622 | } | |
1623 | ||
1624 | crc = ether_crc_le(nvram_tbl[i].size, data); | |
1625 | if (crc != CRC32_RESIDUAL) { | |
1626 | DP(NETIF_MSG_PROBE, | |
1627 | "nvram_tbl[%d] crc value (0x%08x)\n", i, crc); | |
1628 | rc = -ENODEV; | |
1629 | goto test_nvram_exit; | |
1630 | } | |
1631 | } | |
1632 | ||
1633 | test_nvram_exit: | |
1634 | return rc; | |
1635 | } | |
1636 | ||
1637 | static int bnx2x_test_intr(struct bnx2x *bp) | |
1638 | { | |
1639 | struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config); | |
1640 | int i, rc; | |
1641 | ||
1642 | if (!netif_running(bp->dev)) | |
1643 | return -ENODEV; | |
1644 | ||
1645 | config->hdr.length = 0; | |
1646 | if (CHIP_IS_E1(bp)) | |
f2e0899f | 1647 | config->hdr.offset = (BP_PORT(bp) ? 32 : 0); |
de0c62db DK |
1648 | else |
1649 | config->hdr.offset = BP_FUNC(bp); | |
1650 | config->hdr.client_id = bp->fp->cl_id; | |
1651 | config->hdr.reserved1 = 0; | |
1652 | ||
1653 | bp->set_mac_pending++; | |
1654 | smp_wmb(); | |
523224a3 | 1655 | rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0, |
de0c62db | 1656 | U64_HI(bnx2x_sp_mapping(bp, mac_config)), |
523224a3 | 1657 | U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1); |
de0c62db DK |
1658 | if (rc == 0) { |
1659 | for (i = 0; i < 10; i++) { | |
1660 | if (!bp->set_mac_pending) | |
1661 | break; | |
1662 | smp_rmb(); | |
1663 | msleep_interruptible(10); | |
1664 | } | |
1665 | if (i == 10) | |
1666 | rc = -ENODEV; | |
1667 | } | |
1668 | ||
1669 | return rc; | |
1670 | } | |
1671 | ||
1672 | static void bnx2x_self_test(struct net_device *dev, | |
1673 | struct ethtool_test *etest, u64 *buf) | |
1674 | { | |
1675 | struct bnx2x *bp = netdev_priv(dev); | |
a22f0788 | 1676 | u8 is_serdes; |
de0c62db DK |
1677 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
1678 | printk(KERN_ERR "Handling parity error recovery. Try again later\n"); | |
1679 | etest->flags |= ETH_TEST_FL_FAILED; | |
1680 | return; | |
1681 | } | |
1682 | ||
1683 | memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS); | |
1684 | ||
1685 | if (!netif_running(dev)) | |
1686 | return; | |
1687 | ||
1688 | /* offline tests are not supported in MF mode */ | |
fb3bff17 | 1689 | if (IS_MF(bp)) |
de0c62db | 1690 | etest->flags &= ~ETH_TEST_FL_OFFLINE; |
a22f0788 | 1691 | is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; |
de0c62db DK |
1692 | |
1693 | if (etest->flags & ETH_TEST_FL_OFFLINE) { | |
1694 | int port = BP_PORT(bp); | |
1695 | u32 val; | |
1696 | u8 link_up; | |
1697 | ||
1698 | /* save current value of input enable for TX port IF */ | |
1699 | val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); | |
1700 | /* disable input for TX port IF */ | |
1701 | REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); | |
1702 | ||
a22f0788 YR |
1703 | link_up = bp->link_vars.link_up; |
1704 | ||
de0c62db DK |
1705 | bnx2x_nic_unload(bp, UNLOAD_NORMAL); |
1706 | bnx2x_nic_load(bp, LOAD_DIAG); | |
1707 | /* wait until link state is restored */ | |
a22f0788 | 1708 | bnx2x_wait_for_link(bp, link_up, is_serdes); |
de0c62db DK |
1709 | |
1710 | if (bnx2x_test_registers(bp) != 0) { | |
1711 | buf[0] = 1; | |
1712 | etest->flags |= ETH_TEST_FL_FAILED; | |
1713 | } | |
1714 | if (bnx2x_test_memory(bp) != 0) { | |
1715 | buf[1] = 1; | |
1716 | etest->flags |= ETH_TEST_FL_FAILED; | |
1717 | } | |
f85582f8 | 1718 | |
de0c62db DK |
1719 | buf[2] = bnx2x_test_loopback(bp, link_up); |
1720 | if (buf[2] != 0) | |
1721 | etest->flags |= ETH_TEST_FL_FAILED; | |
1722 | ||
1723 | bnx2x_nic_unload(bp, UNLOAD_NORMAL); | |
1724 | ||
1725 | /* restore input for TX port IF */ | |
1726 | REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); | |
1727 | ||
1728 | bnx2x_nic_load(bp, LOAD_NORMAL); | |
1729 | /* wait until link state is restored */ | |
a22f0788 | 1730 | bnx2x_wait_for_link(bp, link_up, is_serdes); |
de0c62db DK |
1731 | } |
1732 | if (bnx2x_test_nvram(bp) != 0) { | |
1733 | buf[3] = 1; | |
1734 | etest->flags |= ETH_TEST_FL_FAILED; | |
1735 | } | |
1736 | if (bnx2x_test_intr(bp) != 0) { | |
1737 | buf[4] = 1; | |
1738 | etest->flags |= ETH_TEST_FL_FAILED; | |
1739 | } | |
1740 | if (bp->port.pmf) | |
a22f0788 | 1741 | if (bnx2x_link_test(bp, is_serdes) != 0) { |
de0c62db DK |
1742 | buf[5] = 1; |
1743 | etest->flags |= ETH_TEST_FL_FAILED; | |
1744 | } | |
1745 | ||
1746 | #ifdef BNX2X_EXTRA_DEBUG | |
1747 | bnx2x_panic_dump(bp); | |
1748 | #endif | |
1749 | } | |
1750 | ||
1751 | static const struct { | |
1752 | long offset; | |
1753 | int size; | |
1754 | u8 string[ETH_GSTRING_LEN]; | |
1755 | } bnx2x_q_stats_arr[BNX2X_NUM_Q_STATS] = { | |
1756 | /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%d]: rx_bytes" }, | |
1757 | { Q_STATS_OFFSET32(error_bytes_received_hi), | |
1758 | 8, "[%d]: rx_error_bytes" }, | |
1759 | { Q_STATS_OFFSET32(total_unicast_packets_received_hi), | |
1760 | 8, "[%d]: rx_ucast_packets" }, | |
1761 | { Q_STATS_OFFSET32(total_multicast_packets_received_hi), | |
1762 | 8, "[%d]: rx_mcast_packets" }, | |
1763 | { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), | |
1764 | 8, "[%d]: rx_bcast_packets" }, | |
1765 | { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%d]: rx_discards" }, | |
1766 | { Q_STATS_OFFSET32(rx_err_discard_pkt), | |
1767 | 4, "[%d]: rx_phy_ip_err_discards"}, | |
1768 | { Q_STATS_OFFSET32(rx_skb_alloc_failed), | |
1769 | 4, "[%d]: rx_skb_alloc_discard" }, | |
1770 | { Q_STATS_OFFSET32(hw_csum_err), 4, "[%d]: rx_csum_offload_errors" }, | |
1771 | ||
1772 | /* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%d]: tx_bytes" }, | |
1773 | { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), | |
1774 | 8, "[%d]: tx_ucast_packets" }, | |
1775 | { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), | |
1776 | 8, "[%d]: tx_mcast_packets" }, | |
1777 | { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), | |
1778 | 8, "[%d]: tx_bcast_packets" } | |
1779 | }; | |
1780 | ||
1781 | static const struct { | |
1782 | long offset; | |
1783 | int size; | |
1784 | u32 flags; | |
1785 | #define STATS_FLAGS_PORT 1 | |
1786 | #define STATS_FLAGS_FUNC 2 | |
1787 | #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) | |
1788 | u8 string[ETH_GSTRING_LEN]; | |
1789 | } bnx2x_stats_arr[BNX2X_NUM_STATS] = { | |
1790 | /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), | |
1791 | 8, STATS_FLAGS_BOTH, "rx_bytes" }, | |
1792 | { STATS_OFFSET32(error_bytes_received_hi), | |
1793 | 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, | |
1794 | { STATS_OFFSET32(total_unicast_packets_received_hi), | |
1795 | 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, | |
1796 | { STATS_OFFSET32(total_multicast_packets_received_hi), | |
1797 | 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, | |
1798 | { STATS_OFFSET32(total_broadcast_packets_received_hi), | |
1799 | 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, | |
1800 | { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), | |
1801 | 8, STATS_FLAGS_PORT, "rx_crc_errors" }, | |
1802 | { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), | |
1803 | 8, STATS_FLAGS_PORT, "rx_align_errors" }, | |
1804 | { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), | |
1805 | 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, | |
1806 | { STATS_OFFSET32(etherstatsoverrsizepkts_hi), | |
1807 | 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, | |
1808 | /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), | |
1809 | 8, STATS_FLAGS_PORT, "rx_fragments" }, | |
1810 | { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), | |
1811 | 8, STATS_FLAGS_PORT, "rx_jabbers" }, | |
1812 | { STATS_OFFSET32(no_buff_discard_hi), | |
1813 | 8, STATS_FLAGS_BOTH, "rx_discards" }, | |
1814 | { STATS_OFFSET32(mac_filter_discard), | |
1815 | 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, | |
1816 | { STATS_OFFSET32(xxoverflow_discard), | |
1817 | 4, STATS_FLAGS_PORT, "rx_fw_discards" }, | |
1818 | { STATS_OFFSET32(brb_drop_hi), | |
1819 | 8, STATS_FLAGS_PORT, "rx_brb_discard" }, | |
1820 | { STATS_OFFSET32(brb_truncate_hi), | |
1821 | 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, | |
1822 | { STATS_OFFSET32(pause_frames_received_hi), | |
1823 | 8, STATS_FLAGS_PORT, "rx_pause_frames" }, | |
1824 | { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), | |
1825 | 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, | |
1826 | { STATS_OFFSET32(nig_timer_max), | |
1827 | 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, | |
1828 | /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), | |
1829 | 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, | |
1830 | { STATS_OFFSET32(rx_skb_alloc_failed), | |
1831 | 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, | |
1832 | { STATS_OFFSET32(hw_csum_err), | |
1833 | 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, | |
1834 | ||
1835 | { STATS_OFFSET32(total_bytes_transmitted_hi), | |
1836 | 8, STATS_FLAGS_BOTH, "tx_bytes" }, | |
1837 | { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), | |
1838 | 8, STATS_FLAGS_PORT, "tx_error_bytes" }, | |
1839 | { STATS_OFFSET32(total_unicast_packets_transmitted_hi), | |
1840 | 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, | |
1841 | { STATS_OFFSET32(total_multicast_packets_transmitted_hi), | |
1842 | 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, | |
1843 | { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), | |
1844 | 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, | |
1845 | { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), | |
1846 | 8, STATS_FLAGS_PORT, "tx_mac_errors" }, | |
1847 | { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), | |
1848 | 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, | |
1849 | /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), | |
1850 | 8, STATS_FLAGS_PORT, "tx_single_collisions" }, | |
1851 | { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), | |
1852 | 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, | |
1853 | { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), | |
1854 | 8, STATS_FLAGS_PORT, "tx_deferred" }, | |
1855 | { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), | |
1856 | 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, | |
1857 | { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), | |
1858 | 8, STATS_FLAGS_PORT, "tx_late_collisions" }, | |
1859 | { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), | |
1860 | 8, STATS_FLAGS_PORT, "tx_total_collisions" }, | |
1861 | { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), | |
1862 | 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, | |
1863 | { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), | |
1864 | 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, | |
1865 | { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), | |
1866 | 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, | |
1867 | { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), | |
1868 | 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, | |
1869 | /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), | |
1870 | 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, | |
1871 | { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), | |
1872 | 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, | |
1873 | { STATS_OFFSET32(etherstatspktsover1522octets_hi), | |
1874 | 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, | |
1875 | { STATS_OFFSET32(pause_frames_sent_hi), | |
1876 | 8, STATS_FLAGS_PORT, "tx_pause_frames" } | |
1877 | }; | |
1878 | ||
1879 | #define IS_PORT_STAT(i) \ | |
1880 | ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) | |
1881 | #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) | |
fb3bff17 DK |
1882 | #define IS_MF_MODE_STAT(bp) \ |
1883 | (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) | |
de0c62db DK |
1884 | |
1885 | static int bnx2x_get_sset_count(struct net_device *dev, int stringset) | |
1886 | { | |
1887 | struct bnx2x *bp = netdev_priv(dev); | |
1888 | int i, num_stats; | |
1889 | ||
1890 | switch (stringset) { | |
1891 | case ETH_SS_STATS: | |
1892 | if (is_multi(bp)) { | |
1893 | num_stats = BNX2X_NUM_Q_STATS * bp->num_queues; | |
fb3bff17 | 1894 | if (!IS_MF_MODE_STAT(bp)) |
de0c62db DK |
1895 | num_stats += BNX2X_NUM_STATS; |
1896 | } else { | |
fb3bff17 | 1897 | if (IS_MF_MODE_STAT(bp)) { |
de0c62db DK |
1898 | num_stats = 0; |
1899 | for (i = 0; i < BNX2X_NUM_STATS; i++) | |
1900 | if (IS_FUNC_STAT(i)) | |
1901 | num_stats++; | |
1902 | } else | |
1903 | num_stats = BNX2X_NUM_STATS; | |
1904 | } | |
1905 | return num_stats; | |
1906 | ||
1907 | case ETH_SS_TEST: | |
1908 | return BNX2X_NUM_TESTS; | |
1909 | ||
1910 | default: | |
1911 | return -EINVAL; | |
1912 | } | |
1913 | } | |
1914 | ||
1915 | static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) | |
1916 | { | |
1917 | struct bnx2x *bp = netdev_priv(dev); | |
1918 | int i, j, k; | |
1919 | ||
1920 | switch (stringset) { | |
1921 | case ETH_SS_STATS: | |
1922 | if (is_multi(bp)) { | |
1923 | k = 0; | |
1924 | for_each_queue(bp, i) { | |
1925 | for (j = 0; j < BNX2X_NUM_Q_STATS; j++) | |
1926 | sprintf(buf + (k + j)*ETH_GSTRING_LEN, | |
1927 | bnx2x_q_stats_arr[j].string, i); | |
1928 | k += BNX2X_NUM_Q_STATS; | |
1929 | } | |
fb3bff17 | 1930 | if (IS_MF_MODE_STAT(bp)) |
de0c62db DK |
1931 | break; |
1932 | for (j = 0; j < BNX2X_NUM_STATS; j++) | |
1933 | strcpy(buf + (k + j)*ETH_GSTRING_LEN, | |
1934 | bnx2x_stats_arr[j].string); | |
1935 | } else { | |
1936 | for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { | |
fb3bff17 | 1937 | if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) |
de0c62db DK |
1938 | continue; |
1939 | strcpy(buf + j*ETH_GSTRING_LEN, | |
1940 | bnx2x_stats_arr[i].string); | |
1941 | j++; | |
1942 | } | |
1943 | } | |
1944 | break; | |
1945 | ||
1946 | case ETH_SS_TEST: | |
1947 | memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr)); | |
1948 | break; | |
1949 | } | |
1950 | } | |
1951 | ||
1952 | static void bnx2x_get_ethtool_stats(struct net_device *dev, | |
1953 | struct ethtool_stats *stats, u64 *buf) | |
1954 | { | |
1955 | struct bnx2x *bp = netdev_priv(dev); | |
1956 | u32 *hw_stats, *offset; | |
1957 | int i, j, k; | |
1958 | ||
1959 | if (is_multi(bp)) { | |
1960 | k = 0; | |
1961 | for_each_queue(bp, i) { | |
1962 | hw_stats = (u32 *)&bp->fp[i].eth_q_stats; | |
1963 | for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { | |
1964 | if (bnx2x_q_stats_arr[j].size == 0) { | |
1965 | /* skip this counter */ | |
1966 | buf[k + j] = 0; | |
1967 | continue; | |
1968 | } | |
1969 | offset = (hw_stats + | |
1970 | bnx2x_q_stats_arr[j].offset); | |
1971 | if (bnx2x_q_stats_arr[j].size == 4) { | |
1972 | /* 4-byte counter */ | |
1973 | buf[k + j] = (u64) *offset; | |
1974 | continue; | |
1975 | } | |
1976 | /* 8-byte counter */ | |
1977 | buf[k + j] = HILO_U64(*offset, *(offset + 1)); | |
1978 | } | |
1979 | k += BNX2X_NUM_Q_STATS; | |
1980 | } | |
fb3bff17 | 1981 | if (IS_MF_MODE_STAT(bp)) |
de0c62db DK |
1982 | return; |
1983 | hw_stats = (u32 *)&bp->eth_stats; | |
1984 | for (j = 0; j < BNX2X_NUM_STATS; j++) { | |
1985 | if (bnx2x_stats_arr[j].size == 0) { | |
1986 | /* skip this counter */ | |
1987 | buf[k + j] = 0; | |
1988 | continue; | |
1989 | } | |
1990 | offset = (hw_stats + bnx2x_stats_arr[j].offset); | |
1991 | if (bnx2x_stats_arr[j].size == 4) { | |
1992 | /* 4-byte counter */ | |
1993 | buf[k + j] = (u64) *offset; | |
1994 | continue; | |
1995 | } | |
1996 | /* 8-byte counter */ | |
1997 | buf[k + j] = HILO_U64(*offset, *(offset + 1)); | |
1998 | } | |
1999 | } else { | |
2000 | hw_stats = (u32 *)&bp->eth_stats; | |
2001 | for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { | |
fb3bff17 | 2002 | if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) |
de0c62db DK |
2003 | continue; |
2004 | if (bnx2x_stats_arr[i].size == 0) { | |
2005 | /* skip this counter */ | |
2006 | buf[j] = 0; | |
2007 | j++; | |
2008 | continue; | |
2009 | } | |
2010 | offset = (hw_stats + bnx2x_stats_arr[i].offset); | |
2011 | if (bnx2x_stats_arr[i].size == 4) { | |
2012 | /* 4-byte counter */ | |
2013 | buf[j] = (u64) *offset; | |
2014 | j++; | |
2015 | continue; | |
2016 | } | |
2017 | /* 8-byte counter */ | |
2018 | buf[j] = HILO_U64(*offset, *(offset + 1)); | |
2019 | j++; | |
2020 | } | |
2021 | } | |
2022 | } | |
2023 | ||
2024 | static int bnx2x_phys_id(struct net_device *dev, u32 data) | |
2025 | { | |
2026 | struct bnx2x *bp = netdev_priv(dev); | |
2027 | int i; | |
2028 | ||
2029 | if (!netif_running(dev)) | |
2030 | return 0; | |
2031 | ||
2032 | if (!bp->port.pmf) | |
2033 | return 0; | |
2034 | ||
2035 | if (data == 0) | |
2036 | data = 2; | |
2037 | ||
2038 | for (i = 0; i < (data * 2); i++) { | |
2039 | if ((i % 2) == 0) | |
7f02c4ad YR |
2040 | bnx2x_set_led(&bp->link_params, &bp->link_vars, |
2041 | LED_MODE_OPER, SPEED_1000); | |
de0c62db | 2042 | else |
7f02c4ad YR |
2043 | bnx2x_set_led(&bp->link_params, &bp->link_vars, |
2044 | LED_MODE_OFF, 0); | |
de0c62db DK |
2045 | |
2046 | msleep_interruptible(500); | |
2047 | if (signal_pending(current)) | |
2048 | break; | |
2049 | } | |
2050 | ||
2051 | if (bp->link_vars.link_up) | |
7f02c4ad | 2052 | bnx2x_set_led(&bp->link_params, &bp->link_vars, LED_MODE_OPER, |
de0c62db DK |
2053 | bp->link_vars.line_speed); |
2054 | ||
2055 | return 0; | |
2056 | } | |
2057 | ||
2058 | static const struct ethtool_ops bnx2x_ethtool_ops = { | |
2059 | .get_settings = bnx2x_get_settings, | |
2060 | .set_settings = bnx2x_set_settings, | |
2061 | .get_drvinfo = bnx2x_get_drvinfo, | |
2062 | .get_regs_len = bnx2x_get_regs_len, | |
2063 | .get_regs = bnx2x_get_regs, | |
2064 | .get_wol = bnx2x_get_wol, | |
2065 | .set_wol = bnx2x_set_wol, | |
2066 | .get_msglevel = bnx2x_get_msglevel, | |
2067 | .set_msglevel = bnx2x_set_msglevel, | |
2068 | .nway_reset = bnx2x_nway_reset, | |
2069 | .get_link = bnx2x_get_link, | |
2070 | .get_eeprom_len = bnx2x_get_eeprom_len, | |
2071 | .get_eeprom = bnx2x_get_eeprom, | |
2072 | .set_eeprom = bnx2x_set_eeprom, | |
2073 | .get_coalesce = bnx2x_get_coalesce, | |
2074 | .set_coalesce = bnx2x_set_coalesce, | |
2075 | .get_ringparam = bnx2x_get_ringparam, | |
2076 | .set_ringparam = bnx2x_set_ringparam, | |
2077 | .get_pauseparam = bnx2x_get_pauseparam, | |
2078 | .set_pauseparam = bnx2x_set_pauseparam, | |
2079 | .get_rx_csum = bnx2x_get_rx_csum, | |
2080 | .set_rx_csum = bnx2x_set_rx_csum, | |
2081 | .get_tx_csum = ethtool_op_get_tx_csum, | |
2082 | .set_tx_csum = ethtool_op_set_tx_hw_csum, | |
2083 | .set_flags = bnx2x_set_flags, | |
2084 | .get_flags = ethtool_op_get_flags, | |
2085 | .get_sg = ethtool_op_get_sg, | |
2086 | .set_sg = ethtool_op_set_sg, | |
2087 | .get_tso = ethtool_op_get_tso, | |
2088 | .set_tso = bnx2x_set_tso, | |
2089 | .self_test = bnx2x_self_test, | |
2090 | .get_sset_count = bnx2x_get_sset_count, | |
2091 | .get_strings = bnx2x_get_strings, | |
2092 | .phys_id = bnx2x_phys_id, | |
2093 | .get_ethtool_stats = bnx2x_get_ethtool_stats, | |
2094 | }; | |
2095 | ||
2096 | void bnx2x_set_ethtool_ops(struct net_device *netdev) | |
2097 | { | |
2098 | SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops); | |
2099 | } |