[mirror_ubuntu-zesty-kernel.git] / drivers / net / bnx2x / bnx2x_link.h

/* Copyright 2008-2011 Broadcom Corporation
 *
 * Unless you and Broadcom execute a separate written software license
 * agreement governing use of this software, this software is licensed to you
 * under the terms of the GNU General Public License version 2, available
 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
 *
 * Notwithstanding the above, under no circumstances may you combine this
 * software in any way with any other Broadcom software provided under a
 * license other than the GPL, without Broadcom's express prior written
 * consent.
 *
 * Written by Yaniv Rosner
 *
 */

#ifndef BNX2X_LINK_H
#define BNX2X_LINK_H


/***********************************************************/
/*                         Defines                         */
/***********************************************************/
#define DEFAULT_PHY_DEV_ADDR	3
#define E2_DEFAULT_PHY_DEV_ADDR	5


#define BNX2X_FLOW_CTRL_AUTO		PORT_FEATURE_FLOW_CONTROL_AUTO
#define BNX2X_FLOW_CTRL_TX		PORT_FEATURE_FLOW_CONTROL_TX
#define BNX2X_FLOW_CTRL_RX		PORT_FEATURE_FLOW_CONTROL_RX
#define BNX2X_FLOW_CTRL_BOTH		PORT_FEATURE_FLOW_CONTROL_BOTH
#define BNX2X_FLOW_CTRL_NONE		PORT_FEATURE_FLOW_CONTROL_NONE

#define SPEED_AUTO_NEG		0
#define SPEED_12000		12000
#define SPEED_12500		12500
#define SPEED_13000		13000
#define SPEED_15000		15000
#define SPEED_16000		16000

#define SFP_EEPROM_VENDOR_NAME_ADDR		0x14
#define SFP_EEPROM_VENDOR_NAME_SIZE		16
#define SFP_EEPROM_VENDOR_OUI_ADDR		0x25
#define SFP_EEPROM_VENDOR_OUI_SIZE		3
#define SFP_EEPROM_PART_NO_ADDR			0x28
#define SFP_EEPROM_PART_NO_SIZE			16
#define PWR_FLT_ERR_MSG_LEN			250

#define XGXS_EXT_PHY_TYPE(ext_phy_config) \
		((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
#define XGXS_EXT_PHY_ADDR(ext_phy_config) \
		(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
		 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
#define SERDES_EXT_PHY_TYPE(ext_phy_config) \
		((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)

/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
#define SINGLE_MEDIA_DIRECT(params)	(params->num_phys == 1)
/* Single Media board contains single external phy */
#define SINGLE_MEDIA(params)		(params->num_phys == 2)
/* Dual Media board contains two external phy with different media */
#define DUAL_MEDIA(params)		(params->num_phys == 3)
#define FW_PARAM_MDIO_CTRL_OFFSET		16
#define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
	(phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)

#define PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE		170
#define PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE		0

#define PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE			250
#define PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE		0

#define PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE			10
#define PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE		90

#define PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE			50
#define PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE		250

#define PFC_BRB_FULL_LB_XOFF_THRESHOLD				170
#define PFC_BRB_FULL_LB_XON_THRESHOLD				250

#define MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
/***********************************************************/
/*                         Structs                         */
/***********************************************************/
#define INT_PHY		0
#define EXT_PHY1	1
#define EXT_PHY2	2
#define MAX_PHYS	3

/* Same configuration is shared between the XGXS and the first external phy */
#define LINK_CONFIG_SIZE (MAX_PHYS - 1)
#define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
					 0 : (_phy_idx - 1))
/***********************************************************/
/*                      bnx2x_phy struct                     */
/*  Defines the required arguments and function per phy    */
/***********************************************************/
struct link_vars;
struct link_params;
struct bnx2x_phy;

typedef u8 (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params,
			    struct link_vars *vars);
typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params,
			    struct link_vars *vars);
typedef void (*link_reset_t)(struct bnx2x_phy *phy,
			     struct link_params *params);
typedef void (*config_loopback_t)(struct bnx2x_phy *phy,
				  struct link_params *params);
typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len);
typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params);
typedef void (*set_link_led_t)(struct bnx2x_phy *phy,
			       struct link_params *params, u8 mode);
typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy,
				    struct link_params *params, u32 action);

struct bnx2x_phy {
	u32 type;

	/* Loaded during init */
	u8 addr;
	u8 def_md_devad;
	u16 flags;
	/* Require HW lock */
#define FLAGS_HW_LOCK_REQUIRED		(1<<0)
	/* No Over-Current detection */
#define FLAGS_NOC			(1<<1)
	/* Fan failure detection required */
#define FLAGS_FAN_FAILURE_DET_REQ	(1<<2)
	/* Initialize first the XGXS and only then the phy itself */
#define FLAGS_INIT_XGXS_FIRST		(1<<3)
#define FLAGS_REARM_LATCH_SIGNAL	(1<<6)
#define FLAGS_SFP_NOT_APPROVED		(1<<7)

	/* preemphasis values for the rx side */
	u16 rx_preemphasis[4];

	/* preemphasis values for the tx side */
	u16 tx_preemphasis[4];

	/* EMAC address for access MDIO */
	u32 mdio_ctrl;

	u32 supported;

	u32 media_type;
#define	ETH_PHY_UNSPECIFIED 0x0
#define	ETH_PHY_SFP_FIBER   0x1
#define	ETH_PHY_XFP_FIBER   0x2
#define	ETH_PHY_DA_TWINAX   0x3
#define	ETH_PHY_BASE_T      0x4
#define	ETH_PHY_KR	    0xf0
#define	ETH_PHY_CX4	    0xf1
#define	ETH_PHY_NOT_PRESENT 0xff

	/* The address in which version is located*/
	u32 ver_addr;

	u16 req_flow_ctrl;

	u16 req_line_speed;

	u32 speed_cap_mask;

	u16 req_duplex;
	u16 rsrv;
	/* Called per phy/port init, and it configures LASI, speed, autoneg,
	 duplex, flow control negotiation, etc. */
	config_init_t config_init;

	/* Called due to interrupt. It determines the link, speed */
	read_status_t read_status;

	/* Called when driver is unloading. Should reset the phy */
	link_reset_t link_reset;

	/* Set the loopback configuration for the phy */
	config_loopback_t config_loopback;

	/* Format the given raw number into str up to len */
	format_fw_ver_t format_fw_ver;

	/* Reset the phy (both ports) */
	hw_reset_t hw_reset;

	/* Set link led mode (on/off/oper)*/
	set_link_led_t set_link_led;

	/* PHY Specific tasks */
	phy_specific_func_t phy_specific_func;
#define DISABLE_TX	1
#define ENABLE_TX	2
};

/* Inputs parameters to the CLC */
struct link_params {

	u8 port;

	/* Default / User Configuration */
	u8 loopback_mode;
#define LOOPBACK_NONE		0
#define LOOPBACK_EMAC		1
#define LOOPBACK_BMAC		2
#define LOOPBACK_XGXS		3
#define LOOPBACK_EXT_PHY	4
#define LOOPBACK_EXT		5
#define LOOPBACK_UMAC		6
#define LOOPBACK_XMAC		7

	/* Device parameters */
	u8 mac_addr[6];

	u16 req_duplex[LINK_CONFIG_SIZE];
	u16 req_flow_ctrl[LINK_CONFIG_SIZE];

	u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */

	/* shmem parameters */
	u32 shmem_base;
	u32 shmem2_base;
	u32 speed_cap_mask[LINK_CONFIG_SIZE];
	u32 switch_cfg;
#define SWITCH_CFG_1G		PORT_FEATURE_CON_SWITCH_1G_SWITCH
#define SWITCH_CFG_10G		PORT_FEATURE_CON_SWITCH_10G_SWITCH
#define SWITCH_CFG_AUTO_DETECT	PORT_FEATURE_CON_SWITCH_AUTO_DETECT

	u32 lane_config;

	/* Phy register parameter */
	u32 chip_id;

	/* features */
	u32 feature_config_flags;
#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED	(1<<0)
#define FEATURE_CONFIG_PFC_ENABLED			(1<<1)
#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY		(1<<2)
#define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY	(1<<3)
	/* Will be populated during common init */
	struct bnx2x_phy phy[MAX_PHYS];

	/* Will be populated during common init */
	u8 num_phys;

	u8 rsrv;
	u16 hw_led_mode; /* part of the hw_config read from the shmem */
	u32 multi_phy_config;

	/* Device pointer passed to all callback functions */
	struct bnx2x *bp;
	u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
				req_flow_ctrl is set to AUTO */
};

/* Output parameters */
struct link_vars {
	u8 phy_flags;

	u8 mac_type;
#define MAC_TYPE_NONE		0
#define MAC_TYPE_EMAC		1
#define MAC_TYPE_BMAC		2
#define MAC_TYPE_UMAC		3
#define MAC_TYPE_XMAC		4

	u8 phy_link_up; /* internal phy link indication */
	u8 link_up;

	u16 line_speed;
	u16 duplex;

	u16 flow_ctrl;
	u16 ieee_fc;

	/* The same definitions as the shmem parameter */
	u32 link_status;
	u8 fault_detected;
	u8 rsrv1;
	u16 rsrv2;
	u32 aeu_int_mask;
};

/***********************************************************/
/*                         Functions                       */
/***********************************************************/
int bnx2x_phy_init(struct link_params *params, struct link_vars *vars);

/* Reset the link. Should be called when driver or interface goes down
   Before calling phy firmware upgrade, the reset_ext_phy should be set
   to 0 */
int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
		     u8 reset_ext_phy);

/* bnx2x_link_update should be called upon link interrupt */
int bnx2x_link_update(struct link_params *params, struct link_vars *vars);

/* use the following phy functions to read/write from external_phy
  In order to use it to read/write internal phy registers, use
  DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
  the register */
int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
		   u8 devad, u16 reg, u16 *ret_val);

int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
		    u8 devad, u16 reg, u16 val);

/* Reads the link_status from the shmem,
   and update the link vars accordingly */
void bnx2x_link_status_update(struct link_params *input,
			    struct link_vars *output);
/* returns string representing the fw_version of the external phy */
int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
				 u8 *version, u16 len);

/* Set/Unset the led
   Basically, the CLC takes care of the led for the link, but in case one needs
   to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
   blink the led, and LED_MODE_OFF to set the led off.*/
int bnx2x_set_led(struct link_params *params,
		  struct link_vars *vars, u8 mode, u32 speed);
#define LED_MODE_OFF			0
#define LED_MODE_ON			1
#define LED_MODE_OPER			2
#define LED_MODE_FRONT_PANEL_OFF	3

/* bnx2x_handle_module_detect_int should be called upon module detection
   interrupt */
void bnx2x_handle_module_detect_int(struct link_params *params);

/* Get the actual link status. In case it returns 0, link is up,
	otherwise link is down*/
int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
		    u8 is_serdes);

/* One-time initialization for external phy after power up */
int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
			  u32 shmem2_base_path[], u32 chip_id);

/* Reset the external PHY using GPIO */
void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);

/* Reset the external of SFX7101 */
void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy);

/* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
				 struct link_params *params, u16 addr,
				 u8 byte_cnt, u8 *o_buf);

void bnx2x_hw_reset_phy(struct link_params *params);

/* Checks if HW lock is required for this phy/board type */
u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base,
			  u32 shmem2_base);

/* Check swap bit and adjust PHY order */
u32 bnx2x_phy_selection(struct link_params *params);

/* Probe the phys on board, and populate them in "params" */
int bnx2x_phy_probe(struct link_params *params);

/* Checks if fan failure detection is required on one of the phys on board */
u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
			     u32 shmem2_base, u8 port);

/* DCBX structs */

/* Number of maximum COS per chip */
#define DCBX_E2E3_MAX_NUM_COS		(2)
#define DCBX_E3B0_MAX_NUM_COS_PORT0	(6)
#define DCBX_E3B0_MAX_NUM_COS_PORT1	(3)
#define DCBX_E3B0_MAX_NUM_COS		( \
			MAXVAL(DCBX_E3B0_MAX_NUM_COS_PORT0, \
			    DCBX_E3B0_MAX_NUM_COS_PORT1))

#define DCBX_MAX_NUM_COS			( \
			MAXVAL(DCBX_E3B0_MAX_NUM_COS, \
			    DCBX_E2E3_MAX_NUM_COS))

/* PFC port configuration params */
struct bnx2x_nig_brb_pfc_port_params {
	/* NIG */
	u32 pause_enable;
	u32 llfc_out_en;
	u32 llfc_enable;
	u32 pkt_priority_to_cos;
	u8 num_of_rx_cos_priority_mask;
	u32 rx_cos_priority_mask[DCBX_MAX_NUM_COS];
	u32 llfc_high_priority_classes;
	u32 llfc_low_priority_classes;
	/* BRB */
	u32 cos0_pauseable;
	u32 cos1_pauseable;
};

/**
 * Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
 * when link is already up
 */
void bnx2x_update_pfc(struct link_params *params,
		      struct link_vars *vars,
		      struct bnx2x_nig_brb_pfc_port_params *pfc_params);


/* Used to configure the ETS to disable */
void bnx2x_ets_disabled(struct link_params *params);

/* Used to configure the ETS to BW limited */
void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
			const u32 cos1_bw);

/* Used to configure the ETS to strict */
int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);

/* Read pfc statistic*/
void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
						 u32 pfc_frames_sent[2],
						 u32 pfc_frames_received[2]);
void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
			    u32 chip_id, u32 shmem_base, u32 shmem2_base,
			    u8 port);
#endif /* BNX2X_LINK_H */
Commit	Line	Data
cd88ccee	1	/* Copyright 2008-2011 Broadcom Corporation
ea4e040a YR	2	*
	3	* Unless you and Broadcom execute a separate written software license
	4	* agreement governing use of this software, this software is licensed to you
	5	* under the terms of the GNU General Public License version 2, available
	6	* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
	7	*
	8	* Notwithstanding the above, under no circumstances may you combine this
	9	* software in any way with any other Broadcom software provided under a
	10	* license other than the GPL, without Broadcom's express prior written
	11	* consent.
	12	*
	13	* Written by Yaniv Rosner
	14	*
	15	*/
	16
	17	#ifndef BNX2X_LINK_H
	18	#define BNX2X_LINK_H
	19
	20
	21
	22	/***********************************************************/
	23	/* Defines */
	24	/***********************************************************/
f2e0899f DK	25	#define DEFAULT_PHY_DEV_ADDR 3
f2e0899f DK	26	#define E2_DEFAULT_PHY_DEV_ADDR 5
ea4e040a YR	27
	28
	29
c0700f90 DM	30	#define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
	31	#define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
	32	#define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
	33	#define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
	34	#define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
ea4e040a	35
cd88ccee	36	#define SPEED_AUTO_NEG 0
ea4e040a YR	37	#define SPEED_12000 12000
	38	#define SPEED_12500 12500
	39	#define SPEED_13000 13000
	40	#define SPEED_15000 15000
	41	#define SPEED_16000 16000
	42
4d295db0 EG	43	#define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
	44	#define SFP_EEPROM_VENDOR_NAME_SIZE 16
	45	#define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
	46	#define SFP_EEPROM_VENDOR_OUI_SIZE 3
cd88ccee YR	47	#define SFP_EEPROM_PART_NO_ADDR 0x28
cd88ccee YR	48	#define SFP_EEPROM_PART_NO_SIZE 16
4d295db0	49	#define PWR_FLT_ERR_MSG_LEN 250
b7737c9b YR	50
	51	#define XGXS_EXT_PHY_TYPE(ext_phy_config) \
	52	((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
	53	#define XGXS_EXT_PHY_ADDR(ext_phy_config) \
	54	(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
	55	PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
	56	#define SERDES_EXT_PHY_TYPE(ext_phy_config) \
	57	((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
	58
e10bc84d YR	59	/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
	60	#define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
	61	/* Single Media board contains single external phy */
	62	#define SINGLE_MEDIA(params) (params->num_phys == 2)
a22f0788 YR	63	/* Dual Media board contains two external phy with different media */
a22f0788 YR	64	#define DUAL_MEDIA(params) (params->num_phys == 3)
cd88ccee	65	#define FW_PARAM_MDIO_CTRL_OFFSET 16
a22f0788 YR	66	#define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
a22f0788 YR	67	(phy_addr \| phy_type \| mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
bcab15c5 VZ	68
	69	#define PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE 170
	70	#define PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE 0
	71
	72	#define PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE 250
	73	#define PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE 0
	74
	75	#define PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE 10
	76	#define PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE 90
	77
	78	#define PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE 50
	79	#define PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE 250
	80
	81	#define PFC_BRB_FULL_LB_XOFF_THRESHOLD 170
	82	#define PFC_BRB_FULL_LB_XON_THRESHOLD 250
	83
619c5cb6	84	#define MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
ea4e040a YR	85	/***********************************************************/
	86	/* Structs */
	87	/***********************************************************/
e10bc84d YR	88	#define INT_PHY 0
e10bc84d YR	89	#define EXT_PHY1 1
a22f0788 YR	90	#define EXT_PHY2 2
a22f0788 YR	91	#define MAX_PHYS 3
e10bc84d	92
b7737c9b YR	93	/* Same configuration is shared between the XGXS and the first external phy */
	94	#define LINK_CONFIG_SIZE (MAX_PHYS - 1)
	95	#define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
	96	0 : (_phy_idx - 1))
e10bc84d YR	97	/***********************************************************/
	98	/* bnx2x_phy struct */
	99	/* Defines the required arguments and function per phy */
	100	/***********************************************************/
	101	struct link_vars;
	102	struct link_params;
	103	struct bnx2x_phy;
	104
b7737c9b YR	105	typedef u8 (config_init_t)(struct bnx2x_phy phy, struct link_params *params,
	106	struct link_vars *vars);
	107	typedef u8 (read_status_t)(struct bnx2x_phy phy, struct link_params *params,
	108	struct link_vars *vars);
	109	typedef void (link_reset_t)(struct bnx2x_phy phy,
	110	struct link_params *params);
	111	typedef void (config_loopback_t)(struct bnx2x_phy phy,
	112	struct link_params *params);
	113	typedef u8 (format_fw_ver_t)(u32 raw, u8 str, u16 *len);
	114	typedef void (hw_reset_t)(struct bnx2x_phy phy, struct link_params *params);
	115	typedef void (set_link_led_t)(struct bnx2x_phy phy,
	116	struct link_params *params, u8 mode);
a22f0788 YR	117	typedef void (phy_specific_func_t)(struct bnx2x_phy phy,
a22f0788 YR	118	struct link_params *params, u32 action);
b7737c9b	119
e10bc84d YR	120	struct bnx2x_phy {
	121	u32 type;
	122
	123	/* Loaded during init */
	124	u8 addr;
9045f6b4 YR	125	u8 def_md_devad;
9045f6b4 YR	126	u16 flags;
b7737c9b YR	127	/* Require HW lock */
	128	#define FLAGS_HW_LOCK_REQUIRED (1<<0)
	129	/* No Over-Current detection */
	130	#define FLAGS_NOC (1<<1)
	131	/* Fan failure detection required */
	132	#define FLAGS_FAN_FAILURE_DET_REQ (1<<2)
	133	/* Initialize first the XGXS and only then the phy itself */
a22f0788 YR	134	#define FLAGS_INIT_XGXS_FIRST (1<<3)
	135	#define FLAGS_REARM_LATCH_SIGNAL (1<<6)
	136	#define FLAGS_SFP_NOT_APPROVED (1<<7)
b7737c9b	137
b7737c9b YR	138	/* preemphasis values for the rx side */
	139	u16 rx_preemphasis[4];
	140
	141	/* preemphasis values for the tx side */
	142	u16 tx_preemphasis[4];
	143
	144	/* EMAC address for access MDIO */
e10bc84d	145	u32 mdio_ctrl;
b7737c9b YR	146
	147	u32 supported;
	148
	149	u32 media_type;
	150	#define ETH_PHY_UNSPECIFIED 0x0
	151	#define ETH_PHY_SFP_FIBER 0x1
	152	#define ETH_PHY_XFP_FIBER 0x2
	153	#define ETH_PHY_DA_TWINAX 0x3
	154	#define ETH_PHY_BASE_T 0x4
1ac9e428 YR	155	#define ETH_PHY_KR 0xf0
1ac9e428 YR	156	#define ETH_PHY_CX4 0xf1
b7737c9b YR	157	#define ETH_PHY_NOT_PRESENT 0xff
	158
	159	/* The address in which version is located*/
	160	u32 ver_addr;
	161
	162	u16 req_flow_ctrl;
	163
	164	u16 req_line_speed;
	165
	166	u32 speed_cap_mask;
	167
	168	u16 req_duplex;
	169	u16 rsrv;
	170	/* Called per phy/port init, and it configures LASI, speed, autoneg,
	171	duplex, flow control negotiation, etc. */
	172	config_init_t config_init;
	173
	174	/* Called due to interrupt. It determines the link, speed */
	175	read_status_t read_status;
	176
	177	/* Called when driver is unloading. Should reset the phy */
	178	link_reset_t link_reset;
	179
	180	/* Set the loopback configuration for the phy */
	181	config_loopback_t config_loopback;
	182
	183	/* Format the given raw number into str up to len */
	184	format_fw_ver_t format_fw_ver;
	185
	186	/* Reset the phy (both ports) */
	187	hw_reset_t hw_reset;
	188
	189	/* Set link led mode (on/off/oper)*/
	190	set_link_led_t set_link_led;
a22f0788 YR	191
	192	/* PHY Specific tasks */
	193	phy_specific_func_t phy_specific_func;
	194	#define DISABLE_TX 1
	195	#define ENABLE_TX 2
e10bc84d YR	196	};
e10bc84d YR	197
ea4e040a YR	198	/* Inputs parameters to the CLC */
	199	struct link_params {
	200
	201	u8 port;
	202
	203	/* Default / User Configuration */
	204	u8 loopback_mode;
cd88ccee YR	205	#define LOOPBACK_NONE 0
	206	#define LOOPBACK_EMAC 1
	207	#define LOOPBACK_BMAC 2
de6eae1f	208	#define LOOPBACK_XGXS 3
ea4e040a	209	#define LOOPBACK_EXT_PHY 4
cd88ccee YR	210	#define LOOPBACK_EXT 5
	211	#define LOOPBACK_UMAC 6
	212	#define LOOPBACK_XMAC 7
ea4e040a	213
ea4e040a YR	214	/* Device parameters */
ea4e040a YR	215	u8 mac_addr[6];
8c99e7b0	216
a22f0788 YR	217	u16 req_duplex[LINK_CONFIG_SIZE];
	218	u16 req_flow_ctrl[LINK_CONFIG_SIZE];
	219
	220	u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
	221
ea4e040a YR	222	/* shmem parameters */
ea4e040a YR	223	u32 shmem_base;
a22f0788 YR	224	u32 shmem2_base;
a22f0788 YR	225	u32 speed_cap_mask[LINK_CONFIG_SIZE];
ea4e040a YR	226	u32 switch_cfg;
	227	#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
	228	#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
	229	#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
	230
ea4e040a	231	u32 lane_config;
659bc5c4	232
ea4e040a YR	233	/* Phy register parameter */
	234	u32 chip_id;
	235
cd88ccee	236	/* features */
589abe3a	237	u32 feature_config_flags;
cd88ccee YR	238	#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
	239	#define FEATURE_CONFIG_PFC_ENABLED (1<<1)
	240	#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
a22f0788	241	#define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
e10bc84d YR	242	/* Will be populated during common init */
	243	struct bnx2x_phy phy[MAX_PHYS];
	244
	245	/* Will be populated during common init */
	246	u8 num_phys;
1ef70b9c	247
b7737c9b YR	248	u8 rsrv;
b7737c9b YR	249	u16 hw_led_mode; /* part of the hw_config read from the shmem */
a22f0788	250	u32 multi_phy_config;
b7737c9b	251
ea4e040a YR	252	/* Device pointer passed to all callback functions */
ea4e040a YR	253	struct bnx2x *bp;
a22f0788 YR	254	u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
a22f0788 YR	255	req_flow_ctrl is set to AUTO */
ea4e040a YR	256	};
	257
	258	/* Output parameters */
	259	struct link_vars {
1ef70b9c EG	260	u8 phy_flags;
	261
	262	u8 mac_type;
	263	#define MAC_TYPE_NONE 0
	264	#define MAC_TYPE_EMAC 1
	265	#define MAC_TYPE_BMAC 2
619c5cb6 VZ	266	#define MAC_TYPE_UMAC 3
619c5cb6 VZ	267	#define MAC_TYPE_XMAC 4
1ef70b9c	268
ea4e040a YR	269	u8 phy_link_up; /* internal phy link indication */
ea4e040a YR	270	u8 link_up;
1ef70b9c EG	271
1ef70b9c EG	272	u16 line_speed;
ea4e040a	273	u16 duplex;
1ef70b9c	274
ea4e040a	275	u16 flow_ctrl;
1ef70b9c	276	u16 ieee_fc;
ea4e040a	277
ea4e040a YR	278	/* The same definitions as the shmem parameter */
ea4e040a YR	279	u32 link_status;
c688fe2f YR	280	u8 fault_detected;
	281	u8 rsrv1;
	282	u16 rsrv2;
020c7e3f	283	u32 aeu_int_mask;
ea4e040a YR	284	};
	285
	286	/***********************************************************/
	287	/* Functions */
	288	/***********************************************************/
fcf5b650	289	int bnx2x_phy_init(struct link_params params, struct link_vars vars);
ea4e040a	290
589abe3a EG	291	/* Reset the link. Should be called when driver or interface goes down
	292	Before calling phy firmware upgrade, the reset_ext_phy should be set
	293	to 0 */
fcf5b650 YR	294	int bnx2x_link_reset(struct link_params params, struct link_vars vars,
fcf5b650 YR	295	u8 reset_ext_phy);
ea4e040a YR	296
ea4e040a YR	297	/* bnx2x_link_update should be called upon link interrupt */
fcf5b650	298	int bnx2x_link_update(struct link_params params, struct link_vars vars);
ea4e040a	299
e10bc84d	300	/* use the following phy functions to read/write from external_phy
ea4e040a YR	301	In order to use it to read/write internal phy registers, use
ea4e040a YR	302	DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
ea4e040a	303	the register */
fcf5b650 YR	304	int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
	305	u8 devad, u16 reg, u16 *ret_val);
	306
	307	int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
	308	u8 devad, u16 reg, u16 val);
ea4e040a	309
ea4e040a	310	/* Reads the link_status from the shmem,
33471629	311	and update the link vars accordingly */
ea4e040a YR	312	void bnx2x_link_status_update(struct link_params *input,
	313	struct link_vars *output);
	314	/* returns string representing the fw_version of the external phy */
fcf5b650 YR	315	int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
fcf5b650 YR	316	u8 *version, u16 len);
ea4e040a YR	317
	318	/* Set/Unset the led
	319	Basically, the CLC takes care of the led for the link, but in case one needs
33471629	320	to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
ea4e040a	321	blink the led, and LED_MODE_OFF to set the led off.*/
fcf5b650 YR	322	int bnx2x_set_led(struct link_params *params,
fcf5b650 YR	323	struct link_vars *vars, u8 mode, u32 speed);
7f02c4ad YR	324	#define LED_MODE_OFF 0
	325	#define LED_MODE_ON 1
	326	#define LED_MODE_OPER 2
	327	#define LED_MODE_FRONT_PANEL_OFF 3
ea4e040a	328
589abe3a EG	329	/* bnx2x_handle_module_detect_int should be called upon module detection
	330	interrupt */
	331	void bnx2x_handle_module_detect_int(struct link_params *params);
	332
ea4e040a YR	333	/* Get the actual link status. In case it returns 0, link is up,
ea4e040a YR	334	otherwise link is down*/
fcf5b650 YR	335	int bnx2x_test_link(struct link_params params, struct link_vars vars,
fcf5b650 YR	336	u8 is_serdes);
ea4e040a	337
6bbca910	338	/* One-time initialization for external phy after power up */
fcf5b650 YR	339	int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
fcf5b650 YR	340	u32 shmem2_base_path[], u32 chip_id);
ea4e040a	341
f57a6025 EG	342	/* Reset the external PHY using GPIO */
	343	void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
	344
e10bc84d YR	345	/* Reset the external of SFX7101 */
e10bc84d YR	346	void bnx2x_sfx7101_sp_sw_reset(struct bnx2x bp, struct bnx2x_phy phy);
356e2385	347
65a001ba	348	/* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
fcf5b650 YR	349	int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
	350	struct link_params *params, u16 addr,
	351	u8 byte_cnt, u8 *o_buf);
65a001ba	352
d90d96ba YR	353	void bnx2x_hw_reset_phy(struct link_params *params);
	354
	355	/* Checks if HW lock is required for this phy/board type */
a22f0788 YR	356	u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base,
	357	u32 shmem2_base);
	358
a22f0788 YR	359	/* Check swap bit and adjust PHY order */
	360	u32 bnx2x_phy_selection(struct link_params *params);
	361
e10bc84d	362	/* Probe the phys on board, and populate them in "params" */
fcf5b650 YR	363	int bnx2x_phy_probe(struct link_params *params);
fcf5b650 YR	364
d90d96ba	365	/* Checks if fan failure detection is required on one of the phys on board */
a22f0788 YR	366	u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
a22f0788 YR	367	u32 shmem2_base, u8 port);
d90d96ba	368
619c5cb6 VZ	369	/* DCBX structs */
	370
	371	/* Number of maximum COS per chip */
	372	#define DCBX_E2E3_MAX_NUM_COS (2)
	373	#define DCBX_E3B0_MAX_NUM_COS_PORT0 (6)
	374	#define DCBX_E3B0_MAX_NUM_COS_PORT1 (3)
	375	#define DCBX_E3B0_MAX_NUM_COS ( \
	376	MAXVAL(DCBX_E3B0_MAX_NUM_COS_PORT0, \
	377	DCBX_E3B0_MAX_NUM_COS_PORT1))
	378
	379	#define DCBX_MAX_NUM_COS ( \
	380	MAXVAL(DCBX_E3B0_MAX_NUM_COS, \
	381	DCBX_E2E3_MAX_NUM_COS))
	382
e4901dde VZ	383	/* PFC port configuration params */
	384	struct bnx2x_nig_brb_pfc_port_params {
	385	/* NIG */
	386	u32 pause_enable;
	387	u32 llfc_out_en;
	388	u32 llfc_enable;
	389	u32 pkt_priority_to_cos;
619c5cb6 VZ	390	u8 num_of_rx_cos_priority_mask;
619c5cb6 VZ	391	u32 rx_cos_priority_mask[DCBX_MAX_NUM_COS];
e4901dde VZ	392	u32 llfc_high_priority_classes;
	393	u32 llfc_low_priority_classes;
	394	/* BRB */
	395	u32 cos0_pauseable;
	396	u32 cos1_pauseable;
	397	};
	398
	399	/**
	400	* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
	401	* when link is already up
	402	*/
	403	void bnx2x_update_pfc(struct link_params *params,
	404	struct link_vars *vars,
	405	struct bnx2x_nig_brb_pfc_port_params *pfc_params);
	406
	407
	408	/* Used to configure the ETS to disable */
	409	void bnx2x_ets_disabled(struct link_params *params);
	410
	411	/* Used to configure the ETS to BW limited */
	412	void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
cd88ccee	413	const u32 cos1_bw);
e4901dde VZ	414
e4901dde VZ	415	/* Used to configure the ETS to strict */
fcf5b650	416	int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);
e4901dde VZ	417
	418	/* Read pfc statistic*/
	419	void bnx2x_pfc_statistic(struct link_params params, struct link_vars vars,
	420	u32 pfc_frames_sent[2],
	421	u32 pfc_frames_received[2]);
020c7e3f YR	422	void bnx2x_init_mod_abs_int(struct bnx2x bp, struct link_vars vars,
	423	u32 chip_id, u32 shmem_base, u32 shmem2_base,
	424	u8 port);
ea4e040a	425	#endif /* BNX2X_LINK_H */