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cxgb3: fix mac index mapping
[mirror_ubuntu-bionic-kernel.git] / drivers / net / cxgb3 / cxgb3_main.c
CommitLineData
4d22de3e 1/*
a02d44a0 2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
4d22de3e 3 *
1d68e93d
DLR		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
4d22de3e 9 *
1d68e93d
DLR		 10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
4d22de3e 31 */
4d22de3e
DLR		 32#include <linux/module.h>
33#include <linux/moduleparam.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/dma-mapping.h>
37#include <linux/netdevice.h>
38#include <linux/etherdevice.h>
39#include <linux/if_vlan.h>
0f07c4ee 40#include <linux/mdio.h>
4d22de3e
DLR		 41#include <linux/sockios.h>
42#include <linux/workqueue.h>
43#include <linux/proc_fs.h>
44#include <linux/rtnetlink.h>
2e283962 45#include <linux/firmware.h>
d9da466a 46#include <linux/log2.h>
4d22de3e
DLR		 47#include <asm/uaccess.h>
48
49#include "common.h"
50#include "cxgb3_ioctl.h"
51#include "regs.h"
52#include "cxgb3_offload.h"
53#include "version.h"
54
55#include "cxgb3_ctl_defs.h"
56#include "t3_cpl.h"
57#include "firmware_exports.h"
58
59enum {
60 MAX_TXQ_ENTRIES = 16384,
61 MAX_CTRL_TXQ_ENTRIES = 1024,
62 MAX_RSPQ_ENTRIES = 16384,
63 MAX_RX_BUFFERS = 16384,
64 MAX_RX_JUMBO_BUFFERS = 16384,
65 MIN_TXQ_ENTRIES = 4,
66 MIN_CTRL_TXQ_ENTRIES = 4,
67 MIN_RSPQ_ENTRIES = 32,
68 MIN_FL_ENTRIES = 32
69};
70
71#define PORT_MASK ((1 << MAX_NPORTS) - 1)
72
73#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
74 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
75 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
76
77#define EEPROM_MAGIC 0x38E2F10C
78
678771d6
DLR		 79#define CH_DEVICE(devid, idx) \
80 { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, PCI_ANY_ID, 0, 0, idx }
4d22de3e
DLR		 81
82static const struct pci_device_id cxgb3_pci_tbl[] = {
678771d6
DLR		 83 CH_DEVICE(0x20, 0), /* PE9000 */
84 CH_DEVICE(0x21, 1), /* T302E */
85 CH_DEVICE(0x22, 2), /* T310E */
86 CH_DEVICE(0x23, 3), /* T320X */
87 CH_DEVICE(0x24, 1), /* T302X */
88 CH_DEVICE(0x25, 3), /* T320E */
89 CH_DEVICE(0x26, 2), /* T310X */
90 CH_DEVICE(0x30, 2), /* T3B10 */
91 CH_DEVICE(0x31, 3), /* T3B20 */
92 CH_DEVICE(0x32, 1), /* T3B02 */
ce03aadd 93 CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */
74451424
DLR		 94 CH_DEVICE(0x36, 3), /* S320E-CR */
95 CH_DEVICE(0x37, 7), /* N320E-G2 */
4d22de3e
DLR		 96 {0,}
97};
98
99MODULE_DESCRIPTION(DRV_DESC);
100MODULE_AUTHOR("Chelsio Communications");
1d68e93d 101MODULE_LICENSE("Dual BSD/GPL");
4d22de3e
DLR		 102MODULE_VERSION(DRV_VERSION);
103MODULE_DEVICE_TABLE(pci, cxgb3_pci_tbl);
104
105static int dflt_msg_enable = DFLT_MSG_ENABLE;
106
107module_param(dflt_msg_enable, int, 0644);
108MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T3 default message enable bitmap");
109
110/*
111 * The driver uses the best interrupt scheme available on a platform in the
112 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
113 * of these schemes the driver may consider as follows:
114 *
115 * msi = 2: choose from among all three options
116 * msi = 1: only consider MSI and pin interrupts
117 * msi = 0: force pin interrupts
118 */
119static int msi = 2;
120
121module_param(msi, int, 0644);
122MODULE_PARM_DESC(msi, "whether to use MSI or MSI-X");
123
124/*
125 * The driver enables offload as a default.
126 * To disable it, use ofld_disable = 1.
127 */
128
129static int ofld_disable = 0;
130
131module_param(ofld_disable, int, 0644);
132MODULE_PARM_DESC(ofld_disable, "whether to enable offload at init time or not");
133
134/*
135 * We have work elements that we need to cancel when an interface is taken
136 * down. Normally the work elements would be executed by keventd but that
137 * can deadlock because of linkwatch. If our close method takes the rtnl
138 * lock and linkwatch is ahead of our work elements in keventd, linkwatch
139 * will block keventd as it needs the rtnl lock, and we'll deadlock waiting
140 * for our work to complete. Get our own work queue to solve this.
141 */
142static struct workqueue_struct *cxgb3_wq;
143
144/**
145 * link_report - show link status and link speed/duplex
146 * @p: the port whose settings are to be reported
147 *
148 * Shows the link status, speed, and duplex of a port.
149 */
150static void link_report(struct net_device *dev)
151{
152 if (!netif_carrier_ok(dev))
153 printk(KERN_INFO "%s: link down\n", dev->name);
154 else {
155 const char *s = "10Mbps";
156 const struct port_info *p = netdev_priv(dev);
157
158 switch (p->link_config.speed) {
159 case SPEED_10000:
160 s = "10Gbps";
161 break;
162 case SPEED_1000:
163 s = "1000Mbps";
164 break;
165 case SPEED_100:
166 s = "100Mbps";
167 break;
168 }
169
170 printk(KERN_INFO "%s: link up, %s, %s-duplex\n", dev->name, s,
171 p->link_config.duplex == DUPLEX_FULL ? "full" : "half");
172 }
173}
174
bf792094
DLR		 175void t3_os_link_fault(struct adapter *adap, int port_id, int state)
176{
177 struct net_device *dev = adap->port[port_id];
178 struct port_info *pi = netdev_priv(dev);
179
180 if (state == netif_carrier_ok(dev))
181 return;
182
183 if (state) {
184 struct cmac *mac = &pi->mac;
185
186 netif_carrier_on(dev);
187
188 /* Clear local faults */
189 t3_xgm_intr_disable(adap, pi->port_id);
190 t3_read_reg(adap, A_XGM_INT_STATUS +
191 pi->mac.offset);
192 t3_write_reg(adap,
193 A_XGM_INT_CAUSE + pi->mac.offset,
194 F_XGM_INT);
195
196 t3_set_reg_field(adap,
197 A_XGM_INT_ENABLE +
198 pi->mac.offset,
199 F_XGM_INT, F_XGM_INT);
200 t3_xgm_intr_enable(adap, pi->port_id);
201
202 t3_mac_enable(mac, MAC_DIRECTION_TX);
203 } else
204 netif_carrier_off(dev);
205
206 link_report(dev);
207}
208
4d22de3e
DLR		 209/**
210 * t3_os_link_changed - handle link status changes
211 * @adapter: the adapter associated with the link change
212 * @port_id: the port index whose limk status has changed
213 * @link_stat: the new status of the link
214 * @speed: the new speed setting
215 * @duplex: the new duplex setting
216 * @pause: the new flow-control setting
217 *
218 * This is the OS-dependent handler for link status changes. The OS
219 * neutral handler takes care of most of the processing for these events,
220 * then calls this handler for any OS-specific processing.
221 */
222void t3_os_link_changed(struct adapter *adapter, int port_id, int link_stat,
223 int speed, int duplex, int pause)
224{
225 struct net_device *dev = adapter->port[port_id];
6d6dabac
DLR		 226 struct port_info *pi = netdev_priv(dev);
227 struct cmac *mac = &pi->mac;
4d22de3e
DLR		 228
229 /* Skip changes from disabled ports. */
230 if (!netif_running(dev))
231 return;
232
233 if (link_stat != netif_carrier_ok(dev)) {
6d6dabac 234 if (link_stat) {
59cf8107 235 t3_mac_enable(mac, MAC_DIRECTION_RX);
bf792094
DLR		 236
237 /* Clear local faults */
238 t3_xgm_intr_disable(adapter, pi->port_id);
239 t3_read_reg(adapter, A_XGM_INT_STATUS +
240 pi->mac.offset);
241 t3_write_reg(adapter,
242 A_XGM_INT_CAUSE + pi->mac.offset,
243 F_XGM_INT);
244
245 t3_set_reg_field(adapter,
246 A_XGM_INT_ENABLE + pi->mac.offset,
247 F_XGM_INT, F_XGM_INT);
248 t3_xgm_intr_enable(adapter, pi->port_id);
249
4d22de3e 250 netif_carrier_on(dev);
6d6dabac 251 } else {
4d22de3e 252 netif_carrier_off(dev);
bf792094
DLR		 253
254 t3_xgm_intr_disable(adapter, pi->port_id);
255 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
256 t3_set_reg_field(adapter,
257 A_XGM_INT_ENABLE + pi->mac.offset,
258 F_XGM_INT, 0);
259
260 if (is_10G(adapter))
261 pi->phy.ops->power_down(&pi->phy, 1);
262
263 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
59cf8107
DLR		 264 t3_mac_disable(mac, MAC_DIRECTION_RX);
265 t3_link_start(&pi->phy, mac, &pi->link_config);
6d6dabac
DLR		 266 }
267
4d22de3e
DLR		 268 link_report(dev);
269 }
270}
271
1e882025
DLR		 272/**
273 * t3_os_phymod_changed - handle PHY module changes
274 * @phy: the PHY reporting the module change
275 * @mod_type: new module type
276 *
277 * This is the OS-dependent handler for PHY module changes. It is
278 * invoked when a PHY module is removed or inserted for any OS-specific
279 * processing.
280 */
281void t3_os_phymod_changed(struct adapter *adap, int port_id)
282{
283 static const char *mod_str[] = {
284 NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX", "unknown"
285 };
286
287 const struct net_device *dev = adap->port[port_id];
288 const struct port_info *pi = netdev_priv(dev);
289
290 if (pi->phy.modtype == phy_modtype_none)
291 printk(KERN_INFO "%s: PHY module unplugged\n", dev->name);
292 else
293 printk(KERN_INFO "%s: %s PHY module inserted\n", dev->name,
294 mod_str[pi->phy.modtype]);
295}
296
4d22de3e
DLR		 297static void cxgb_set_rxmode(struct net_device *dev)
298{
299 struct t3_rx_mode rm;
300 struct port_info *pi = netdev_priv(dev);
301
302 init_rx_mode(&rm, dev, dev->mc_list);
303 t3_mac_set_rx_mode(&pi->mac, &rm);
304}
305
306/**
307 * link_start - enable a port
308 * @dev: the device to enable
309 *
310 * Performs the MAC and PHY actions needed to enable a port.
311 */
312static void link_start(struct net_device *dev)
313{
314 struct t3_rx_mode rm;
315 struct port_info *pi = netdev_priv(dev);
316 struct cmac *mac = &pi->mac;
317
318 init_rx_mode(&rm, dev, dev->mc_list);
319 t3_mac_reset(mac);
320 t3_mac_set_mtu(mac, dev->mtu);
321 t3_mac_set_address(mac, 0, dev->dev_addr);
322 t3_mac_set_rx_mode(mac, &rm);
323 t3_link_start(&pi->phy, mac, &pi->link_config);
324 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
325}
326
327static inline void cxgb_disable_msi(struct adapter *adapter)
328{
329 if (adapter->flags & USING_MSIX) {
330 pci_disable_msix(adapter->pdev);
331 adapter->flags &= ~USING_MSIX;
332 } else if (adapter->flags & USING_MSI) {
333 pci_disable_msi(adapter->pdev);
334 adapter->flags &= ~USING_MSI;
335 }
336}
337
338/*
339 * Interrupt handler for asynchronous events used with MSI-X.
340 */
341static irqreturn_t t3_async_intr_handler(int irq, void *cookie)
342{
343 t3_slow_intr_handler(cookie);
344 return IRQ_HANDLED;
345}
346
347/*
348 * Name the MSI-X interrupts.
349 */
350static void name_msix_vecs(struct adapter *adap)
351{
352 int i, j, msi_idx = 1, n = sizeof(adap->msix_info[0].desc) - 1;
353
354 snprintf(adap->msix_info[0].desc, n, "%s", adap->name);
355 adap->msix_info[0].desc[n] = 0;
356
357 for_each_port(adap, j) {
358 struct net_device *d = adap->port[j];
359 const struct port_info *pi = netdev_priv(d);
360
361 for (i = 0; i < pi->nqsets; i++, msi_idx++) {
362 snprintf(adap->msix_info[msi_idx].desc, n,
8c263761 363 "%s-%d", d->name, pi->first_qset + i);
4d22de3e
DLR		 364 adap->msix_info[msi_idx].desc[n] = 0;
365 }
8c263761 366 }
4d22de3e
DLR		 367}
368
369static int request_msix_data_irqs(struct adapter *adap)
370{
371 int i, j, err, qidx = 0;
372
373 for_each_port(adap, i) {
374 int nqsets = adap2pinfo(adap, i)->nqsets;
375
376 for (j = 0; j < nqsets; ++j) {
377 err = request_irq(adap->msix_info[qidx + 1].vec,
378 t3_intr_handler(adap,
379 adap->sge.qs[qidx].
380 rspq.polling), 0,
381 adap->msix_info[qidx + 1].desc,
382 &adap->sge.qs[qidx]);
383 if (err) {
384 while (--qidx >= 0)
385 free_irq(adap->msix_info[qidx + 1].vec,
386 &adap->sge.qs[qidx]);
387 return err;
388 }
389 qidx++;
390 }
391 }
392 return 0;
393}
394
8c263761
DLR		 395static void free_irq_resources(struct adapter *adapter)
396{
397 if (adapter->flags & USING_MSIX) {
398 int i, n = 0;
399
400 free_irq(adapter->msix_info[0].vec, adapter);
401 for_each_port(adapter, i)
5cda9364 402 n += adap2pinfo(adapter, i)->nqsets;
8c263761
DLR		 403
404 for (i = 0; i < n; ++i)
405 free_irq(adapter->msix_info[i + 1].vec,
406 &adapter->sge.qs[i]);
407 } else
408 free_irq(adapter->pdev->irq, adapter);
409}
410
b881955b
DLR		 411static int await_mgmt_replies(struct adapter *adap, unsigned long init_cnt,
412 unsigned long n)
413{
414 int attempts = 5;
415
416 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) {
417 if (!--attempts)
418 return -ETIMEDOUT;
419 msleep(10);
420 }
421 return 0;
422}
423
424static int init_tp_parity(struct adapter *adap)
425{
426 int i;
427 struct sk_buff *skb;
428 struct cpl_set_tcb_field *greq;
429 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts;
430
431 t3_tp_set_offload_mode(adap, 1);
432
433 for (i = 0; i < 16; i++) {
434 struct cpl_smt_write_req *req;
435
74b793e1
DLR		 436 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
437 if (!skb)
438 skb = adap->nofail_skb;
439 if (!skb)
440 goto alloc_skb_fail;
441
b881955b
DLR		 442 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req));
443 memset(req, 0, sizeof(*req));
444 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
445 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i));
dce7d1d0 446 req->mtu_idx = NMTUS - 1;
b881955b
DLR		 447 req->iff = i;
448 t3_mgmt_tx(adap, skb);
74b793e1
DLR		 449 if (skb == adap->nofail_skb) {
450 await_mgmt_replies(adap, cnt, i + 1);
451 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
452 if (!adap->nofail_skb)
453 goto alloc_skb_fail;
454 }
b881955b
DLR		 455 }
456
457 for (i = 0; i < 2048; i++) {
458 struct cpl_l2t_write_req *req;
459
74b793e1
DLR		 460 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
461 if (!skb)
462 skb = adap->nofail_skb;
463 if (!skb)
464 goto alloc_skb_fail;
465
b881955b
DLR		 466 req = (struct cpl_l2t_write_req *)__skb_put(skb, sizeof(*req));
467 memset(req, 0, sizeof(*req));
468 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
469 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i));
470 req->params = htonl(V_L2T_W_IDX(i));
471 t3_mgmt_tx(adap, skb);
74b793e1
DLR		 472 if (skb == adap->nofail_skb) {
473 await_mgmt_replies(adap, cnt, 16 + i + 1);
474 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
475 if (!adap->nofail_skb)
476 goto alloc_skb_fail;
477 }
b881955b
DLR		 478 }
479
480 for (i = 0; i < 2048; i++) {
481 struct cpl_rte_write_req *req;
482
74b793e1
DLR		 483 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
484 if (!skb)
485 skb = adap->nofail_skb;
486 if (!skb)
487 goto alloc_skb_fail;
488
b881955b
DLR		 489 req = (struct cpl_rte_write_req *)__skb_put(skb, sizeof(*req));
490 memset(req, 0, sizeof(*req));
491 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
492 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i));
493 req->l2t_idx = htonl(V_L2T_W_IDX(i));
494 t3_mgmt_tx(adap, skb);
74b793e1
DLR		 495 if (skb == adap->nofail_skb) {
496 await_mgmt_replies(adap, cnt, 16 + 2048 + i + 1);
497 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
498 if (!adap->nofail_skb)
499 goto alloc_skb_fail;
500 }
b881955b
DLR		 501 }
502
74b793e1
DLR		 503 skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
504 if (!skb)
505 skb = adap->nofail_skb;
506 if (!skb)
507 goto alloc_skb_fail;
508
b881955b
DLR		 509 greq = (struct cpl_set_tcb_field *)__skb_put(skb, sizeof(*greq));
510 memset(greq, 0, sizeof(*greq));
511 greq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
512 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0));
513 greq->mask = cpu_to_be64(1);
514 t3_mgmt_tx(adap, skb);
515
516 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
74b793e1
DLR		 517 if (skb == adap->nofail_skb) {
518 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
519 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
520 }
521
b881955b
DLR		 522 t3_tp_set_offload_mode(adap, 0);
523 return i;
74b793e1
DLR		 524
525alloc_skb_fail:
526 t3_tp_set_offload_mode(adap, 0);
527 return -ENOMEM;
b881955b
DLR		 528}
529
4d22de3e
DLR		 530/**
531 * setup_rss - configure RSS
532 * @adap: the adapter
533 *
534 * Sets up RSS to distribute packets to multiple receive queues. We
535 * configure the RSS CPU lookup table to distribute to the number of HW
536 * receive queues, and the response queue lookup table to narrow that
537 * down to the response queues actually configured for each port.
538 * We always configure the RSS mapping for two ports since the mapping
539 * table has plenty of entries.
540 */
541static void setup_rss(struct adapter *adap)
542{
543 int i;
544 unsigned int nq0 = adap2pinfo(adap, 0)->nqsets;
545 unsigned int nq1 = adap->port[1] ? adap2pinfo(adap, 1)->nqsets : 1;
546 u8 cpus[SGE_QSETS + 1];
547 u16 rspq_map[RSS_TABLE_SIZE];
548
549 for (i = 0; i < SGE_QSETS; ++i)
550 cpus[i] = i;
551 cpus[SGE_QSETS] = 0xff; /* terminator */
552
553 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) {
554 rspq_map[i] = i % nq0;
555 rspq_map[i + RSS_TABLE_SIZE / 2] = (i % nq1) + nq0;
556 }
557
558 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN |
559 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN |
a2604be5 560 V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, cpus, rspq_map);
4d22de3e
DLR		 561}
562
bea3348e 563static void init_napi(struct adapter *adap)
4d22de3e 564{
bea3348e 565 int i;
4d22de3e 566
bea3348e
SH		 567 for (i = 0; i < SGE_QSETS; i++) {
568 struct sge_qset *qs = &adap->sge.qs[i];
4d22de3e 569
bea3348e
SH		 570 if (qs->adap)
571 netif_napi_add(qs->netdev, &qs->napi, qs->napi.poll,
572 64);
4d22de3e 573 }
48c4b6db
DLR		 574
575 /*
576 * netif_napi_add() can be called only once per napi_struct because it
577 * adds each new napi_struct to a list. Be careful not to call it a
578 * second time, e.g., during EEH recovery, by making a note of it.
579 */
580 adap->flags |= NAPI_INIT;
4d22de3e
DLR		 581}
582
583/*
584 * Wait until all NAPI handlers are descheduled. This includes the handlers of
585 * both netdevices representing interfaces and the dummy ones for the extra
586 * queues.
587 */
588static void quiesce_rx(struct adapter *adap)
589{
590 int i;
4d22de3e 591
bea3348e
SH		 592 for (i = 0; i < SGE_QSETS; i++)
593 if (adap->sge.qs[i].adap)
594 napi_disable(&adap->sge.qs[i].napi);
595}
4d22de3e 596
bea3348e
SH		 597static void enable_all_napi(struct adapter *adap)
598{
599 int i;
600 for (i = 0; i < SGE_QSETS; i++)
601 if (adap->sge.qs[i].adap)
602 napi_enable(&adap->sge.qs[i].napi);
4d22de3e
DLR		 603}
604
04ecb072
DLR		 605/**
606 * set_qset_lro - Turn a queue set's LRO capability on and off
607 * @dev: the device the qset is attached to
608 * @qset_idx: the queue set index
609 * @val: the LRO switch
610 *
611 * Sets LRO on or off for a particular queue set.
612 * the device's features flag is updated to reflect the LRO
613 * capability when all queues belonging to the device are
614 * in the same state.
615 */
616static void set_qset_lro(struct net_device *dev, int qset_idx, int val)
617{
618 struct port_info *pi = netdev_priv(dev);
619 struct adapter *adapter = pi->adapter;
04ecb072
DLR		 620
621 adapter->params.sge.qset[qset_idx].lro = !!val;
622 adapter->sge.qs[qset_idx].lro_enabled = !!val;
04ecb072
DLR		 623}
624
4d22de3e
DLR		 625/**
626 * setup_sge_qsets - configure SGE Tx/Rx/response queues
627 * @adap: the adapter
628 *
629 * Determines how many sets of SGE queues to use and initializes them.
630 * We support multiple queue sets per port if we have MSI-X, otherwise
631 * just one queue set per port.
632 */
633static int setup_sge_qsets(struct adapter *adap)
634{
bea3348e 635 int i, j, err, irq_idx = 0, qset_idx = 0;
8ac3ba68 636 unsigned int ntxq = SGE_TXQ_PER_SET;
4d22de3e
DLR		 637
638 if (adap->params.rev > 0 && !(adap->flags & USING_MSI))
639 irq_idx = -1;
640
641 for_each_port(adap, i) {
642 struct net_device *dev = adap->port[i];
bea3348e 643 struct port_info *pi = netdev_priv(dev);
4d22de3e 644
bea3348e 645 pi->qs = &adap->sge.qs[pi->first_qset];
8c263761
DLR		 646 for (j = pi->first_qset; j < pi->first_qset + pi->nqsets;
647 ++j, ++qset_idx) {
47fd23fe 648 set_qset_lro(dev, qset_idx, pi->rx_offload & T3_LRO);
4d22de3e
DLR		 649 err = t3_sge_alloc_qset(adap, qset_idx, 1,
650 (adap->flags & USING_MSIX) ? qset_idx + 1 :
651 irq_idx,
82ad3329
DLR		 652 &adap->params.sge.qset[qset_idx], ntxq, dev,
653 netdev_get_tx_queue(dev, j));
4d22de3e
DLR		 654 if (err) {
655 t3_free_sge_resources(adap);
656 return err;
657 }
658 }
659 }
660
661 return 0;
662}
663
3e5192ee 664static ssize_t attr_show(struct device *d, char *buf,
896392ef 665 ssize_t(*format) (struct net_device *, char *))
4d22de3e
DLR		 666{
667 ssize_t len;
4d22de3e
DLR		 668
669 /* Synchronize with ioctls that may shut down the device */
670 rtnl_lock();
896392ef 671 len = (*format) (to_net_dev(d), buf);
4d22de3e
DLR		 672 rtnl_unlock();
673 return len;
674}
675
3e5192ee 676static ssize_t attr_store(struct device *d,
0ee8d33c 677 const char *buf, size_t len,
896392ef 678 ssize_t(*set) (struct net_device *, unsigned int),
4d22de3e
DLR		 679 unsigned int min_val, unsigned int max_val)
680{
681 char *endp;
682 ssize_t ret;
683 unsigned int val;
4d22de3e
DLR		 684
685 if (!capable(CAP_NET_ADMIN))
686 return -EPERM;
687
688 val = simple_strtoul(buf, &endp, 0);
689 if (endp == buf || val < min_val || val > max_val)
690 return -EINVAL;
691
692 rtnl_lock();
896392ef 693 ret = (*set) (to_net_dev(d), val);
4d22de3e
DLR		 694 if (!ret)
695 ret = len;
696 rtnl_unlock();
697 return ret;
698}
699
700#define CXGB3_SHOW(name, val_expr) \
896392ef 701static ssize_t format_##name(struct net_device *dev, char *buf) \
4d22de3e 702{ \
5fbf816f
DLR		 703 struct port_info *pi = netdev_priv(dev); \
704 struct adapter *adap = pi->adapter; \
4d22de3e
DLR		 705 return sprintf(buf, "%u\n", val_expr); \
706} \
0ee8d33c
DLR		 707static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
708 char *buf) \
4d22de3e 709{ \
3e5192ee 710 return attr_show(d, buf, format_##name); \
4d22de3e
DLR		 711}
712
896392ef 713static ssize_t set_nfilters(struct net_device *dev, unsigned int val)
4d22de3e 714{
5fbf816f
DLR		 715 struct port_info *pi = netdev_priv(dev);
716 struct adapter *adap = pi->adapter;
9f238486 717 int min_tids = is_offload(adap) ? MC5_MIN_TIDS : 0;
896392ef 718
4d22de3e
DLR		 719 if (adap->flags & FULL_INIT_DONE)
720 return -EBUSY;
721 if (val && adap->params.rev == 0)
722 return -EINVAL;
9f238486
DLR		 723 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers -
724 min_tids)
4d22de3e
DLR		 725 return -EINVAL;
726 adap->params.mc5.nfilters = val;
727 return 0;
728}
729
0ee8d33c
DLR		 730static ssize_t store_nfilters(struct device *d, struct device_attribute *attr,
731 const char *buf, size_t len)
4d22de3e 732{
3e5192ee 733 return attr_store(d, buf, len, set_nfilters, 0, ~0);
4d22de3e
DLR		 734}
735
896392ef 736static ssize_t set_nservers(struct net_device *dev, unsigned int val)
4d22de3e 737{
5fbf816f
DLR		 738 struct port_info *pi = netdev_priv(dev);
739 struct adapter *adap = pi->adapter;
896392ef 740
4d22de3e
DLR		 741 if (adap->flags & FULL_INIT_DONE)
742 return -EBUSY;
9f238486
DLR		 743 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nfilters -
744 MC5_MIN_TIDS)
4d22de3e
DLR		 745 return -EINVAL;
746 adap->params.mc5.nservers = val;
747 return 0;
748}
749
0ee8d33c
DLR		 750static ssize_t store_nservers(struct device *d, struct device_attribute *attr,
751 const char *buf, size_t len)
4d22de3e 752{
3e5192ee 753 return attr_store(d, buf, len, set_nservers, 0, ~0);
4d22de3e
DLR		 754}
755
756#define CXGB3_ATTR_R(name, val_expr) \
757CXGB3_SHOW(name, val_expr) \
0ee8d33c 758static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL)
4d22de3e
DLR		 759
760#define CXGB3_ATTR_RW(name, val_expr, store_method) \
761CXGB3_SHOW(name, val_expr) \
0ee8d33c 762static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_method)
4d22de3e
DLR		 763
764CXGB3_ATTR_R(cam_size, t3_mc5_size(&adap->mc5));
765CXGB3_ATTR_RW(nfilters, adap->params.mc5.nfilters, store_nfilters);
766CXGB3_ATTR_RW(nservers, adap->params.mc5.nservers, store_nservers);
767
768static struct attribute *cxgb3_attrs[] = {
0ee8d33c
DLR		 769 &dev_attr_cam_size.attr,
770 &dev_attr_nfilters.attr,
771 &dev_attr_nservers.attr,
4d22de3e
DLR		 772 NULL
773};
774
775static struct attribute_group cxgb3_attr_group = {.attrs = cxgb3_attrs };
776
3e5192ee 777static ssize_t tm_attr_show(struct device *d,
0ee8d33c 778 char *buf, int sched)
4d22de3e 779{
5fbf816f
DLR		 780 struct port_info *pi = netdev_priv(to_net_dev(d));
781 struct adapter *adap = pi->adapter;
4d22de3e 782 unsigned int v, addr, bpt, cpt;
5fbf816f 783 ssize_t len;
4d22de3e
DLR		 784
785 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
786 rtnl_lock();
787 t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
788 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
789 if (sched & 1)
790 v >>= 16;
791 bpt = (v >> 8) & 0xff;
792 cpt = v & 0xff;
793 if (!cpt)
794 len = sprintf(buf, "disabled\n");
795 else {
796 v = (adap->params.vpd.cclk * 1000) / cpt;
797 len = sprintf(buf, "%u Kbps\n", (v * bpt) / 125);
798 }
799 rtnl_unlock();
800 return len;
801}
802
3e5192ee 803static ssize_t tm_attr_store(struct device *d,
0ee8d33c 804 const char *buf, size_t len, int sched)
4d22de3e 805{
5fbf816f
DLR		 806 struct port_info *pi = netdev_priv(to_net_dev(d));
807 struct adapter *adap = pi->adapter;
808 unsigned int val;
4d22de3e
DLR		 809 char *endp;
810 ssize_t ret;
4d22de3e
DLR		 811
812 if (!capable(CAP_NET_ADMIN))
813 return -EPERM;
814
815 val = simple_strtoul(buf, &endp, 0);
816 if (endp == buf || val > 10000000)
817 return -EINVAL;
818
819 rtnl_lock();
820 ret = t3_config_sched(adap, val, sched);
821 if (!ret)
822 ret = len;
823 rtnl_unlock();
824 return ret;
825}
826
827#define TM_ATTR(name, sched) \
0ee8d33c
DLR		 828static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
829 char *buf) \
4d22de3e 830{ \
3e5192ee 831 return tm_attr_show(d, buf, sched); \
4d22de3e 832} \
0ee8d33c
DLR		 833static ssize_t store_##name(struct device *d, struct device_attribute *attr, \
834 const char *buf, size_t len) \
4d22de3e 835{ \
3e5192ee 836 return tm_attr_store(d, buf, len, sched); \
4d22de3e 837} \
0ee8d33c 838static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_##name)
4d22de3e
DLR		 839
840TM_ATTR(sched0, 0);
841TM_ATTR(sched1, 1);
842TM_ATTR(sched2, 2);
843TM_ATTR(sched3, 3);
844TM_ATTR(sched4, 4);
845TM_ATTR(sched5, 5);
846TM_ATTR(sched6, 6);
847TM_ATTR(sched7, 7);
848
849static struct attribute *offload_attrs[] = {
0ee8d33c
DLR		 850 &dev_attr_sched0.attr,
851 &dev_attr_sched1.attr,
852 &dev_attr_sched2.attr,
853 &dev_attr_sched3.attr,
854 &dev_attr_sched4.attr,
855 &dev_attr_sched5.attr,
856 &dev_attr_sched6.attr,
857 &dev_attr_sched7.attr,
4d22de3e
DLR		 858 NULL
859};
860
861static struct attribute_group offload_attr_group = {.attrs = offload_attrs };
862
863/*
864 * Sends an sk_buff to an offload queue driver
865 * after dealing with any active network taps.
866 */
867static inline int offload_tx(struct t3cdev *tdev, struct sk_buff *skb)
868{
869 int ret;
870
871 local_bh_disable();
872 ret = t3_offload_tx(tdev, skb);
873 local_bh_enable();
874 return ret;
875}
876
877static int write_smt_entry(struct adapter *adapter, int idx)
878{
879 struct cpl_smt_write_req *req;
880 struct sk_buff *skb = alloc_skb(sizeof(*req), GFP_KERNEL);
881
882 if (!skb)
883 return -ENOMEM;
884
885 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req));
886 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
887 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx));
888 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */
889 req->iff = idx;
890 memset(req->src_mac1, 0, sizeof(req->src_mac1));
891 memcpy(req->src_mac0, adapter->port[idx]->dev_addr, ETH_ALEN);
892 skb->priority = 1;
893 offload_tx(&adapter->tdev, skb);
894 return 0;
895}
896
897static int init_smt(struct adapter *adapter)
898{
899 int i;
900
901 for_each_port(adapter, i)
902 write_smt_entry(adapter, i);
903 return 0;
904}
905
906static void init_port_mtus(struct adapter *adapter)
907{
908 unsigned int mtus = adapter->port[0]->mtu;
909
910 if (adapter->port[1])
911 mtus |= adapter->port[1]->mtu << 16;
912 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus);
913}
914
8c263761 915static int send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo,
14ab9892
DLR		 916 int hi, int port)
917{
918 struct sk_buff *skb;
919 struct mngt_pktsched_wr *req;
8c263761 920 int ret;
14ab9892 921
74b793e1
DLR		 922 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
923 if (!skb)
924 skb = adap->nofail_skb;
925 if (!skb)
926 return -ENOMEM;
927
14ab9892
DLR		 928 req = (struct mngt_pktsched_wr *)skb_put(skb, sizeof(*req));
929 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT));
930 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET;
931 req->sched = sched;
932 req->idx = qidx;
933 req->min = lo;
934 req->max = hi;
935 req->binding = port;
8c263761 936 ret = t3_mgmt_tx(adap, skb);
74b793e1
DLR		 937 if (skb == adap->nofail_skb) {
938 adap->nofail_skb = alloc_skb(sizeof(struct cpl_set_tcb_field),
939 GFP_KERNEL);
940 if (!adap->nofail_skb)
941 ret = -ENOMEM;
942 }
8c263761
DLR		 943
944 return ret;
14ab9892
DLR		 945}
946
8c263761 947static int bind_qsets(struct adapter *adap)
14ab9892 948{
8c263761 949 int i, j, err = 0;
14ab9892
DLR		 950
951 for_each_port(adap, i) {
952 const struct port_info *pi = adap2pinfo(adap, i);
953
8c263761
DLR		 954 for (j = 0; j < pi->nqsets; ++j) {
955 int ret = send_pktsched_cmd(adap, 1,
956 pi->first_qset + j, -1,
957 -1, i);
958 if (ret)
959 err = ret;
960 }
14ab9892 961 }
8c263761
DLR		 962
963 return err;
14ab9892
DLR		 964}
965
851fd7bd
DLR		 966#define FW_FNAME "cxgb3/t3fw-%d.%d.%d.bin"
967#define TPSRAM_NAME "cxgb3/t3%c_psram-%d.%d.%d.bin"
2e8c07c3
DLR		 968#define AEL2005_OPT_EDC_NAME "cxgb3/ael2005_opt_edc.bin"
969#define AEL2005_TWX_EDC_NAME "cxgb3/ael2005_twx_edc.bin"
970#define AEL2020_TWX_EDC_NAME "cxgb3/ael2005_twx_edc.bin"
971
972static inline const char *get_edc_fw_name(int edc_idx)
973{
974 const char *fw_name = NULL;
975
976 switch (edc_idx) {
977 case EDC_OPT_AEL2005:
978 fw_name = AEL2005_OPT_EDC_NAME;
979 break;
980 case EDC_TWX_AEL2005:
981 fw_name = AEL2005_TWX_EDC_NAME;
982 break;
983 case EDC_TWX_AEL2020:
984 fw_name = AEL2020_TWX_EDC_NAME;
985 break;
986 }
987 return fw_name;
988}
989
990int t3_get_edc_fw(struct cphy *phy, int edc_idx, int size)
991{
992 struct adapter *adapter = phy->adapter;
993 const struct firmware *fw;
994 char buf[64];
995 u32 csum;
996 const __be32 *p;
997 u16 *cache = phy->phy_cache;
998 int i, ret;
999
1000 snprintf(buf, sizeof(buf), get_edc_fw_name(edc_idx));
1001
1002 ret = request_firmware(&fw, buf, &adapter->pdev->dev);
1003 if (ret < 0) {
1004 dev_err(&adapter->pdev->dev,
1005 "could not upgrade firmware: unable to load %s\n",
1006 buf);
1007 return ret;
1008 }
1009
1010 /* check size, take checksum in account */
1011 if (fw->size > size + 4) {
1012 CH_ERR(adapter, "firmware image too large %u, expected %d\n",
1013 (unsigned int)fw->size, size + 4);
1014 ret = -EINVAL;
1015 }
1016
1017 /* compute checksum */
1018 p = (const __be32 *)fw->data;
1019 for (csum = 0, i = 0; i < fw->size / sizeof(csum); i++)
1020 csum += ntohl(p[i]);
1021
1022 if (csum != 0xffffffff) {
1023 CH_ERR(adapter, "corrupted firmware image, checksum %u\n",
1024 csum);
1025 ret = -EINVAL;
1026 }
1027
1028 for (i = 0; i < size / 4 ; i++) {
1029 *cache++ = (be32_to_cpu(p[i]) & 0xffff0000) >> 16;
1030 *cache++ = be32_to_cpu(p[i]) & 0xffff;
1031 }
1032
1033 release_firmware(fw);
1034
1035 return ret;
1036}
2e283962
DLR		 1037
1038static int upgrade_fw(struct adapter *adap)
1039{
1040 int ret;
1041 char buf[64];
1042 const struct firmware *fw;
1043 struct device *dev = &adap->pdev->dev;
1044
1045 snprintf(buf, sizeof(buf), FW_FNAME, FW_VERSION_MAJOR,
7f672cf5 1046 FW_VERSION_MINOR, FW_VERSION_MICRO);
2e283962
DLR		 1047 ret = request_firmware(&fw, buf, dev);
1048 if (ret < 0) {
1049 dev_err(dev, "could not upgrade firmware: unable to load %s\n",
1050 buf);
1051 return ret;
1052 }
1053 ret = t3_load_fw(adap, fw->data, fw->size);
1054 release_firmware(fw);
47330077
DLR		 1055
1056 if (ret == 0)
1057 dev_info(dev, "successful upgrade to firmware %d.%d.%d\n",
1058 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
1059 else
1060 dev_err(dev, "failed to upgrade to firmware %d.%d.%d\n",
1061 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
2eab17ab 1062
47330077
DLR		 1063 return ret;
1064}
1065
1066static inline char t3rev2char(struct adapter *adapter)
1067{
1068 char rev = 0;
1069
1070 switch(adapter->params.rev) {
1071 case T3_REV_B:
1072 case T3_REV_B2:
1073 rev = 'b';
1074 break;
1aafee26
DLR		 1075 case T3_REV_C:
1076 rev = 'c';
1077 break;
47330077
DLR		 1078 }
1079 return rev;
1080}
1081
9265fabf 1082static int update_tpsram(struct adapter *adap)
47330077
DLR		 1083{
1084 const struct firmware *tpsram;
1085 char buf[64];
1086 struct device *dev = &adap->pdev->dev;
1087 int ret;
1088 char rev;
2eab17ab 1089
47330077
DLR		 1090 rev = t3rev2char(adap);
1091 if (!rev)
1092 return 0;
1093
1094 snprintf(buf, sizeof(buf), TPSRAM_NAME, rev,
1095 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1096
1097 ret = request_firmware(&tpsram, buf, dev);
1098 if (ret < 0) {
1099 dev_err(dev, "could not load TP SRAM: unable to load %s\n",
1100 buf);
1101 return ret;
1102 }
2eab17ab 1103
47330077
DLR		 1104 ret = t3_check_tpsram(adap, tpsram->data, tpsram->size);
1105 if (ret)
2eab17ab 1106 goto release_tpsram;
47330077
DLR		 1107
1108 ret = t3_set_proto_sram(adap, tpsram->data);
1109 if (ret == 0)
1110 dev_info(dev,
1111 "successful update of protocol engine "
1112 "to %d.%d.%d\n",
1113 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1114 else
1115 dev_err(dev, "failed to update of protocol engine %d.%d.%d\n",
1116 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1117 if (ret)
1118 dev_err(dev, "loading protocol SRAM failed\n");
1119
1120release_tpsram:
1121 release_firmware(tpsram);
2eab17ab 1122
2e283962
DLR		 1123 return ret;
1124}
1125
4d22de3e
DLR		 1126/**
1127 * cxgb_up - enable the adapter
1128 * @adapter: adapter being enabled
1129 *
1130 * Called when the first port is enabled, this function performs the
1131 * actions necessary to make an adapter operational, such as completing
1132 * the initialization of HW modules, and enabling interrupts.
1133 *
1134 * Must be called with the rtnl lock held.
1135 */
1136static int cxgb_up(struct adapter *adap)
1137{
c54f5c24 1138 int err;
4d22de3e
DLR		 1139
1140 if (!(adap->flags & FULL_INIT_DONE)) {
8207befa 1141 err = t3_check_fw_version(adap);
a5a3b460 1142 if (err == -EINVAL) {
2e283962 1143 err = upgrade_fw(adap);
8207befa
DLR		 1144 CH_WARN(adap, "FW upgrade to %d.%d.%d %s\n",
1145 FW_VERSION_MAJOR, FW_VERSION_MINOR,
1146 FW_VERSION_MICRO, err ? "failed" : "succeeded");
a5a3b460 1147 }
4d22de3e 1148
8207befa 1149 err = t3_check_tpsram_version(adap);
47330077
DLR		 1150 if (err == -EINVAL) {
1151 err = update_tpsram(adap);
8207befa
DLR		 1152 CH_WARN(adap, "TP upgrade to %d.%d.%d %s\n",
1153 TP_VERSION_MAJOR, TP_VERSION_MINOR,
1154 TP_VERSION_MICRO, err ? "failed" : "succeeded");
47330077
DLR		 1155 }
1156
20d3fc11
DLR		 1157 /*
1158 * Clear interrupts now to catch errors if t3_init_hw fails.
1159 * We clear them again later as initialization may trigger
1160 * conditions that can interrupt.
1161 */
1162 t3_intr_clear(adap);
1163
4d22de3e
DLR		 1164 err = t3_init_hw(adap, 0);
1165 if (err)
1166 goto out;
1167
b881955b 1168 t3_set_reg_field(adap, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT);
6cdbd77e 1169 t3_write_reg(adap, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12));
bea3348e 1170
4d22de3e
DLR		 1171 err = setup_sge_qsets(adap);
1172 if (err)
1173 goto out;
1174
1175 setup_rss(adap);
48c4b6db
DLR		 1176 if (!(adap->flags & NAPI_INIT))
1177 init_napi(adap);
31563789
DLR		 1178
1179 t3_start_sge_timers(adap);
4d22de3e
DLR		 1180 adap->flags |= FULL_INIT_DONE;
1181 }
1182
1183 t3_intr_clear(adap);
1184
1185 if (adap->flags & USING_MSIX) {
1186 name_msix_vecs(adap);
1187 err = request_irq(adap->msix_info[0].vec,
1188 t3_async_intr_handler, 0,
1189 adap->msix_info[0].desc, adap);
1190 if (err)
1191 goto irq_err;
1192
42256f57
DLR		 1193 err = request_msix_data_irqs(adap);
1194 if (err) {
4d22de3e
DLR		 1195 free_irq(adap->msix_info[0].vec, adap);
1196 goto irq_err;
1197 }
1198 } else if ((err = request_irq(adap->pdev->irq,
1199 t3_intr_handler(adap,
1200 adap->sge.qs[0].rspq.
1201 polling),
2db6346f
TG		 1202 (adap->flags & USING_MSI) ?
1203 0 : IRQF_SHARED,
4d22de3e
DLR		 1204 adap->name, adap)))
1205 goto irq_err;
1206
bea3348e 1207 enable_all_napi(adap);
4d22de3e
DLR		 1208 t3_sge_start(adap);
1209 t3_intr_enable(adap);
14ab9892 1210
b881955b
DLR		 1211 if (adap->params.rev >= T3_REV_C && !(adap->flags & TP_PARITY_INIT) &&
1212 is_offload(adap) && init_tp_parity(adap) == 0)
1213 adap->flags |= TP_PARITY_INIT;
1214
1215 if (adap->flags & TP_PARITY_INIT) {
1216 t3_write_reg(adap, A_TP_INT_CAUSE,
1217 F_CMCACHEPERR | F_ARPLUTPERR);
1218 t3_write_reg(adap, A_TP_INT_ENABLE, 0x7fbfffff);
1219 }
1220
8c263761
DLR		 1221 if (!(adap->flags & QUEUES_BOUND)) {
1222 err = bind_qsets(adap);
1223 if (err) {
1224 CH_ERR(adap, "failed to bind qsets, err %d\n", err);
1225 t3_intr_disable(adap);
1226 free_irq_resources(adap);
1227 goto out;
1228 }
1229 adap->flags |= QUEUES_BOUND;
1230 }
14ab9892 1231
4d22de3e
DLR		 1232out:
1233 return err;
1234irq_err:
1235 CH_ERR(adap, "request_irq failed, err %d\n", err);
1236 goto out;
1237}
1238
1239/*
1240 * Release resources when all the ports and offloading have been stopped.
1241 */
1242static void cxgb_down(struct adapter *adapter)
1243{
1244 t3_sge_stop(adapter);
1245 spin_lock_irq(&adapter->work_lock); /* sync with PHY intr task */
1246 t3_intr_disable(adapter);
1247 spin_unlock_irq(&adapter->work_lock);
1248
8c263761 1249 free_irq_resources(adapter);
4d22de3e 1250 quiesce_rx(adapter);
c80b0c28 1251 flush_workqueue(cxgb3_wq); /* wait for external IRQ handler */
4d22de3e
DLR		 1252}
1253
1254static void schedule_chk_task(struct adapter *adap)
1255{
1256 unsigned int timeo;
1257
1258 timeo = adap->params.linkpoll_period ?
1259 (HZ * adap->params.linkpoll_period) / 10 :
1260 adap->params.stats_update_period * HZ;
1261 if (timeo)
1262 queue_delayed_work(cxgb3_wq, &adap->adap_check_task, timeo);
1263}
1264
1265static int offload_open(struct net_device *dev)
1266{
5fbf816f
DLR		 1267 struct port_info *pi = netdev_priv(dev);
1268 struct adapter *adapter = pi->adapter;
1269 struct t3cdev *tdev = dev2t3cdev(dev);
4d22de3e 1270 int adap_up = adapter->open_device_map & PORT_MASK;
c54f5c24 1271 int err;
4d22de3e
DLR		 1272
1273 if (test_and_set_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1274 return 0;
1275
1276 if (!adap_up && (err = cxgb_up(adapter)) < 0)
48c4b6db 1277 goto out;
4d22de3e
DLR		 1278
1279 t3_tp_set_offload_mode(adapter, 1);
1280 tdev->lldev = adapter->port[0];
1281 err = cxgb3_offload_activate(adapter);
1282 if (err)
1283 goto out;
1284
1285 init_port_mtus(adapter);
1286 t3_load_mtus(adapter, adapter->params.mtus, adapter->params.a_wnd,
1287 adapter->params.b_wnd,
1288 adapter->params.rev == 0 ?
1289 adapter->port[0]->mtu : 0xffff);
1290 init_smt(adapter);
1291
d96a51f6
DN		 1292 if (sysfs_create_group(&tdev->lldev->dev.kobj, &offload_attr_group))
1293 dev_dbg(&dev->dev, "cannot create sysfs group\n");
4d22de3e
DLR		 1294
1295 /* Call back all registered clients */
1296 cxgb3_add_clients(tdev);
1297
1298out:
1299 /* restore them in case the offload module has changed them */
1300 if (err) {
1301 t3_tp_set_offload_mode(adapter, 0);
1302 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1303 cxgb3_set_dummy_ops(tdev);
1304 }
1305 return err;
1306}
1307
1308static int offload_close(struct t3cdev *tdev)
1309{
1310 struct adapter *adapter = tdev2adap(tdev);
1311
1312 if (!test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1313 return 0;
1314
1315 /* Call back all registered clients */
1316 cxgb3_remove_clients(tdev);
1317
0ee8d33c 1318 sysfs_remove_group(&tdev->lldev->dev.kobj, &offload_attr_group);
4d22de3e 1319
c80b0c28
DLR		 1320 /* Flush work scheduled while releasing TIDs */
1321 flush_scheduled_work();
1322
4d22de3e
DLR		 1323 tdev->lldev = NULL;
1324 cxgb3_set_dummy_ops(tdev);
1325 t3_tp_set_offload_mode(adapter, 0);
1326 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1327
1328 if (!adapter->open_device_map)
1329 cxgb_down(adapter);
1330
1331 cxgb3_offload_deactivate(adapter);
1332 return 0;
1333}
1334
1335static int cxgb_open(struct net_device *dev)
1336{
4d22de3e 1337 struct port_info *pi = netdev_priv(dev);
5fbf816f 1338 struct adapter *adapter = pi->adapter;
4d22de3e 1339 int other_ports = adapter->open_device_map & PORT_MASK;
5fbf816f 1340 int err;
4d22de3e 1341
48c4b6db 1342 if (!adapter->open_device_map && (err = cxgb_up(adapter)) < 0)
4d22de3e
DLR		 1343 return err;
1344
1345 set_bit(pi->port_id, &adapter->open_device_map);
8ac3ba68 1346 if (is_offload(adapter) && !ofld_disable) {
4d22de3e
DLR		 1347 err = offload_open(dev);
1348 if (err)
1349 printk(KERN_WARNING
1350 "Could not initialize offload capabilities\n");
1351 }
1352
82ad3329 1353 dev->real_num_tx_queues = pi->nqsets;
4d22de3e
DLR		 1354 link_start(dev);
1355 t3_port_intr_enable(adapter, pi->port_id);
82ad3329 1356 netif_tx_start_all_queues(dev);
4d22de3e
DLR		 1357 if (!other_ports)
1358 schedule_chk_task(adapter);
1359
1360 return 0;
1361}
1362
1363static int cxgb_close(struct net_device *dev)
1364{
5fbf816f
DLR		 1365 struct port_info *pi = netdev_priv(dev);
1366 struct adapter *adapter = pi->adapter;
4d22de3e 1367
e8d19370
DLR		 1368
1369 if (!adapter->open_device_map)
1370 return 0;
1371
bf792094
DLR		 1372 /* Stop link fault interrupts */
1373 t3_xgm_intr_disable(adapter, pi->port_id);
1374 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
1375
5fbf816f 1376 t3_port_intr_disable(adapter, pi->port_id);
82ad3329 1377 netif_tx_stop_all_queues(dev);
5fbf816f 1378 pi->phy.ops->power_down(&pi->phy, 1);
4d22de3e 1379 netif_carrier_off(dev);
5fbf816f 1380 t3_mac_disable(&pi->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX);
4d22de3e 1381
20d3fc11 1382 spin_lock_irq(&adapter->work_lock); /* sync with update task */
5fbf816f 1383 clear_bit(pi->port_id, &adapter->open_device_map);
20d3fc11 1384 spin_unlock_irq(&adapter->work_lock);
4d22de3e
DLR		 1385
1386 if (!(adapter->open_device_map & PORT_MASK))
c80b0c28 1387 cancel_delayed_work_sync(&adapter->adap_check_task);
4d22de3e
DLR		 1388
1389 if (!adapter->open_device_map)
1390 cxgb_down(adapter);
1391
1392 return 0;
1393}
1394
1395static struct net_device_stats *cxgb_get_stats(struct net_device *dev)
1396{
5fbf816f
DLR		 1397 struct port_info *pi = netdev_priv(dev);
1398 struct adapter *adapter = pi->adapter;
1399 struct net_device_stats *ns = &pi->netstats;
4d22de3e
DLR		 1400 const struct mac_stats *pstats;
1401
1402 spin_lock(&adapter->stats_lock);
5fbf816f 1403 pstats = t3_mac_update_stats(&pi->mac);
4d22de3e
DLR		 1404 spin_unlock(&adapter->stats_lock);
1405
1406 ns->tx_bytes = pstats->tx_octets;
1407 ns->tx_packets = pstats->tx_frames;
1408 ns->rx_bytes = pstats->rx_octets;
1409 ns->rx_packets = pstats->rx_frames;
1410 ns->multicast = pstats->rx_mcast_frames;
1411
1412 ns->tx_errors = pstats->tx_underrun;
1413 ns->rx_errors = pstats->rx_symbol_errs + pstats->rx_fcs_errs +
1414 pstats->rx_too_long + pstats->rx_jabber + pstats->rx_short +
1415 pstats->rx_fifo_ovfl;
1416
1417 /* detailed rx_errors */
1418 ns->rx_length_errors = pstats->rx_jabber + pstats->rx_too_long;
1419 ns->rx_over_errors = 0;
1420 ns->rx_crc_errors = pstats->rx_fcs_errs;
1421 ns->rx_frame_errors = pstats->rx_symbol_errs;
1422 ns->rx_fifo_errors = pstats->rx_fifo_ovfl;
1423 ns->rx_missed_errors = pstats->rx_cong_drops;
1424
1425 /* detailed tx_errors */
1426 ns->tx_aborted_errors = 0;
1427 ns->tx_carrier_errors = 0;
1428 ns->tx_fifo_errors = pstats->tx_underrun;
1429 ns->tx_heartbeat_errors = 0;
1430 ns->tx_window_errors = 0;
1431 return ns;
1432}
1433
1434static u32 get_msglevel(struct net_device *dev)
1435{
5fbf816f
DLR		 1436 struct port_info *pi = netdev_priv(dev);
1437 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1438
1439 return adapter->msg_enable;
1440}
1441
1442static void set_msglevel(struct net_device *dev, u32 val)
1443{
5fbf816f
DLR		 1444 struct port_info *pi = netdev_priv(dev);
1445 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1446
1447 adapter->msg_enable = val;
1448}
1449
1450static char stats_strings[][ETH_GSTRING_LEN] = {
1451 "TxOctetsOK ",
1452 "TxFramesOK ",
1453 "TxMulticastFramesOK",
1454 "TxBroadcastFramesOK",
1455 "TxPauseFrames ",
1456 "TxUnderrun ",
1457 "TxExtUnderrun ",
1458
1459 "TxFrames64 ",
1460 "TxFrames65To127 ",
1461 "TxFrames128To255 ",
1462 "TxFrames256To511 ",
1463 "TxFrames512To1023 ",
1464 "TxFrames1024To1518 ",
1465 "TxFrames1519ToMax ",
1466
1467 "RxOctetsOK ",
1468 "RxFramesOK ",
1469 "RxMulticastFramesOK",
1470 "RxBroadcastFramesOK",
1471 "RxPauseFrames ",
1472 "RxFCSErrors ",
1473 "RxSymbolErrors ",
1474 "RxShortErrors ",
1475 "RxJabberErrors ",
1476 "RxLengthErrors ",
1477 "RxFIFOoverflow ",
1478
1479 "RxFrames64 ",
1480 "RxFrames65To127 ",
1481 "RxFrames128To255 ",
1482 "RxFrames256To511 ",
1483 "RxFrames512To1023 ",
1484 "RxFrames1024To1518 ",
1485 "RxFrames1519ToMax ",
1486
1487 "PhyFIFOErrors ",
1488 "TSO ",
1489 "VLANextractions ",
1490 "VLANinsertions ",
1491 "TxCsumOffload ",
1492 "RxCsumGood ",
b47385bd
DLR		 1493 "LroAggregated ",
1494 "LroFlushed ",
1495 "LroNoDesc ",
fc90664e
DLR		 1496 "RxDrops ",
1497
1498 "CheckTXEnToggled ",
1499 "CheckResets ",
1500
bf792094 1501 "LinkFaults ",
4d22de3e
DLR		 1502};
1503
b9f2c044 1504static int get_sset_count(struct net_device *dev, int sset)
4d22de3e 1505{
b9f2c044
JG		 1506 switch (sset) {
1507 case ETH_SS_STATS:
1508 return ARRAY_SIZE(stats_strings);
1509 default:
1510 return -EOPNOTSUPP;
1511 }
4d22de3e
DLR		 1512}
1513
1514#define T3_REGMAP_SIZE (3 * 1024)
1515
1516static int get_regs_len(struct net_device *dev)
1517{
1518 return T3_REGMAP_SIZE;
1519}
1520
1521static int get_eeprom_len(struct net_device *dev)
1522{
1523 return EEPROMSIZE;
1524}
1525
1526static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1527{
5fbf816f
DLR		 1528 struct port_info *pi = netdev_priv(dev);
1529 struct adapter *adapter = pi->adapter;
4d22de3e 1530 u32 fw_vers = 0;
47330077 1531 u32 tp_vers = 0;
4d22de3e 1532
cf3760da 1533 spin_lock(&adapter->stats_lock);
4d22de3e 1534 t3_get_fw_version(adapter, &fw_vers);
47330077 1535 t3_get_tp_version(adapter, &tp_vers);
cf3760da 1536 spin_unlock(&adapter->stats_lock);
4d22de3e
DLR		 1537
1538 strcpy(info->driver, DRV_NAME);
1539 strcpy(info->version, DRV_VERSION);
1540 strcpy(info->bus_info, pci_name(adapter->pdev));
1541 if (!fw_vers)
1542 strcpy(info->fw_version, "N/A");
4aac3899 1543 else {
4d22de3e 1544 snprintf(info->fw_version, sizeof(info->fw_version),
47330077 1545 "%s %u.%u.%u TP %u.%u.%u",
4aac3899
DLR		 1546 G_FW_VERSION_TYPE(fw_vers) ? "T" : "N",
1547 G_FW_VERSION_MAJOR(fw_vers),
1548 G_FW_VERSION_MINOR(fw_vers),
47330077
DLR		 1549 G_FW_VERSION_MICRO(fw_vers),
1550 G_TP_VERSION_MAJOR(tp_vers),
1551 G_TP_VERSION_MINOR(tp_vers),
1552 G_TP_VERSION_MICRO(tp_vers));
4aac3899 1553 }
4d22de3e
DLR		 1554}
1555
1556static void get_strings(struct net_device *dev, u32 stringset, u8 * data)
1557{
1558 if (stringset == ETH_SS_STATS)
1559 memcpy(data, stats_strings, sizeof(stats_strings));
1560}
1561
1562static unsigned long collect_sge_port_stats(struct adapter *adapter,
1563 struct port_info *p, int idx)
1564{
1565 int i;
1566 unsigned long tot = 0;
1567
8c263761
DLR		 1568 for (i = p->first_qset; i < p->first_qset + p->nqsets; ++i)
1569 tot += adapter->sge.qs[i].port_stats[idx];
4d22de3e
DLR		 1570 return tot;
1571}
1572
1573static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1574 u64 *data)
1575{
4d22de3e 1576 struct port_info *pi = netdev_priv(dev);
5fbf816f 1577 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1578 const struct mac_stats *s;
1579
1580 spin_lock(&adapter->stats_lock);
1581 s = t3_mac_update_stats(&pi->mac);
1582 spin_unlock(&adapter->stats_lock);
1583
1584 *data++ = s->tx_octets;
1585 *data++ = s->tx_frames;
1586 *data++ = s->tx_mcast_frames;
1587 *data++ = s->tx_bcast_frames;
1588 *data++ = s->tx_pause;
1589 *data++ = s->tx_underrun;
1590 *data++ = s->tx_fifo_urun;
1591
1592 *data++ = s->tx_frames_64;
1593 *data++ = s->tx_frames_65_127;
1594 *data++ = s->tx_frames_128_255;
1595 *data++ = s->tx_frames_256_511;
1596 *data++ = s->tx_frames_512_1023;
1597 *data++ = s->tx_frames_1024_1518;
1598 *data++ = s->tx_frames_1519_max;
1599
1600 *data++ = s->rx_octets;
1601 *data++ = s->rx_frames;
1602 *data++ = s->rx_mcast_frames;
1603 *data++ = s->rx_bcast_frames;
1604 *data++ = s->rx_pause;
1605 *data++ = s->rx_fcs_errs;
1606 *data++ = s->rx_symbol_errs;
1607 *data++ = s->rx_short;
1608 *data++ = s->rx_jabber;
1609 *data++ = s->rx_too_long;
1610 *data++ = s->rx_fifo_ovfl;
1611
1612 *data++ = s->rx_frames_64;
1613 *data++ = s->rx_frames_65_127;
1614 *data++ = s->rx_frames_128_255;
1615 *data++ = s->rx_frames_256_511;
1616 *data++ = s->rx_frames_512_1023;
1617 *data++ = s->rx_frames_1024_1518;
1618 *data++ = s->rx_frames_1519_max;
1619
1620 *data++ = pi->phy.fifo_errors;
1621
1622 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TSO);
1623 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANEX);
1624 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANINS);
1625 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_CSUM);
1626 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_RX_CSUM_GOOD);
7be2df45
HX		 1627 *data++ = 0;
1628 *data++ = 0;
1629 *data++ = 0;
4d22de3e 1630 *data++ = s->rx_cong_drops;
fc90664e
DLR		 1631
1632 *data++ = s->num_toggled;
1633 *data++ = s->num_resets;
bf792094
DLR		 1634
1635 *data++ = s->link_faults;
4d22de3e
DLR		 1636}
1637
1638static inline void reg_block_dump(struct adapter *ap, void *buf,
1639 unsigned int start, unsigned int end)
1640{
1641 u32 *p = buf + start;
1642
1643 for (; start <= end; start += sizeof(u32))
1644 *p++ = t3_read_reg(ap, start);
1645}
1646
1647static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1648 void *buf)
1649{
5fbf816f
DLR		 1650 struct port_info *pi = netdev_priv(dev);
1651 struct adapter *ap = pi->adapter;
4d22de3e
DLR		 1652
1653 /*
1654 * Version scheme:
1655 * bits 0..9: chip version
1656 * bits 10..15: chip revision
1657 * bit 31: set for PCIe cards
1658 */
1659 regs->version = 3 | (ap->params.rev << 10) | (is_pcie(ap) << 31);
1660
1661 /*
1662 * We skip the MAC statistics registers because they are clear-on-read.
1663 * Also reading multi-register stats would need to synchronize with the
1664 * periodic mac stats accumulation. Hard to justify the complexity.
1665 */
1666 memset(buf, 0, T3_REGMAP_SIZE);
1667 reg_block_dump(ap, buf, 0, A_SG_RSPQ_CREDIT_RETURN);
1668 reg_block_dump(ap, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT);
1669 reg_block_dump(ap, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE);
1670 reg_block_dump(ap, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA);
1671 reg_block_dump(ap, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3);
1672 reg_block_dump(ap, buf, A_XGM_SERDES_STATUS0,
1673 XGM_REG(A_XGM_SERDES_STAT3, 1));
1674 reg_block_dump(ap, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1),
1675 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1));
1676}
1677
1678static int restart_autoneg(struct net_device *dev)
1679{
1680 struct port_info *p = netdev_priv(dev);
1681
1682 if (!netif_running(dev))
1683 return -EAGAIN;
1684 if (p->link_config.autoneg != AUTONEG_ENABLE)
1685 return -EINVAL;
1686 p->phy.ops->autoneg_restart(&p->phy);
1687 return 0;
1688}
1689
1690static int cxgb3_phys_id(struct net_device *dev, u32 data)
1691{
5fbf816f
DLR		 1692 struct port_info *pi = netdev_priv(dev);
1693 struct adapter *adapter = pi->adapter;
4d22de3e 1694 int i;
4d22de3e
DLR		 1695
1696 if (data == 0)
1697 data = 2;
1698
1699 for (i = 0; i < data * 2; i++) {
1700 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
1701 (i & 1) ? F_GPIO0_OUT_VAL : 0);
1702 if (msleep_interruptible(500))
1703 break;
1704 }
1705 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
1706 F_GPIO0_OUT_VAL);
1707 return 0;
1708}
1709
1710static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1711{
1712 struct port_info *p = netdev_priv(dev);
1713
1714 cmd->supported = p->link_config.supported;
1715 cmd->advertising = p->link_config.advertising;
1716
1717 if (netif_carrier_ok(dev)) {
1718 cmd->speed = p->link_config.speed;
1719 cmd->duplex = p->link_config.duplex;
1720 } else {
1721 cmd->speed = -1;
1722 cmd->duplex = -1;
1723 }
1724
1725 cmd->port = (cmd->supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE;
0f07c4ee 1726 cmd->phy_address = p->phy.mdio.prtad;
4d22de3e
DLR		 1727 cmd->transceiver = XCVR_EXTERNAL;
1728 cmd->autoneg = p->link_config.autoneg;
1729 cmd->maxtxpkt = 0;
1730 cmd->maxrxpkt = 0;
1731 return 0;
1732}
1733
1734static int speed_duplex_to_caps(int speed, int duplex)
1735{
1736 int cap = 0;
1737
1738 switch (speed) {
1739 case SPEED_10:
1740 if (duplex == DUPLEX_FULL)
1741 cap = SUPPORTED_10baseT_Full;
1742 else
1743 cap = SUPPORTED_10baseT_Half;
1744 break;
1745 case SPEED_100:
1746 if (duplex == DUPLEX_FULL)
1747 cap = SUPPORTED_100baseT_Full;
1748 else
1749 cap = SUPPORTED_100baseT_Half;
1750 break;
1751 case SPEED_1000:
1752 if (duplex == DUPLEX_FULL)
1753 cap = SUPPORTED_1000baseT_Full;
1754 else
1755 cap = SUPPORTED_1000baseT_Half;
1756 break;
1757 case SPEED_10000:
1758 if (duplex == DUPLEX_FULL)
1759 cap = SUPPORTED_10000baseT_Full;
1760 }
1761 return cap;
1762}
1763
1764#define ADVERTISED_MASK (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1765 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1766 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | \
1767 ADVERTISED_10000baseT_Full)
1768
1769static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1770{
1771 struct port_info *p = netdev_priv(dev);
1772 struct link_config *lc = &p->link_config;
1773
9b1e3656
DLR		 1774 if (!(lc->supported & SUPPORTED_Autoneg)) {
1775 /*
1776 * PHY offers a single speed/duplex. See if that's what's
1777 * being requested.
1778 */
1779 if (cmd->autoneg == AUTONEG_DISABLE) {
97915b5b 1780 int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex);
9b1e3656
DLR		 1781 if (lc->supported & cap)
1782 return 0;
1783 }
1784 return -EINVAL;
1785 }
4d22de3e
DLR		 1786
1787 if (cmd->autoneg == AUTONEG_DISABLE) {
1788 int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex);
1789
1790 if (!(lc->supported & cap) || cmd->speed == SPEED_1000)
1791 return -EINVAL;
1792 lc->requested_speed = cmd->speed;
1793 lc->requested_duplex = cmd->duplex;
1794 lc->advertising = 0;
1795 } else {
1796 cmd->advertising &= ADVERTISED_MASK;
1797 cmd->advertising &= lc->supported;
1798 if (!cmd->advertising)
1799 return -EINVAL;
1800 lc->requested_speed = SPEED_INVALID;
1801 lc->requested_duplex = DUPLEX_INVALID;
1802 lc->advertising = cmd->advertising | ADVERTISED_Autoneg;
1803 }
1804 lc->autoneg = cmd->autoneg;
1805 if (netif_running(dev))
1806 t3_link_start(&p->phy, &p->mac, lc);
1807 return 0;
1808}
1809
1810static void get_pauseparam(struct net_device *dev,
1811 struct ethtool_pauseparam *epause)
1812{
1813 struct port_info *p = netdev_priv(dev);
1814
1815 epause->autoneg = (p->link_config.requested_fc & PAUSE_AUTONEG) != 0;
1816 epause->rx_pause = (p->link_config.fc & PAUSE_RX) != 0;
1817 epause->tx_pause = (p->link_config.fc & PAUSE_TX) != 0;
1818}
1819
1820static int set_pauseparam(struct net_device *dev,
1821 struct ethtool_pauseparam *epause)
1822{
1823 struct port_info *p = netdev_priv(dev);
1824 struct link_config *lc = &p->link_config;
1825
1826 if (epause->autoneg == AUTONEG_DISABLE)
1827 lc->requested_fc = 0;
1828 else if (lc->supported & SUPPORTED_Autoneg)
1829 lc->requested_fc = PAUSE_AUTONEG;
1830 else
1831 return -EINVAL;
1832
1833 if (epause->rx_pause)
1834 lc->requested_fc |= PAUSE_RX;
1835 if (epause->tx_pause)
1836 lc->requested_fc |= PAUSE_TX;
1837 if (lc->autoneg == AUTONEG_ENABLE) {
1838 if (netif_running(dev))
1839 t3_link_start(&p->phy, &p->mac, lc);
1840 } else {
1841 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1842 if (netif_running(dev))
1843 t3_mac_set_speed_duplex_fc(&p->mac, -1, -1, lc->fc);
1844 }
1845 return 0;
1846}
1847
1848static u32 get_rx_csum(struct net_device *dev)
1849{
1850 struct port_info *p = netdev_priv(dev);
1851
47fd23fe 1852 return p->rx_offload & T3_RX_CSUM;
4d22de3e
DLR		 1853}
1854
1855static int set_rx_csum(struct net_device *dev, u32 data)
1856{
1857 struct port_info *p = netdev_priv(dev);
1858
47fd23fe
RD		 1859 if (data) {
1860 p->rx_offload |= T3_RX_CSUM;
1861 } else {
b47385bd
DLR		 1862 int i;
1863
47fd23fe 1864 p->rx_offload &= ~(T3_RX_CSUM | T3_LRO);
04ecb072
DLR		 1865 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++)
1866 set_qset_lro(dev, i, 0);
b47385bd 1867 }
4d22de3e
DLR		 1868 return 0;
1869}
1870
1871static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1872{
5fbf816f
DLR		 1873 struct port_info *pi = netdev_priv(dev);
1874 struct adapter *adapter = pi->adapter;
05b97b30 1875 const struct qset_params *q = &adapter->params.sge.qset[pi->first_qset];
4d22de3e
DLR		 1876
1877 e->rx_max_pending = MAX_RX_BUFFERS;
1878 e->rx_mini_max_pending = 0;
1879 e->rx_jumbo_max_pending = MAX_RX_JUMBO_BUFFERS;
1880 e->tx_max_pending = MAX_TXQ_ENTRIES;
1881
05b97b30
DLR		 1882 e->rx_pending = q->fl_size;
1883 e->rx_mini_pending = q->rspq_size;
1884 e->rx_jumbo_pending = q->jumbo_size;
1885 e->tx_pending = q->txq_size[0];
4d22de3e
DLR		 1886}
1887
1888static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1889{
5fbf816f
DLR		 1890 struct port_info *pi = netdev_priv(dev);
1891 struct adapter *adapter = pi->adapter;
05b97b30 1892 struct qset_params *q;
5fbf816f 1893 int i;
4d22de3e
DLR		 1894
1895 if (e->rx_pending > MAX_RX_BUFFERS ||
1896 e->rx_jumbo_pending > MAX_RX_JUMBO_BUFFERS ||
1897 e->tx_pending > MAX_TXQ_ENTRIES ||
1898 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
1899 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
1900 e->rx_pending < MIN_FL_ENTRIES ||
1901 e->rx_jumbo_pending < MIN_FL_ENTRIES ||
1902 e->tx_pending < adapter->params.nports * MIN_TXQ_ENTRIES)
1903 return -EINVAL;
1904
1905 if (adapter->flags & FULL_INIT_DONE)
1906 return -EBUSY;
1907
05b97b30
DLR		 1908 q = &adapter->params.sge.qset[pi->first_qset];
1909 for (i = 0; i < pi->nqsets; ++i, ++q) {
4d22de3e
DLR		 1910 q->rspq_size = e->rx_mini_pending;
1911 q->fl_size = e->rx_pending;
1912 q->jumbo_size = e->rx_jumbo_pending;
1913 q->txq_size[0] = e->tx_pending;
1914 q->txq_size[1] = e->tx_pending;
1915 q->txq_size[2] = e->tx_pending;
1916 }
1917 return 0;
1918}
1919
1920static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1921{
5fbf816f
DLR		 1922 struct port_info *pi = netdev_priv(dev);
1923 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1924 struct qset_params *qsp = &adapter->params.sge.qset[0];
1925 struct sge_qset *qs = &adapter->sge.qs[0];
1926
1927 if (c->rx_coalesce_usecs * 10 > M_NEWTIMER)
1928 return -EINVAL;
1929
1930 qsp->coalesce_usecs = c->rx_coalesce_usecs;
1931 t3_update_qset_coalesce(qs, qsp);
1932 return 0;
1933}
1934
1935static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1936{
5fbf816f
DLR		 1937 struct port_info *pi = netdev_priv(dev);
1938 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1939 struct qset_params *q = adapter->params.sge.qset;
1940
1941 c->rx_coalesce_usecs = q->coalesce_usecs;
1942 return 0;
1943}
1944
1945static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
1946 u8 * data)
1947{
5fbf816f
DLR		 1948 struct port_info *pi = netdev_priv(dev);
1949 struct adapter *adapter = pi->adapter;
4d22de3e 1950 int i, err = 0;
4d22de3e
DLR		 1951
1952 u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
1953 if (!buf)
1954 return -ENOMEM;
1955
1956 e->magic = EEPROM_MAGIC;
1957 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
05e5c116 1958 err = t3_seeprom_read(adapter, i, (__le32 *) & buf[i]);
4d22de3e
DLR		 1959
1960 if (!err)
1961 memcpy(data, buf + e->offset, e->len);
1962 kfree(buf);
1963 return err;
1964}
1965
1966static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
1967 u8 * data)
1968{
5fbf816f
DLR		 1969 struct port_info *pi = netdev_priv(dev);
1970 struct adapter *adapter = pi->adapter;
05e5c116
AV		 1971 u32 aligned_offset, aligned_len;
1972 __le32 *p;
4d22de3e 1973 u8 *buf;
c54f5c24 1974 int err;
4d22de3e
DLR		 1975
1976 if (eeprom->magic != EEPROM_MAGIC)
1977 return -EINVAL;
1978
1979 aligned_offset = eeprom->offset & ~3;
1980 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
1981
1982 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
1983 buf = kmalloc(aligned_len, GFP_KERNEL);
1984 if (!buf)
1985 return -ENOMEM;
05e5c116 1986 err = t3_seeprom_read(adapter, aligned_offset, (__le32 *) buf);
4d22de3e
DLR		 1987 if (!err && aligned_len > 4)
1988 err = t3_seeprom_read(adapter,
1989 aligned_offset + aligned_len - 4,
05e5c116 1990 (__le32 *) & buf[aligned_len - 4]);
4d22de3e
DLR		 1991 if (err)
1992 goto out;
1993 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
1994 } else
1995 buf = data;
1996
1997 err = t3_seeprom_wp(adapter, 0);
1998 if (err)
1999 goto out;
2000
05e5c116 2001 for (p = (__le32 *) buf; !err && aligned_len; aligned_len -= 4, p++) {
4d22de3e
DLR		 2002 err = t3_seeprom_write(adapter, aligned_offset, *p);
2003 aligned_offset += 4;
2004 }
2005
2006 if (!err)
2007 err = t3_seeprom_wp(adapter, 1);
2008out:
2009 if (buf != data)
2010 kfree(buf);
2011 return err;
2012}
2013
2014static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2015{
2016 wol->supported = 0;
2017 wol->wolopts = 0;
2018 memset(&wol->sopass, 0, sizeof(wol->sopass));
2019}
2020
2021static const struct ethtool_ops cxgb_ethtool_ops = {
2022 .get_settings = get_settings,
2023 .set_settings = set_settings,
2024 .get_drvinfo = get_drvinfo,
2025 .get_msglevel = get_msglevel,
2026 .set_msglevel = set_msglevel,
2027 .get_ringparam = get_sge_param,
2028 .set_ringparam = set_sge_param,
2029 .get_coalesce = get_coalesce,
2030 .set_coalesce = set_coalesce,
2031 .get_eeprom_len = get_eeprom_len,
2032 .get_eeprom = get_eeprom,
2033 .set_eeprom = set_eeprom,
2034 .get_pauseparam = get_pauseparam,
2035 .set_pauseparam = set_pauseparam,
2036 .get_rx_csum = get_rx_csum,
2037 .set_rx_csum = set_rx_csum,
4d22de3e 2038 .set_tx_csum = ethtool_op_set_tx_csum,
4d22de3e
DLR		 2039 .set_sg = ethtool_op_set_sg,
2040 .get_link = ethtool_op_get_link,
2041 .get_strings = get_strings,
2042 .phys_id = cxgb3_phys_id,
2043 .nway_reset = restart_autoneg,
b9f2c044 2044 .get_sset_count = get_sset_count,
4d22de3e
DLR		 2045 .get_ethtool_stats = get_stats,
2046 .get_regs_len = get_regs_len,
2047 .get_regs = get_regs,
2048 .get_wol = get_wol,
4d22de3e 2049 .set_tso = ethtool_op_set_tso,
4d22de3e
DLR		 2050};
2051
2052static int in_range(int val, int lo, int hi)
2053{
2054 return val < 0 || (val <= hi && val >= lo);
2055}
2056
2057static int cxgb_extension_ioctl(struct net_device *dev, void __user *useraddr)
2058{
5fbf816f
DLR		 2059 struct port_info *pi = netdev_priv(dev);
2060 struct adapter *adapter = pi->adapter;
4d22de3e 2061 u32 cmd;
5fbf816f 2062 int ret;
4d22de3e
DLR		 2063
2064 if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
2065 return -EFAULT;
2066
2067 switch (cmd) {
4d22de3e
DLR		 2068 case CHELSIO_SET_QSET_PARAMS:{
2069 int i;
2070 struct qset_params *q;
2071 struct ch_qset_params t;
8c263761
DLR		 2072 int q1 = pi->first_qset;
2073 int nqsets = pi->nqsets;
4d22de3e
DLR		 2074
2075 if (!capable(CAP_NET_ADMIN))
2076 return -EPERM;
2077 if (copy_from_user(&t, useraddr, sizeof(t)))
2078 return -EFAULT;
2079 if (t.qset_idx >= SGE_QSETS)
2080 return -EINVAL;
2081 if (!in_range(t.intr_lat, 0, M_NEWTIMER) ||
2082 !in_range(t.cong_thres, 0, 255) ||
2083 !in_range(t.txq_size[0], MIN_TXQ_ENTRIES,
2084 MAX_TXQ_ENTRIES) ||
2085 !in_range(t.txq_size[1], MIN_TXQ_ENTRIES,
2086 MAX_TXQ_ENTRIES) ||
2087 !in_range(t.txq_size[2], MIN_CTRL_TXQ_ENTRIES,
2088 MAX_CTRL_TXQ_ENTRIES) ||
2089 !in_range(t.fl_size[0], MIN_FL_ENTRIES,
2090 MAX_RX_BUFFERS)
2091 || !in_range(t.fl_size[1], MIN_FL_ENTRIES,
2092 MAX_RX_JUMBO_BUFFERS)
2093 || !in_range(t.rspq_size, MIN_RSPQ_ENTRIES,
2094 MAX_RSPQ_ENTRIES))
2095 return -EINVAL;
8c263761
DLR		 2096
2097 if ((adapter->flags & FULL_INIT_DONE) && t.lro > 0)
2098 for_each_port(adapter, i) {
2099 pi = adap2pinfo(adapter, i);
2100 if (t.qset_idx >= pi->first_qset &&
2101 t.qset_idx < pi->first_qset + pi->nqsets &&
47fd23fe 2102 !(pi->rx_offload & T3_RX_CSUM))
8c263761
DLR		 2103 return -EINVAL;
2104 }
2105
4d22de3e
DLR		 2106 if ((adapter->flags & FULL_INIT_DONE) &&
2107 (t.rspq_size >= 0 || t.fl_size[0] >= 0 ||
2108 t.fl_size[1] >= 0 || t.txq_size[0] >= 0 ||
2109 t.txq_size[1] >= 0 || t.txq_size[2] >= 0 ||
2110 t.polling >= 0 || t.cong_thres >= 0))
2111 return -EBUSY;
2112
8c263761
DLR		 2113 /* Allow setting of any available qset when offload enabled */
2114 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2115 q1 = 0;
2116 for_each_port(adapter, i) {
2117 pi = adap2pinfo(adapter, i);
2118 nqsets += pi->first_qset + pi->nqsets;
2119 }
2120 }
2121
2122 if (t.qset_idx < q1)
2123 return -EINVAL;
2124 if (t.qset_idx > q1 + nqsets - 1)
2125 return -EINVAL;
2126
4d22de3e
DLR		 2127 q = &adapter->params.sge.qset[t.qset_idx];
2128
2129 if (t.rspq_size >= 0)
2130 q->rspq_size = t.rspq_size;
2131 if (t.fl_size[0] >= 0)
2132 q->fl_size = t.fl_size[0];
2133 if (t.fl_size[1] >= 0)
2134 q->jumbo_size = t.fl_size[1];
2135 if (t.txq_size[0] >= 0)
2136 q->txq_size[0] = t.txq_size[0];
2137 if (t.txq_size[1] >= 0)
2138 q->txq_size[1] = t.txq_size[1];
2139 if (t.txq_size[2] >= 0)
2140 q->txq_size[2] = t.txq_size[2];
2141 if (t.cong_thres >= 0)
2142 q->cong_thres = t.cong_thres;
2143 if (t.intr_lat >= 0) {
2144 struct sge_qset *qs =
2145 &adapter->sge.qs[t.qset_idx];
2146
2147 q->coalesce_usecs = t.intr_lat;
2148 t3_update_qset_coalesce(qs, q);
2149 }
2150 if (t.polling >= 0) {
2151 if (adapter->flags & USING_MSIX)
2152 q->polling = t.polling;
2153 else {
2154 /* No polling with INTx for T3A */
2155 if (adapter->params.rev == 0 &&
2156 !(adapter->flags & USING_MSI))
2157 t.polling = 0;
2158
2159 for (i = 0; i < SGE_QSETS; i++) {
2160 q = &adapter->params.sge.
2161 qset[i];
2162 q->polling = t.polling;
2163 }
2164 }
2165 }
04ecb072
DLR		 2166 if (t.lro >= 0)
2167 set_qset_lro(dev, t.qset_idx, t.lro);
2168
4d22de3e
DLR		 2169 break;
2170 }
2171 case CHELSIO_GET_QSET_PARAMS:{
2172 struct qset_params *q;
2173 struct ch_qset_params t;
8c263761
DLR		 2174 int q1 = pi->first_qset;
2175 int nqsets = pi->nqsets;
2176 int i;
4d22de3e
DLR		 2177
2178 if (copy_from_user(&t, useraddr, sizeof(t)))
2179 return -EFAULT;
8c263761
DLR		 2180
2181 /* Display qsets for all ports when offload enabled */
2182 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2183 q1 = 0;
2184 for_each_port(adapter, i) {
2185 pi = adap2pinfo(adapter, i);
2186 nqsets = pi->first_qset + pi->nqsets;
2187 }
2188 }
2189
2190 if (t.qset_idx >= nqsets)
4d22de3e
DLR		 2191 return -EINVAL;
2192
8c263761 2193 q = &adapter->params.sge.qset[q1 + t.qset_idx];
4d22de3e
DLR		 2194 t.rspq_size = q->rspq_size;
2195 t.txq_size[0] = q->txq_size[0];
2196 t.txq_size[1] = q->txq_size[1];
2197 t.txq_size[2] = q->txq_size[2];
2198 t.fl_size[0] = q->fl_size;
2199 t.fl_size[1] = q->jumbo_size;
2200 t.polling = q->polling;
b47385bd 2201 t.lro = q->lro;
4d22de3e
DLR		 2202 t.intr_lat = q->coalesce_usecs;
2203 t.cong_thres = q->cong_thres;
8c263761
DLR		 2204 t.qnum = q1;
2205
2206 if (adapter->flags & USING_MSIX)
2207 t.vector = adapter->msix_info[q1 + t.qset_idx + 1].vec;
2208 else
2209 t.vector = adapter->pdev->irq;
4d22de3e
DLR		 2210
2211 if (copy_to_user(useraddr, &t, sizeof(t)))
2212 return -EFAULT;
2213 break;
2214 }
2215 case CHELSIO_SET_QSET_NUM:{
2216 struct ch_reg edata;
4d22de3e
DLR		 2217 unsigned int i, first_qset = 0, other_qsets = 0;
2218
2219 if (!capable(CAP_NET_ADMIN))
2220 return -EPERM;
2221 if (adapter->flags & FULL_INIT_DONE)
2222 return -EBUSY;
2223 if (copy_from_user(&edata, useraddr, sizeof(edata)))
2224 return -EFAULT;
2225 if (edata.val < 1 ||
2226 (edata.val > 1 && !(adapter->flags & USING_MSIX)))
2227 return -EINVAL;
2228
2229 for_each_port(adapter, i)
2230 if (adapter->port[i] && adapter->port[i] != dev)
2231 other_qsets += adap2pinfo(adapter, i)->nqsets;
2232
2233 if (edata.val + other_qsets > SGE_QSETS)
2234 return -EINVAL;
2235
2236 pi->nqsets = edata.val;
2237
2238 for_each_port(adapter, i)
2239 if (adapter->port[i]) {
2240 pi = adap2pinfo(adapter, i);
2241 pi->first_qset = first_qset;
2242 first_qset += pi->nqsets;
2243 }
2244 break;
2245 }
2246 case CHELSIO_GET_QSET_NUM:{
2247 struct ch_reg edata;
4d22de3e
DLR		 2248
2249 edata.cmd = CHELSIO_GET_QSET_NUM;
2250 edata.val = pi->nqsets;
2251 if (copy_to_user(useraddr, &edata, sizeof(edata)))
2252 return -EFAULT;
2253 break;
2254 }
2255 case CHELSIO_LOAD_FW:{
2256 u8 *fw_data;
2257 struct ch_mem_range t;
2258
1b3aa7af 2259 if (!capable(CAP_SYS_RAWIO))
4d22de3e
DLR		 2260 return -EPERM;
2261 if (copy_from_user(&t, useraddr, sizeof(t)))
2262 return -EFAULT;
1b3aa7af 2263 /* Check t.len sanity ? */
4d22de3e
DLR		 2264 fw_data = kmalloc(t.len, GFP_KERNEL);
2265 if (!fw_data)
2266 return -ENOMEM;
2267
2268 if (copy_from_user
2269 (fw_data, useraddr + sizeof(t), t.len)) {
2270 kfree(fw_data);
2271 return -EFAULT;
2272 }
2273
2274 ret = t3_load_fw(adapter, fw_data, t.len);
2275 kfree(fw_data);
2276 if (ret)
2277 return ret;
2278 break;
2279 }
2280 case CHELSIO_SETMTUTAB:{
2281 struct ch_mtus m;
2282 int i;
2283
2284 if (!is_offload(adapter))
2285 return -EOPNOTSUPP;
2286 if (!capable(CAP_NET_ADMIN))
2287 return -EPERM;
2288 if (offload_running(adapter))
2289 return -EBUSY;
2290 if (copy_from_user(&m, useraddr, sizeof(m)))
2291 return -EFAULT;
2292 if (m.nmtus != NMTUS)
2293 return -EINVAL;
2294 if (m.mtus[0] < 81) /* accommodate SACK */
2295 return -EINVAL;
2296
2297 /* MTUs must be in ascending order */
2298 for (i = 1; i < NMTUS; ++i)
2299 if (m.mtus[i] < m.mtus[i - 1])
2300 return -EINVAL;
2301
2302 memcpy(adapter->params.mtus, m.mtus,
2303 sizeof(adapter->params.mtus));
2304 break;
2305 }
2306 case CHELSIO_GET_PM:{
2307 struct tp_params *p = &adapter->params.tp;
2308 struct ch_pm m = {.cmd = CHELSIO_GET_PM };
2309
2310 if (!is_offload(adapter))
2311 return -EOPNOTSUPP;
2312 m.tx_pg_sz = p->tx_pg_size;
2313 m.tx_num_pg = p->tx_num_pgs;
2314 m.rx_pg_sz = p->rx_pg_size;
2315 m.rx_num_pg = p->rx_num_pgs;
2316 m.pm_total = p->pmtx_size + p->chan_rx_size * p->nchan;
2317 if (copy_to_user(useraddr, &m, sizeof(m)))
2318 return -EFAULT;
2319 break;
2320 }
2321 case CHELSIO_SET_PM:{
2322 struct ch_pm m;
2323 struct tp_params *p = &adapter->params.tp;
2324
2325 if (!is_offload(adapter))
2326 return -EOPNOTSUPP;
2327 if (!capable(CAP_NET_ADMIN))
2328 return -EPERM;
2329 if (adapter->flags & FULL_INIT_DONE)
2330 return -EBUSY;
2331 if (copy_from_user(&m, useraddr, sizeof(m)))
2332 return -EFAULT;
d9da466a 2333 if (!is_power_of_2(m.rx_pg_sz) ||
2334 !is_power_of_2(m.tx_pg_sz))
4d22de3e
DLR		 2335 return -EINVAL; /* not power of 2 */
2336 if (!(m.rx_pg_sz & 0x14000))
2337 return -EINVAL; /* not 16KB or 64KB */
2338 if (!(m.tx_pg_sz & 0x1554000))
2339 return -EINVAL;
2340 if (m.tx_num_pg == -1)
2341 m.tx_num_pg = p->tx_num_pgs;
2342 if (m.rx_num_pg == -1)
2343 m.rx_num_pg = p->rx_num_pgs;
2344 if (m.tx_num_pg % 24 || m.rx_num_pg % 24)
2345 return -EINVAL;
2346 if (m.rx_num_pg * m.rx_pg_sz > p->chan_rx_size ||
2347 m.tx_num_pg * m.tx_pg_sz > p->chan_tx_size)
2348 return -EINVAL;
2349 p->rx_pg_size = m.rx_pg_sz;
2350 p->tx_pg_size = m.tx_pg_sz;
2351 p->rx_num_pgs = m.rx_num_pg;
2352 p->tx_num_pgs = m.tx_num_pg;
2353 break;
2354 }
2355 case CHELSIO_GET_MEM:{
2356 struct ch_mem_range t;
2357 struct mc7 *mem;
2358 u64 buf[32];
2359
2360 if (!is_offload(adapter))
2361 return -EOPNOTSUPP;
2362 if (!(adapter->flags & FULL_INIT_DONE))
2363 return -EIO; /* need the memory controllers */
2364 if (copy_from_user(&t, useraddr, sizeof(t)))
2365 return -EFAULT;
2366 if ((t.addr & 7) || (t.len & 7))
2367 return -EINVAL;
2368 if (t.mem_id == MEM_CM)
2369 mem = &adapter->cm;
2370 else if (t.mem_id == MEM_PMRX)
2371 mem = &adapter->pmrx;
2372 else if (t.mem_id == MEM_PMTX)
2373 mem = &adapter->pmtx;
2374 else
2375 return -EINVAL;
2376
2377 /*
1825494a
DLR		 2378 * Version scheme:
2379 * bits 0..9: chip version
2380 * bits 10..15: chip revision
2381 */
4d22de3e
DLR		 2382 t.version = 3 | (adapter->params.rev << 10);
2383 if (copy_to_user(useraddr, &t, sizeof(t)))
2384 return -EFAULT;
2385
2386 /*
2387 * Read 256 bytes at a time as len can be large and we don't
2388 * want to use huge intermediate buffers.
2389 */
2390 useraddr += sizeof(t); /* advance to start of buffer */
2391 while (t.len) {
2392 unsigned int chunk =
2393 min_t(unsigned int, t.len, sizeof(buf));
2394
2395 ret =
2396 t3_mc7_bd_read(mem, t.addr / 8, chunk / 8,
2397 buf);
2398 if (ret)
2399 return ret;
2400 if (copy_to_user(useraddr, buf, chunk))
2401 return -EFAULT;
2402 useraddr += chunk;
2403 t.addr += chunk;
2404 t.len -= chunk;
2405 }
2406 break;
2407 }
2408 case CHELSIO_SET_TRACE_FILTER:{
2409 struct ch_trace t;
2410 const struct trace_params *tp;
2411
2412 if (!capable(CAP_NET_ADMIN))
2413 return -EPERM;
2414 if (!offload_running(adapter))
2415 return -EAGAIN;
2416 if (copy_from_user(&t, useraddr, sizeof(t)))
2417 return -EFAULT;
2418
2419 tp = (const struct trace_params *)&t.sip;
2420 if (t.config_tx)
2421 t3_config_trace_filter(adapter, tp, 0,
2422 t.invert_match,
2423 t.trace_tx);
2424 if (t.config_rx)
2425 t3_config_trace_filter(adapter, tp, 1,
2426 t.invert_match,
2427 t.trace_rx);
2428 break;
2429 }
4d22de3e
DLR		 2430 default:
2431 return -EOPNOTSUPP;
2432 }
2433 return 0;
2434}
2435
2436static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2437{
4d22de3e 2438 struct mii_ioctl_data *data = if_mii(req);
5fbf816f
DLR		 2439 struct port_info *pi = netdev_priv(dev);
2440 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 2441
2442 switch (cmd) {
0f07c4ee
BH		 2443 case SIOCGMIIREG:
2444 case SIOCSMIIREG:
2445 /* Convert phy_id from older PRTAD/DEVAD format */
2446 if (is_10G(adapter) &&
2447 !mdio_phy_id_is_c45(data->phy_id) &&
2448 (data->phy_id & 0x1f00) &&
2449 !(data->phy_id & 0xe0e0))
2450 data->phy_id = mdio_phy_id_c45(data->phy_id >> 8,
2451 data->phy_id & 0x1f);
4d22de3e 2452 /* FALLTHRU */
0f07c4ee
BH		 2453 case SIOCGMIIPHY:
2454 return mdio_mii_ioctl(&pi->phy.mdio, data, cmd);
4d22de3e
DLR		 2455 case SIOCCHIOCTL:
2456 return cxgb_extension_ioctl(dev, req->ifr_data);
2457 default:
2458 return -EOPNOTSUPP;
2459 }
4d22de3e
DLR		 2460}
2461
2462static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2463{
4d22de3e 2464 struct port_info *pi = netdev_priv(dev);
5fbf816f
DLR		 2465 struct adapter *adapter = pi->adapter;
2466 int ret;
4d22de3e
DLR		 2467
2468 if (new_mtu < 81) /* accommodate SACK */
2469 return -EINVAL;
2470 if ((ret = t3_mac_set_mtu(&pi->mac, new_mtu)))
2471 return ret;
2472 dev->mtu = new_mtu;
2473 init_port_mtus(adapter);
2474 if (adapter->params.rev == 0 && offload_running(adapter))
2475 t3_load_mtus(adapter, adapter->params.mtus,
2476 adapter->params.a_wnd, adapter->params.b_wnd,
2477 adapter->port[0]->mtu);
2478 return 0;
2479}
2480
2481static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2482{
4d22de3e 2483 struct port_info *pi = netdev_priv(dev);
5fbf816f 2484 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 2485 struct sockaddr *addr = p;
2486
2487 if (!is_valid_ether_addr(addr->sa_data))
2488 return -EINVAL;
2489
2490 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2491 t3_mac_set_address(&pi->mac, 0, dev->dev_addr);
2492 if (offload_running(adapter))
2493 write_smt_entry(adapter, pi->port_id);
2494 return 0;
2495}
2496
2497/**
2498 * t3_synchronize_rx - wait for current Rx processing on a port to complete
2499 * @adap: the adapter
2500 * @p: the port
2501 *
2502 * Ensures that current Rx processing on any of the queues associated with
2503 * the given port completes before returning. We do this by acquiring and
2504 * releasing the locks of the response queues associated with the port.
2505 */
2506static void t3_synchronize_rx(struct adapter *adap, const struct port_info *p)
2507{
2508 int i;
2509
8c263761
DLR		 2510 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) {
2511 struct sge_rspq *q = &adap->sge.qs[i].rspq;
4d22de3e
DLR		 2512
2513 spin_lock_irq(&q->lock);
2514 spin_unlock_irq(&q->lock);
2515 }
2516}
2517
2518static void vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2519{
4d22de3e 2520 struct port_info *pi = netdev_priv(dev);
5fbf816f 2521 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 2522
2523 pi->vlan_grp = grp;
2524 if (adapter->params.rev > 0)
2525 t3_set_vlan_accel(adapter, 1 << pi->port_id, grp != NULL);
2526 else {
2527 /* single control for all ports */
2528 unsigned int i, have_vlans = 0;
2529 for_each_port(adapter, i)
2530 have_vlans |= adap2pinfo(adapter, i)->vlan_grp != NULL;
2531
2532 t3_set_vlan_accel(adapter, 1, have_vlans);
2533 }
2534 t3_synchronize_rx(adapter, pi);
2535}
2536
4d22de3e
DLR		 2537#ifdef CONFIG_NET_POLL_CONTROLLER
2538static void cxgb_netpoll(struct net_device *dev)
2539{
890de332 2540 struct port_info *pi = netdev_priv(dev);
5fbf816f 2541 struct adapter *adapter = pi->adapter;
890de332 2542 int qidx;
4d22de3e 2543
890de332
DLR		 2544 for (qidx = pi->first_qset; qidx < pi->first_qset + pi->nqsets; qidx++) {
2545 struct sge_qset *qs = &adapter->sge.qs[qidx];
2546 void *source;
2eab17ab 2547
890de332
DLR		 2548 if (adapter->flags & USING_MSIX)
2549 source = qs;
2550 else
2551 source = adapter;
2552
2553 t3_intr_handler(adapter, qs->rspq.polling) (0, source);
2554 }
4d22de3e
DLR		 2555}
2556#endif
2557
2558/*
2559 * Periodic accumulation of MAC statistics.
2560 */
2561static void mac_stats_update(struct adapter *adapter)
2562{
2563 int i;
2564
2565 for_each_port(adapter, i) {
2566 struct net_device *dev = adapter->port[i];
2567 struct port_info *p = netdev_priv(dev);
2568
2569 if (netif_running(dev)) {
2570 spin_lock(&adapter->stats_lock);
2571 t3_mac_update_stats(&p->mac);
2572 spin_unlock(&adapter->stats_lock);
2573 }
2574 }
2575}
2576
2577static void check_link_status(struct adapter *adapter)
2578{
2579 int i;
2580
2581 for_each_port(adapter, i) {
2582 struct net_device *dev = adapter->port[i];
2583 struct port_info *p = netdev_priv(dev);
c22c8149 2584 int link_fault;
4d22de3e 2585
bf792094 2586 spin_lock_irq(&adapter->work_lock);
c22c8149
DLR		 2587 link_fault = p->link_fault;
2588 spin_unlock_irq(&adapter->work_lock);
2589
2590 if (link_fault) {
3851c66c 2591 t3_link_fault(adapter, i);
bf792094
DLR		 2592 continue;
2593 }
bf792094
DLR		 2594
2595 if (!(p->phy.caps & SUPPORTED_IRQ) && netif_running(dev)) {
2596 t3_xgm_intr_disable(adapter, i);
2597 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2598
4d22de3e 2599 t3_link_changed(adapter, i);
bf792094
DLR		 2600 t3_xgm_intr_enable(adapter, i);
2601 }
4d22de3e
DLR		 2602 }
2603}
2604
fc90664e
DLR		 2605static void check_t3b2_mac(struct adapter *adapter)
2606{
2607 int i;
2608
f2d961c9
DLR		 2609 if (!rtnl_trylock()) /* synchronize with ifdown */
2610 return;
2611
fc90664e
DLR		 2612 for_each_port(adapter, i) {
2613 struct net_device *dev = adapter->port[i];
2614 struct port_info *p = netdev_priv(dev);
2615 int status;
2616
2617 if (!netif_running(dev))
2618 continue;
2619
2620 status = 0;
6d6dabac 2621 if (netif_running(dev) && netif_carrier_ok(dev))
fc90664e
DLR		 2622 status = t3b2_mac_watchdog_task(&p->mac);
2623 if (status == 1)
2624 p->mac.stats.num_toggled++;
2625 else if (status == 2) {
2626 struct cmac *mac = &p->mac;
2627
2628 t3_mac_set_mtu(mac, dev->mtu);
2629 t3_mac_set_address(mac, 0, dev->dev_addr);
2630 cxgb_set_rxmode(dev);
2631 t3_link_start(&p->phy, mac, &p->link_config);
2632 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
2633 t3_port_intr_enable(adapter, p->port_id);
2634 p->mac.stats.num_resets++;
2635 }
2636 }
2637 rtnl_unlock();
2638}
2639
2640
4d22de3e
DLR		 2641static void t3_adap_check_task(struct work_struct *work)
2642{
2643 struct adapter *adapter = container_of(work, struct adapter,
2644 adap_check_task.work);
2645 const struct adapter_params *p = &adapter->params;
fc882196
DLR		 2646 int port;
2647 unsigned int v, status, reset;
4d22de3e
DLR		 2648
2649 adapter->check_task_cnt++;
2650
3851c66c 2651 check_link_status(adapter);
4d22de3e
DLR		 2652
2653 /* Accumulate MAC stats if needed */
2654 if (!p->linkpoll_period ||
2655 (adapter->check_task_cnt * p->linkpoll_period) / 10 >=
2656 p->stats_update_period) {
2657 mac_stats_update(adapter);
2658 adapter->check_task_cnt = 0;
2659 }
2660
fc90664e
DLR		 2661 if (p->rev == T3_REV_B2)
2662 check_t3b2_mac(adapter);
2663
fc882196
DLR		 2664 /*
2665 * Scan the XGMAC's to check for various conditions which we want to
2666 * monitor in a periodic polling manner rather than via an interrupt
2667 * condition. This is used for conditions which would otherwise flood
2668 * the system with interrupts and we only really need to know that the
2669 * conditions are "happening" ... For each condition we count the
2670 * detection of the condition and reset it for the next polling loop.
2671 */
2672 for_each_port(adapter, port) {
2673 struct cmac *mac = &adap2pinfo(adapter, port)->mac;
2674 u32 cause;
2675
2676 cause = t3_read_reg(adapter, A_XGM_INT_CAUSE + mac->offset);
2677 reset = 0;
2678 if (cause & F_RXFIFO_OVERFLOW) {
2679 mac->stats.rx_fifo_ovfl++;
2680 reset |= F_RXFIFO_OVERFLOW;
2681 }
2682
2683 t3_write_reg(adapter, A_XGM_INT_CAUSE + mac->offset, reset);
2684 }
2685
2686 /*
2687 * We do the same as above for FL_EMPTY interrupts.
2688 */
2689 status = t3_read_reg(adapter, A_SG_INT_CAUSE);
2690 reset = 0;
2691
2692 if (status & F_FLEMPTY) {
2693 struct sge_qset *qs = &adapter->sge.qs[0];
2694 int i = 0;
2695
2696 reset |= F_FLEMPTY;
2697
2698 v = (t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS) >> S_FL0EMPTY) &
2699 0xffff;
2700
2701 while (v) {
2702 qs->fl[i].empty += (v & 1);
2703 if (i)
2704 qs++;
2705 i ^= 1;
2706 v >>= 1;
2707 }
2708 }
2709
2710 t3_write_reg(adapter, A_SG_INT_CAUSE, reset);
2711
4d22de3e 2712 /* Schedule the next check update if any port is active. */
20d3fc11 2713 spin_lock_irq(&adapter->work_lock);
4d22de3e
DLR		 2714 if (adapter->open_device_map & PORT_MASK)
2715 schedule_chk_task(adapter);
20d3fc11 2716 spin_unlock_irq(&adapter->work_lock);
4d22de3e
DLR		 2717}
2718
2719/*
2720 * Processes external (PHY) interrupts in process context.
2721 */
2722static void ext_intr_task(struct work_struct *work)
2723{
2724 struct adapter *adapter = container_of(work, struct adapter,
2725 ext_intr_handler_task);
bf792094
DLR		 2726 int i;
2727
2728 /* Disable link fault interrupts */
2729 for_each_port(adapter, i) {
2730 struct net_device *dev = adapter->port[i];
2731 struct port_info *p = netdev_priv(dev);
2732
2733 t3_xgm_intr_disable(adapter, i);
2734 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2735 }
4d22de3e 2736
bf792094 2737 /* Re-enable link fault interrupts */
4d22de3e
DLR		 2738 t3_phy_intr_handler(adapter);
2739
bf792094
DLR		 2740 for_each_port(adapter, i)
2741 t3_xgm_intr_enable(adapter, i);
2742
4d22de3e
DLR		 2743 /* Now reenable external interrupts */
2744 spin_lock_irq(&adapter->work_lock);
2745 if (adapter->slow_intr_mask) {
2746 adapter->slow_intr_mask |= F_T3DBG;
2747 t3_write_reg(adapter, A_PL_INT_CAUSE0, F_T3DBG);
2748 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2749 adapter->slow_intr_mask);
2750 }
2751 spin_unlock_irq(&adapter->work_lock);
2752}
2753
2754/*
2755 * Interrupt-context handler for external (PHY) interrupts.
2756 */
2757void t3_os_ext_intr_handler(struct adapter *adapter)
2758{
2759 /*
2760 * Schedule a task to handle external interrupts as they may be slow
2761 * and we use a mutex to protect MDIO registers. We disable PHY
2762 * interrupts in the meantime and let the task reenable them when
2763 * it's done.
2764 */
2765 spin_lock(&adapter->work_lock);
2766 if (adapter->slow_intr_mask) {
2767 adapter->slow_intr_mask &= ~F_T3DBG;
2768 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2769 adapter->slow_intr_mask);
2770 queue_work(cxgb3_wq, &adapter->ext_intr_handler_task);
2771 }
2772 spin_unlock(&adapter->work_lock);
2773}
2774
bf792094
DLR		 2775void t3_os_link_fault_handler(struct adapter *adapter, int port_id)
2776{
2777 struct net_device *netdev = adapter->port[port_id];
2778 struct port_info *pi = netdev_priv(netdev);
2779
2780 spin_lock(&adapter->work_lock);
2781 pi->link_fault = 1;
bf792094
DLR		 2782 spin_unlock(&adapter->work_lock);
2783}
2784
20d3fc11
DLR		 2785static int t3_adapter_error(struct adapter *adapter, int reset)
2786{
2787 int i, ret = 0;
2788
cb0bc205
DLR		 2789 if (is_offload(adapter) &&
2790 test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2791 cxgb3_err_notify(&adapter->tdev, OFFLOAD_STATUS_DOWN, 0);
2792 offload_close(&adapter->tdev);
2793 }
2794
20d3fc11
DLR		 2795 /* Stop all ports */
2796 for_each_port(adapter, i) {
2797 struct net_device *netdev = adapter->port[i];
2798
2799 if (netif_running(netdev))
2800 cxgb_close(netdev);
2801 }
2802
20d3fc11
DLR		 2803 /* Stop SGE timers */
2804 t3_stop_sge_timers(adapter);
2805
2806 adapter->flags &= ~FULL_INIT_DONE;
2807
2808 if (reset)
2809 ret = t3_reset_adapter(adapter);
2810
2811 pci_disable_device(adapter->pdev);
2812
2813 return ret;
2814}
2815
2816static int t3_reenable_adapter(struct adapter *adapter)
2817{
2818 if (pci_enable_device(adapter->pdev)) {
2819 dev_err(&adapter->pdev->dev,
2820 "Cannot re-enable PCI device after reset.\n");
2821 goto err;
2822 }
2823 pci_set_master(adapter->pdev);
2824 pci_restore_state(adapter->pdev);
2825
2826 /* Free sge resources */
2827 t3_free_sge_resources(adapter);
2828
2829 if (t3_replay_prep_adapter(adapter))
2830 goto err;
2831
2832 return 0;
2833err:
2834 return -1;
2835}
2836
2837static void t3_resume_ports(struct adapter *adapter)
2838{
2839 int i;
2840
2841 /* Restart the ports */
2842 for_each_port(adapter, i) {
2843 struct net_device *netdev = adapter->port[i];
2844
2845 if (netif_running(netdev)) {
2846 if (cxgb_open(netdev)) {
2847 dev_err(&adapter->pdev->dev,
2848 "can't bring device back up"
2849 " after reset\n");
2850 continue;
2851 }
2852 }
2853 }
cb0bc205
DLR		 2854
2855 if (is_offload(adapter) && !ofld_disable)
2856 cxgb3_err_notify(&adapter->tdev, OFFLOAD_STATUS_UP, 0);
20d3fc11
DLR		 2857}
2858
2859/*
2860 * processes a fatal error.
2861 * Bring the ports down, reset the chip, bring the ports back up.
2862 */
2863static void fatal_error_task(struct work_struct *work)
2864{
2865 struct adapter *adapter = container_of(work, struct adapter,
2866 fatal_error_handler_task);
2867 int err = 0;
2868
2869 rtnl_lock();
2870 err = t3_adapter_error(adapter, 1);
2871 if (!err)
2872 err = t3_reenable_adapter(adapter);
2873 if (!err)
2874 t3_resume_ports(adapter);
2875
2876 CH_ALERT(adapter, "adapter reset %s\n", err ? "failed" : "succeeded");
2877 rtnl_unlock();
2878}
2879
4d22de3e
DLR		 2880void t3_fatal_err(struct adapter *adapter)
2881{
2882 unsigned int fw_status[4];
2883
2884 if (adapter->flags & FULL_INIT_DONE) {
2885 t3_sge_stop(adapter);
c64c2eae
DLR		 2886 t3_write_reg(adapter, A_XGM_TX_CTRL, 0);
2887 t3_write_reg(adapter, A_XGM_RX_CTRL, 0);
2888 t3_write_reg(adapter, XGM_REG(A_XGM_TX_CTRL, 1), 0);
2889 t3_write_reg(adapter, XGM_REG(A_XGM_RX_CTRL, 1), 0);
20d3fc11
DLR		 2890
2891 spin_lock(&adapter->work_lock);
4d22de3e 2892 t3_intr_disable(adapter);
20d3fc11
DLR		 2893 queue_work(cxgb3_wq, &adapter->fatal_error_handler_task);
2894 spin_unlock(&adapter->work_lock);
4d22de3e
DLR		 2895 }
2896 CH_ALERT(adapter, "encountered fatal error, operation suspended\n");
2897 if (!t3_cim_ctl_blk_read(adapter, 0xa0, 4, fw_status))
2898 CH_ALERT(adapter, "FW status: 0x%x, 0x%x, 0x%x, 0x%x\n",
2899 fw_status[0], fw_status[1],
2900 fw_status[2], fw_status[3]);
4d22de3e
DLR		 2901}
2902
91a6b50c
DLR		 2903/**
2904 * t3_io_error_detected - called when PCI error is detected
2905 * @pdev: Pointer to PCI device
2906 * @state: The current pci connection state
2907 *
2908 * This function is called after a PCI bus error affecting
2909 * this device has been detected.
2910 */
2911static pci_ers_result_t t3_io_error_detected(struct pci_dev *pdev,
2912 pci_channel_state_t state)
2913{
bc4b6b52 2914 struct adapter *adapter = pci_get_drvdata(pdev);
20d3fc11 2915 int ret;
91a6b50c 2916
e8d19370
DLR		 2917 if (state == pci_channel_io_perm_failure)
2918 return PCI_ERS_RESULT_DISCONNECT;
2919
20d3fc11 2920 ret = t3_adapter_error(adapter, 0);
91a6b50c 2921
48c4b6db 2922 /* Request a slot reset. */
91a6b50c
DLR		 2923 return PCI_ERS_RESULT_NEED_RESET;
2924}
2925
2926/**
2927 * t3_io_slot_reset - called after the pci bus has been reset.
2928 * @pdev: Pointer to PCI device
2929 *
2930 * Restart the card from scratch, as if from a cold-boot.
2931 */
2932static pci_ers_result_t t3_io_slot_reset(struct pci_dev *pdev)
2933{
bc4b6b52 2934 struct adapter *adapter = pci_get_drvdata(pdev);
91a6b50c 2935
20d3fc11
DLR		 2936 if (!t3_reenable_adapter(adapter))
2937 return PCI_ERS_RESULT_RECOVERED;
91a6b50c 2938
48c4b6db 2939 return PCI_ERS_RESULT_DISCONNECT;
91a6b50c
DLR		 2940}
2941
2942/**
2943 * t3_io_resume - called when traffic can start flowing again.
2944 * @pdev: Pointer to PCI device
2945 *
2946 * This callback is called when the error recovery driver tells us that
2947 * its OK to resume normal operation.
2948 */
2949static void t3_io_resume(struct pci_dev *pdev)
2950{
bc4b6b52 2951 struct adapter *adapter = pci_get_drvdata(pdev);
91a6b50c 2952
68f40c10
DLR		 2953 CH_ALERT(adapter, "adapter recovering, PEX ERR 0x%x\n",
2954 t3_read_reg(adapter, A_PCIE_PEX_ERR));
2955
20d3fc11 2956 t3_resume_ports(adapter);
91a6b50c
DLR		 2957}
2958
2959static struct pci_error_handlers t3_err_handler = {
2960 .error_detected = t3_io_error_detected,
2961 .slot_reset = t3_io_slot_reset,
2962 .resume = t3_io_resume,
2963};
2964
8c263761
DLR		 2965/*
2966 * Set the number of qsets based on the number of CPUs and the number of ports,
2967 * not to exceed the number of available qsets, assuming there are enough qsets
2968 * per port in HW.
2969 */
2970static void set_nqsets(struct adapter *adap)
2971{
2972 int i, j = 0;
2973 int num_cpus = num_online_cpus();
2974 int hwports = adap->params.nports;
5cda9364 2975 int nqsets = adap->msix_nvectors - 1;
8c263761 2976
f9ee3882 2977 if (adap->params.rev > 0 && adap->flags & USING_MSIX) {
8c263761
DLR		 2978 if (hwports == 2 &&
2979 (hwports * nqsets > SGE_QSETS ||
2980 num_cpus >= nqsets / hwports))
2981 nqsets /= hwports;
2982 if (nqsets > num_cpus)
2983 nqsets = num_cpus;
2984 if (nqsets < 1 || hwports == 4)
2985 nqsets = 1;
2986 } else
2987 nqsets = 1;
2988
2989 for_each_port(adap, i) {
2990 struct port_info *pi = adap2pinfo(adap, i);
2991
2992 pi->first_qset = j;
2993 pi->nqsets = nqsets;
2994 j = pi->first_qset + nqsets;
2995
2996 dev_info(&adap->pdev->dev,
2997 "Port %d using %d queue sets.\n", i, nqsets);
2998 }
2999}
3000
4d22de3e
DLR		 3001static int __devinit cxgb_enable_msix(struct adapter *adap)
3002{
3003 struct msix_entry entries[SGE_QSETS + 1];
5cda9364 3004 int vectors;
4d22de3e
DLR		 3005 int i, err;
3006
5cda9364
DLR		 3007 vectors = ARRAY_SIZE(entries);
3008 for (i = 0; i < vectors; ++i)
4d22de3e
DLR		 3009 entries[i].entry = i;
3010
5cda9364
DLR		 3011 while ((err = pci_enable_msix(adap->pdev, entries, vectors)) > 0)
3012 vectors = err;
3013
2c2f409f
DLR		 3014 if (err < 0)
3015 pci_disable_msix(adap->pdev);
3016
3017 if (!err && vectors < (adap->params.nports + 1)) {
3018 pci_disable_msix(adap->pdev);
5cda9364 3019 err = -1;
2c2f409f 3020 }
5cda9364 3021
4d22de3e 3022 if (!err) {
5cda9364 3023 for (i = 0; i < vectors; ++i)
4d22de3e 3024 adap->msix_info[i].vec = entries[i].vector;
5cda9364
DLR		 3025 adap->msix_nvectors = vectors;
3026 }
3027
4d22de3e
DLR		 3028 return err;
3029}
3030
3031static void __devinit print_port_info(struct adapter *adap,
3032 const struct adapter_info *ai)
3033{
3034 static const char *pci_variant[] = {
3035 "PCI", "PCI-X", "PCI-X ECC", "PCI-X 266", "PCI Express"
3036 };
3037
3038 int i;
3039 char buf[80];
3040
3041 if (is_pcie(adap))
3042 snprintf(buf, sizeof(buf), "%s x%d",
3043 pci_variant[adap->params.pci.variant],
3044 adap->params.pci.width);
3045 else
3046 snprintf(buf, sizeof(buf), "%s %dMHz/%d-bit",
3047 pci_variant[adap->params.pci.variant],
3048 adap->params.pci.speed, adap->params.pci.width);
3049
3050 for_each_port(adap, i) {
3051 struct net_device *dev = adap->port[i];
3052 const struct port_info *pi = netdev_priv(dev);
3053
3054 if (!test_bit(i, &adap->registered_device_map))
3055 continue;
8ac3ba68 3056 printk(KERN_INFO "%s: %s %s %sNIC (rev %d) %s%s\n",
04497982 3057 dev->name, ai->desc, pi->phy.desc,
8ac3ba68 3058 is_offload(adap) ? "R" : "", adap->params.rev, buf,
4d22de3e
DLR		 3059 (adap->flags & USING_MSIX) ? " MSI-X" :
3060 (adap->flags & USING_MSI) ? " MSI" : "");
3061 if (adap->name == dev->name && adap->params.vpd.mclk)
167cdf5f
DLR		 3062 printk(KERN_INFO
3063 "%s: %uMB CM, %uMB PMTX, %uMB PMRX, S/N: %s\n",
4d22de3e
DLR		 3064 adap->name, t3_mc7_size(&adap->cm) >> 20,
3065 t3_mc7_size(&adap->pmtx) >> 20,
167cdf5f
DLR		 3066 t3_mc7_size(&adap->pmrx) >> 20,
3067 adap->params.vpd.sn);
4d22de3e
DLR		 3068 }
3069}
3070
dd752696
SH		 3071static const struct net_device_ops cxgb_netdev_ops = {
3072 .ndo_open = cxgb_open,
3073 .ndo_stop = cxgb_close,
43a944f3 3074 .ndo_start_xmit = t3_eth_xmit,
dd752696
SH		 3075 .ndo_get_stats = cxgb_get_stats,
3076 .ndo_validate_addr = eth_validate_addr,
3077 .ndo_set_multicast_list = cxgb_set_rxmode,
3078 .ndo_do_ioctl = cxgb_ioctl,
3079 .ndo_change_mtu = cxgb_change_mtu,
3080 .ndo_set_mac_address = cxgb_set_mac_addr,
3081 .ndo_vlan_rx_register = vlan_rx_register,
3082#ifdef CONFIG_NET_POLL_CONTROLLER
3083 .ndo_poll_controller = cxgb_netpoll,
3084#endif
3085};
3086
4d22de3e
DLR		 3087static int __devinit init_one(struct pci_dev *pdev,
3088 const struct pci_device_id *ent)
3089{
3090 static int version_printed;
3091
3092 int i, err, pci_using_dac = 0;
68f40c10 3093 resource_size_t mmio_start, mmio_len;
4d22de3e
DLR		 3094 const struct adapter_info *ai;
3095 struct adapter *adapter = NULL;
3096 struct port_info *pi;
3097
3098 if (!version_printed) {
3099 printk(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
3100 ++version_printed;
3101 }
3102
3103 if (!cxgb3_wq) {
3104 cxgb3_wq = create_singlethread_workqueue(DRV_NAME);
3105 if (!cxgb3_wq) {
3106 printk(KERN_ERR DRV_NAME
3107 ": cannot initialize work queue\n");
3108 return -ENOMEM;
3109 }
3110 }
3111
3112 err = pci_request_regions(pdev, DRV_NAME);
3113 if (err) {
3114 /* Just info, some other driver may have claimed the device. */
3115 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
3116 return err;
3117 }
3118
3119 err = pci_enable_device(pdev);
3120 if (err) {
3121 dev_err(&pdev->dev, "cannot enable PCI device\n");
3122 goto out_release_regions;
3123 }
3124
6a35528a 3125 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4d22de3e 3126 pci_using_dac = 1;
6a35528a 3127 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4d22de3e
DLR		 3128 if (err) {
3129 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
3130 "coherent allocations\n");
3131 goto out_disable_device;
3132 }
284901a9 3133 } else if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
4d22de3e
DLR		 3134 dev_err(&pdev->dev, "no usable DMA configuration\n");
3135 goto out_disable_device;
3136 }
3137
3138 pci_set_master(pdev);
204e2f98 3139 pci_save_state(pdev);
4d22de3e
DLR		 3140
3141 mmio_start = pci_resource_start(pdev, 0);
3142 mmio_len = pci_resource_len(pdev, 0);
3143 ai = t3_get_adapter_info(ent->driver_data);
3144
3145 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
3146 if (!adapter) {
3147 err = -ENOMEM;
3148 goto out_disable_device;
3149 }
3150
74b793e1
DLR		 3151 adapter->nofail_skb =
3152 alloc_skb(sizeof(struct cpl_set_tcb_field), GFP_KERNEL);
3153 if (!adapter->nofail_skb) {
3154 dev_err(&pdev->dev, "cannot allocate nofail buffer\n");
3155 err = -ENOMEM;
3156 goto out_free_adapter;
3157 }
3158
4d22de3e
DLR		 3159 adapter->regs = ioremap_nocache(mmio_start, mmio_len);
3160 if (!adapter->regs) {
3161 dev_err(&pdev->dev, "cannot map device registers\n");
3162 err = -ENOMEM;
3163 goto out_free_adapter;
3164 }
3165
3166 adapter->pdev = pdev;
3167 adapter->name = pci_name(pdev);
3168 adapter->msg_enable = dflt_msg_enable;
3169 adapter->mmio_len = mmio_len;
3170
3171 mutex_init(&adapter->mdio_lock);
3172 spin_lock_init(&adapter->work_lock);
3173 spin_lock_init(&adapter->stats_lock);
3174
3175 INIT_LIST_HEAD(&adapter->adapter_list);
3176 INIT_WORK(&adapter->ext_intr_handler_task, ext_intr_task);
20d3fc11 3177 INIT_WORK(&adapter->fatal_error_handler_task, fatal_error_task);
4d22de3e
DLR		 3178 INIT_DELAYED_WORK(&adapter->adap_check_task, t3_adap_check_task);
3179
952cdf33 3180 for (i = 0; i < ai->nports0 + ai->nports1; ++i) {
4d22de3e
DLR		 3181 struct net_device *netdev;
3182
82ad3329 3183 netdev = alloc_etherdev_mq(sizeof(struct port_info), SGE_QSETS);
4d22de3e
DLR		 3184 if (!netdev) {
3185 err = -ENOMEM;
3186 goto out_free_dev;
3187 }
3188
4d22de3e
DLR		 3189 SET_NETDEV_DEV(netdev, &pdev->dev);
3190
3191 adapter->port[i] = netdev;
3192 pi = netdev_priv(netdev);
5fbf816f 3193 pi->adapter = adapter;
47fd23fe 3194 pi->rx_offload = T3_RX_CSUM | T3_LRO;
4d22de3e
DLR		 3195 pi->port_id = i;
3196 netif_carrier_off(netdev);
82ad3329 3197 netif_tx_stop_all_queues(netdev);
4d22de3e
DLR		 3198 netdev->irq = pdev->irq;
3199 netdev->mem_start = mmio_start;
3200 netdev->mem_end = mmio_start + mmio_len - 1;
4d22de3e 3201 netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
7be2df45 3202 netdev->features |= NETIF_F_GRO;
4d22de3e
DLR		 3203 if (pci_using_dac)
3204 netdev->features |= NETIF_F_HIGHDMA;
3205
3206 netdev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
dd752696 3207 netdev->netdev_ops = &cxgb_netdev_ops;
4d22de3e
DLR		 3208 SET_ETHTOOL_OPS(netdev, &cxgb_ethtool_ops);
3209 }
3210
5fbf816f 3211 pci_set_drvdata(pdev, adapter);
4d22de3e
DLR		 3212 if (t3_prep_adapter(adapter, ai, 1) < 0) {
3213 err = -ENODEV;
3214 goto out_free_dev;
3215 }
2eab17ab 3216
4d22de3e
DLR		 3217 /*
3218 * The card is now ready to go. If any errors occur during device
3219 * registration we do not fail the whole card but rather proceed only
3220 * with the ports we manage to register successfully. However we must
3221 * register at least one net device.
3222 */
3223 for_each_port(adapter, i) {
3224 err = register_netdev(adapter->port[i]);
3225 if (err)
3226 dev_warn(&pdev->dev,
3227 "cannot register net device %s, skipping\n",
3228 adapter->port[i]->name);
3229 else {
3230 /*
3231 * Change the name we use for messages to the name of
3232 * the first successfully registered interface.
3233 */
3234 if (!adapter->registered_device_map)
3235 adapter->name = adapter->port[i]->name;
3236
3237 __set_bit(i, &adapter->registered_device_map);
3238 }
3239 }
3240 if (!adapter->registered_device_map) {
3241 dev_err(&pdev->dev, "could not register any net devices\n");
3242 goto out_free_dev;
3243 }
3244
3245 /* Driver's ready. Reflect it on LEDs */
3246 t3_led_ready(adapter);
3247
3248 if (is_offload(adapter)) {
3249 __set_bit(OFFLOAD_DEVMAP_BIT, &adapter->registered_device_map);
3250 cxgb3_adapter_ofld(adapter);
3251 }
3252
3253 /* See what interrupts we'll be using */
3254 if (msi > 1 && cxgb_enable_msix(adapter) == 0)
3255 adapter->flags |= USING_MSIX;
3256 else if (msi > 0 && pci_enable_msi(pdev) == 0)
3257 adapter->flags |= USING_MSI;
3258
8c263761
DLR		 3259 set_nqsets(adapter);
3260
0ee8d33c 3261 err = sysfs_create_group(&adapter->port[0]->dev.kobj,
4d22de3e
DLR		 3262 &cxgb3_attr_group);
3263
3264 print_port_info(adapter, ai);
3265 return 0;
3266
3267out_free_dev:
3268 iounmap(adapter->regs);
952cdf33 3269 for (i = ai->nports0 + ai->nports1 - 1; i >= 0; --i)
4d22de3e
DLR		 3270 if (adapter->port[i])
3271 free_netdev(adapter->port[i]);
3272
3273out_free_adapter:
3274 kfree(adapter);
3275
3276out_disable_device:
3277 pci_disable_device(pdev);
3278out_release_regions:
3279 pci_release_regions(pdev);
3280 pci_set_drvdata(pdev, NULL);
3281 return err;
3282}
3283
3284static void __devexit remove_one(struct pci_dev *pdev)
3285{
5fbf816f 3286 struct adapter *adapter = pci_get_drvdata(pdev);
4d22de3e 3287
5fbf816f 3288 if (adapter) {
4d22de3e 3289 int i;
4d22de3e
DLR		 3290
3291 t3_sge_stop(adapter);
0ee8d33c 3292 sysfs_remove_group(&adapter->port[0]->dev.kobj,
4d22de3e
DLR		 3293 &cxgb3_attr_group);
3294
4d22de3e
DLR		 3295 if (is_offload(adapter)) {
3296 cxgb3_adapter_unofld(adapter);
3297 if (test_bit(OFFLOAD_DEVMAP_BIT,
3298 &adapter->open_device_map))
3299 offload_close(&adapter->tdev);
3300 }
3301
67d92ab7
DLR		 3302 for_each_port(adapter, i)
3303 if (test_bit(i, &adapter->registered_device_map))
3304 unregister_netdev(adapter->port[i]);
3305
0ca41c04 3306 t3_stop_sge_timers(adapter);
4d22de3e
DLR		 3307 t3_free_sge_resources(adapter);
3308 cxgb_disable_msi(adapter);
3309
4d22de3e
DLR		 3310 for_each_port(adapter, i)
3311 if (adapter->port[i])
3312 free_netdev(adapter->port[i]);
3313
3314 iounmap(adapter->regs);
74b793e1
DLR		 3315 if (adapter->nofail_skb)
3316 kfree_skb(adapter->nofail_skb);
4d22de3e
DLR		 3317 kfree(adapter);
3318 pci_release_regions(pdev);
3319 pci_disable_device(pdev);
3320 pci_set_drvdata(pdev, NULL);
3321 }
3322}
3323
3324static struct pci_driver driver = {
3325 .name = DRV_NAME,
3326 .id_table = cxgb3_pci_tbl,
3327 .probe = init_one,
3328 .remove = __devexit_p(remove_one),
91a6b50c 3329 .err_handler = &t3_err_handler,
4d22de3e
DLR		 3330};
3331
3332static int __init cxgb3_init_module(void)
3333{
3334 int ret;
3335
3336 cxgb3_offload_init();
3337
3338 ret = pci_register_driver(&driver);
3339 return ret;
3340}
3341
3342static void __exit cxgb3_cleanup_module(void)
3343{
3344 pci_unregister_driver(&driver);
3345 if (cxgb3_wq)
3346 destroy_workqueue(cxgb3_wq);
3347}
3348
3349module_init(cxgb3_init_module);
3350module_exit(cxgb3_cleanup_module);
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