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Commit | Line | Data |
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91da11f8 | 1 | /* |
0d3cd4b6 VD |
2 | * Marvell 88e6xxx Ethernet switch single-chip support |
3 | * | |
91da11f8 LB |
4 | * Copyright (c) 2008 Marvell Semiconductor |
5 | * | |
b8fee957 VD |
6 | * Copyright (c) 2015 CMC Electronics, Inc. |
7 | * Added support for VLAN Table Unit operations | |
8 | * | |
14c7b3c3 AL |
9 | * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> |
10 | * | |
91da11f8 LB |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
19b2f97e | 17 | #include <linux/delay.h> |
defb05b9 | 18 | #include <linux/etherdevice.h> |
dea87024 | 19 | #include <linux/ethtool.h> |
facd95b2 | 20 | #include <linux/if_bridge.h> |
dc30c35b AL |
21 | #include <linux/interrupt.h> |
22 | #include <linux/irq.h> | |
23 | #include <linux/irqdomain.h> | |
19b2f97e | 24 | #include <linux/jiffies.h> |
91da11f8 | 25 | #include <linux/list.h> |
14c7b3c3 | 26 | #include <linux/mdio.h> |
2bbba277 | 27 | #include <linux/module.h> |
caac8545 | 28 | #include <linux/of_device.h> |
dc30c35b | 29 | #include <linux/of_irq.h> |
b516d453 | 30 | #include <linux/of_mdio.h> |
91da11f8 | 31 | #include <linux/netdevice.h> |
c8c1b39a | 32 | #include <linux/gpio/consumer.h> |
91da11f8 | 33 | #include <linux/phy.h> |
c8f0b869 | 34 | #include <net/dsa.h> |
1f36faf2 | 35 | #include <net/switchdev.h> |
ec561276 | 36 | |
91da11f8 | 37 | #include "mv88e6xxx.h" |
a935c052 | 38 | #include "global1.h" |
ec561276 | 39 | #include "global2.h" |
18abed21 | 40 | #include "port.h" |
91da11f8 | 41 | |
fad09c73 | 42 | static void assert_reg_lock(struct mv88e6xxx_chip *chip) |
3996a4ff | 43 | { |
fad09c73 VD |
44 | if (unlikely(!mutex_is_locked(&chip->reg_lock))) { |
45 | dev_err(chip->dev, "Switch registers lock not held!\n"); | |
3996a4ff VD |
46 | dump_stack(); |
47 | } | |
48 | } | |
49 | ||
914b32f6 VD |
50 | /* The switch ADDR[4:1] configuration pins define the chip SMI device address |
51 | * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). | |
52 | * | |
53 | * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it | |
54 | * is the only device connected to the SMI master. In this mode it responds to | |
55 | * all 32 possible SMI addresses, and thus maps directly the internal devices. | |
56 | * | |
57 | * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing | |
58 | * multiple devices to share the SMI interface. In this mode it responds to only | |
59 | * 2 registers, used to indirectly access the internal SMI devices. | |
91da11f8 | 60 | */ |
914b32f6 | 61 | |
fad09c73 | 62 | static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
63 | int addr, int reg, u16 *val) |
64 | { | |
fad09c73 | 65 | if (!chip->smi_ops) |
914b32f6 VD |
66 | return -EOPNOTSUPP; |
67 | ||
fad09c73 | 68 | return chip->smi_ops->read(chip, addr, reg, val); |
914b32f6 VD |
69 | } |
70 | ||
fad09c73 | 71 | static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
72 | int addr, int reg, u16 val) |
73 | { | |
fad09c73 | 74 | if (!chip->smi_ops) |
914b32f6 VD |
75 | return -EOPNOTSUPP; |
76 | ||
fad09c73 | 77 | return chip->smi_ops->write(chip, addr, reg, val); |
914b32f6 VD |
78 | } |
79 | ||
fad09c73 | 80 | static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
81 | int addr, int reg, u16 *val) |
82 | { | |
83 | int ret; | |
84 | ||
fad09c73 | 85 | ret = mdiobus_read_nested(chip->bus, addr, reg); |
914b32f6 VD |
86 | if (ret < 0) |
87 | return ret; | |
88 | ||
89 | *val = ret & 0xffff; | |
90 | ||
91 | return 0; | |
92 | } | |
93 | ||
fad09c73 | 94 | static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
95 | int addr, int reg, u16 val) |
96 | { | |
97 | int ret; | |
98 | ||
fad09c73 | 99 | ret = mdiobus_write_nested(chip->bus, addr, reg, val); |
914b32f6 VD |
100 | if (ret < 0) |
101 | return ret; | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
c08026ab | 106 | static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { |
914b32f6 VD |
107 | .read = mv88e6xxx_smi_single_chip_read, |
108 | .write = mv88e6xxx_smi_single_chip_write, | |
109 | }; | |
110 | ||
fad09c73 | 111 | static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) |
91da11f8 LB |
112 | { |
113 | int ret; | |
114 | int i; | |
115 | ||
116 | for (i = 0; i < 16; i++) { | |
fad09c73 | 117 | ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); |
91da11f8 LB |
118 | if (ret < 0) |
119 | return ret; | |
120 | ||
cca8b133 | 121 | if ((ret & SMI_CMD_BUSY) == 0) |
91da11f8 LB |
122 | return 0; |
123 | } | |
124 | ||
125 | return -ETIMEDOUT; | |
126 | } | |
127 | ||
fad09c73 | 128 | static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, |
914b32f6 | 129 | int addr, int reg, u16 *val) |
91da11f8 LB |
130 | { |
131 | int ret; | |
132 | ||
3675c8d7 | 133 | /* Wait for the bus to become free. */ |
fad09c73 | 134 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
135 | if (ret < 0) |
136 | return ret; | |
137 | ||
3675c8d7 | 138 | /* Transmit the read command. */ |
fad09c73 | 139 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, |
6e899e6c | 140 | SMI_CMD_OP_22_READ | (addr << 5) | reg); |
91da11f8 LB |
141 | if (ret < 0) |
142 | return ret; | |
143 | ||
3675c8d7 | 144 | /* Wait for the read command to complete. */ |
fad09c73 | 145 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
146 | if (ret < 0) |
147 | return ret; | |
148 | ||
3675c8d7 | 149 | /* Read the data. */ |
fad09c73 | 150 | ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); |
bb92ea5e VD |
151 | if (ret < 0) |
152 | return ret; | |
153 | ||
914b32f6 | 154 | *val = ret & 0xffff; |
91da11f8 | 155 | |
914b32f6 | 156 | return 0; |
8d6d09e7 GR |
157 | } |
158 | ||
fad09c73 | 159 | static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, |
914b32f6 | 160 | int addr, int reg, u16 val) |
91da11f8 LB |
161 | { |
162 | int ret; | |
163 | ||
3675c8d7 | 164 | /* Wait for the bus to become free. */ |
fad09c73 | 165 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
166 | if (ret < 0) |
167 | return ret; | |
168 | ||
3675c8d7 | 169 | /* Transmit the data to write. */ |
fad09c73 | 170 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); |
91da11f8 LB |
171 | if (ret < 0) |
172 | return ret; | |
173 | ||
3675c8d7 | 174 | /* Transmit the write command. */ |
fad09c73 | 175 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, |
6e899e6c | 176 | SMI_CMD_OP_22_WRITE | (addr << 5) | reg); |
91da11f8 LB |
177 | if (ret < 0) |
178 | return ret; | |
179 | ||
3675c8d7 | 180 | /* Wait for the write command to complete. */ |
fad09c73 | 181 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
182 | if (ret < 0) |
183 | return ret; | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
c08026ab | 188 | static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { |
914b32f6 VD |
189 | .read = mv88e6xxx_smi_multi_chip_read, |
190 | .write = mv88e6xxx_smi_multi_chip_write, | |
191 | }; | |
192 | ||
ec561276 | 193 | int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) |
914b32f6 VD |
194 | { |
195 | int err; | |
196 | ||
fad09c73 | 197 | assert_reg_lock(chip); |
914b32f6 | 198 | |
fad09c73 | 199 | err = mv88e6xxx_smi_read(chip, addr, reg, val); |
914b32f6 VD |
200 | if (err) |
201 | return err; | |
202 | ||
fad09c73 | 203 | dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
914b32f6 VD |
204 | addr, reg, *val); |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
ec561276 | 209 | int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) |
91da11f8 | 210 | { |
914b32f6 VD |
211 | int err; |
212 | ||
fad09c73 | 213 | assert_reg_lock(chip); |
91da11f8 | 214 | |
fad09c73 | 215 | err = mv88e6xxx_smi_write(chip, addr, reg, val); |
914b32f6 VD |
216 | if (err) |
217 | return err; | |
218 | ||
fad09c73 | 219 | dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
bb92ea5e VD |
220 | addr, reg, val); |
221 | ||
914b32f6 VD |
222 | return 0; |
223 | } | |
224 | ||
e57e5e77 VD |
225 | static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy, |
226 | int reg, u16 *val) | |
227 | { | |
228 | int addr = phy; /* PHY devices addresses start at 0x0 */ | |
229 | ||
b3469dd8 | 230 | if (!chip->info->ops->phy_read) |
e57e5e77 VD |
231 | return -EOPNOTSUPP; |
232 | ||
b3469dd8 | 233 | return chip->info->ops->phy_read(chip, addr, reg, val); |
e57e5e77 VD |
234 | } |
235 | ||
236 | static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, | |
237 | int reg, u16 val) | |
238 | { | |
239 | int addr = phy; /* PHY devices addresses start at 0x0 */ | |
240 | ||
b3469dd8 | 241 | if (!chip->info->ops->phy_write) |
e57e5e77 VD |
242 | return -EOPNOTSUPP; |
243 | ||
b3469dd8 | 244 | return chip->info->ops->phy_write(chip, addr, reg, val); |
e57e5e77 VD |
245 | } |
246 | ||
09cb7dfd VD |
247 | static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page) |
248 | { | |
249 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE)) | |
250 | return -EOPNOTSUPP; | |
251 | ||
252 | return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); | |
253 | } | |
254 | ||
255 | static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy) | |
256 | { | |
257 | int err; | |
258 | ||
259 | /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */ | |
260 | err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER); | |
261 | if (unlikely(err)) { | |
262 | dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n", | |
263 | phy, err); | |
264 | } | |
265 | } | |
266 | ||
267 | static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy, | |
268 | u8 page, int reg, u16 *val) | |
269 | { | |
270 | int err; | |
271 | ||
272 | /* There is no paging for registers 22 */ | |
273 | if (reg == PHY_PAGE) | |
274 | return -EINVAL; | |
275 | ||
276 | err = mv88e6xxx_phy_page_get(chip, phy, page); | |
277 | if (!err) { | |
278 | err = mv88e6xxx_phy_read(chip, phy, reg, val); | |
279 | mv88e6xxx_phy_page_put(chip, phy); | |
280 | } | |
281 | ||
282 | return err; | |
283 | } | |
284 | ||
285 | static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy, | |
286 | u8 page, int reg, u16 val) | |
287 | { | |
288 | int err; | |
289 | ||
290 | /* There is no paging for registers 22 */ | |
291 | if (reg == PHY_PAGE) | |
292 | return -EINVAL; | |
293 | ||
294 | err = mv88e6xxx_phy_page_get(chip, phy, page); | |
295 | if (!err) { | |
296 | err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); | |
297 | mv88e6xxx_phy_page_put(chip, phy); | |
298 | } | |
299 | ||
300 | return err; | |
301 | } | |
302 | ||
303 | static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) | |
304 | { | |
305 | return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER, | |
306 | reg, val); | |
307 | } | |
308 | ||
309 | static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val) | |
310 | { | |
311 | return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER, | |
312 | reg, val); | |
313 | } | |
314 | ||
dc30c35b AL |
315 | static void mv88e6xxx_g1_irq_mask(struct irq_data *d) |
316 | { | |
317 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
318 | unsigned int n = d->hwirq; | |
319 | ||
320 | chip->g1_irq.masked |= (1 << n); | |
321 | } | |
322 | ||
323 | static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) | |
324 | { | |
325 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
326 | unsigned int n = d->hwirq; | |
327 | ||
328 | chip->g1_irq.masked &= ~(1 << n); | |
329 | } | |
330 | ||
331 | static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) | |
332 | { | |
333 | struct mv88e6xxx_chip *chip = dev_id; | |
334 | unsigned int nhandled = 0; | |
335 | unsigned int sub_irq; | |
336 | unsigned int n; | |
337 | u16 reg; | |
338 | int err; | |
339 | ||
340 | mutex_lock(&chip->reg_lock); | |
341 | err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®); | |
342 | mutex_unlock(&chip->reg_lock); | |
343 | ||
344 | if (err) | |
345 | goto out; | |
346 | ||
347 | for (n = 0; n < chip->g1_irq.nirqs; ++n) { | |
348 | if (reg & (1 << n)) { | |
349 | sub_irq = irq_find_mapping(chip->g1_irq.domain, n); | |
350 | handle_nested_irq(sub_irq); | |
351 | ++nhandled; | |
352 | } | |
353 | } | |
354 | out: | |
355 | return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); | |
356 | } | |
357 | ||
358 | static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) | |
359 | { | |
360 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
361 | ||
362 | mutex_lock(&chip->reg_lock); | |
363 | } | |
364 | ||
365 | static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) | |
366 | { | |
367 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
368 | u16 mask = GENMASK(chip->g1_irq.nirqs, 0); | |
369 | u16 reg; | |
370 | int err; | |
371 | ||
372 | err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®); | |
373 | if (err) | |
374 | goto out; | |
375 | ||
376 | reg &= ~mask; | |
377 | reg |= (~chip->g1_irq.masked & mask); | |
378 | ||
379 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg); | |
380 | if (err) | |
381 | goto out; | |
382 | ||
383 | out: | |
384 | mutex_unlock(&chip->reg_lock); | |
385 | } | |
386 | ||
387 | static struct irq_chip mv88e6xxx_g1_irq_chip = { | |
388 | .name = "mv88e6xxx-g1", | |
389 | .irq_mask = mv88e6xxx_g1_irq_mask, | |
390 | .irq_unmask = mv88e6xxx_g1_irq_unmask, | |
391 | .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, | |
392 | .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, | |
393 | }; | |
394 | ||
395 | static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, | |
396 | unsigned int irq, | |
397 | irq_hw_number_t hwirq) | |
398 | { | |
399 | struct mv88e6xxx_chip *chip = d->host_data; | |
400 | ||
401 | irq_set_chip_data(irq, d->host_data); | |
402 | irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); | |
403 | irq_set_noprobe(irq); | |
404 | ||
405 | return 0; | |
406 | } | |
407 | ||
408 | static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { | |
409 | .map = mv88e6xxx_g1_irq_domain_map, | |
410 | .xlate = irq_domain_xlate_twocell, | |
411 | }; | |
412 | ||
413 | static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) | |
414 | { | |
415 | int irq, virq; | |
3460a577 AL |
416 | u16 mask; |
417 | ||
418 | mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask); | |
419 | mask |= GENMASK(chip->g1_irq.nirqs, 0); | |
420 | mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); | |
421 | ||
422 | free_irq(chip->irq, chip); | |
dc30c35b | 423 | |
5edef2f2 | 424 | for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { |
a3db3d3a | 425 | virq = irq_find_mapping(chip->g1_irq.domain, irq); |
dc30c35b AL |
426 | irq_dispose_mapping(virq); |
427 | } | |
428 | ||
a3db3d3a | 429 | irq_domain_remove(chip->g1_irq.domain); |
dc30c35b AL |
430 | } |
431 | ||
432 | static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) | |
433 | { | |
3dd0ef05 AL |
434 | int err, irq, virq; |
435 | u16 reg, mask; | |
dc30c35b AL |
436 | |
437 | chip->g1_irq.nirqs = chip->info->g1_irqs; | |
438 | chip->g1_irq.domain = irq_domain_add_simple( | |
439 | NULL, chip->g1_irq.nirqs, 0, | |
440 | &mv88e6xxx_g1_irq_domain_ops, chip); | |
441 | if (!chip->g1_irq.domain) | |
442 | return -ENOMEM; | |
443 | ||
444 | for (irq = 0; irq < chip->g1_irq.nirqs; irq++) | |
445 | irq_create_mapping(chip->g1_irq.domain, irq); | |
446 | ||
447 | chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; | |
448 | chip->g1_irq.masked = ~0; | |
449 | ||
3dd0ef05 | 450 | err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask); |
dc30c35b | 451 | if (err) |
3dd0ef05 | 452 | goto out_mapping; |
dc30c35b | 453 | |
3dd0ef05 | 454 | mask &= ~GENMASK(chip->g1_irq.nirqs, 0); |
dc30c35b | 455 | |
3dd0ef05 | 456 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); |
dc30c35b | 457 | if (err) |
3dd0ef05 | 458 | goto out_disable; |
dc30c35b AL |
459 | |
460 | /* Reading the interrupt status clears (most of) them */ | |
461 | err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®); | |
462 | if (err) | |
3dd0ef05 | 463 | goto out_disable; |
dc30c35b AL |
464 | |
465 | err = request_threaded_irq(chip->irq, NULL, | |
466 | mv88e6xxx_g1_irq_thread_fn, | |
467 | IRQF_ONESHOT | IRQF_TRIGGER_FALLING, | |
468 | dev_name(chip->dev), chip); | |
469 | if (err) | |
3dd0ef05 | 470 | goto out_disable; |
dc30c35b AL |
471 | |
472 | return 0; | |
473 | ||
3dd0ef05 AL |
474 | out_disable: |
475 | mask |= GENMASK(chip->g1_irq.nirqs, 0); | |
476 | mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); | |
477 | ||
478 | out_mapping: | |
479 | for (irq = 0; irq < 16; irq++) { | |
480 | virq = irq_find_mapping(chip->g1_irq.domain, irq); | |
481 | irq_dispose_mapping(virq); | |
482 | } | |
483 | ||
484 | irq_domain_remove(chip->g1_irq.domain); | |
dc30c35b AL |
485 | |
486 | return err; | |
487 | } | |
488 | ||
ec561276 | 489 | int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) |
2d79af6e | 490 | { |
6441e669 | 491 | int i; |
2d79af6e | 492 | |
6441e669 | 493 | for (i = 0; i < 16; i++) { |
2d79af6e VD |
494 | u16 val; |
495 | int err; | |
496 | ||
497 | err = mv88e6xxx_read(chip, addr, reg, &val); | |
498 | if (err) | |
499 | return err; | |
500 | ||
501 | if (!(val & mask)) | |
502 | return 0; | |
503 | ||
504 | usleep_range(1000, 2000); | |
505 | } | |
506 | ||
30853553 | 507 | dev_err(chip->dev, "Timeout while waiting for switch\n"); |
2d79af6e VD |
508 | return -ETIMEDOUT; |
509 | } | |
510 | ||
f22ab641 | 511 | /* Indirect write to single pointer-data register with an Update bit */ |
ec561276 | 512 | int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) |
f22ab641 VD |
513 | { |
514 | u16 val; | |
0f02b4f7 | 515 | int err; |
f22ab641 VD |
516 | |
517 | /* Wait until the previous operation is completed */ | |
0f02b4f7 AL |
518 | err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); |
519 | if (err) | |
520 | return err; | |
f22ab641 VD |
521 | |
522 | /* Set the Update bit to trigger a write operation */ | |
523 | val = BIT(15) | update; | |
524 | ||
525 | return mv88e6xxx_write(chip, addr, reg, val); | |
526 | } | |
527 | ||
a935c052 | 528 | static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip) |
914b32f6 VD |
529 | { |
530 | u16 val; | |
a935c052 | 531 | int i, err; |
914b32f6 | 532 | |
a935c052 | 533 | err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val); |
914b32f6 VD |
534 | if (err) |
535 | return err; | |
536 | ||
a935c052 VD |
537 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, |
538 | val & ~GLOBAL_CONTROL_PPU_ENABLE); | |
539 | if (err) | |
540 | return err; | |
2e5f0320 | 541 | |
6441e669 | 542 | for (i = 0; i < 16; i++) { |
a935c052 VD |
543 | err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val); |
544 | if (err) | |
545 | return err; | |
48ace4ef | 546 | |
19b2f97e | 547 | usleep_range(1000, 2000); |
17e708ba VD |
548 | val &= GLOBAL_STATUS_PPU_STATE_MASK; |
549 | if (val != GLOBAL_STATUS_PPU_STATE_POLLING) | |
85686581 | 550 | return 0; |
2e5f0320 LB |
551 | } |
552 | ||
553 | return -ETIMEDOUT; | |
554 | } | |
555 | ||
fad09c73 | 556 | static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip) |
2e5f0320 | 557 | { |
a935c052 VD |
558 | u16 val; |
559 | int i, err; | |
2e5f0320 | 560 | |
a935c052 VD |
561 | err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val); |
562 | if (err) | |
563 | return err; | |
48ace4ef | 564 | |
a935c052 VD |
565 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, |
566 | val | GLOBAL_CONTROL_PPU_ENABLE); | |
48ace4ef AL |
567 | if (err) |
568 | return err; | |
2e5f0320 | 569 | |
6441e669 | 570 | for (i = 0; i < 16; i++) { |
a935c052 VD |
571 | err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val); |
572 | if (err) | |
573 | return err; | |
48ace4ef | 574 | |
19b2f97e | 575 | usleep_range(1000, 2000); |
17e708ba VD |
576 | val &= GLOBAL_STATUS_PPU_STATE_MASK; |
577 | if (val == GLOBAL_STATUS_PPU_STATE_POLLING) | |
85686581 | 578 | return 0; |
2e5f0320 LB |
579 | } |
580 | ||
581 | return -ETIMEDOUT; | |
582 | } | |
583 | ||
584 | static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) | |
585 | { | |
fad09c73 | 586 | struct mv88e6xxx_chip *chip; |
2e5f0320 | 587 | |
fad09c73 | 588 | chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work); |
762eb67b | 589 | |
fad09c73 | 590 | mutex_lock(&chip->reg_lock); |
762eb67b | 591 | |
fad09c73 VD |
592 | if (mutex_trylock(&chip->ppu_mutex)) { |
593 | if (mv88e6xxx_ppu_enable(chip) == 0) | |
594 | chip->ppu_disabled = 0; | |
595 | mutex_unlock(&chip->ppu_mutex); | |
2e5f0320 | 596 | } |
762eb67b | 597 | |
fad09c73 | 598 | mutex_unlock(&chip->reg_lock); |
2e5f0320 LB |
599 | } |
600 | ||
601 | static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) | |
602 | { | |
fad09c73 | 603 | struct mv88e6xxx_chip *chip = (void *)_ps; |
2e5f0320 | 604 | |
fad09c73 | 605 | schedule_work(&chip->ppu_work); |
2e5f0320 LB |
606 | } |
607 | ||
fad09c73 | 608 | static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip) |
2e5f0320 | 609 | { |
2e5f0320 LB |
610 | int ret; |
611 | ||
fad09c73 | 612 | mutex_lock(&chip->ppu_mutex); |
2e5f0320 | 613 | |
3675c8d7 | 614 | /* If the PHY polling unit is enabled, disable it so that |
2e5f0320 LB |
615 | * we can access the PHY registers. If it was already |
616 | * disabled, cancel the timer that is going to re-enable | |
617 | * it. | |
618 | */ | |
fad09c73 VD |
619 | if (!chip->ppu_disabled) { |
620 | ret = mv88e6xxx_ppu_disable(chip); | |
85686581 | 621 | if (ret < 0) { |
fad09c73 | 622 | mutex_unlock(&chip->ppu_mutex); |
85686581 BG |
623 | return ret; |
624 | } | |
fad09c73 | 625 | chip->ppu_disabled = 1; |
2e5f0320 | 626 | } else { |
fad09c73 | 627 | del_timer(&chip->ppu_timer); |
85686581 | 628 | ret = 0; |
2e5f0320 LB |
629 | } |
630 | ||
631 | return ret; | |
632 | } | |
633 | ||
fad09c73 | 634 | static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip) |
2e5f0320 | 635 | { |
3675c8d7 | 636 | /* Schedule a timer to re-enable the PHY polling unit. */ |
fad09c73 VD |
637 | mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10)); |
638 | mutex_unlock(&chip->ppu_mutex); | |
2e5f0320 LB |
639 | } |
640 | ||
fad09c73 | 641 | static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip) |
2e5f0320 | 642 | { |
fad09c73 VD |
643 | mutex_init(&chip->ppu_mutex); |
644 | INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work); | |
68497a87 WY |
645 | setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer, |
646 | (unsigned long)chip); | |
2e5f0320 LB |
647 | } |
648 | ||
930188ce AL |
649 | static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip) |
650 | { | |
651 | del_timer_sync(&chip->ppu_timer); | |
652 | } | |
653 | ||
e57e5e77 VD |
654 | static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr, |
655 | int reg, u16 *val) | |
2e5f0320 | 656 | { |
e57e5e77 | 657 | int err; |
2e5f0320 | 658 | |
e57e5e77 VD |
659 | err = mv88e6xxx_ppu_access_get(chip); |
660 | if (!err) { | |
661 | err = mv88e6xxx_read(chip, addr, reg, val); | |
fad09c73 | 662 | mv88e6xxx_ppu_access_put(chip); |
2e5f0320 LB |
663 | } |
664 | ||
e57e5e77 | 665 | return err; |
2e5f0320 LB |
666 | } |
667 | ||
e57e5e77 VD |
668 | static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr, |
669 | int reg, u16 val) | |
2e5f0320 | 670 | { |
e57e5e77 | 671 | int err; |
2e5f0320 | 672 | |
e57e5e77 VD |
673 | err = mv88e6xxx_ppu_access_get(chip); |
674 | if (!err) { | |
675 | err = mv88e6xxx_write(chip, addr, reg, val); | |
fad09c73 | 676 | mv88e6xxx_ppu_access_put(chip); |
2e5f0320 LB |
677 | } |
678 | ||
e57e5e77 | 679 | return err; |
2e5f0320 | 680 | } |
2e5f0320 | 681 | |
fad09c73 | 682 | static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip) |
54d792f2 | 683 | { |
fad09c73 | 684 | return chip->info->family == MV88E6XXX_FAMILY_6095; |
54d792f2 AL |
685 | } |
686 | ||
fad09c73 | 687 | static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip) |
54d792f2 | 688 | { |
fad09c73 | 689 | return chip->info->family == MV88E6XXX_FAMILY_6097; |
54d792f2 AL |
690 | } |
691 | ||
fad09c73 | 692 | static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip) |
54d792f2 | 693 | { |
fad09c73 | 694 | return chip->info->family == MV88E6XXX_FAMILY_6165; |
54d792f2 AL |
695 | } |
696 | ||
fad09c73 | 697 | static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip) |
54d792f2 | 698 | { |
fad09c73 | 699 | return chip->info->family == MV88E6XXX_FAMILY_6185; |
54d792f2 AL |
700 | } |
701 | ||
fad09c73 | 702 | static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip) |
7c3d0d67 | 703 | { |
fad09c73 | 704 | return chip->info->family == MV88E6XXX_FAMILY_6320; |
7c3d0d67 AK |
705 | } |
706 | ||
fad09c73 | 707 | static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip) |
54d792f2 | 708 | { |
fad09c73 | 709 | return chip->info->family == MV88E6XXX_FAMILY_6351; |
54d792f2 AL |
710 | } |
711 | ||
fad09c73 | 712 | static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip) |
f3a8b6b6 | 713 | { |
fad09c73 | 714 | return chip->info->family == MV88E6XXX_FAMILY_6352; |
f3a8b6b6 AL |
715 | } |
716 | ||
d78343d2 VD |
717 | static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, |
718 | int link, int speed, int duplex, | |
719 | phy_interface_t mode) | |
720 | { | |
721 | int err; | |
722 | ||
723 | if (!chip->info->ops->port_set_link) | |
724 | return 0; | |
725 | ||
726 | /* Port's MAC control must not be changed unless the link is down */ | |
727 | err = chip->info->ops->port_set_link(chip, port, 0); | |
728 | if (err) | |
729 | return err; | |
730 | ||
731 | if (chip->info->ops->port_set_speed) { | |
732 | err = chip->info->ops->port_set_speed(chip, port, speed); | |
733 | if (err && err != -EOPNOTSUPP) | |
734 | goto restore_link; | |
735 | } | |
736 | ||
737 | if (chip->info->ops->port_set_duplex) { | |
738 | err = chip->info->ops->port_set_duplex(chip, port, duplex); | |
739 | if (err && err != -EOPNOTSUPP) | |
740 | goto restore_link; | |
741 | } | |
742 | ||
743 | if (chip->info->ops->port_set_rgmii_delay) { | |
744 | err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); | |
745 | if (err && err != -EOPNOTSUPP) | |
746 | goto restore_link; | |
747 | } | |
748 | ||
749 | err = 0; | |
750 | restore_link: | |
751 | if (chip->info->ops->port_set_link(chip, port, link)) | |
752 | netdev_err(chip->ds->ports[port].netdev, | |
753 | "failed to restore MAC's link\n"); | |
754 | ||
755 | return err; | |
756 | } | |
757 | ||
dea87024 AL |
758 | /* We expect the switch to perform auto negotiation if there is a real |
759 | * phy. However, in the case of a fixed link phy, we force the port | |
760 | * settings from the fixed link settings. | |
761 | */ | |
f81ec90f VD |
762 | static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, |
763 | struct phy_device *phydev) | |
dea87024 | 764 | { |
04bed143 | 765 | struct mv88e6xxx_chip *chip = ds->priv; |
0e7b9925 | 766 | int err; |
dea87024 AL |
767 | |
768 | if (!phy_is_pseudo_fixed_link(phydev)) | |
769 | return; | |
770 | ||
fad09c73 | 771 | mutex_lock(&chip->reg_lock); |
d78343d2 VD |
772 | err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, |
773 | phydev->duplex, phydev->interface); | |
fad09c73 | 774 | mutex_unlock(&chip->reg_lock); |
d78343d2 VD |
775 | |
776 | if (err && err != -EOPNOTSUPP) | |
777 | netdev_err(ds->ports[port].netdev, "failed to configure MAC\n"); | |
dea87024 AL |
778 | } |
779 | ||
a605a0fe | 780 | static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) |
91da11f8 | 781 | { |
a605a0fe AL |
782 | if (!chip->info->ops->stats_snapshot) |
783 | return -EOPNOTSUPP; | |
91da11f8 | 784 | |
a605a0fe | 785 | return chip->info->ops->stats_snapshot(chip, port); |
91da11f8 LB |
786 | } |
787 | ||
e413e7e1 | 788 | static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { |
dfafe449 AL |
789 | { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, |
790 | { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, | |
791 | { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, | |
792 | { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, | |
793 | { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, | |
794 | { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, | |
795 | { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, | |
796 | { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, | |
797 | { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, | |
798 | { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, | |
799 | { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, | |
800 | { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, | |
801 | { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, | |
802 | { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, | |
803 | { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, | |
804 | { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, | |
805 | { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, | |
806 | { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, | |
807 | { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, | |
808 | { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, | |
809 | { "single", 4, 0x14, STATS_TYPE_BANK0, }, | |
810 | { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, | |
811 | { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, | |
812 | { "late", 4, 0x1f, STATS_TYPE_BANK0, }, | |
813 | { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, | |
814 | { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, | |
815 | { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, | |
816 | { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, | |
817 | { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, | |
818 | { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, | |
819 | { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, | |
820 | { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, | |
821 | { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, | |
822 | { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, | |
823 | { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, | |
824 | { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, | |
825 | { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, | |
826 | { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, | |
827 | { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, | |
828 | { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, | |
829 | { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, | |
830 | { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, | |
831 | { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, | |
832 | { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, | |
833 | { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, | |
834 | { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, | |
835 | { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, | |
836 | { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, | |
837 | { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, | |
838 | { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, | |
839 | { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, | |
840 | { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, | |
841 | { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, | |
842 | { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, | |
843 | { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, | |
844 | { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, | |
845 | { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, | |
846 | { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, | |
847 | { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, | |
e413e7e1 AL |
848 | }; |
849 | ||
fad09c73 | 850 | static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, |
f5e2ed02 | 851 | struct mv88e6xxx_hw_stat *s, |
e0d8b615 AL |
852 | int port, u16 bank1_select, |
853 | u16 histogram) | |
80c4627b | 854 | { |
80c4627b AL |
855 | u32 low; |
856 | u32 high = 0; | |
dfafe449 | 857 | u16 reg = 0; |
0e7b9925 | 858 | int err; |
80c4627b AL |
859 | u64 value; |
860 | ||
f5e2ed02 | 861 | switch (s->type) { |
dfafe449 | 862 | case STATS_TYPE_PORT: |
0e7b9925 AL |
863 | err = mv88e6xxx_port_read(chip, port, s->reg, ®); |
864 | if (err) | |
80c4627b AL |
865 | return UINT64_MAX; |
866 | ||
0e7b9925 | 867 | low = reg; |
80c4627b | 868 | if (s->sizeof_stat == 4) { |
0e7b9925 AL |
869 | err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); |
870 | if (err) | |
80c4627b | 871 | return UINT64_MAX; |
0e7b9925 | 872 | high = reg; |
80c4627b | 873 | } |
f5e2ed02 | 874 | break; |
dfafe449 | 875 | case STATS_TYPE_BANK1: |
e0d8b615 | 876 | reg = bank1_select; |
dfafe449 AL |
877 | /* fall through */ |
878 | case STATS_TYPE_BANK0: | |
e0d8b615 | 879 | reg |= s->reg | histogram; |
7f9ef3af | 880 | mv88e6xxx_g1_stats_read(chip, reg, &low); |
80c4627b | 881 | if (s->sizeof_stat == 8) |
7f9ef3af | 882 | mv88e6xxx_g1_stats_read(chip, reg + 1, &high); |
80c4627b AL |
883 | } |
884 | value = (((u64)high) << 16) | low; | |
885 | return value; | |
886 | } | |
887 | ||
dfafe449 AL |
888 | static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, |
889 | uint8_t *data, int types) | |
91da11f8 | 890 | { |
f5e2ed02 AL |
891 | struct mv88e6xxx_hw_stat *stat; |
892 | int i, j; | |
91da11f8 | 893 | |
f5e2ed02 AL |
894 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { |
895 | stat = &mv88e6xxx_hw_stats[i]; | |
dfafe449 | 896 | if (stat->type & types) { |
f5e2ed02 AL |
897 | memcpy(data + j * ETH_GSTRING_LEN, stat->string, |
898 | ETH_GSTRING_LEN); | |
899 | j++; | |
900 | } | |
91da11f8 | 901 | } |
e413e7e1 AL |
902 | } |
903 | ||
dfafe449 AL |
904 | static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, |
905 | uint8_t *data) | |
906 | { | |
907 | mv88e6xxx_stats_get_strings(chip, data, | |
908 | STATS_TYPE_BANK0 | STATS_TYPE_PORT); | |
909 | } | |
910 | ||
911 | static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, | |
912 | uint8_t *data) | |
913 | { | |
914 | mv88e6xxx_stats_get_strings(chip, data, | |
915 | STATS_TYPE_BANK0 | STATS_TYPE_BANK1); | |
916 | } | |
917 | ||
918 | static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, | |
919 | uint8_t *data) | |
e413e7e1 | 920 | { |
04bed143 | 921 | struct mv88e6xxx_chip *chip = ds->priv; |
dfafe449 AL |
922 | |
923 | if (chip->info->ops->stats_get_strings) | |
924 | chip->info->ops->stats_get_strings(chip, data); | |
925 | } | |
926 | ||
927 | static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, | |
928 | int types) | |
929 | { | |
f5e2ed02 AL |
930 | struct mv88e6xxx_hw_stat *stat; |
931 | int i, j; | |
932 | ||
933 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { | |
934 | stat = &mv88e6xxx_hw_stats[i]; | |
dfafe449 | 935 | if (stat->type & types) |
f5e2ed02 AL |
936 | j++; |
937 | } | |
938 | return j; | |
e413e7e1 AL |
939 | } |
940 | ||
dfafe449 AL |
941 | static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) |
942 | { | |
943 | return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | | |
944 | STATS_TYPE_PORT); | |
945 | } | |
946 | ||
947 | static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) | |
948 | { | |
949 | return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | | |
950 | STATS_TYPE_BANK1); | |
951 | } | |
952 | ||
953 | static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) | |
954 | { | |
955 | struct mv88e6xxx_chip *chip = ds->priv; | |
956 | ||
957 | if (chip->info->ops->stats_get_sset_count) | |
958 | return chip->info->ops->stats_get_sset_count(chip); | |
959 | ||
960 | return 0; | |
961 | } | |
962 | ||
052f947f | 963 | static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, |
e0d8b615 AL |
964 | uint64_t *data, int types, |
965 | u16 bank1_select, u16 histogram) | |
052f947f AL |
966 | { |
967 | struct mv88e6xxx_hw_stat *stat; | |
968 | int i, j; | |
969 | ||
970 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { | |
971 | stat = &mv88e6xxx_hw_stats[i]; | |
972 | if (stat->type & types) { | |
e0d8b615 AL |
973 | data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, |
974 | bank1_select, | |
975 | histogram); | |
052f947f AL |
976 | j++; |
977 | } | |
978 | } | |
979 | } | |
980 | ||
981 | static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, | |
982 | uint64_t *data) | |
983 | { | |
984 | return mv88e6xxx_stats_get_stats(chip, port, data, | |
e0d8b615 AL |
985 | STATS_TYPE_BANK0 | STATS_TYPE_PORT, |
986 | 0, GLOBAL_STATS_OP_HIST_RX_TX); | |
052f947f AL |
987 | } |
988 | ||
989 | static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, | |
990 | uint64_t *data) | |
991 | { | |
992 | return mv88e6xxx_stats_get_stats(chip, port, data, | |
e0d8b615 AL |
993 | STATS_TYPE_BANK0 | STATS_TYPE_BANK1, |
994 | GLOBAL_STATS_OP_BANK_1_BIT_9, | |
995 | GLOBAL_STATS_OP_HIST_RX_TX); | |
996 | } | |
997 | ||
998 | static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, | |
999 | uint64_t *data) | |
1000 | { | |
1001 | return mv88e6xxx_stats_get_stats(chip, port, data, | |
1002 | STATS_TYPE_BANK0 | STATS_TYPE_BANK1, | |
1003 | GLOBAL_STATS_OP_BANK_1_BIT_10, 0); | |
052f947f AL |
1004 | } |
1005 | ||
1006 | static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, | |
1007 | uint64_t *data) | |
1008 | { | |
1009 | if (chip->info->ops->stats_get_stats) | |
1010 | chip->info->ops->stats_get_stats(chip, port, data); | |
1011 | } | |
1012 | ||
f81ec90f VD |
1013 | static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, |
1014 | uint64_t *data) | |
e413e7e1 | 1015 | { |
04bed143 | 1016 | struct mv88e6xxx_chip *chip = ds->priv; |
f5e2ed02 | 1017 | int ret; |
f5e2ed02 | 1018 | |
fad09c73 | 1019 | mutex_lock(&chip->reg_lock); |
f5e2ed02 | 1020 | |
a605a0fe | 1021 | ret = mv88e6xxx_stats_snapshot(chip, port); |
f5e2ed02 | 1022 | if (ret < 0) { |
fad09c73 | 1023 | mutex_unlock(&chip->reg_lock); |
f5e2ed02 AL |
1024 | return; |
1025 | } | |
052f947f AL |
1026 | |
1027 | mv88e6xxx_get_stats(chip, port, data); | |
f5e2ed02 | 1028 | |
fad09c73 | 1029 | mutex_unlock(&chip->reg_lock); |
e413e7e1 AL |
1030 | } |
1031 | ||
de227387 AL |
1032 | static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip) |
1033 | { | |
1034 | if (chip->info->ops->stats_set_histogram) | |
1035 | return chip->info->ops->stats_set_histogram(chip); | |
1036 | ||
1037 | return 0; | |
1038 | } | |
1039 | ||
f81ec90f | 1040 | static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) |
a1ab91f3 GR |
1041 | { |
1042 | return 32 * sizeof(u16); | |
1043 | } | |
1044 | ||
f81ec90f VD |
1045 | static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, |
1046 | struct ethtool_regs *regs, void *_p) | |
a1ab91f3 | 1047 | { |
04bed143 | 1048 | struct mv88e6xxx_chip *chip = ds->priv; |
0e7b9925 AL |
1049 | int err; |
1050 | u16 reg; | |
a1ab91f3 GR |
1051 | u16 *p = _p; |
1052 | int i; | |
1053 | ||
1054 | regs->version = 0; | |
1055 | ||
1056 | memset(p, 0xff, 32 * sizeof(u16)); | |
1057 | ||
fad09c73 | 1058 | mutex_lock(&chip->reg_lock); |
23062513 | 1059 | |
a1ab91f3 | 1060 | for (i = 0; i < 32; i++) { |
a1ab91f3 | 1061 | |
0e7b9925 AL |
1062 | err = mv88e6xxx_port_read(chip, port, i, ®); |
1063 | if (!err) | |
1064 | p[i] = reg; | |
a1ab91f3 | 1065 | } |
23062513 | 1066 | |
fad09c73 | 1067 | mutex_unlock(&chip->reg_lock); |
a1ab91f3 GR |
1068 | } |
1069 | ||
fad09c73 | 1070 | static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip) |
facd95b2 | 1071 | { |
a935c052 | 1072 | return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY); |
facd95b2 GR |
1073 | } |
1074 | ||
f81ec90f VD |
1075 | static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, |
1076 | struct ethtool_eee *e) | |
11b3b45d | 1077 | { |
04bed143 | 1078 | struct mv88e6xxx_chip *chip = ds->priv; |
9c93829c VD |
1079 | u16 reg; |
1080 | int err; | |
11b3b45d | 1081 | |
fad09c73 | 1082 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) |
aadbdb8a VD |
1083 | return -EOPNOTSUPP; |
1084 | ||
fad09c73 | 1085 | mutex_lock(&chip->reg_lock); |
2f40c698 | 1086 | |
9c93829c VD |
1087 | err = mv88e6xxx_phy_read(chip, port, 16, ®); |
1088 | if (err) | |
2f40c698 | 1089 | goto out; |
11b3b45d GR |
1090 | |
1091 | e->eee_enabled = !!(reg & 0x0200); | |
1092 | e->tx_lpi_enabled = !!(reg & 0x0100); | |
1093 | ||
0e7b9925 | 1094 | err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®); |
9c93829c | 1095 | if (err) |
2f40c698 | 1096 | goto out; |
11b3b45d | 1097 | |
cca8b133 | 1098 | e->eee_active = !!(reg & PORT_STATUS_EEE); |
2f40c698 | 1099 | out: |
fad09c73 | 1100 | mutex_unlock(&chip->reg_lock); |
9c93829c VD |
1101 | |
1102 | return err; | |
11b3b45d GR |
1103 | } |
1104 | ||
f81ec90f VD |
1105 | static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, |
1106 | struct phy_device *phydev, struct ethtool_eee *e) | |
11b3b45d | 1107 | { |
04bed143 | 1108 | struct mv88e6xxx_chip *chip = ds->priv; |
9c93829c VD |
1109 | u16 reg; |
1110 | int err; | |
11b3b45d | 1111 | |
fad09c73 | 1112 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) |
aadbdb8a VD |
1113 | return -EOPNOTSUPP; |
1114 | ||
fad09c73 | 1115 | mutex_lock(&chip->reg_lock); |
11b3b45d | 1116 | |
9c93829c VD |
1117 | err = mv88e6xxx_phy_read(chip, port, 16, ®); |
1118 | if (err) | |
2f40c698 AL |
1119 | goto out; |
1120 | ||
9c93829c | 1121 | reg &= ~0x0300; |
2f40c698 AL |
1122 | if (e->eee_enabled) |
1123 | reg |= 0x0200; | |
1124 | if (e->tx_lpi_enabled) | |
1125 | reg |= 0x0100; | |
1126 | ||
9c93829c | 1127 | err = mv88e6xxx_phy_write(chip, port, 16, reg); |
2f40c698 | 1128 | out: |
fad09c73 | 1129 | mutex_unlock(&chip->reg_lock); |
2f40c698 | 1130 | |
9c93829c | 1131 | return err; |
11b3b45d GR |
1132 | } |
1133 | ||
fad09c73 | 1134 | static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd) |
facd95b2 | 1135 | { |
a935c052 VD |
1136 | u16 val; |
1137 | int err; | |
facd95b2 | 1138 | |
6dc10bbc | 1139 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) { |
a935c052 VD |
1140 | err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid); |
1141 | if (err) | |
1142 | return err; | |
fad09c73 | 1143 | } else if (mv88e6xxx_num_databases(chip) == 256) { |
11ea809f | 1144 | /* ATU DBNum[7:4] are located in ATU Control 15:12 */ |
a935c052 VD |
1145 | err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val); |
1146 | if (err) | |
1147 | return err; | |
11ea809f | 1148 | |
a935c052 VD |
1149 | err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, |
1150 | (val & 0xfff) | ((fid << 8) & 0xf000)); | |
1151 | if (err) | |
1152 | return err; | |
11ea809f VD |
1153 | |
1154 | /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ | |
1155 | cmd |= fid & 0xf; | |
b426e5f7 VD |
1156 | } |
1157 | ||
a935c052 VD |
1158 | err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd); |
1159 | if (err) | |
1160 | return err; | |
facd95b2 | 1161 | |
fad09c73 | 1162 | return _mv88e6xxx_atu_wait(chip); |
facd95b2 GR |
1163 | } |
1164 | ||
fad09c73 | 1165 | static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip, |
37705b73 VD |
1166 | struct mv88e6xxx_atu_entry *entry) |
1167 | { | |
1168 | u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK; | |
1169 | ||
1170 | if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) { | |
1171 | unsigned int mask, shift; | |
1172 | ||
1173 | if (entry->trunk) { | |
1174 | data |= GLOBAL_ATU_DATA_TRUNK; | |
1175 | mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; | |
1176 | shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; | |
1177 | } else { | |
1178 | mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; | |
1179 | shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; | |
1180 | } | |
1181 | ||
1182 | data |= (entry->portv_trunkid << shift) & mask; | |
1183 | } | |
1184 | ||
a935c052 | 1185 | return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data); |
37705b73 VD |
1186 | } |
1187 | ||
fad09c73 | 1188 | static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip, |
7fb5e755 VD |
1189 | struct mv88e6xxx_atu_entry *entry, |
1190 | bool static_too) | |
facd95b2 | 1191 | { |
7fb5e755 VD |
1192 | int op; |
1193 | int err; | |
facd95b2 | 1194 | |
fad09c73 | 1195 | err = _mv88e6xxx_atu_wait(chip); |
7fb5e755 VD |
1196 | if (err) |
1197 | return err; | |
facd95b2 | 1198 | |
fad09c73 | 1199 | err = _mv88e6xxx_atu_data_write(chip, entry); |
7fb5e755 VD |
1200 | if (err) |
1201 | return err; | |
1202 | ||
1203 | if (entry->fid) { | |
7fb5e755 VD |
1204 | op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB : |
1205 | GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; | |
1206 | } else { | |
1207 | op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL : | |
1208 | GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC; | |
1209 | } | |
1210 | ||
fad09c73 | 1211 | return _mv88e6xxx_atu_cmd(chip, entry->fid, op); |
7fb5e755 VD |
1212 | } |
1213 | ||
fad09c73 | 1214 | static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip, |
158bc065 | 1215 | u16 fid, bool static_too) |
7fb5e755 VD |
1216 | { |
1217 | struct mv88e6xxx_atu_entry entry = { | |
1218 | .fid = fid, | |
1219 | .state = 0, /* EntryState bits must be 0 */ | |
1220 | }; | |
70cc99d1 | 1221 | |
fad09c73 | 1222 | return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); |
7fb5e755 VD |
1223 | } |
1224 | ||
fad09c73 | 1225 | static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid, |
158bc065 | 1226 | int from_port, int to_port, bool static_too) |
9f4d55d2 VD |
1227 | { |
1228 | struct mv88e6xxx_atu_entry entry = { | |
1229 | .trunk = false, | |
1230 | .fid = fid, | |
1231 | }; | |
1232 | ||
1233 | /* EntryState bits must be 0xF */ | |
1234 | entry.state = GLOBAL_ATU_DATA_STATE_MASK; | |
1235 | ||
1236 | /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */ | |
1237 | entry.portv_trunkid = (to_port & 0x0f) << 4; | |
1238 | entry.portv_trunkid |= from_port & 0x0f; | |
1239 | ||
fad09c73 | 1240 | return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); |
9f4d55d2 VD |
1241 | } |
1242 | ||
fad09c73 | 1243 | static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, |
158bc065 | 1244 | int port, bool static_too) |
9f4d55d2 VD |
1245 | { |
1246 | /* Destination port 0xF means remove the entries */ | |
fad09c73 | 1247 | return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too); |
9f4d55d2 VD |
1248 | } |
1249 | ||
fad09c73 | 1250 | static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port) |
facd95b2 | 1251 | { |
fad09c73 | 1252 | struct net_device *bridge = chip->ports[port].bridge_dev; |
fad09c73 | 1253 | struct dsa_switch *ds = chip->ds; |
b7666efe | 1254 | u16 output_ports = 0; |
b7666efe VD |
1255 | int i; |
1256 | ||
1257 | /* allow CPU port or DSA link(s) to send frames to every port */ | |
1258 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { | |
5a7921f4 | 1259 | output_ports = ~0; |
b7666efe | 1260 | } else { |
370b4ffb | 1261 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
b7666efe | 1262 | /* allow sending frames to every group member */ |
fad09c73 | 1263 | if (bridge && chip->ports[i].bridge_dev == bridge) |
b7666efe VD |
1264 | output_ports |= BIT(i); |
1265 | ||
1266 | /* allow sending frames to CPU port and DSA link(s) */ | |
1267 | if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) | |
1268 | output_ports |= BIT(i); | |
1269 | } | |
1270 | } | |
1271 | ||
1272 | /* prevent frames from going back out of the port they came in on */ | |
1273 | output_ports &= ~BIT(port); | |
facd95b2 | 1274 | |
5a7921f4 | 1275 | return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); |
facd95b2 GR |
1276 | } |
1277 | ||
f81ec90f VD |
1278 | static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, |
1279 | u8 state) | |
facd95b2 | 1280 | { |
04bed143 | 1281 | struct mv88e6xxx_chip *chip = ds->priv; |
facd95b2 | 1282 | int stp_state; |
553eb544 | 1283 | int err; |
facd95b2 GR |
1284 | |
1285 | switch (state) { | |
1286 | case BR_STATE_DISABLED: | |
cca8b133 | 1287 | stp_state = PORT_CONTROL_STATE_DISABLED; |
facd95b2 GR |
1288 | break; |
1289 | case BR_STATE_BLOCKING: | |
1290 | case BR_STATE_LISTENING: | |
cca8b133 | 1291 | stp_state = PORT_CONTROL_STATE_BLOCKING; |
facd95b2 GR |
1292 | break; |
1293 | case BR_STATE_LEARNING: | |
cca8b133 | 1294 | stp_state = PORT_CONTROL_STATE_LEARNING; |
facd95b2 GR |
1295 | break; |
1296 | case BR_STATE_FORWARDING: | |
1297 | default: | |
cca8b133 | 1298 | stp_state = PORT_CONTROL_STATE_FORWARDING; |
facd95b2 GR |
1299 | break; |
1300 | } | |
1301 | ||
fad09c73 | 1302 | mutex_lock(&chip->reg_lock); |
e28def33 | 1303 | err = mv88e6xxx_port_set_state(chip, port, stp_state); |
fad09c73 | 1304 | mutex_unlock(&chip->reg_lock); |
553eb544 VD |
1305 | |
1306 | if (err) | |
e28def33 | 1307 | netdev_err(ds->ports[port].netdev, "failed to update state\n"); |
facd95b2 GR |
1308 | } |
1309 | ||
749efcb8 VD |
1310 | static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) |
1311 | { | |
1312 | struct mv88e6xxx_chip *chip = ds->priv; | |
1313 | int err; | |
1314 | ||
1315 | mutex_lock(&chip->reg_lock); | |
1316 | err = _mv88e6xxx_atu_remove(chip, 0, port, false); | |
1317 | mutex_unlock(&chip->reg_lock); | |
1318 | ||
1319 | if (err) | |
1320 | netdev_err(ds->ports[port].netdev, "failed to flush ATU\n"); | |
1321 | } | |
1322 | ||
fad09c73 | 1323 | static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip) |
6b17e864 | 1324 | { |
a935c052 | 1325 | return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY); |
6b17e864 VD |
1326 | } |
1327 | ||
fad09c73 | 1328 | static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op) |
6b17e864 | 1329 | { |
a935c052 | 1330 | int err; |
6b17e864 | 1331 | |
a935c052 VD |
1332 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op); |
1333 | if (err) | |
1334 | return err; | |
6b17e864 | 1335 | |
fad09c73 | 1336 | return _mv88e6xxx_vtu_wait(chip); |
6b17e864 VD |
1337 | } |
1338 | ||
fad09c73 | 1339 | static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip) |
6b17e864 VD |
1340 | { |
1341 | int ret; | |
1342 | ||
fad09c73 | 1343 | ret = _mv88e6xxx_vtu_wait(chip); |
6b17e864 VD |
1344 | if (ret < 0) |
1345 | return ret; | |
1346 | ||
fad09c73 | 1347 | return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL); |
6b17e864 VD |
1348 | } |
1349 | ||
fad09c73 | 1350 | static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1351 | struct mv88e6xxx_vtu_entry *entry, |
b8fee957 VD |
1352 | unsigned int nibble_offset) |
1353 | { | |
b8fee957 | 1354 | u16 regs[3]; |
a935c052 | 1355 | int i, err; |
b8fee957 VD |
1356 | |
1357 | for (i = 0; i < 3; ++i) { | |
a935c052 | 1358 | u16 *reg = ®s[i]; |
b8fee957 | 1359 | |
a935c052 VD |
1360 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg); |
1361 | if (err) | |
1362 | return err; | |
b8fee957 VD |
1363 | } |
1364 | ||
370b4ffb | 1365 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
b8fee957 VD |
1366 | unsigned int shift = (i % 4) * 4 + nibble_offset; |
1367 | u16 reg = regs[i / 4]; | |
1368 | ||
1369 | entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK; | |
1370 | } | |
1371 | ||
1372 | return 0; | |
1373 | } | |
1374 | ||
fad09c73 | 1375 | static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1376 | struct mv88e6xxx_vtu_entry *entry) |
15d7d7d4 | 1377 | { |
fad09c73 | 1378 | return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0); |
15d7d7d4 VD |
1379 | } |
1380 | ||
fad09c73 | 1381 | static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1382 | struct mv88e6xxx_vtu_entry *entry) |
15d7d7d4 | 1383 | { |
fad09c73 | 1384 | return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2); |
15d7d7d4 VD |
1385 | } |
1386 | ||
fad09c73 | 1387 | static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1388 | struct mv88e6xxx_vtu_entry *entry, |
7dad08d7 VD |
1389 | unsigned int nibble_offset) |
1390 | { | |
7dad08d7 | 1391 | u16 regs[3] = { 0 }; |
a935c052 | 1392 | int i, err; |
7dad08d7 | 1393 | |
370b4ffb | 1394 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
7dad08d7 VD |
1395 | unsigned int shift = (i % 4) * 4 + nibble_offset; |
1396 | u8 data = entry->data[i]; | |
1397 | ||
1398 | regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift; | |
1399 | } | |
1400 | ||
1401 | for (i = 0; i < 3; ++i) { | |
a935c052 VD |
1402 | u16 reg = regs[i]; |
1403 | ||
1404 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg); | |
1405 | if (err) | |
1406 | return err; | |
7dad08d7 VD |
1407 | } |
1408 | ||
1409 | return 0; | |
1410 | } | |
1411 | ||
fad09c73 | 1412 | static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1413 | struct mv88e6xxx_vtu_entry *entry) |
15d7d7d4 | 1414 | { |
fad09c73 | 1415 | return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0); |
15d7d7d4 VD |
1416 | } |
1417 | ||
fad09c73 | 1418 | static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1419 | struct mv88e6xxx_vtu_entry *entry) |
15d7d7d4 | 1420 | { |
fad09c73 | 1421 | return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2); |
15d7d7d4 VD |
1422 | } |
1423 | ||
fad09c73 | 1424 | static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid) |
36d04ba1 | 1425 | { |
a935c052 VD |
1426 | return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, |
1427 | vid & GLOBAL_VTU_VID_MASK); | |
36d04ba1 VD |
1428 | } |
1429 | ||
fad09c73 | 1430 | static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1431 | struct mv88e6xxx_vtu_entry *entry) |
b8fee957 | 1432 | { |
b4e47c0f | 1433 | struct mv88e6xxx_vtu_entry next = { 0 }; |
a935c052 VD |
1434 | u16 val; |
1435 | int err; | |
b8fee957 | 1436 | |
a935c052 VD |
1437 | err = _mv88e6xxx_vtu_wait(chip); |
1438 | if (err) | |
1439 | return err; | |
b8fee957 | 1440 | |
a935c052 VD |
1441 | err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT); |
1442 | if (err) | |
1443 | return err; | |
b8fee957 | 1444 | |
a935c052 VD |
1445 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val); |
1446 | if (err) | |
1447 | return err; | |
b8fee957 | 1448 | |
a935c052 VD |
1449 | next.vid = val & GLOBAL_VTU_VID_MASK; |
1450 | next.valid = !!(val & GLOBAL_VTU_VID_VALID); | |
b8fee957 VD |
1451 | |
1452 | if (next.valid) { | |
a935c052 VD |
1453 | err = mv88e6xxx_vtu_data_read(chip, &next); |
1454 | if (err) | |
1455 | return err; | |
b8fee957 | 1456 | |
6dc10bbc | 1457 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) { |
a935c052 VD |
1458 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val); |
1459 | if (err) | |
1460 | return err; | |
b8fee957 | 1461 | |
a935c052 | 1462 | next.fid = val & GLOBAL_VTU_FID_MASK; |
fad09c73 | 1463 | } else if (mv88e6xxx_num_databases(chip) == 256) { |
11ea809f VD |
1464 | /* VTU DBNum[7:4] are located in VTU Operation 11:8, and |
1465 | * VTU DBNum[3:0] are located in VTU Operation 3:0 | |
1466 | */ | |
a935c052 VD |
1467 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val); |
1468 | if (err) | |
1469 | return err; | |
11ea809f | 1470 | |
a935c052 VD |
1471 | next.fid = (val & 0xf00) >> 4; |
1472 | next.fid |= val & 0xf; | |
2e7bd5ef | 1473 | } |
b8fee957 | 1474 | |
fad09c73 | 1475 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { |
a935c052 VD |
1476 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val); |
1477 | if (err) | |
1478 | return err; | |
b8fee957 | 1479 | |
a935c052 | 1480 | next.sid = val & GLOBAL_VTU_SID_MASK; |
b8fee957 VD |
1481 | } |
1482 | } | |
1483 | ||
1484 | *entry = next; | |
1485 | return 0; | |
1486 | } | |
1487 | ||
f81ec90f VD |
1488 | static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port, |
1489 | struct switchdev_obj_port_vlan *vlan, | |
1490 | int (*cb)(struct switchdev_obj *obj)) | |
ceff5eff | 1491 | { |
04bed143 | 1492 | struct mv88e6xxx_chip *chip = ds->priv; |
b4e47c0f | 1493 | struct mv88e6xxx_vtu_entry next; |
ceff5eff VD |
1494 | u16 pvid; |
1495 | int err; | |
1496 | ||
fad09c73 | 1497 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
54d77b5b VD |
1498 | return -EOPNOTSUPP; |
1499 | ||
fad09c73 | 1500 | mutex_lock(&chip->reg_lock); |
ceff5eff | 1501 | |
77064f37 | 1502 | err = mv88e6xxx_port_get_pvid(chip, port, &pvid); |
ceff5eff VD |
1503 | if (err) |
1504 | goto unlock; | |
1505 | ||
fad09c73 | 1506 | err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); |
ceff5eff VD |
1507 | if (err) |
1508 | goto unlock; | |
1509 | ||
1510 | do { | |
fad09c73 | 1511 | err = _mv88e6xxx_vtu_getnext(chip, &next); |
ceff5eff VD |
1512 | if (err) |
1513 | break; | |
1514 | ||
1515 | if (!next.valid) | |
1516 | break; | |
1517 | ||
1518 | if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) | |
1519 | continue; | |
1520 | ||
1521 | /* reinit and dump this VLAN obj */ | |
57d32310 VD |
1522 | vlan->vid_begin = next.vid; |
1523 | vlan->vid_end = next.vid; | |
ceff5eff VD |
1524 | vlan->flags = 0; |
1525 | ||
1526 | if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED) | |
1527 | vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED; | |
1528 | ||
1529 | if (next.vid == pvid) | |
1530 | vlan->flags |= BRIDGE_VLAN_INFO_PVID; | |
1531 | ||
1532 | err = cb(&vlan->obj); | |
1533 | if (err) | |
1534 | break; | |
1535 | } while (next.vid < GLOBAL_VTU_VID_MASK); | |
1536 | ||
1537 | unlock: | |
fad09c73 | 1538 | mutex_unlock(&chip->reg_lock); |
ceff5eff VD |
1539 | |
1540 | return err; | |
1541 | } | |
1542 | ||
fad09c73 | 1543 | static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1544 | struct mv88e6xxx_vtu_entry *entry) |
7dad08d7 | 1545 | { |
11ea809f | 1546 | u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE; |
7dad08d7 | 1547 | u16 reg = 0; |
a935c052 | 1548 | int err; |
7dad08d7 | 1549 | |
a935c052 VD |
1550 | err = _mv88e6xxx_vtu_wait(chip); |
1551 | if (err) | |
1552 | return err; | |
7dad08d7 VD |
1553 | |
1554 | if (!entry->valid) | |
1555 | goto loadpurge; | |
1556 | ||
1557 | /* Write port member tags */ | |
a935c052 VD |
1558 | err = mv88e6xxx_vtu_data_write(chip, entry); |
1559 | if (err) | |
1560 | return err; | |
7dad08d7 | 1561 | |
fad09c73 | 1562 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { |
7dad08d7 | 1563 | reg = entry->sid & GLOBAL_VTU_SID_MASK; |
a935c052 VD |
1564 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg); |
1565 | if (err) | |
1566 | return err; | |
b426e5f7 | 1567 | } |
7dad08d7 | 1568 | |
6dc10bbc | 1569 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) { |
7dad08d7 | 1570 | reg = entry->fid & GLOBAL_VTU_FID_MASK; |
a935c052 VD |
1571 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg); |
1572 | if (err) | |
1573 | return err; | |
fad09c73 | 1574 | } else if (mv88e6xxx_num_databases(chip) == 256) { |
11ea809f VD |
1575 | /* VTU DBNum[7:4] are located in VTU Operation 11:8, and |
1576 | * VTU DBNum[3:0] are located in VTU Operation 3:0 | |
1577 | */ | |
1578 | op |= (entry->fid & 0xf0) << 8; | |
1579 | op |= entry->fid & 0xf; | |
7dad08d7 VD |
1580 | } |
1581 | ||
1582 | reg = GLOBAL_VTU_VID_VALID; | |
1583 | loadpurge: | |
1584 | reg |= entry->vid & GLOBAL_VTU_VID_MASK; | |
a935c052 VD |
1585 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg); |
1586 | if (err) | |
1587 | return err; | |
7dad08d7 | 1588 | |
fad09c73 | 1589 | return _mv88e6xxx_vtu_cmd(chip, op); |
7dad08d7 VD |
1590 | } |
1591 | ||
fad09c73 | 1592 | static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid, |
b4e47c0f | 1593 | struct mv88e6xxx_vtu_entry *entry) |
0d3b33e6 | 1594 | { |
b4e47c0f | 1595 | struct mv88e6xxx_vtu_entry next = { 0 }; |
a935c052 VD |
1596 | u16 val; |
1597 | int err; | |
0d3b33e6 | 1598 | |
a935c052 VD |
1599 | err = _mv88e6xxx_vtu_wait(chip); |
1600 | if (err) | |
1601 | return err; | |
0d3b33e6 | 1602 | |
a935c052 VD |
1603 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, |
1604 | sid & GLOBAL_VTU_SID_MASK); | |
1605 | if (err) | |
1606 | return err; | |
0d3b33e6 | 1607 | |
a935c052 VD |
1608 | err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT); |
1609 | if (err) | |
1610 | return err; | |
0d3b33e6 | 1611 | |
a935c052 VD |
1612 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val); |
1613 | if (err) | |
1614 | return err; | |
0d3b33e6 | 1615 | |
a935c052 | 1616 | next.sid = val & GLOBAL_VTU_SID_MASK; |
0d3b33e6 | 1617 | |
a935c052 VD |
1618 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val); |
1619 | if (err) | |
1620 | return err; | |
0d3b33e6 | 1621 | |
a935c052 | 1622 | next.valid = !!(val & GLOBAL_VTU_VID_VALID); |
0d3b33e6 VD |
1623 | |
1624 | if (next.valid) { | |
a935c052 VD |
1625 | err = mv88e6xxx_stu_data_read(chip, &next); |
1626 | if (err) | |
1627 | return err; | |
0d3b33e6 VD |
1628 | } |
1629 | ||
1630 | *entry = next; | |
1631 | return 0; | |
1632 | } | |
1633 | ||
fad09c73 | 1634 | static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1635 | struct mv88e6xxx_vtu_entry *entry) |
0d3b33e6 VD |
1636 | { |
1637 | u16 reg = 0; | |
a935c052 | 1638 | int err; |
0d3b33e6 | 1639 | |
a935c052 VD |
1640 | err = _mv88e6xxx_vtu_wait(chip); |
1641 | if (err) | |
1642 | return err; | |
0d3b33e6 VD |
1643 | |
1644 | if (!entry->valid) | |
1645 | goto loadpurge; | |
1646 | ||
1647 | /* Write port states */ | |
a935c052 VD |
1648 | err = mv88e6xxx_stu_data_write(chip, entry); |
1649 | if (err) | |
1650 | return err; | |
0d3b33e6 VD |
1651 | |
1652 | reg = GLOBAL_VTU_VID_VALID; | |
1653 | loadpurge: | |
a935c052 VD |
1654 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg); |
1655 | if (err) | |
1656 | return err; | |
0d3b33e6 VD |
1657 | |
1658 | reg = entry->sid & GLOBAL_VTU_SID_MASK; | |
a935c052 VD |
1659 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg); |
1660 | if (err) | |
1661 | return err; | |
0d3b33e6 | 1662 | |
fad09c73 | 1663 | return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE); |
0d3b33e6 VD |
1664 | } |
1665 | ||
fad09c73 | 1666 | static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid) |
3285f9e8 VD |
1667 | { |
1668 | DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); | |
b4e47c0f | 1669 | struct mv88e6xxx_vtu_entry vlan; |
2db9ce1f | 1670 | int i, err; |
3285f9e8 VD |
1671 | |
1672 | bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); | |
1673 | ||
2db9ce1f | 1674 | /* Set every FID bit used by the (un)bridged ports */ |
370b4ffb | 1675 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
b4e48c50 | 1676 | err = mv88e6xxx_port_get_fid(chip, i, fid); |
2db9ce1f VD |
1677 | if (err) |
1678 | return err; | |
1679 | ||
1680 | set_bit(*fid, fid_bitmap); | |
1681 | } | |
1682 | ||
3285f9e8 | 1683 | /* Set every FID bit used by the VLAN entries */ |
fad09c73 | 1684 | err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); |
3285f9e8 VD |
1685 | if (err) |
1686 | return err; | |
1687 | ||
1688 | do { | |
fad09c73 | 1689 | err = _mv88e6xxx_vtu_getnext(chip, &vlan); |
3285f9e8 VD |
1690 | if (err) |
1691 | return err; | |
1692 | ||
1693 | if (!vlan.valid) | |
1694 | break; | |
1695 | ||
1696 | set_bit(vlan.fid, fid_bitmap); | |
1697 | } while (vlan.vid < GLOBAL_VTU_VID_MASK); | |
1698 | ||
1699 | /* The reset value 0x000 is used to indicate that multiple address | |
1700 | * databases are not needed. Return the next positive available. | |
1701 | */ | |
1702 | *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); | |
fad09c73 | 1703 | if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) |
3285f9e8 VD |
1704 | return -ENOSPC; |
1705 | ||
1706 | /* Clear the database */ | |
fad09c73 | 1707 | return _mv88e6xxx_atu_flush(chip, *fid, true); |
3285f9e8 VD |
1708 | } |
1709 | ||
fad09c73 | 1710 | static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid, |
b4e47c0f | 1711 | struct mv88e6xxx_vtu_entry *entry) |
0d3b33e6 | 1712 | { |
fad09c73 | 1713 | struct dsa_switch *ds = chip->ds; |
b4e47c0f | 1714 | struct mv88e6xxx_vtu_entry vlan = { |
0d3b33e6 VD |
1715 | .valid = true, |
1716 | .vid = vid, | |
1717 | }; | |
3285f9e8 VD |
1718 | int i, err; |
1719 | ||
fad09c73 | 1720 | err = _mv88e6xxx_fid_new(chip, &vlan.fid); |
3285f9e8 VD |
1721 | if (err) |
1722 | return err; | |
0d3b33e6 | 1723 | |
3d131f07 | 1724 | /* exclude all ports except the CPU and DSA ports */ |
370b4ffb | 1725 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) |
3d131f07 VD |
1726 | vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i) |
1727 | ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED | |
1728 | : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; | |
0d3b33e6 | 1729 | |
fad09c73 VD |
1730 | if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) || |
1731 | mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) { | |
b4e47c0f | 1732 | struct mv88e6xxx_vtu_entry vstp; |
0d3b33e6 VD |
1733 | |
1734 | /* Adding a VTU entry requires a valid STU entry. As VSTP is not | |
1735 | * implemented, only one STU entry is needed to cover all VTU | |
1736 | * entries. Thus, validate the SID 0. | |
1737 | */ | |
1738 | vlan.sid = 0; | |
fad09c73 | 1739 | err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp); |
0d3b33e6 VD |
1740 | if (err) |
1741 | return err; | |
1742 | ||
1743 | if (vstp.sid != vlan.sid || !vstp.valid) { | |
1744 | memset(&vstp, 0, sizeof(vstp)); | |
1745 | vstp.valid = true; | |
1746 | vstp.sid = vlan.sid; | |
1747 | ||
fad09c73 | 1748 | err = _mv88e6xxx_stu_loadpurge(chip, &vstp); |
0d3b33e6 VD |
1749 | if (err) |
1750 | return err; | |
1751 | } | |
0d3b33e6 VD |
1752 | } |
1753 | ||
1754 | *entry = vlan; | |
1755 | return 0; | |
1756 | } | |
1757 | ||
fad09c73 | 1758 | static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, |
b4e47c0f | 1759 | struct mv88e6xxx_vtu_entry *entry, bool creat) |
2fb5ef09 VD |
1760 | { |
1761 | int err; | |
1762 | ||
1763 | if (!vid) | |
1764 | return -EINVAL; | |
1765 | ||
fad09c73 | 1766 | err = _mv88e6xxx_vtu_vid_write(chip, vid - 1); |
2fb5ef09 VD |
1767 | if (err) |
1768 | return err; | |
1769 | ||
fad09c73 | 1770 | err = _mv88e6xxx_vtu_getnext(chip, entry); |
2fb5ef09 VD |
1771 | if (err) |
1772 | return err; | |
1773 | ||
1774 | if (entry->vid != vid || !entry->valid) { | |
1775 | if (!creat) | |
1776 | return -EOPNOTSUPP; | |
1777 | /* -ENOENT would've been more appropriate, but switchdev expects | |
1778 | * -EOPNOTSUPP to inform bridge about an eventual software VLAN. | |
1779 | */ | |
1780 | ||
fad09c73 | 1781 | err = _mv88e6xxx_vtu_new(chip, vid, entry); |
2fb5ef09 VD |
1782 | } |
1783 | ||
1784 | return err; | |
1785 | } | |
1786 | ||
da9c359e VD |
1787 | static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, |
1788 | u16 vid_begin, u16 vid_end) | |
1789 | { | |
04bed143 | 1790 | struct mv88e6xxx_chip *chip = ds->priv; |
b4e47c0f | 1791 | struct mv88e6xxx_vtu_entry vlan; |
da9c359e VD |
1792 | int i, err; |
1793 | ||
1794 | if (!vid_begin) | |
1795 | return -EOPNOTSUPP; | |
1796 | ||
fad09c73 | 1797 | mutex_lock(&chip->reg_lock); |
da9c359e | 1798 | |
fad09c73 | 1799 | err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1); |
da9c359e VD |
1800 | if (err) |
1801 | goto unlock; | |
1802 | ||
1803 | do { | |
fad09c73 | 1804 | err = _mv88e6xxx_vtu_getnext(chip, &vlan); |
da9c359e VD |
1805 | if (err) |
1806 | goto unlock; | |
1807 | ||
1808 | if (!vlan.valid) | |
1809 | break; | |
1810 | ||
1811 | if (vlan.vid > vid_end) | |
1812 | break; | |
1813 | ||
370b4ffb | 1814 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
da9c359e VD |
1815 | if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) |
1816 | continue; | |
1817 | ||
1818 | if (vlan.data[i] == | |
1819 | GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) | |
1820 | continue; | |
1821 | ||
fad09c73 VD |
1822 | if (chip->ports[i].bridge_dev == |
1823 | chip->ports[port].bridge_dev) | |
da9c359e VD |
1824 | break; /* same bridge, check next VLAN */ |
1825 | ||
c8b09808 | 1826 | netdev_warn(ds->ports[port].netdev, |
da9c359e VD |
1827 | "hardware VLAN %d already used by %s\n", |
1828 | vlan.vid, | |
fad09c73 | 1829 | netdev_name(chip->ports[i].bridge_dev)); |
da9c359e VD |
1830 | err = -EOPNOTSUPP; |
1831 | goto unlock; | |
1832 | } | |
1833 | } while (vlan.vid < vid_end); | |
1834 | ||
1835 | unlock: | |
fad09c73 | 1836 | mutex_unlock(&chip->reg_lock); |
da9c359e VD |
1837 | |
1838 | return err; | |
1839 | } | |
1840 | ||
f81ec90f VD |
1841 | static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, |
1842 | bool vlan_filtering) | |
214cdb99 | 1843 | { |
04bed143 | 1844 | struct mv88e6xxx_chip *chip = ds->priv; |
385a0995 | 1845 | u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE : |
214cdb99 | 1846 | PORT_CONTROL_2_8021Q_DISABLED; |
0e7b9925 | 1847 | int err; |
214cdb99 | 1848 | |
fad09c73 | 1849 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
54d77b5b VD |
1850 | return -EOPNOTSUPP; |
1851 | ||
fad09c73 | 1852 | mutex_lock(&chip->reg_lock); |
385a0995 | 1853 | err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); |
fad09c73 | 1854 | mutex_unlock(&chip->reg_lock); |
214cdb99 | 1855 | |
0e7b9925 | 1856 | return err; |
214cdb99 VD |
1857 | } |
1858 | ||
57d32310 VD |
1859 | static int |
1860 | mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, | |
1861 | const struct switchdev_obj_port_vlan *vlan, | |
1862 | struct switchdev_trans *trans) | |
76e398a6 | 1863 | { |
04bed143 | 1864 | struct mv88e6xxx_chip *chip = ds->priv; |
da9c359e VD |
1865 | int err; |
1866 | ||
fad09c73 | 1867 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
54d77b5b VD |
1868 | return -EOPNOTSUPP; |
1869 | ||
da9c359e VD |
1870 | /* If the requested port doesn't belong to the same bridge as the VLAN |
1871 | * members, do not support it (yet) and fallback to software VLAN. | |
1872 | */ | |
1873 | err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, | |
1874 | vlan->vid_end); | |
1875 | if (err) | |
1876 | return err; | |
1877 | ||
76e398a6 VD |
1878 | /* We don't need any dynamic resource from the kernel (yet), |
1879 | * so skip the prepare phase. | |
1880 | */ | |
1881 | return 0; | |
1882 | } | |
1883 | ||
fad09c73 | 1884 | static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, |
158bc065 | 1885 | u16 vid, bool untagged) |
0d3b33e6 | 1886 | { |
b4e47c0f | 1887 | struct mv88e6xxx_vtu_entry vlan; |
0d3b33e6 VD |
1888 | int err; |
1889 | ||
fad09c73 | 1890 | err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true); |
0d3b33e6 | 1891 | if (err) |
76e398a6 | 1892 | return err; |
0d3b33e6 | 1893 | |
0d3b33e6 VD |
1894 | vlan.data[port] = untagged ? |
1895 | GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED : | |
1896 | GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED; | |
1897 | ||
fad09c73 | 1898 | return _mv88e6xxx_vtu_loadpurge(chip, &vlan); |
76e398a6 VD |
1899 | } |
1900 | ||
f81ec90f VD |
1901 | static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, |
1902 | const struct switchdev_obj_port_vlan *vlan, | |
1903 | struct switchdev_trans *trans) | |
76e398a6 | 1904 | { |
04bed143 | 1905 | struct mv88e6xxx_chip *chip = ds->priv; |
76e398a6 VD |
1906 | bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; |
1907 | bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; | |
1908 | u16 vid; | |
76e398a6 | 1909 | |
fad09c73 | 1910 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
54d77b5b VD |
1911 | return; |
1912 | ||
fad09c73 | 1913 | mutex_lock(&chip->reg_lock); |
76e398a6 | 1914 | |
4d5770b3 | 1915 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) |
fad09c73 | 1916 | if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged)) |
c8b09808 AL |
1917 | netdev_err(ds->ports[port].netdev, |
1918 | "failed to add VLAN %d%c\n", | |
4d5770b3 | 1919 | vid, untagged ? 'u' : 't'); |
76e398a6 | 1920 | |
77064f37 | 1921 | if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) |
c8b09808 | 1922 | netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n", |
4d5770b3 | 1923 | vlan->vid_end); |
0d3b33e6 | 1924 | |
fad09c73 | 1925 | mutex_unlock(&chip->reg_lock); |
0d3b33e6 VD |
1926 | } |
1927 | ||
fad09c73 | 1928 | static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, |
158bc065 | 1929 | int port, u16 vid) |
7dad08d7 | 1930 | { |
fad09c73 | 1931 | struct dsa_switch *ds = chip->ds; |
b4e47c0f | 1932 | struct mv88e6xxx_vtu_entry vlan; |
7dad08d7 VD |
1933 | int i, err; |
1934 | ||
fad09c73 | 1935 | err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); |
7dad08d7 | 1936 | if (err) |
76e398a6 | 1937 | return err; |
7dad08d7 | 1938 | |
2fb5ef09 VD |
1939 | /* Tell switchdev if this VLAN is handled in software */ |
1940 | if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) | |
3c06f08b | 1941 | return -EOPNOTSUPP; |
7dad08d7 VD |
1942 | |
1943 | vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; | |
1944 | ||
1945 | /* keep the VLAN unless all ports are excluded */ | |
f02bdffc | 1946 | vlan.valid = false; |
370b4ffb | 1947 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
3d131f07 | 1948 | if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) |
7dad08d7 VD |
1949 | continue; |
1950 | ||
1951 | if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) { | |
f02bdffc | 1952 | vlan.valid = true; |
7dad08d7 VD |
1953 | break; |
1954 | } | |
1955 | } | |
1956 | ||
fad09c73 | 1957 | err = _mv88e6xxx_vtu_loadpurge(chip, &vlan); |
76e398a6 VD |
1958 | if (err) |
1959 | return err; | |
1960 | ||
fad09c73 | 1961 | return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false); |
76e398a6 VD |
1962 | } |
1963 | ||
f81ec90f VD |
1964 | static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, |
1965 | const struct switchdev_obj_port_vlan *vlan) | |
76e398a6 | 1966 | { |
04bed143 | 1967 | struct mv88e6xxx_chip *chip = ds->priv; |
76e398a6 VD |
1968 | u16 pvid, vid; |
1969 | int err = 0; | |
1970 | ||
fad09c73 | 1971 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
54d77b5b VD |
1972 | return -EOPNOTSUPP; |
1973 | ||
fad09c73 | 1974 | mutex_lock(&chip->reg_lock); |
76e398a6 | 1975 | |
77064f37 | 1976 | err = mv88e6xxx_port_get_pvid(chip, port, &pvid); |
7dad08d7 VD |
1977 | if (err) |
1978 | goto unlock; | |
1979 | ||
76e398a6 | 1980 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { |
fad09c73 | 1981 | err = _mv88e6xxx_port_vlan_del(chip, port, vid); |
76e398a6 VD |
1982 | if (err) |
1983 | goto unlock; | |
1984 | ||
1985 | if (vid == pvid) { | |
77064f37 | 1986 | err = mv88e6xxx_port_set_pvid(chip, port, 0); |
76e398a6 VD |
1987 | if (err) |
1988 | goto unlock; | |
1989 | } | |
1990 | } | |
1991 | ||
7dad08d7 | 1992 | unlock: |
fad09c73 | 1993 | mutex_unlock(&chip->reg_lock); |
7dad08d7 VD |
1994 | |
1995 | return err; | |
1996 | } | |
1997 | ||
fad09c73 | 1998 | static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip, |
c5723ac5 | 1999 | const unsigned char *addr) |
defb05b9 | 2000 | { |
a935c052 | 2001 | int i, err; |
defb05b9 GR |
2002 | |
2003 | for (i = 0; i < 3; i++) { | |
a935c052 VD |
2004 | err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i, |
2005 | (addr[i * 2] << 8) | addr[i * 2 + 1]); | |
2006 | if (err) | |
2007 | return err; | |
defb05b9 GR |
2008 | } |
2009 | ||
2010 | return 0; | |
2011 | } | |
2012 | ||
fad09c73 | 2013 | static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip, |
158bc065 | 2014 | unsigned char *addr) |
defb05b9 | 2015 | { |
a935c052 VD |
2016 | u16 val; |
2017 | int i, err; | |
defb05b9 GR |
2018 | |
2019 | for (i = 0; i < 3; i++) { | |
a935c052 VD |
2020 | err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val); |
2021 | if (err) | |
2022 | return err; | |
2023 | ||
2024 | addr[i * 2] = val >> 8; | |
2025 | addr[i * 2 + 1] = val & 0xff; | |
defb05b9 GR |
2026 | } |
2027 | ||
2028 | return 0; | |
2029 | } | |
2030 | ||
fad09c73 | 2031 | static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip, |
fd231c82 | 2032 | struct mv88e6xxx_atu_entry *entry) |
defb05b9 | 2033 | { |
6630e236 VD |
2034 | int ret; |
2035 | ||
fad09c73 | 2036 | ret = _mv88e6xxx_atu_wait(chip); |
defb05b9 GR |
2037 | if (ret < 0) |
2038 | return ret; | |
2039 | ||
fad09c73 | 2040 | ret = _mv88e6xxx_atu_mac_write(chip, entry->mac); |
defb05b9 GR |
2041 | if (ret < 0) |
2042 | return ret; | |
2043 | ||
fad09c73 | 2044 | ret = _mv88e6xxx_atu_data_write(chip, entry); |
fd231c82 | 2045 | if (ret < 0) |
87820510 VD |
2046 | return ret; |
2047 | ||
fad09c73 | 2048 | return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB); |
fd231c82 | 2049 | } |
87820510 | 2050 | |
88472939 VD |
2051 | static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, |
2052 | struct mv88e6xxx_atu_entry *entry); | |
2053 | ||
2054 | static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid, | |
2055 | const u8 *addr, struct mv88e6xxx_atu_entry *entry) | |
2056 | { | |
2057 | struct mv88e6xxx_atu_entry next; | |
2058 | int err; | |
2059 | ||
2060 | eth_broadcast_addr(next.mac); | |
2061 | ||
2062 | err = _mv88e6xxx_atu_mac_write(chip, next.mac); | |
2063 | if (err) | |
2064 | return err; | |
2065 | ||
2066 | do { | |
2067 | err = _mv88e6xxx_atu_getnext(chip, fid, &next); | |
2068 | if (err) | |
2069 | return err; | |
2070 | ||
2071 | if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED) | |
2072 | break; | |
2073 | ||
2074 | if (ether_addr_equal(next.mac, addr)) { | |
2075 | *entry = next; | |
2076 | return 0; | |
2077 | } | |
2078 | } while (!is_broadcast_ether_addr(next.mac)); | |
2079 | ||
2080 | memset(entry, 0, sizeof(*entry)); | |
2081 | entry->fid = fid; | |
2082 | ether_addr_copy(entry->mac, addr); | |
2083 | ||
2084 | return 0; | |
2085 | } | |
2086 | ||
83dabd1f VD |
2087 | static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, |
2088 | const unsigned char *addr, u16 vid, | |
2089 | u8 state) | |
fd231c82 | 2090 | { |
b4e47c0f | 2091 | struct mv88e6xxx_vtu_entry vlan; |
88472939 | 2092 | struct mv88e6xxx_atu_entry entry; |
3285f9e8 VD |
2093 | int err; |
2094 | ||
2db9ce1f VD |
2095 | /* Null VLAN ID corresponds to the port private database */ |
2096 | if (vid == 0) | |
b4e48c50 | 2097 | err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); |
2db9ce1f | 2098 | else |
fad09c73 | 2099 | err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); |
3285f9e8 VD |
2100 | if (err) |
2101 | return err; | |
fd231c82 | 2102 | |
88472939 VD |
2103 | err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry); |
2104 | if (err) | |
2105 | return err; | |
2106 | ||
2107 | /* Purge the ATU entry only if no port is using it anymore */ | |
2108 | if (state == GLOBAL_ATU_DATA_STATE_UNUSED) { | |
2109 | entry.portv_trunkid &= ~BIT(port); | |
2110 | if (!entry.portv_trunkid) | |
2111 | entry.state = GLOBAL_ATU_DATA_STATE_UNUSED; | |
2112 | } else { | |
2113 | entry.portv_trunkid |= BIT(port); | |
2114 | entry.state = state; | |
fd231c82 VD |
2115 | } |
2116 | ||
fad09c73 | 2117 | return _mv88e6xxx_atu_load(chip, &entry); |
87820510 VD |
2118 | } |
2119 | ||
f81ec90f VD |
2120 | static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, |
2121 | const struct switchdev_obj_port_fdb *fdb, | |
2122 | struct switchdev_trans *trans) | |
146a3206 VD |
2123 | { |
2124 | /* We don't need any dynamic resource from the kernel (yet), | |
2125 | * so skip the prepare phase. | |
2126 | */ | |
2127 | return 0; | |
2128 | } | |
2129 | ||
f81ec90f VD |
2130 | static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, |
2131 | const struct switchdev_obj_port_fdb *fdb, | |
2132 | struct switchdev_trans *trans) | |
87820510 | 2133 | { |
04bed143 | 2134 | struct mv88e6xxx_chip *chip = ds->priv; |
87820510 | 2135 | |
fad09c73 | 2136 | mutex_lock(&chip->reg_lock); |
83dabd1f VD |
2137 | if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, |
2138 | GLOBAL_ATU_DATA_STATE_UC_STATIC)) | |
2139 | netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n"); | |
fad09c73 | 2140 | mutex_unlock(&chip->reg_lock); |
87820510 VD |
2141 | } |
2142 | ||
f81ec90f VD |
2143 | static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, |
2144 | const struct switchdev_obj_port_fdb *fdb) | |
87820510 | 2145 | { |
04bed143 | 2146 | struct mv88e6xxx_chip *chip = ds->priv; |
83dabd1f | 2147 | int err; |
87820510 | 2148 | |
fad09c73 | 2149 | mutex_lock(&chip->reg_lock); |
83dabd1f VD |
2150 | err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, |
2151 | GLOBAL_ATU_DATA_STATE_UNUSED); | |
fad09c73 | 2152 | mutex_unlock(&chip->reg_lock); |
87820510 | 2153 | |
83dabd1f | 2154 | return err; |
87820510 VD |
2155 | } |
2156 | ||
fad09c73 | 2157 | static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, |
1d194046 | 2158 | struct mv88e6xxx_atu_entry *entry) |
6630e236 | 2159 | { |
1d194046 | 2160 | struct mv88e6xxx_atu_entry next = { 0 }; |
a935c052 VD |
2161 | u16 val; |
2162 | int err; | |
1d194046 VD |
2163 | |
2164 | next.fid = fid; | |
defb05b9 | 2165 | |
a935c052 VD |
2166 | err = _mv88e6xxx_atu_wait(chip); |
2167 | if (err) | |
2168 | return err; | |
6630e236 | 2169 | |
a935c052 VD |
2170 | err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB); |
2171 | if (err) | |
2172 | return err; | |
6630e236 | 2173 | |
a935c052 VD |
2174 | err = _mv88e6xxx_atu_mac_read(chip, next.mac); |
2175 | if (err) | |
2176 | return err; | |
6630e236 | 2177 | |
a935c052 VD |
2178 | err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val); |
2179 | if (err) | |
2180 | return err; | |
6630e236 | 2181 | |
a935c052 | 2182 | next.state = val & GLOBAL_ATU_DATA_STATE_MASK; |
1d194046 VD |
2183 | if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) { |
2184 | unsigned int mask, shift; | |
2185 | ||
a935c052 | 2186 | if (val & GLOBAL_ATU_DATA_TRUNK) { |
1d194046 VD |
2187 | next.trunk = true; |
2188 | mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; | |
2189 | shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; | |
2190 | } else { | |
2191 | next.trunk = false; | |
2192 | mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; | |
2193 | shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; | |
2194 | } | |
2195 | ||
a935c052 | 2196 | next.portv_trunkid = (val & mask) >> shift; |
1d194046 | 2197 | } |
cdf09697 | 2198 | |
1d194046 | 2199 | *entry = next; |
cdf09697 DM |
2200 | return 0; |
2201 | } | |
2202 | ||
83dabd1f VD |
2203 | static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, |
2204 | u16 fid, u16 vid, int port, | |
2205 | struct switchdev_obj *obj, | |
2206 | int (*cb)(struct switchdev_obj *obj)) | |
74b6ba0d VD |
2207 | { |
2208 | struct mv88e6xxx_atu_entry addr = { | |
2209 | .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, | |
2210 | }; | |
2211 | int err; | |
2212 | ||
fad09c73 | 2213 | err = _mv88e6xxx_atu_mac_write(chip, addr.mac); |
74b6ba0d VD |
2214 | if (err) |
2215 | return err; | |
2216 | ||
2217 | do { | |
fad09c73 | 2218 | err = _mv88e6xxx_atu_getnext(chip, fid, &addr); |
74b6ba0d | 2219 | if (err) |
83dabd1f | 2220 | return err; |
74b6ba0d VD |
2221 | |
2222 | if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED) | |
2223 | break; | |
2224 | ||
83dabd1f VD |
2225 | if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0) |
2226 | continue; | |
2227 | ||
2228 | if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) { | |
2229 | struct switchdev_obj_port_fdb *fdb; | |
74b6ba0d | 2230 | |
83dabd1f VD |
2231 | if (!is_unicast_ether_addr(addr.mac)) |
2232 | continue; | |
2233 | ||
2234 | fdb = SWITCHDEV_OBJ_PORT_FDB(obj); | |
74b6ba0d VD |
2235 | fdb->vid = vid; |
2236 | ether_addr_copy(fdb->addr, addr.mac); | |
83dabd1f VD |
2237 | if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC) |
2238 | fdb->ndm_state = NUD_NOARP; | |
2239 | else | |
2240 | fdb->ndm_state = NUD_REACHABLE; | |
7df8fbdd VD |
2241 | } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) { |
2242 | struct switchdev_obj_port_mdb *mdb; | |
2243 | ||
2244 | if (!is_multicast_ether_addr(addr.mac)) | |
2245 | continue; | |
2246 | ||
2247 | mdb = SWITCHDEV_OBJ_PORT_MDB(obj); | |
2248 | mdb->vid = vid; | |
2249 | ether_addr_copy(mdb->addr, addr.mac); | |
83dabd1f VD |
2250 | } else { |
2251 | return -EOPNOTSUPP; | |
74b6ba0d | 2252 | } |
83dabd1f VD |
2253 | |
2254 | err = cb(obj); | |
2255 | if (err) | |
2256 | return err; | |
74b6ba0d VD |
2257 | } while (!is_broadcast_ether_addr(addr.mac)); |
2258 | ||
2259 | return err; | |
2260 | } | |
2261 | ||
83dabd1f VD |
2262 | static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, |
2263 | struct switchdev_obj *obj, | |
2264 | int (*cb)(struct switchdev_obj *obj)) | |
f33475bd | 2265 | { |
b4e47c0f | 2266 | struct mv88e6xxx_vtu_entry vlan = { |
f33475bd VD |
2267 | .vid = GLOBAL_VTU_VID_MASK, /* all ones */ |
2268 | }; | |
2db9ce1f | 2269 | u16 fid; |
f33475bd VD |
2270 | int err; |
2271 | ||
2db9ce1f | 2272 | /* Dump port's default Filtering Information Database (VLAN ID 0) */ |
b4e48c50 | 2273 | err = mv88e6xxx_port_get_fid(chip, port, &fid); |
2db9ce1f | 2274 | if (err) |
83dabd1f | 2275 | return err; |
2db9ce1f | 2276 | |
83dabd1f | 2277 | err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb); |
2db9ce1f | 2278 | if (err) |
83dabd1f | 2279 | return err; |
2db9ce1f | 2280 | |
74b6ba0d | 2281 | /* Dump VLANs' Filtering Information Databases */ |
fad09c73 | 2282 | err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid); |
f33475bd | 2283 | if (err) |
83dabd1f | 2284 | return err; |
f33475bd VD |
2285 | |
2286 | do { | |
fad09c73 | 2287 | err = _mv88e6xxx_vtu_getnext(chip, &vlan); |
f33475bd | 2288 | if (err) |
83dabd1f | 2289 | return err; |
f33475bd VD |
2290 | |
2291 | if (!vlan.valid) | |
2292 | break; | |
2293 | ||
83dabd1f VD |
2294 | err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, |
2295 | obj, cb); | |
f33475bd | 2296 | if (err) |
83dabd1f | 2297 | return err; |
f33475bd VD |
2298 | } while (vlan.vid < GLOBAL_VTU_VID_MASK); |
2299 | ||
83dabd1f VD |
2300 | return err; |
2301 | } | |
2302 | ||
2303 | static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, | |
2304 | struct switchdev_obj_port_fdb *fdb, | |
2305 | int (*cb)(struct switchdev_obj *obj)) | |
2306 | { | |
04bed143 | 2307 | struct mv88e6xxx_chip *chip = ds->priv; |
83dabd1f VD |
2308 | int err; |
2309 | ||
2310 | mutex_lock(&chip->reg_lock); | |
2311 | err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb); | |
fad09c73 | 2312 | mutex_unlock(&chip->reg_lock); |
f33475bd VD |
2313 | |
2314 | return err; | |
2315 | } | |
2316 | ||
f81ec90f VD |
2317 | static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, |
2318 | struct net_device *bridge) | |
e79a8bcb | 2319 | { |
04bed143 | 2320 | struct mv88e6xxx_chip *chip = ds->priv; |
1d9619d5 | 2321 | int i, err = 0; |
466dfa07 | 2322 | |
fad09c73 | 2323 | mutex_lock(&chip->reg_lock); |
466dfa07 | 2324 | |
b7666efe | 2325 | /* Assign the bridge and remap each port's VLANTable */ |
fad09c73 | 2326 | chip->ports[port].bridge_dev = bridge; |
b7666efe | 2327 | |
370b4ffb | 2328 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
fad09c73 VD |
2329 | if (chip->ports[i].bridge_dev == bridge) { |
2330 | err = _mv88e6xxx_port_based_vlan_map(chip, i); | |
b7666efe VD |
2331 | if (err) |
2332 | break; | |
2333 | } | |
2334 | } | |
2335 | ||
fad09c73 | 2336 | mutex_unlock(&chip->reg_lock); |
a6692754 | 2337 | |
466dfa07 | 2338 | return err; |
e79a8bcb VD |
2339 | } |
2340 | ||
f81ec90f | 2341 | static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port) |
66d9cd0f | 2342 | { |
04bed143 | 2343 | struct mv88e6xxx_chip *chip = ds->priv; |
fad09c73 | 2344 | struct net_device *bridge = chip->ports[port].bridge_dev; |
16bfa702 | 2345 | int i; |
466dfa07 | 2346 | |
fad09c73 | 2347 | mutex_lock(&chip->reg_lock); |
466dfa07 | 2348 | |
b7666efe | 2349 | /* Unassign the bridge and remap each port's VLANTable */ |
fad09c73 | 2350 | chip->ports[port].bridge_dev = NULL; |
b7666efe | 2351 | |
370b4ffb | 2352 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) |
fad09c73 VD |
2353 | if (i == port || chip->ports[i].bridge_dev == bridge) |
2354 | if (_mv88e6xxx_port_based_vlan_map(chip, i)) | |
c8b09808 AL |
2355 | netdev_warn(ds->ports[i].netdev, |
2356 | "failed to remap\n"); | |
b7666efe | 2357 | |
fad09c73 | 2358 | mutex_unlock(&chip->reg_lock); |
66d9cd0f VD |
2359 | } |
2360 | ||
17e708ba VD |
2361 | static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) |
2362 | { | |
2363 | if (chip->info->ops->reset) | |
2364 | return chip->info->ops->reset(chip); | |
2365 | ||
2366 | return 0; | |
2367 | } | |
2368 | ||
309eca6d VD |
2369 | static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) |
2370 | { | |
2371 | struct gpio_desc *gpiod = chip->reset; | |
2372 | ||
2373 | /* If there is a GPIO connected to the reset pin, toggle it */ | |
2374 | if (gpiod) { | |
2375 | gpiod_set_value_cansleep(gpiod, 1); | |
2376 | usleep_range(10000, 20000); | |
2377 | gpiod_set_value_cansleep(gpiod, 0); | |
2378 | usleep_range(10000, 20000); | |
2379 | } | |
2380 | } | |
2381 | ||
4ac4b5a6 | 2382 | static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) |
552238b5 | 2383 | { |
4ac4b5a6 | 2384 | int i, err; |
552238b5 | 2385 | |
4ac4b5a6 | 2386 | /* Set all ports to the Disabled state */ |
370b4ffb | 2387 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { |
e28def33 VD |
2388 | err = mv88e6xxx_port_set_state(chip, i, |
2389 | PORT_CONTROL_STATE_DISABLED); | |
0e7b9925 AL |
2390 | if (err) |
2391 | return err; | |
552238b5 VD |
2392 | } |
2393 | ||
4ac4b5a6 VD |
2394 | /* Wait for transmit queues to drain, |
2395 | * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. | |
2396 | */ | |
552238b5 VD |
2397 | usleep_range(2000, 4000); |
2398 | ||
4ac4b5a6 VD |
2399 | return 0; |
2400 | } | |
2401 | ||
2402 | static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) | |
2403 | { | |
4ac4b5a6 VD |
2404 | int err; |
2405 | ||
2406 | err = mv88e6xxx_disable_ports(chip); | |
2407 | if (err) | |
2408 | return err; | |
2409 | ||
309eca6d | 2410 | mv88e6xxx_hardware_reset(chip); |
552238b5 | 2411 | |
17e708ba | 2412 | return mv88e6xxx_software_reset(chip); |
552238b5 VD |
2413 | } |
2414 | ||
09cb7dfd | 2415 | static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip) |
13a7ebb3 | 2416 | { |
09cb7dfd VD |
2417 | u16 val; |
2418 | int err; | |
13a7ebb3 | 2419 | |
09cb7dfd VD |
2420 | /* Clear Power Down bit */ |
2421 | err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val); | |
2422 | if (err) | |
2423 | return err; | |
13a7ebb3 | 2424 | |
09cb7dfd VD |
2425 | if (val & BMCR_PDOWN) { |
2426 | val &= ~BMCR_PDOWN; | |
2427 | err = mv88e6xxx_serdes_write(chip, MII_BMCR, val); | |
13a7ebb3 PU |
2428 | } |
2429 | ||
09cb7dfd | 2430 | return err; |
13a7ebb3 PU |
2431 | } |
2432 | ||
56995cbc AL |
2433 | static int mv88e6xxx_setup_port_dsa(struct mv88e6xxx_chip *chip, int port, |
2434 | int upstream_port) | |
2435 | { | |
2436 | int err; | |
2437 | ||
2438 | err = chip->info->ops->port_set_frame_mode( | |
2439 | chip, port, MV88E6XXX_FRAME_MODE_DSA); | |
2440 | if (err) | |
2441 | return err; | |
2442 | ||
2443 | return chip->info->ops->port_set_egress_unknowns( | |
2444 | chip, port, port == upstream_port); | |
2445 | } | |
2446 | ||
2447 | static int mv88e6xxx_setup_port_cpu(struct mv88e6xxx_chip *chip, int port) | |
2448 | { | |
2449 | int err; | |
2450 | ||
2451 | switch (chip->info->tag_protocol) { | |
2452 | case DSA_TAG_PROTO_EDSA: | |
2453 | err = chip->info->ops->port_set_frame_mode( | |
2454 | chip, port, MV88E6XXX_FRAME_MODE_ETHERTYPE); | |
2455 | if (err) | |
2456 | return err; | |
2457 | ||
2458 | err = mv88e6xxx_port_set_egress_mode( | |
2459 | chip, port, PORT_CONTROL_EGRESS_ADD_TAG); | |
2460 | if (err) | |
2461 | return err; | |
2462 | ||
2463 | if (chip->info->ops->port_set_ether_type) | |
2464 | err = chip->info->ops->port_set_ether_type( | |
2465 | chip, port, ETH_P_EDSA); | |
2466 | break; | |
2467 | ||
2468 | case DSA_TAG_PROTO_DSA: | |
2469 | err = chip->info->ops->port_set_frame_mode( | |
2470 | chip, port, MV88E6XXX_FRAME_MODE_DSA); | |
2471 | if (err) | |
2472 | return err; | |
2473 | ||
2474 | err = mv88e6xxx_port_set_egress_mode( | |
2475 | chip, port, PORT_CONTROL_EGRESS_UNMODIFIED); | |
2476 | break; | |
2477 | default: | |
2478 | err = -EINVAL; | |
2479 | } | |
2480 | ||
2481 | if (err) | |
2482 | return err; | |
2483 | ||
2484 | return chip->info->ops->port_set_egress_unknowns(chip, port, true); | |
2485 | } | |
2486 | ||
2487 | static int mv88e6xxx_setup_port_normal(struct mv88e6xxx_chip *chip, int port) | |
2488 | { | |
2489 | int err; | |
2490 | ||
2491 | err = chip->info->ops->port_set_frame_mode( | |
2492 | chip, port, MV88E6XXX_FRAME_MODE_NORMAL); | |
2493 | if (err) | |
2494 | return err; | |
2495 | ||
2496 | return chip->info->ops->port_set_egress_unknowns(chip, port, false); | |
2497 | } | |
2498 | ||
fad09c73 | 2499 | static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) |
d827e88a | 2500 | { |
fad09c73 | 2501 | struct dsa_switch *ds = chip->ds; |
0e7b9925 | 2502 | int err; |
54d792f2 | 2503 | u16 reg; |
d827e88a | 2504 | |
d78343d2 VD |
2505 | /* MAC Forcing register: don't force link, speed, duplex or flow control |
2506 | * state to any particular values on physical ports, but force the CPU | |
2507 | * port and all DSA ports to their maximum bandwidth and full duplex. | |
2508 | */ | |
2509 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) | |
2510 | err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, | |
2511 | SPEED_MAX, DUPLEX_FULL, | |
2512 | PHY_INTERFACE_MODE_NA); | |
2513 | else | |
2514 | err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, | |
2515 | SPEED_UNFORCED, DUPLEX_UNFORCED, | |
2516 | PHY_INTERFACE_MODE_NA); | |
2517 | if (err) | |
2518 | return err; | |
54d792f2 AL |
2519 | |
2520 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, | |
2521 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN | |
2522 | * tunneling, determine priority by looking at 802.1p and IP | |
2523 | * priority fields (IP prio has precedence), and set STP state | |
2524 | * to Forwarding. | |
2525 | * | |
2526 | * If this is the CPU link, use DSA or EDSA tagging depending | |
2527 | * on which tagging mode was configured. | |
2528 | * | |
2529 | * If this is a link to another switch, use DSA tagging mode. | |
2530 | * | |
2531 | * If this is the upstream port for this switch, enable | |
2532 | * forwarding of unknown unicasts and multicasts. | |
2533 | */ | |
56995cbc | 2534 | reg = PORT_CONTROL_IGMP_MLD_SNOOP | |
54d792f2 AL |
2535 | PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | |
2536 | PORT_CONTROL_STATE_FORWARDING; | |
56995cbc AL |
2537 | err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg); |
2538 | if (err) | |
2539 | return err; | |
6083ce71 | 2540 | |
56995cbc AL |
2541 | if (dsa_is_cpu_port(ds, port)) { |
2542 | err = mv88e6xxx_setup_port_cpu(chip, port); | |
2543 | } else if (dsa_is_dsa_port(ds, port)) { | |
2544 | err = mv88e6xxx_setup_port_dsa(chip, port, | |
2545 | dsa_upstream_port(ds)); | |
2546 | } else { | |
2547 | err = mv88e6xxx_setup_port_normal(chip, port); | |
54d792f2 | 2548 | } |
56995cbc AL |
2549 | if (err) |
2550 | return err; | |
54d792f2 | 2551 | |
13a7ebb3 PU |
2552 | /* If this port is connected to a SerDes, make sure the SerDes is not |
2553 | * powered down. | |
2554 | */ | |
09cb7dfd | 2555 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) { |
0e7b9925 AL |
2556 | err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®); |
2557 | if (err) | |
2558 | return err; | |
2559 | reg &= PORT_STATUS_CMODE_MASK; | |
2560 | if ((reg == PORT_STATUS_CMODE_100BASE_X) || | |
2561 | (reg == PORT_STATUS_CMODE_1000BASE_X) || | |
2562 | (reg == PORT_STATUS_CMODE_SGMII)) { | |
2563 | err = mv88e6xxx_serdes_power_on(chip); | |
2564 | if (err < 0) | |
2565 | return err; | |
13a7ebb3 PU |
2566 | } |
2567 | } | |
2568 | ||
8efdda4a | 2569 | /* Port Control 2: don't force a good FCS, set the maximum frame size to |
46fbe5e5 | 2570 | * 10240 bytes, disable 802.1q tags checking, don't discard tagged or |
8efdda4a VD |
2571 | * untagged frames on this port, do a destination address lookup on all |
2572 | * received packets as usual, disable ARP mirroring and don't send a | |
2573 | * copy of all transmitted/received frames on this port to the CPU. | |
54d792f2 AL |
2574 | */ |
2575 | reg = 0; | |
fad09c73 VD |
2576 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
2577 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || | |
2578 | mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) || | |
2579 | mv88e6xxx_6185_family(chip)) | |
54d792f2 AL |
2580 | reg = PORT_CONTROL_2_MAP_DA; |
2581 | ||
fad09c73 | 2582 | if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) { |
54d792f2 AL |
2583 | /* Set the upstream port this port should use */ |
2584 | reg |= dsa_upstream_port(ds); | |
2585 | /* enable forwarding of unknown multicast addresses to | |
2586 | * the upstream port | |
2587 | */ | |
2588 | if (port == dsa_upstream_port(ds)) | |
2589 | reg |= PORT_CONTROL_2_FORWARD_UNKNOWN; | |
2590 | } | |
2591 | ||
46fbe5e5 | 2592 | reg |= PORT_CONTROL_2_8021Q_DISABLED; |
8efdda4a | 2593 | |
54d792f2 | 2594 | if (reg) { |
0e7b9925 AL |
2595 | err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg); |
2596 | if (err) | |
2597 | return err; | |
54d792f2 AL |
2598 | } |
2599 | ||
5f436666 AL |
2600 | if (chip->info->ops->port_jumbo_config) { |
2601 | err = chip->info->ops->port_jumbo_config(chip, port); | |
2602 | if (err) | |
2603 | return err; | |
2604 | } | |
2605 | ||
54d792f2 AL |
2606 | /* Port Association Vector: when learning source addresses |
2607 | * of packets, add the address to the address database using | |
2608 | * a port bitmap that has only the bit for this port set and | |
2609 | * the other bits clear. | |
2610 | */ | |
4c7ea3c0 | 2611 | reg = 1 << port; |
996ecb82 VD |
2612 | /* Disable learning for CPU port */ |
2613 | if (dsa_is_cpu_port(ds, port)) | |
65fa4027 | 2614 | reg = 0; |
4c7ea3c0 | 2615 | |
0e7b9925 AL |
2616 | err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg); |
2617 | if (err) | |
2618 | return err; | |
54d792f2 AL |
2619 | |
2620 | /* Egress rate control 2: disable egress rate control. */ | |
0e7b9925 AL |
2621 | err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000); |
2622 | if (err) | |
2623 | return err; | |
54d792f2 | 2624 | |
b35d322a AL |
2625 | if (chip->info->ops->port_pause_config) { |
2626 | err = chip->info->ops->port_pause_config(chip, port); | |
0e7b9925 AL |
2627 | if (err) |
2628 | return err; | |
b35d322a | 2629 | } |
54d792f2 | 2630 | |
b35d322a AL |
2631 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
2632 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || | |
2633 | mv88e6xxx_6320_family(chip)) { | |
54d792f2 AL |
2634 | /* Port ATU control: disable limiting the number of |
2635 | * address database entries that this port is allowed | |
2636 | * to use. | |
2637 | */ | |
0e7b9925 AL |
2638 | err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL, |
2639 | 0x0000); | |
54d792f2 AL |
2640 | /* Priority Override: disable DA, SA and VTU priority |
2641 | * override. | |
2642 | */ | |
0e7b9925 AL |
2643 | err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE, |
2644 | 0x0000); | |
2645 | if (err) | |
2646 | return err; | |
ef0a7318 | 2647 | } |
2bbb33be | 2648 | |
ef0a7318 AL |
2649 | if (chip->info->ops->port_tag_remap) { |
2650 | err = chip->info->ops->port_tag_remap(chip, port); | |
0e7b9925 AL |
2651 | if (err) |
2652 | return err; | |
54d792f2 AL |
2653 | } |
2654 | ||
ef70b111 AL |
2655 | if (chip->info->ops->port_egress_rate_limiting) { |
2656 | err = chip->info->ops->port_egress_rate_limiting(chip, port); | |
0e7b9925 AL |
2657 | if (err) |
2658 | return err; | |
54d792f2 AL |
2659 | } |
2660 | ||
366f0a0f GR |
2661 | /* Port Control 1: disable trunking, disable sending |
2662 | * learning messages to this port. | |
d827e88a | 2663 | */ |
0e7b9925 AL |
2664 | err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000); |
2665 | if (err) | |
2666 | return err; | |
d827e88a | 2667 | |
207afda1 | 2668 | /* Port based VLAN map: give each port the same default address |
b7666efe VD |
2669 | * database, and allow bidirectional communication between the |
2670 | * CPU and DSA port(s), and the other ports. | |
d827e88a | 2671 | */ |
b4e48c50 | 2672 | err = mv88e6xxx_port_set_fid(chip, port, 0); |
0e7b9925 AL |
2673 | if (err) |
2674 | return err; | |
2db9ce1f | 2675 | |
0e7b9925 AL |
2676 | err = _mv88e6xxx_port_based_vlan_map(chip, port); |
2677 | if (err) | |
2678 | return err; | |
d827e88a GR |
2679 | |
2680 | /* Default VLAN ID and priority: don't set a default VLAN | |
2681 | * ID, and set the default packet priority to zero. | |
2682 | */ | |
0e7b9925 | 2683 | return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000); |
dbde9e66 AL |
2684 | } |
2685 | ||
aa0938c6 | 2686 | static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) |
3b4caa1b VD |
2687 | { |
2688 | int err; | |
2689 | ||
a935c052 | 2690 | err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]); |
3b4caa1b VD |
2691 | if (err) |
2692 | return err; | |
2693 | ||
a935c052 | 2694 | err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); |
3b4caa1b VD |
2695 | if (err) |
2696 | return err; | |
2697 | ||
a935c052 VD |
2698 | err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); |
2699 | if (err) | |
2700 | return err; | |
2701 | ||
2702 | return 0; | |
3b4caa1b VD |
2703 | } |
2704 | ||
acddbd21 VD |
2705 | static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip, |
2706 | unsigned int msecs) | |
2707 | { | |
2708 | const unsigned int coeff = chip->info->age_time_coeff; | |
2709 | const unsigned int min = 0x01 * coeff; | |
2710 | const unsigned int max = 0xff * coeff; | |
2711 | u8 age_time; | |
2712 | u16 val; | |
2713 | int err; | |
2714 | ||
2715 | if (msecs < min || msecs > max) | |
2716 | return -ERANGE; | |
2717 | ||
2718 | /* Round to nearest multiple of coeff */ | |
2719 | age_time = (msecs + coeff / 2) / coeff; | |
2720 | ||
a935c052 | 2721 | err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val); |
acddbd21 VD |
2722 | if (err) |
2723 | return err; | |
2724 | ||
2725 | /* AgeTime is 11:4 bits */ | |
2726 | val &= ~0xff0; | |
2727 | val |= age_time << 4; | |
2728 | ||
a935c052 | 2729 | return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val); |
acddbd21 VD |
2730 | } |
2731 | ||
2cfcd964 VD |
2732 | static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, |
2733 | unsigned int ageing_time) | |
2734 | { | |
04bed143 | 2735 | struct mv88e6xxx_chip *chip = ds->priv; |
2cfcd964 VD |
2736 | int err; |
2737 | ||
2738 | mutex_lock(&chip->reg_lock); | |
2739 | err = mv88e6xxx_g1_set_age_time(chip, ageing_time); | |
2740 | mutex_unlock(&chip->reg_lock); | |
2741 | ||
2742 | return err; | |
2743 | } | |
2744 | ||
9729934c | 2745 | static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) |
acdaffcc | 2746 | { |
fad09c73 | 2747 | struct dsa_switch *ds = chip->ds; |
b0745e87 | 2748 | u32 upstream_port = dsa_upstream_port(ds); |
119477bd | 2749 | u16 reg; |
552238b5 | 2750 | int err; |
54d792f2 | 2751 | |
119477bd VD |
2752 | /* Enable the PHY Polling Unit if present, don't discard any packets, |
2753 | * and mask all interrupt sources. | |
2754 | */ | |
dc30c35b AL |
2755 | err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®); |
2756 | if (err < 0) | |
2757 | return err; | |
2758 | ||
2759 | reg &= ~GLOBAL_CONTROL_PPU_ENABLE; | |
fad09c73 VD |
2760 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) || |
2761 | mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE)) | |
119477bd VD |
2762 | reg |= GLOBAL_CONTROL_PPU_ENABLE; |
2763 | ||
a935c052 | 2764 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg); |
119477bd VD |
2765 | if (err) |
2766 | return err; | |
2767 | ||
33641994 AL |
2768 | if (chip->info->ops->g1_set_cpu_port) { |
2769 | err = chip->info->ops->g1_set_cpu_port(chip, upstream_port); | |
2770 | if (err) | |
2771 | return err; | |
2772 | } | |
2773 | ||
2774 | if (chip->info->ops->g1_set_egress_port) { | |
2775 | err = chip->info->ops->g1_set_egress_port(chip, upstream_port); | |
2776 | if (err) | |
2777 | return err; | |
2778 | } | |
b0745e87 | 2779 | |
50484ff4 | 2780 | /* Disable remote management, and set the switch's DSA device number. */ |
a935c052 VD |
2781 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2, |
2782 | GLOBAL_CONTROL_2_MULTIPLE_CASCADE | | |
2783 | (ds->index & 0x1f)); | |
50484ff4 VD |
2784 | if (err) |
2785 | return err; | |
2786 | ||
acddbd21 VD |
2787 | /* Clear all the VTU and STU entries */ |
2788 | err = _mv88e6xxx_vtu_stu_flush(chip); | |
2789 | if (err < 0) | |
2790 | return err; | |
2791 | ||
54d792f2 AL |
2792 | /* Set the default address aging time to 5 minutes, and |
2793 | * enable address learn messages to be sent to all message | |
2794 | * ports. | |
2795 | */ | |
a935c052 VD |
2796 | err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, |
2797 | GLOBAL_ATU_CONTROL_LEARN2ALL); | |
48ace4ef | 2798 | if (err) |
08a01261 | 2799 | return err; |
54d792f2 | 2800 | |
acddbd21 VD |
2801 | err = mv88e6xxx_g1_set_age_time(chip, 300000); |
2802 | if (err) | |
9729934c VD |
2803 | return err; |
2804 | ||
2805 | /* Clear all ATU entries */ | |
2806 | err = _mv88e6xxx_atu_flush(chip, 0, true); | |
2807 | if (err) | |
2808 | return err; | |
2809 | ||
54d792f2 | 2810 | /* Configure the IP ToS mapping registers. */ |
a935c052 | 2811 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000); |
48ace4ef | 2812 | if (err) |
08a01261 | 2813 | return err; |
a935c052 | 2814 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000); |
48ace4ef | 2815 | if (err) |
08a01261 | 2816 | return err; |
a935c052 | 2817 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555); |
48ace4ef | 2818 | if (err) |
08a01261 | 2819 | return err; |
a935c052 | 2820 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555); |
48ace4ef | 2821 | if (err) |
08a01261 | 2822 | return err; |
a935c052 | 2823 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa); |
48ace4ef | 2824 | if (err) |
08a01261 | 2825 | return err; |
a935c052 | 2826 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa); |
48ace4ef | 2827 | if (err) |
08a01261 | 2828 | return err; |
a935c052 | 2829 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff); |
48ace4ef | 2830 | if (err) |
08a01261 | 2831 | return err; |
a935c052 | 2832 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff); |
48ace4ef | 2833 | if (err) |
08a01261 | 2834 | return err; |
54d792f2 AL |
2835 | |
2836 | /* Configure the IEEE 802.1p priority mapping register. */ | |
a935c052 | 2837 | err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41); |
48ace4ef | 2838 | if (err) |
08a01261 | 2839 | return err; |
54d792f2 | 2840 | |
de227387 AL |
2841 | /* Initialize the statistics unit */ |
2842 | err = mv88e6xxx_stats_set_histogram(chip); | |
2843 | if (err) | |
2844 | return err; | |
2845 | ||
9729934c | 2846 | /* Clear the statistics counters for all ports */ |
a935c052 VD |
2847 | err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP, |
2848 | GLOBAL_STATS_OP_FLUSH_ALL); | |
9729934c VD |
2849 | if (err) |
2850 | return err; | |
2851 | ||
2852 | /* Wait for the flush to complete. */ | |
7f9ef3af | 2853 | err = mv88e6xxx_g1_stats_wait(chip); |
9729934c VD |
2854 | if (err) |
2855 | return err; | |
2856 | ||
2857 | return 0; | |
2858 | } | |
2859 | ||
f81ec90f | 2860 | static int mv88e6xxx_setup(struct dsa_switch *ds) |
08a01261 | 2861 | { |
04bed143 | 2862 | struct mv88e6xxx_chip *chip = ds->priv; |
08a01261 | 2863 | int err; |
a1a6a4d1 VD |
2864 | int i; |
2865 | ||
fad09c73 VD |
2866 | chip->ds = ds; |
2867 | ds->slave_mii_bus = chip->mdio_bus; | |
08a01261 | 2868 | |
fad09c73 | 2869 | mutex_lock(&chip->reg_lock); |
08a01261 | 2870 | |
9729934c | 2871 | /* Setup Switch Port Registers */ |
370b4ffb | 2872 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { |
9729934c VD |
2873 | err = mv88e6xxx_setup_port(chip, i); |
2874 | if (err) | |
2875 | goto unlock; | |
2876 | } | |
2877 | ||
2878 | /* Setup Switch Global 1 Registers */ | |
2879 | err = mv88e6xxx_g1_setup(chip); | |
a1a6a4d1 VD |
2880 | if (err) |
2881 | goto unlock; | |
2882 | ||
9729934c VD |
2883 | /* Setup Switch Global 2 Registers */ |
2884 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) { | |
2885 | err = mv88e6xxx_g2_setup(chip); | |
a1a6a4d1 VD |
2886 | if (err) |
2887 | goto unlock; | |
2888 | } | |
08a01261 | 2889 | |
6e55f698 AL |
2890 | /* Some generations have the configuration of sending reserved |
2891 | * management frames to the CPU in global2, others in | |
2892 | * global1. Hence it does not fit the two setup functions | |
2893 | * above. | |
2894 | */ | |
2895 | if (chip->info->ops->mgmt_rsvd2cpu) { | |
2896 | err = chip->info->ops->mgmt_rsvd2cpu(chip); | |
2897 | if (err) | |
2898 | goto unlock; | |
2899 | } | |
2900 | ||
6b17e864 | 2901 | unlock: |
fad09c73 | 2902 | mutex_unlock(&chip->reg_lock); |
db687a56 | 2903 | |
48ace4ef | 2904 | return err; |
54d792f2 AL |
2905 | } |
2906 | ||
3b4caa1b VD |
2907 | static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr) |
2908 | { | |
04bed143 | 2909 | struct mv88e6xxx_chip *chip = ds->priv; |
3b4caa1b VD |
2910 | int err; |
2911 | ||
b073d4e2 VD |
2912 | if (!chip->info->ops->set_switch_mac) |
2913 | return -EOPNOTSUPP; | |
3b4caa1b | 2914 | |
b073d4e2 VD |
2915 | mutex_lock(&chip->reg_lock); |
2916 | err = chip->info->ops->set_switch_mac(chip, addr); | |
3b4caa1b VD |
2917 | mutex_unlock(&chip->reg_lock); |
2918 | ||
2919 | return err; | |
2920 | } | |
2921 | ||
e57e5e77 | 2922 | static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) |
fd3a0ee4 | 2923 | { |
fad09c73 | 2924 | struct mv88e6xxx_chip *chip = bus->priv; |
e57e5e77 VD |
2925 | u16 val; |
2926 | int err; | |
fd3a0ee4 | 2927 | |
370b4ffb | 2928 | if (phy >= mv88e6xxx_num_ports(chip)) |
158bc065 | 2929 | return 0xffff; |
fd3a0ee4 | 2930 | |
fad09c73 | 2931 | mutex_lock(&chip->reg_lock); |
e57e5e77 | 2932 | err = mv88e6xxx_phy_read(chip, phy, reg, &val); |
fad09c73 | 2933 | mutex_unlock(&chip->reg_lock); |
e57e5e77 VD |
2934 | |
2935 | return err ? err : val; | |
fd3a0ee4 AL |
2936 | } |
2937 | ||
e57e5e77 | 2938 | static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) |
fd3a0ee4 | 2939 | { |
fad09c73 | 2940 | struct mv88e6xxx_chip *chip = bus->priv; |
e57e5e77 | 2941 | int err; |
fd3a0ee4 | 2942 | |
370b4ffb | 2943 | if (phy >= mv88e6xxx_num_ports(chip)) |
158bc065 | 2944 | return 0xffff; |
fd3a0ee4 | 2945 | |
fad09c73 | 2946 | mutex_lock(&chip->reg_lock); |
e57e5e77 | 2947 | err = mv88e6xxx_phy_write(chip, phy, reg, val); |
fad09c73 | 2948 | mutex_unlock(&chip->reg_lock); |
e57e5e77 VD |
2949 | |
2950 | return err; | |
fd3a0ee4 AL |
2951 | } |
2952 | ||
fad09c73 | 2953 | static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, |
b516d453 AL |
2954 | struct device_node *np) |
2955 | { | |
2956 | static int index; | |
2957 | struct mii_bus *bus; | |
2958 | int err; | |
2959 | ||
b516d453 | 2960 | if (np) |
fad09c73 | 2961 | chip->mdio_np = of_get_child_by_name(np, "mdio"); |
b516d453 | 2962 | |
fad09c73 | 2963 | bus = devm_mdiobus_alloc(chip->dev); |
b516d453 AL |
2964 | if (!bus) |
2965 | return -ENOMEM; | |
2966 | ||
fad09c73 | 2967 | bus->priv = (void *)chip; |
b516d453 AL |
2968 | if (np) { |
2969 | bus->name = np->full_name; | |
2970 | snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name); | |
2971 | } else { | |
2972 | bus->name = "mv88e6xxx SMI"; | |
2973 | snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); | |
2974 | } | |
2975 | ||
2976 | bus->read = mv88e6xxx_mdio_read; | |
2977 | bus->write = mv88e6xxx_mdio_write; | |
fad09c73 | 2978 | bus->parent = chip->dev; |
b516d453 | 2979 | |
fad09c73 VD |
2980 | if (chip->mdio_np) |
2981 | err = of_mdiobus_register(bus, chip->mdio_np); | |
b516d453 AL |
2982 | else |
2983 | err = mdiobus_register(bus); | |
2984 | if (err) { | |
fad09c73 | 2985 | dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); |
b516d453 AL |
2986 | goto out; |
2987 | } | |
fad09c73 | 2988 | chip->mdio_bus = bus; |
b516d453 AL |
2989 | |
2990 | return 0; | |
2991 | ||
2992 | out: | |
fad09c73 VD |
2993 | if (chip->mdio_np) |
2994 | of_node_put(chip->mdio_np); | |
b516d453 AL |
2995 | |
2996 | return err; | |
2997 | } | |
2998 | ||
fad09c73 | 2999 | static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip) |
b516d453 AL |
3000 | |
3001 | { | |
fad09c73 | 3002 | struct mii_bus *bus = chip->mdio_bus; |
b516d453 AL |
3003 | |
3004 | mdiobus_unregister(bus); | |
3005 | ||
fad09c73 VD |
3006 | if (chip->mdio_np) |
3007 | of_node_put(chip->mdio_np); | |
b516d453 AL |
3008 | } |
3009 | ||
c22995c5 GR |
3010 | #ifdef CONFIG_NET_DSA_HWMON |
3011 | ||
3012 | static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp) | |
3013 | { | |
04bed143 | 3014 | struct mv88e6xxx_chip *chip = ds->priv; |
9c93829c | 3015 | u16 val; |
c22995c5 | 3016 | int ret; |
c22995c5 GR |
3017 | |
3018 | *temp = 0; | |
3019 | ||
fad09c73 | 3020 | mutex_lock(&chip->reg_lock); |
c22995c5 | 3021 | |
9c93829c | 3022 | ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6); |
c22995c5 GR |
3023 | if (ret < 0) |
3024 | goto error; | |
3025 | ||
3026 | /* Enable temperature sensor */ | |
9c93829c | 3027 | ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val); |
c22995c5 GR |
3028 | if (ret < 0) |
3029 | goto error; | |
3030 | ||
9c93829c | 3031 | ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5)); |
c22995c5 GR |
3032 | if (ret < 0) |
3033 | goto error; | |
3034 | ||
3035 | /* Wait for temperature to stabilize */ | |
3036 | usleep_range(10000, 12000); | |
3037 | ||
9c93829c VD |
3038 | ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val); |
3039 | if (ret < 0) | |
c22995c5 | 3040 | goto error; |
c22995c5 GR |
3041 | |
3042 | /* Disable temperature sensor */ | |
9c93829c | 3043 | ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5)); |
c22995c5 GR |
3044 | if (ret < 0) |
3045 | goto error; | |
3046 | ||
3047 | *temp = ((val & 0x1f) - 5) * 5; | |
3048 | ||
3049 | error: | |
9c93829c | 3050 | mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0); |
fad09c73 | 3051 | mutex_unlock(&chip->reg_lock); |
c22995c5 GR |
3052 | return ret; |
3053 | } | |
3054 | ||
3055 | static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp) | |
3056 | { | |
04bed143 | 3057 | struct mv88e6xxx_chip *chip = ds->priv; |
fad09c73 | 3058 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
9c93829c | 3059 | u16 val; |
c22995c5 GR |
3060 | int ret; |
3061 | ||
3062 | *temp = 0; | |
3063 | ||
9c93829c VD |
3064 | mutex_lock(&chip->reg_lock); |
3065 | ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val); | |
3066 | mutex_unlock(&chip->reg_lock); | |
c22995c5 GR |
3067 | if (ret < 0) |
3068 | return ret; | |
3069 | ||
9c93829c | 3070 | *temp = (val & 0xff) - 25; |
c22995c5 GR |
3071 | |
3072 | return 0; | |
3073 | } | |
3074 | ||
f81ec90f | 3075 | static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) |
c22995c5 | 3076 | { |
04bed143 | 3077 | struct mv88e6xxx_chip *chip = ds->priv; |
158bc065 | 3078 | |
fad09c73 | 3079 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP)) |
6594f615 VD |
3080 | return -EOPNOTSUPP; |
3081 | ||
fad09c73 | 3082 | if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip)) |
c22995c5 GR |
3083 | return mv88e63xx_get_temp(ds, temp); |
3084 | ||
3085 | return mv88e61xx_get_temp(ds, temp); | |
3086 | } | |
3087 | ||
f81ec90f | 3088 | static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp) |
c22995c5 | 3089 | { |
04bed143 | 3090 | struct mv88e6xxx_chip *chip = ds->priv; |
fad09c73 | 3091 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
9c93829c | 3092 | u16 val; |
c22995c5 GR |
3093 | int ret; |
3094 | ||
fad09c73 | 3095 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) |
c22995c5 GR |
3096 | return -EOPNOTSUPP; |
3097 | ||
3098 | *temp = 0; | |
3099 | ||
9c93829c VD |
3100 | mutex_lock(&chip->reg_lock); |
3101 | ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); | |
3102 | mutex_unlock(&chip->reg_lock); | |
c22995c5 GR |
3103 | if (ret < 0) |
3104 | return ret; | |
3105 | ||
9c93829c | 3106 | *temp = (((val >> 8) & 0x1f) * 5) - 25; |
c22995c5 GR |
3107 | |
3108 | return 0; | |
3109 | } | |
3110 | ||
f81ec90f | 3111 | static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp) |
c22995c5 | 3112 | { |
04bed143 | 3113 | struct mv88e6xxx_chip *chip = ds->priv; |
fad09c73 | 3114 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
9c93829c VD |
3115 | u16 val; |
3116 | int err; | |
c22995c5 | 3117 | |
fad09c73 | 3118 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) |
c22995c5 GR |
3119 | return -EOPNOTSUPP; |
3120 | ||
9c93829c VD |
3121 | mutex_lock(&chip->reg_lock); |
3122 | err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); | |
3123 | if (err) | |
3124 | goto unlock; | |
c22995c5 | 3125 | temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); |
9c93829c VD |
3126 | err = mv88e6xxx_phy_page_write(chip, phy, 6, 26, |
3127 | (val & 0xe0ff) | (temp << 8)); | |
3128 | unlock: | |
3129 | mutex_unlock(&chip->reg_lock); | |
3130 | ||
3131 | return err; | |
c22995c5 GR |
3132 | } |
3133 | ||
f81ec90f | 3134 | static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm) |
c22995c5 | 3135 | { |
04bed143 | 3136 | struct mv88e6xxx_chip *chip = ds->priv; |
fad09c73 | 3137 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
9c93829c | 3138 | u16 val; |
c22995c5 GR |
3139 | int ret; |
3140 | ||
fad09c73 | 3141 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) |
c22995c5 GR |
3142 | return -EOPNOTSUPP; |
3143 | ||
3144 | *alarm = false; | |
3145 | ||
9c93829c VD |
3146 | mutex_lock(&chip->reg_lock); |
3147 | ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); | |
3148 | mutex_unlock(&chip->reg_lock); | |
c22995c5 GR |
3149 | if (ret < 0) |
3150 | return ret; | |
3151 | ||
9c93829c | 3152 | *alarm = !!(val & 0x40); |
c22995c5 GR |
3153 | |
3154 | return 0; | |
3155 | } | |
3156 | #endif /* CONFIG_NET_DSA_HWMON */ | |
3157 | ||
855b1932 VD |
3158 | static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) |
3159 | { | |
04bed143 | 3160 | struct mv88e6xxx_chip *chip = ds->priv; |
855b1932 VD |
3161 | |
3162 | return chip->eeprom_len; | |
3163 | } | |
3164 | ||
855b1932 VD |
3165 | static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, |
3166 | struct ethtool_eeprom *eeprom, u8 *data) | |
3167 | { | |
04bed143 | 3168 | struct mv88e6xxx_chip *chip = ds->priv; |
855b1932 VD |
3169 | int err; |
3170 | ||
ee4dc2e7 VD |
3171 | if (!chip->info->ops->get_eeprom) |
3172 | return -EOPNOTSUPP; | |
855b1932 | 3173 | |
ee4dc2e7 VD |
3174 | mutex_lock(&chip->reg_lock); |
3175 | err = chip->info->ops->get_eeprom(chip, eeprom, data); | |
855b1932 VD |
3176 | mutex_unlock(&chip->reg_lock); |
3177 | ||
3178 | if (err) | |
3179 | return err; | |
3180 | ||
3181 | eeprom->magic = 0xc3ec4951; | |
3182 | ||
3183 | return 0; | |
3184 | } | |
3185 | ||
855b1932 VD |
3186 | static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, |
3187 | struct ethtool_eeprom *eeprom, u8 *data) | |
3188 | { | |
04bed143 | 3189 | struct mv88e6xxx_chip *chip = ds->priv; |
855b1932 VD |
3190 | int err; |
3191 | ||
ee4dc2e7 VD |
3192 | if (!chip->info->ops->set_eeprom) |
3193 | return -EOPNOTSUPP; | |
3194 | ||
855b1932 VD |
3195 | if (eeprom->magic != 0xc3ec4951) |
3196 | return -EINVAL; | |
3197 | ||
3198 | mutex_lock(&chip->reg_lock); | |
ee4dc2e7 | 3199 | err = chip->info->ops->set_eeprom(chip, eeprom, data); |
855b1932 VD |
3200 | mutex_unlock(&chip->reg_lock); |
3201 | ||
3202 | return err; | |
3203 | } | |
3204 | ||
b3469dd8 | 3205 | static const struct mv88e6xxx_ops mv88e6085_ops = { |
4b325d8c | 3206 | /* MV88E6XXX_FAMILY_6097 */ |
b073d4e2 | 3207 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
b3469dd8 VD |
3208 | .phy_read = mv88e6xxx_phy_ppu_read, |
3209 | .phy_write = mv88e6xxx_phy_ppu_write, | |
08ef7f10 | 3210 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3211 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3212 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 3213 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc AL |
3214 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3215 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3216 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
ef70b111 | 3217 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
b35d322a | 3218 | .port_pause_config = mv88e6097_port_pause_config, |
a605a0fe | 3219 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
dfafe449 AL |
3220 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3221 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3222 | .stats_get_stats = mv88e6095_stats_get_stats, |
33641994 AL |
3223 | .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, |
3224 | .g1_set_egress_port = mv88e6095_g1_set_egress_port, | |
6e55f698 | 3225 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3226 | .reset = mv88e6185_g1_reset, |
b3469dd8 VD |
3227 | }; |
3228 | ||
3229 | static const struct mv88e6xxx_ops mv88e6095_ops = { | |
4b325d8c | 3230 | /* MV88E6XXX_FAMILY_6095 */ |
b073d4e2 | 3231 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
b3469dd8 VD |
3232 | .phy_read = mv88e6xxx_phy_ppu_read, |
3233 | .phy_write = mv88e6xxx_phy_ppu_write, | |
08ef7f10 | 3234 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3235 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3236 | .port_set_speed = mv88e6185_port_set_speed, |
56995cbc AL |
3237 | .port_set_frame_mode = mv88e6085_port_set_frame_mode, |
3238 | .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns, | |
a605a0fe | 3239 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
dfafe449 AL |
3240 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3241 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3242 | .stats_get_stats = mv88e6095_stats_get_stats, |
6e55f698 | 3243 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3244 | .reset = mv88e6185_g1_reset, |
b3469dd8 VD |
3245 | }; |
3246 | ||
7d381a02 | 3247 | static const struct mv88e6xxx_ops mv88e6097_ops = { |
15da3cc8 | 3248 | /* MV88E6XXX_FAMILY_6097 */ |
7d381a02 SE |
3249 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3250 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3251 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3252 | .port_set_link = mv88e6xxx_port_set_link, | |
3253 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3254 | .port_set_speed = mv88e6185_port_set_speed, | |
ef0a7318 | 3255 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc AL |
3256 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3257 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3258 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
5f436666 | 3259 | .port_jumbo_config = mv88e6165_port_jumbo_config, |
ef70b111 | 3260 | .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, |
b35d322a | 3261 | .port_pause_config = mv88e6097_port_pause_config, |
7d381a02 SE |
3262 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
3263 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, | |
3264 | .stats_get_strings = mv88e6095_stats_get_strings, | |
3265 | .stats_get_stats = mv88e6095_stats_get_stats, | |
33641994 AL |
3266 | .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, |
3267 | .g1_set_egress_port = mv88e6095_g1_set_egress_port, | |
6e55f698 | 3268 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3269 | .reset = mv88e6352_g1_reset, |
7d381a02 SE |
3270 | }; |
3271 | ||
b3469dd8 | 3272 | static const struct mv88e6xxx_ops mv88e6123_ops = { |
4b325d8c | 3273 | /* MV88E6XXX_FAMILY_6165 */ |
b073d4e2 | 3274 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3275 | .phy_read = mv88e6xxx_read, |
3276 | .phy_write = mv88e6xxx_write, | |
08ef7f10 | 3277 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3278 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3279 | .port_set_speed = mv88e6185_port_set_speed, |
56995cbc AL |
3280 | .port_set_frame_mode = mv88e6085_port_set_frame_mode, |
3281 | .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns, | |
a605a0fe | 3282 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
dfafe449 AL |
3283 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3284 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3285 | .stats_get_stats = mv88e6095_stats_get_stats, |
33641994 AL |
3286 | .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, |
3287 | .g1_set_egress_port = mv88e6095_g1_set_egress_port, | |
6e55f698 | 3288 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3289 | .reset = mv88e6352_g1_reset, |
b3469dd8 VD |
3290 | }; |
3291 | ||
3292 | static const struct mv88e6xxx_ops mv88e6131_ops = { | |
4b325d8c | 3293 | /* MV88E6XXX_FAMILY_6185 */ |
b073d4e2 | 3294 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
b3469dd8 VD |
3295 | .phy_read = mv88e6xxx_phy_ppu_read, |
3296 | .phy_write = mv88e6xxx_phy_ppu_write, | |
08ef7f10 | 3297 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3298 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3299 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 3300 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc AL |
3301 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3302 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3303 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
5f436666 | 3304 | .port_jumbo_config = mv88e6165_port_jumbo_config, |
ef70b111 | 3305 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
b35d322a | 3306 | .port_pause_config = mv88e6097_port_pause_config, |
a605a0fe | 3307 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
dfafe449 AL |
3308 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3309 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3310 | .stats_get_stats = mv88e6095_stats_get_stats, |
33641994 AL |
3311 | .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, |
3312 | .g1_set_egress_port = mv88e6095_g1_set_egress_port, | |
6e55f698 | 3313 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3314 | .reset = mv88e6185_g1_reset, |
b3469dd8 VD |
3315 | }; |
3316 | ||
3317 | static const struct mv88e6xxx_ops mv88e6161_ops = { | |
4b325d8c | 3318 | /* MV88E6XXX_FAMILY_6165 */ |
b073d4e2 | 3319 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3320 | .phy_read = mv88e6xxx_read, |
3321 | .phy_write = mv88e6xxx_write, | |
08ef7f10 | 3322 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3323 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3324 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 3325 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc AL |
3326 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3327 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3328 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
5f436666 | 3329 | .port_jumbo_config = mv88e6165_port_jumbo_config, |
ef70b111 | 3330 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
b35d322a | 3331 | .port_pause_config = mv88e6097_port_pause_config, |
a605a0fe | 3332 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
dfafe449 AL |
3333 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3334 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3335 | .stats_get_stats = mv88e6095_stats_get_stats, |
33641994 AL |
3336 | .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, |
3337 | .g1_set_egress_port = mv88e6095_g1_set_egress_port, | |
6e55f698 | 3338 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3339 | .reset = mv88e6352_g1_reset, |
b3469dd8 VD |
3340 | }; |
3341 | ||
3342 | static const struct mv88e6xxx_ops mv88e6165_ops = { | |
4b325d8c | 3343 | /* MV88E6XXX_FAMILY_6165 */ |
b073d4e2 | 3344 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3345 | .phy_read = mv88e6xxx_read, |
3346 | .phy_write = mv88e6xxx_write, | |
08ef7f10 | 3347 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3348 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3349 | .port_set_speed = mv88e6185_port_set_speed, |
a605a0fe | 3350 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
dfafe449 AL |
3351 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3352 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3353 | .stats_get_stats = mv88e6095_stats_get_stats, |
33641994 AL |
3354 | .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, |
3355 | .g1_set_egress_port = mv88e6095_g1_set_egress_port, | |
6e55f698 | 3356 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3357 | .reset = mv88e6352_g1_reset, |
b3469dd8 VD |
3358 | }; |
3359 | ||
3360 | static const struct mv88e6xxx_ops mv88e6171_ops = { | |
4b325d8c | 3361 | /* MV88E6XXX_FAMILY_6351 */ |
b073d4e2 | 3362 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3363 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3364 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3365 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3366 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
94d66ae6 | 3367 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3368 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 3369 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc AL |
3370 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3371 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3372 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
5f436666 | 3373 | .port_jumbo_config = mv88e6165_port_jumbo_config, |
ef70b111 | 3374 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
b35d322a | 3375 | .port_pause_config = mv88e6097_port_pause_config, |
a605a0fe | 3376 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
3377 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3378 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3379 | .stats_get_stats = mv88e6095_stats_get_stats, |
33641994 AL |
3380 | .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, |
3381 | .g1_set_egress_port = mv88e6095_g1_set_egress_port, | |
6e55f698 | 3382 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3383 | .reset = mv88e6352_g1_reset, |
b3469dd8 VD |
3384 | }; |
3385 | ||
3386 | static const struct mv88e6xxx_ops mv88e6172_ops = { | |
4b325d8c | 3387 | /* MV88E6XXX_FAMILY_6352 */ |
ee4dc2e7 VD |
3388 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3389 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3390 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3391 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3392 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3393 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3394 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 3395 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3396 | .port_set_speed = mv88e6352_port_set_speed, |
ef0a7318 | 3397 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc AL |
3398 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3399 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3400 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
5f436666 | 3401 | .port_jumbo_config = mv88e6165_port_jumbo_config, |
ef70b111 | 3402 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
b35d322a | 3403 | .port_pause_config = mv88e6097_port_pause_config, |
a605a0fe | 3404 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
3405 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3406 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3407 | .stats_get_stats = mv88e6095_stats_get_stats, |
33641994 AL |
3408 | .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, |
3409 | .g1_set_egress_port = mv88e6095_g1_set_egress_port, | |
6e55f698 | 3410 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3411 | .reset = mv88e6352_g1_reset, |
b3469dd8 VD |
3412 | }; |
3413 | ||
3414 | static const struct mv88e6xxx_ops mv88e6175_ops = { | |
4b325d8c | 3415 | /* MV88E6XXX_FAMILY_6351 */ |
b073d4e2 | 3416 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3417 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3418 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3419 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3420 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
94d66ae6 | 3421 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3422 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 3423 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc AL |
3424 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3425 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3426 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
5f436666 | 3427 | .port_jumbo_config = mv88e6165_port_jumbo_config, |
ef70b111 | 3428 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
b35d322a | 3429 | .port_pause_config = mv88e6097_port_pause_config, |
a605a0fe | 3430 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
3431 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3432 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3433 | .stats_get_stats = mv88e6095_stats_get_stats, |
33641994 AL |
3434 | .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, |
3435 | .g1_set_egress_port = mv88e6095_g1_set_egress_port, | |
6e55f698 | 3436 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3437 | .reset = mv88e6352_g1_reset, |
b3469dd8 VD |
3438 | }; |
3439 | ||
3440 | static const struct mv88e6xxx_ops mv88e6176_ops = { | |
4b325d8c | 3441 | /* MV88E6XXX_FAMILY_6352 */ |
ee4dc2e7 VD |
3442 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3443 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3444 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3445 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3446 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3447 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3448 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 3449 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3450 | .port_set_speed = mv88e6352_port_set_speed, |
ef0a7318 | 3451 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc AL |
3452 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3453 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3454 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
5f436666 | 3455 | .port_jumbo_config = mv88e6165_port_jumbo_config, |
ef70b111 | 3456 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
b35d322a | 3457 | .port_pause_config = mv88e6097_port_pause_config, |
a605a0fe | 3458 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
3459 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3460 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3461 | .stats_get_stats = mv88e6095_stats_get_stats, |
33641994 AL |
3462 | .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, |
3463 | .g1_set_egress_port = mv88e6095_g1_set_egress_port, | |
6e55f698 | 3464 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3465 | .reset = mv88e6352_g1_reset, |
b3469dd8 VD |
3466 | }; |
3467 | ||
3468 | static const struct mv88e6xxx_ops mv88e6185_ops = { | |
4b325d8c | 3469 | /* MV88E6XXX_FAMILY_6185 */ |
b073d4e2 | 3470 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
b3469dd8 VD |
3471 | .phy_read = mv88e6xxx_phy_ppu_read, |
3472 | .phy_write = mv88e6xxx_phy_ppu_write, | |
08ef7f10 | 3473 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3474 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3475 | .port_set_speed = mv88e6185_port_set_speed, |
56995cbc AL |
3476 | .port_set_frame_mode = mv88e6085_port_set_frame_mode, |
3477 | .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns, | |
ef70b111 | 3478 | .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, |
a605a0fe | 3479 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
dfafe449 AL |
3480 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3481 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3482 | .stats_get_stats = mv88e6095_stats_get_stats, |
33641994 AL |
3483 | .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, |
3484 | .g1_set_egress_port = mv88e6095_g1_set_egress_port, | |
6e55f698 | 3485 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3486 | .reset = mv88e6185_g1_reset, |
b3469dd8 VD |
3487 | }; |
3488 | ||
1a3b39ec | 3489 | static const struct mv88e6xxx_ops mv88e6190_ops = { |
4b325d8c | 3490 | /* MV88E6XXX_FAMILY_6390 */ |
1a3b39ec AL |
3491 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3492 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3493 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3494 | .port_set_link = mv88e6xxx_port_set_link, | |
3495 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3496 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
3497 | .port_set_speed = mv88e6390_port_set_speed, | |
ef0a7318 | 3498 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc AL |
3499 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3500 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3501 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
3ce0e65e | 3502 | .port_pause_config = mv88e6390_port_pause_config, |
79523473 | 3503 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 3504 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
3505 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
3506 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 3507 | .stats_get_stats = mv88e6390_stats_get_stats, |
33641994 AL |
3508 | .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, |
3509 | .g1_set_egress_port = mv88e6390_g1_set_egress_port, | |
6e55f698 | 3510 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
17e708ba | 3511 | .reset = mv88e6352_g1_reset, |
1a3b39ec AL |
3512 | }; |
3513 | ||
3514 | static const struct mv88e6xxx_ops mv88e6190x_ops = { | |
4b325d8c | 3515 | /* MV88E6XXX_FAMILY_6390 */ |
1a3b39ec AL |
3516 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3517 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3518 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3519 | .port_set_link = mv88e6xxx_port_set_link, | |
3520 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3521 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
3522 | .port_set_speed = mv88e6390x_port_set_speed, | |
ef0a7318 | 3523 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc AL |
3524 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3525 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3526 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
3ce0e65e | 3527 | .port_pause_config = mv88e6390_port_pause_config, |
79523473 | 3528 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 3529 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
3530 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
3531 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 3532 | .stats_get_stats = mv88e6390_stats_get_stats, |
33641994 AL |
3533 | .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, |
3534 | .g1_set_egress_port = mv88e6390_g1_set_egress_port, | |
6e55f698 | 3535 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
17e708ba | 3536 | .reset = mv88e6352_g1_reset, |
1a3b39ec AL |
3537 | }; |
3538 | ||
3539 | static const struct mv88e6xxx_ops mv88e6191_ops = { | |
4b325d8c | 3540 | /* MV88E6XXX_FAMILY_6390 */ |
1a3b39ec AL |
3541 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3542 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3543 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3544 | .port_set_link = mv88e6xxx_port_set_link, | |
3545 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3546 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
3547 | .port_set_speed = mv88e6390_port_set_speed, | |
ef0a7318 | 3548 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc AL |
3549 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3550 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3551 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
3ce0e65e | 3552 | .port_pause_config = mv88e6390_port_pause_config, |
79523473 | 3553 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 3554 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
3555 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
3556 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 3557 | .stats_get_stats = mv88e6390_stats_get_stats, |
33641994 AL |
3558 | .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, |
3559 | .g1_set_egress_port = mv88e6390_g1_set_egress_port, | |
6e55f698 | 3560 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
17e708ba | 3561 | .reset = mv88e6352_g1_reset, |
1a3b39ec AL |
3562 | }; |
3563 | ||
b3469dd8 | 3564 | static const struct mv88e6xxx_ops mv88e6240_ops = { |
4b325d8c | 3565 | /* MV88E6XXX_FAMILY_6352 */ |
ee4dc2e7 VD |
3566 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3567 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3568 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3569 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3570 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3571 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3572 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 3573 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3574 | .port_set_speed = mv88e6352_port_set_speed, |
ef0a7318 | 3575 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc AL |
3576 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3577 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3578 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
5f436666 | 3579 | .port_jumbo_config = mv88e6165_port_jumbo_config, |
ef70b111 | 3580 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
b35d322a | 3581 | .port_pause_config = mv88e6097_port_pause_config, |
a605a0fe | 3582 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
3583 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3584 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3585 | .stats_get_stats = mv88e6095_stats_get_stats, |
33641994 AL |
3586 | .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, |
3587 | .g1_set_egress_port = mv88e6095_g1_set_egress_port, | |
6e55f698 | 3588 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3589 | .reset = mv88e6352_g1_reset, |
b3469dd8 VD |
3590 | }; |
3591 | ||
1a3b39ec | 3592 | static const struct mv88e6xxx_ops mv88e6290_ops = { |
4b325d8c | 3593 | /* MV88E6XXX_FAMILY_6390 */ |
1a3b39ec AL |
3594 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3595 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3596 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3597 | .port_set_link = mv88e6xxx_port_set_link, | |
3598 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3599 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
3600 | .port_set_speed = mv88e6390_port_set_speed, | |
ef0a7318 | 3601 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc AL |
3602 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3603 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3604 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
3ce0e65e | 3605 | .port_pause_config = mv88e6390_port_pause_config, |
79523473 | 3606 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 3607 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
3608 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
3609 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 3610 | .stats_get_stats = mv88e6390_stats_get_stats, |
33641994 AL |
3611 | .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, |
3612 | .g1_set_egress_port = mv88e6390_g1_set_egress_port, | |
6e55f698 | 3613 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
17e708ba | 3614 | .reset = mv88e6352_g1_reset, |
1a3b39ec AL |
3615 | }; |
3616 | ||
b3469dd8 | 3617 | static const struct mv88e6xxx_ops mv88e6320_ops = { |
4b325d8c | 3618 | /* MV88E6XXX_FAMILY_6320 */ |
ee4dc2e7 VD |
3619 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3620 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3621 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3622 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3623 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3624 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3625 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3626 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 3627 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc AL |
3628 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3629 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3630 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
5f436666 | 3631 | .port_jumbo_config = mv88e6165_port_jumbo_config, |
ef70b111 | 3632 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
b35d322a | 3633 | .port_pause_config = mv88e6097_port_pause_config, |
a605a0fe | 3634 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
3635 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
3636 | .stats_get_strings = mv88e6320_stats_get_strings, | |
052f947f | 3637 | .stats_get_stats = mv88e6320_stats_get_stats, |
33641994 AL |
3638 | .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, |
3639 | .g1_set_egress_port = mv88e6095_g1_set_egress_port, | |
6e55f698 | 3640 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3641 | .reset = mv88e6352_g1_reset, |
b3469dd8 VD |
3642 | }; |
3643 | ||
3644 | static const struct mv88e6xxx_ops mv88e6321_ops = { | |
4b325d8c | 3645 | /* MV88E6XXX_FAMILY_6321 */ |
ee4dc2e7 VD |
3646 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3647 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3648 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3649 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3650 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3651 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3652 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3653 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 3654 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc AL |
3655 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3656 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3657 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
5f436666 | 3658 | .port_jumbo_config = mv88e6165_port_jumbo_config, |
ef70b111 | 3659 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
b35d322a | 3660 | .port_pause_config = mv88e6097_port_pause_config, |
a605a0fe | 3661 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
3662 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
3663 | .stats_get_strings = mv88e6320_stats_get_strings, | |
052f947f | 3664 | .stats_get_stats = mv88e6320_stats_get_stats, |
33641994 AL |
3665 | .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, |
3666 | .g1_set_egress_port = mv88e6095_g1_set_egress_port, | |
17e708ba | 3667 | .reset = mv88e6352_g1_reset, |
b3469dd8 VD |
3668 | }; |
3669 | ||
3670 | static const struct mv88e6xxx_ops mv88e6350_ops = { | |
4b325d8c | 3671 | /* MV88E6XXX_FAMILY_6351 */ |
b073d4e2 | 3672 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3673 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3674 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3675 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3676 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
94d66ae6 | 3677 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3678 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 3679 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc AL |
3680 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3681 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3682 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
5f436666 | 3683 | .port_jumbo_config = mv88e6165_port_jumbo_config, |
ef70b111 | 3684 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
b35d322a | 3685 | .port_pause_config = mv88e6097_port_pause_config, |
a605a0fe | 3686 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
3687 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3688 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3689 | .stats_get_stats = mv88e6095_stats_get_stats, |
33641994 AL |
3690 | .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, |
3691 | .g1_set_egress_port = mv88e6095_g1_set_egress_port, | |
6e55f698 | 3692 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3693 | .reset = mv88e6352_g1_reset, |
b3469dd8 VD |
3694 | }; |
3695 | ||
3696 | static const struct mv88e6xxx_ops mv88e6351_ops = { | |
4b325d8c | 3697 | /* MV88E6XXX_FAMILY_6351 */ |
b073d4e2 | 3698 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3699 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3700 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3701 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3702 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
94d66ae6 | 3703 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3704 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 3705 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc AL |
3706 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3707 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3708 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
5f436666 | 3709 | .port_jumbo_config = mv88e6165_port_jumbo_config, |
ef70b111 | 3710 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
b35d322a | 3711 | .port_pause_config = mv88e6097_port_pause_config, |
a605a0fe | 3712 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
3713 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3714 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3715 | .stats_get_stats = mv88e6095_stats_get_stats, |
33641994 AL |
3716 | .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, |
3717 | .g1_set_egress_port = mv88e6095_g1_set_egress_port, | |
6e55f698 | 3718 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3719 | .reset = mv88e6352_g1_reset, |
b3469dd8 VD |
3720 | }; |
3721 | ||
3722 | static const struct mv88e6xxx_ops mv88e6352_ops = { | |
4b325d8c | 3723 | /* MV88E6XXX_FAMILY_6352 */ |
ee4dc2e7 VD |
3724 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3725 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3726 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3727 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3728 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3729 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3730 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 3731 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3732 | .port_set_speed = mv88e6352_port_set_speed, |
ef0a7318 | 3733 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc AL |
3734 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3735 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3736 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
5f436666 | 3737 | .port_jumbo_config = mv88e6165_port_jumbo_config, |
ef70b111 | 3738 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
b35d322a | 3739 | .port_pause_config = mv88e6097_port_pause_config, |
a605a0fe | 3740 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
3741 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3742 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3743 | .stats_get_stats = mv88e6095_stats_get_stats, |
33641994 AL |
3744 | .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, |
3745 | .g1_set_egress_port = mv88e6095_g1_set_egress_port, | |
6e55f698 | 3746 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3747 | .reset = mv88e6352_g1_reset, |
b3469dd8 VD |
3748 | }; |
3749 | ||
1a3b39ec | 3750 | static const struct mv88e6xxx_ops mv88e6390_ops = { |
4b325d8c | 3751 | /* MV88E6XXX_FAMILY_6390 */ |
1a3b39ec AL |
3752 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3753 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3754 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3755 | .port_set_link = mv88e6xxx_port_set_link, | |
3756 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3757 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
3758 | .port_set_speed = mv88e6390_port_set_speed, | |
ef0a7318 | 3759 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc AL |
3760 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3761 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3762 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
5f436666 | 3763 | .port_jumbo_config = mv88e6165_port_jumbo_config, |
ef70b111 | 3764 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
3ce0e65e | 3765 | .port_pause_config = mv88e6390_port_pause_config, |
79523473 | 3766 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 3767 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
3768 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
3769 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 3770 | .stats_get_stats = mv88e6390_stats_get_stats, |
33641994 AL |
3771 | .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, |
3772 | .g1_set_egress_port = mv88e6390_g1_set_egress_port, | |
6e55f698 | 3773 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
17e708ba | 3774 | .reset = mv88e6352_g1_reset, |
1a3b39ec AL |
3775 | }; |
3776 | ||
3777 | static const struct mv88e6xxx_ops mv88e6390x_ops = { | |
4b325d8c | 3778 | /* MV88E6XXX_FAMILY_6390 */ |
1a3b39ec AL |
3779 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3780 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3781 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3782 | .port_set_link = mv88e6xxx_port_set_link, | |
3783 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3784 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
3785 | .port_set_speed = mv88e6390x_port_set_speed, | |
ef0a7318 | 3786 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc AL |
3787 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3788 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3789 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
5f436666 | 3790 | .port_jumbo_config = mv88e6165_port_jumbo_config, |
ef70b111 | 3791 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
3ce0e65e | 3792 | .port_pause_config = mv88e6390_port_pause_config, |
79523473 | 3793 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 3794 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
3795 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
3796 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 3797 | .stats_get_stats = mv88e6390_stats_get_stats, |
33641994 AL |
3798 | .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, |
3799 | .g1_set_egress_port = mv88e6390_g1_set_egress_port, | |
6e55f698 | 3800 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
17e708ba | 3801 | .reset = mv88e6352_g1_reset, |
1a3b39ec AL |
3802 | }; |
3803 | ||
3804 | static const struct mv88e6xxx_ops mv88e6391_ops = { | |
4b325d8c | 3805 | /* MV88E6XXX_FAMILY_6390 */ |
1a3b39ec AL |
3806 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3807 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3808 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3809 | .port_set_link = mv88e6xxx_port_set_link, | |
3810 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3811 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
3812 | .port_set_speed = mv88e6390_port_set_speed, | |
ef0a7318 | 3813 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc AL |
3814 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
3815 | .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, | |
3816 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
3ce0e65e | 3817 | .port_pause_config = mv88e6390_port_pause_config, |
79523473 | 3818 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 3819 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
3820 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
3821 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 3822 | .stats_get_stats = mv88e6390_stats_get_stats, |
33641994 AL |
3823 | .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, |
3824 | .g1_set_egress_port = mv88e6390_g1_set_egress_port, | |
6e55f698 | 3825 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
17e708ba | 3826 | .reset = mv88e6352_g1_reset, |
1a3b39ec AL |
3827 | }; |
3828 | ||
56995cbc AL |
3829 | static int mv88e6xxx_verify_madatory_ops(struct mv88e6xxx_chip *chip, |
3830 | const struct mv88e6xxx_ops *ops) | |
3831 | { | |
3832 | if (!ops->port_set_frame_mode) { | |
3833 | dev_err(chip->dev, "Missing port_set_frame_mode"); | |
3834 | return -EINVAL; | |
3835 | } | |
3836 | ||
3837 | if (!ops->port_set_egress_unknowns) { | |
3838 | dev_err(chip->dev, "Missing port_set_egress_mode"); | |
3839 | return -EINVAL; | |
3840 | } | |
3841 | ||
3842 | return 0; | |
3843 | } | |
3844 | ||
f81ec90f VD |
3845 | static const struct mv88e6xxx_info mv88e6xxx_table[] = { |
3846 | [MV88E6085] = { | |
3847 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6085, | |
3848 | .family = MV88E6XXX_FAMILY_6097, | |
3849 | .name = "Marvell 88E6085", | |
3850 | .num_databases = 4096, | |
3851 | .num_ports = 10, | |
9dddd478 | 3852 | .port_base_addr = 0x10, |
a935c052 | 3853 | .global1_addr = 0x1b, |
acddbd21 | 3854 | .age_time_coeff = 15000, |
dc30c35b | 3855 | .g1_irqs = 8, |
443d5a1b | 3856 | .tag_protocol = DSA_TAG_PROTO_DSA, |
f81ec90f | 3857 | .flags = MV88E6XXX_FLAGS_FAMILY_6097, |
b3469dd8 | 3858 | .ops = &mv88e6085_ops, |
f81ec90f VD |
3859 | }, |
3860 | ||
3861 | [MV88E6095] = { | |
3862 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6095, | |
3863 | .family = MV88E6XXX_FAMILY_6095, | |
3864 | .name = "Marvell 88E6095/88E6095F", | |
3865 | .num_databases = 256, | |
3866 | .num_ports = 11, | |
9dddd478 | 3867 | .port_base_addr = 0x10, |
a935c052 | 3868 | .global1_addr = 0x1b, |
acddbd21 | 3869 | .age_time_coeff = 15000, |
dc30c35b | 3870 | .g1_irqs = 8, |
443d5a1b | 3871 | .tag_protocol = DSA_TAG_PROTO_DSA, |
f81ec90f | 3872 | .flags = MV88E6XXX_FLAGS_FAMILY_6095, |
b3469dd8 | 3873 | .ops = &mv88e6095_ops, |
f81ec90f VD |
3874 | }, |
3875 | ||
7d381a02 SE |
3876 | [MV88E6097] = { |
3877 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6097, | |
3878 | .family = MV88E6XXX_FAMILY_6097, | |
3879 | .name = "Marvell 88E6097/88E6097F", | |
3880 | .num_databases = 4096, | |
3881 | .num_ports = 11, | |
3882 | .port_base_addr = 0x10, | |
3883 | .global1_addr = 0x1b, | |
3884 | .age_time_coeff = 15000, | |
c534178b | 3885 | .g1_irqs = 8, |
2bfcfcd3 | 3886 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
7d381a02 SE |
3887 | .flags = MV88E6XXX_FLAGS_FAMILY_6097, |
3888 | .ops = &mv88e6097_ops, | |
3889 | }, | |
3890 | ||
f81ec90f VD |
3891 | [MV88E6123] = { |
3892 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6123, | |
3893 | .family = MV88E6XXX_FAMILY_6165, | |
3894 | .name = "Marvell 88E6123", | |
3895 | .num_databases = 4096, | |
3896 | .num_ports = 3, | |
9dddd478 | 3897 | .port_base_addr = 0x10, |
a935c052 | 3898 | .global1_addr = 0x1b, |
acddbd21 | 3899 | .age_time_coeff = 15000, |
dc30c35b | 3900 | .g1_irqs = 9, |
443d5a1b | 3901 | .tag_protocol = DSA_TAG_PROTO_DSA, |
f81ec90f | 3902 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
b3469dd8 | 3903 | .ops = &mv88e6123_ops, |
f81ec90f VD |
3904 | }, |
3905 | ||
3906 | [MV88E6131] = { | |
3907 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6131, | |
3908 | .family = MV88E6XXX_FAMILY_6185, | |
3909 | .name = "Marvell 88E6131", | |
3910 | .num_databases = 256, | |
3911 | .num_ports = 8, | |
9dddd478 | 3912 | .port_base_addr = 0x10, |
a935c052 | 3913 | .global1_addr = 0x1b, |
acddbd21 | 3914 | .age_time_coeff = 15000, |
dc30c35b | 3915 | .g1_irqs = 9, |
443d5a1b | 3916 | .tag_protocol = DSA_TAG_PROTO_DSA, |
f81ec90f | 3917 | .flags = MV88E6XXX_FLAGS_FAMILY_6185, |
b3469dd8 | 3918 | .ops = &mv88e6131_ops, |
f81ec90f VD |
3919 | }, |
3920 | ||
3921 | [MV88E6161] = { | |
3922 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6161, | |
3923 | .family = MV88E6XXX_FAMILY_6165, | |
3924 | .name = "Marvell 88E6161", | |
3925 | .num_databases = 4096, | |
3926 | .num_ports = 6, | |
9dddd478 | 3927 | .port_base_addr = 0x10, |
a935c052 | 3928 | .global1_addr = 0x1b, |
acddbd21 | 3929 | .age_time_coeff = 15000, |
dc30c35b | 3930 | .g1_irqs = 9, |
443d5a1b | 3931 | .tag_protocol = DSA_TAG_PROTO_DSA, |
f81ec90f | 3932 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
b3469dd8 | 3933 | .ops = &mv88e6161_ops, |
f81ec90f VD |
3934 | }, |
3935 | ||
3936 | [MV88E6165] = { | |
3937 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6165, | |
3938 | .family = MV88E6XXX_FAMILY_6165, | |
3939 | .name = "Marvell 88E6165", | |
3940 | .num_databases = 4096, | |
3941 | .num_ports = 6, | |
9dddd478 | 3942 | .port_base_addr = 0x10, |
a935c052 | 3943 | .global1_addr = 0x1b, |
acddbd21 | 3944 | .age_time_coeff = 15000, |
dc30c35b | 3945 | .g1_irqs = 9, |
443d5a1b | 3946 | .tag_protocol = DSA_TAG_PROTO_DSA, |
f81ec90f | 3947 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
b3469dd8 | 3948 | .ops = &mv88e6165_ops, |
f81ec90f VD |
3949 | }, |
3950 | ||
3951 | [MV88E6171] = { | |
3952 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6171, | |
3953 | .family = MV88E6XXX_FAMILY_6351, | |
3954 | .name = "Marvell 88E6171", | |
3955 | .num_databases = 4096, | |
3956 | .num_ports = 7, | |
9dddd478 | 3957 | .port_base_addr = 0x10, |
a935c052 | 3958 | .global1_addr = 0x1b, |
acddbd21 | 3959 | .age_time_coeff = 15000, |
dc30c35b | 3960 | .g1_irqs = 9, |
443d5a1b | 3961 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 3962 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
b3469dd8 | 3963 | .ops = &mv88e6171_ops, |
f81ec90f VD |
3964 | }, |
3965 | ||
3966 | [MV88E6172] = { | |
3967 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6172, | |
3968 | .family = MV88E6XXX_FAMILY_6352, | |
3969 | .name = "Marvell 88E6172", | |
3970 | .num_databases = 4096, | |
3971 | .num_ports = 7, | |
9dddd478 | 3972 | .port_base_addr = 0x10, |
a935c052 | 3973 | .global1_addr = 0x1b, |
acddbd21 | 3974 | .age_time_coeff = 15000, |
dc30c35b | 3975 | .g1_irqs = 9, |
443d5a1b | 3976 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 3977 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
b3469dd8 | 3978 | .ops = &mv88e6172_ops, |
f81ec90f VD |
3979 | }, |
3980 | ||
3981 | [MV88E6175] = { | |
3982 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6175, | |
3983 | .family = MV88E6XXX_FAMILY_6351, | |
3984 | .name = "Marvell 88E6175", | |
3985 | .num_databases = 4096, | |
3986 | .num_ports = 7, | |
9dddd478 | 3987 | .port_base_addr = 0x10, |
a935c052 | 3988 | .global1_addr = 0x1b, |
acddbd21 | 3989 | .age_time_coeff = 15000, |
dc30c35b | 3990 | .g1_irqs = 9, |
443d5a1b | 3991 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 3992 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
b3469dd8 | 3993 | .ops = &mv88e6175_ops, |
f81ec90f VD |
3994 | }, |
3995 | ||
3996 | [MV88E6176] = { | |
3997 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6176, | |
3998 | .family = MV88E6XXX_FAMILY_6352, | |
3999 | .name = "Marvell 88E6176", | |
4000 | .num_databases = 4096, | |
4001 | .num_ports = 7, | |
9dddd478 | 4002 | .port_base_addr = 0x10, |
a935c052 | 4003 | .global1_addr = 0x1b, |
acddbd21 | 4004 | .age_time_coeff = 15000, |
dc30c35b | 4005 | .g1_irqs = 9, |
443d5a1b | 4006 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 4007 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
b3469dd8 | 4008 | .ops = &mv88e6176_ops, |
f81ec90f VD |
4009 | }, |
4010 | ||
4011 | [MV88E6185] = { | |
4012 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6185, | |
4013 | .family = MV88E6XXX_FAMILY_6185, | |
4014 | .name = "Marvell 88E6185", | |
4015 | .num_databases = 256, | |
4016 | .num_ports = 10, | |
9dddd478 | 4017 | .port_base_addr = 0x10, |
a935c052 | 4018 | .global1_addr = 0x1b, |
acddbd21 | 4019 | .age_time_coeff = 15000, |
dc30c35b | 4020 | .g1_irqs = 8, |
443d5a1b | 4021 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 4022 | .flags = MV88E6XXX_FLAGS_FAMILY_6185, |
b3469dd8 | 4023 | .ops = &mv88e6185_ops, |
f81ec90f VD |
4024 | }, |
4025 | ||
1a3b39ec AL |
4026 | [MV88E6190] = { |
4027 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6190, | |
4028 | .family = MV88E6XXX_FAMILY_6390, | |
4029 | .name = "Marvell 88E6190", | |
4030 | .num_databases = 4096, | |
4031 | .num_ports = 11, /* 10 + Z80 */ | |
4032 | .port_base_addr = 0x0, | |
4033 | .global1_addr = 0x1b, | |
443d5a1b | 4034 | .tag_protocol = DSA_TAG_PROTO_DSA, |
1a3b39ec AL |
4035 | .age_time_coeff = 15000, |
4036 | .g1_irqs = 9, | |
4037 | .flags = MV88E6XXX_FLAGS_FAMILY_6390, | |
4038 | .ops = &mv88e6190_ops, | |
4039 | }, | |
4040 | ||
4041 | [MV88E6190X] = { | |
4042 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X, | |
4043 | .family = MV88E6XXX_FAMILY_6390, | |
4044 | .name = "Marvell 88E6190X", | |
4045 | .num_databases = 4096, | |
4046 | .num_ports = 11, /* 10 + Z80 */ | |
4047 | .port_base_addr = 0x0, | |
4048 | .global1_addr = 0x1b, | |
4049 | .age_time_coeff = 15000, | |
4050 | .g1_irqs = 9, | |
443d5a1b | 4051 | .tag_protocol = DSA_TAG_PROTO_DSA, |
1a3b39ec AL |
4052 | .flags = MV88E6XXX_FLAGS_FAMILY_6390, |
4053 | .ops = &mv88e6190x_ops, | |
4054 | }, | |
4055 | ||
4056 | [MV88E6191] = { | |
4057 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6191, | |
4058 | .family = MV88E6XXX_FAMILY_6390, | |
4059 | .name = "Marvell 88E6191", | |
4060 | .num_databases = 4096, | |
4061 | .num_ports = 11, /* 10 + Z80 */ | |
4062 | .port_base_addr = 0x0, | |
4063 | .global1_addr = 0x1b, | |
4064 | .age_time_coeff = 15000, | |
443d5a1b AL |
4065 | .g1_irqs = 9, |
4066 | .tag_protocol = DSA_TAG_PROTO_DSA, | |
1a3b39ec AL |
4067 | .flags = MV88E6XXX_FLAGS_FAMILY_6390, |
4068 | .ops = &mv88e6391_ops, | |
4069 | }, | |
4070 | ||
f81ec90f VD |
4071 | [MV88E6240] = { |
4072 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6240, | |
4073 | .family = MV88E6XXX_FAMILY_6352, | |
4074 | .name = "Marvell 88E6240", | |
4075 | .num_databases = 4096, | |
4076 | .num_ports = 7, | |
9dddd478 | 4077 | .port_base_addr = 0x10, |
a935c052 | 4078 | .global1_addr = 0x1b, |
acddbd21 | 4079 | .age_time_coeff = 15000, |
dc30c35b | 4080 | .g1_irqs = 9, |
443d5a1b | 4081 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 4082 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
b3469dd8 | 4083 | .ops = &mv88e6240_ops, |
f81ec90f VD |
4084 | }, |
4085 | ||
1a3b39ec AL |
4086 | [MV88E6290] = { |
4087 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6290, | |
4088 | .family = MV88E6XXX_FAMILY_6390, | |
4089 | .name = "Marvell 88E6290", | |
4090 | .num_databases = 4096, | |
4091 | .num_ports = 11, /* 10 + Z80 */ | |
4092 | .port_base_addr = 0x0, | |
4093 | .global1_addr = 0x1b, | |
4094 | .age_time_coeff = 15000, | |
4095 | .g1_irqs = 9, | |
443d5a1b | 4096 | .tag_protocol = DSA_TAG_PROTO_DSA, |
1a3b39ec AL |
4097 | .flags = MV88E6XXX_FLAGS_FAMILY_6390, |
4098 | .ops = &mv88e6290_ops, | |
4099 | }, | |
4100 | ||
f81ec90f VD |
4101 | [MV88E6320] = { |
4102 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6320, | |
4103 | .family = MV88E6XXX_FAMILY_6320, | |
4104 | .name = "Marvell 88E6320", | |
4105 | .num_databases = 4096, | |
4106 | .num_ports = 7, | |
9dddd478 | 4107 | .port_base_addr = 0x10, |
a935c052 | 4108 | .global1_addr = 0x1b, |
acddbd21 | 4109 | .age_time_coeff = 15000, |
dc30c35b | 4110 | .g1_irqs = 8, |
443d5a1b | 4111 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 4112 | .flags = MV88E6XXX_FLAGS_FAMILY_6320, |
b3469dd8 | 4113 | .ops = &mv88e6320_ops, |
f81ec90f VD |
4114 | }, |
4115 | ||
4116 | [MV88E6321] = { | |
4117 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6321, | |
4118 | .family = MV88E6XXX_FAMILY_6320, | |
4119 | .name = "Marvell 88E6321", | |
4120 | .num_databases = 4096, | |
4121 | .num_ports = 7, | |
9dddd478 | 4122 | .port_base_addr = 0x10, |
a935c052 | 4123 | .global1_addr = 0x1b, |
acddbd21 | 4124 | .age_time_coeff = 15000, |
dc30c35b | 4125 | .g1_irqs = 8, |
443d5a1b | 4126 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 4127 | .flags = MV88E6XXX_FLAGS_FAMILY_6320, |
b3469dd8 | 4128 | .ops = &mv88e6321_ops, |
f81ec90f VD |
4129 | }, |
4130 | ||
4131 | [MV88E6350] = { | |
4132 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6350, | |
4133 | .family = MV88E6XXX_FAMILY_6351, | |
4134 | .name = "Marvell 88E6350", | |
4135 | .num_databases = 4096, | |
4136 | .num_ports = 7, | |
9dddd478 | 4137 | .port_base_addr = 0x10, |
a935c052 | 4138 | .global1_addr = 0x1b, |
acddbd21 | 4139 | .age_time_coeff = 15000, |
dc30c35b | 4140 | .g1_irqs = 9, |
443d5a1b | 4141 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 4142 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
b3469dd8 | 4143 | .ops = &mv88e6350_ops, |
f81ec90f VD |
4144 | }, |
4145 | ||
4146 | [MV88E6351] = { | |
4147 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6351, | |
4148 | .family = MV88E6XXX_FAMILY_6351, | |
4149 | .name = "Marvell 88E6351", | |
4150 | .num_databases = 4096, | |
4151 | .num_ports = 7, | |
9dddd478 | 4152 | .port_base_addr = 0x10, |
a935c052 | 4153 | .global1_addr = 0x1b, |
acddbd21 | 4154 | .age_time_coeff = 15000, |
dc30c35b | 4155 | .g1_irqs = 9, |
443d5a1b | 4156 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 4157 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
b3469dd8 | 4158 | .ops = &mv88e6351_ops, |
f81ec90f VD |
4159 | }, |
4160 | ||
4161 | [MV88E6352] = { | |
4162 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6352, | |
4163 | .family = MV88E6XXX_FAMILY_6352, | |
4164 | .name = "Marvell 88E6352", | |
4165 | .num_databases = 4096, | |
4166 | .num_ports = 7, | |
9dddd478 | 4167 | .port_base_addr = 0x10, |
a935c052 | 4168 | .global1_addr = 0x1b, |
acddbd21 | 4169 | .age_time_coeff = 15000, |
dc30c35b | 4170 | .g1_irqs = 9, |
443d5a1b | 4171 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 4172 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
b3469dd8 | 4173 | .ops = &mv88e6352_ops, |
f81ec90f | 4174 | }, |
1a3b39ec AL |
4175 | [MV88E6390] = { |
4176 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6390, | |
4177 | .family = MV88E6XXX_FAMILY_6390, | |
4178 | .name = "Marvell 88E6390", | |
4179 | .num_databases = 4096, | |
4180 | .num_ports = 11, /* 10 + Z80 */ | |
4181 | .port_base_addr = 0x0, | |
4182 | .global1_addr = 0x1b, | |
4183 | .age_time_coeff = 15000, | |
4184 | .g1_irqs = 9, | |
443d5a1b | 4185 | .tag_protocol = DSA_TAG_PROTO_DSA, |
1a3b39ec AL |
4186 | .flags = MV88E6XXX_FLAGS_FAMILY_6390, |
4187 | .ops = &mv88e6390_ops, | |
4188 | }, | |
4189 | [MV88E6390X] = { | |
4190 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X, | |
4191 | .family = MV88E6XXX_FAMILY_6390, | |
4192 | .name = "Marvell 88E6390X", | |
4193 | .num_databases = 4096, | |
4194 | .num_ports = 11, /* 10 + Z80 */ | |
4195 | .port_base_addr = 0x0, | |
4196 | .global1_addr = 0x1b, | |
4197 | .age_time_coeff = 15000, | |
4198 | .g1_irqs = 9, | |
443d5a1b | 4199 | .tag_protocol = DSA_TAG_PROTO_DSA, |
1a3b39ec AL |
4200 | .flags = MV88E6XXX_FLAGS_FAMILY_6390, |
4201 | .ops = &mv88e6390x_ops, | |
4202 | }, | |
f81ec90f VD |
4203 | }; |
4204 | ||
5f7c0367 | 4205 | static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) |
b9b37713 | 4206 | { |
a439c061 | 4207 | int i; |
b9b37713 | 4208 | |
5f7c0367 VD |
4209 | for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) |
4210 | if (mv88e6xxx_table[i].prod_num == prod_num) | |
4211 | return &mv88e6xxx_table[i]; | |
b9b37713 | 4212 | |
b9b37713 VD |
4213 | return NULL; |
4214 | } | |
4215 | ||
fad09c73 | 4216 | static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) |
bc46a3d5 VD |
4217 | { |
4218 | const struct mv88e6xxx_info *info; | |
8f6345b2 VD |
4219 | unsigned int prod_num, rev; |
4220 | u16 id; | |
4221 | int err; | |
bc46a3d5 | 4222 | |
8f6345b2 VD |
4223 | mutex_lock(&chip->reg_lock); |
4224 | err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id); | |
4225 | mutex_unlock(&chip->reg_lock); | |
4226 | if (err) | |
4227 | return err; | |
bc46a3d5 VD |
4228 | |
4229 | prod_num = (id & 0xfff0) >> 4; | |
4230 | rev = id & 0x000f; | |
4231 | ||
4232 | info = mv88e6xxx_lookup_info(prod_num); | |
4233 | if (!info) | |
4234 | return -ENODEV; | |
4235 | ||
caac8545 | 4236 | /* Update the compatible info with the probed one */ |
fad09c73 | 4237 | chip->info = info; |
bc46a3d5 | 4238 | |
ca070c10 VD |
4239 | err = mv88e6xxx_g2_require(chip); |
4240 | if (err) | |
4241 | return err; | |
4242 | ||
fad09c73 VD |
4243 | dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", |
4244 | chip->info->prod_num, chip->info->name, rev); | |
bc46a3d5 VD |
4245 | |
4246 | return 0; | |
4247 | } | |
4248 | ||
fad09c73 | 4249 | static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) |
469d729f | 4250 | { |
fad09c73 | 4251 | struct mv88e6xxx_chip *chip; |
469d729f | 4252 | |
fad09c73 VD |
4253 | chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); |
4254 | if (!chip) | |
469d729f VD |
4255 | return NULL; |
4256 | ||
fad09c73 | 4257 | chip->dev = dev; |
469d729f | 4258 | |
fad09c73 | 4259 | mutex_init(&chip->reg_lock); |
469d729f | 4260 | |
fad09c73 | 4261 | return chip; |
469d729f VD |
4262 | } |
4263 | ||
e57e5e77 VD |
4264 | static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip) |
4265 | { | |
b3469dd8 | 4266 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) |
e57e5e77 | 4267 | mv88e6xxx_ppu_state_init(chip); |
e57e5e77 VD |
4268 | } |
4269 | ||
930188ce AL |
4270 | static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip) |
4271 | { | |
b3469dd8 | 4272 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) |
930188ce | 4273 | mv88e6xxx_ppu_state_destroy(chip); |
930188ce AL |
4274 | } |
4275 | ||
fad09c73 | 4276 | static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, |
4a70c4ab VD |
4277 | struct mii_bus *bus, int sw_addr) |
4278 | { | |
4279 | /* ADDR[0] pin is unavailable externally and considered zero */ | |
4280 | if (sw_addr & 0x1) | |
4281 | return -EINVAL; | |
4282 | ||
914b32f6 | 4283 | if (sw_addr == 0) |
fad09c73 | 4284 | chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; |
a0ffff24 | 4285 | else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP)) |
fad09c73 | 4286 | chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; |
914b32f6 VD |
4287 | else |
4288 | return -EINVAL; | |
4289 | ||
fad09c73 VD |
4290 | chip->bus = bus; |
4291 | chip->sw_addr = sw_addr; | |
4a70c4ab VD |
4292 | |
4293 | return 0; | |
4294 | } | |
4295 | ||
7b314362 AL |
4296 | static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds) |
4297 | { | |
04bed143 | 4298 | struct mv88e6xxx_chip *chip = ds->priv; |
2bbb33be | 4299 | |
443d5a1b | 4300 | return chip->info->tag_protocol; |
7b314362 AL |
4301 | } |
4302 | ||
fcdce7d0 AL |
4303 | static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, |
4304 | struct device *host_dev, int sw_addr, | |
4305 | void **priv) | |
a77d43f1 | 4306 | { |
fad09c73 | 4307 | struct mv88e6xxx_chip *chip; |
a439c061 | 4308 | struct mii_bus *bus; |
b516d453 | 4309 | int err; |
a77d43f1 | 4310 | |
a439c061 | 4311 | bus = dsa_host_dev_to_mii_bus(host_dev); |
c156913b AL |
4312 | if (!bus) |
4313 | return NULL; | |
4314 | ||
fad09c73 VD |
4315 | chip = mv88e6xxx_alloc_chip(dsa_dev); |
4316 | if (!chip) | |
469d729f VD |
4317 | return NULL; |
4318 | ||
caac8545 | 4319 | /* Legacy SMI probing will only support chips similar to 88E6085 */ |
fad09c73 | 4320 | chip->info = &mv88e6xxx_table[MV88E6085]; |
caac8545 | 4321 | |
fad09c73 | 4322 | err = mv88e6xxx_smi_init(chip, bus, sw_addr); |
4a70c4ab VD |
4323 | if (err) |
4324 | goto free; | |
4325 | ||
fad09c73 | 4326 | err = mv88e6xxx_detect(chip); |
bc46a3d5 | 4327 | if (err) |
469d729f | 4328 | goto free; |
a439c061 | 4329 | |
dc30c35b AL |
4330 | mutex_lock(&chip->reg_lock); |
4331 | err = mv88e6xxx_switch_reset(chip); | |
4332 | mutex_unlock(&chip->reg_lock); | |
4333 | if (err) | |
4334 | goto free; | |
4335 | ||
e57e5e77 VD |
4336 | mv88e6xxx_phy_init(chip); |
4337 | ||
fad09c73 | 4338 | err = mv88e6xxx_mdio_register(chip, NULL); |
b516d453 | 4339 | if (err) |
469d729f | 4340 | goto free; |
b516d453 | 4341 | |
fad09c73 | 4342 | *priv = chip; |
a439c061 | 4343 | |
fad09c73 | 4344 | return chip->info->name; |
469d729f | 4345 | free: |
fad09c73 | 4346 | devm_kfree(dsa_dev, chip); |
469d729f VD |
4347 | |
4348 | return NULL; | |
a77d43f1 AL |
4349 | } |
4350 | ||
7df8fbdd VD |
4351 | static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, |
4352 | const struct switchdev_obj_port_mdb *mdb, | |
4353 | struct switchdev_trans *trans) | |
4354 | { | |
4355 | /* We don't need any dynamic resource from the kernel (yet), | |
4356 | * so skip the prepare phase. | |
4357 | */ | |
4358 | ||
4359 | return 0; | |
4360 | } | |
4361 | ||
4362 | static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, | |
4363 | const struct switchdev_obj_port_mdb *mdb, | |
4364 | struct switchdev_trans *trans) | |
4365 | { | |
04bed143 | 4366 | struct mv88e6xxx_chip *chip = ds->priv; |
7df8fbdd VD |
4367 | |
4368 | mutex_lock(&chip->reg_lock); | |
4369 | if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, | |
4370 | GLOBAL_ATU_DATA_STATE_MC_STATIC)) | |
4371 | netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n"); | |
4372 | mutex_unlock(&chip->reg_lock); | |
4373 | } | |
4374 | ||
4375 | static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, | |
4376 | const struct switchdev_obj_port_mdb *mdb) | |
4377 | { | |
04bed143 | 4378 | struct mv88e6xxx_chip *chip = ds->priv; |
7df8fbdd VD |
4379 | int err; |
4380 | ||
4381 | mutex_lock(&chip->reg_lock); | |
4382 | err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, | |
4383 | GLOBAL_ATU_DATA_STATE_UNUSED); | |
4384 | mutex_unlock(&chip->reg_lock); | |
4385 | ||
4386 | return err; | |
4387 | } | |
4388 | ||
4389 | static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port, | |
4390 | struct switchdev_obj_port_mdb *mdb, | |
4391 | int (*cb)(struct switchdev_obj *obj)) | |
4392 | { | |
04bed143 | 4393 | struct mv88e6xxx_chip *chip = ds->priv; |
7df8fbdd VD |
4394 | int err; |
4395 | ||
4396 | mutex_lock(&chip->reg_lock); | |
4397 | err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb); | |
4398 | mutex_unlock(&chip->reg_lock); | |
4399 | ||
4400 | return err; | |
4401 | } | |
4402 | ||
9d490b4e | 4403 | static struct dsa_switch_ops mv88e6xxx_switch_ops = { |
fcdce7d0 | 4404 | .probe = mv88e6xxx_drv_probe, |
7b314362 | 4405 | .get_tag_protocol = mv88e6xxx_get_tag_protocol, |
f81ec90f VD |
4406 | .setup = mv88e6xxx_setup, |
4407 | .set_addr = mv88e6xxx_set_addr, | |
f81ec90f VD |
4408 | .adjust_link = mv88e6xxx_adjust_link, |
4409 | .get_strings = mv88e6xxx_get_strings, | |
4410 | .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, | |
4411 | .get_sset_count = mv88e6xxx_get_sset_count, | |
4412 | .set_eee = mv88e6xxx_set_eee, | |
4413 | .get_eee = mv88e6xxx_get_eee, | |
4414 | #ifdef CONFIG_NET_DSA_HWMON | |
4415 | .get_temp = mv88e6xxx_get_temp, | |
4416 | .get_temp_limit = mv88e6xxx_get_temp_limit, | |
4417 | .set_temp_limit = mv88e6xxx_set_temp_limit, | |
4418 | .get_temp_alarm = mv88e6xxx_get_temp_alarm, | |
4419 | #endif | |
f8cd8753 | 4420 | .get_eeprom_len = mv88e6xxx_get_eeprom_len, |
f81ec90f VD |
4421 | .get_eeprom = mv88e6xxx_get_eeprom, |
4422 | .set_eeprom = mv88e6xxx_set_eeprom, | |
4423 | .get_regs_len = mv88e6xxx_get_regs_len, | |
4424 | .get_regs = mv88e6xxx_get_regs, | |
2cfcd964 | 4425 | .set_ageing_time = mv88e6xxx_set_ageing_time, |
f81ec90f VD |
4426 | .port_bridge_join = mv88e6xxx_port_bridge_join, |
4427 | .port_bridge_leave = mv88e6xxx_port_bridge_leave, | |
4428 | .port_stp_state_set = mv88e6xxx_port_stp_state_set, | |
749efcb8 | 4429 | .port_fast_age = mv88e6xxx_port_fast_age, |
f81ec90f VD |
4430 | .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, |
4431 | .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, | |
4432 | .port_vlan_add = mv88e6xxx_port_vlan_add, | |
4433 | .port_vlan_del = mv88e6xxx_port_vlan_del, | |
4434 | .port_vlan_dump = mv88e6xxx_port_vlan_dump, | |
4435 | .port_fdb_prepare = mv88e6xxx_port_fdb_prepare, | |
4436 | .port_fdb_add = mv88e6xxx_port_fdb_add, | |
4437 | .port_fdb_del = mv88e6xxx_port_fdb_del, | |
4438 | .port_fdb_dump = mv88e6xxx_port_fdb_dump, | |
7df8fbdd VD |
4439 | .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, |
4440 | .port_mdb_add = mv88e6xxx_port_mdb_add, | |
4441 | .port_mdb_del = mv88e6xxx_port_mdb_del, | |
4442 | .port_mdb_dump = mv88e6xxx_port_mdb_dump, | |
f81ec90f VD |
4443 | }; |
4444 | ||
fad09c73 | 4445 | static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip, |
b7e66a5f VD |
4446 | struct device_node *np) |
4447 | { | |
fad09c73 | 4448 | struct device *dev = chip->dev; |
b7e66a5f VD |
4449 | struct dsa_switch *ds; |
4450 | ||
4451 | ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); | |
4452 | if (!ds) | |
4453 | return -ENOMEM; | |
4454 | ||
4455 | ds->dev = dev; | |
fad09c73 | 4456 | ds->priv = chip; |
9d490b4e | 4457 | ds->ops = &mv88e6xxx_switch_ops; |
b7e66a5f VD |
4458 | |
4459 | dev_set_drvdata(dev, ds); | |
4460 | ||
4461 | return dsa_register_switch(ds, np); | |
4462 | } | |
4463 | ||
fad09c73 | 4464 | static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) |
b7e66a5f | 4465 | { |
fad09c73 | 4466 | dsa_unregister_switch(chip->ds); |
b7e66a5f VD |
4467 | } |
4468 | ||
57d32310 | 4469 | static int mv88e6xxx_probe(struct mdio_device *mdiodev) |
98e67308 | 4470 | { |
14c7b3c3 | 4471 | struct device *dev = &mdiodev->dev; |
f8cd8753 | 4472 | struct device_node *np = dev->of_node; |
caac8545 | 4473 | const struct mv88e6xxx_info *compat_info; |
fad09c73 | 4474 | struct mv88e6xxx_chip *chip; |
f8cd8753 | 4475 | u32 eeprom_len; |
52638f71 | 4476 | int err; |
14c7b3c3 | 4477 | |
caac8545 VD |
4478 | compat_info = of_device_get_match_data(dev); |
4479 | if (!compat_info) | |
4480 | return -EINVAL; | |
4481 | ||
fad09c73 VD |
4482 | chip = mv88e6xxx_alloc_chip(dev); |
4483 | if (!chip) | |
14c7b3c3 AL |
4484 | return -ENOMEM; |
4485 | ||
fad09c73 | 4486 | chip->info = compat_info; |
caac8545 | 4487 | |
56995cbc AL |
4488 | err = mv88e6xxx_verify_madatory_ops(chip, chip->info->ops); |
4489 | if (err) | |
4490 | return err; | |
4491 | ||
fad09c73 | 4492 | err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); |
4a70c4ab VD |
4493 | if (err) |
4494 | return err; | |
14c7b3c3 | 4495 | |
b4308f04 AL |
4496 | chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); |
4497 | if (IS_ERR(chip->reset)) | |
4498 | return PTR_ERR(chip->reset); | |
4499 | ||
fad09c73 | 4500 | err = mv88e6xxx_detect(chip); |
bc46a3d5 VD |
4501 | if (err) |
4502 | return err; | |
14c7b3c3 | 4503 | |
e57e5e77 VD |
4504 | mv88e6xxx_phy_init(chip); |
4505 | ||
ee4dc2e7 | 4506 | if (chip->info->ops->get_eeprom && |
f8cd8753 | 4507 | !of_property_read_u32(np, "eeprom-length", &eeprom_len)) |
fad09c73 | 4508 | chip->eeprom_len = eeprom_len; |
f8cd8753 | 4509 | |
dc30c35b AL |
4510 | mutex_lock(&chip->reg_lock); |
4511 | err = mv88e6xxx_switch_reset(chip); | |
4512 | mutex_unlock(&chip->reg_lock); | |
4513 | if (err) | |
4514 | goto out; | |
4515 | ||
4516 | chip->irq = of_irq_get(np, 0); | |
4517 | if (chip->irq == -EPROBE_DEFER) { | |
4518 | err = chip->irq; | |
4519 | goto out; | |
4520 | } | |
4521 | ||
4522 | if (chip->irq > 0) { | |
4523 | /* Has to be performed before the MDIO bus is created, | |
4524 | * because the PHYs will link there interrupts to these | |
4525 | * interrupt controllers | |
4526 | */ | |
4527 | mutex_lock(&chip->reg_lock); | |
4528 | err = mv88e6xxx_g1_irq_setup(chip); | |
4529 | mutex_unlock(&chip->reg_lock); | |
4530 | ||
4531 | if (err) | |
4532 | goto out; | |
4533 | ||
4534 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) { | |
4535 | err = mv88e6xxx_g2_irq_setup(chip); | |
4536 | if (err) | |
4537 | goto out_g1_irq; | |
4538 | } | |
4539 | } | |
4540 | ||
fad09c73 | 4541 | err = mv88e6xxx_mdio_register(chip, np); |
b516d453 | 4542 | if (err) |
dc30c35b | 4543 | goto out_g2_irq; |
b516d453 | 4544 | |
fad09c73 | 4545 | err = mv88e6xxx_register_switch(chip, np); |
dc30c35b AL |
4546 | if (err) |
4547 | goto out_mdio; | |
83c0afae | 4548 | |
98e67308 | 4549 | return 0; |
dc30c35b AL |
4550 | |
4551 | out_mdio: | |
4552 | mv88e6xxx_mdio_unregister(chip); | |
4553 | out_g2_irq: | |
46712644 | 4554 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0) |
dc30c35b AL |
4555 | mv88e6xxx_g2_irq_free(chip); |
4556 | out_g1_irq: | |
61f7c3f8 AL |
4557 | if (chip->irq > 0) { |
4558 | mutex_lock(&chip->reg_lock); | |
46712644 | 4559 | mv88e6xxx_g1_irq_free(chip); |
61f7c3f8 AL |
4560 | mutex_unlock(&chip->reg_lock); |
4561 | } | |
dc30c35b AL |
4562 | out: |
4563 | return err; | |
98e67308 | 4564 | } |
14c7b3c3 AL |
4565 | |
4566 | static void mv88e6xxx_remove(struct mdio_device *mdiodev) | |
4567 | { | |
4568 | struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); | |
04bed143 | 4569 | struct mv88e6xxx_chip *chip = ds->priv; |
14c7b3c3 | 4570 | |
930188ce | 4571 | mv88e6xxx_phy_destroy(chip); |
fad09c73 VD |
4572 | mv88e6xxx_unregister_switch(chip); |
4573 | mv88e6xxx_mdio_unregister(chip); | |
dc30c35b | 4574 | |
46712644 AL |
4575 | if (chip->irq > 0) { |
4576 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) | |
4577 | mv88e6xxx_g2_irq_free(chip); | |
4578 | mv88e6xxx_g1_irq_free(chip); | |
4579 | } | |
14c7b3c3 AL |
4580 | } |
4581 | ||
4582 | static const struct of_device_id mv88e6xxx_of_match[] = { | |
caac8545 VD |
4583 | { |
4584 | .compatible = "marvell,mv88e6085", | |
4585 | .data = &mv88e6xxx_table[MV88E6085], | |
4586 | }, | |
1a3b39ec AL |
4587 | { |
4588 | .compatible = "marvell,mv88e6190", | |
4589 | .data = &mv88e6xxx_table[MV88E6190], | |
4590 | }, | |
14c7b3c3 AL |
4591 | { /* sentinel */ }, |
4592 | }; | |
4593 | ||
4594 | MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); | |
4595 | ||
4596 | static struct mdio_driver mv88e6xxx_driver = { | |
4597 | .probe = mv88e6xxx_probe, | |
4598 | .remove = mv88e6xxx_remove, | |
4599 | .mdiodrv.driver = { | |
4600 | .name = "mv88e6085", | |
4601 | .of_match_table = mv88e6xxx_of_match, | |
4602 | }, | |
4603 | }; | |
4604 | ||
4605 | static int __init mv88e6xxx_init(void) | |
4606 | { | |
9d490b4e | 4607 | register_switch_driver(&mv88e6xxx_switch_ops); |
14c7b3c3 AL |
4608 | return mdio_driver_register(&mv88e6xxx_driver); |
4609 | } | |
98e67308 BH |
4610 | module_init(mv88e6xxx_init); |
4611 | ||
4612 | static void __exit mv88e6xxx_cleanup(void) | |
4613 | { | |
14c7b3c3 | 4614 | mdio_driver_unregister(&mv88e6xxx_driver); |
9d490b4e | 4615 | unregister_switch_driver(&mv88e6xxx_switch_ops); |
98e67308 BH |
4616 | } |
4617 | module_exit(mv88e6xxx_cleanup); | |
3d825ede BH |
4618 | |
4619 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); | |
4620 | MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); | |
4621 | MODULE_LICENSE("GPL"); |