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Commit | Line | Data |
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91da11f8 | 1 | /* |
0d3cd4b6 VD |
2 | * Marvell 88e6xxx Ethernet switch single-chip support |
3 | * | |
91da11f8 LB |
4 | * Copyright (c) 2008 Marvell Semiconductor |
5 | * | |
14c7b3c3 AL |
6 | * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> |
7 | * | |
4333d619 VD |
8 | * Copyright (c) 2016-2017 Savoir-faire Linux Inc. |
9 | * Vivien Didelot <vivien.didelot@savoirfairelinux.com> | |
10 | * | |
91da11f8 LB |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
19b2f97e | 17 | #include <linux/delay.h> |
defb05b9 | 18 | #include <linux/etherdevice.h> |
dea87024 | 19 | #include <linux/ethtool.h> |
facd95b2 | 20 | #include <linux/if_bridge.h> |
dc30c35b AL |
21 | #include <linux/interrupt.h> |
22 | #include <linux/irq.h> | |
23 | #include <linux/irqdomain.h> | |
19b2f97e | 24 | #include <linux/jiffies.h> |
91da11f8 | 25 | #include <linux/list.h> |
14c7b3c3 | 26 | #include <linux/mdio.h> |
2bbba277 | 27 | #include <linux/module.h> |
caac8545 | 28 | #include <linux/of_device.h> |
dc30c35b | 29 | #include <linux/of_irq.h> |
b516d453 | 30 | #include <linux/of_mdio.h> |
91da11f8 | 31 | #include <linux/netdevice.h> |
c8c1b39a | 32 | #include <linux/gpio/consumer.h> |
91da11f8 | 33 | #include <linux/phy.h> |
c8f0b869 | 34 | #include <net/dsa.h> |
ec561276 | 35 | |
4d5f2ba7 | 36 | #include "chip.h" |
a935c052 | 37 | #include "global1.h" |
ec561276 | 38 | #include "global2.h" |
10fa5bfc | 39 | #include "phy.h" |
18abed21 | 40 | #include "port.h" |
6d91782f | 41 | #include "serdes.h" |
91da11f8 | 42 | |
fad09c73 | 43 | static void assert_reg_lock(struct mv88e6xxx_chip *chip) |
3996a4ff | 44 | { |
fad09c73 VD |
45 | if (unlikely(!mutex_is_locked(&chip->reg_lock))) { |
46 | dev_err(chip->dev, "Switch registers lock not held!\n"); | |
3996a4ff VD |
47 | dump_stack(); |
48 | } | |
49 | } | |
50 | ||
914b32f6 VD |
51 | /* The switch ADDR[4:1] configuration pins define the chip SMI device address |
52 | * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). | |
53 | * | |
54 | * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it | |
55 | * is the only device connected to the SMI master. In this mode it responds to | |
56 | * all 32 possible SMI addresses, and thus maps directly the internal devices. | |
57 | * | |
58 | * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing | |
59 | * multiple devices to share the SMI interface. In this mode it responds to only | |
60 | * 2 registers, used to indirectly access the internal SMI devices. | |
91da11f8 | 61 | */ |
914b32f6 | 62 | |
fad09c73 | 63 | static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
64 | int addr, int reg, u16 *val) |
65 | { | |
fad09c73 | 66 | if (!chip->smi_ops) |
914b32f6 VD |
67 | return -EOPNOTSUPP; |
68 | ||
fad09c73 | 69 | return chip->smi_ops->read(chip, addr, reg, val); |
914b32f6 VD |
70 | } |
71 | ||
fad09c73 | 72 | static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
73 | int addr, int reg, u16 val) |
74 | { | |
fad09c73 | 75 | if (!chip->smi_ops) |
914b32f6 VD |
76 | return -EOPNOTSUPP; |
77 | ||
fad09c73 | 78 | return chip->smi_ops->write(chip, addr, reg, val); |
914b32f6 VD |
79 | } |
80 | ||
fad09c73 | 81 | static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
82 | int addr, int reg, u16 *val) |
83 | { | |
84 | int ret; | |
85 | ||
fad09c73 | 86 | ret = mdiobus_read_nested(chip->bus, addr, reg); |
914b32f6 VD |
87 | if (ret < 0) |
88 | return ret; | |
89 | ||
90 | *val = ret & 0xffff; | |
91 | ||
92 | return 0; | |
93 | } | |
94 | ||
fad09c73 | 95 | static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
96 | int addr, int reg, u16 val) |
97 | { | |
98 | int ret; | |
99 | ||
fad09c73 | 100 | ret = mdiobus_write_nested(chip->bus, addr, reg, val); |
914b32f6 VD |
101 | if (ret < 0) |
102 | return ret; | |
103 | ||
104 | return 0; | |
105 | } | |
106 | ||
c08026ab | 107 | static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { |
914b32f6 VD |
108 | .read = mv88e6xxx_smi_single_chip_read, |
109 | .write = mv88e6xxx_smi_single_chip_write, | |
110 | }; | |
111 | ||
fad09c73 | 112 | static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) |
91da11f8 LB |
113 | { |
114 | int ret; | |
115 | int i; | |
116 | ||
117 | for (i = 0; i < 16; i++) { | |
fad09c73 | 118 | ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); |
91da11f8 LB |
119 | if (ret < 0) |
120 | return ret; | |
121 | ||
cca8b133 | 122 | if ((ret & SMI_CMD_BUSY) == 0) |
91da11f8 LB |
123 | return 0; |
124 | } | |
125 | ||
126 | return -ETIMEDOUT; | |
127 | } | |
128 | ||
fad09c73 | 129 | static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, |
914b32f6 | 130 | int addr, int reg, u16 *val) |
91da11f8 LB |
131 | { |
132 | int ret; | |
133 | ||
3675c8d7 | 134 | /* Wait for the bus to become free. */ |
fad09c73 | 135 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
136 | if (ret < 0) |
137 | return ret; | |
138 | ||
3675c8d7 | 139 | /* Transmit the read command. */ |
fad09c73 | 140 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, |
6e899e6c | 141 | SMI_CMD_OP_22_READ | (addr << 5) | reg); |
91da11f8 LB |
142 | if (ret < 0) |
143 | return ret; | |
144 | ||
3675c8d7 | 145 | /* Wait for the read command to complete. */ |
fad09c73 | 146 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
147 | if (ret < 0) |
148 | return ret; | |
149 | ||
3675c8d7 | 150 | /* Read the data. */ |
fad09c73 | 151 | ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); |
bb92ea5e VD |
152 | if (ret < 0) |
153 | return ret; | |
154 | ||
914b32f6 | 155 | *val = ret & 0xffff; |
91da11f8 | 156 | |
914b32f6 | 157 | return 0; |
8d6d09e7 GR |
158 | } |
159 | ||
fad09c73 | 160 | static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, |
914b32f6 | 161 | int addr, int reg, u16 val) |
91da11f8 LB |
162 | { |
163 | int ret; | |
164 | ||
3675c8d7 | 165 | /* Wait for the bus to become free. */ |
fad09c73 | 166 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
167 | if (ret < 0) |
168 | return ret; | |
169 | ||
3675c8d7 | 170 | /* Transmit the data to write. */ |
fad09c73 | 171 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); |
91da11f8 LB |
172 | if (ret < 0) |
173 | return ret; | |
174 | ||
3675c8d7 | 175 | /* Transmit the write command. */ |
fad09c73 | 176 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, |
6e899e6c | 177 | SMI_CMD_OP_22_WRITE | (addr << 5) | reg); |
91da11f8 LB |
178 | if (ret < 0) |
179 | return ret; | |
180 | ||
3675c8d7 | 181 | /* Wait for the write command to complete. */ |
fad09c73 | 182 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
183 | if (ret < 0) |
184 | return ret; | |
185 | ||
186 | return 0; | |
187 | } | |
188 | ||
c08026ab | 189 | static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { |
914b32f6 VD |
190 | .read = mv88e6xxx_smi_multi_chip_read, |
191 | .write = mv88e6xxx_smi_multi_chip_write, | |
192 | }; | |
193 | ||
ec561276 | 194 | int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) |
914b32f6 VD |
195 | { |
196 | int err; | |
197 | ||
fad09c73 | 198 | assert_reg_lock(chip); |
914b32f6 | 199 | |
fad09c73 | 200 | err = mv88e6xxx_smi_read(chip, addr, reg, val); |
914b32f6 VD |
201 | if (err) |
202 | return err; | |
203 | ||
fad09c73 | 204 | dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
914b32f6 VD |
205 | addr, reg, *val); |
206 | ||
207 | return 0; | |
208 | } | |
209 | ||
ec561276 | 210 | int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) |
91da11f8 | 211 | { |
914b32f6 VD |
212 | int err; |
213 | ||
fad09c73 | 214 | assert_reg_lock(chip); |
91da11f8 | 215 | |
fad09c73 | 216 | err = mv88e6xxx_smi_write(chip, addr, reg, val); |
914b32f6 VD |
217 | if (err) |
218 | return err; | |
219 | ||
fad09c73 | 220 | dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
bb92ea5e VD |
221 | addr, reg, val); |
222 | ||
914b32f6 VD |
223 | return 0; |
224 | } | |
225 | ||
10fa5bfc | 226 | struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) |
a3c53be5 AL |
227 | { |
228 | struct mv88e6xxx_mdio_bus *mdio_bus; | |
229 | ||
230 | mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, | |
231 | list); | |
232 | if (!mdio_bus) | |
233 | return NULL; | |
234 | ||
235 | return mdio_bus->bus; | |
236 | } | |
237 | ||
dc30c35b AL |
238 | static void mv88e6xxx_g1_irq_mask(struct irq_data *d) |
239 | { | |
240 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
241 | unsigned int n = d->hwirq; | |
242 | ||
243 | chip->g1_irq.masked |= (1 << n); | |
244 | } | |
245 | ||
246 | static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) | |
247 | { | |
248 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
249 | unsigned int n = d->hwirq; | |
250 | ||
251 | chip->g1_irq.masked &= ~(1 << n); | |
252 | } | |
253 | ||
254 | static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) | |
255 | { | |
256 | struct mv88e6xxx_chip *chip = dev_id; | |
257 | unsigned int nhandled = 0; | |
258 | unsigned int sub_irq; | |
259 | unsigned int n; | |
260 | u16 reg; | |
261 | int err; | |
262 | ||
263 | mutex_lock(&chip->reg_lock); | |
82466921 | 264 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); |
dc30c35b AL |
265 | mutex_unlock(&chip->reg_lock); |
266 | ||
267 | if (err) | |
268 | goto out; | |
269 | ||
270 | for (n = 0; n < chip->g1_irq.nirqs; ++n) { | |
271 | if (reg & (1 << n)) { | |
272 | sub_irq = irq_find_mapping(chip->g1_irq.domain, n); | |
273 | handle_nested_irq(sub_irq); | |
274 | ++nhandled; | |
275 | } | |
276 | } | |
277 | out: | |
278 | return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); | |
279 | } | |
280 | ||
281 | static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) | |
282 | { | |
283 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
284 | ||
285 | mutex_lock(&chip->reg_lock); | |
286 | } | |
287 | ||
288 | static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) | |
289 | { | |
290 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
291 | u16 mask = GENMASK(chip->g1_irq.nirqs, 0); | |
292 | u16 reg; | |
293 | int err; | |
294 | ||
295 | err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®); | |
296 | if (err) | |
297 | goto out; | |
298 | ||
299 | reg &= ~mask; | |
300 | reg |= (~chip->g1_irq.masked & mask); | |
301 | ||
302 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg); | |
303 | if (err) | |
304 | goto out; | |
305 | ||
306 | out: | |
307 | mutex_unlock(&chip->reg_lock); | |
308 | } | |
309 | ||
310 | static struct irq_chip mv88e6xxx_g1_irq_chip = { | |
311 | .name = "mv88e6xxx-g1", | |
312 | .irq_mask = mv88e6xxx_g1_irq_mask, | |
313 | .irq_unmask = mv88e6xxx_g1_irq_unmask, | |
314 | .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, | |
315 | .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, | |
316 | }; | |
317 | ||
318 | static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, | |
319 | unsigned int irq, | |
320 | irq_hw_number_t hwirq) | |
321 | { | |
322 | struct mv88e6xxx_chip *chip = d->host_data; | |
323 | ||
324 | irq_set_chip_data(irq, d->host_data); | |
325 | irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); | |
326 | irq_set_noprobe(irq); | |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
331 | static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { | |
332 | .map = mv88e6xxx_g1_irq_domain_map, | |
333 | .xlate = irq_domain_xlate_twocell, | |
334 | }; | |
335 | ||
336 | static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) | |
337 | { | |
338 | int irq, virq; | |
3460a577 AL |
339 | u16 mask; |
340 | ||
341 | mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask); | |
342 | mask |= GENMASK(chip->g1_irq.nirqs, 0); | |
343 | mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); | |
344 | ||
345 | free_irq(chip->irq, chip); | |
dc30c35b | 346 | |
5edef2f2 | 347 | for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { |
a3db3d3a | 348 | virq = irq_find_mapping(chip->g1_irq.domain, irq); |
dc30c35b AL |
349 | irq_dispose_mapping(virq); |
350 | } | |
351 | ||
a3db3d3a | 352 | irq_domain_remove(chip->g1_irq.domain); |
dc30c35b AL |
353 | } |
354 | ||
355 | static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) | |
356 | { | |
3dd0ef05 AL |
357 | int err, irq, virq; |
358 | u16 reg, mask; | |
dc30c35b AL |
359 | |
360 | chip->g1_irq.nirqs = chip->info->g1_irqs; | |
361 | chip->g1_irq.domain = irq_domain_add_simple( | |
362 | NULL, chip->g1_irq.nirqs, 0, | |
363 | &mv88e6xxx_g1_irq_domain_ops, chip); | |
364 | if (!chip->g1_irq.domain) | |
365 | return -ENOMEM; | |
366 | ||
367 | for (irq = 0; irq < chip->g1_irq.nirqs; irq++) | |
368 | irq_create_mapping(chip->g1_irq.domain, irq); | |
369 | ||
370 | chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; | |
371 | chip->g1_irq.masked = ~0; | |
372 | ||
3dd0ef05 | 373 | err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask); |
dc30c35b | 374 | if (err) |
3dd0ef05 | 375 | goto out_mapping; |
dc30c35b | 376 | |
3dd0ef05 | 377 | mask &= ~GENMASK(chip->g1_irq.nirqs, 0); |
dc30c35b | 378 | |
3dd0ef05 | 379 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); |
dc30c35b | 380 | if (err) |
3dd0ef05 | 381 | goto out_disable; |
dc30c35b AL |
382 | |
383 | /* Reading the interrupt status clears (most of) them */ | |
82466921 | 384 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); |
dc30c35b | 385 | if (err) |
3dd0ef05 | 386 | goto out_disable; |
dc30c35b AL |
387 | |
388 | err = request_threaded_irq(chip->irq, NULL, | |
389 | mv88e6xxx_g1_irq_thread_fn, | |
390 | IRQF_ONESHOT | IRQF_TRIGGER_FALLING, | |
391 | dev_name(chip->dev), chip); | |
392 | if (err) | |
3dd0ef05 | 393 | goto out_disable; |
dc30c35b AL |
394 | |
395 | return 0; | |
396 | ||
3dd0ef05 AL |
397 | out_disable: |
398 | mask |= GENMASK(chip->g1_irq.nirqs, 0); | |
399 | mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); | |
400 | ||
401 | out_mapping: | |
402 | for (irq = 0; irq < 16; irq++) { | |
403 | virq = irq_find_mapping(chip->g1_irq.domain, irq); | |
404 | irq_dispose_mapping(virq); | |
405 | } | |
406 | ||
407 | irq_domain_remove(chip->g1_irq.domain); | |
dc30c35b AL |
408 | |
409 | return err; | |
410 | } | |
411 | ||
ec561276 | 412 | int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) |
2d79af6e | 413 | { |
6441e669 | 414 | int i; |
2d79af6e | 415 | |
6441e669 | 416 | for (i = 0; i < 16; i++) { |
2d79af6e VD |
417 | u16 val; |
418 | int err; | |
419 | ||
420 | err = mv88e6xxx_read(chip, addr, reg, &val); | |
421 | if (err) | |
422 | return err; | |
423 | ||
424 | if (!(val & mask)) | |
425 | return 0; | |
426 | ||
427 | usleep_range(1000, 2000); | |
428 | } | |
429 | ||
30853553 | 430 | dev_err(chip->dev, "Timeout while waiting for switch\n"); |
2d79af6e VD |
431 | return -ETIMEDOUT; |
432 | } | |
433 | ||
f22ab641 | 434 | /* Indirect write to single pointer-data register with an Update bit */ |
ec561276 | 435 | int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) |
f22ab641 VD |
436 | { |
437 | u16 val; | |
0f02b4f7 | 438 | int err; |
f22ab641 VD |
439 | |
440 | /* Wait until the previous operation is completed */ | |
0f02b4f7 AL |
441 | err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); |
442 | if (err) | |
443 | return err; | |
f22ab641 VD |
444 | |
445 | /* Set the Update bit to trigger a write operation */ | |
446 | val = BIT(15) | update; | |
447 | ||
448 | return mv88e6xxx_write(chip, addr, reg, val); | |
449 | } | |
450 | ||
d78343d2 VD |
451 | static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, |
452 | int link, int speed, int duplex, | |
453 | phy_interface_t mode) | |
454 | { | |
455 | int err; | |
456 | ||
457 | if (!chip->info->ops->port_set_link) | |
458 | return 0; | |
459 | ||
460 | /* Port's MAC control must not be changed unless the link is down */ | |
461 | err = chip->info->ops->port_set_link(chip, port, 0); | |
462 | if (err) | |
463 | return err; | |
464 | ||
465 | if (chip->info->ops->port_set_speed) { | |
466 | err = chip->info->ops->port_set_speed(chip, port, speed); | |
467 | if (err && err != -EOPNOTSUPP) | |
468 | goto restore_link; | |
469 | } | |
470 | ||
471 | if (chip->info->ops->port_set_duplex) { | |
472 | err = chip->info->ops->port_set_duplex(chip, port, duplex); | |
473 | if (err && err != -EOPNOTSUPP) | |
474 | goto restore_link; | |
475 | } | |
476 | ||
477 | if (chip->info->ops->port_set_rgmii_delay) { | |
478 | err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); | |
479 | if (err && err != -EOPNOTSUPP) | |
480 | goto restore_link; | |
481 | } | |
482 | ||
f39908d3 AL |
483 | if (chip->info->ops->port_set_cmode) { |
484 | err = chip->info->ops->port_set_cmode(chip, port, mode); | |
485 | if (err && err != -EOPNOTSUPP) | |
486 | goto restore_link; | |
487 | } | |
488 | ||
d78343d2 VD |
489 | err = 0; |
490 | restore_link: | |
491 | if (chip->info->ops->port_set_link(chip, port, link)) | |
774439e5 | 492 | dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); |
d78343d2 VD |
493 | |
494 | return err; | |
495 | } | |
496 | ||
dea87024 AL |
497 | /* We expect the switch to perform auto negotiation if there is a real |
498 | * phy. However, in the case of a fixed link phy, we force the port | |
499 | * settings from the fixed link settings. | |
500 | */ | |
f81ec90f VD |
501 | static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, |
502 | struct phy_device *phydev) | |
dea87024 | 503 | { |
04bed143 | 504 | struct mv88e6xxx_chip *chip = ds->priv; |
0e7b9925 | 505 | int err; |
dea87024 AL |
506 | |
507 | if (!phy_is_pseudo_fixed_link(phydev)) | |
508 | return; | |
509 | ||
fad09c73 | 510 | mutex_lock(&chip->reg_lock); |
d78343d2 VD |
511 | err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, |
512 | phydev->duplex, phydev->interface); | |
fad09c73 | 513 | mutex_unlock(&chip->reg_lock); |
d78343d2 VD |
514 | |
515 | if (err && err != -EOPNOTSUPP) | |
774439e5 | 516 | dev_err(ds->dev, "p%d: failed to configure MAC\n", port); |
dea87024 AL |
517 | } |
518 | ||
a605a0fe | 519 | static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) |
91da11f8 | 520 | { |
a605a0fe AL |
521 | if (!chip->info->ops->stats_snapshot) |
522 | return -EOPNOTSUPP; | |
91da11f8 | 523 | |
a605a0fe | 524 | return chip->info->ops->stats_snapshot(chip, port); |
91da11f8 LB |
525 | } |
526 | ||
e413e7e1 | 527 | static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { |
dfafe449 AL |
528 | { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, |
529 | { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, | |
530 | { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, | |
531 | { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, | |
532 | { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, | |
533 | { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, | |
534 | { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, | |
535 | { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, | |
536 | { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, | |
537 | { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, | |
538 | { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, | |
539 | { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, | |
540 | { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, | |
541 | { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, | |
542 | { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, | |
543 | { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, | |
544 | { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, | |
545 | { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, | |
546 | { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, | |
547 | { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, | |
548 | { "single", 4, 0x14, STATS_TYPE_BANK0, }, | |
549 | { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, | |
550 | { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, | |
551 | { "late", 4, 0x1f, STATS_TYPE_BANK0, }, | |
552 | { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, | |
553 | { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, | |
554 | { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, | |
555 | { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, | |
556 | { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, | |
557 | { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, | |
558 | { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, | |
559 | { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, | |
560 | { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, | |
561 | { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, | |
562 | { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, | |
563 | { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, | |
564 | { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, | |
565 | { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, | |
566 | { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, | |
567 | { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, | |
568 | { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, | |
569 | { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, | |
570 | { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, | |
571 | { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, | |
572 | { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, | |
573 | { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, | |
574 | { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, | |
575 | { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, | |
576 | { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, | |
577 | { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, | |
578 | { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, | |
579 | { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, | |
580 | { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, | |
581 | { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, | |
582 | { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, | |
583 | { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, | |
584 | { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, | |
585 | { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, | |
586 | { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, | |
e413e7e1 AL |
587 | }; |
588 | ||
fad09c73 | 589 | static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, |
f5e2ed02 | 590 | struct mv88e6xxx_hw_stat *s, |
e0d8b615 AL |
591 | int port, u16 bank1_select, |
592 | u16 histogram) | |
80c4627b | 593 | { |
80c4627b AL |
594 | u32 low; |
595 | u32 high = 0; | |
dfafe449 | 596 | u16 reg = 0; |
0e7b9925 | 597 | int err; |
80c4627b AL |
598 | u64 value; |
599 | ||
f5e2ed02 | 600 | switch (s->type) { |
dfafe449 | 601 | case STATS_TYPE_PORT: |
0e7b9925 AL |
602 | err = mv88e6xxx_port_read(chip, port, s->reg, ®); |
603 | if (err) | |
80c4627b AL |
604 | return UINT64_MAX; |
605 | ||
0e7b9925 | 606 | low = reg; |
80c4627b | 607 | if (s->sizeof_stat == 4) { |
0e7b9925 AL |
608 | err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); |
609 | if (err) | |
80c4627b | 610 | return UINT64_MAX; |
0e7b9925 | 611 | high = reg; |
80c4627b | 612 | } |
f5e2ed02 | 613 | break; |
dfafe449 | 614 | case STATS_TYPE_BANK1: |
e0d8b615 | 615 | reg = bank1_select; |
dfafe449 AL |
616 | /* fall through */ |
617 | case STATS_TYPE_BANK0: | |
e0d8b615 | 618 | reg |= s->reg | histogram; |
7f9ef3af | 619 | mv88e6xxx_g1_stats_read(chip, reg, &low); |
80c4627b | 620 | if (s->sizeof_stat == 8) |
7f9ef3af | 621 | mv88e6xxx_g1_stats_read(chip, reg + 1, &high); |
9fc3e4dc GS |
622 | break; |
623 | default: | |
624 | return UINT64_MAX; | |
80c4627b AL |
625 | } |
626 | value = (((u64)high) << 16) | low; | |
627 | return value; | |
628 | } | |
629 | ||
dfafe449 AL |
630 | static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, |
631 | uint8_t *data, int types) | |
91da11f8 | 632 | { |
f5e2ed02 AL |
633 | struct mv88e6xxx_hw_stat *stat; |
634 | int i, j; | |
91da11f8 | 635 | |
f5e2ed02 AL |
636 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { |
637 | stat = &mv88e6xxx_hw_stats[i]; | |
dfafe449 | 638 | if (stat->type & types) { |
f5e2ed02 AL |
639 | memcpy(data + j * ETH_GSTRING_LEN, stat->string, |
640 | ETH_GSTRING_LEN); | |
641 | j++; | |
642 | } | |
91da11f8 | 643 | } |
e413e7e1 AL |
644 | } |
645 | ||
dfafe449 AL |
646 | static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, |
647 | uint8_t *data) | |
648 | { | |
649 | mv88e6xxx_stats_get_strings(chip, data, | |
650 | STATS_TYPE_BANK0 | STATS_TYPE_PORT); | |
651 | } | |
652 | ||
653 | static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, | |
654 | uint8_t *data) | |
655 | { | |
656 | mv88e6xxx_stats_get_strings(chip, data, | |
657 | STATS_TYPE_BANK0 | STATS_TYPE_BANK1); | |
658 | } | |
659 | ||
660 | static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, | |
661 | uint8_t *data) | |
e413e7e1 | 662 | { |
04bed143 | 663 | struct mv88e6xxx_chip *chip = ds->priv; |
dfafe449 AL |
664 | |
665 | if (chip->info->ops->stats_get_strings) | |
666 | chip->info->ops->stats_get_strings(chip, data); | |
667 | } | |
668 | ||
669 | static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, | |
670 | int types) | |
671 | { | |
f5e2ed02 AL |
672 | struct mv88e6xxx_hw_stat *stat; |
673 | int i, j; | |
674 | ||
675 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { | |
676 | stat = &mv88e6xxx_hw_stats[i]; | |
dfafe449 | 677 | if (stat->type & types) |
f5e2ed02 AL |
678 | j++; |
679 | } | |
680 | return j; | |
e413e7e1 AL |
681 | } |
682 | ||
dfafe449 AL |
683 | static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) |
684 | { | |
685 | return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | | |
686 | STATS_TYPE_PORT); | |
687 | } | |
688 | ||
689 | static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) | |
690 | { | |
691 | return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | | |
692 | STATS_TYPE_BANK1); | |
693 | } | |
694 | ||
695 | static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) | |
696 | { | |
697 | struct mv88e6xxx_chip *chip = ds->priv; | |
698 | ||
699 | if (chip->info->ops->stats_get_sset_count) | |
700 | return chip->info->ops->stats_get_sset_count(chip); | |
701 | ||
702 | return 0; | |
703 | } | |
704 | ||
052f947f | 705 | static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, |
e0d8b615 AL |
706 | uint64_t *data, int types, |
707 | u16 bank1_select, u16 histogram) | |
052f947f AL |
708 | { |
709 | struct mv88e6xxx_hw_stat *stat; | |
710 | int i, j; | |
711 | ||
712 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { | |
713 | stat = &mv88e6xxx_hw_stats[i]; | |
714 | if (stat->type & types) { | |
e0d8b615 AL |
715 | data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, |
716 | bank1_select, | |
717 | histogram); | |
052f947f AL |
718 | j++; |
719 | } | |
720 | } | |
721 | } | |
722 | ||
723 | static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, | |
724 | uint64_t *data) | |
725 | { | |
726 | return mv88e6xxx_stats_get_stats(chip, port, data, | |
e0d8b615 AL |
727 | STATS_TYPE_BANK0 | STATS_TYPE_PORT, |
728 | 0, GLOBAL_STATS_OP_HIST_RX_TX); | |
052f947f AL |
729 | } |
730 | ||
731 | static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, | |
732 | uint64_t *data) | |
733 | { | |
734 | return mv88e6xxx_stats_get_stats(chip, port, data, | |
e0d8b615 AL |
735 | STATS_TYPE_BANK0 | STATS_TYPE_BANK1, |
736 | GLOBAL_STATS_OP_BANK_1_BIT_9, | |
737 | GLOBAL_STATS_OP_HIST_RX_TX); | |
738 | } | |
739 | ||
740 | static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, | |
741 | uint64_t *data) | |
742 | { | |
743 | return mv88e6xxx_stats_get_stats(chip, port, data, | |
744 | STATS_TYPE_BANK0 | STATS_TYPE_BANK1, | |
745 | GLOBAL_STATS_OP_BANK_1_BIT_10, 0); | |
052f947f AL |
746 | } |
747 | ||
748 | static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, | |
749 | uint64_t *data) | |
750 | { | |
751 | if (chip->info->ops->stats_get_stats) | |
752 | chip->info->ops->stats_get_stats(chip, port, data); | |
753 | } | |
754 | ||
f81ec90f VD |
755 | static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, |
756 | uint64_t *data) | |
e413e7e1 | 757 | { |
04bed143 | 758 | struct mv88e6xxx_chip *chip = ds->priv; |
f5e2ed02 | 759 | int ret; |
f5e2ed02 | 760 | |
fad09c73 | 761 | mutex_lock(&chip->reg_lock); |
f5e2ed02 | 762 | |
a605a0fe | 763 | ret = mv88e6xxx_stats_snapshot(chip, port); |
f5e2ed02 | 764 | if (ret < 0) { |
fad09c73 | 765 | mutex_unlock(&chip->reg_lock); |
f5e2ed02 AL |
766 | return; |
767 | } | |
052f947f AL |
768 | |
769 | mv88e6xxx_get_stats(chip, port, data); | |
f5e2ed02 | 770 | |
fad09c73 | 771 | mutex_unlock(&chip->reg_lock); |
e413e7e1 AL |
772 | } |
773 | ||
de227387 AL |
774 | static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip) |
775 | { | |
776 | if (chip->info->ops->stats_set_histogram) | |
777 | return chip->info->ops->stats_set_histogram(chip); | |
778 | ||
779 | return 0; | |
780 | } | |
781 | ||
f81ec90f | 782 | static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) |
a1ab91f3 GR |
783 | { |
784 | return 32 * sizeof(u16); | |
785 | } | |
786 | ||
f81ec90f VD |
787 | static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, |
788 | struct ethtool_regs *regs, void *_p) | |
a1ab91f3 | 789 | { |
04bed143 | 790 | struct mv88e6xxx_chip *chip = ds->priv; |
0e7b9925 AL |
791 | int err; |
792 | u16 reg; | |
a1ab91f3 GR |
793 | u16 *p = _p; |
794 | int i; | |
795 | ||
796 | regs->version = 0; | |
797 | ||
798 | memset(p, 0xff, 32 * sizeof(u16)); | |
799 | ||
fad09c73 | 800 | mutex_lock(&chip->reg_lock); |
23062513 | 801 | |
a1ab91f3 | 802 | for (i = 0; i < 32; i++) { |
a1ab91f3 | 803 | |
0e7b9925 AL |
804 | err = mv88e6xxx_port_read(chip, port, i, ®); |
805 | if (!err) | |
806 | p[i] = reg; | |
a1ab91f3 | 807 | } |
23062513 | 808 | |
fad09c73 | 809 | mutex_unlock(&chip->reg_lock); |
a1ab91f3 GR |
810 | } |
811 | ||
f81ec90f VD |
812 | static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, |
813 | struct ethtool_eee *e) | |
11b3b45d | 814 | { |
04bed143 | 815 | struct mv88e6xxx_chip *chip = ds->priv; |
9c93829c VD |
816 | u16 reg; |
817 | int err; | |
11b3b45d | 818 | |
fad09c73 | 819 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) |
aadbdb8a VD |
820 | return -EOPNOTSUPP; |
821 | ||
fad09c73 | 822 | mutex_lock(&chip->reg_lock); |
2f40c698 | 823 | |
9c93829c VD |
824 | err = mv88e6xxx_phy_read(chip, port, 16, ®); |
825 | if (err) | |
2f40c698 | 826 | goto out; |
11b3b45d GR |
827 | |
828 | e->eee_enabled = !!(reg & 0x0200); | |
829 | e->tx_lpi_enabled = !!(reg & 0x0100); | |
830 | ||
5f83dc93 | 831 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); |
9c93829c | 832 | if (err) |
2f40c698 | 833 | goto out; |
11b3b45d | 834 | |
5f83dc93 | 835 | e->eee_active = !!(reg & MV88E6352_PORT_STS_EEE); |
2f40c698 | 836 | out: |
fad09c73 | 837 | mutex_unlock(&chip->reg_lock); |
9c93829c VD |
838 | |
839 | return err; | |
11b3b45d GR |
840 | } |
841 | ||
f81ec90f VD |
842 | static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, |
843 | struct phy_device *phydev, struct ethtool_eee *e) | |
11b3b45d | 844 | { |
04bed143 | 845 | struct mv88e6xxx_chip *chip = ds->priv; |
9c93829c VD |
846 | u16 reg; |
847 | int err; | |
11b3b45d | 848 | |
fad09c73 | 849 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) |
aadbdb8a VD |
850 | return -EOPNOTSUPP; |
851 | ||
fad09c73 | 852 | mutex_lock(&chip->reg_lock); |
11b3b45d | 853 | |
9c93829c VD |
854 | err = mv88e6xxx_phy_read(chip, port, 16, ®); |
855 | if (err) | |
2f40c698 AL |
856 | goto out; |
857 | ||
9c93829c | 858 | reg &= ~0x0300; |
2f40c698 AL |
859 | if (e->eee_enabled) |
860 | reg |= 0x0200; | |
861 | if (e->tx_lpi_enabled) | |
862 | reg |= 0x0100; | |
863 | ||
9c93829c | 864 | err = mv88e6xxx_phy_write(chip, port, 16, reg); |
2f40c698 | 865 | out: |
fad09c73 | 866 | mutex_unlock(&chip->reg_lock); |
2f40c698 | 867 | |
9c93829c | 868 | return err; |
11b3b45d GR |
869 | } |
870 | ||
e5887a2a | 871 | static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) |
facd95b2 | 872 | { |
e5887a2a VD |
873 | struct dsa_switch *ds = NULL; |
874 | struct net_device *br; | |
875 | u16 pvlan; | |
b7666efe VD |
876 | int i; |
877 | ||
e5887a2a VD |
878 | if (dev < DSA_MAX_SWITCHES) |
879 | ds = chip->ds->dst->ds[dev]; | |
880 | ||
881 | /* Prevent frames from unknown switch or port */ | |
882 | if (!ds || port >= ds->num_ports) | |
883 | return 0; | |
884 | ||
885 | /* Frames from DSA links and CPU ports can egress any local port */ | |
886 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) | |
887 | return mv88e6xxx_port_mask(chip); | |
888 | ||
889 | br = ds->ports[port].bridge_dev; | |
890 | pvlan = 0; | |
891 | ||
892 | /* Frames from user ports can egress any local DSA links and CPU ports, | |
893 | * as well as any local member of their bridge group. | |
894 | */ | |
895 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) | |
896 | if (dsa_is_cpu_port(chip->ds, i) || | |
897 | dsa_is_dsa_port(chip->ds, i) || | |
898 | (br && chip->ds->ports[i].bridge_dev == br)) | |
899 | pvlan |= BIT(i); | |
900 | ||
901 | return pvlan; | |
902 | } | |
903 | ||
240ea3ef | 904 | static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) |
e5887a2a VD |
905 | { |
906 | u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); | |
b7666efe VD |
907 | |
908 | /* prevent frames from going back out of the port they came in on */ | |
909 | output_ports &= ~BIT(port); | |
facd95b2 | 910 | |
5a7921f4 | 911 | return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); |
facd95b2 GR |
912 | } |
913 | ||
f81ec90f VD |
914 | static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, |
915 | u8 state) | |
facd95b2 | 916 | { |
04bed143 | 917 | struct mv88e6xxx_chip *chip = ds->priv; |
553eb544 | 918 | int err; |
facd95b2 | 919 | |
fad09c73 | 920 | mutex_lock(&chip->reg_lock); |
f894c29c | 921 | err = mv88e6xxx_port_set_state(chip, port, state); |
fad09c73 | 922 | mutex_unlock(&chip->reg_lock); |
553eb544 VD |
923 | |
924 | if (err) | |
774439e5 | 925 | dev_err(ds->dev, "p%d: failed to update state\n", port); |
facd95b2 GR |
926 | } |
927 | ||
a2ac29d2 VD |
928 | static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) |
929 | { | |
c3a7d4ad VD |
930 | int err; |
931 | ||
daefc943 VD |
932 | err = mv88e6xxx_g1_atu_flush(chip, 0, true); |
933 | if (err) | |
934 | return err; | |
935 | ||
c3a7d4ad VD |
936 | err = mv88e6xxx_g1_atu_set_learn2all(chip, true); |
937 | if (err) | |
938 | return err; | |
939 | ||
a2ac29d2 VD |
940 | return mv88e6xxx_g1_atu_set_age_time(chip, 300000); |
941 | } | |
942 | ||
17a1594e VD |
943 | static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) |
944 | { | |
945 | u16 pvlan = 0; | |
946 | ||
947 | if (!mv88e6xxx_has_pvt(chip)) | |
948 | return -EOPNOTSUPP; | |
949 | ||
950 | /* Skip the local source device, which uses in-chip port VLAN */ | |
951 | if (dev != chip->ds->index) | |
aec5ac88 | 952 | pvlan = mv88e6xxx_port_vlan(chip, dev, port); |
17a1594e VD |
953 | |
954 | return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); | |
955 | } | |
956 | ||
81228996 VD |
957 | static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) |
958 | { | |
17a1594e VD |
959 | int dev, port; |
960 | int err; | |
961 | ||
81228996 VD |
962 | if (!mv88e6xxx_has_pvt(chip)) |
963 | return 0; | |
964 | ||
965 | /* Clear 5 Bit Port for usage with Marvell Link Street devices: | |
966 | * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. | |
967 | */ | |
17a1594e VD |
968 | err = mv88e6xxx_g2_misc_4_bit_port(chip); |
969 | if (err) | |
970 | return err; | |
971 | ||
972 | for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { | |
973 | for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { | |
974 | err = mv88e6xxx_pvt_map(chip, dev, port); | |
975 | if (err) | |
976 | return err; | |
977 | } | |
978 | } | |
979 | ||
980 | return 0; | |
81228996 VD |
981 | } |
982 | ||
749efcb8 VD |
983 | static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) |
984 | { | |
985 | struct mv88e6xxx_chip *chip = ds->priv; | |
986 | int err; | |
987 | ||
988 | mutex_lock(&chip->reg_lock); | |
e606ca36 | 989 | err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); |
749efcb8 VD |
990 | mutex_unlock(&chip->reg_lock); |
991 | ||
992 | if (err) | |
774439e5 | 993 | dev_err(ds->dev, "p%d: failed to flush ATU\n", port); |
749efcb8 VD |
994 | } |
995 | ||
b486d7c9 VD |
996 | static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) |
997 | { | |
998 | if (!chip->info->max_vid) | |
999 | return 0; | |
1000 | ||
1001 | return mv88e6xxx_g1_vtu_flush(chip); | |
1002 | } | |
1003 | ||
f1394b78 VD |
1004 | static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, |
1005 | struct mv88e6xxx_vtu_entry *entry) | |
1006 | { | |
1007 | if (!chip->info->ops->vtu_getnext) | |
1008 | return -EOPNOTSUPP; | |
1009 | ||
1010 | return chip->info->ops->vtu_getnext(chip, entry); | |
1011 | } | |
1012 | ||
0ad5daf6 VD |
1013 | static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, |
1014 | struct mv88e6xxx_vtu_entry *entry) | |
1015 | { | |
1016 | if (!chip->info->ops->vtu_loadpurge) | |
1017 | return -EOPNOTSUPP; | |
1018 | ||
1019 | return chip->info->ops->vtu_loadpurge(chip, entry); | |
1020 | } | |
1021 | ||
f81ec90f VD |
1022 | static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port, |
1023 | struct switchdev_obj_port_vlan *vlan, | |
438ff537 | 1024 | switchdev_obj_dump_cb_t *cb) |
ceff5eff | 1025 | { |
04bed143 | 1026 | struct mv88e6xxx_chip *chip = ds->priv; |
3afb4bde VD |
1027 | struct mv88e6xxx_vtu_entry next = { |
1028 | .vid = chip->info->max_vid, | |
1029 | }; | |
ceff5eff VD |
1030 | u16 pvid; |
1031 | int err; | |
1032 | ||
3cf3c846 | 1033 | if (!chip->info->max_vid) |
54d77b5b VD |
1034 | return -EOPNOTSUPP; |
1035 | ||
fad09c73 | 1036 | mutex_lock(&chip->reg_lock); |
ceff5eff | 1037 | |
77064f37 | 1038 | err = mv88e6xxx_port_get_pvid(chip, port, &pvid); |
ceff5eff VD |
1039 | if (err) |
1040 | goto unlock; | |
1041 | ||
ceff5eff | 1042 | do { |
f1394b78 | 1043 | err = mv88e6xxx_vtu_getnext(chip, &next); |
ceff5eff VD |
1044 | if (err) |
1045 | break; | |
1046 | ||
1047 | if (!next.valid) | |
1048 | break; | |
1049 | ||
bd00e053 | 1050 | if (next.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) |
ceff5eff VD |
1051 | continue; |
1052 | ||
1053 | /* reinit and dump this VLAN obj */ | |
57d32310 VD |
1054 | vlan->vid_begin = next.vid; |
1055 | vlan->vid_end = next.vid; | |
ceff5eff VD |
1056 | vlan->flags = 0; |
1057 | ||
bd00e053 | 1058 | if (next.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED) |
ceff5eff VD |
1059 | vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED; |
1060 | ||
1061 | if (next.vid == pvid) | |
1062 | vlan->flags |= BRIDGE_VLAN_INFO_PVID; | |
1063 | ||
1064 | err = cb(&vlan->obj); | |
1065 | if (err) | |
1066 | break; | |
3cf3c846 | 1067 | } while (next.vid < chip->info->max_vid); |
ceff5eff VD |
1068 | |
1069 | unlock: | |
fad09c73 | 1070 | mutex_unlock(&chip->reg_lock); |
ceff5eff VD |
1071 | |
1072 | return err; | |
1073 | } | |
1074 | ||
d7f435f9 | 1075 | static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) |
3285f9e8 VD |
1076 | { |
1077 | DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); | |
3afb4bde VD |
1078 | struct mv88e6xxx_vtu_entry vlan = { |
1079 | .vid = chip->info->max_vid, | |
1080 | }; | |
2db9ce1f | 1081 | int i, err; |
3285f9e8 VD |
1082 | |
1083 | bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); | |
1084 | ||
2db9ce1f | 1085 | /* Set every FID bit used by the (un)bridged ports */ |
370b4ffb | 1086 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
b4e48c50 | 1087 | err = mv88e6xxx_port_get_fid(chip, i, fid); |
2db9ce1f VD |
1088 | if (err) |
1089 | return err; | |
1090 | ||
1091 | set_bit(*fid, fid_bitmap); | |
1092 | } | |
1093 | ||
3285f9e8 | 1094 | /* Set every FID bit used by the VLAN entries */ |
3285f9e8 | 1095 | do { |
f1394b78 | 1096 | err = mv88e6xxx_vtu_getnext(chip, &vlan); |
3285f9e8 VD |
1097 | if (err) |
1098 | return err; | |
1099 | ||
1100 | if (!vlan.valid) | |
1101 | break; | |
1102 | ||
1103 | set_bit(vlan.fid, fid_bitmap); | |
3cf3c846 | 1104 | } while (vlan.vid < chip->info->max_vid); |
3285f9e8 VD |
1105 | |
1106 | /* The reset value 0x000 is used to indicate that multiple address | |
1107 | * databases are not needed. Return the next positive available. | |
1108 | */ | |
1109 | *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); | |
fad09c73 | 1110 | if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) |
3285f9e8 VD |
1111 | return -ENOSPC; |
1112 | ||
1113 | /* Clear the database */ | |
daefc943 | 1114 | return mv88e6xxx_g1_atu_flush(chip, *fid, true); |
3285f9e8 VD |
1115 | } |
1116 | ||
567aa59a VD |
1117 | static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, |
1118 | struct mv88e6xxx_vtu_entry *entry, bool new) | |
2fb5ef09 VD |
1119 | { |
1120 | int err; | |
1121 | ||
1122 | if (!vid) | |
1123 | return -EINVAL; | |
1124 | ||
3afb4bde VD |
1125 | entry->vid = vid - 1; |
1126 | entry->valid = false; | |
2fb5ef09 | 1127 | |
f1394b78 | 1128 | err = mv88e6xxx_vtu_getnext(chip, entry); |
2fb5ef09 VD |
1129 | if (err) |
1130 | return err; | |
1131 | ||
567aa59a VD |
1132 | if (entry->vid == vid && entry->valid) |
1133 | return 0; | |
2fb5ef09 | 1134 | |
567aa59a VD |
1135 | if (new) { |
1136 | int i; | |
1137 | ||
1138 | /* Initialize a fresh VLAN entry */ | |
1139 | memset(entry, 0, sizeof(*entry)); | |
1140 | entry->valid = true; | |
1141 | entry->vid = vid; | |
1142 | ||
553a768d | 1143 | /* Exclude all ports */ |
567aa59a | 1144 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) |
553a768d VD |
1145 | entry->member[i] = |
1146 | GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; | |
567aa59a VD |
1147 | |
1148 | return mv88e6xxx_atu_new(chip, &entry->fid); | |
2fb5ef09 VD |
1149 | } |
1150 | ||
567aa59a VD |
1151 | /* switchdev expects -EOPNOTSUPP to honor software VLANs */ |
1152 | return -EOPNOTSUPP; | |
2fb5ef09 VD |
1153 | } |
1154 | ||
da9c359e VD |
1155 | static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, |
1156 | u16 vid_begin, u16 vid_end) | |
1157 | { | |
04bed143 | 1158 | struct mv88e6xxx_chip *chip = ds->priv; |
3afb4bde VD |
1159 | struct mv88e6xxx_vtu_entry vlan = { |
1160 | .vid = vid_begin - 1, | |
1161 | }; | |
da9c359e VD |
1162 | int i, err; |
1163 | ||
1164 | if (!vid_begin) | |
1165 | return -EOPNOTSUPP; | |
1166 | ||
fad09c73 | 1167 | mutex_lock(&chip->reg_lock); |
da9c359e | 1168 | |
da9c359e | 1169 | do { |
f1394b78 | 1170 | err = mv88e6xxx_vtu_getnext(chip, &vlan); |
da9c359e VD |
1171 | if (err) |
1172 | goto unlock; | |
1173 | ||
1174 | if (!vlan.valid) | |
1175 | break; | |
1176 | ||
1177 | if (vlan.vid > vid_end) | |
1178 | break; | |
1179 | ||
370b4ffb | 1180 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
da9c359e VD |
1181 | if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) |
1182 | continue; | |
1183 | ||
66e2809d AL |
1184 | if (!ds->ports[port].netdev) |
1185 | continue; | |
1186 | ||
bd00e053 | 1187 | if (vlan.member[i] == |
da9c359e VD |
1188 | GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) |
1189 | continue; | |
1190 | ||
fae8a25e VD |
1191 | if (ds->ports[i].bridge_dev == |
1192 | ds->ports[port].bridge_dev) | |
da9c359e VD |
1193 | break; /* same bridge, check next VLAN */ |
1194 | ||
fae8a25e | 1195 | if (!ds->ports[i].bridge_dev) |
66e2809d AL |
1196 | continue; |
1197 | ||
774439e5 VD |
1198 | dev_err(ds->dev, "p%d: hw VLAN %d already used by %s\n", |
1199 | port, vlan.vid, | |
1200 | netdev_name(ds->ports[i].bridge_dev)); | |
da9c359e VD |
1201 | err = -EOPNOTSUPP; |
1202 | goto unlock; | |
1203 | } | |
1204 | } while (vlan.vid < vid_end); | |
1205 | ||
1206 | unlock: | |
fad09c73 | 1207 | mutex_unlock(&chip->reg_lock); |
da9c359e VD |
1208 | |
1209 | return err; | |
1210 | } | |
1211 | ||
f81ec90f VD |
1212 | static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, |
1213 | bool vlan_filtering) | |
214cdb99 | 1214 | { |
04bed143 | 1215 | struct mv88e6xxx_chip *chip = ds->priv; |
81c6edb2 VD |
1216 | u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : |
1217 | MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; | |
0e7b9925 | 1218 | int err; |
214cdb99 | 1219 | |
3cf3c846 | 1220 | if (!chip->info->max_vid) |
54d77b5b VD |
1221 | return -EOPNOTSUPP; |
1222 | ||
fad09c73 | 1223 | mutex_lock(&chip->reg_lock); |
385a0995 | 1224 | err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); |
fad09c73 | 1225 | mutex_unlock(&chip->reg_lock); |
214cdb99 | 1226 | |
0e7b9925 | 1227 | return err; |
214cdb99 VD |
1228 | } |
1229 | ||
57d32310 VD |
1230 | static int |
1231 | mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, | |
1232 | const struct switchdev_obj_port_vlan *vlan, | |
1233 | struct switchdev_trans *trans) | |
76e398a6 | 1234 | { |
04bed143 | 1235 | struct mv88e6xxx_chip *chip = ds->priv; |
da9c359e VD |
1236 | int err; |
1237 | ||
3cf3c846 | 1238 | if (!chip->info->max_vid) |
54d77b5b VD |
1239 | return -EOPNOTSUPP; |
1240 | ||
da9c359e VD |
1241 | /* If the requested port doesn't belong to the same bridge as the VLAN |
1242 | * members, do not support it (yet) and fallback to software VLAN. | |
1243 | */ | |
1244 | err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, | |
1245 | vlan->vid_end); | |
1246 | if (err) | |
1247 | return err; | |
1248 | ||
76e398a6 VD |
1249 | /* We don't need any dynamic resource from the kernel (yet), |
1250 | * so skip the prepare phase. | |
1251 | */ | |
1252 | return 0; | |
1253 | } | |
1254 | ||
fad09c73 | 1255 | static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, |
c91498e1 | 1256 | u16 vid, u8 member) |
0d3b33e6 | 1257 | { |
b4e47c0f | 1258 | struct mv88e6xxx_vtu_entry vlan; |
0d3b33e6 VD |
1259 | int err; |
1260 | ||
567aa59a | 1261 | err = mv88e6xxx_vtu_get(chip, vid, &vlan, true); |
0d3b33e6 | 1262 | if (err) |
76e398a6 | 1263 | return err; |
0d3b33e6 | 1264 | |
c91498e1 | 1265 | vlan.member[port] = member; |
0d3b33e6 | 1266 | |
0ad5daf6 | 1267 | return mv88e6xxx_vtu_loadpurge(chip, &vlan); |
76e398a6 VD |
1268 | } |
1269 | ||
f81ec90f VD |
1270 | static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, |
1271 | const struct switchdev_obj_port_vlan *vlan, | |
1272 | struct switchdev_trans *trans) | |
76e398a6 | 1273 | { |
04bed143 | 1274 | struct mv88e6xxx_chip *chip = ds->priv; |
76e398a6 VD |
1275 | bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; |
1276 | bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; | |
c91498e1 | 1277 | u8 member; |
76e398a6 | 1278 | u16 vid; |
76e398a6 | 1279 | |
3cf3c846 | 1280 | if (!chip->info->max_vid) |
54d77b5b VD |
1281 | return; |
1282 | ||
c91498e1 VD |
1283 | if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) |
1284 | member = GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED; | |
1285 | else if (untagged) | |
1286 | member = GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED; | |
1287 | else | |
1288 | member = GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED; | |
1289 | ||
fad09c73 | 1290 | mutex_lock(&chip->reg_lock); |
76e398a6 | 1291 | |
4d5770b3 | 1292 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) |
c91498e1 | 1293 | if (_mv88e6xxx_port_vlan_add(chip, port, vid, member)) |
774439e5 VD |
1294 | dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, |
1295 | vid, untagged ? 'u' : 't'); | |
76e398a6 | 1296 | |
77064f37 | 1297 | if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) |
774439e5 VD |
1298 | dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, |
1299 | vlan->vid_end); | |
0d3b33e6 | 1300 | |
fad09c73 | 1301 | mutex_unlock(&chip->reg_lock); |
0d3b33e6 VD |
1302 | } |
1303 | ||
fad09c73 | 1304 | static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, |
158bc065 | 1305 | int port, u16 vid) |
7dad08d7 | 1306 | { |
b4e47c0f | 1307 | struct mv88e6xxx_vtu_entry vlan; |
7dad08d7 VD |
1308 | int i, err; |
1309 | ||
567aa59a | 1310 | err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); |
7dad08d7 | 1311 | if (err) |
76e398a6 | 1312 | return err; |
7dad08d7 | 1313 | |
2fb5ef09 | 1314 | /* Tell switchdev if this VLAN is handled in software */ |
bd00e053 | 1315 | if (vlan.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) |
3c06f08b | 1316 | return -EOPNOTSUPP; |
7dad08d7 | 1317 | |
bd00e053 | 1318 | vlan.member[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; |
7dad08d7 VD |
1319 | |
1320 | /* keep the VLAN unless all ports are excluded */ | |
f02bdffc | 1321 | vlan.valid = false; |
370b4ffb | 1322 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
bd00e053 | 1323 | if (vlan.member[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) { |
f02bdffc | 1324 | vlan.valid = true; |
7dad08d7 VD |
1325 | break; |
1326 | } | |
1327 | } | |
1328 | ||
0ad5daf6 | 1329 | err = mv88e6xxx_vtu_loadpurge(chip, &vlan); |
76e398a6 VD |
1330 | if (err) |
1331 | return err; | |
1332 | ||
e606ca36 | 1333 | return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); |
76e398a6 VD |
1334 | } |
1335 | ||
f81ec90f VD |
1336 | static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, |
1337 | const struct switchdev_obj_port_vlan *vlan) | |
76e398a6 | 1338 | { |
04bed143 | 1339 | struct mv88e6xxx_chip *chip = ds->priv; |
76e398a6 VD |
1340 | u16 pvid, vid; |
1341 | int err = 0; | |
1342 | ||
3cf3c846 | 1343 | if (!chip->info->max_vid) |
54d77b5b VD |
1344 | return -EOPNOTSUPP; |
1345 | ||
fad09c73 | 1346 | mutex_lock(&chip->reg_lock); |
76e398a6 | 1347 | |
77064f37 | 1348 | err = mv88e6xxx_port_get_pvid(chip, port, &pvid); |
7dad08d7 VD |
1349 | if (err) |
1350 | goto unlock; | |
1351 | ||
76e398a6 | 1352 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { |
fad09c73 | 1353 | err = _mv88e6xxx_port_vlan_del(chip, port, vid); |
76e398a6 VD |
1354 | if (err) |
1355 | goto unlock; | |
1356 | ||
1357 | if (vid == pvid) { | |
77064f37 | 1358 | err = mv88e6xxx_port_set_pvid(chip, port, 0); |
76e398a6 VD |
1359 | if (err) |
1360 | goto unlock; | |
1361 | } | |
1362 | } | |
1363 | ||
7dad08d7 | 1364 | unlock: |
fad09c73 | 1365 | mutex_unlock(&chip->reg_lock); |
7dad08d7 VD |
1366 | |
1367 | return err; | |
1368 | } | |
1369 | ||
83dabd1f VD |
1370 | static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, |
1371 | const unsigned char *addr, u16 vid, | |
1372 | u8 state) | |
fd231c82 | 1373 | { |
b4e47c0f | 1374 | struct mv88e6xxx_vtu_entry vlan; |
88472939 | 1375 | struct mv88e6xxx_atu_entry entry; |
3285f9e8 VD |
1376 | int err; |
1377 | ||
2db9ce1f VD |
1378 | /* Null VLAN ID corresponds to the port private database */ |
1379 | if (vid == 0) | |
b4e48c50 | 1380 | err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); |
2db9ce1f | 1381 | else |
567aa59a | 1382 | err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); |
3285f9e8 VD |
1383 | if (err) |
1384 | return err; | |
fd231c82 | 1385 | |
27c0e600 | 1386 | entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; |
dabc1a96 VD |
1387 | ether_addr_copy(entry.mac, addr); |
1388 | eth_addr_dec(entry.mac); | |
1389 | ||
1390 | err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry); | |
88472939 VD |
1391 | if (err) |
1392 | return err; | |
1393 | ||
dabc1a96 | 1394 | /* Initialize a fresh ATU entry if it isn't found */ |
27c0e600 | 1395 | if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || |
dabc1a96 VD |
1396 | !ether_addr_equal(entry.mac, addr)) { |
1397 | memset(&entry, 0, sizeof(entry)); | |
1398 | ether_addr_copy(entry.mac, addr); | |
1399 | } | |
1400 | ||
88472939 | 1401 | /* Purge the ATU entry only if no port is using it anymore */ |
27c0e600 | 1402 | if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { |
01bd96c8 VD |
1403 | entry.portvec &= ~BIT(port); |
1404 | if (!entry.portvec) | |
27c0e600 | 1405 | entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; |
88472939 | 1406 | } else { |
01bd96c8 | 1407 | entry.portvec |= BIT(port); |
88472939 | 1408 | entry.state = state; |
fd231c82 VD |
1409 | } |
1410 | ||
9c13c026 | 1411 | return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry); |
87820510 VD |
1412 | } |
1413 | ||
f81ec90f VD |
1414 | static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, |
1415 | const struct switchdev_obj_port_fdb *fdb, | |
1416 | struct switchdev_trans *trans) | |
146a3206 VD |
1417 | { |
1418 | /* We don't need any dynamic resource from the kernel (yet), | |
1419 | * so skip the prepare phase. | |
1420 | */ | |
1421 | return 0; | |
1422 | } | |
1423 | ||
f81ec90f VD |
1424 | static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, |
1425 | const struct switchdev_obj_port_fdb *fdb, | |
1426 | struct switchdev_trans *trans) | |
87820510 | 1427 | { |
04bed143 | 1428 | struct mv88e6xxx_chip *chip = ds->priv; |
87820510 | 1429 | |
fad09c73 | 1430 | mutex_lock(&chip->reg_lock); |
83dabd1f | 1431 | if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, |
27c0e600 | 1432 | MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)) |
774439e5 VD |
1433 | dev_err(ds->dev, "p%d: failed to load unicast MAC address\n", |
1434 | port); | |
fad09c73 | 1435 | mutex_unlock(&chip->reg_lock); |
87820510 VD |
1436 | } |
1437 | ||
f81ec90f VD |
1438 | static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, |
1439 | const struct switchdev_obj_port_fdb *fdb) | |
87820510 | 1440 | { |
04bed143 | 1441 | struct mv88e6xxx_chip *chip = ds->priv; |
83dabd1f | 1442 | int err; |
87820510 | 1443 | |
fad09c73 | 1444 | mutex_lock(&chip->reg_lock); |
83dabd1f | 1445 | err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, |
27c0e600 | 1446 | MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); |
fad09c73 | 1447 | mutex_unlock(&chip->reg_lock); |
87820510 | 1448 | |
83dabd1f | 1449 | return err; |
87820510 VD |
1450 | } |
1451 | ||
83dabd1f VD |
1452 | static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, |
1453 | u16 fid, u16 vid, int port, | |
1454 | struct switchdev_obj *obj, | |
438ff537 | 1455 | switchdev_obj_dump_cb_t *cb) |
74b6ba0d | 1456 | { |
dabc1a96 | 1457 | struct mv88e6xxx_atu_entry addr; |
74b6ba0d VD |
1458 | int err; |
1459 | ||
27c0e600 | 1460 | addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; |
dabc1a96 | 1461 | eth_broadcast_addr(addr.mac); |
74b6ba0d VD |
1462 | |
1463 | do { | |
dabc1a96 | 1464 | err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); |
74b6ba0d | 1465 | if (err) |
83dabd1f | 1466 | return err; |
74b6ba0d | 1467 | |
27c0e600 | 1468 | if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) |
74b6ba0d VD |
1469 | break; |
1470 | ||
01bd96c8 | 1471 | if (addr.trunk || (addr.portvec & BIT(port)) == 0) |
83dabd1f VD |
1472 | continue; |
1473 | ||
1474 | if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) { | |
1475 | struct switchdev_obj_port_fdb *fdb; | |
74b6ba0d | 1476 | |
83dabd1f VD |
1477 | if (!is_unicast_ether_addr(addr.mac)) |
1478 | continue; | |
1479 | ||
1480 | fdb = SWITCHDEV_OBJ_PORT_FDB(obj); | |
74b6ba0d VD |
1481 | fdb->vid = vid; |
1482 | ether_addr_copy(fdb->addr, addr.mac); | |
27c0e600 | 1483 | if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) |
83dabd1f VD |
1484 | fdb->ndm_state = NUD_NOARP; |
1485 | else | |
1486 | fdb->ndm_state = NUD_REACHABLE; | |
7df8fbdd VD |
1487 | } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) { |
1488 | struct switchdev_obj_port_mdb *mdb; | |
1489 | ||
1490 | if (!is_multicast_ether_addr(addr.mac)) | |
1491 | continue; | |
1492 | ||
1493 | mdb = SWITCHDEV_OBJ_PORT_MDB(obj); | |
1494 | mdb->vid = vid; | |
1495 | ether_addr_copy(mdb->addr, addr.mac); | |
83dabd1f VD |
1496 | } else { |
1497 | return -EOPNOTSUPP; | |
74b6ba0d | 1498 | } |
83dabd1f VD |
1499 | |
1500 | err = cb(obj); | |
1501 | if (err) | |
1502 | return err; | |
74b6ba0d VD |
1503 | } while (!is_broadcast_ether_addr(addr.mac)); |
1504 | ||
1505 | return err; | |
1506 | } | |
1507 | ||
83dabd1f VD |
1508 | static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, |
1509 | struct switchdev_obj *obj, | |
438ff537 | 1510 | switchdev_obj_dump_cb_t *cb) |
f33475bd | 1511 | { |
b4e47c0f | 1512 | struct mv88e6xxx_vtu_entry vlan = { |
3cf3c846 | 1513 | .vid = chip->info->max_vid, |
f33475bd | 1514 | }; |
2db9ce1f | 1515 | u16 fid; |
f33475bd VD |
1516 | int err; |
1517 | ||
2db9ce1f | 1518 | /* Dump port's default Filtering Information Database (VLAN ID 0) */ |
b4e48c50 | 1519 | err = mv88e6xxx_port_get_fid(chip, port, &fid); |
2db9ce1f | 1520 | if (err) |
83dabd1f | 1521 | return err; |
2db9ce1f | 1522 | |
83dabd1f | 1523 | err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb); |
2db9ce1f | 1524 | if (err) |
83dabd1f | 1525 | return err; |
2db9ce1f | 1526 | |
74b6ba0d | 1527 | /* Dump VLANs' Filtering Information Databases */ |
f33475bd | 1528 | do { |
f1394b78 | 1529 | err = mv88e6xxx_vtu_getnext(chip, &vlan); |
f33475bd | 1530 | if (err) |
83dabd1f | 1531 | return err; |
f33475bd VD |
1532 | |
1533 | if (!vlan.valid) | |
1534 | break; | |
1535 | ||
83dabd1f VD |
1536 | err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, |
1537 | obj, cb); | |
f33475bd | 1538 | if (err) |
83dabd1f | 1539 | return err; |
3cf3c846 | 1540 | } while (vlan.vid < chip->info->max_vid); |
f33475bd | 1541 | |
83dabd1f VD |
1542 | return err; |
1543 | } | |
1544 | ||
1545 | static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, | |
1546 | struct switchdev_obj_port_fdb *fdb, | |
438ff537 | 1547 | switchdev_obj_dump_cb_t *cb) |
83dabd1f | 1548 | { |
04bed143 | 1549 | struct mv88e6xxx_chip *chip = ds->priv; |
83dabd1f VD |
1550 | int err; |
1551 | ||
1552 | mutex_lock(&chip->reg_lock); | |
1553 | err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb); | |
fad09c73 | 1554 | mutex_unlock(&chip->reg_lock); |
f33475bd VD |
1555 | |
1556 | return err; | |
1557 | } | |
1558 | ||
240ea3ef VD |
1559 | static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, |
1560 | struct net_device *br) | |
e79a8bcb | 1561 | { |
e96a6e02 | 1562 | struct dsa_switch *ds; |
240ea3ef | 1563 | int port; |
e96a6e02 | 1564 | int dev; |
240ea3ef | 1565 | int err; |
466dfa07 | 1566 | |
240ea3ef VD |
1567 | /* Remap the Port VLAN of each local bridge group member */ |
1568 | for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { | |
1569 | if (chip->ds->ports[port].bridge_dev == br) { | |
1570 | err = mv88e6xxx_port_vlan_map(chip, port); | |
b7666efe | 1571 | if (err) |
240ea3ef | 1572 | return err; |
b7666efe VD |
1573 | } |
1574 | } | |
1575 | ||
e96a6e02 VD |
1576 | if (!mv88e6xxx_has_pvt(chip)) |
1577 | return 0; | |
1578 | ||
1579 | /* Remap the Port VLAN of each cross-chip bridge group member */ | |
1580 | for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { | |
1581 | ds = chip->ds->dst->ds[dev]; | |
1582 | if (!ds) | |
1583 | break; | |
1584 | ||
1585 | for (port = 0; port < ds->num_ports; ++port) { | |
1586 | if (ds->ports[port].bridge_dev == br) { | |
1587 | err = mv88e6xxx_pvt_map(chip, dev, port); | |
1588 | if (err) | |
1589 | return err; | |
1590 | } | |
1591 | } | |
1592 | } | |
1593 | ||
240ea3ef VD |
1594 | return 0; |
1595 | } | |
1596 | ||
1597 | static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, | |
1598 | struct net_device *br) | |
1599 | { | |
1600 | struct mv88e6xxx_chip *chip = ds->priv; | |
1601 | int err; | |
1602 | ||
1603 | mutex_lock(&chip->reg_lock); | |
1604 | err = mv88e6xxx_bridge_map(chip, br); | |
fad09c73 | 1605 | mutex_unlock(&chip->reg_lock); |
a6692754 | 1606 | |
466dfa07 | 1607 | return err; |
e79a8bcb VD |
1608 | } |
1609 | ||
f123f2fb VD |
1610 | static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, |
1611 | struct net_device *br) | |
66d9cd0f | 1612 | { |
04bed143 | 1613 | struct mv88e6xxx_chip *chip = ds->priv; |
466dfa07 | 1614 | |
fad09c73 | 1615 | mutex_lock(&chip->reg_lock); |
240ea3ef VD |
1616 | if (mv88e6xxx_bridge_map(chip, br) || |
1617 | mv88e6xxx_port_vlan_map(chip, port)) | |
1618 | dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); | |
fad09c73 | 1619 | mutex_unlock(&chip->reg_lock); |
66d9cd0f VD |
1620 | } |
1621 | ||
aec5ac88 VD |
1622 | static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, |
1623 | int port, struct net_device *br) | |
1624 | { | |
1625 | struct mv88e6xxx_chip *chip = ds->priv; | |
1626 | int err; | |
1627 | ||
1628 | if (!mv88e6xxx_has_pvt(chip)) | |
1629 | return 0; | |
1630 | ||
1631 | mutex_lock(&chip->reg_lock); | |
1632 | err = mv88e6xxx_pvt_map(chip, dev, port); | |
1633 | mutex_unlock(&chip->reg_lock); | |
1634 | ||
1635 | return err; | |
1636 | } | |
1637 | ||
1638 | static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, | |
1639 | int port, struct net_device *br) | |
1640 | { | |
1641 | struct mv88e6xxx_chip *chip = ds->priv; | |
1642 | ||
1643 | if (!mv88e6xxx_has_pvt(chip)) | |
1644 | return; | |
1645 | ||
1646 | mutex_lock(&chip->reg_lock); | |
1647 | if (mv88e6xxx_pvt_map(chip, dev, port)) | |
1648 | dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); | |
1649 | mutex_unlock(&chip->reg_lock); | |
1650 | } | |
1651 | ||
17e708ba VD |
1652 | static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) |
1653 | { | |
1654 | if (chip->info->ops->reset) | |
1655 | return chip->info->ops->reset(chip); | |
1656 | ||
1657 | return 0; | |
1658 | } | |
1659 | ||
309eca6d VD |
1660 | static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) |
1661 | { | |
1662 | struct gpio_desc *gpiod = chip->reset; | |
1663 | ||
1664 | /* If there is a GPIO connected to the reset pin, toggle it */ | |
1665 | if (gpiod) { | |
1666 | gpiod_set_value_cansleep(gpiod, 1); | |
1667 | usleep_range(10000, 20000); | |
1668 | gpiod_set_value_cansleep(gpiod, 0); | |
1669 | usleep_range(10000, 20000); | |
1670 | } | |
1671 | } | |
1672 | ||
4ac4b5a6 | 1673 | static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) |
552238b5 | 1674 | { |
4ac4b5a6 | 1675 | int i, err; |
552238b5 | 1676 | |
4ac4b5a6 | 1677 | /* Set all ports to the Disabled state */ |
370b4ffb | 1678 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { |
f894c29c | 1679 | err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); |
0e7b9925 AL |
1680 | if (err) |
1681 | return err; | |
552238b5 VD |
1682 | } |
1683 | ||
4ac4b5a6 VD |
1684 | /* Wait for transmit queues to drain, |
1685 | * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. | |
1686 | */ | |
552238b5 VD |
1687 | usleep_range(2000, 4000); |
1688 | ||
4ac4b5a6 VD |
1689 | return 0; |
1690 | } | |
1691 | ||
1692 | static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) | |
1693 | { | |
4ac4b5a6 VD |
1694 | int err; |
1695 | ||
1696 | err = mv88e6xxx_disable_ports(chip); | |
1697 | if (err) | |
1698 | return err; | |
1699 | ||
309eca6d | 1700 | mv88e6xxx_hardware_reset(chip); |
552238b5 | 1701 | |
17e708ba | 1702 | return mv88e6xxx_software_reset(chip); |
552238b5 VD |
1703 | } |
1704 | ||
4314557c | 1705 | static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, |
31bef4e9 VD |
1706 | enum mv88e6xxx_frame_mode frame, |
1707 | enum mv88e6xxx_egress_mode egress, u16 etype) | |
56995cbc AL |
1708 | { |
1709 | int err; | |
1710 | ||
4314557c VD |
1711 | if (!chip->info->ops->port_set_frame_mode) |
1712 | return -EOPNOTSUPP; | |
1713 | ||
1714 | err = mv88e6xxx_port_set_egress_mode(chip, port, egress); | |
56995cbc AL |
1715 | if (err) |
1716 | return err; | |
1717 | ||
4314557c VD |
1718 | err = chip->info->ops->port_set_frame_mode(chip, port, frame); |
1719 | if (err) | |
1720 | return err; | |
1721 | ||
1722 | if (chip->info->ops->port_set_ether_type) | |
1723 | return chip->info->ops->port_set_ether_type(chip, port, etype); | |
1724 | ||
1725 | return 0; | |
56995cbc AL |
1726 | } |
1727 | ||
4314557c | 1728 | static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) |
56995cbc | 1729 | { |
4314557c | 1730 | return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, |
31bef4e9 | 1731 | MV88E6XXX_EGRESS_MODE_UNMODIFIED, |
b8109594 | 1732 | MV88E6XXX_PORT_ETH_TYPE_DEFAULT); |
4314557c | 1733 | } |
56995cbc | 1734 | |
4314557c VD |
1735 | static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) |
1736 | { | |
1737 | return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, | |
31bef4e9 | 1738 | MV88E6XXX_EGRESS_MODE_UNMODIFIED, |
b8109594 | 1739 | MV88E6XXX_PORT_ETH_TYPE_DEFAULT); |
4314557c | 1740 | } |
56995cbc | 1741 | |
4314557c VD |
1742 | static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) |
1743 | { | |
1744 | return mv88e6xxx_set_port_mode(chip, port, | |
1745 | MV88E6XXX_FRAME_MODE_ETHERTYPE, | |
31bef4e9 VD |
1746 | MV88E6XXX_EGRESS_MODE_ETHERTYPE, |
1747 | ETH_P_EDSA); | |
4314557c | 1748 | } |
56995cbc | 1749 | |
4314557c VD |
1750 | static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) |
1751 | { | |
1752 | if (dsa_is_dsa_port(chip->ds, port)) | |
1753 | return mv88e6xxx_set_port_mode_dsa(chip, port); | |
56995cbc | 1754 | |
4314557c VD |
1755 | if (dsa_is_normal_port(chip->ds, port)) |
1756 | return mv88e6xxx_set_port_mode_normal(chip, port); | |
56995cbc | 1757 | |
4314557c VD |
1758 | /* Setup CPU port mode depending on its supported tag format */ |
1759 | if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) | |
1760 | return mv88e6xxx_set_port_mode_dsa(chip, port); | |
56995cbc | 1761 | |
4314557c VD |
1762 | if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) |
1763 | return mv88e6xxx_set_port_mode_edsa(chip, port); | |
56995cbc | 1764 | |
4314557c | 1765 | return -EINVAL; |
56995cbc AL |
1766 | } |
1767 | ||
601aeed3 | 1768 | static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) |
56995cbc | 1769 | { |
601aeed3 | 1770 | bool message = dsa_is_dsa_port(chip->ds, port); |
56995cbc | 1771 | |
601aeed3 | 1772 | return mv88e6xxx_port_set_message_port(chip, port, message); |
4314557c | 1773 | } |
56995cbc | 1774 | |
601aeed3 | 1775 | static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) |
4314557c | 1776 | { |
601aeed3 | 1777 | bool flood = port == dsa_upstream_port(chip->ds); |
56995cbc | 1778 | |
601aeed3 VD |
1779 | /* Upstream ports flood frames with unknown unicast or multicast DA */ |
1780 | if (chip->info->ops->port_set_egress_floods) | |
1781 | return chip->info->ops->port_set_egress_floods(chip, port, | |
1782 | flood, flood); | |
ea698f4f | 1783 | |
601aeed3 | 1784 | return 0; |
ea698f4f VD |
1785 | } |
1786 | ||
6d91782f AL |
1787 | static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, |
1788 | bool on) | |
1789 | { | |
523a8904 VD |
1790 | if (chip->info->ops->serdes_power) |
1791 | return chip->info->ops->serdes_power(chip, port, on); | |
04aca993 | 1792 | |
523a8904 | 1793 | return 0; |
6d91782f AL |
1794 | } |
1795 | ||
fad09c73 | 1796 | static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) |
d827e88a | 1797 | { |
fad09c73 | 1798 | struct dsa_switch *ds = chip->ds; |
0e7b9925 | 1799 | int err; |
54d792f2 | 1800 | u16 reg; |
d827e88a | 1801 | |
d78343d2 VD |
1802 | /* MAC Forcing register: don't force link, speed, duplex or flow control |
1803 | * state to any particular values on physical ports, but force the CPU | |
1804 | * port and all DSA ports to their maximum bandwidth and full duplex. | |
1805 | */ | |
1806 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) | |
1807 | err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, | |
1808 | SPEED_MAX, DUPLEX_FULL, | |
1809 | PHY_INTERFACE_MODE_NA); | |
1810 | else | |
1811 | err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, | |
1812 | SPEED_UNFORCED, DUPLEX_UNFORCED, | |
1813 | PHY_INTERFACE_MODE_NA); | |
1814 | if (err) | |
1815 | return err; | |
54d792f2 AL |
1816 | |
1817 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, | |
1818 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN | |
1819 | * tunneling, determine priority by looking at 802.1p and IP | |
1820 | * priority fields (IP prio has precedence), and set STP state | |
1821 | * to Forwarding. | |
1822 | * | |
1823 | * If this is the CPU link, use DSA or EDSA tagging depending | |
1824 | * on which tagging mode was configured. | |
1825 | * | |
1826 | * If this is a link to another switch, use DSA tagging mode. | |
1827 | * | |
1828 | * If this is the upstream port for this switch, enable | |
1829 | * forwarding of unknown unicasts and multicasts. | |
1830 | */ | |
a89b433b VD |
1831 | reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | |
1832 | MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | | |
1833 | MV88E6XXX_PORT_CTL0_STATE_FORWARDING; | |
1834 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); | |
56995cbc AL |
1835 | if (err) |
1836 | return err; | |
6083ce71 | 1837 | |
601aeed3 | 1838 | err = mv88e6xxx_setup_port_mode(chip, port); |
56995cbc AL |
1839 | if (err) |
1840 | return err; | |
54d792f2 | 1841 | |
601aeed3 | 1842 | err = mv88e6xxx_setup_egress_floods(chip, port); |
4314557c VD |
1843 | if (err) |
1844 | return err; | |
1845 | ||
04aca993 AL |
1846 | /* Enable the SERDES interface for DSA and CPU ports. Normal |
1847 | * ports SERDES are enabled when the port is enabled, thus | |
1848 | * saving a bit of power. | |
13a7ebb3 | 1849 | */ |
04aca993 AL |
1850 | if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { |
1851 | err = mv88e6xxx_serdes_power(chip, port, true); | |
1852 | if (err) | |
1853 | return err; | |
1854 | } | |
13a7ebb3 | 1855 | |
8efdda4a | 1856 | /* Port Control 2: don't force a good FCS, set the maximum frame size to |
46fbe5e5 | 1857 | * 10240 bytes, disable 802.1q tags checking, don't discard tagged or |
8efdda4a VD |
1858 | * untagged frames on this port, do a destination address lookup on all |
1859 | * received packets as usual, disable ARP mirroring and don't send a | |
1860 | * copy of all transmitted/received frames on this port to the CPU. | |
54d792f2 | 1861 | */ |
a23b2961 AL |
1862 | err = mv88e6xxx_port_set_map_da(chip, port); |
1863 | if (err) | |
1864 | return err; | |
8efdda4a | 1865 | |
a23b2961 AL |
1866 | reg = 0; |
1867 | if (chip->info->ops->port_set_upstream_port) { | |
1868 | err = chip->info->ops->port_set_upstream_port( | |
1869 | chip, port, dsa_upstream_port(ds)); | |
0e7b9925 AL |
1870 | if (err) |
1871 | return err; | |
54d792f2 AL |
1872 | } |
1873 | ||
a23b2961 | 1874 | err = mv88e6xxx_port_set_8021q_mode(chip, port, |
81c6edb2 | 1875 | MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); |
a23b2961 AL |
1876 | if (err) |
1877 | return err; | |
1878 | ||
cd782656 VD |
1879 | if (chip->info->ops->port_set_jumbo_size) { |
1880 | err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); | |
5f436666 AL |
1881 | if (err) |
1882 | return err; | |
1883 | } | |
1884 | ||
54d792f2 AL |
1885 | /* Port Association Vector: when learning source addresses |
1886 | * of packets, add the address to the address database using | |
1887 | * a port bitmap that has only the bit for this port set and | |
1888 | * the other bits clear. | |
1889 | */ | |
4c7ea3c0 | 1890 | reg = 1 << port; |
996ecb82 VD |
1891 | /* Disable learning for CPU port */ |
1892 | if (dsa_is_cpu_port(ds, port)) | |
65fa4027 | 1893 | reg = 0; |
4c7ea3c0 | 1894 | |
2a4614e4 VD |
1895 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, |
1896 | reg); | |
0e7b9925 AL |
1897 | if (err) |
1898 | return err; | |
54d792f2 AL |
1899 | |
1900 | /* Egress rate control 2: disable egress rate control. */ | |
2cb8cb14 VD |
1901 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, |
1902 | 0x0000); | |
0e7b9925 AL |
1903 | if (err) |
1904 | return err; | |
54d792f2 | 1905 | |
0898432c VD |
1906 | if (chip->info->ops->port_pause_limit) { |
1907 | err = chip->info->ops->port_pause_limit(chip, port, 0, 0); | |
0e7b9925 AL |
1908 | if (err) |
1909 | return err; | |
b35d322a | 1910 | } |
54d792f2 | 1911 | |
c8c94891 VD |
1912 | if (chip->info->ops->port_disable_learn_limit) { |
1913 | err = chip->info->ops->port_disable_learn_limit(chip, port); | |
1914 | if (err) | |
1915 | return err; | |
1916 | } | |
1917 | ||
9dbfb4e1 VD |
1918 | if (chip->info->ops->port_disable_pri_override) { |
1919 | err = chip->info->ops->port_disable_pri_override(chip, port); | |
0e7b9925 AL |
1920 | if (err) |
1921 | return err; | |
ef0a7318 | 1922 | } |
2bbb33be | 1923 | |
ef0a7318 AL |
1924 | if (chip->info->ops->port_tag_remap) { |
1925 | err = chip->info->ops->port_tag_remap(chip, port); | |
0e7b9925 AL |
1926 | if (err) |
1927 | return err; | |
54d792f2 AL |
1928 | } |
1929 | ||
ef70b111 AL |
1930 | if (chip->info->ops->port_egress_rate_limiting) { |
1931 | err = chip->info->ops->port_egress_rate_limiting(chip, port); | |
0e7b9925 AL |
1932 | if (err) |
1933 | return err; | |
54d792f2 AL |
1934 | } |
1935 | ||
ea698f4f | 1936 | err = mv88e6xxx_setup_message_port(chip, port); |
0e7b9925 AL |
1937 | if (err) |
1938 | return err; | |
d827e88a | 1939 | |
207afda1 | 1940 | /* Port based VLAN map: give each port the same default address |
b7666efe VD |
1941 | * database, and allow bidirectional communication between the |
1942 | * CPU and DSA port(s), and the other ports. | |
d827e88a | 1943 | */ |
b4e48c50 | 1944 | err = mv88e6xxx_port_set_fid(chip, port, 0); |
0e7b9925 AL |
1945 | if (err) |
1946 | return err; | |
2db9ce1f | 1947 | |
240ea3ef | 1948 | err = mv88e6xxx_port_vlan_map(chip, port); |
0e7b9925 AL |
1949 | if (err) |
1950 | return err; | |
d827e88a GR |
1951 | |
1952 | /* Default VLAN ID and priority: don't set a default VLAN | |
1953 | * ID, and set the default packet priority to zero. | |
1954 | */ | |
b7929fb3 | 1955 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); |
dbde9e66 AL |
1956 | } |
1957 | ||
04aca993 AL |
1958 | static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, |
1959 | struct phy_device *phydev) | |
1960 | { | |
1961 | struct mv88e6xxx_chip *chip = ds->priv; | |
523a8904 | 1962 | int err; |
04aca993 AL |
1963 | |
1964 | mutex_lock(&chip->reg_lock); | |
523a8904 | 1965 | err = mv88e6xxx_serdes_power(chip, port, true); |
04aca993 AL |
1966 | mutex_unlock(&chip->reg_lock); |
1967 | ||
1968 | return err; | |
1969 | } | |
1970 | ||
1971 | static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port, | |
1972 | struct phy_device *phydev) | |
1973 | { | |
1974 | struct mv88e6xxx_chip *chip = ds->priv; | |
1975 | ||
1976 | mutex_lock(&chip->reg_lock); | |
523a8904 VD |
1977 | if (mv88e6xxx_serdes_power(chip, port, false)) |
1978 | dev_err(chip->dev, "failed to power off SERDES\n"); | |
04aca993 AL |
1979 | mutex_unlock(&chip->reg_lock); |
1980 | } | |
1981 | ||
2cfcd964 VD |
1982 | static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, |
1983 | unsigned int ageing_time) | |
1984 | { | |
04bed143 | 1985 | struct mv88e6xxx_chip *chip = ds->priv; |
2cfcd964 VD |
1986 | int err; |
1987 | ||
1988 | mutex_lock(&chip->reg_lock); | |
720c6343 | 1989 | err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); |
2cfcd964 VD |
1990 | mutex_unlock(&chip->reg_lock); |
1991 | ||
1992 | return err; | |
1993 | } | |
1994 | ||
9729934c | 1995 | static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) |
acdaffcc | 1996 | { |
fad09c73 | 1997 | struct dsa_switch *ds = chip->ds; |
b0745e87 | 1998 | u32 upstream_port = dsa_upstream_port(ds); |
552238b5 | 1999 | int err; |
54d792f2 | 2000 | |
fa8d1179 VD |
2001 | if (chip->info->ops->set_cpu_port) { |
2002 | err = chip->info->ops->set_cpu_port(chip, upstream_port); | |
33641994 AL |
2003 | if (err) |
2004 | return err; | |
2005 | } | |
2006 | ||
fa8d1179 VD |
2007 | if (chip->info->ops->set_egress_port) { |
2008 | err = chip->info->ops->set_egress_port(chip, upstream_port); | |
33641994 AL |
2009 | if (err) |
2010 | return err; | |
2011 | } | |
b0745e87 | 2012 | |
50484ff4 | 2013 | /* Disable remote management, and set the switch's DSA device number. */ |
a935c052 VD |
2014 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2, |
2015 | GLOBAL_CONTROL_2_MULTIPLE_CASCADE | | |
2016 | (ds->index & 0x1f)); | |
50484ff4 VD |
2017 | if (err) |
2018 | return err; | |
2019 | ||
54d792f2 | 2020 | /* Configure the IP ToS mapping registers. */ |
a935c052 | 2021 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000); |
48ace4ef | 2022 | if (err) |
08a01261 | 2023 | return err; |
a935c052 | 2024 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000); |
48ace4ef | 2025 | if (err) |
08a01261 | 2026 | return err; |
a935c052 | 2027 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555); |
48ace4ef | 2028 | if (err) |
08a01261 | 2029 | return err; |
a935c052 | 2030 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555); |
48ace4ef | 2031 | if (err) |
08a01261 | 2032 | return err; |
a935c052 | 2033 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa); |
48ace4ef | 2034 | if (err) |
08a01261 | 2035 | return err; |
a935c052 | 2036 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa); |
48ace4ef | 2037 | if (err) |
08a01261 | 2038 | return err; |
a935c052 | 2039 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff); |
48ace4ef | 2040 | if (err) |
08a01261 | 2041 | return err; |
a935c052 | 2042 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff); |
48ace4ef | 2043 | if (err) |
08a01261 | 2044 | return err; |
54d792f2 AL |
2045 | |
2046 | /* Configure the IEEE 802.1p priority mapping register. */ | |
a935c052 | 2047 | err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41); |
48ace4ef | 2048 | if (err) |
08a01261 | 2049 | return err; |
54d792f2 | 2050 | |
de227387 AL |
2051 | /* Initialize the statistics unit */ |
2052 | err = mv88e6xxx_stats_set_histogram(chip); | |
2053 | if (err) | |
2054 | return err; | |
2055 | ||
9729934c | 2056 | /* Clear the statistics counters for all ports */ |
a935c052 VD |
2057 | err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP, |
2058 | GLOBAL_STATS_OP_FLUSH_ALL); | |
9729934c VD |
2059 | if (err) |
2060 | return err; | |
2061 | ||
2062 | /* Wait for the flush to complete. */ | |
7f9ef3af | 2063 | err = mv88e6xxx_g1_stats_wait(chip); |
9729934c VD |
2064 | if (err) |
2065 | return err; | |
2066 | ||
2067 | return 0; | |
2068 | } | |
2069 | ||
f81ec90f | 2070 | static int mv88e6xxx_setup(struct dsa_switch *ds) |
08a01261 | 2071 | { |
04bed143 | 2072 | struct mv88e6xxx_chip *chip = ds->priv; |
08a01261 | 2073 | int err; |
a1a6a4d1 VD |
2074 | int i; |
2075 | ||
fad09c73 | 2076 | chip->ds = ds; |
a3c53be5 | 2077 | ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); |
08a01261 | 2078 | |
fad09c73 | 2079 | mutex_lock(&chip->reg_lock); |
08a01261 | 2080 | |
9729934c | 2081 | /* Setup Switch Port Registers */ |
370b4ffb | 2082 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { |
9729934c VD |
2083 | err = mv88e6xxx_setup_port(chip, i); |
2084 | if (err) | |
2085 | goto unlock; | |
2086 | } | |
2087 | ||
2088 | /* Setup Switch Global 1 Registers */ | |
2089 | err = mv88e6xxx_g1_setup(chip); | |
a1a6a4d1 VD |
2090 | if (err) |
2091 | goto unlock; | |
2092 | ||
9729934c VD |
2093 | /* Setup Switch Global 2 Registers */ |
2094 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) { | |
2095 | err = mv88e6xxx_g2_setup(chip); | |
a1a6a4d1 VD |
2096 | if (err) |
2097 | goto unlock; | |
2098 | } | |
08a01261 | 2099 | |
1b17aedf VD |
2100 | err = mv88e6xxx_phy_setup(chip); |
2101 | if (err) | |
2102 | goto unlock; | |
2103 | ||
b486d7c9 VD |
2104 | err = mv88e6xxx_vtu_setup(chip); |
2105 | if (err) | |
2106 | goto unlock; | |
2107 | ||
81228996 VD |
2108 | err = mv88e6xxx_pvt_setup(chip); |
2109 | if (err) | |
2110 | goto unlock; | |
2111 | ||
a2ac29d2 VD |
2112 | err = mv88e6xxx_atu_setup(chip); |
2113 | if (err) | |
2114 | goto unlock; | |
2115 | ||
6e55f698 AL |
2116 | /* Some generations have the configuration of sending reserved |
2117 | * management frames to the CPU in global2, others in | |
2118 | * global1. Hence it does not fit the two setup functions | |
2119 | * above. | |
2120 | */ | |
2121 | if (chip->info->ops->mgmt_rsvd2cpu) { | |
2122 | err = chip->info->ops->mgmt_rsvd2cpu(chip); | |
2123 | if (err) | |
2124 | goto unlock; | |
2125 | } | |
2126 | ||
6b17e864 | 2127 | unlock: |
fad09c73 | 2128 | mutex_unlock(&chip->reg_lock); |
db687a56 | 2129 | |
48ace4ef | 2130 | return err; |
54d792f2 AL |
2131 | } |
2132 | ||
3b4caa1b VD |
2133 | static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr) |
2134 | { | |
04bed143 | 2135 | struct mv88e6xxx_chip *chip = ds->priv; |
3b4caa1b VD |
2136 | int err; |
2137 | ||
b073d4e2 VD |
2138 | if (!chip->info->ops->set_switch_mac) |
2139 | return -EOPNOTSUPP; | |
3b4caa1b | 2140 | |
b073d4e2 VD |
2141 | mutex_lock(&chip->reg_lock); |
2142 | err = chip->info->ops->set_switch_mac(chip, addr); | |
3b4caa1b VD |
2143 | mutex_unlock(&chip->reg_lock); |
2144 | ||
2145 | return err; | |
2146 | } | |
2147 | ||
e57e5e77 | 2148 | static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) |
fd3a0ee4 | 2149 | { |
0dd12d54 AL |
2150 | struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; |
2151 | struct mv88e6xxx_chip *chip = mdio_bus->chip; | |
e57e5e77 VD |
2152 | u16 val; |
2153 | int err; | |
fd3a0ee4 | 2154 | |
ee26a228 AL |
2155 | if (!chip->info->ops->phy_read) |
2156 | return -EOPNOTSUPP; | |
2157 | ||
fad09c73 | 2158 | mutex_lock(&chip->reg_lock); |
ee26a228 | 2159 | err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); |
fad09c73 | 2160 | mutex_unlock(&chip->reg_lock); |
e57e5e77 | 2161 | |
da9f3301 AL |
2162 | if (reg == MII_PHYSID2) { |
2163 | /* Some internal PHYS don't have a model number. Use | |
2164 | * the mv88e6390 family model number instead. | |
2165 | */ | |
2166 | if (!(val & 0x3f0)) | |
107fcc10 | 2167 | val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; |
da9f3301 AL |
2168 | } |
2169 | ||
e57e5e77 | 2170 | return err ? err : val; |
fd3a0ee4 AL |
2171 | } |
2172 | ||
e57e5e77 | 2173 | static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) |
fd3a0ee4 | 2174 | { |
0dd12d54 AL |
2175 | struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; |
2176 | struct mv88e6xxx_chip *chip = mdio_bus->chip; | |
e57e5e77 | 2177 | int err; |
fd3a0ee4 | 2178 | |
ee26a228 AL |
2179 | if (!chip->info->ops->phy_write) |
2180 | return -EOPNOTSUPP; | |
2181 | ||
fad09c73 | 2182 | mutex_lock(&chip->reg_lock); |
ee26a228 | 2183 | err = chip->info->ops->phy_write(chip, bus, phy, reg, val); |
fad09c73 | 2184 | mutex_unlock(&chip->reg_lock); |
e57e5e77 VD |
2185 | |
2186 | return err; | |
fd3a0ee4 AL |
2187 | } |
2188 | ||
fad09c73 | 2189 | static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, |
a3c53be5 AL |
2190 | struct device_node *np, |
2191 | bool external) | |
b516d453 AL |
2192 | { |
2193 | static int index; | |
0dd12d54 | 2194 | struct mv88e6xxx_mdio_bus *mdio_bus; |
b516d453 AL |
2195 | struct mii_bus *bus; |
2196 | int err; | |
2197 | ||
0dd12d54 | 2198 | bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); |
b516d453 AL |
2199 | if (!bus) |
2200 | return -ENOMEM; | |
2201 | ||
0dd12d54 | 2202 | mdio_bus = bus->priv; |
a3c53be5 | 2203 | mdio_bus->bus = bus; |
0dd12d54 | 2204 | mdio_bus->chip = chip; |
a3c53be5 AL |
2205 | INIT_LIST_HEAD(&mdio_bus->list); |
2206 | mdio_bus->external = external; | |
0dd12d54 | 2207 | |
b516d453 AL |
2208 | if (np) { |
2209 | bus->name = np->full_name; | |
2210 | snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name); | |
2211 | } else { | |
2212 | bus->name = "mv88e6xxx SMI"; | |
2213 | snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); | |
2214 | } | |
2215 | ||
2216 | bus->read = mv88e6xxx_mdio_read; | |
2217 | bus->write = mv88e6xxx_mdio_write; | |
fad09c73 | 2218 | bus->parent = chip->dev; |
b516d453 | 2219 | |
a3c53be5 AL |
2220 | if (np) |
2221 | err = of_mdiobus_register(bus, np); | |
b516d453 AL |
2222 | else |
2223 | err = mdiobus_register(bus); | |
2224 | if (err) { | |
fad09c73 | 2225 | dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); |
a3c53be5 | 2226 | return err; |
b516d453 | 2227 | } |
a3c53be5 AL |
2228 | |
2229 | if (external) | |
2230 | list_add_tail(&mdio_bus->list, &chip->mdios); | |
2231 | else | |
2232 | list_add(&mdio_bus->list, &chip->mdios); | |
b516d453 AL |
2233 | |
2234 | return 0; | |
a3c53be5 | 2235 | } |
b516d453 | 2236 | |
a3c53be5 AL |
2237 | static const struct of_device_id mv88e6xxx_mdio_external_match[] = { |
2238 | { .compatible = "marvell,mv88e6xxx-mdio-external", | |
2239 | .data = (void *)true }, | |
2240 | { }, | |
2241 | }; | |
b516d453 | 2242 | |
a3c53be5 AL |
2243 | static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, |
2244 | struct device_node *np) | |
2245 | { | |
2246 | const struct of_device_id *match; | |
2247 | struct device_node *child; | |
2248 | int err; | |
2249 | ||
2250 | /* Always register one mdio bus for the internal/default mdio | |
2251 | * bus. This maybe represented in the device tree, but is | |
2252 | * optional. | |
2253 | */ | |
2254 | child = of_get_child_by_name(np, "mdio"); | |
2255 | err = mv88e6xxx_mdio_register(chip, child, false); | |
2256 | if (err) | |
2257 | return err; | |
2258 | ||
2259 | /* Walk the device tree, and see if there are any other nodes | |
2260 | * which say they are compatible with the external mdio | |
2261 | * bus. | |
2262 | */ | |
2263 | for_each_available_child_of_node(np, child) { | |
2264 | match = of_match_node(mv88e6xxx_mdio_external_match, child); | |
2265 | if (match) { | |
2266 | err = mv88e6xxx_mdio_register(chip, child, true); | |
2267 | if (err) | |
2268 | return err; | |
2269 | } | |
2270 | } | |
2271 | ||
2272 | return 0; | |
b516d453 AL |
2273 | } |
2274 | ||
a3c53be5 | 2275 | static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) |
b516d453 AL |
2276 | |
2277 | { | |
a3c53be5 AL |
2278 | struct mv88e6xxx_mdio_bus *mdio_bus; |
2279 | struct mii_bus *bus; | |
b516d453 | 2280 | |
a3c53be5 AL |
2281 | list_for_each_entry(mdio_bus, &chip->mdios, list) { |
2282 | bus = mdio_bus->bus; | |
b516d453 | 2283 | |
a3c53be5 AL |
2284 | mdiobus_unregister(bus); |
2285 | } | |
b516d453 AL |
2286 | } |
2287 | ||
855b1932 VD |
2288 | static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) |
2289 | { | |
04bed143 | 2290 | struct mv88e6xxx_chip *chip = ds->priv; |
855b1932 VD |
2291 | |
2292 | return chip->eeprom_len; | |
2293 | } | |
2294 | ||
855b1932 VD |
2295 | static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, |
2296 | struct ethtool_eeprom *eeprom, u8 *data) | |
2297 | { | |
04bed143 | 2298 | struct mv88e6xxx_chip *chip = ds->priv; |
855b1932 VD |
2299 | int err; |
2300 | ||
ee4dc2e7 VD |
2301 | if (!chip->info->ops->get_eeprom) |
2302 | return -EOPNOTSUPP; | |
855b1932 | 2303 | |
ee4dc2e7 VD |
2304 | mutex_lock(&chip->reg_lock); |
2305 | err = chip->info->ops->get_eeprom(chip, eeprom, data); | |
855b1932 VD |
2306 | mutex_unlock(&chip->reg_lock); |
2307 | ||
2308 | if (err) | |
2309 | return err; | |
2310 | ||
2311 | eeprom->magic = 0xc3ec4951; | |
2312 | ||
2313 | return 0; | |
2314 | } | |
2315 | ||
855b1932 VD |
2316 | static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, |
2317 | struct ethtool_eeprom *eeprom, u8 *data) | |
2318 | { | |
04bed143 | 2319 | struct mv88e6xxx_chip *chip = ds->priv; |
855b1932 VD |
2320 | int err; |
2321 | ||
ee4dc2e7 VD |
2322 | if (!chip->info->ops->set_eeprom) |
2323 | return -EOPNOTSUPP; | |
2324 | ||
855b1932 VD |
2325 | if (eeprom->magic != 0xc3ec4951) |
2326 | return -EINVAL; | |
2327 | ||
2328 | mutex_lock(&chip->reg_lock); | |
ee4dc2e7 | 2329 | err = chip->info->ops->set_eeprom(chip, eeprom, data); |
855b1932 VD |
2330 | mutex_unlock(&chip->reg_lock); |
2331 | ||
2332 | return err; | |
2333 | } | |
2334 | ||
b3469dd8 | 2335 | static const struct mv88e6xxx_ops mv88e6085_ops = { |
4b325d8c | 2336 | /* MV88E6XXX_FAMILY_6097 */ |
b073d4e2 | 2337 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
7e20cfb5 VD |
2338 | .phy_read = mv88e6185_phy_ppu_read, |
2339 | .phy_write = mv88e6185_phy_ppu_write, | |
08ef7f10 | 2340 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2341 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 2342 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 2343 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2344 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2345 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2346 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
ef70b111 | 2347 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2348 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 2349 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2350 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 2351 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
dfafe449 AL |
2352 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2353 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2354 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2355 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2356 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2357 | .watchdog_ops = &mv88e6097_watchdog_ops, |
6e55f698 | 2358 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
a199d8b6 VD |
2359 | .ppu_enable = mv88e6185_g1_ppu_enable, |
2360 | .ppu_disable = mv88e6185_g1_ppu_disable, | |
17e708ba | 2361 | .reset = mv88e6185_g1_reset, |
f1394b78 | 2362 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2363 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
b3469dd8 VD |
2364 | }; |
2365 | ||
2366 | static const struct mv88e6xxx_ops mv88e6095_ops = { | |
4b325d8c | 2367 | /* MV88E6XXX_FAMILY_6095 */ |
b073d4e2 | 2368 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
7e20cfb5 VD |
2369 | .phy_read = mv88e6185_phy_ppu_read, |
2370 | .phy_write = mv88e6185_phy_ppu_write, | |
08ef7f10 | 2371 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2372 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 2373 | .port_set_speed = mv88e6185_port_set_speed, |
56995cbc | 2374 | .port_set_frame_mode = mv88e6085_port_set_frame_mode, |
601aeed3 | 2375 | .port_set_egress_floods = mv88e6185_port_set_egress_floods, |
a23b2961 | 2376 | .port_set_upstream_port = mv88e6095_port_set_upstream_port, |
a605a0fe | 2377 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
dfafe449 AL |
2378 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2379 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2380 | .stats_get_stats = mv88e6095_stats_get_stats, |
6e55f698 | 2381 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
a199d8b6 VD |
2382 | .ppu_enable = mv88e6185_g1_ppu_enable, |
2383 | .ppu_disable = mv88e6185_g1_ppu_disable, | |
17e708ba | 2384 | .reset = mv88e6185_g1_reset, |
f1394b78 | 2385 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
0ad5daf6 | 2386 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
b3469dd8 VD |
2387 | }; |
2388 | ||
7d381a02 | 2389 | static const struct mv88e6xxx_ops mv88e6097_ops = { |
15da3cc8 | 2390 | /* MV88E6XXX_FAMILY_6097 */ |
7d381a02 SE |
2391 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
2392 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
2393 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
2394 | .port_set_link = mv88e6xxx_port_set_link, | |
2395 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
2396 | .port_set_speed = mv88e6185_port_set_speed, | |
ef0a7318 | 2397 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2398 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2399 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2400 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 2401 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 2402 | .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, |
0898432c | 2403 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 2404 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2405 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
7d381a02 SE |
2406 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
2407 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, | |
2408 | .stats_get_strings = mv88e6095_stats_get_strings, | |
2409 | .stats_get_stats = mv88e6095_stats_get_stats, | |
fa8d1179 VD |
2410 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2411 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
91eaa475 | 2412 | .watchdog_ops = &mv88e6097_watchdog_ops, |
6e55f698 | 2413 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 2414 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2415 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2416 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
7d381a02 SE |
2417 | }; |
2418 | ||
b3469dd8 | 2419 | static const struct mv88e6xxx_ops mv88e6123_ops = { |
4b325d8c | 2420 | /* MV88E6XXX_FAMILY_6165 */ |
b073d4e2 | 2421 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
ec8378bb AL |
2422 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
2423 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 2424 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2425 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 2426 | .port_set_speed = mv88e6185_port_set_speed, |
56995cbc | 2427 | .port_set_frame_mode = mv88e6085_port_set_frame_mode, |
601aeed3 | 2428 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
c8c94891 | 2429 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2430 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
0ac64c39 | 2431 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
2432 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2433 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2434 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2435 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2436 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2437 | .watchdog_ops = &mv88e6097_watchdog_ops, |
6e55f698 | 2438 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 2439 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2440 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2441 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
b3469dd8 VD |
2442 | }; |
2443 | ||
2444 | static const struct mv88e6xxx_ops mv88e6131_ops = { | |
4b325d8c | 2445 | /* MV88E6XXX_FAMILY_6185 */ |
b073d4e2 | 2446 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
7e20cfb5 VD |
2447 | .phy_read = mv88e6185_phy_ppu_read, |
2448 | .phy_write = mv88e6185_phy_ppu_write, | |
08ef7f10 | 2449 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2450 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 2451 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 2452 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2453 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2454 | .port_set_egress_floods = mv88e6185_port_set_egress_floods, |
56995cbc | 2455 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
a23b2961 | 2456 | .port_set_upstream_port = mv88e6095_port_set_upstream_port, |
cd782656 | 2457 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 2458 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2459 | .port_pause_limit = mv88e6097_port_pause_limit, |
a605a0fe | 2460 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
dfafe449 AL |
2461 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2462 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2463 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2464 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2465 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2466 | .watchdog_ops = &mv88e6097_watchdog_ops, |
6e55f698 | 2467 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
a199d8b6 VD |
2468 | .ppu_enable = mv88e6185_g1_ppu_enable, |
2469 | .ppu_disable = mv88e6185_g1_ppu_disable, | |
17e708ba | 2470 | .reset = mv88e6185_g1_reset, |
f1394b78 | 2471 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
0ad5daf6 | 2472 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
b3469dd8 VD |
2473 | }; |
2474 | ||
990e27b0 VD |
2475 | static const struct mv88e6xxx_ops mv88e6141_ops = { |
2476 | /* MV88E6XXX_FAMILY_6341 */ | |
2477 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, | |
2478 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
2479 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | |
2480 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
2481 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
2482 | .port_set_link = mv88e6xxx_port_set_link, | |
2483 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
2484 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
2485 | .port_set_speed = mv88e6390_port_set_speed, | |
2486 | .port_tag_remap = mv88e6095_port_tag_remap, | |
2487 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, | |
2488 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, | |
2489 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
cd782656 | 2490 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
990e27b0 | 2491 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2492 | .port_pause_limit = mv88e6097_port_pause_limit, |
990e27b0 VD |
2493 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
2494 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, | |
2495 | .stats_snapshot = mv88e6390_g1_stats_snapshot, | |
2496 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, | |
2497 | .stats_get_strings = mv88e6320_stats_get_strings, | |
2498 | .stats_get_stats = mv88e6390_stats_get_stats, | |
fa8d1179 VD |
2499 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
2500 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
990e27b0 VD |
2501 | .watchdog_ops = &mv88e6390_watchdog_ops, |
2502 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, | |
2503 | .reset = mv88e6352_g1_reset, | |
f1394b78 | 2504 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2505 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
990e27b0 VD |
2506 | }; |
2507 | ||
b3469dd8 | 2508 | static const struct mv88e6xxx_ops mv88e6161_ops = { |
4b325d8c | 2509 | /* MV88E6XXX_FAMILY_6165 */ |
b073d4e2 | 2510 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
ec8378bb AL |
2511 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
2512 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 2513 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2514 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 2515 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 2516 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2517 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2518 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2519 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 2520 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 2521 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2522 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 2523 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2524 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
0ac64c39 | 2525 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
2526 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2527 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2528 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2529 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2530 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2531 | .watchdog_ops = &mv88e6097_watchdog_ops, |
6e55f698 | 2532 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 2533 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2534 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2535 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
b3469dd8 VD |
2536 | }; |
2537 | ||
2538 | static const struct mv88e6xxx_ops mv88e6165_ops = { | |
4b325d8c | 2539 | /* MV88E6XXX_FAMILY_6165 */ |
b073d4e2 | 2540 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
efb3e74d AL |
2541 | .phy_read = mv88e6165_phy_read, |
2542 | .phy_write = mv88e6165_phy_write, | |
08ef7f10 | 2543 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2544 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 2545 | .port_set_speed = mv88e6185_port_set_speed, |
c8c94891 | 2546 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2547 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 2548 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
dfafe449 AL |
2549 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2550 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2551 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2552 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2553 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2554 | .watchdog_ops = &mv88e6097_watchdog_ops, |
6e55f698 | 2555 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 2556 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2557 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2558 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
b3469dd8 VD |
2559 | }; |
2560 | ||
2561 | static const struct mv88e6xxx_ops mv88e6171_ops = { | |
4b325d8c | 2562 | /* MV88E6XXX_FAMILY_6351 */ |
b073d4e2 | 2563 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
2564 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
2565 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 2566 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2567 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
94d66ae6 | 2568 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 2569 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 2570 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2571 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2572 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2573 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 2574 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 2575 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2576 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 2577 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2578 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 2579 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
2580 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2581 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2582 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2583 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2584 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2585 | .watchdog_ops = &mv88e6097_watchdog_ops, |
6e55f698 | 2586 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 2587 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2588 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2589 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
b3469dd8 VD |
2590 | }; |
2591 | ||
2592 | static const struct mv88e6xxx_ops mv88e6172_ops = { | |
4b325d8c | 2593 | /* MV88E6XXX_FAMILY_6352 */ |
ee4dc2e7 VD |
2594 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
2595 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 2596 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
2597 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
2598 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 2599 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2600 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 2601 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 2602 | .port_set_speed = mv88e6352_port_set_speed, |
ef0a7318 | 2603 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2604 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2605 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2606 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 2607 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 2608 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2609 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 2610 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2611 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 2612 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
2613 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2614 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2615 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2616 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2617 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2618 | .watchdog_ops = &mv88e6097_watchdog_ops, |
6e55f698 | 2619 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 2620 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2621 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2622 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
6d91782f | 2623 | .serdes_power = mv88e6352_serdes_power, |
b3469dd8 VD |
2624 | }; |
2625 | ||
2626 | static const struct mv88e6xxx_ops mv88e6175_ops = { | |
4b325d8c | 2627 | /* MV88E6XXX_FAMILY_6351 */ |
b073d4e2 | 2628 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
2629 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
2630 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 2631 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2632 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
94d66ae6 | 2633 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 2634 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 2635 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2636 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2637 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2638 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 2639 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 2640 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2641 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 2642 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2643 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 2644 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
2645 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2646 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2647 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2648 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2649 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2650 | .watchdog_ops = &mv88e6097_watchdog_ops, |
6e55f698 | 2651 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 2652 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2653 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2654 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
b3469dd8 VD |
2655 | }; |
2656 | ||
2657 | static const struct mv88e6xxx_ops mv88e6176_ops = { | |
4b325d8c | 2658 | /* MV88E6XXX_FAMILY_6352 */ |
ee4dc2e7 VD |
2659 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
2660 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 2661 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
2662 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
2663 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 2664 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2665 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 2666 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 2667 | .port_set_speed = mv88e6352_port_set_speed, |
ef0a7318 | 2668 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2669 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2670 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2671 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 2672 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 2673 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2674 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 2675 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2676 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 2677 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
2678 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2679 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2680 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2681 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2682 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2683 | .watchdog_ops = &mv88e6097_watchdog_ops, |
6e55f698 | 2684 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 2685 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2686 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2687 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
6d91782f | 2688 | .serdes_power = mv88e6352_serdes_power, |
b3469dd8 VD |
2689 | }; |
2690 | ||
2691 | static const struct mv88e6xxx_ops mv88e6185_ops = { | |
4b325d8c | 2692 | /* MV88E6XXX_FAMILY_6185 */ |
b073d4e2 | 2693 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
7e20cfb5 VD |
2694 | .phy_read = mv88e6185_phy_ppu_read, |
2695 | .phy_write = mv88e6185_phy_ppu_write, | |
08ef7f10 | 2696 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2697 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 2698 | .port_set_speed = mv88e6185_port_set_speed, |
56995cbc | 2699 | .port_set_frame_mode = mv88e6085_port_set_frame_mode, |
601aeed3 | 2700 | .port_set_egress_floods = mv88e6185_port_set_egress_floods, |
ef70b111 | 2701 | .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, |
a23b2961 | 2702 | .port_set_upstream_port = mv88e6095_port_set_upstream_port, |
a605a0fe | 2703 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
dfafe449 AL |
2704 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2705 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2706 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2707 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2708 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2709 | .watchdog_ops = &mv88e6097_watchdog_ops, |
6e55f698 | 2710 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
a199d8b6 VD |
2711 | .ppu_enable = mv88e6185_g1_ppu_enable, |
2712 | .ppu_disable = mv88e6185_g1_ppu_disable, | |
17e708ba | 2713 | .reset = mv88e6185_g1_reset, |
f1394b78 | 2714 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
0ad5daf6 | 2715 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
b3469dd8 VD |
2716 | }; |
2717 | ||
1a3b39ec | 2718 | static const struct mv88e6xxx_ops mv88e6190_ops = { |
4b325d8c | 2719 | /* MV88E6XXX_FAMILY_6390 */ |
98fc3c6f VD |
2720 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
2721 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
1a3b39ec AL |
2722 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
2723 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
2724 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
2725 | .port_set_link = mv88e6xxx_port_set_link, | |
2726 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
2727 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
2728 | .port_set_speed = mv88e6390_port_set_speed, | |
ef0a7318 | 2729 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc | 2730 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2731 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2732 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
0898432c | 2733 | .port_pause_limit = mv88e6390_port_pause_limit, |
c8c94891 | 2734 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2735 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
79523473 | 2736 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 2737 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
2738 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
2739 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 2740 | .stats_get_stats = mv88e6390_stats_get_stats, |
fa8d1179 VD |
2741 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
2742 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
61303736 | 2743 | .watchdog_ops = &mv88e6390_watchdog_ops, |
6e55f698 | 2744 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
17e708ba | 2745 | .reset = mv88e6352_g1_reset, |
931d1822 VD |
2746 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
2747 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, | |
6335e9f2 | 2748 | .serdes_power = mv88e6390_serdes_power, |
1a3b39ec AL |
2749 | }; |
2750 | ||
2751 | static const struct mv88e6xxx_ops mv88e6190x_ops = { | |
4b325d8c | 2752 | /* MV88E6XXX_FAMILY_6390 */ |
98fc3c6f VD |
2753 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
2754 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
1a3b39ec AL |
2755 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
2756 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
2757 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
2758 | .port_set_link = mv88e6xxx_port_set_link, | |
2759 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
2760 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
2761 | .port_set_speed = mv88e6390x_port_set_speed, | |
ef0a7318 | 2762 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc | 2763 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2764 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2765 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
0898432c | 2766 | .port_pause_limit = mv88e6390_port_pause_limit, |
c8c94891 | 2767 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2768 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
79523473 | 2769 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 2770 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
2771 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
2772 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 2773 | .stats_get_stats = mv88e6390_stats_get_stats, |
fa8d1179 VD |
2774 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
2775 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
61303736 | 2776 | .watchdog_ops = &mv88e6390_watchdog_ops, |
6e55f698 | 2777 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
17e708ba | 2778 | .reset = mv88e6352_g1_reset, |
931d1822 VD |
2779 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
2780 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, | |
6335e9f2 | 2781 | .serdes_power = mv88e6390_serdes_power, |
1a3b39ec AL |
2782 | }; |
2783 | ||
2784 | static const struct mv88e6xxx_ops mv88e6191_ops = { | |
4b325d8c | 2785 | /* MV88E6XXX_FAMILY_6390 */ |
98fc3c6f VD |
2786 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
2787 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
1a3b39ec AL |
2788 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
2789 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
2790 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
2791 | .port_set_link = mv88e6xxx_port_set_link, | |
2792 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
2793 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
2794 | .port_set_speed = mv88e6390_port_set_speed, | |
ef0a7318 | 2795 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc | 2796 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2797 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2798 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
0898432c | 2799 | .port_pause_limit = mv88e6390_port_pause_limit, |
c8c94891 | 2800 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2801 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
79523473 | 2802 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 2803 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
2804 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
2805 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 2806 | .stats_get_stats = mv88e6390_stats_get_stats, |
fa8d1179 VD |
2807 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
2808 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
61303736 | 2809 | .watchdog_ops = &mv88e6390_watchdog_ops, |
6e55f698 | 2810 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
17e708ba | 2811 | .reset = mv88e6352_g1_reset, |
931d1822 VD |
2812 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
2813 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, | |
6335e9f2 | 2814 | .serdes_power = mv88e6390_serdes_power, |
1a3b39ec AL |
2815 | }; |
2816 | ||
b3469dd8 | 2817 | static const struct mv88e6xxx_ops mv88e6240_ops = { |
4b325d8c | 2818 | /* MV88E6XXX_FAMILY_6352 */ |
ee4dc2e7 VD |
2819 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
2820 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 2821 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
2822 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
2823 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 2824 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2825 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 2826 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 2827 | .port_set_speed = mv88e6352_port_set_speed, |
ef0a7318 | 2828 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2829 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2830 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2831 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 2832 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 2833 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2834 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 2835 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2836 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 2837 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
2838 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2839 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2840 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2841 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2842 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2843 | .watchdog_ops = &mv88e6097_watchdog_ops, |
6e55f698 | 2844 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 2845 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2846 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2847 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
6d91782f | 2848 | .serdes_power = mv88e6352_serdes_power, |
b3469dd8 VD |
2849 | }; |
2850 | ||
1a3b39ec | 2851 | static const struct mv88e6xxx_ops mv88e6290_ops = { |
4b325d8c | 2852 | /* MV88E6XXX_FAMILY_6390 */ |
98fc3c6f VD |
2853 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
2854 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
1a3b39ec AL |
2855 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
2856 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
2857 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
2858 | .port_set_link = mv88e6xxx_port_set_link, | |
2859 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
2860 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
2861 | .port_set_speed = mv88e6390_port_set_speed, | |
ef0a7318 | 2862 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc | 2863 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2864 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2865 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
0898432c | 2866 | .port_pause_limit = mv88e6390_port_pause_limit, |
f39908d3 | 2867 | .port_set_cmode = mv88e6390x_port_set_cmode, |
c8c94891 | 2868 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2869 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
79523473 | 2870 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 2871 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
2872 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
2873 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 2874 | .stats_get_stats = mv88e6390_stats_get_stats, |
fa8d1179 VD |
2875 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
2876 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
61303736 | 2877 | .watchdog_ops = &mv88e6390_watchdog_ops, |
6e55f698 | 2878 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
17e708ba | 2879 | .reset = mv88e6352_g1_reset, |
931d1822 VD |
2880 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
2881 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, | |
6335e9f2 | 2882 | .serdes_power = mv88e6390_serdes_power, |
1a3b39ec AL |
2883 | }; |
2884 | ||
b3469dd8 | 2885 | static const struct mv88e6xxx_ops mv88e6320_ops = { |
4b325d8c | 2886 | /* MV88E6XXX_FAMILY_6320 */ |
ee4dc2e7 VD |
2887 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
2888 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 2889 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
2890 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
2891 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 2892 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2893 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 2894 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 2895 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2896 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2897 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2898 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 2899 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 2900 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2901 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 2902 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2903 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 2904 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
2905 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
2906 | .stats_get_strings = mv88e6320_stats_get_strings, | |
052f947f | 2907 | .stats_get_stats = mv88e6320_stats_get_stats, |
fa8d1179 VD |
2908 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2909 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
6e55f698 | 2910 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 2911 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2912 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
0ad5daf6 | 2913 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
b3469dd8 VD |
2914 | }; |
2915 | ||
2916 | static const struct mv88e6xxx_ops mv88e6321_ops = { | |
4b325d8c | 2917 | /* MV88E6XXX_FAMILY_6321 */ |
ee4dc2e7 VD |
2918 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
2919 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 2920 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
2921 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
2922 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 2923 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2924 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 2925 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 2926 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2927 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2928 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2929 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 2930 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 2931 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2932 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 2933 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2934 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 2935 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
2936 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
2937 | .stats_get_strings = mv88e6320_stats_get_strings, | |
052f947f | 2938 | .stats_get_stats = mv88e6320_stats_get_stats, |
fa8d1179 VD |
2939 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2940 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
17e708ba | 2941 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2942 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
0ad5daf6 | 2943 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
b3469dd8 VD |
2944 | }; |
2945 | ||
16e329ae VD |
2946 | static const struct mv88e6xxx_ops mv88e6341_ops = { |
2947 | /* MV88E6XXX_FAMILY_6341 */ | |
2948 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, | |
2949 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
2950 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | |
2951 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
2952 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
2953 | .port_set_link = mv88e6xxx_port_set_link, | |
2954 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
2955 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
2956 | .port_set_speed = mv88e6390_port_set_speed, | |
2957 | .port_tag_remap = mv88e6095_port_tag_remap, | |
2958 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, | |
2959 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, | |
2960 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
cd782656 | 2961 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
16e329ae | 2962 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2963 | .port_pause_limit = mv88e6097_port_pause_limit, |
16e329ae VD |
2964 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
2965 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, | |
2966 | .stats_snapshot = mv88e6390_g1_stats_snapshot, | |
2967 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, | |
2968 | .stats_get_strings = mv88e6320_stats_get_strings, | |
2969 | .stats_get_stats = mv88e6390_stats_get_stats, | |
fa8d1179 VD |
2970 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
2971 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
16e329ae VD |
2972 | .watchdog_ops = &mv88e6390_watchdog_ops, |
2973 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, | |
2974 | .reset = mv88e6352_g1_reset, | |
f1394b78 | 2975 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2976 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
16e329ae VD |
2977 | }; |
2978 | ||
b3469dd8 | 2979 | static const struct mv88e6xxx_ops mv88e6350_ops = { |
4b325d8c | 2980 | /* MV88E6XXX_FAMILY_6351 */ |
b073d4e2 | 2981 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
2982 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
2983 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 2984 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2985 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
94d66ae6 | 2986 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 2987 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 2988 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2989 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2990 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2991 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 2992 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 2993 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2994 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 2995 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2996 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 2997 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
2998 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2999 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3000 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
3001 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
3002 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 3003 | .watchdog_ops = &mv88e6097_watchdog_ops, |
6e55f698 | 3004 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3005 | .reset = mv88e6352_g1_reset, |
f1394b78 | 3006 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 3007 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
b3469dd8 VD |
3008 | }; |
3009 | ||
3010 | static const struct mv88e6xxx_ops mv88e6351_ops = { | |
4b325d8c | 3011 | /* MV88E6XXX_FAMILY_6351 */ |
b073d4e2 | 3012 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3013 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3014 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3015 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3016 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
94d66ae6 | 3017 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3018 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 3019 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 3020 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 3021 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 3022 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 3023 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 3024 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 3025 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 3026 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 3027 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 3028 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
3029 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3030 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3031 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
3032 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
3033 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 3034 | .watchdog_ops = &mv88e6097_watchdog_ops, |
6e55f698 | 3035 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3036 | .reset = mv88e6352_g1_reset, |
f1394b78 | 3037 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 3038 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
b3469dd8 VD |
3039 | }; |
3040 | ||
3041 | static const struct mv88e6xxx_ops mv88e6352_ops = { | |
4b325d8c | 3042 | /* MV88E6XXX_FAMILY_6352 */ |
ee4dc2e7 VD |
3043 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3044 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3045 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3046 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3047 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3048 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3049 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 3050 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3051 | .port_set_speed = mv88e6352_port_set_speed, |
ef0a7318 | 3052 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 3053 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 3054 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 3055 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 3056 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 3057 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 3058 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 3059 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 3060 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 3061 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
dfafe449 AL |
3062 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3063 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3064 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
3065 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
3066 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 3067 | .watchdog_ops = &mv88e6097_watchdog_ops, |
6e55f698 | 3068 | .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, |
17e708ba | 3069 | .reset = mv88e6352_g1_reset, |
f1394b78 | 3070 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 3071 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
6d91782f | 3072 | .serdes_power = mv88e6352_serdes_power, |
b3469dd8 VD |
3073 | }; |
3074 | ||
1a3b39ec | 3075 | static const struct mv88e6xxx_ops mv88e6390_ops = { |
4b325d8c | 3076 | /* MV88E6XXX_FAMILY_6390 */ |
98fc3c6f VD |
3077 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
3078 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
1a3b39ec AL |
3079 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3080 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3081 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3082 | .port_set_link = mv88e6xxx_port_set_link, | |
3083 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3084 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
3085 | .port_set_speed = mv88e6390_port_set_speed, | |
ef0a7318 | 3086 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc | 3087 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 3088 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 3089 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 3090 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 3091 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 3092 | .port_pause_limit = mv88e6390_port_pause_limit, |
f39908d3 | 3093 | .port_set_cmode = mv88e6390x_port_set_cmode, |
c8c94891 | 3094 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 3095 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
79523473 | 3096 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 3097 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
3098 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
3099 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 3100 | .stats_get_stats = mv88e6390_stats_get_stats, |
fa8d1179 VD |
3101 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
3102 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
61303736 | 3103 | .watchdog_ops = &mv88e6390_watchdog_ops, |
6e55f698 | 3104 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
17e708ba | 3105 | .reset = mv88e6352_g1_reset, |
931d1822 VD |
3106 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
3107 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, | |
6335e9f2 | 3108 | .serdes_power = mv88e6390_serdes_power, |
1a3b39ec AL |
3109 | }; |
3110 | ||
3111 | static const struct mv88e6xxx_ops mv88e6390x_ops = { | |
4b325d8c | 3112 | /* MV88E6XXX_FAMILY_6390 */ |
98fc3c6f VD |
3113 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
3114 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
1a3b39ec AL |
3115 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3116 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3117 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3118 | .port_set_link = mv88e6xxx_port_set_link, | |
3119 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3120 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
3121 | .port_set_speed = mv88e6390x_port_set_speed, | |
ef0a7318 | 3122 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc | 3123 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 3124 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 3125 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 3126 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 3127 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 3128 | .port_pause_limit = mv88e6390_port_pause_limit, |
c8c94891 | 3129 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 3130 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
79523473 | 3131 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 3132 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
3133 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
3134 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 3135 | .stats_get_stats = mv88e6390_stats_get_stats, |
fa8d1179 VD |
3136 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
3137 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
61303736 | 3138 | .watchdog_ops = &mv88e6390_watchdog_ops, |
6e55f698 | 3139 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
17e708ba | 3140 | .reset = mv88e6352_g1_reset, |
931d1822 VD |
3141 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
3142 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, | |
6335e9f2 | 3143 | .serdes_power = mv88e6390_serdes_power, |
1a3b39ec AL |
3144 | }; |
3145 | ||
f81ec90f VD |
3146 | static const struct mv88e6xxx_info mv88e6xxx_table[] = { |
3147 | [MV88E6085] = { | |
107fcc10 | 3148 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, |
f81ec90f VD |
3149 | .family = MV88E6XXX_FAMILY_6097, |
3150 | .name = "Marvell 88E6085", | |
3151 | .num_databases = 4096, | |
3152 | .num_ports = 10, | |
3cf3c846 | 3153 | .max_vid = 4095, |
9dddd478 | 3154 | .port_base_addr = 0x10, |
a935c052 | 3155 | .global1_addr = 0x1b, |
acddbd21 | 3156 | .age_time_coeff = 15000, |
dc30c35b | 3157 | .g1_irqs = 8, |
e606ca36 | 3158 | .atu_move_port_mask = 0xf, |
f3645652 | 3159 | .pvt = true, |
443d5a1b | 3160 | .tag_protocol = DSA_TAG_PROTO_DSA, |
f81ec90f | 3161 | .flags = MV88E6XXX_FLAGS_FAMILY_6097, |
b3469dd8 | 3162 | .ops = &mv88e6085_ops, |
f81ec90f VD |
3163 | }, |
3164 | ||
3165 | [MV88E6095] = { | |
107fcc10 | 3166 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, |
f81ec90f VD |
3167 | .family = MV88E6XXX_FAMILY_6095, |
3168 | .name = "Marvell 88E6095/88E6095F", | |
3169 | .num_databases = 256, | |
3170 | .num_ports = 11, | |
3cf3c846 | 3171 | .max_vid = 4095, |
9dddd478 | 3172 | .port_base_addr = 0x10, |
a935c052 | 3173 | .global1_addr = 0x1b, |
acddbd21 | 3174 | .age_time_coeff = 15000, |
dc30c35b | 3175 | .g1_irqs = 8, |
e606ca36 | 3176 | .atu_move_port_mask = 0xf, |
443d5a1b | 3177 | .tag_protocol = DSA_TAG_PROTO_DSA, |
f81ec90f | 3178 | .flags = MV88E6XXX_FLAGS_FAMILY_6095, |
b3469dd8 | 3179 | .ops = &mv88e6095_ops, |
f81ec90f VD |
3180 | }, |
3181 | ||
7d381a02 | 3182 | [MV88E6097] = { |
107fcc10 | 3183 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, |
7d381a02 SE |
3184 | .family = MV88E6XXX_FAMILY_6097, |
3185 | .name = "Marvell 88E6097/88E6097F", | |
3186 | .num_databases = 4096, | |
3187 | .num_ports = 11, | |
3cf3c846 | 3188 | .max_vid = 4095, |
7d381a02 SE |
3189 | .port_base_addr = 0x10, |
3190 | .global1_addr = 0x1b, | |
3191 | .age_time_coeff = 15000, | |
c534178b | 3192 | .g1_irqs = 8, |
e606ca36 | 3193 | .atu_move_port_mask = 0xf, |
f3645652 | 3194 | .pvt = true, |
2bfcfcd3 | 3195 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
7d381a02 SE |
3196 | .flags = MV88E6XXX_FLAGS_FAMILY_6097, |
3197 | .ops = &mv88e6097_ops, | |
3198 | }, | |
3199 | ||
f81ec90f | 3200 | [MV88E6123] = { |
107fcc10 | 3201 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, |
f81ec90f VD |
3202 | .family = MV88E6XXX_FAMILY_6165, |
3203 | .name = "Marvell 88E6123", | |
3204 | .num_databases = 4096, | |
3205 | .num_ports = 3, | |
3cf3c846 | 3206 | .max_vid = 4095, |
9dddd478 | 3207 | .port_base_addr = 0x10, |
a935c052 | 3208 | .global1_addr = 0x1b, |
acddbd21 | 3209 | .age_time_coeff = 15000, |
dc30c35b | 3210 | .g1_irqs = 9, |
e606ca36 | 3211 | .atu_move_port_mask = 0xf, |
f3645652 | 3212 | .pvt = true, |
5ebe31d7 | 3213 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 3214 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
b3469dd8 | 3215 | .ops = &mv88e6123_ops, |
f81ec90f VD |
3216 | }, |
3217 | ||
3218 | [MV88E6131] = { | |
107fcc10 | 3219 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, |
f81ec90f VD |
3220 | .family = MV88E6XXX_FAMILY_6185, |
3221 | .name = "Marvell 88E6131", | |
3222 | .num_databases = 256, | |
3223 | .num_ports = 8, | |
3cf3c846 | 3224 | .max_vid = 4095, |
9dddd478 | 3225 | .port_base_addr = 0x10, |
a935c052 | 3226 | .global1_addr = 0x1b, |
acddbd21 | 3227 | .age_time_coeff = 15000, |
dc30c35b | 3228 | .g1_irqs = 9, |
e606ca36 | 3229 | .atu_move_port_mask = 0xf, |
443d5a1b | 3230 | .tag_protocol = DSA_TAG_PROTO_DSA, |
f81ec90f | 3231 | .flags = MV88E6XXX_FLAGS_FAMILY_6185, |
b3469dd8 | 3232 | .ops = &mv88e6131_ops, |
f81ec90f VD |
3233 | }, |
3234 | ||
990e27b0 | 3235 | [MV88E6141] = { |
107fcc10 | 3236 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, |
990e27b0 VD |
3237 | .family = MV88E6XXX_FAMILY_6341, |
3238 | .name = "Marvell 88E6341", | |
3239 | .num_databases = 4096, | |
3240 | .num_ports = 6, | |
3cf3c846 | 3241 | .max_vid = 4095, |
990e27b0 VD |
3242 | .port_base_addr = 0x10, |
3243 | .global1_addr = 0x1b, | |
3244 | .age_time_coeff = 3750, | |
3245 | .atu_move_port_mask = 0x1f, | |
f3645652 | 3246 | .pvt = true, |
990e27b0 VD |
3247 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
3248 | .flags = MV88E6XXX_FLAGS_FAMILY_6341, | |
3249 | .ops = &mv88e6141_ops, | |
3250 | }, | |
3251 | ||
f81ec90f | 3252 | [MV88E6161] = { |
107fcc10 | 3253 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, |
f81ec90f VD |
3254 | .family = MV88E6XXX_FAMILY_6165, |
3255 | .name = "Marvell 88E6161", | |
3256 | .num_databases = 4096, | |
3257 | .num_ports = 6, | |
3cf3c846 | 3258 | .max_vid = 4095, |
9dddd478 | 3259 | .port_base_addr = 0x10, |
a935c052 | 3260 | .global1_addr = 0x1b, |
acddbd21 | 3261 | .age_time_coeff = 15000, |
dc30c35b | 3262 | .g1_irqs = 9, |
e606ca36 | 3263 | .atu_move_port_mask = 0xf, |
f3645652 | 3264 | .pvt = true, |
5ebe31d7 | 3265 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 3266 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
b3469dd8 | 3267 | .ops = &mv88e6161_ops, |
f81ec90f VD |
3268 | }, |
3269 | ||
3270 | [MV88E6165] = { | |
107fcc10 | 3271 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, |
f81ec90f VD |
3272 | .family = MV88E6XXX_FAMILY_6165, |
3273 | .name = "Marvell 88E6165", | |
3274 | .num_databases = 4096, | |
3275 | .num_ports = 6, | |
3cf3c846 | 3276 | .max_vid = 4095, |
9dddd478 | 3277 | .port_base_addr = 0x10, |
a935c052 | 3278 | .global1_addr = 0x1b, |
acddbd21 | 3279 | .age_time_coeff = 15000, |
dc30c35b | 3280 | .g1_irqs = 9, |
e606ca36 | 3281 | .atu_move_port_mask = 0xf, |
f3645652 | 3282 | .pvt = true, |
443d5a1b | 3283 | .tag_protocol = DSA_TAG_PROTO_DSA, |
f81ec90f | 3284 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
b3469dd8 | 3285 | .ops = &mv88e6165_ops, |
f81ec90f VD |
3286 | }, |
3287 | ||
3288 | [MV88E6171] = { | |
107fcc10 | 3289 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, |
f81ec90f VD |
3290 | .family = MV88E6XXX_FAMILY_6351, |
3291 | .name = "Marvell 88E6171", | |
3292 | .num_databases = 4096, | |
3293 | .num_ports = 7, | |
3cf3c846 | 3294 | .max_vid = 4095, |
9dddd478 | 3295 | .port_base_addr = 0x10, |
a935c052 | 3296 | .global1_addr = 0x1b, |
acddbd21 | 3297 | .age_time_coeff = 15000, |
dc30c35b | 3298 | .g1_irqs = 9, |
e606ca36 | 3299 | .atu_move_port_mask = 0xf, |
f3645652 | 3300 | .pvt = true, |
443d5a1b | 3301 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 3302 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
b3469dd8 | 3303 | .ops = &mv88e6171_ops, |
f81ec90f VD |
3304 | }, |
3305 | ||
3306 | [MV88E6172] = { | |
107fcc10 | 3307 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, |
f81ec90f VD |
3308 | .family = MV88E6XXX_FAMILY_6352, |
3309 | .name = "Marvell 88E6172", | |
3310 | .num_databases = 4096, | |
3311 | .num_ports = 7, | |
3cf3c846 | 3312 | .max_vid = 4095, |
9dddd478 | 3313 | .port_base_addr = 0x10, |
a935c052 | 3314 | .global1_addr = 0x1b, |
acddbd21 | 3315 | .age_time_coeff = 15000, |
dc30c35b | 3316 | .g1_irqs = 9, |
e606ca36 | 3317 | .atu_move_port_mask = 0xf, |
f3645652 | 3318 | .pvt = true, |
443d5a1b | 3319 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 3320 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
b3469dd8 | 3321 | .ops = &mv88e6172_ops, |
f81ec90f VD |
3322 | }, |
3323 | ||
3324 | [MV88E6175] = { | |
107fcc10 | 3325 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, |
f81ec90f VD |
3326 | .family = MV88E6XXX_FAMILY_6351, |
3327 | .name = "Marvell 88E6175", | |
3328 | .num_databases = 4096, | |
3329 | .num_ports = 7, | |
3cf3c846 | 3330 | .max_vid = 4095, |
9dddd478 | 3331 | .port_base_addr = 0x10, |
a935c052 | 3332 | .global1_addr = 0x1b, |
acddbd21 | 3333 | .age_time_coeff = 15000, |
dc30c35b | 3334 | .g1_irqs = 9, |
e606ca36 | 3335 | .atu_move_port_mask = 0xf, |
f3645652 | 3336 | .pvt = true, |
443d5a1b | 3337 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 3338 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
b3469dd8 | 3339 | .ops = &mv88e6175_ops, |
f81ec90f VD |
3340 | }, |
3341 | ||
3342 | [MV88E6176] = { | |
107fcc10 | 3343 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, |
f81ec90f VD |
3344 | .family = MV88E6XXX_FAMILY_6352, |
3345 | .name = "Marvell 88E6176", | |
3346 | .num_databases = 4096, | |
3347 | .num_ports = 7, | |
3cf3c846 | 3348 | .max_vid = 4095, |
9dddd478 | 3349 | .port_base_addr = 0x10, |
a935c052 | 3350 | .global1_addr = 0x1b, |
acddbd21 | 3351 | .age_time_coeff = 15000, |
dc30c35b | 3352 | .g1_irqs = 9, |
e606ca36 | 3353 | .atu_move_port_mask = 0xf, |
f3645652 | 3354 | .pvt = true, |
443d5a1b | 3355 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 3356 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
b3469dd8 | 3357 | .ops = &mv88e6176_ops, |
f81ec90f VD |
3358 | }, |
3359 | ||
3360 | [MV88E6185] = { | |
107fcc10 | 3361 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, |
f81ec90f VD |
3362 | .family = MV88E6XXX_FAMILY_6185, |
3363 | .name = "Marvell 88E6185", | |
3364 | .num_databases = 256, | |
3365 | .num_ports = 10, | |
3cf3c846 | 3366 | .max_vid = 4095, |
9dddd478 | 3367 | .port_base_addr = 0x10, |
a935c052 | 3368 | .global1_addr = 0x1b, |
acddbd21 | 3369 | .age_time_coeff = 15000, |
dc30c35b | 3370 | .g1_irqs = 8, |
e606ca36 | 3371 | .atu_move_port_mask = 0xf, |
443d5a1b | 3372 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 3373 | .flags = MV88E6XXX_FLAGS_FAMILY_6185, |
b3469dd8 | 3374 | .ops = &mv88e6185_ops, |
f81ec90f VD |
3375 | }, |
3376 | ||
1a3b39ec | 3377 | [MV88E6190] = { |
107fcc10 | 3378 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, |
1a3b39ec AL |
3379 | .family = MV88E6XXX_FAMILY_6390, |
3380 | .name = "Marvell 88E6190", | |
3381 | .num_databases = 4096, | |
3382 | .num_ports = 11, /* 10 + Z80 */ | |
931d1822 | 3383 | .max_vid = 8191, |
1a3b39ec AL |
3384 | .port_base_addr = 0x0, |
3385 | .global1_addr = 0x1b, | |
443d5a1b | 3386 | .tag_protocol = DSA_TAG_PROTO_DSA, |
b91e055c | 3387 | .age_time_coeff = 3750, |
1a3b39ec | 3388 | .g1_irqs = 9, |
f3645652 | 3389 | .pvt = true, |
e606ca36 | 3390 | .atu_move_port_mask = 0x1f, |
1a3b39ec AL |
3391 | .flags = MV88E6XXX_FLAGS_FAMILY_6390, |
3392 | .ops = &mv88e6190_ops, | |
3393 | }, | |
3394 | ||
3395 | [MV88E6190X] = { | |
107fcc10 | 3396 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, |
1a3b39ec AL |
3397 | .family = MV88E6XXX_FAMILY_6390, |
3398 | .name = "Marvell 88E6190X", | |
3399 | .num_databases = 4096, | |
3400 | .num_ports = 11, /* 10 + Z80 */ | |
931d1822 | 3401 | .max_vid = 8191, |
1a3b39ec AL |
3402 | .port_base_addr = 0x0, |
3403 | .global1_addr = 0x1b, | |
b91e055c | 3404 | .age_time_coeff = 3750, |
1a3b39ec | 3405 | .g1_irqs = 9, |
e606ca36 | 3406 | .atu_move_port_mask = 0x1f, |
f3645652 | 3407 | .pvt = true, |
443d5a1b | 3408 | .tag_protocol = DSA_TAG_PROTO_DSA, |
1a3b39ec AL |
3409 | .flags = MV88E6XXX_FLAGS_FAMILY_6390, |
3410 | .ops = &mv88e6190x_ops, | |
3411 | }, | |
3412 | ||
3413 | [MV88E6191] = { | |
107fcc10 | 3414 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, |
1a3b39ec AL |
3415 | .family = MV88E6XXX_FAMILY_6390, |
3416 | .name = "Marvell 88E6191", | |
3417 | .num_databases = 4096, | |
3418 | .num_ports = 11, /* 10 + Z80 */ | |
931d1822 | 3419 | .max_vid = 8191, |
1a3b39ec AL |
3420 | .port_base_addr = 0x0, |
3421 | .global1_addr = 0x1b, | |
b91e055c | 3422 | .age_time_coeff = 3750, |
443d5a1b | 3423 | .g1_irqs = 9, |
e606ca36 | 3424 | .atu_move_port_mask = 0x1f, |
f3645652 | 3425 | .pvt = true, |
443d5a1b | 3426 | .tag_protocol = DSA_TAG_PROTO_DSA, |
1a3b39ec | 3427 | .flags = MV88E6XXX_FLAGS_FAMILY_6390, |
2cf4cefb | 3428 | .ops = &mv88e6191_ops, |
1a3b39ec AL |
3429 | }, |
3430 | ||
f81ec90f | 3431 | [MV88E6240] = { |
107fcc10 | 3432 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, |
f81ec90f VD |
3433 | .family = MV88E6XXX_FAMILY_6352, |
3434 | .name = "Marvell 88E6240", | |
3435 | .num_databases = 4096, | |
3436 | .num_ports = 7, | |
3cf3c846 | 3437 | .max_vid = 4095, |
9dddd478 | 3438 | .port_base_addr = 0x10, |
a935c052 | 3439 | .global1_addr = 0x1b, |
acddbd21 | 3440 | .age_time_coeff = 15000, |
dc30c35b | 3441 | .g1_irqs = 9, |
e606ca36 | 3442 | .atu_move_port_mask = 0xf, |
f3645652 | 3443 | .pvt = true, |
443d5a1b | 3444 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 3445 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
b3469dd8 | 3446 | .ops = &mv88e6240_ops, |
f81ec90f VD |
3447 | }, |
3448 | ||
1a3b39ec | 3449 | [MV88E6290] = { |
107fcc10 | 3450 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, |
1a3b39ec AL |
3451 | .family = MV88E6XXX_FAMILY_6390, |
3452 | .name = "Marvell 88E6290", | |
3453 | .num_databases = 4096, | |
3454 | .num_ports = 11, /* 10 + Z80 */ | |
931d1822 | 3455 | .max_vid = 8191, |
1a3b39ec AL |
3456 | .port_base_addr = 0x0, |
3457 | .global1_addr = 0x1b, | |
b91e055c | 3458 | .age_time_coeff = 3750, |
1a3b39ec | 3459 | .g1_irqs = 9, |
e606ca36 | 3460 | .atu_move_port_mask = 0x1f, |
f3645652 | 3461 | .pvt = true, |
443d5a1b | 3462 | .tag_protocol = DSA_TAG_PROTO_DSA, |
1a3b39ec AL |
3463 | .flags = MV88E6XXX_FLAGS_FAMILY_6390, |
3464 | .ops = &mv88e6290_ops, | |
3465 | }, | |
3466 | ||
f81ec90f | 3467 | [MV88E6320] = { |
107fcc10 | 3468 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, |
f81ec90f VD |
3469 | .family = MV88E6XXX_FAMILY_6320, |
3470 | .name = "Marvell 88E6320", | |
3471 | .num_databases = 4096, | |
3472 | .num_ports = 7, | |
3cf3c846 | 3473 | .max_vid = 4095, |
9dddd478 | 3474 | .port_base_addr = 0x10, |
a935c052 | 3475 | .global1_addr = 0x1b, |
acddbd21 | 3476 | .age_time_coeff = 15000, |
dc30c35b | 3477 | .g1_irqs = 8, |
e606ca36 | 3478 | .atu_move_port_mask = 0xf, |
f3645652 | 3479 | .pvt = true, |
443d5a1b | 3480 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 3481 | .flags = MV88E6XXX_FLAGS_FAMILY_6320, |
b3469dd8 | 3482 | .ops = &mv88e6320_ops, |
f81ec90f VD |
3483 | }, |
3484 | ||
3485 | [MV88E6321] = { | |
107fcc10 | 3486 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, |
f81ec90f VD |
3487 | .family = MV88E6XXX_FAMILY_6320, |
3488 | .name = "Marvell 88E6321", | |
3489 | .num_databases = 4096, | |
3490 | .num_ports = 7, | |
3cf3c846 | 3491 | .max_vid = 4095, |
9dddd478 | 3492 | .port_base_addr = 0x10, |
a935c052 | 3493 | .global1_addr = 0x1b, |
acddbd21 | 3494 | .age_time_coeff = 15000, |
dc30c35b | 3495 | .g1_irqs = 8, |
e606ca36 | 3496 | .atu_move_port_mask = 0xf, |
443d5a1b | 3497 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 3498 | .flags = MV88E6XXX_FLAGS_FAMILY_6320, |
b3469dd8 | 3499 | .ops = &mv88e6321_ops, |
f81ec90f VD |
3500 | }, |
3501 | ||
a75961d0 | 3502 | [MV88E6341] = { |
107fcc10 | 3503 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, |
a75961d0 GC |
3504 | .family = MV88E6XXX_FAMILY_6341, |
3505 | .name = "Marvell 88E6341", | |
3506 | .num_databases = 4096, | |
3507 | .num_ports = 6, | |
3cf3c846 | 3508 | .max_vid = 4095, |
a75961d0 GC |
3509 | .port_base_addr = 0x10, |
3510 | .global1_addr = 0x1b, | |
3511 | .age_time_coeff = 3750, | |
e606ca36 | 3512 | .atu_move_port_mask = 0x1f, |
f3645652 | 3513 | .pvt = true, |
a75961d0 GC |
3514 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
3515 | .flags = MV88E6XXX_FLAGS_FAMILY_6341, | |
3516 | .ops = &mv88e6341_ops, | |
3517 | }, | |
3518 | ||
f81ec90f | 3519 | [MV88E6350] = { |
107fcc10 | 3520 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, |
f81ec90f VD |
3521 | .family = MV88E6XXX_FAMILY_6351, |
3522 | .name = "Marvell 88E6350", | |
3523 | .num_databases = 4096, | |
3524 | .num_ports = 7, | |
3cf3c846 | 3525 | .max_vid = 4095, |
9dddd478 | 3526 | .port_base_addr = 0x10, |
a935c052 | 3527 | .global1_addr = 0x1b, |
acddbd21 | 3528 | .age_time_coeff = 15000, |
dc30c35b | 3529 | .g1_irqs = 9, |
e606ca36 | 3530 | .atu_move_port_mask = 0xf, |
f3645652 | 3531 | .pvt = true, |
443d5a1b | 3532 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 3533 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
b3469dd8 | 3534 | .ops = &mv88e6350_ops, |
f81ec90f VD |
3535 | }, |
3536 | ||
3537 | [MV88E6351] = { | |
107fcc10 | 3538 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, |
f81ec90f VD |
3539 | .family = MV88E6XXX_FAMILY_6351, |
3540 | .name = "Marvell 88E6351", | |
3541 | .num_databases = 4096, | |
3542 | .num_ports = 7, | |
3cf3c846 | 3543 | .max_vid = 4095, |
9dddd478 | 3544 | .port_base_addr = 0x10, |
a935c052 | 3545 | .global1_addr = 0x1b, |
acddbd21 | 3546 | .age_time_coeff = 15000, |
dc30c35b | 3547 | .g1_irqs = 9, |
e606ca36 | 3548 | .atu_move_port_mask = 0xf, |
f3645652 | 3549 | .pvt = true, |
443d5a1b | 3550 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 3551 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
b3469dd8 | 3552 | .ops = &mv88e6351_ops, |
f81ec90f VD |
3553 | }, |
3554 | ||
3555 | [MV88E6352] = { | |
107fcc10 | 3556 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, |
f81ec90f VD |
3557 | .family = MV88E6XXX_FAMILY_6352, |
3558 | .name = "Marvell 88E6352", | |
3559 | .num_databases = 4096, | |
3560 | .num_ports = 7, | |
3cf3c846 | 3561 | .max_vid = 4095, |
9dddd478 | 3562 | .port_base_addr = 0x10, |
a935c052 | 3563 | .global1_addr = 0x1b, |
acddbd21 | 3564 | .age_time_coeff = 15000, |
dc30c35b | 3565 | .g1_irqs = 9, |
e606ca36 | 3566 | .atu_move_port_mask = 0xf, |
f3645652 | 3567 | .pvt = true, |
443d5a1b | 3568 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
f81ec90f | 3569 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
b3469dd8 | 3570 | .ops = &mv88e6352_ops, |
f81ec90f | 3571 | }, |
1a3b39ec | 3572 | [MV88E6390] = { |
107fcc10 | 3573 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, |
1a3b39ec AL |
3574 | .family = MV88E6XXX_FAMILY_6390, |
3575 | .name = "Marvell 88E6390", | |
3576 | .num_databases = 4096, | |
3577 | .num_ports = 11, /* 10 + Z80 */ | |
931d1822 | 3578 | .max_vid = 8191, |
1a3b39ec AL |
3579 | .port_base_addr = 0x0, |
3580 | .global1_addr = 0x1b, | |
b91e055c | 3581 | .age_time_coeff = 3750, |
1a3b39ec | 3582 | .g1_irqs = 9, |
e606ca36 | 3583 | .atu_move_port_mask = 0x1f, |
f3645652 | 3584 | .pvt = true, |
443d5a1b | 3585 | .tag_protocol = DSA_TAG_PROTO_DSA, |
1a3b39ec AL |
3586 | .flags = MV88E6XXX_FLAGS_FAMILY_6390, |
3587 | .ops = &mv88e6390_ops, | |
3588 | }, | |
3589 | [MV88E6390X] = { | |
107fcc10 | 3590 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, |
1a3b39ec AL |
3591 | .family = MV88E6XXX_FAMILY_6390, |
3592 | .name = "Marvell 88E6390X", | |
3593 | .num_databases = 4096, | |
3594 | .num_ports = 11, /* 10 + Z80 */ | |
931d1822 | 3595 | .max_vid = 8191, |
1a3b39ec AL |
3596 | .port_base_addr = 0x0, |
3597 | .global1_addr = 0x1b, | |
b91e055c | 3598 | .age_time_coeff = 3750, |
1a3b39ec | 3599 | .g1_irqs = 9, |
e606ca36 | 3600 | .atu_move_port_mask = 0x1f, |
f3645652 | 3601 | .pvt = true, |
443d5a1b | 3602 | .tag_protocol = DSA_TAG_PROTO_DSA, |
1a3b39ec AL |
3603 | .flags = MV88E6XXX_FLAGS_FAMILY_6390, |
3604 | .ops = &mv88e6390x_ops, | |
3605 | }, | |
f81ec90f VD |
3606 | }; |
3607 | ||
5f7c0367 | 3608 | static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) |
b9b37713 | 3609 | { |
a439c061 | 3610 | int i; |
b9b37713 | 3611 | |
5f7c0367 VD |
3612 | for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) |
3613 | if (mv88e6xxx_table[i].prod_num == prod_num) | |
3614 | return &mv88e6xxx_table[i]; | |
b9b37713 | 3615 | |
b9b37713 VD |
3616 | return NULL; |
3617 | } | |
3618 | ||
fad09c73 | 3619 | static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) |
bc46a3d5 VD |
3620 | { |
3621 | const struct mv88e6xxx_info *info; | |
8f6345b2 VD |
3622 | unsigned int prod_num, rev; |
3623 | u16 id; | |
3624 | int err; | |
bc46a3d5 | 3625 | |
8f6345b2 | 3626 | mutex_lock(&chip->reg_lock); |
107fcc10 | 3627 | err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); |
8f6345b2 VD |
3628 | mutex_unlock(&chip->reg_lock); |
3629 | if (err) | |
3630 | return err; | |
bc46a3d5 | 3631 | |
107fcc10 VD |
3632 | prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; |
3633 | rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; | |
bc46a3d5 VD |
3634 | |
3635 | info = mv88e6xxx_lookup_info(prod_num); | |
3636 | if (!info) | |
3637 | return -ENODEV; | |
3638 | ||
caac8545 | 3639 | /* Update the compatible info with the probed one */ |
fad09c73 | 3640 | chip->info = info; |
bc46a3d5 | 3641 | |
ca070c10 VD |
3642 | err = mv88e6xxx_g2_require(chip); |
3643 | if (err) | |
3644 | return err; | |
3645 | ||
fad09c73 VD |
3646 | dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", |
3647 | chip->info->prod_num, chip->info->name, rev); | |
bc46a3d5 VD |
3648 | |
3649 | return 0; | |
3650 | } | |
3651 | ||
fad09c73 | 3652 | static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) |
469d729f | 3653 | { |
fad09c73 | 3654 | struct mv88e6xxx_chip *chip; |
469d729f | 3655 | |
fad09c73 VD |
3656 | chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); |
3657 | if (!chip) | |
469d729f VD |
3658 | return NULL; |
3659 | ||
fad09c73 | 3660 | chip->dev = dev; |
469d729f | 3661 | |
fad09c73 | 3662 | mutex_init(&chip->reg_lock); |
a3c53be5 | 3663 | INIT_LIST_HEAD(&chip->mdios); |
469d729f | 3664 | |
fad09c73 | 3665 | return chip; |
469d729f VD |
3666 | } |
3667 | ||
fad09c73 | 3668 | static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, |
4a70c4ab VD |
3669 | struct mii_bus *bus, int sw_addr) |
3670 | { | |
914b32f6 | 3671 | if (sw_addr == 0) |
fad09c73 | 3672 | chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; |
a0ffff24 | 3673 | else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP)) |
fad09c73 | 3674 | chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; |
914b32f6 VD |
3675 | else |
3676 | return -EINVAL; | |
3677 | ||
fad09c73 VD |
3678 | chip->bus = bus; |
3679 | chip->sw_addr = sw_addr; | |
4a70c4ab VD |
3680 | |
3681 | return 0; | |
3682 | } | |
3683 | ||
7b314362 AL |
3684 | static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds) |
3685 | { | |
04bed143 | 3686 | struct mv88e6xxx_chip *chip = ds->priv; |
2bbb33be | 3687 | |
443d5a1b | 3688 | return chip->info->tag_protocol; |
7b314362 AL |
3689 | } |
3690 | ||
fcdce7d0 AL |
3691 | static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, |
3692 | struct device *host_dev, int sw_addr, | |
3693 | void **priv) | |
a77d43f1 | 3694 | { |
fad09c73 | 3695 | struct mv88e6xxx_chip *chip; |
a439c061 | 3696 | struct mii_bus *bus; |
b516d453 | 3697 | int err; |
a77d43f1 | 3698 | |
a439c061 | 3699 | bus = dsa_host_dev_to_mii_bus(host_dev); |
c156913b AL |
3700 | if (!bus) |
3701 | return NULL; | |
3702 | ||
fad09c73 VD |
3703 | chip = mv88e6xxx_alloc_chip(dsa_dev); |
3704 | if (!chip) | |
469d729f VD |
3705 | return NULL; |
3706 | ||
caac8545 | 3707 | /* Legacy SMI probing will only support chips similar to 88E6085 */ |
fad09c73 | 3708 | chip->info = &mv88e6xxx_table[MV88E6085]; |
caac8545 | 3709 | |
fad09c73 | 3710 | err = mv88e6xxx_smi_init(chip, bus, sw_addr); |
4a70c4ab VD |
3711 | if (err) |
3712 | goto free; | |
3713 | ||
fad09c73 | 3714 | err = mv88e6xxx_detect(chip); |
bc46a3d5 | 3715 | if (err) |
469d729f | 3716 | goto free; |
a439c061 | 3717 | |
dc30c35b AL |
3718 | mutex_lock(&chip->reg_lock); |
3719 | err = mv88e6xxx_switch_reset(chip); | |
3720 | mutex_unlock(&chip->reg_lock); | |
3721 | if (err) | |
3722 | goto free; | |
3723 | ||
e57e5e77 VD |
3724 | mv88e6xxx_phy_init(chip); |
3725 | ||
a3c53be5 | 3726 | err = mv88e6xxx_mdios_register(chip, NULL); |
b516d453 | 3727 | if (err) |
469d729f | 3728 | goto free; |
b516d453 | 3729 | |
fad09c73 | 3730 | *priv = chip; |
a439c061 | 3731 | |
fad09c73 | 3732 | return chip->info->name; |
469d729f | 3733 | free: |
fad09c73 | 3734 | devm_kfree(dsa_dev, chip); |
469d729f VD |
3735 | |
3736 | return NULL; | |
a77d43f1 AL |
3737 | } |
3738 | ||
7df8fbdd VD |
3739 | static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, |
3740 | const struct switchdev_obj_port_mdb *mdb, | |
3741 | struct switchdev_trans *trans) | |
3742 | { | |
3743 | /* We don't need any dynamic resource from the kernel (yet), | |
3744 | * so skip the prepare phase. | |
3745 | */ | |
3746 | ||
3747 | return 0; | |
3748 | } | |
3749 | ||
3750 | static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, | |
3751 | const struct switchdev_obj_port_mdb *mdb, | |
3752 | struct switchdev_trans *trans) | |
3753 | { | |
04bed143 | 3754 | struct mv88e6xxx_chip *chip = ds->priv; |
7df8fbdd VD |
3755 | |
3756 | mutex_lock(&chip->reg_lock); | |
3757 | if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, | |
27c0e600 | 3758 | MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) |
774439e5 VD |
3759 | dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", |
3760 | port); | |
7df8fbdd VD |
3761 | mutex_unlock(&chip->reg_lock); |
3762 | } | |
3763 | ||
3764 | static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, | |
3765 | const struct switchdev_obj_port_mdb *mdb) | |
3766 | { | |
04bed143 | 3767 | struct mv88e6xxx_chip *chip = ds->priv; |
7df8fbdd VD |
3768 | int err; |
3769 | ||
3770 | mutex_lock(&chip->reg_lock); | |
3771 | err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, | |
27c0e600 | 3772 | MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); |
7df8fbdd VD |
3773 | mutex_unlock(&chip->reg_lock); |
3774 | ||
3775 | return err; | |
3776 | } | |
3777 | ||
3778 | static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port, | |
3779 | struct switchdev_obj_port_mdb *mdb, | |
438ff537 | 3780 | switchdev_obj_dump_cb_t *cb) |
7df8fbdd | 3781 | { |
04bed143 | 3782 | struct mv88e6xxx_chip *chip = ds->priv; |
7df8fbdd VD |
3783 | int err; |
3784 | ||
3785 | mutex_lock(&chip->reg_lock); | |
3786 | err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb); | |
3787 | mutex_unlock(&chip->reg_lock); | |
3788 | ||
3789 | return err; | |
3790 | } | |
3791 | ||
a82f67af | 3792 | static const struct dsa_switch_ops mv88e6xxx_switch_ops = { |
fcdce7d0 | 3793 | .probe = mv88e6xxx_drv_probe, |
7b314362 | 3794 | .get_tag_protocol = mv88e6xxx_get_tag_protocol, |
f81ec90f VD |
3795 | .setup = mv88e6xxx_setup, |
3796 | .set_addr = mv88e6xxx_set_addr, | |
f81ec90f VD |
3797 | .adjust_link = mv88e6xxx_adjust_link, |
3798 | .get_strings = mv88e6xxx_get_strings, | |
3799 | .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, | |
3800 | .get_sset_count = mv88e6xxx_get_sset_count, | |
04aca993 AL |
3801 | .port_enable = mv88e6xxx_port_enable, |
3802 | .port_disable = mv88e6xxx_port_disable, | |
f81ec90f VD |
3803 | .set_eee = mv88e6xxx_set_eee, |
3804 | .get_eee = mv88e6xxx_get_eee, | |
f8cd8753 | 3805 | .get_eeprom_len = mv88e6xxx_get_eeprom_len, |
f81ec90f VD |
3806 | .get_eeprom = mv88e6xxx_get_eeprom, |
3807 | .set_eeprom = mv88e6xxx_set_eeprom, | |
3808 | .get_regs_len = mv88e6xxx_get_regs_len, | |
3809 | .get_regs = mv88e6xxx_get_regs, | |
2cfcd964 | 3810 | .set_ageing_time = mv88e6xxx_set_ageing_time, |
f81ec90f VD |
3811 | .port_bridge_join = mv88e6xxx_port_bridge_join, |
3812 | .port_bridge_leave = mv88e6xxx_port_bridge_leave, | |
3813 | .port_stp_state_set = mv88e6xxx_port_stp_state_set, | |
749efcb8 | 3814 | .port_fast_age = mv88e6xxx_port_fast_age, |
f81ec90f VD |
3815 | .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, |
3816 | .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, | |
3817 | .port_vlan_add = mv88e6xxx_port_vlan_add, | |
3818 | .port_vlan_del = mv88e6xxx_port_vlan_del, | |
3819 | .port_vlan_dump = mv88e6xxx_port_vlan_dump, | |
3820 | .port_fdb_prepare = mv88e6xxx_port_fdb_prepare, | |
3821 | .port_fdb_add = mv88e6xxx_port_fdb_add, | |
3822 | .port_fdb_del = mv88e6xxx_port_fdb_del, | |
3823 | .port_fdb_dump = mv88e6xxx_port_fdb_dump, | |
7df8fbdd VD |
3824 | .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, |
3825 | .port_mdb_add = mv88e6xxx_port_mdb_add, | |
3826 | .port_mdb_del = mv88e6xxx_port_mdb_del, | |
3827 | .port_mdb_dump = mv88e6xxx_port_mdb_dump, | |
aec5ac88 VD |
3828 | .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, |
3829 | .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, | |
f81ec90f VD |
3830 | }; |
3831 | ||
ab3d408d FF |
3832 | static struct dsa_switch_driver mv88e6xxx_switch_drv = { |
3833 | .ops = &mv88e6xxx_switch_ops, | |
3834 | }; | |
3835 | ||
55ed0ce0 | 3836 | static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) |
b7e66a5f | 3837 | { |
fad09c73 | 3838 | struct device *dev = chip->dev; |
b7e66a5f VD |
3839 | struct dsa_switch *ds; |
3840 | ||
73b1204d | 3841 | ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); |
b7e66a5f VD |
3842 | if (!ds) |
3843 | return -ENOMEM; | |
3844 | ||
fad09c73 | 3845 | ds->priv = chip; |
9d490b4e | 3846 | ds->ops = &mv88e6xxx_switch_ops; |
9ff74f24 VD |
3847 | ds->ageing_time_min = chip->info->age_time_coeff; |
3848 | ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; | |
b7e66a5f VD |
3849 | |
3850 | dev_set_drvdata(dev, ds); | |
3851 | ||
23c9ee49 | 3852 | return dsa_register_switch(ds); |
b7e66a5f VD |
3853 | } |
3854 | ||
fad09c73 | 3855 | static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) |
b7e66a5f | 3856 | { |
fad09c73 | 3857 | dsa_unregister_switch(chip->ds); |
b7e66a5f VD |
3858 | } |
3859 | ||
57d32310 | 3860 | static int mv88e6xxx_probe(struct mdio_device *mdiodev) |
98e67308 | 3861 | { |
14c7b3c3 | 3862 | struct device *dev = &mdiodev->dev; |
f8cd8753 | 3863 | struct device_node *np = dev->of_node; |
caac8545 | 3864 | const struct mv88e6xxx_info *compat_info; |
fad09c73 | 3865 | struct mv88e6xxx_chip *chip; |
f8cd8753 | 3866 | u32 eeprom_len; |
52638f71 | 3867 | int err; |
14c7b3c3 | 3868 | |
caac8545 VD |
3869 | compat_info = of_device_get_match_data(dev); |
3870 | if (!compat_info) | |
3871 | return -EINVAL; | |
3872 | ||
fad09c73 VD |
3873 | chip = mv88e6xxx_alloc_chip(dev); |
3874 | if (!chip) | |
14c7b3c3 AL |
3875 | return -ENOMEM; |
3876 | ||
fad09c73 | 3877 | chip->info = compat_info; |
caac8545 | 3878 | |
fad09c73 | 3879 | err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); |
4a70c4ab VD |
3880 | if (err) |
3881 | return err; | |
14c7b3c3 | 3882 | |
b4308f04 AL |
3883 | chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); |
3884 | if (IS_ERR(chip->reset)) | |
3885 | return PTR_ERR(chip->reset); | |
3886 | ||
fad09c73 | 3887 | err = mv88e6xxx_detect(chip); |
bc46a3d5 VD |
3888 | if (err) |
3889 | return err; | |
14c7b3c3 | 3890 | |
e57e5e77 VD |
3891 | mv88e6xxx_phy_init(chip); |
3892 | ||
ee4dc2e7 | 3893 | if (chip->info->ops->get_eeprom && |
f8cd8753 | 3894 | !of_property_read_u32(np, "eeprom-length", &eeprom_len)) |
fad09c73 | 3895 | chip->eeprom_len = eeprom_len; |
f8cd8753 | 3896 | |
dc30c35b AL |
3897 | mutex_lock(&chip->reg_lock); |
3898 | err = mv88e6xxx_switch_reset(chip); | |
3899 | mutex_unlock(&chip->reg_lock); | |
3900 | if (err) | |
3901 | goto out; | |
3902 | ||
3903 | chip->irq = of_irq_get(np, 0); | |
3904 | if (chip->irq == -EPROBE_DEFER) { | |
3905 | err = chip->irq; | |
3906 | goto out; | |
3907 | } | |
3908 | ||
3909 | if (chip->irq > 0) { | |
3910 | /* Has to be performed before the MDIO bus is created, | |
3911 | * because the PHYs will link there interrupts to these | |
3912 | * interrupt controllers | |
3913 | */ | |
3914 | mutex_lock(&chip->reg_lock); | |
3915 | err = mv88e6xxx_g1_irq_setup(chip); | |
3916 | mutex_unlock(&chip->reg_lock); | |
3917 | ||
3918 | if (err) | |
3919 | goto out; | |
3920 | ||
3921 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) { | |
3922 | err = mv88e6xxx_g2_irq_setup(chip); | |
3923 | if (err) | |
3924 | goto out_g1_irq; | |
3925 | } | |
3926 | } | |
3927 | ||
a3c53be5 | 3928 | err = mv88e6xxx_mdios_register(chip, np); |
b516d453 | 3929 | if (err) |
dc30c35b | 3930 | goto out_g2_irq; |
b516d453 | 3931 | |
55ed0ce0 | 3932 | err = mv88e6xxx_register_switch(chip); |
dc30c35b AL |
3933 | if (err) |
3934 | goto out_mdio; | |
83c0afae | 3935 | |
98e67308 | 3936 | return 0; |
dc30c35b AL |
3937 | |
3938 | out_mdio: | |
a3c53be5 | 3939 | mv88e6xxx_mdios_unregister(chip); |
dc30c35b | 3940 | out_g2_irq: |
46712644 | 3941 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0) |
dc30c35b AL |
3942 | mv88e6xxx_g2_irq_free(chip); |
3943 | out_g1_irq: | |
61f7c3f8 AL |
3944 | if (chip->irq > 0) { |
3945 | mutex_lock(&chip->reg_lock); | |
46712644 | 3946 | mv88e6xxx_g1_irq_free(chip); |
61f7c3f8 AL |
3947 | mutex_unlock(&chip->reg_lock); |
3948 | } | |
dc30c35b AL |
3949 | out: |
3950 | return err; | |
98e67308 | 3951 | } |
14c7b3c3 AL |
3952 | |
3953 | static void mv88e6xxx_remove(struct mdio_device *mdiodev) | |
3954 | { | |
3955 | struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); | |
04bed143 | 3956 | struct mv88e6xxx_chip *chip = ds->priv; |
14c7b3c3 | 3957 | |
930188ce | 3958 | mv88e6xxx_phy_destroy(chip); |
fad09c73 | 3959 | mv88e6xxx_unregister_switch(chip); |
a3c53be5 | 3960 | mv88e6xxx_mdios_unregister(chip); |
dc30c35b | 3961 | |
46712644 AL |
3962 | if (chip->irq > 0) { |
3963 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) | |
3964 | mv88e6xxx_g2_irq_free(chip); | |
3965 | mv88e6xxx_g1_irq_free(chip); | |
3966 | } | |
14c7b3c3 AL |
3967 | } |
3968 | ||
3969 | static const struct of_device_id mv88e6xxx_of_match[] = { | |
caac8545 VD |
3970 | { |
3971 | .compatible = "marvell,mv88e6085", | |
3972 | .data = &mv88e6xxx_table[MV88E6085], | |
3973 | }, | |
1a3b39ec AL |
3974 | { |
3975 | .compatible = "marvell,mv88e6190", | |
3976 | .data = &mv88e6xxx_table[MV88E6190], | |
3977 | }, | |
14c7b3c3 AL |
3978 | { /* sentinel */ }, |
3979 | }; | |
3980 | ||
3981 | MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); | |
3982 | ||
3983 | static struct mdio_driver mv88e6xxx_driver = { | |
3984 | .probe = mv88e6xxx_probe, | |
3985 | .remove = mv88e6xxx_remove, | |
3986 | .mdiodrv.driver = { | |
3987 | .name = "mv88e6085", | |
3988 | .of_match_table = mv88e6xxx_of_match, | |
3989 | }, | |
3990 | }; | |
3991 | ||
3992 | static int __init mv88e6xxx_init(void) | |
3993 | { | |
ab3d408d | 3994 | register_switch_driver(&mv88e6xxx_switch_drv); |
14c7b3c3 AL |
3995 | return mdio_driver_register(&mv88e6xxx_driver); |
3996 | } | |
98e67308 BH |
3997 | module_init(mv88e6xxx_init); |
3998 | ||
3999 | static void __exit mv88e6xxx_cleanup(void) | |
4000 | { | |
14c7b3c3 | 4001 | mdio_driver_unregister(&mv88e6xxx_driver); |
ab3d408d | 4002 | unregister_switch_driver(&mv88e6xxx_switch_drv); |
98e67308 BH |
4003 | } |
4004 | module_exit(mv88e6xxx_cleanup); | |
3d825ede BH |
4005 | |
4006 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); | |
4007 | MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); | |
4008 | MODULE_LICENSE("GPL"); |