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net: dsa: mv88e6xxx: fix port egress flooding mode
[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
1f36faf2 35#include <net/switchdev.h>
ec561276 36
91da11f8 37#include "mv88e6xxx.h"
a935c052 38#include "global1.h"
ec561276 39#include "global2.h"
18abed21 40#include "port.h"
91da11f8 41
fad09c73 42static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 43{
fad09c73
VD		 44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 46 dump_stack();
47 }
48}
49
914b32f6
VD		 50/* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
52 *
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
56 *
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 60 */
914b32f6 61
fad09c73 62static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 63 int addr, int reg, u16 *val)
64{
fad09c73 65 if (!chip->smi_ops)
914b32f6
VD		 66 return -EOPNOTSUPP;
67
fad09c73 68 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 69}
70
fad09c73 71static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 72 int addr, int reg, u16 val)
73{
fad09c73 74 if (!chip->smi_ops)
914b32f6
VD		 75 return -EOPNOTSUPP;
76
fad09c73 77 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 78}
79
fad09c73 80static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 81 int addr, int reg, u16 *val)
82{
83 int ret;
84
fad09c73 85 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 86 if (ret < 0)
87 return ret;
88
89 *val = ret & 0xffff;
90
91 return 0;
92}
93
fad09c73 94static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 95 int addr, int reg, u16 val)
96{
97 int ret;
98
fad09c73 99 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 100 if (ret < 0)
101 return ret;
102
103 return 0;
104}
105
c08026ab 106static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
109};
110
fad09c73 111static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 112{
113 int ret;
114 int i;
115
116 for (i = 0; i < 16; i++) {
fad09c73 117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 118 if (ret < 0)
119 return ret;
120
cca8b133 121 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 122 return 0;
123 }
124
125 return -ETIMEDOUT;
126}
127
fad09c73 128static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 129 int addr, int reg, u16 *val)
91da11f8
LB		 130{
131 int ret;
132
3675c8d7 133 /* Wait for the bus to become free. */
fad09c73 134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 135 if (ret < 0)
136 return ret;
137
3675c8d7 138 /* Transmit the read command. */
fad09c73 139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 141 if (ret < 0)
142 return ret;
143
3675c8d7 144 /* Wait for the read command to complete. */
fad09c73 145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 146 if (ret < 0)
147 return ret;
148
3675c8d7 149 /* Read the data. */
fad09c73 150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 151 if (ret < 0)
152 return ret;
153
914b32f6 154 *val = ret & 0xffff;
91da11f8 155
914b32f6 156 return 0;
8d6d09e7
GR		 157}
158
fad09c73 159static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 160 int addr, int reg, u16 val)
91da11f8
LB		 161{
162 int ret;
163
3675c8d7 164 /* Wait for the bus to become free. */
fad09c73 165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 166 if (ret < 0)
167 return ret;
168
3675c8d7 169 /* Transmit the data to write. */
fad09c73 170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 171 if (ret < 0)
172 return ret;
173
3675c8d7 174 /* Transmit the write command. */
fad09c73 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 177 if (ret < 0)
178 return ret;
179
3675c8d7 180 /* Wait for the write command to complete. */
fad09c73 181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 182 if (ret < 0)
183 return ret;
184
185 return 0;
186}
187
c08026ab 188static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
191};
192
ec561276 193int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 194{
195 int err;
196
fad09c73 197 assert_reg_lock(chip);
914b32f6 198
fad09c73 199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 200 if (err)
201 return err;
202
fad09c73 203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 204 addr, reg, *val);
205
206 return 0;
207}
208
ec561276 209int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 210{
914b32f6
VD		 211 int err;
212
fad09c73 213 assert_reg_lock(chip);
91da11f8 214
fad09c73 215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 216 if (err)
217 return err;
218
fad09c73 219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 220 addr, reg, val);
221
914b32f6
VD		 222 return 0;
223}
224
ee26a228
AL		 225static int mv88e6165_phy_read(struct mv88e6xxx_chip *chip,
226 struct mii_bus *bus,
227 int addr, int reg, u16 *val)
efb3e74d
AL		 228{
229 return mv88e6xxx_read(chip, addr, reg, val);
230}
231
ee26a228
AL		 232static int mv88e6165_phy_write(struct mv88e6xxx_chip *chip,
233 struct mii_bus *bus,
234 int addr, int reg, u16 val)
efb3e74d
AL		 235{
236 return mv88e6xxx_write(chip, addr, reg, val);
237}
238
a3c53be5
AL		 239static struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
240{
241 struct mv88e6xxx_mdio_bus *mdio_bus;
242
243 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
244 list);
245 if (!mdio_bus)
246 return NULL;
247
248 return mdio_bus->bus;
249}
250
e57e5e77
VD		 251static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
252 int reg, u16 *val)
253{
254 int addr = phy; /* PHY devices addresses start at 0x0 */
a3c53be5 255 struct mii_bus *bus;
e57e5e77 256
a3c53be5
AL		 257 bus = mv88e6xxx_default_mdio_bus(chip);
258 if (!bus)
e57e5e77
VD		 259 return -EOPNOTSUPP;
260
a3c53be5 261 if (!chip->info->ops->phy_read)
ee26a228
AL		 262 return -EOPNOTSUPP;
263
264 return chip->info->ops->phy_read(chip, bus, addr, reg, val);
e57e5e77
VD		 265}
266
267static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
268 int reg, u16 val)
269{
270 int addr = phy; /* PHY devices addresses start at 0x0 */
a3c53be5 271 struct mii_bus *bus;
e57e5e77 272
a3c53be5
AL		 273 bus = mv88e6xxx_default_mdio_bus(chip);
274 if (!bus)
e57e5e77
VD		 275 return -EOPNOTSUPP;
276
a3c53be5 277 if (!chip->info->ops->phy_write)
ee26a228
AL		 278 return -EOPNOTSUPP;
279
280 return chip->info->ops->phy_write(chip, bus, addr, reg, val);
e57e5e77
VD		 281}
282
09cb7dfd
VD		 283static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
284{
285 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
286 return -EOPNOTSUPP;
287
288 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
289}
290
291static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
292{
293 int err;
294
295 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
297 if (unlikely(err)) {
298 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
299 phy, err);
300 }
301}
302
303static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
304 u8 page, int reg, u16 *val)
305{
306 int err;
307
308 /* There is no paging for registers 22 */
309 if (reg == PHY_PAGE)
310 return -EINVAL;
311
312 err = mv88e6xxx_phy_page_get(chip, phy, page);
313 if (!err) {
314 err = mv88e6xxx_phy_read(chip, phy, reg, val);
315 mv88e6xxx_phy_page_put(chip, phy);
316 }
317
318 return err;
319}
320
321static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
322 u8 page, int reg, u16 val)
323{
324 int err;
325
326 /* There is no paging for registers 22 */
327 if (reg == PHY_PAGE)
328 return -EINVAL;
329
330 err = mv88e6xxx_phy_page_get(chip, phy, page);
331 if (!err) {
332 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
333 mv88e6xxx_phy_page_put(chip, phy);
334 }
335
336 return err;
337}
338
339static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
340{
341 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
342 reg, val);
343}
344
345static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
346{
347 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
348 reg, val);
349}
350
dc30c35b
AL		 351static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
352{
353 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
354 unsigned int n = d->hwirq;
355
356 chip->g1_irq.masked |= (1 << n);
357}
358
359static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
360{
361 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
362 unsigned int n = d->hwirq;
363
364 chip->g1_irq.masked &= ~(1 << n);
365}
366
367static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
368{
369 struct mv88e6xxx_chip *chip = dev_id;
370 unsigned int nhandled = 0;
371 unsigned int sub_irq;
372 unsigned int n;
373 u16 reg;
374 int err;
375
376 mutex_lock(&chip->reg_lock);
377 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
378 mutex_unlock(&chip->reg_lock);
379
380 if (err)
381 goto out;
382
383 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
384 if (reg & (1 << n)) {
385 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
386 handle_nested_irq(sub_irq);
387 ++nhandled;
388 }
389 }
390out:
391 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
392}
393
394static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
395{
396 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
397
398 mutex_lock(&chip->reg_lock);
399}
400
401static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
402{
403 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
404 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
405 u16 reg;
406 int err;
407
408 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
409 if (err)
410 goto out;
411
412 reg &= ~mask;
413 reg |= (~chip->g1_irq.masked & mask);
414
415 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
416 if (err)
417 goto out;
418
419out:
420 mutex_unlock(&chip->reg_lock);
421}
422
423static struct irq_chip mv88e6xxx_g1_irq_chip = {
424 .name = "mv88e6xxx-g1",
425 .irq_mask = mv88e6xxx_g1_irq_mask,
426 .irq_unmask = mv88e6xxx_g1_irq_unmask,
427 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
428 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
429};
430
431static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
432 unsigned int irq,
433 irq_hw_number_t hwirq)
434{
435 struct mv88e6xxx_chip *chip = d->host_data;
436
437 irq_set_chip_data(irq, d->host_data);
438 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
439 irq_set_noprobe(irq);
440
441 return 0;
442}
443
444static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
445 .map = mv88e6xxx_g1_irq_domain_map,
446 .xlate = irq_domain_xlate_twocell,
447};
448
449static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
450{
451 int irq, virq;
3460a577
AL		 452 u16 mask;
453
454 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
455 mask |= GENMASK(chip->g1_irq.nirqs, 0);
456 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
457
458 free_irq(chip->irq, chip);
dc30c35b 459
5edef2f2 460 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
a3db3d3a 461 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 462 irq_dispose_mapping(virq);
463 }
464
a3db3d3a 465 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 466}
467
468static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
469{
3dd0ef05
AL		 470 int err, irq, virq;
471 u16 reg, mask;
dc30c35b
AL		 472
473 chip->g1_irq.nirqs = chip->info->g1_irqs;
474 chip->g1_irq.domain = irq_domain_add_simple(
475 NULL, chip->g1_irq.nirqs, 0,
476 &mv88e6xxx_g1_irq_domain_ops, chip);
477 if (!chip->g1_irq.domain)
478 return -ENOMEM;
479
480 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
481 irq_create_mapping(chip->g1_irq.domain, irq);
482
483 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
484 chip->g1_irq.masked = ~0;
485
3dd0ef05 486 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
dc30c35b 487 if (err)
3dd0ef05 488 goto out_mapping;
dc30c35b 489
3dd0ef05 490 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 491
3dd0ef05 492 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
dc30c35b 493 if (err)
3dd0ef05 494 goto out_disable;
dc30c35b
AL		 495
496 /* Reading the interrupt status clears (most of) them */
497 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
498 if (err)
3dd0ef05 499 goto out_disable;
dc30c35b
AL		 500
501 err = request_threaded_irq(chip->irq, NULL,
502 mv88e6xxx_g1_irq_thread_fn,
503 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
504 dev_name(chip->dev), chip);
505 if (err)
3dd0ef05 506 goto out_disable;
dc30c35b
AL		 507
508 return 0;
509
3dd0ef05
AL		 510out_disable:
511 mask |= GENMASK(chip->g1_irq.nirqs, 0);
512 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
513
514out_mapping:
515 for (irq = 0; irq < 16; irq++) {
516 virq = irq_find_mapping(chip->g1_irq.domain, irq);
517 irq_dispose_mapping(virq);
518 }
519
520 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 521
522 return err;
523}
524
ec561276 525int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 526{
6441e669 527 int i;
2d79af6e 528
6441e669 529 for (i = 0; i < 16; i++) {
2d79af6e
VD		 530 u16 val;
531 int err;
532
533 err = mv88e6xxx_read(chip, addr, reg, &val);
534 if (err)
535 return err;
536
537 if (!(val & mask))
538 return 0;
539
540 usleep_range(1000, 2000);
541 }
542
30853553 543 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 544 return -ETIMEDOUT;
545}
546
f22ab641 547/* Indirect write to single pointer-data register with an Update bit */
ec561276 548int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 549{
550 u16 val;
0f02b4f7 551 int err;
f22ab641
VD		 552
553 /* Wait until the previous operation is completed */
0f02b4f7
AL		 554 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
555 if (err)
556 return err;
f22ab641
VD		 557
558 /* Set the Update bit to trigger a write operation */
559 val = BIT(15) | update;
560
561 return mv88e6xxx_write(chip, addr, reg, val);
562}
563
a935c052 564static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
914b32f6 565{
a199d8b6
VD		 566 if (!chip->info->ops->ppu_disable)
567 return 0;
2e5f0320 568
a199d8b6 569 return chip->info->ops->ppu_disable(chip);
2e5f0320
LB		 570}
571
fad09c73 572static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 573{
a199d8b6
VD		 574 if (!chip->info->ops->ppu_enable)
575 return 0;
2e5f0320 576
a199d8b6 577 return chip->info->ops->ppu_enable(chip);
2e5f0320
LB		 578}
579
580static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
581{
fad09c73 582 struct mv88e6xxx_chip *chip;
2e5f0320 583
fad09c73 584 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 585
fad09c73 586 mutex_lock(&chip->reg_lock);
762eb67b 587
fad09c73
VD		 588 if (mutex_trylock(&chip->ppu_mutex)) {
589 if (mv88e6xxx_ppu_enable(chip) == 0)
590 chip->ppu_disabled = 0;
591 mutex_unlock(&chip->ppu_mutex);
2e5f0320 592 }
762eb67b 593
fad09c73 594 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 595}
596
597static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
598{
fad09c73 599 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 600
fad09c73 601 schedule_work(&chip->ppu_work);
2e5f0320
LB		 602}
603
fad09c73 604static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 605{
2e5f0320
LB		 606 int ret;
607
fad09c73 608 mutex_lock(&chip->ppu_mutex);
2e5f0320 609
3675c8d7 610 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 611 * we can access the PHY registers. If it was already
612 * disabled, cancel the timer that is going to re-enable
613 * it.
614 */
fad09c73
VD		 615 if (!chip->ppu_disabled) {
616 ret = mv88e6xxx_ppu_disable(chip);
85686581 617 if (ret < 0) {
fad09c73 618 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 619 return ret;
620 }
fad09c73 621 chip->ppu_disabled = 1;
2e5f0320 622 } else {
fad09c73 623 del_timer(&chip->ppu_timer);
85686581 624 ret = 0;
2e5f0320
LB		 625 }
626
627 return ret;
628}
629
fad09c73 630static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 631{
3675c8d7 632 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 633 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
634 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 635}
636
fad09c73 637static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 638{
fad09c73
VD		 639 mutex_init(&chip->ppu_mutex);
640 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
68497a87
WY		 641 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
642 (unsigned long)chip);
2e5f0320
LB		 643}
644
930188ce
AL		 645static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
646{
647 del_timer_sync(&chip->ppu_timer);
648}
649
ee26a228
AL		 650static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip,
651 struct mii_bus *bus,
652 int addr, int reg, u16 *val)
2e5f0320 653{
e57e5e77 654 int err;
2e5f0320 655
e57e5e77
VD		 656 err = mv88e6xxx_ppu_access_get(chip);
657 if (!err) {
658 err = mv88e6xxx_read(chip, addr, reg, val);
fad09c73 659 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 660 }
661
e57e5e77 662 return err;
2e5f0320
LB		 663}
664
ee26a228
AL		 665static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip,
666 struct mii_bus *bus,
667 int addr, int reg, u16 val)
2e5f0320 668{
e57e5e77 669 int err;
2e5f0320 670
e57e5e77
VD		 671 err = mv88e6xxx_ppu_access_get(chip);
672 if (!err) {
673 err = mv88e6xxx_write(chip, addr, reg, val);
fad09c73 674 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 675 }
676
e57e5e77 677 return err;
2e5f0320 678}
2e5f0320 679
fad09c73 680static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 681{
fad09c73 682 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 683}
684
fad09c73 685static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 686{
fad09c73 687 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 688}
689
fad09c73 690static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
7c3d0d67 691{
fad09c73 692 return chip->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 693}
694
a75961d0
GC		 695static bool mv88e6xxx_6341_family(struct mv88e6xxx_chip *chip)
696{
697 return chip->info->family == MV88E6XXX_FAMILY_6341;
698}
699
fad09c73 700static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 701{
fad09c73 702 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 703}
704
fad09c73 705static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 706{
fad09c73 707 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 708}
709
d78343d2
VD		 710static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
711 int link, int speed, int duplex,
712 phy_interface_t mode)
713{
714 int err;
715
716 if (!chip->info->ops->port_set_link)
717 return 0;
718
719 /* Port's MAC control must not be changed unless the link is down */
720 err = chip->info->ops->port_set_link(chip, port, 0);
721 if (err)
722 return err;
723
724 if (chip->info->ops->port_set_speed) {
725 err = chip->info->ops->port_set_speed(chip, port, speed);
726 if (err && err != -EOPNOTSUPP)
727 goto restore_link;
728 }
729
730 if (chip->info->ops->port_set_duplex) {
731 err = chip->info->ops->port_set_duplex(chip, port, duplex);
732 if (err && err != -EOPNOTSUPP)
733 goto restore_link;
734 }
735
736 if (chip->info->ops->port_set_rgmii_delay) {
737 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
738 if (err && err != -EOPNOTSUPP)
739 goto restore_link;
740 }
741
f39908d3
AL		 742 if (chip->info->ops->port_set_cmode) {
743 err = chip->info->ops->port_set_cmode(chip, port, mode);
744 if (err && err != -EOPNOTSUPP)
745 goto restore_link;
746 }
747
d78343d2
VD		 748 err = 0;
749restore_link:
750 if (chip->info->ops->port_set_link(chip, port, link))
751 netdev_err(chip->ds->ports[port].netdev,
752 "failed to restore MAC's link\n");
753
754 return err;
755}
756
dea87024
AL		 757/* We expect the switch to perform auto negotiation if there is a real
758 * phy. However, in the case of a fixed link phy, we force the port
759 * settings from the fixed link settings.
760 */
f81ec90f
VD		 761static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
762 struct phy_device *phydev)
dea87024 763{
04bed143 764 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 765 int err;
dea87024
AL		 766
767 if (!phy_is_pseudo_fixed_link(phydev))
768 return;
769
fad09c73 770 mutex_lock(&chip->reg_lock);
d78343d2
VD		 771 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
772 phydev->duplex, phydev->interface);
fad09c73 773 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 774
775 if (err && err != -EOPNOTSUPP)
776 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
dea87024
AL		 777}
778
a605a0fe 779static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 780{
a605a0fe
AL		 781 if (!chip->info->ops->stats_snapshot)
782 return -EOPNOTSUPP;
91da11f8 783
a605a0fe 784 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 785}
786
e413e7e1 787static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 788 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
789 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
790 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
791 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
792 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
793 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
794 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
795 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
796 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
797 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
798 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
799 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
800 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
801 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
802 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
803 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
804 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
805 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
806 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
807 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
808 { "single", 4, 0x14, STATS_TYPE_BANK0, },
809 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
810 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
811 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
812 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
813 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
814 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
815 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
816 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
817 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
818 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
819 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
820 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
821 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
822 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
823 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
824 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
825 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
826 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
827 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
828 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
829 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
830 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
831 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
832 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
833 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
834 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
835 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
836 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
837 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
838 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
839 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
840 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
841 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
842 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
843 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
844 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
845 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
846 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 847};
848
fad09c73 849static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 850 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 851 int port, u16 bank1_select,
852 u16 histogram)
80c4627b 853{
80c4627b
AL		 854 u32 low;
855 u32 high = 0;
dfafe449 856 u16 reg = 0;
0e7b9925 857 int err;
80c4627b
AL		 858 u64 value;
859
f5e2ed02 860 switch (s->type) {
dfafe449 861 case STATS_TYPE_PORT:
0e7b9925
AL		 862 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
863 if (err)
80c4627b
AL		 864 return UINT64_MAX;
865
0e7b9925 866 low = reg;
80c4627b 867 if (s->sizeof_stat == 4) {
0e7b9925
AL		 868 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
869 if (err)
80c4627b 870 return UINT64_MAX;
0e7b9925 871 high = reg;
80c4627b 872 }
f5e2ed02 873 break;
dfafe449 874 case STATS_TYPE_BANK1:
e0d8b615 875 reg = bank1_select;
dfafe449
AL		 876 /* fall through */
877 case STATS_TYPE_BANK0:
e0d8b615 878 reg |= s->reg | histogram;
7f9ef3af 879 mv88e6xxx_g1_stats_read(chip, reg, &low);
80c4627b 880 if (s->sizeof_stat == 8)
7f9ef3af 881 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
80c4627b
AL		 882 }
883 value = (((u64)high) << 16) | low;
884 return value;
885}
886
dfafe449
AL		 887static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
888 uint8_t *data, int types)
91da11f8 889{
f5e2ed02
AL		 890 struct mv88e6xxx_hw_stat *stat;
891 int i, j;
91da11f8 892
f5e2ed02
AL		 893 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
894 stat = &mv88e6xxx_hw_stats[i];
dfafe449 895 if (stat->type & types) {
f5e2ed02
AL		 896 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
897 ETH_GSTRING_LEN);
898 j++;
899 }
91da11f8 900 }
e413e7e1
AL		 901}
902
dfafe449
AL		 903static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
904 uint8_t *data)
905{
906 mv88e6xxx_stats_get_strings(chip, data,
907 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
908}
909
910static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
911 uint8_t *data)
912{
913 mv88e6xxx_stats_get_strings(chip, data,
914 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
915}
916
917static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
918 uint8_t *data)
e413e7e1 919{
04bed143 920 struct mv88e6xxx_chip *chip = ds->priv;
dfafe449
AL		 921
922 if (chip->info->ops->stats_get_strings)
923 chip->info->ops->stats_get_strings(chip, data);
924}
925
926static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
927 int types)
928{
f5e2ed02
AL		 929 struct mv88e6xxx_hw_stat *stat;
930 int i, j;
931
932 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
933 stat = &mv88e6xxx_hw_stats[i];
dfafe449 934 if (stat->type & types)
f5e2ed02
AL		 935 j++;
936 }
937 return j;
e413e7e1
AL		 938}
939
dfafe449
AL		 940static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
941{
942 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
943 STATS_TYPE_PORT);
944}
945
946static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
947{
948 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
949 STATS_TYPE_BANK1);
950}
951
952static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
953{
954 struct mv88e6xxx_chip *chip = ds->priv;
955
956 if (chip->info->ops->stats_get_sset_count)
957 return chip->info->ops->stats_get_sset_count(chip);
958
959 return 0;
960}
961
052f947f 962static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
e0d8b615
AL		 963 uint64_t *data, int types,
964 u16 bank1_select, u16 histogram)
052f947f
AL		 965{
966 struct mv88e6xxx_hw_stat *stat;
967 int i, j;
968
969 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
970 stat = &mv88e6xxx_hw_stats[i];
971 if (stat->type & types) {
e0d8b615
AL		 972 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
973 bank1_select,
974 histogram);
052f947f
AL		 975 j++;
976 }
977 }
978}
979
980static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
981 uint64_t *data)
982{
983 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 984 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
985 0, GLOBAL_STATS_OP_HIST_RX_TX);
052f947f
AL		 986}
987
988static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
989 uint64_t *data)
990{
991 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 992 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
993 GLOBAL_STATS_OP_BANK_1_BIT_9,
994 GLOBAL_STATS_OP_HIST_RX_TX);
995}
996
997static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
998 uint64_t *data)
999{
1000 return mv88e6xxx_stats_get_stats(chip, port, data,
1001 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1002 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
052f947f
AL		 1003}
1004
1005static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1006 uint64_t *data)
1007{
1008 if (chip->info->ops->stats_get_stats)
1009 chip->info->ops->stats_get_stats(chip, port, data);
1010}
1011
f81ec90f
VD		 1012static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1013 uint64_t *data)
e413e7e1 1014{
04bed143 1015 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 1016 int ret;
f5e2ed02 1017
fad09c73 1018 mutex_lock(&chip->reg_lock);
f5e2ed02 1019
a605a0fe 1020 ret = mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 1021 if (ret < 0) {
fad09c73 1022 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 1023 return;
1024 }
052f947f
AL		 1025
1026 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 1027
fad09c73 1028 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 1029}
1030
de227387
AL		 1031static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
1032{
1033 if (chip->info->ops->stats_set_histogram)
1034 return chip->info->ops->stats_set_histogram(chip);
1035
1036 return 0;
1037}
1038
f81ec90f 1039static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 1040{
1041 return 32 * sizeof(u16);
1042}
1043
f81ec90f
VD		 1044static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1045 struct ethtool_regs *regs, void *_p)
a1ab91f3 1046{
04bed143 1047 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 1048 int err;
1049 u16 reg;
a1ab91f3
GR		 1050 u16 *p = _p;
1051 int i;
1052
1053 regs->version = 0;
1054
1055 memset(p, 0xff, 32 * sizeof(u16));
1056
fad09c73 1057 mutex_lock(&chip->reg_lock);
23062513 1058
a1ab91f3 1059 for (i = 0; i < 32; i++) {
a1ab91f3 1060
0e7b9925
AL		 1061 err = mv88e6xxx_port_read(chip, port, i, &reg);
1062 if (!err)
1063 p[i] = reg;
a1ab91f3 1064 }
23062513 1065
fad09c73 1066 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 1067}
1068
f81ec90f
VD		 1069static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1070 struct ethtool_eee *e)
11b3b45d 1071{
04bed143 1072 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1073 u16 reg;
1074 int err;
11b3b45d 1075
fad09c73 1076 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1077 return -EOPNOTSUPP;
1078
fad09c73 1079 mutex_lock(&chip->reg_lock);
2f40c698 1080
9c93829c
VD		 1081 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1082 if (err)
2f40c698 1083 goto out;
11b3b45d
GR		 1084
1085 e->eee_enabled = !!(reg & 0x0200);
1086 e->tx_lpi_enabled = !!(reg & 0x0100);
1087
0e7b9925 1088 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
9c93829c 1089 if (err)
2f40c698 1090 goto out;
11b3b45d 1091
cca8b133 1092 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1093out:
fad09c73 1094 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 1095
1096 return err;
11b3b45d
GR		 1097}
1098
f81ec90f
VD		 1099static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1100 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 1101{
04bed143 1102 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1103 u16 reg;
1104 int err;
11b3b45d 1105
fad09c73 1106 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1107 return -EOPNOTSUPP;
1108
fad09c73 1109 mutex_lock(&chip->reg_lock);
11b3b45d 1110
9c93829c
VD		 1111 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1112 if (err)
2f40c698
AL		 1113 goto out;
1114
9c93829c 1115 reg &= ~0x0300;
2f40c698
AL		 1116 if (e->eee_enabled)
1117 reg |= 0x0200;
1118 if (e->tx_lpi_enabled)
1119 reg |= 0x0100;
1120
9c93829c 1121 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 1122out:
fad09c73 1123 mutex_unlock(&chip->reg_lock);
2f40c698 1124
9c93829c 1125 return err;
11b3b45d
GR		 1126}
1127
fad09c73 1128static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1129{
fad09c73 1130 struct dsa_switch *ds = chip->ds;
fae8a25e 1131 struct net_device *bridge = ds->ports[port].bridge_dev;
b7666efe 1132 u16 output_ports = 0;
b7666efe
VD		 1133 int i;
1134
1135 /* allow CPU port or DSA link(s) to send frames to every port */
1136 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
5a7921f4 1137 output_ports = ~0;
b7666efe 1138 } else {
370b4ffb 1139 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b7666efe 1140 /* allow sending frames to every group member */
fae8a25e 1141 if (bridge && ds->ports[i].bridge_dev == bridge)
b7666efe
VD		 1142 output_ports |= BIT(i);
1143
1144 /* allow sending frames to CPU port and DSA link(s) */
1145 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1146 output_ports |= BIT(i);
1147 }
1148 }
1149
1150 /* prevent frames from going back out of the port they came in on */
1151 output_ports &= ~BIT(port);
facd95b2 1152
5a7921f4 1153 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 1154}
1155
f81ec90f
VD		 1156static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1157 u8 state)
facd95b2 1158{
04bed143 1159 struct mv88e6xxx_chip *chip = ds->priv;
facd95b2 1160 int stp_state;
553eb544 1161 int err;
facd95b2
GR		 1162
1163 switch (state) {
1164 case BR_STATE_DISABLED:
cca8b133 1165 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1166 break;
1167 case BR_STATE_BLOCKING:
1168 case BR_STATE_LISTENING:
cca8b133 1169 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1170 break;
1171 case BR_STATE_LEARNING:
cca8b133 1172 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1173 break;
1174 case BR_STATE_FORWARDING:
1175 default:
cca8b133 1176 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1177 break;
1178 }
1179
fad09c73 1180 mutex_lock(&chip->reg_lock);
e28def33 1181 err = mv88e6xxx_port_set_state(chip, port, stp_state);
fad09c73 1182 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1183
1184 if (err)
e28def33 1185 netdev_err(ds->ports[port].netdev, "failed to update state\n");
facd95b2
GR		 1186}
1187
a2ac29d2
VD		 1188static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1189{
c3a7d4ad
VD		 1190 int err;
1191
daefc943
VD		 1192 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1193 if (err)
1194 return err;
1195
c3a7d4ad
VD		 1196 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1197 if (err)
1198 return err;
1199
a2ac29d2
VD		 1200 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1201}
1202
749efcb8
VD		 1203static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1204{
1205 struct mv88e6xxx_chip *chip = ds->priv;
1206 int err;
1207
1208 mutex_lock(&chip->reg_lock);
e606ca36 1209 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
749efcb8
VD		 1210 mutex_unlock(&chip->reg_lock);
1211
1212 if (err)
1213 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1214}
1215
fad09c73 1216static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1217{
a935c052 1218 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
6b17e864
VD		 1219}
1220
fad09c73 1221static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864 1222{
a935c052 1223 int err;
6b17e864 1224
a935c052
VD		 1225 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1226 if (err)
1227 return err;
6b17e864 1228
fad09c73 1229 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1230}
1231
fad09c73 1232static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1233{
1234 int ret;
1235
fad09c73 1236 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1237 if (ret < 0)
1238 return ret;
1239
fad09c73 1240 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1241}
1242
fad09c73 1243static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1244 struct mv88e6xxx_vtu_entry *entry,
b8fee957
VD		 1245 unsigned int nibble_offset)
1246{
b8fee957 1247 u16 regs[3];
a935c052 1248 int i, err;
b8fee957
VD		 1249
1250 for (i = 0; i < 3; ++i) {
a935c052 1251 u16 *reg = &regs[i];
b8fee957 1252
a935c052
VD		 1253 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1254 if (err)
1255 return err;
b8fee957
VD		 1256 }
1257
370b4ffb 1258 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b8fee957
VD		 1259 unsigned int shift = (i % 4) * 4 + nibble_offset;
1260 u16 reg = regs[i / 4];
1261
1262 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1263 }
1264
1265 return 0;
1266}
1267
fad09c73 1268static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1269 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1270{
fad09c73 1271 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1272}
1273
fad09c73 1274static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1275 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1276{
fad09c73 1277 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1278}
1279
fad09c73 1280static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1281 struct mv88e6xxx_vtu_entry *entry,
7dad08d7
VD		 1282 unsigned int nibble_offset)
1283{
7dad08d7 1284 u16 regs[3] = { 0 };
a935c052 1285 int i, err;
7dad08d7 1286
370b4ffb 1287 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7dad08d7
VD		 1288 unsigned int shift = (i % 4) * 4 + nibble_offset;
1289 u8 data = entry->data[i];
1290
1291 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1292 }
1293
1294 for (i = 0; i < 3; ++i) {
a935c052
VD		 1295 u16 reg = regs[i];
1296
1297 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1298 if (err)
1299 return err;
7dad08d7
VD		 1300 }
1301
1302 return 0;
1303}
1304
fad09c73 1305static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1306 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1307{
fad09c73 1308 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1309}
1310
fad09c73 1311static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1312 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1313{
fad09c73 1314 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1315}
1316
fad09c73 1317static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1318{
a935c052
VD		 1319 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1320 vid & GLOBAL_VTU_VID_MASK);
36d04ba1
VD		 1321}
1322
fad09c73 1323static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b4e47c0f 1324 struct mv88e6xxx_vtu_entry *entry)
b8fee957 1325{
b4e47c0f 1326 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1327 u16 val;
1328 int err;
b8fee957 1329
a935c052
VD		 1330 err = _mv88e6xxx_vtu_wait(chip);
1331 if (err)
1332 return err;
b8fee957 1333
a935c052
VD		 1334 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1335 if (err)
1336 return err;
b8fee957 1337
a935c052
VD		 1338 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1339 if (err)
1340 return err;
b8fee957 1341
a935c052
VD		 1342 next.vid = val & GLOBAL_VTU_VID_MASK;
1343 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
b8fee957
VD		 1344
1345 if (next.valid) {
a935c052
VD		 1346 err = mv88e6xxx_vtu_data_read(chip, &next);
1347 if (err)
1348 return err;
b8fee957 1349
6dc10bbc 1350 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
a935c052
VD		 1351 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1352 if (err)
1353 return err;
b8fee957 1354
a935c052 1355 next.fid = val & GLOBAL_VTU_FID_MASK;
fad09c73 1356 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1357 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1358 * VTU DBNum[3:0] are located in VTU Operation 3:0
1359 */
a935c052
VD		 1360 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1361 if (err)
1362 return err;
11ea809f 1363
a935c052
VD		 1364 next.fid = (val & 0xf00) >> 4;
1365 next.fid |= val & 0xf;
2e7bd5ef 1366 }
b8fee957 1367
fad09c73 1368 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
a935c052
VD		 1369 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1370 if (err)
1371 return err;
b8fee957 1372
a935c052 1373 next.sid = val & GLOBAL_VTU_SID_MASK;
b8fee957
VD		 1374 }
1375 }
1376
1377 *entry = next;
1378 return 0;
1379}
1380
f81ec90f
VD		 1381static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1382 struct switchdev_obj_port_vlan *vlan,
1383 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1384{
04bed143 1385 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1386 struct mv88e6xxx_vtu_entry next;
ceff5eff
VD		 1387 u16 pvid;
1388 int err;
1389
fad09c73 1390 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1391 return -EOPNOTSUPP;
1392
fad09c73 1393 mutex_lock(&chip->reg_lock);
ceff5eff 1394
77064f37 1395 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
ceff5eff
VD		 1396 if (err)
1397 goto unlock;
1398
fad09c73 1399 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1400 if (err)
1401 goto unlock;
1402
1403 do {
fad09c73 1404 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1405 if (err)
1406 break;
1407
1408 if (!next.valid)
1409 break;
1410
1411 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1412 continue;
1413
1414 /* reinit and dump this VLAN obj */
57d32310
VD		 1415 vlan->vid_begin = next.vid;
1416 vlan->vid_end = next.vid;
ceff5eff
VD		 1417 vlan->flags = 0;
1418
1419 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1420 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1421
1422 if (next.vid == pvid)
1423 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1424
1425 err = cb(&vlan->obj);
1426 if (err)
1427 break;
1428 } while (next.vid < GLOBAL_VTU_VID_MASK);
1429
1430unlock:
fad09c73 1431 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1432
1433 return err;
1434}
1435
fad09c73 1436static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1437 struct mv88e6xxx_vtu_entry *entry)
7dad08d7 1438{
11ea809f 1439 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7 1440 u16 reg = 0;
a935c052 1441 int err;
7dad08d7 1442
a935c052
VD		 1443 err = _mv88e6xxx_vtu_wait(chip);
1444 if (err)
1445 return err;
7dad08d7
VD		 1446
1447 if (!entry->valid)
1448 goto loadpurge;
1449
1450 /* Write port member tags */
a935c052
VD		 1451 err = mv88e6xxx_vtu_data_write(chip, entry);
1452 if (err)
1453 return err;
7dad08d7 1454
fad09c73 1455 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1456 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1457 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1458 if (err)
1459 return err;
b426e5f7 1460 }
7dad08d7 1461
6dc10bbc 1462 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
7dad08d7 1463 reg = entry->fid & GLOBAL_VTU_FID_MASK;
a935c052
VD		 1464 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1465 if (err)
1466 return err;
fad09c73 1467 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1468 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1469 * VTU DBNum[3:0] are located in VTU Operation 3:0
1470 */
1471 op |= (entry->fid & 0xf0) << 8;
1472 op |= entry->fid & 0xf;
7dad08d7
VD		 1473 }
1474
1475 reg = GLOBAL_VTU_VID_VALID;
1476loadpurge:
1477 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
a935c052
VD		 1478 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1479 if (err)
1480 return err;
7dad08d7 1481
fad09c73 1482 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1483}
1484
fad09c73 1485static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
b4e47c0f 1486 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1487{
b4e47c0f 1488 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1489 u16 val;
1490 int err;
0d3b33e6 1491
a935c052
VD		 1492 err = _mv88e6xxx_vtu_wait(chip);
1493 if (err)
1494 return err;
0d3b33e6 1495
a935c052
VD		 1496 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1497 sid & GLOBAL_VTU_SID_MASK);
1498 if (err)
1499 return err;
0d3b33e6 1500
a935c052
VD		 1501 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1502 if (err)
1503 return err;
0d3b33e6 1504
a935c052
VD		 1505 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1506 if (err)
1507 return err;
0d3b33e6 1508
a935c052 1509 next.sid = val & GLOBAL_VTU_SID_MASK;
0d3b33e6 1510
a935c052
VD		 1511 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1512 if (err)
1513 return err;
0d3b33e6 1514
a935c052 1515 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
0d3b33e6
VD		 1516
1517 if (next.valid) {
a935c052
VD		 1518 err = mv88e6xxx_stu_data_read(chip, &next);
1519 if (err)
1520 return err;
0d3b33e6
VD		 1521 }
1522
1523 *entry = next;
1524 return 0;
1525}
1526
fad09c73 1527static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1528 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6
VD		 1529{
1530 u16 reg = 0;
a935c052 1531 int err;
0d3b33e6 1532
a935c052
VD		 1533 err = _mv88e6xxx_vtu_wait(chip);
1534 if (err)
1535 return err;
0d3b33e6
VD		 1536
1537 if (!entry->valid)
1538 goto loadpurge;
1539
1540 /* Write port states */
a935c052
VD		 1541 err = mv88e6xxx_stu_data_write(chip, entry);
1542 if (err)
1543 return err;
0d3b33e6
VD		 1544
1545 reg = GLOBAL_VTU_VID_VALID;
1546loadpurge:
a935c052
VD		 1547 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1548 if (err)
1549 return err;
0d3b33e6
VD		 1550
1551 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1552 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1553 if (err)
1554 return err;
0d3b33e6 1555
fad09c73 1556 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1557}
1558
d7f435f9 1559static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1560{
1561 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
b4e47c0f 1562 struct mv88e6xxx_vtu_entry vlan;
2db9ce1f 1563 int i, err;
3285f9e8
VD		 1564
1565 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1566
2db9ce1f 1567 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1568 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1569 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1570 if (err)
1571 return err;
1572
1573 set_bit(*fid, fid_bitmap);
1574 }
1575
3285f9e8 1576 /* Set every FID bit used by the VLAN entries */
fad09c73 1577 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1578 if (err)
1579 return err;
1580
1581 do {
fad09c73 1582 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1583 if (err)
1584 return err;
1585
1586 if (!vlan.valid)
1587 break;
1588
1589 set_bit(vlan.fid, fid_bitmap);
1590 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1591
1592 /* The reset value 0x000 is used to indicate that multiple address
1593 * databases are not needed. Return the next positive available.
1594 */
1595 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1596 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1597 return -ENOSPC;
1598
1599 /* Clear the database */
daefc943 1600 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
3285f9e8
VD		 1601}
1602
fad09c73 1603static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1604 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1605{
fad09c73 1606 struct dsa_switch *ds = chip->ds;
b4e47c0f 1607 struct mv88e6xxx_vtu_entry vlan = {
0d3b33e6
VD		 1608 .valid = true,
1609 .vid = vid,
1610 };
3285f9e8
VD		 1611 int i, err;
1612
d7f435f9 1613 err = mv88e6xxx_atu_new(chip, &vlan.fid);
3285f9e8
VD		 1614 if (err)
1615 return err;
0d3b33e6 1616
3d131f07 1617 /* exclude all ports except the CPU and DSA ports */
370b4ffb 1618 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
3d131f07
VD		 1619 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1620 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1621 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1622
fad09c73 1623 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
a75961d0
GC		 1624 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip) ||
1625 mv88e6xxx_6341_family(chip)) {
b4e47c0f 1626 struct mv88e6xxx_vtu_entry vstp;
0d3b33e6
VD		 1627
1628 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1629 * implemented, only one STU entry is needed to cover all VTU
1630 * entries. Thus, validate the SID 0.
1631 */
1632 vlan.sid = 0;
fad09c73 1633 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1634 if (err)
1635 return err;
1636
1637 if (vstp.sid != vlan.sid || !vstp.valid) {
1638 memset(&vstp, 0, sizeof(vstp));
1639 vstp.valid = true;
1640 vstp.sid = vlan.sid;
1641
fad09c73 1642 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1643 if (err)
1644 return err;
1645 }
0d3b33e6
VD		 1646 }
1647
1648 *entry = vlan;
1649 return 0;
1650}
1651
fad09c73 1652static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1653 struct mv88e6xxx_vtu_entry *entry, bool creat)
2fb5ef09
VD		 1654{
1655 int err;
1656
1657 if (!vid)
1658 return -EINVAL;
1659
fad09c73 1660 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1661 if (err)
1662 return err;
1663
fad09c73 1664 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1665 if (err)
1666 return err;
1667
1668 if (entry->vid != vid || !entry->valid) {
1669 if (!creat)
1670 return -EOPNOTSUPP;
1671 /* -ENOENT would've been more appropriate, but switchdev expects
1672 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1673 */
1674
fad09c73 1675 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1676 }
1677
1678 return err;
1679}
1680
da9c359e
VD		 1681static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1682 u16 vid_begin, u16 vid_end)
1683{
04bed143 1684 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1685 struct mv88e6xxx_vtu_entry vlan;
da9c359e
VD		 1686 int i, err;
1687
1688 if (!vid_begin)
1689 return -EOPNOTSUPP;
1690
fad09c73 1691 mutex_lock(&chip->reg_lock);
da9c359e 1692
fad09c73 1693 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1694 if (err)
1695 goto unlock;
1696
1697 do {
fad09c73 1698 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1699 if (err)
1700 goto unlock;
1701
1702 if (!vlan.valid)
1703 break;
1704
1705 if (vlan.vid > vid_end)
1706 break;
1707
370b4ffb 1708 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1709 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1710 continue;
1711
66e2809d
AL		 1712 if (!ds->ports[port].netdev)
1713 continue;
1714
da9c359e
VD		 1715 if (vlan.data[i] ==
1716 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1717 continue;
1718
fae8a25e
VD		 1719 if (ds->ports[i].bridge_dev ==
1720 ds->ports[port].bridge_dev)
da9c359e
VD		 1721 break; /* same bridge, check next VLAN */
1722
fae8a25e 1723 if (!ds->ports[i].bridge_dev)
66e2809d
AL		 1724 continue;
1725
c8b09808 1726 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1727 "hardware VLAN %d already used by %s\n",
1728 vlan.vid,
fae8a25e 1729 netdev_name(ds->ports[i].bridge_dev));
da9c359e
VD		 1730 err = -EOPNOTSUPP;
1731 goto unlock;
1732 }
1733 } while (vlan.vid < vid_end);
1734
1735unlock:
fad09c73 1736 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1737
1738 return err;
1739}
1740
f81ec90f
VD		 1741static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1742 bool vlan_filtering)
214cdb99 1743{
04bed143 1744 struct mv88e6xxx_chip *chip = ds->priv;
385a0995 1745 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
214cdb99 1746 PORT_CONTROL_2_8021Q_DISABLED;
0e7b9925 1747 int err;
214cdb99 1748
fad09c73 1749 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1750 return -EOPNOTSUPP;
1751
fad09c73 1752 mutex_lock(&chip->reg_lock);
385a0995 1753 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1754 mutex_unlock(&chip->reg_lock);
214cdb99 1755
0e7b9925 1756 return err;
214cdb99
VD		 1757}
1758
57d32310
VD		 1759static int
1760mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1761 const struct switchdev_obj_port_vlan *vlan,
1762 struct switchdev_trans *trans)
76e398a6 1763{
04bed143 1764 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1765 int err;
1766
fad09c73 1767 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1768 return -EOPNOTSUPP;
1769
da9c359e
VD		 1770 /* If the requested port doesn't belong to the same bridge as the VLAN
1771 * members, do not support it (yet) and fallback to software VLAN.
1772 */
1773 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1774 vlan->vid_end);
1775 if (err)
1776 return err;
1777
76e398a6
VD		 1778 /* We don't need any dynamic resource from the kernel (yet),
1779 * so skip the prepare phase.
1780 */
1781 return 0;
1782}
1783
fad09c73 1784static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1785 u16 vid, bool untagged)
0d3b33e6 1786{
b4e47c0f 1787 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1788 int err;
1789
fad09c73 1790 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1791 if (err)
76e398a6 1792 return err;
0d3b33e6 1793
0d3b33e6
VD		 1794 vlan.data[port] = untagged ?
1795 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1796 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1797
fad09c73 1798 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1799}
1800
f81ec90f
VD		 1801static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1802 const struct switchdev_obj_port_vlan *vlan,
1803 struct switchdev_trans *trans)
76e398a6 1804{
04bed143 1805 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1806 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1807 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1808 u16 vid;
76e398a6 1809
fad09c73 1810 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1811 return;
1812
fad09c73 1813 mutex_lock(&chip->reg_lock);
76e398a6 1814
4d5770b3 1815 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1816 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1817 netdev_err(ds->ports[port].netdev,
1818 "failed to add VLAN %d%c\n",
4d5770b3 1819 vid, untagged ? 'u' : 't');
76e398a6 1820
77064f37 1821 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
c8b09808 1822 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1823 vlan->vid_end);
0d3b33e6 1824
fad09c73 1825 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1826}
1827
fad09c73 1828static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1829 int port, u16 vid)
7dad08d7 1830{
fad09c73 1831 struct dsa_switch *ds = chip->ds;
b4e47c0f 1832 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1833 int i, err;
1834
fad09c73 1835 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1836 if (err)
76e398a6 1837 return err;
7dad08d7 1838
2fb5ef09
VD		 1839 /* Tell switchdev if this VLAN is handled in software */
1840 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1841 return -EOPNOTSUPP;
7dad08d7
VD		 1842
1843 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1844
1845 /* keep the VLAN unless all ports are excluded */
f02bdffc 1846 vlan.valid = false;
370b4ffb 1847 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
3d131f07 1848 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1849 continue;
1850
1851 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1852 vlan.valid = true;
7dad08d7
VD		 1853 break;
1854 }
1855 }
1856
fad09c73 1857 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1858 if (err)
1859 return err;
1860
e606ca36 1861 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1862}
1863
f81ec90f
VD		 1864static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1865 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1866{
04bed143 1867 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1868 u16 pvid, vid;
1869 int err = 0;
1870
fad09c73 1871 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1872 return -EOPNOTSUPP;
1873
fad09c73 1874 mutex_lock(&chip->reg_lock);
76e398a6 1875
77064f37 1876 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1877 if (err)
1878 goto unlock;
1879
76e398a6 1880 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1881 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1882 if (err)
1883 goto unlock;
1884
1885 if (vid == pvid) {
77064f37 1886 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1887 if (err)
1888 goto unlock;
1889 }
1890 }
1891
7dad08d7 1892unlock:
fad09c73 1893 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 1894
1895 return err;
1896}
1897
83dabd1f
VD		 1898static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1899 const unsigned char *addr, u16 vid,
1900 u8 state)
fd231c82 1901{
b4e47c0f 1902 struct mv88e6xxx_vtu_entry vlan;
88472939 1903 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 1904 int err;
1905
2db9ce1f
VD		 1906 /* Null VLAN ID corresponds to the port private database */
1907 if (vid == 0)
b4e48c50 1908 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2db9ce1f 1909 else
fad09c73 1910 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 1911 if (err)
1912 return err;
fd231c82 1913
dabc1a96
VD		 1914 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1915 ether_addr_copy(entry.mac, addr);
1916 eth_addr_dec(entry.mac);
1917
1918 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
88472939
VD		 1919 if (err)
1920 return err;
1921
dabc1a96
VD		 1922 /* Initialize a fresh ATU entry if it isn't found */
1923 if (entry.state == GLOBAL_ATU_DATA_STATE_UNUSED ||
1924 !ether_addr_equal(entry.mac, addr)) {
1925 memset(&entry, 0, sizeof(entry));
1926 ether_addr_copy(entry.mac, addr);
1927 }
1928
88472939
VD		 1929 /* Purge the ATU entry only if no port is using it anymore */
1930 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
01bd96c8
VD		 1931 entry.portvec &= ~BIT(port);
1932 if (!entry.portvec)
88472939
VD		 1933 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1934 } else {
01bd96c8 1935 entry.portvec |= BIT(port);
88472939 1936 entry.state = state;
fd231c82
VD		 1937 }
1938
9c13c026 1939 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
87820510
VD		 1940}
1941
f81ec90f
VD		 1942static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1943 const struct switchdev_obj_port_fdb *fdb,
1944 struct switchdev_trans *trans)
146a3206
VD		 1945{
1946 /* We don't need any dynamic resource from the kernel (yet),
1947 * so skip the prepare phase.
1948 */
1949 return 0;
1950}
1951
f81ec90f
VD		 1952static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1953 const struct switchdev_obj_port_fdb *fdb,
1954 struct switchdev_trans *trans)
87820510 1955{
04bed143 1956 struct mv88e6xxx_chip *chip = ds->priv;
87820510 1957
fad09c73 1958 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 1959 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
1960 GLOBAL_ATU_DATA_STATE_UC_STATIC))
1961 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
fad09c73 1962 mutex_unlock(&chip->reg_lock);
87820510
VD		 1963}
1964
f81ec90f
VD		 1965static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1966 const struct switchdev_obj_port_fdb *fdb)
87820510 1967{
04bed143 1968 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 1969 int err;
87820510 1970
fad09c73 1971 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 1972 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
1973 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 1974 mutex_unlock(&chip->reg_lock);
87820510 1975
83dabd1f 1976 return err;
87820510
VD		 1977}
1978
83dabd1f
VD		 1979static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1980 u16 fid, u16 vid, int port,
1981 struct switchdev_obj *obj,
1982 int (*cb)(struct switchdev_obj *obj))
74b6ba0d 1983{
dabc1a96 1984 struct mv88e6xxx_atu_entry addr;
74b6ba0d
VD		 1985 int err;
1986
dabc1a96
VD		 1987 addr.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1988 eth_broadcast_addr(addr.mac);
74b6ba0d
VD		 1989
1990 do {
dabc1a96 1991 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
74b6ba0d 1992 if (err)
83dabd1f 1993 return err;
74b6ba0d
VD		 1994
1995 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
1996 break;
1997
01bd96c8 1998 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
83dabd1f
VD		 1999 continue;
2000
2001 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2002 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 2003
83dabd1f
VD		 2004 if (!is_unicast_ether_addr(addr.mac))
2005 continue;
2006
2007 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 2008 fdb->vid = vid;
2009 ether_addr_copy(fdb->addr, addr.mac);
83dabd1f
VD		 2010 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2011 fdb->ndm_state = NUD_NOARP;
2012 else
2013 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 2014 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2015 struct switchdev_obj_port_mdb *mdb;
2016
2017 if (!is_multicast_ether_addr(addr.mac))
2018 continue;
2019
2020 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2021 mdb->vid = vid;
2022 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 2023 } else {
2024 return -EOPNOTSUPP;
74b6ba0d 2025 }
83dabd1f
VD		 2026
2027 err = cb(obj);
2028 if (err)
2029 return err;
74b6ba0d
VD		 2030 } while (!is_broadcast_ether_addr(addr.mac));
2031
2032 return err;
2033}
2034
83dabd1f
VD		 2035static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2036 struct switchdev_obj *obj,
2037 int (*cb)(struct switchdev_obj *obj))
f33475bd 2038{
b4e47c0f 2039 struct mv88e6xxx_vtu_entry vlan = {
f33475bd
VD		 2040 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2041 };
2db9ce1f 2042 u16 fid;
f33475bd
VD		 2043 int err;
2044
2db9ce1f 2045 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 2046 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 2047 if (err)
83dabd1f 2048 return err;
2db9ce1f 2049
83dabd1f 2050 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 2051 if (err)
83dabd1f 2052 return err;
2db9ce1f 2053
74b6ba0d 2054 /* Dump VLANs' Filtering Information Databases */
fad09c73 2055 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd 2056 if (err)
83dabd1f 2057 return err;
f33475bd
VD		 2058
2059 do {
fad09c73 2060 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2061 if (err)
83dabd1f 2062 return err;
f33475bd
VD		 2063
2064 if (!vlan.valid)
2065 break;
2066
83dabd1f
VD		 2067 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2068 obj, cb);
f33475bd 2069 if (err)
83dabd1f 2070 return err;
f33475bd
VD		 2071 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2072
83dabd1f
VD		 2073 return err;
2074}
2075
2076static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2077 struct switchdev_obj_port_fdb *fdb,
2078 int (*cb)(struct switchdev_obj *obj))
2079{
04bed143 2080 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 2081 int err;
2082
2083 mutex_lock(&chip->reg_lock);
2084 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 2085 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2086
2087 return err;
2088}
2089
f81ec90f 2090static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
fae8a25e 2091 struct net_device *br)
e79a8bcb 2092{
04bed143 2093 struct mv88e6xxx_chip *chip = ds->priv;
1d9619d5 2094 int i, err = 0;
466dfa07 2095
fad09c73 2096 mutex_lock(&chip->reg_lock);
466dfa07 2097
fae8a25e 2098 /* Remap each port's VLANTable */
370b4ffb 2099 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
fae8a25e 2100 if (ds->ports[i].bridge_dev == br) {
fad09c73 2101 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2102 if (err)
2103 break;
2104 }
2105 }
2106
fad09c73 2107 mutex_unlock(&chip->reg_lock);
a6692754 2108
466dfa07 2109 return err;
e79a8bcb
VD		 2110}
2111
f123f2fb
VD		 2112static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2113 struct net_device *br)
66d9cd0f 2114{
04bed143 2115 struct mv88e6xxx_chip *chip = ds->priv;
16bfa702 2116 int i;
466dfa07 2117
fad09c73 2118 mutex_lock(&chip->reg_lock);
466dfa07 2119
fae8a25e 2120 /* Remap each port's VLANTable */
370b4ffb 2121 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
fae8a25e 2122 if (i == port || ds->ports[i].bridge_dev == br)
fad09c73 2123 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2124 netdev_warn(ds->ports[i].netdev,
2125 "failed to remap\n");
b7666efe 2126
fad09c73 2127 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2128}
2129
17e708ba
VD		 2130static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2131{
2132 if (chip->info->ops->reset)
2133 return chip->info->ops->reset(chip);
2134
2135 return 0;
2136}
2137
309eca6d
VD		 2138static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2139{
2140 struct gpio_desc *gpiod = chip->reset;
2141
2142 /* If there is a GPIO connected to the reset pin, toggle it */
2143 if (gpiod) {
2144 gpiod_set_value_cansleep(gpiod, 1);
2145 usleep_range(10000, 20000);
2146 gpiod_set_value_cansleep(gpiod, 0);
2147 usleep_range(10000, 20000);
2148 }
2149}
2150
4ac4b5a6 2151static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
552238b5 2152{
4ac4b5a6 2153 int i, err;
552238b5 2154
4ac4b5a6 2155 /* Set all ports to the Disabled state */
370b4ffb 2156 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
e28def33
VD		 2157 err = mv88e6xxx_port_set_state(chip, i,
2158 PORT_CONTROL_STATE_DISABLED);
0e7b9925
AL		 2159 if (err)
2160 return err;
552238b5
VD		 2161 }
2162
4ac4b5a6
VD		 2163 /* Wait for transmit queues to drain,
2164 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2165 */
552238b5
VD		 2166 usleep_range(2000, 4000);
2167
4ac4b5a6
VD		 2168 return 0;
2169}
2170
2171static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2172{
4ac4b5a6
VD		 2173 int err;
2174
2175 err = mv88e6xxx_disable_ports(chip);
2176 if (err)
2177 return err;
2178
309eca6d 2179 mv88e6xxx_hardware_reset(chip);
552238b5 2180
17e708ba 2181 return mv88e6xxx_software_reset(chip);
552238b5
VD		 2182}
2183
09cb7dfd 2184static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
13a7ebb3 2185{
09cb7dfd
VD		 2186 u16 val;
2187 int err;
13a7ebb3 2188
09cb7dfd
VD		 2189 /* Clear Power Down bit */
2190 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2191 if (err)
2192 return err;
13a7ebb3 2193
09cb7dfd
VD		 2194 if (val & BMCR_PDOWN) {
2195 val &= ~BMCR_PDOWN;
2196 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
13a7ebb3
PU		 2197 }
2198
09cb7dfd 2199 return err;
13a7ebb3
PU		 2200}
2201
4314557c
VD		 2202static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2203 enum mv88e6xxx_frame_mode frame, u16 egress,
2204 u16 etype)
56995cbc
AL		 2205{
2206 int err;
2207
4314557c
VD		 2208 if (!chip->info->ops->port_set_frame_mode)
2209 return -EOPNOTSUPP;
2210
2211 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
56995cbc
AL		 2212 if (err)
2213 return err;
2214
4314557c
VD		 2215 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2216 if (err)
2217 return err;
2218
2219 if (chip->info->ops->port_set_ether_type)
2220 return chip->info->ops->port_set_ether_type(chip, port, etype);
2221
2222 return 0;
56995cbc
AL		 2223}
2224
4314557c 2225static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
56995cbc 2226{
4314557c
VD		 2227 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2228 PORT_CONTROL_EGRESS_UNMODIFIED,
2229 PORT_ETH_TYPE_DEFAULT);
2230}
56995cbc 2231
4314557c
VD		 2232static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2233{
2234 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2235 PORT_CONTROL_EGRESS_UNMODIFIED,
2236 PORT_ETH_TYPE_DEFAULT);
2237}
56995cbc 2238
4314557c
VD		 2239static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2240{
2241 return mv88e6xxx_set_port_mode(chip, port,
2242 MV88E6XXX_FRAME_MODE_ETHERTYPE,
2243 PORT_CONTROL_EGRESS_ADD_TAG, ETH_P_EDSA);
2244}
56995cbc 2245
4314557c
VD		 2246static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2247{
2248 if (dsa_is_dsa_port(chip->ds, port))
2249 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 2250
4314557c
VD		 2251 if (dsa_is_normal_port(chip->ds, port))
2252 return mv88e6xxx_set_port_mode_normal(chip, port);
56995cbc 2253
4314557c
VD		 2254 /* Setup CPU port mode depending on its supported tag format */
2255 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2256 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 2257
4314557c
VD		 2258 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2259 return mv88e6xxx_set_port_mode_edsa(chip, port);
56995cbc 2260
4314557c 2261 return -EINVAL;
56995cbc
AL		 2262}
2263
601aeed3 2264static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
56995cbc 2265{
601aeed3 2266 bool message = dsa_is_dsa_port(chip->ds, port);
56995cbc 2267
601aeed3 2268 return mv88e6xxx_port_set_message_port(chip, port, message);
4314557c 2269}
56995cbc 2270
601aeed3 2271static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
4314557c 2272{
601aeed3 2273 bool flood = port == dsa_upstream_port(chip->ds);
56995cbc 2274
601aeed3
VD		 2275 /* Upstream ports flood frames with unknown unicast or multicast DA */
2276 if (chip->info->ops->port_set_egress_floods)
2277 return chip->info->ops->port_set_egress_floods(chip, port,
2278 flood, flood);
ea698f4f 2279
601aeed3 2280 return 0;
ea698f4f
VD		 2281}
2282
fad09c73 2283static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2284{
fad09c73 2285 struct dsa_switch *ds = chip->ds;
0e7b9925 2286 int err;
54d792f2 2287 u16 reg;
d827e88a 2288
d78343d2
VD		 2289 /* MAC Forcing register: don't force link, speed, duplex or flow control
2290 * state to any particular values on physical ports, but force the CPU
2291 * port and all DSA ports to their maximum bandwidth and full duplex.
2292 */
2293 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2294 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2295 SPEED_MAX, DUPLEX_FULL,
2296 PHY_INTERFACE_MODE_NA);
2297 else
2298 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2299 SPEED_UNFORCED, DUPLEX_UNFORCED,
2300 PHY_INTERFACE_MODE_NA);
2301 if (err)
2302 return err;
54d792f2
AL		 2303
2304 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2305 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2306 * tunneling, determine priority by looking at 802.1p and IP
2307 * priority fields (IP prio has precedence), and set STP state
2308 * to Forwarding.
2309 *
2310 * If this is the CPU link, use DSA or EDSA tagging depending
2311 * on which tagging mode was configured.
2312 *
2313 * If this is a link to another switch, use DSA tagging mode.
2314 *
2315 * If this is the upstream port for this switch, enable
2316 * forwarding of unknown unicasts and multicasts.
2317 */
56995cbc 2318 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
54d792f2
AL		 2319 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2320 PORT_CONTROL_STATE_FORWARDING;
56995cbc
AL		 2321 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2322 if (err)
2323 return err;
6083ce71 2324
601aeed3 2325 err = mv88e6xxx_setup_port_mode(chip, port);
56995cbc
AL		 2326 if (err)
2327 return err;
54d792f2 2328
601aeed3 2329 err = mv88e6xxx_setup_egress_floods(chip, port);
4314557c
VD		 2330 if (err)
2331 return err;
2332
13a7ebb3
PU		 2333 /* If this port is connected to a SerDes, make sure the SerDes is not
2334 * powered down.
2335 */
09cb7dfd 2336 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
0e7b9925
AL		 2337 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2338 if (err)
2339 return err;
2340 reg &= PORT_STATUS_CMODE_MASK;
2341 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2342 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2343 (reg == PORT_STATUS_CMODE_SGMII)) {
2344 err = mv88e6xxx_serdes_power_on(chip);
2345 if (err < 0)
2346 return err;
13a7ebb3
PU		 2347 }
2348 }
2349
8efdda4a 2350 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2351 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2352 * untagged frames on this port, do a destination address lookup on all
2353 * received packets as usual, disable ARP mirroring and don't send a
2354 * copy of all transmitted/received frames on this port to the CPU.
54d792f2 2355 */
a23b2961
AL		 2356 err = mv88e6xxx_port_set_map_da(chip, port);
2357 if (err)
2358 return err;
8efdda4a 2359
a23b2961
AL		 2360 reg = 0;
2361 if (chip->info->ops->port_set_upstream_port) {
2362 err = chip->info->ops->port_set_upstream_port(
2363 chip, port, dsa_upstream_port(ds));
0e7b9925
AL		 2364 if (err)
2365 return err;
54d792f2
AL		 2366 }
2367
a23b2961
AL		 2368 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2369 PORT_CONTROL_2_8021Q_DISABLED);
2370 if (err)
2371 return err;
2372
5f436666
AL		 2373 if (chip->info->ops->port_jumbo_config) {
2374 err = chip->info->ops->port_jumbo_config(chip, port);
2375 if (err)
2376 return err;
2377 }
2378
54d792f2
AL		 2379 /* Port Association Vector: when learning source addresses
2380 * of packets, add the address to the address database using
2381 * a port bitmap that has only the bit for this port set and
2382 * the other bits clear.
2383 */
4c7ea3c0 2384 reg = 1 << port;
996ecb82
VD		 2385 /* Disable learning for CPU port */
2386 if (dsa_is_cpu_port(ds, port))
65fa4027 2387 reg = 0;
4c7ea3c0 2388
0e7b9925
AL		 2389 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2390 if (err)
2391 return err;
54d792f2
AL		 2392
2393 /* Egress rate control 2: disable egress rate control. */
0e7b9925
AL		 2394 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2395 if (err)
2396 return err;
54d792f2 2397
b35d322a
AL		 2398 if (chip->info->ops->port_pause_config) {
2399 err = chip->info->ops->port_pause_config(chip, port);
0e7b9925
AL		 2400 if (err)
2401 return err;
b35d322a 2402 }
54d792f2 2403
b35d322a
AL		 2404 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2405 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
a75961d0 2406 mv88e6xxx_6320_family(chip) || mv88e6xxx_6341_family(chip)) {
54d792f2
AL		 2407 /* Port ATU control: disable limiting the number of
2408 * address database entries that this port is allowed
2409 * to use.
2410 */
0e7b9925
AL		 2411 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2412 0x0000);
54d792f2
AL		 2413 /* Priority Override: disable DA, SA and VTU priority
2414 * override.
2415 */
0e7b9925
AL		 2416 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2417 0x0000);
2418 if (err)
2419 return err;
ef0a7318 2420 }
2bbb33be 2421
ef0a7318
AL		 2422 if (chip->info->ops->port_tag_remap) {
2423 err = chip->info->ops->port_tag_remap(chip, port);
0e7b9925
AL		 2424 if (err)
2425 return err;
54d792f2
AL		 2426 }
2427
ef70b111
AL		 2428 if (chip->info->ops->port_egress_rate_limiting) {
2429 err = chip->info->ops->port_egress_rate_limiting(chip, port);
0e7b9925
AL		 2430 if (err)
2431 return err;
54d792f2
AL		 2432 }
2433
ea698f4f 2434 err = mv88e6xxx_setup_message_port(chip, port);
0e7b9925
AL		 2435 if (err)
2436 return err;
d827e88a 2437
207afda1 2438 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2439 * database, and allow bidirectional communication between the
2440 * CPU and DSA port(s), and the other ports.
d827e88a 2441 */
b4e48c50 2442 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 2443 if (err)
2444 return err;
2db9ce1f 2445
0e7b9925
AL		 2446 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2447 if (err)
2448 return err;
d827e88a
GR		 2449
2450 /* Default VLAN ID and priority: don't set a default VLAN
2451 * ID, and set the default packet priority to zero.
2452 */
0e7b9925 2453 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
dbde9e66
AL		 2454}
2455
aa0938c6 2456static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3b4caa1b
VD		 2457{
2458 int err;
2459
a935c052 2460 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
3b4caa1b
VD		 2461 if (err)
2462 return err;
2463
a935c052 2464 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
3b4caa1b
VD		 2465 if (err)
2466 return err;
2467
a935c052
VD		 2468 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2469 if (err)
2470 return err;
2471
2472 return 0;
3b4caa1b
VD		 2473}
2474
2cfcd964
VD		 2475static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2476 unsigned int ageing_time)
2477{
04bed143 2478 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2479 int err;
2480
2481 mutex_lock(&chip->reg_lock);
720c6343 2482 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2cfcd964
VD		 2483 mutex_unlock(&chip->reg_lock);
2484
2485 return err;
2486}
2487
9729934c 2488static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2489{
fad09c73 2490 struct dsa_switch *ds = chip->ds;
b0745e87 2491 u32 upstream_port = dsa_upstream_port(ds);
552238b5 2492 int err;
54d792f2 2493
119477bd
VD		 2494 /* Enable the PHY Polling Unit if present, don't discard any packets,
2495 * and mask all interrupt sources.
2496 */
a199d8b6 2497 err = mv88e6xxx_ppu_enable(chip);
119477bd
VD		 2498 if (err)
2499 return err;
2500
33641994
AL		 2501 if (chip->info->ops->g1_set_cpu_port) {
2502 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port);
2503 if (err)
2504 return err;
2505 }
2506
2507 if (chip->info->ops->g1_set_egress_port) {
2508 err = chip->info->ops->g1_set_egress_port(chip, upstream_port);
2509 if (err)
2510 return err;
2511 }
b0745e87 2512
50484ff4 2513 /* Disable remote management, and set the switch's DSA device number. */
a935c052
VD		 2514 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2515 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2516 (ds->index & 0x1f));
50484ff4
VD		 2517 if (err)
2518 return err;
2519
acddbd21
VD		 2520 /* Clear all the VTU and STU entries */
2521 err = _mv88e6xxx_vtu_stu_flush(chip);
2522 if (err < 0)
2523 return err;
2524
54d792f2 2525 /* Configure the IP ToS mapping registers. */
a935c052 2526 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2527 if (err)
08a01261 2528 return err;
a935c052 2529 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2530 if (err)
08a01261 2531 return err;
a935c052 2532 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2533 if (err)
08a01261 2534 return err;
a935c052 2535 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2536 if (err)
08a01261 2537 return err;
a935c052 2538 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2539 if (err)
08a01261 2540 return err;
a935c052 2541 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2542 if (err)
08a01261 2543 return err;
a935c052 2544 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2545 if (err)
08a01261 2546 return err;
a935c052 2547 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2548 if (err)
08a01261 2549 return err;
54d792f2
AL		 2550
2551 /* Configure the IEEE 802.1p priority mapping register. */
a935c052 2552 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2553 if (err)
08a01261 2554 return err;
54d792f2 2555
de227387
AL		 2556 /* Initialize the statistics unit */
2557 err = mv88e6xxx_stats_set_histogram(chip);
2558 if (err)
2559 return err;
2560
9729934c 2561 /* Clear the statistics counters for all ports */
a935c052
VD		 2562 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2563 GLOBAL_STATS_OP_FLUSH_ALL);
9729934c
VD		 2564 if (err)
2565 return err;
2566
2567 /* Wait for the flush to complete. */
7f9ef3af 2568 err = mv88e6xxx_g1_stats_wait(chip);
9729934c
VD		 2569 if (err)
2570 return err;
2571
2572 return 0;
2573}
2574
f81ec90f 2575static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2576{
04bed143 2577 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2578 int err;
a1a6a4d1
VD		 2579 int i;
2580
fad09c73 2581 chip->ds = ds;
a3c53be5 2582 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
08a01261 2583
fad09c73 2584 mutex_lock(&chip->reg_lock);
08a01261 2585
9729934c 2586 /* Setup Switch Port Registers */
370b4ffb 2587 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
9729934c
VD		 2588 err = mv88e6xxx_setup_port(chip, i);
2589 if (err)
2590 goto unlock;
2591 }
2592
2593 /* Setup Switch Global 1 Registers */
2594 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2595 if (err)
2596 goto unlock;
2597
9729934c
VD		 2598 /* Setup Switch Global 2 Registers */
2599 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2600 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2601 if (err)
2602 goto unlock;
2603 }
08a01261 2604
a2ac29d2
VD		 2605 err = mv88e6xxx_atu_setup(chip);
2606 if (err)
2607 goto unlock;
2608
6e55f698
AL		 2609 /* Some generations have the configuration of sending reserved
2610 * management frames to the CPU in global2, others in
2611 * global1. Hence it does not fit the two setup functions
2612 * above.
2613 */
2614 if (chip->info->ops->mgmt_rsvd2cpu) {
2615 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2616 if (err)
2617 goto unlock;
2618 }
2619
6b17e864 2620unlock:
fad09c73 2621 mutex_unlock(&chip->reg_lock);
db687a56 2622
48ace4ef 2623 return err;
54d792f2
AL		 2624}
2625
3b4caa1b
VD		 2626static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2627{
04bed143 2628 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2629 int err;
2630
b073d4e2
VD		 2631 if (!chip->info->ops->set_switch_mac)
2632 return -EOPNOTSUPP;
3b4caa1b 2633
b073d4e2
VD		 2634 mutex_lock(&chip->reg_lock);
2635 err = chip->info->ops->set_switch_mac(chip, addr);
3b4caa1b
VD		 2636 mutex_unlock(&chip->reg_lock);
2637
2638 return err;
2639}
2640
e57e5e77 2641static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2642{
0dd12d54
AL		 2643 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2644 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77
VD		 2645 u16 val;
2646 int err;
fd3a0ee4 2647
ee26a228
AL		 2648 if (!chip->info->ops->phy_read)
2649 return -EOPNOTSUPP;
2650
fad09c73 2651 mutex_lock(&chip->reg_lock);
ee26a228 2652 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
fad09c73 2653 mutex_unlock(&chip->reg_lock);
e57e5e77 2654
da9f3301
AL		 2655 if (reg == MII_PHYSID2) {
2656 /* Some internal PHYS don't have a model number. Use
2657 * the mv88e6390 family model number instead.
2658 */
2659 if (!(val & 0x3f0))
2660 val |= PORT_SWITCH_ID_PROD_NUM_6390;
2661 }
2662
e57e5e77 2663 return err ? err : val;
fd3a0ee4
AL		 2664}
2665
e57e5e77 2666static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2667{
0dd12d54
AL		 2668 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2669 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77 2670 int err;
fd3a0ee4 2671
ee26a228
AL		 2672 if (!chip->info->ops->phy_write)
2673 return -EOPNOTSUPP;
2674
fad09c73 2675 mutex_lock(&chip->reg_lock);
ee26a228 2676 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
fad09c73 2677 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2678
2679 return err;
fd3a0ee4
AL		 2680}
2681
fad09c73 2682static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
a3c53be5
AL		 2683 struct device_node *np,
2684 bool external)
b516d453
AL		 2685{
2686 static int index;
0dd12d54 2687 struct mv88e6xxx_mdio_bus *mdio_bus;
b516d453
AL		 2688 struct mii_bus *bus;
2689 int err;
2690
0dd12d54 2691 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
b516d453
AL		 2692 if (!bus)
2693 return -ENOMEM;
2694
0dd12d54 2695 mdio_bus = bus->priv;
a3c53be5 2696 mdio_bus->bus = bus;
0dd12d54 2697 mdio_bus->chip = chip;
a3c53be5
AL		 2698 INIT_LIST_HEAD(&mdio_bus->list);
2699 mdio_bus->external = external;
0dd12d54 2700
b516d453
AL		 2701 if (np) {
2702 bus->name = np->full_name;
2703 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2704 } else {
2705 bus->name = "mv88e6xxx SMI";
2706 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2707 }
2708
2709 bus->read = mv88e6xxx_mdio_read;
2710 bus->write = mv88e6xxx_mdio_write;
fad09c73 2711 bus->parent = chip->dev;
b516d453 2712
a3c53be5
AL		 2713 if (np)
2714 err = of_mdiobus_register(bus, np);
b516d453
AL		 2715 else
2716 err = mdiobus_register(bus);
2717 if (err) {
fad09c73 2718 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
a3c53be5 2719 return err;
b516d453 2720 }
a3c53be5
AL		 2721
2722 if (external)
2723 list_add_tail(&mdio_bus->list, &chip->mdios);
2724 else
2725 list_add(&mdio_bus->list, &chip->mdios);
b516d453
AL		 2726
2727 return 0;
a3c53be5 2728}
b516d453 2729
a3c53be5
AL		 2730static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2731 { .compatible = "marvell,mv88e6xxx-mdio-external",
2732 .data = (void *)true },
2733 { },
2734};
b516d453 2735
a3c53be5
AL		 2736static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2737 struct device_node *np)
2738{
2739 const struct of_device_id *match;
2740 struct device_node *child;
2741 int err;
2742
2743 /* Always register one mdio bus for the internal/default mdio
2744 * bus. This maybe represented in the device tree, but is
2745 * optional.
2746 */
2747 child = of_get_child_by_name(np, "mdio");
2748 err = mv88e6xxx_mdio_register(chip, child, false);
2749 if (err)
2750 return err;
2751
2752 /* Walk the device tree, and see if there are any other nodes
2753 * which say they are compatible with the external mdio
2754 * bus.
2755 */
2756 for_each_available_child_of_node(np, child) {
2757 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2758 if (match) {
2759 err = mv88e6xxx_mdio_register(chip, child, true);
2760 if (err)
2761 return err;
2762 }
2763 }
2764
2765 return 0;
b516d453
AL		 2766}
2767
a3c53be5 2768static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 2769
2770{
a3c53be5
AL		 2771 struct mv88e6xxx_mdio_bus *mdio_bus;
2772 struct mii_bus *bus;
b516d453 2773
a3c53be5
AL		 2774 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2775 bus = mdio_bus->bus;
b516d453 2776
a3c53be5
AL		 2777 mdiobus_unregister(bus);
2778 }
b516d453
AL		 2779}
2780
855b1932
VD		 2781static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2782{
04bed143 2783 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2784
2785 return chip->eeprom_len;
2786}
2787
855b1932
VD		 2788static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2789 struct ethtool_eeprom *eeprom, u8 *data)
2790{
04bed143 2791 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2792 int err;
2793
ee4dc2e7
VD		 2794 if (!chip->info->ops->get_eeprom)
2795 return -EOPNOTSUPP;
855b1932 2796
ee4dc2e7
VD		 2797 mutex_lock(&chip->reg_lock);
2798 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 2799 mutex_unlock(&chip->reg_lock);
2800
2801 if (err)
2802 return err;
2803
2804 eeprom->magic = 0xc3ec4951;
2805
2806 return 0;
2807}
2808
855b1932
VD		 2809static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2810 struct ethtool_eeprom *eeprom, u8 *data)
2811{
04bed143 2812 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2813 int err;
2814
ee4dc2e7
VD		 2815 if (!chip->info->ops->set_eeprom)
2816 return -EOPNOTSUPP;
2817
855b1932
VD		 2818 if (eeprom->magic != 0xc3ec4951)
2819 return -EINVAL;
2820
2821 mutex_lock(&chip->reg_lock);
ee4dc2e7 2822 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 2823 mutex_unlock(&chip->reg_lock);
2824
2825 return err;
2826}
2827
b3469dd8 2828static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 2829 /* MV88E6XXX_FAMILY_6097 */
b073d4e2 2830 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 2831 .phy_read = mv88e6xxx_phy_ppu_read,
2832 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 2833 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2834 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2835 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2836 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2837 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2838 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2839 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 2840 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 2841 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 2842 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2843 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2844 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2845 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 2846 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2847 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2848 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2849 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2850 .ppu_enable = mv88e6185_g1_ppu_enable,
2851 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2852 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 2853};
2854
2855static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 2856 /* MV88E6XXX_FAMILY_6095 */
b073d4e2 2857 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 2858 .phy_read = mv88e6xxx_phy_ppu_read,
2859 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 2860 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2861 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2862 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2863 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2864 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
a23b2961 2865 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 2866 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2867 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2868 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2869 .stats_get_stats = mv88e6095_stats_get_stats,
6e55f698 2870 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2871 .ppu_enable = mv88e6185_g1_ppu_enable,
2872 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2873 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 2874};
2875
7d381a02 2876static const struct mv88e6xxx_ops mv88e6097_ops = {
15da3cc8 2877 /* MV88E6XXX_FAMILY_6097 */
7d381a02
SE		 2878 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2879 .phy_read = mv88e6xxx_g2_smi_phy_read,
2880 .phy_write = mv88e6xxx_g2_smi_phy_write,
2881 .port_set_link = mv88e6xxx_port_set_link,
2882 .port_set_duplex = mv88e6xxx_port_set_duplex,
2883 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2884 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2885 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2886 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2887 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 2888 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 2889 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
b35d322a 2890 .port_pause_config = mv88e6097_port_pause_config,
7d381a02
SE		 2891 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2892 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2893 .stats_get_strings = mv88e6095_stats_get_strings,
2894 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 2895 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2896 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
91eaa475 2897 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2898 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2899 .reset = mv88e6352_g1_reset,
7d381a02
SE		 2900};
2901
b3469dd8 2902static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 2903 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 2904 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 2905 .phy_read = mv88e6165_phy_read,
2906 .phy_write = mv88e6165_phy_write,
08ef7f10 2907 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2908 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2909 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2910 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2911 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
a605a0fe 2912 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2913 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2914 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2915 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 2916 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2917 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2918 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2919 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2920 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 2921};
2922
2923static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 2924 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 2925 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 2926 .phy_read = mv88e6xxx_phy_ppu_read,
2927 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 2928 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2929 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2930 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2931 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2932 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2933 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
56995cbc 2934 .port_set_ether_type = mv88e6351_port_set_ether_type,
a23b2961 2935 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
5f436666 2936 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 2937 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 2938 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 2939 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2940 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2941 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2942 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 2943 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2944 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2945 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2946 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2947 .ppu_enable = mv88e6185_g1_ppu_enable,
2948 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2949 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 2950};
2951
2952static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 2953 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 2954 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 2955 .phy_read = mv88e6165_phy_read,
2956 .phy_write = mv88e6165_phy_write,
08ef7f10 2957 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2958 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2959 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2960 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2961 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2962 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2963 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 2964 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 2965 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 2966 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 2967 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2968 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2969 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2970 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 2971 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2972 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2973 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2974 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2975 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 2976};
2977
2978static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 2979 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 2980 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 2981 .phy_read = mv88e6165_phy_read,
2982 .phy_write = mv88e6165_phy_write,
08ef7f10 2983 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2984 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2985 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 2986 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2987 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2988 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2989 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 2990 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2991 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2992 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2993 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2994 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 2995};
2996
2997static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 2998 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 2999 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3000 .phy_read = mv88e6xxx_g2_smi_phy_read,
3001 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3002 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3003 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3004 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3005 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3006 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3007 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3008 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3009 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3010 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3011 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3012 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3013 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3014 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3015 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3016 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3017 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3018 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3019 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3020 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3021 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3022};
3023
3024static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 3025 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3026 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3027 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3028 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3029 .phy_read = mv88e6xxx_g2_smi_phy_read,
3030 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3031 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3032 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3033 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3034 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3035 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3036 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3037 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3038 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3039 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3040 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3041 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3042 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3043 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3044 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3045 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3046 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3047 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3048 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3049 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3050 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3051};
3052
3053static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 3054 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3055 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3056 .phy_read = mv88e6xxx_g2_smi_phy_read,
3057 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3058 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3059 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3060 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3061 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3062 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3063 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3064 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3065 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3066 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3067 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3068 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3069 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3070 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3071 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3072 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3073 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3074 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3075 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3076 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3077 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3078};
3079
3080static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 3081 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3082 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3083 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3084 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3085 .phy_read = mv88e6xxx_g2_smi_phy_read,
3086 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3087 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3088 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3089 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3090 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3091 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3092 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3093 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3094 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3095 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3096 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3097 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3098 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3099 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3100 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3101 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3102 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3103 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3104 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3105 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3106 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3107};
3108
3109static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 3110 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3111 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3112 .phy_read = mv88e6xxx_phy_ppu_read,
3113 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3114 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3115 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3116 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 3117 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 3118 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
ef70b111 3119 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
a23b2961 3120 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 3121 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3122 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3123 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3124 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3125 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3126 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3127 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3128 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3129 .ppu_enable = mv88e6185_g1_ppu_enable,
3130 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3131 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3132};
3133
1a3b39ec 3134static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 3135 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3136 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3137 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3138 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3139 .phy_read = mv88e6xxx_g2_smi_phy_read,
3140 .phy_write = mv88e6xxx_g2_smi_phy_write,
3141 .port_set_link = mv88e6xxx_port_set_link,
3142 .port_set_duplex = mv88e6xxx_port_set_duplex,
3143 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3144 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3145 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3146 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3147 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3148 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3149 .port_pause_config = mv88e6390_port_pause_config,
79523473 3150 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3151 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3152 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3153 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3154 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3155 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3156 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3157 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3158 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3159 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3160};
3161
3162static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 3163 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3164 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3165 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3166 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3167 .phy_read = mv88e6xxx_g2_smi_phy_read,
3168 .phy_write = mv88e6xxx_g2_smi_phy_write,
3169 .port_set_link = mv88e6xxx_port_set_link,
3170 .port_set_duplex = mv88e6xxx_port_set_duplex,
3171 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3172 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3173 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3174 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3175 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3176 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3177 .port_pause_config = mv88e6390_port_pause_config,
79523473 3178 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3179 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3180 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3181 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3182 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3183 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3184 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3185 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3186 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3187 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3188};
3189
3190static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 3191 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3192 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3193 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3194 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3195 .phy_read = mv88e6xxx_g2_smi_phy_read,
3196 .phy_write = mv88e6xxx_g2_smi_phy_write,
3197 .port_set_link = mv88e6xxx_port_set_link,
3198 .port_set_duplex = mv88e6xxx_port_set_duplex,
3199 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3200 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3201 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3202 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3203 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3204 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3205 .port_pause_config = mv88e6390_port_pause_config,
79523473 3206 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3207 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3208 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3209 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3210 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3211 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3212 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3213 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3214 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3215 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3216};
3217
b3469dd8 3218static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 3219 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3220 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3221 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3222 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3223 .phy_read = mv88e6xxx_g2_smi_phy_read,
3224 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3225 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3226 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3227 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3228 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3229 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3230 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3231 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3232 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3233 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3234 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3235 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3236 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3237 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3238 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3239 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3240 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3241 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3242 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3243 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3244 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3245};
3246
1a3b39ec 3247static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 3248 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3249 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3250 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3251 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3252 .phy_read = mv88e6xxx_g2_smi_phy_read,
3253 .phy_write = mv88e6xxx_g2_smi_phy_write,
3254 .port_set_link = mv88e6xxx_port_set_link,
3255 .port_set_duplex = mv88e6xxx_port_set_duplex,
3256 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3257 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3258 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3259 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3260 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3261 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3262 .port_pause_config = mv88e6390_port_pause_config,
f39908d3 3263 .port_set_cmode = mv88e6390x_port_set_cmode,
79523473 3264 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3265 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3266 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3267 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3268 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3269 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3270 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3271 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3272 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3273 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3274};
3275
b3469dd8 3276static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 3277 /* MV88E6XXX_FAMILY_6320 */
ee4dc2e7
VD		 3278 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3279 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3280 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3281 .phy_read = mv88e6xxx_g2_smi_phy_read,
3282 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3283 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3284 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3285 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3286 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3287 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3288 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3289 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3290 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3291 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3292 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3293 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3294 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3295 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3296 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3297 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3298 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3299 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3300 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3301};
3302
3303static const struct mv88e6xxx_ops mv88e6321_ops = {
4b325d8c 3304 /* MV88E6XXX_FAMILY_6321 */
ee4dc2e7
VD		 3305 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3306 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3307 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3308 .phy_read = mv88e6xxx_g2_smi_phy_read,
3309 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3310 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3311 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3312 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3313 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3314 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3315 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3316 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3317 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3318 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3319 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3320 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3321 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3322 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3323 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3324 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3325 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
17e708ba 3326 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3327};
3328
3329static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 3330 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3331 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3332 .phy_read = mv88e6xxx_g2_smi_phy_read,
3333 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3334 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3335 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3336 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3337 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3338 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3339 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3340 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3341 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3342 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3343 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3344 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3345 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3346 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3347 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3348 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3349 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3350 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3351 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3352 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3353 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3354};
3355
3356static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 3357 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3358 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3359 .phy_read = mv88e6xxx_g2_smi_phy_read,
3360 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3361 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3362 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3363 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3364 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3365 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3366 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3367 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3368 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3369 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3370 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3371 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3372 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3373 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3374 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3375 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3376 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3377 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3378 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3379 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3380 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3381};
3382
3383static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 3384 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3385 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3386 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3387 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3388 .phy_read = mv88e6xxx_g2_smi_phy_read,
3389 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3390 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3391 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3392 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3393 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3394 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3395 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3396 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3397 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3398 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3399 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3400 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3401 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3402 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3403 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3404 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3405 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3406 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3407 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3408 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3409 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3410};
3411
1558727a
GC		 3412static const struct mv88e6xxx_ops mv88e6141_ops = {
3413 /* MV88E6XXX_FAMILY_6341 */
3414 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3415 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3416 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3417 .phy_read = mv88e6xxx_g2_smi_phy_read,
3418 .phy_write = mv88e6xxx_g2_smi_phy_write,
3419 .port_set_link = mv88e6xxx_port_set_link,
3420 .port_set_duplex = mv88e6xxx_port_set_duplex,
3421 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3422 .port_set_speed = mv88e6390_port_set_speed,
3423 .port_tag_remap = mv88e6095_port_tag_remap,
3424 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3425 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
1558727a
GC		 3426 .port_set_ether_type = mv88e6351_port_set_ether_type,
3427 .port_jumbo_config = mv88e6165_port_jumbo_config,
3428 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3429 .port_pause_config = mv88e6097_port_pause_config,
3430 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3431 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3432 .stats_get_strings = mv88e6320_stats_get_strings,
3433 .stats_get_stats = mv88e6390_stats_get_stats,
3434 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3435 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3436 .watchdog_ops = &mv88e6390_watchdog_ops,
1558727a
GC		 3437 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3438 .reset = mv88e6352_g1_reset,
3439};
3440
a75961d0
GC		 3441static const struct mv88e6xxx_ops mv88e6341_ops = {
3442 /* MV88E6XXX_FAMILY_6341 */
3443 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3444 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3445 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3446 .phy_read = mv88e6xxx_g2_smi_phy_read,
3447 .phy_write = mv88e6xxx_g2_smi_phy_write,
3448 .port_set_link = mv88e6xxx_port_set_link,
3449 .port_set_duplex = mv88e6xxx_port_set_duplex,
3450 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3451 .port_set_speed = mv88e6390_port_set_speed,
3452 .port_tag_remap = mv88e6095_port_tag_remap,
3453 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3454 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
a75961d0
GC		 3455 .port_set_ether_type = mv88e6351_port_set_ether_type,
3456 .port_jumbo_config = mv88e6165_port_jumbo_config,
3457 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3458 .port_pause_config = mv88e6097_port_pause_config,
3459 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3460 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3461 .stats_get_strings = mv88e6320_stats_get_strings,
3462 .stats_get_stats = mv88e6390_stats_get_stats,
3463 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3464 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3465 .watchdog_ops = &mv88e6390_watchdog_ops,
a75961d0
GC		 3466 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3467 .reset = mv88e6352_g1_reset,
3468};
3469
1a3b39ec 3470static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 3471 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3472 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3473 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3474 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3475 .phy_read = mv88e6xxx_g2_smi_phy_read,
3476 .phy_write = mv88e6xxx_g2_smi_phy_write,
3477 .port_set_link = mv88e6xxx_port_set_link,
3478 .port_set_duplex = mv88e6xxx_port_set_duplex,
3479 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3480 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3481 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3482 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3483 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3484 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3485 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3486 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3487 .port_pause_config = mv88e6390_port_pause_config,
f39908d3 3488 .port_set_cmode = mv88e6390x_port_set_cmode,
79523473 3489 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3490 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3491 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3492 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3493 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3494 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3495 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3496 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3497 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3498 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3499};
3500
3501static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 3502 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3503 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3504 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3505 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3506 .phy_read = mv88e6xxx_g2_smi_phy_read,
3507 .phy_write = mv88e6xxx_g2_smi_phy_write,
3508 .port_set_link = mv88e6xxx_port_set_link,
3509 .port_set_duplex = mv88e6xxx_port_set_duplex,
3510 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3511 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3512 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3513 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3514 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3515 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3516 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3517 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3518 .port_pause_config = mv88e6390_port_pause_config,
79523473 3519 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3520 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3521 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3522 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3523 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3524 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3525 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3526 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3527 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3528 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3529};
3530
3531static const struct mv88e6xxx_ops mv88e6391_ops = {
4b325d8c 3532 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3533 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3534 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3535 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3536 .phy_read = mv88e6xxx_g2_smi_phy_read,
3537 .phy_write = mv88e6xxx_g2_smi_phy_write,
3538 .port_set_link = mv88e6xxx_port_set_link,
3539 .port_set_duplex = mv88e6xxx_port_set_duplex,
3540 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3541 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3542 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3543 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3544 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3545 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3546 .port_pause_config = mv88e6390_port_pause_config,
79523473 3547 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3548 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3549 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3550 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3551 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3552 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3553 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3554 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3555 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3556 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3557};
3558
f81ec90f
VD		 3559static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3560 [MV88E6085] = {
3561 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3562 .family = MV88E6XXX_FAMILY_6097,
3563 .name = "Marvell 88E6085",
3564 .num_databases = 4096,
3565 .num_ports = 10,
9dddd478 3566 .port_base_addr = 0x10,
a935c052 3567 .global1_addr = 0x1b,
acddbd21 3568 .age_time_coeff = 15000,
dc30c35b 3569 .g1_irqs = 8,
e606ca36 3570 .atu_move_port_mask = 0xf,
443d5a1b 3571 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3572 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
b3469dd8 3573 .ops = &mv88e6085_ops,
f81ec90f
VD		 3574 },
3575
3576 [MV88E6095] = {
3577 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3578 .family = MV88E6XXX_FAMILY_6095,
3579 .name = "Marvell 88E6095/88E6095F",
3580 .num_databases = 256,
3581 .num_ports = 11,
9dddd478 3582 .port_base_addr = 0x10,
a935c052 3583 .global1_addr = 0x1b,
acddbd21 3584 .age_time_coeff = 15000,
dc30c35b 3585 .g1_irqs = 8,
e606ca36 3586 .atu_move_port_mask = 0xf,
443d5a1b 3587 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3588 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
b3469dd8 3589 .ops = &mv88e6095_ops,
f81ec90f
VD		 3590 },
3591
7d381a02
SE		 3592 [MV88E6097] = {
3593 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
3594 .family = MV88E6XXX_FAMILY_6097,
3595 .name = "Marvell 88E6097/88E6097F",
3596 .num_databases = 4096,
3597 .num_ports = 11,
3598 .port_base_addr = 0x10,
3599 .global1_addr = 0x1b,
3600 .age_time_coeff = 15000,
c534178b 3601 .g1_irqs = 8,
e606ca36 3602 .atu_move_port_mask = 0xf,
2bfcfcd3 3603 .tag_protocol = DSA_TAG_PROTO_EDSA,
7d381a02
SE		 3604 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3605 .ops = &mv88e6097_ops,
3606 },
3607
f81ec90f
VD		 3608 [MV88E6123] = {
3609 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3610 .family = MV88E6XXX_FAMILY_6165,
3611 .name = "Marvell 88E6123",
3612 .num_databases = 4096,
3613 .num_ports = 3,
9dddd478 3614 .port_base_addr = 0x10,
a935c052 3615 .global1_addr = 0x1b,
acddbd21 3616 .age_time_coeff = 15000,
dc30c35b 3617 .g1_irqs = 9,
e606ca36 3618 .atu_move_port_mask = 0xf,
443d5a1b 3619 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3620 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3621 .ops = &mv88e6123_ops,
f81ec90f
VD		 3622 },
3623
3624 [MV88E6131] = {
3625 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3626 .family = MV88E6XXX_FAMILY_6185,
3627 .name = "Marvell 88E6131",
3628 .num_databases = 256,
3629 .num_ports = 8,
9dddd478 3630 .port_base_addr = 0x10,
a935c052 3631 .global1_addr = 0x1b,
acddbd21 3632 .age_time_coeff = 15000,
dc30c35b 3633 .g1_irqs = 9,
e606ca36 3634 .atu_move_port_mask = 0xf,
443d5a1b 3635 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3636 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3637 .ops = &mv88e6131_ops,
f81ec90f
VD		 3638 },
3639
3640 [MV88E6161] = {
3641 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3642 .family = MV88E6XXX_FAMILY_6165,
3643 .name = "Marvell 88E6161",
3644 .num_databases = 4096,
3645 .num_ports = 6,
9dddd478 3646 .port_base_addr = 0x10,
a935c052 3647 .global1_addr = 0x1b,
acddbd21 3648 .age_time_coeff = 15000,
dc30c35b 3649 .g1_irqs = 9,
e606ca36 3650 .atu_move_port_mask = 0xf,
443d5a1b 3651 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3652 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3653 .ops = &mv88e6161_ops,
f81ec90f
VD		 3654 },
3655
3656 [MV88E6165] = {
3657 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3658 .family = MV88E6XXX_FAMILY_6165,
3659 .name = "Marvell 88E6165",
3660 .num_databases = 4096,
3661 .num_ports = 6,
9dddd478 3662 .port_base_addr = 0x10,
a935c052 3663 .global1_addr = 0x1b,
acddbd21 3664 .age_time_coeff = 15000,
dc30c35b 3665 .g1_irqs = 9,
e606ca36 3666 .atu_move_port_mask = 0xf,
443d5a1b 3667 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3668 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3669 .ops = &mv88e6165_ops,
f81ec90f
VD		 3670 },
3671
3672 [MV88E6171] = {
3673 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3674 .family = MV88E6XXX_FAMILY_6351,
3675 .name = "Marvell 88E6171",
3676 .num_databases = 4096,
3677 .num_ports = 7,
9dddd478 3678 .port_base_addr = 0x10,
a935c052 3679 .global1_addr = 0x1b,
acddbd21 3680 .age_time_coeff = 15000,
dc30c35b 3681 .g1_irqs = 9,
e606ca36 3682 .atu_move_port_mask = 0xf,
443d5a1b 3683 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3684 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3685 .ops = &mv88e6171_ops,
f81ec90f
VD		 3686 },
3687
3688 [MV88E6172] = {
3689 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3690 .family = MV88E6XXX_FAMILY_6352,
3691 .name = "Marvell 88E6172",
3692 .num_databases = 4096,
3693 .num_ports = 7,
9dddd478 3694 .port_base_addr = 0x10,
a935c052 3695 .global1_addr = 0x1b,
acddbd21 3696 .age_time_coeff = 15000,
dc30c35b 3697 .g1_irqs = 9,
e606ca36 3698 .atu_move_port_mask = 0xf,
443d5a1b 3699 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3700 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3701 .ops = &mv88e6172_ops,
f81ec90f
VD		 3702 },
3703
3704 [MV88E6175] = {
3705 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3706 .family = MV88E6XXX_FAMILY_6351,
3707 .name = "Marvell 88E6175",
3708 .num_databases = 4096,
3709 .num_ports = 7,
9dddd478 3710 .port_base_addr = 0x10,
a935c052 3711 .global1_addr = 0x1b,
acddbd21 3712 .age_time_coeff = 15000,
dc30c35b 3713 .g1_irqs = 9,
e606ca36 3714 .atu_move_port_mask = 0xf,
443d5a1b 3715 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3716 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3717 .ops = &mv88e6175_ops,
f81ec90f
VD		 3718 },
3719
3720 [MV88E6176] = {
3721 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3722 .family = MV88E6XXX_FAMILY_6352,
3723 .name = "Marvell 88E6176",
3724 .num_databases = 4096,
3725 .num_ports = 7,
9dddd478 3726 .port_base_addr = 0x10,
a935c052 3727 .global1_addr = 0x1b,
acddbd21 3728 .age_time_coeff = 15000,
dc30c35b 3729 .g1_irqs = 9,
e606ca36 3730 .atu_move_port_mask = 0xf,
443d5a1b 3731 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3732 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3733 .ops = &mv88e6176_ops,
f81ec90f
VD		 3734 },
3735
3736 [MV88E6185] = {
3737 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3738 .family = MV88E6XXX_FAMILY_6185,
3739 .name = "Marvell 88E6185",
3740 .num_databases = 256,
3741 .num_ports = 10,
9dddd478 3742 .port_base_addr = 0x10,
a935c052 3743 .global1_addr = 0x1b,
acddbd21 3744 .age_time_coeff = 15000,
dc30c35b 3745 .g1_irqs = 8,
e606ca36 3746 .atu_move_port_mask = 0xf,
443d5a1b 3747 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3748 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3749 .ops = &mv88e6185_ops,
f81ec90f
VD		 3750 },
3751
1a3b39ec
AL		 3752 [MV88E6190] = {
3753 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
3754 .family = MV88E6XXX_FAMILY_6390,
3755 .name = "Marvell 88E6190",
3756 .num_databases = 4096,
3757 .num_ports = 11, /* 10 + Z80 */
3758 .port_base_addr = 0x0,
3759 .global1_addr = 0x1b,
443d5a1b 3760 .tag_protocol = DSA_TAG_PROTO_DSA,
b91e055c 3761 .age_time_coeff = 3750,
1a3b39ec 3762 .g1_irqs = 9,
e606ca36 3763 .atu_move_port_mask = 0x1f,
1a3b39ec
AL		 3764 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3765 .ops = &mv88e6190_ops,
3766 },
3767
3768 [MV88E6190X] = {
3769 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
3770 .family = MV88E6XXX_FAMILY_6390,
3771 .name = "Marvell 88E6190X",
3772 .num_databases = 4096,
3773 .num_ports = 11, /* 10 + Z80 */
3774 .port_base_addr = 0x0,
3775 .global1_addr = 0x1b,
b91e055c 3776 .age_time_coeff = 3750,
1a3b39ec 3777 .g1_irqs = 9,
e606ca36 3778 .atu_move_port_mask = 0x1f,
443d5a1b 3779 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3780 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3781 .ops = &mv88e6190x_ops,
3782 },
3783
3784 [MV88E6191] = {
3785 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
3786 .family = MV88E6XXX_FAMILY_6390,
3787 .name = "Marvell 88E6191",
3788 .num_databases = 4096,
3789 .num_ports = 11, /* 10 + Z80 */
3790 .port_base_addr = 0x0,
3791 .global1_addr = 0x1b,
b91e055c 3792 .age_time_coeff = 3750,
443d5a1b 3793 .g1_irqs = 9,
e606ca36 3794 .atu_move_port_mask = 0x1f,
443d5a1b 3795 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3796 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3797 .ops = &mv88e6391_ops,
3798 },
3799
f81ec90f
VD		 3800 [MV88E6240] = {
3801 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3802 .family = MV88E6XXX_FAMILY_6352,
3803 .name = "Marvell 88E6240",
3804 .num_databases = 4096,
3805 .num_ports = 7,
9dddd478 3806 .port_base_addr = 0x10,
a935c052 3807 .global1_addr = 0x1b,
acddbd21 3808 .age_time_coeff = 15000,
dc30c35b 3809 .g1_irqs = 9,
e606ca36 3810 .atu_move_port_mask = 0xf,
443d5a1b 3811 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3812 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3813 .ops = &mv88e6240_ops,
f81ec90f
VD		 3814 },
3815
1a3b39ec
AL		 3816 [MV88E6290] = {
3817 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
3818 .family = MV88E6XXX_FAMILY_6390,
3819 .name = "Marvell 88E6290",
3820 .num_databases = 4096,
3821 .num_ports = 11, /* 10 + Z80 */
3822 .port_base_addr = 0x0,
3823 .global1_addr = 0x1b,
b91e055c 3824 .age_time_coeff = 3750,
1a3b39ec 3825 .g1_irqs = 9,
e606ca36 3826 .atu_move_port_mask = 0x1f,
443d5a1b 3827 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3828 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3829 .ops = &mv88e6290_ops,
3830 },
3831
f81ec90f
VD		 3832 [MV88E6320] = {
3833 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3834 .family = MV88E6XXX_FAMILY_6320,
3835 .name = "Marvell 88E6320",
3836 .num_databases = 4096,
3837 .num_ports = 7,
9dddd478 3838 .port_base_addr = 0x10,
a935c052 3839 .global1_addr = 0x1b,
acddbd21 3840 .age_time_coeff = 15000,
dc30c35b 3841 .g1_irqs = 8,
e606ca36 3842 .atu_move_port_mask = 0xf,
443d5a1b 3843 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3844 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3845 .ops = &mv88e6320_ops,
f81ec90f
VD		 3846 },
3847
3848 [MV88E6321] = {
3849 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3850 .family = MV88E6XXX_FAMILY_6320,
3851 .name = "Marvell 88E6321",
3852 .num_databases = 4096,
3853 .num_ports = 7,
9dddd478 3854 .port_base_addr = 0x10,
a935c052 3855 .global1_addr = 0x1b,
acddbd21 3856 .age_time_coeff = 15000,
dc30c35b 3857 .g1_irqs = 8,
e606ca36 3858 .atu_move_port_mask = 0xf,
443d5a1b 3859 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3860 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3861 .ops = &mv88e6321_ops,
f81ec90f
VD		 3862 },
3863
1558727a
GC		 3864 [MV88E6141] = {
3865 .prod_num = PORT_SWITCH_ID_PROD_NUM_6141,
3866 .family = MV88E6XXX_FAMILY_6341,
3867 .name = "Marvell 88E6341",
3868 .num_databases = 4096,
3869 .num_ports = 6,
3870 .port_base_addr = 0x10,
3871 .global1_addr = 0x1b,
3872 .age_time_coeff = 3750,
e606ca36 3873 .atu_move_port_mask = 0x1f,
1558727a
GC		 3874 .tag_protocol = DSA_TAG_PROTO_EDSA,
3875 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
3876 .ops = &mv88e6141_ops,
3877 },
3878
a75961d0
GC		 3879 [MV88E6341] = {
3880 .prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
3881 .family = MV88E6XXX_FAMILY_6341,
3882 .name = "Marvell 88E6341",
3883 .num_databases = 4096,
3884 .num_ports = 6,
3885 .port_base_addr = 0x10,
3886 .global1_addr = 0x1b,
3887 .age_time_coeff = 3750,
e606ca36 3888 .atu_move_port_mask = 0x1f,
a75961d0
GC		 3889 .tag_protocol = DSA_TAG_PROTO_EDSA,
3890 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
3891 .ops = &mv88e6341_ops,
3892 },
3893
f81ec90f
VD		 3894 [MV88E6350] = {
3895 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3896 .family = MV88E6XXX_FAMILY_6351,
3897 .name = "Marvell 88E6350",
3898 .num_databases = 4096,
3899 .num_ports = 7,
9dddd478 3900 .port_base_addr = 0x10,
a935c052 3901 .global1_addr = 0x1b,
acddbd21 3902 .age_time_coeff = 15000,
dc30c35b 3903 .g1_irqs = 9,
e606ca36 3904 .atu_move_port_mask = 0xf,
443d5a1b 3905 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3906 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3907 .ops = &mv88e6350_ops,
f81ec90f
VD		 3908 },
3909
3910 [MV88E6351] = {
3911 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3912 .family = MV88E6XXX_FAMILY_6351,
3913 .name = "Marvell 88E6351",
3914 .num_databases = 4096,
3915 .num_ports = 7,
9dddd478 3916 .port_base_addr = 0x10,
a935c052 3917 .global1_addr = 0x1b,
acddbd21 3918 .age_time_coeff = 15000,
dc30c35b 3919 .g1_irqs = 9,
e606ca36 3920 .atu_move_port_mask = 0xf,
443d5a1b 3921 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3922 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3923 .ops = &mv88e6351_ops,
f81ec90f
VD		 3924 },
3925
3926 [MV88E6352] = {
3927 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3928 .family = MV88E6XXX_FAMILY_6352,
3929 .name = "Marvell 88E6352",
3930 .num_databases = 4096,
3931 .num_ports = 7,
9dddd478 3932 .port_base_addr = 0x10,
a935c052 3933 .global1_addr = 0x1b,
acddbd21 3934 .age_time_coeff = 15000,
dc30c35b 3935 .g1_irqs = 9,
e606ca36 3936 .atu_move_port_mask = 0xf,
443d5a1b 3937 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3938 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3939 .ops = &mv88e6352_ops,
f81ec90f 3940 },
1a3b39ec
AL		 3941 [MV88E6390] = {
3942 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
3943 .family = MV88E6XXX_FAMILY_6390,
3944 .name = "Marvell 88E6390",
3945 .num_databases = 4096,
3946 .num_ports = 11, /* 10 + Z80 */
3947 .port_base_addr = 0x0,
3948 .global1_addr = 0x1b,
b91e055c 3949 .age_time_coeff = 3750,
1a3b39ec 3950 .g1_irqs = 9,
e606ca36 3951 .atu_move_port_mask = 0x1f,
443d5a1b 3952 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3953 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3954 .ops = &mv88e6390_ops,
3955 },
3956 [MV88E6390X] = {
3957 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
3958 .family = MV88E6XXX_FAMILY_6390,
3959 .name = "Marvell 88E6390X",
3960 .num_databases = 4096,
3961 .num_ports = 11, /* 10 + Z80 */
3962 .port_base_addr = 0x0,
3963 .global1_addr = 0x1b,
b91e055c 3964 .age_time_coeff = 3750,
1a3b39ec 3965 .g1_irqs = 9,
e606ca36 3966 .atu_move_port_mask = 0x1f,
443d5a1b 3967 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3968 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3969 .ops = &mv88e6390x_ops,
3970 },
f81ec90f
VD		 3971};
3972
5f7c0367 3973static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3974{
a439c061 3975 int i;
b9b37713 3976
5f7c0367
VD		 3977 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3978 if (mv88e6xxx_table[i].prod_num == prod_num)
3979 return &mv88e6xxx_table[i];
b9b37713 3980
b9b37713
VD		 3981 return NULL;
3982}
3983
fad09c73 3984static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3985{
3986 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3987 unsigned int prod_num, rev;
3988 u16 id;
3989 int err;
bc46a3d5 3990
8f6345b2
VD		 3991 mutex_lock(&chip->reg_lock);
3992 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3993 mutex_unlock(&chip->reg_lock);
3994 if (err)
3995 return err;
bc46a3d5
VD		 3996
3997 prod_num = (id & 0xfff0) >> 4;
3998 rev = id & 0x000f;
3999
4000 info = mv88e6xxx_lookup_info(prod_num);
4001 if (!info)
4002 return -ENODEV;
4003
caac8545 4004 /* Update the compatible info with the probed one */
fad09c73 4005 chip->info = info;
bc46a3d5 4006
ca070c10
VD		 4007 err = mv88e6xxx_g2_require(chip);
4008 if (err)
4009 return err;
4010
fad09c73
VD		 4011 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4012 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 4013
4014 return 0;
4015}
4016
fad09c73 4017static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 4018{
fad09c73 4019 struct mv88e6xxx_chip *chip;
469d729f 4020
fad09c73
VD		 4021 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4022 if (!chip)
469d729f
VD		 4023 return NULL;
4024
fad09c73 4025 chip->dev = dev;
469d729f 4026
fad09c73 4027 mutex_init(&chip->reg_lock);
a3c53be5 4028 INIT_LIST_HEAD(&chip->mdios);
469d729f 4029
fad09c73 4030 return chip;
469d729f
VD		 4031}
4032
e57e5e77
VD		 4033static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
4034{
a199d8b6 4035 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
e57e5e77 4036 mv88e6xxx_ppu_state_init(chip);
e57e5e77
VD		 4037}
4038
930188ce
AL		 4039static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
4040{
a199d8b6 4041 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
930188ce 4042 mv88e6xxx_ppu_state_destroy(chip);
930188ce
AL		 4043}
4044
fad09c73 4045static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 4046 struct mii_bus *bus, int sw_addr)
4047{
914b32f6 4048 if (sw_addr == 0)
fad09c73 4049 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 4050 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 4051 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 4052 else
4053 return -EINVAL;
4054
fad09c73
VD		 4055 chip->bus = bus;
4056 chip->sw_addr = sw_addr;
4a70c4ab
VD		 4057
4058 return 0;
4059}
4060
7b314362
AL		 4061static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
4062{
04bed143 4063 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be 4064
443d5a1b 4065 return chip->info->tag_protocol;
7b314362
AL		 4066}
4067
fcdce7d0
AL		 4068static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4069 struct device *host_dev, int sw_addr,
4070 void **priv)
a77d43f1 4071{
fad09c73 4072 struct mv88e6xxx_chip *chip;
a439c061 4073 struct mii_bus *bus;
b516d453 4074 int err;
a77d43f1 4075
a439c061 4076 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 4077 if (!bus)
4078 return NULL;
4079
fad09c73
VD		 4080 chip = mv88e6xxx_alloc_chip(dsa_dev);
4081 if (!chip)
469d729f
VD		 4082 return NULL;
4083
caac8545 4084 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 4085 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 4086
fad09c73 4087 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 4088 if (err)
4089 goto free;
4090
fad09c73 4091 err = mv88e6xxx_detect(chip);
bc46a3d5 4092 if (err)
469d729f 4093 goto free;
a439c061 4094
dc30c35b
AL		 4095 mutex_lock(&chip->reg_lock);
4096 err = mv88e6xxx_switch_reset(chip);
4097 mutex_unlock(&chip->reg_lock);
4098 if (err)
4099 goto free;
4100
e57e5e77
VD		 4101 mv88e6xxx_phy_init(chip);
4102
a3c53be5 4103 err = mv88e6xxx_mdios_register(chip, NULL);
b516d453 4104 if (err)
469d729f 4105 goto free;
b516d453 4106
fad09c73 4107 *priv = chip;
a439c061 4108
fad09c73 4109 return chip->info->name;
469d729f 4110free:
fad09c73 4111 devm_kfree(dsa_dev, chip);
469d729f
VD		 4112
4113 return NULL;
a77d43f1
AL		 4114}
4115
7df8fbdd
VD		 4116static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4117 const struct switchdev_obj_port_mdb *mdb,
4118 struct switchdev_trans *trans)
4119{
4120 /* We don't need any dynamic resource from the kernel (yet),
4121 * so skip the prepare phase.
4122 */
4123
4124 return 0;
4125}
4126
4127static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4128 const struct switchdev_obj_port_mdb *mdb,
4129 struct switchdev_trans *trans)
4130{
04bed143 4131 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4132
4133 mutex_lock(&chip->reg_lock);
4134 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4135 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4136 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4137 mutex_unlock(&chip->reg_lock);
4138}
4139
4140static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4141 const struct switchdev_obj_port_mdb *mdb)
4142{
04bed143 4143 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4144 int err;
4145
4146 mutex_lock(&chip->reg_lock);
4147 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4148 GLOBAL_ATU_DATA_STATE_UNUSED);
4149 mutex_unlock(&chip->reg_lock);
4150
4151 return err;
4152}
4153
4154static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4155 struct switchdev_obj_port_mdb *mdb,
4156 int (*cb)(struct switchdev_obj *obj))
4157{
04bed143 4158 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4159 int err;
4160
4161 mutex_lock(&chip->reg_lock);
4162 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4163 mutex_unlock(&chip->reg_lock);
4164
4165 return err;
4166}
4167
a82f67af 4168static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 4169 .probe = mv88e6xxx_drv_probe,
7b314362 4170 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 4171 .setup = mv88e6xxx_setup,
4172 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 4173 .adjust_link = mv88e6xxx_adjust_link,
4174 .get_strings = mv88e6xxx_get_strings,
4175 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4176 .get_sset_count = mv88e6xxx_get_sset_count,
4177 .set_eee = mv88e6xxx_set_eee,
4178 .get_eee = mv88e6xxx_get_eee,
f8cd8753 4179 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 4180 .get_eeprom = mv88e6xxx_get_eeprom,
4181 .set_eeprom = mv88e6xxx_set_eeprom,
4182 .get_regs_len = mv88e6xxx_get_regs_len,
4183 .get_regs = mv88e6xxx_get_regs,
2cfcd964 4184 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 4185 .port_bridge_join = mv88e6xxx_port_bridge_join,
4186 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4187 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 4188 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 4189 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4190 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4191 .port_vlan_add = mv88e6xxx_port_vlan_add,
4192 .port_vlan_del = mv88e6xxx_port_vlan_del,
4193 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4194 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4195 .port_fdb_add = mv88e6xxx_port_fdb_add,
4196 .port_fdb_del = mv88e6xxx_port_fdb_del,
4197 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 4198 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4199 .port_mdb_add = mv88e6xxx_port_mdb_add,
4200 .port_mdb_del = mv88e6xxx_port_mdb_del,
4201 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
f81ec90f
VD		 4202};
4203
ab3d408d
FF		 4204static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4205 .ops = &mv88e6xxx_switch_ops,
4206};
4207
55ed0ce0 4208static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4209{
fad09c73 4210 struct device *dev = chip->dev;
b7e66a5f
VD		 4211 struct dsa_switch *ds;
4212
a0c02161 4213 ds = dsa_switch_alloc(dev, DSA_MAX_PORTS);
b7e66a5f
VD		 4214 if (!ds)
4215 return -ENOMEM;
4216
fad09c73 4217 ds->priv = chip;
9d490b4e 4218 ds->ops = &mv88e6xxx_switch_ops;
b7e66a5f
VD		 4219
4220 dev_set_drvdata(dev, ds);
4221
55ed0ce0 4222 return dsa_register_switch(ds, dev);
b7e66a5f
VD		 4223}
4224
fad09c73 4225static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4226{
fad09c73 4227 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 4228}
4229
57d32310 4230static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 4231{
14c7b3c3 4232 struct device *dev = &mdiodev->dev;
f8cd8753 4233 struct device_node *np = dev->of_node;
caac8545 4234 const struct mv88e6xxx_info *compat_info;
fad09c73 4235 struct mv88e6xxx_chip *chip;
f8cd8753 4236 u32 eeprom_len;
52638f71 4237 int err;
14c7b3c3 4238
caac8545
VD		 4239 compat_info = of_device_get_match_data(dev);
4240 if (!compat_info)
4241 return -EINVAL;
4242
fad09c73
VD		 4243 chip = mv88e6xxx_alloc_chip(dev);
4244 if (!chip)
14c7b3c3
AL		 4245 return -ENOMEM;
4246
fad09c73 4247 chip->info = compat_info;
caac8545 4248
fad09c73 4249 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4250 if (err)
4251 return err;
14c7b3c3 4252
b4308f04
AL		 4253 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4254 if (IS_ERR(chip->reset))
4255 return PTR_ERR(chip->reset);
4256
fad09c73 4257 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4258 if (err)
4259 return err;
14c7b3c3 4260
e57e5e77
VD		 4261 mv88e6xxx_phy_init(chip);
4262
ee4dc2e7 4263 if (chip->info->ops->get_eeprom &&
f8cd8753 4264 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4265 chip->eeprom_len = eeprom_len;
f8cd8753 4266
dc30c35b
AL		 4267 mutex_lock(&chip->reg_lock);
4268 err = mv88e6xxx_switch_reset(chip);
4269 mutex_unlock(&chip->reg_lock);
4270 if (err)
4271 goto out;
4272
4273 chip->irq = of_irq_get(np, 0);
4274 if (chip->irq == -EPROBE_DEFER) {
4275 err = chip->irq;
4276 goto out;
4277 }
4278
4279 if (chip->irq > 0) {
4280 /* Has to be performed before the MDIO bus is created,
4281 * because the PHYs will link there interrupts to these
4282 * interrupt controllers
4283 */
4284 mutex_lock(&chip->reg_lock);
4285 err = mv88e6xxx_g1_irq_setup(chip);
4286 mutex_unlock(&chip->reg_lock);
4287
4288 if (err)
4289 goto out;
4290
4291 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4292 err = mv88e6xxx_g2_irq_setup(chip);
4293 if (err)
4294 goto out_g1_irq;
4295 }
4296 }
4297
a3c53be5 4298 err = mv88e6xxx_mdios_register(chip, np);
b516d453 4299 if (err)
dc30c35b 4300 goto out_g2_irq;
b516d453 4301
55ed0ce0 4302 err = mv88e6xxx_register_switch(chip);
dc30c35b
AL		 4303 if (err)
4304 goto out_mdio;
83c0afae 4305
98e67308 4306 return 0;
dc30c35b
AL		 4307
4308out_mdio:
a3c53be5 4309 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4310out_g2_irq:
46712644 4311 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
dc30c35b
AL		 4312 mv88e6xxx_g2_irq_free(chip);
4313out_g1_irq:
61f7c3f8
AL		 4314 if (chip->irq > 0) {
4315 mutex_lock(&chip->reg_lock);
46712644 4316 mv88e6xxx_g1_irq_free(chip);
61f7c3f8
AL		 4317 mutex_unlock(&chip->reg_lock);
4318 }
dc30c35b
AL		 4319out:
4320 return err;
98e67308 4321}
14c7b3c3
AL		 4322
4323static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4324{
4325 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 4326 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 4327
930188ce 4328 mv88e6xxx_phy_destroy(chip);
fad09c73 4329 mv88e6xxx_unregister_switch(chip);
a3c53be5 4330 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4331
46712644
AL		 4332 if (chip->irq > 0) {
4333 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4334 mv88e6xxx_g2_irq_free(chip);
4335 mv88e6xxx_g1_irq_free(chip);
4336 }
14c7b3c3
AL		 4337}
4338
4339static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4340 {
4341 .compatible = "marvell,mv88e6085",
4342 .data = &mv88e6xxx_table[MV88E6085],
4343 },
1a3b39ec
AL		 4344 {
4345 .compatible = "marvell,mv88e6190",
4346 .data = &mv88e6xxx_table[MV88E6190],
4347 },
14c7b3c3
AL		 4348 { /* sentinel */ },
4349};
4350
4351MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4352
4353static struct mdio_driver mv88e6xxx_driver = {
4354 .probe = mv88e6xxx_probe,
4355 .remove = mv88e6xxx_remove,
4356 .mdiodrv.driver = {
4357 .name = "mv88e6085",
4358 .of_match_table = mv88e6xxx_of_match,
4359 },
4360};
4361
4362static int __init mv88e6xxx_init(void)
4363{
ab3d408d 4364 register_switch_driver(&mv88e6xxx_switch_drv);
14c7b3c3
AL		 4365 return mdio_driver_register(&mv88e6xxx_driver);
4366}
98e67308
BH		 4367module_init(mv88e6xxx_init);
4368
4369static void __exit mv88e6xxx_cleanup(void)
4370{
14c7b3c3 4371 mdio_driver_unregister(&mv88e6xxx_driver);
ab3d408d 4372 unregister_switch_driver(&mv88e6xxx_switch_drv);
98e67308
BH		 4373}
4374module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4375
4376MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4377MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4378MODULE_LICENSE("GPL");
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