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net: dsa: bcm_sf2: Declare our own dsa_switch_ops
[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
1f36faf2 35#include <net/switchdev.h>
ec561276 36
91da11f8 37#include "mv88e6xxx.h"
a935c052 38#include "global1.h"
ec561276 39#include "global2.h"
18abed21 40#include "port.h"
91da11f8 41
fad09c73 42static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 43{
fad09c73
VD		 44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 46 dump_stack();
47 }
48}
49
914b32f6
VD		 50/* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
52 *
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
56 *
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 60 */
914b32f6 61
fad09c73 62static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 63 int addr, int reg, u16 *val)
64{
fad09c73 65 if (!chip->smi_ops)
914b32f6
VD		 66 return -EOPNOTSUPP;
67
fad09c73 68 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 69}
70
fad09c73 71static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 72 int addr, int reg, u16 val)
73{
fad09c73 74 if (!chip->smi_ops)
914b32f6
VD		 75 return -EOPNOTSUPP;
76
fad09c73 77 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 78}
79
fad09c73 80static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 81 int addr, int reg, u16 *val)
82{
83 int ret;
84
fad09c73 85 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 86 if (ret < 0)
87 return ret;
88
89 *val = ret & 0xffff;
90
91 return 0;
92}
93
fad09c73 94static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 95 int addr, int reg, u16 val)
96{
97 int ret;
98
fad09c73 99 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 100 if (ret < 0)
101 return ret;
102
103 return 0;
104}
105
c08026ab 106static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
109};
110
fad09c73 111static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 112{
113 int ret;
114 int i;
115
116 for (i = 0; i < 16; i++) {
fad09c73 117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 118 if (ret < 0)
119 return ret;
120
cca8b133 121 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 122 return 0;
123 }
124
125 return -ETIMEDOUT;
126}
127
fad09c73 128static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 129 int addr, int reg, u16 *val)
91da11f8
LB		 130{
131 int ret;
132
3675c8d7 133 /* Wait for the bus to become free. */
fad09c73 134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 135 if (ret < 0)
136 return ret;
137
3675c8d7 138 /* Transmit the read command. */
fad09c73 139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 141 if (ret < 0)
142 return ret;
143
3675c8d7 144 /* Wait for the read command to complete. */
fad09c73 145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 146 if (ret < 0)
147 return ret;
148
3675c8d7 149 /* Read the data. */
fad09c73 150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 151 if (ret < 0)
152 return ret;
153
914b32f6 154 *val = ret & 0xffff;
91da11f8 155
914b32f6 156 return 0;
8d6d09e7
GR		 157}
158
fad09c73 159static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 160 int addr, int reg, u16 val)
91da11f8
LB		 161{
162 int ret;
163
3675c8d7 164 /* Wait for the bus to become free. */
fad09c73 165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 166 if (ret < 0)
167 return ret;
168
3675c8d7 169 /* Transmit the data to write. */
fad09c73 170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 171 if (ret < 0)
172 return ret;
173
3675c8d7 174 /* Transmit the write command. */
fad09c73 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 177 if (ret < 0)
178 return ret;
179
3675c8d7 180 /* Wait for the write command to complete. */
fad09c73 181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 182 if (ret < 0)
183 return ret;
184
185 return 0;
186}
187
c08026ab 188static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
191};
192
ec561276 193int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 194{
195 int err;
196
fad09c73 197 assert_reg_lock(chip);
914b32f6 198
fad09c73 199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 200 if (err)
201 return err;
202
fad09c73 203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 204 addr, reg, *val);
205
206 return 0;
207}
208
ec561276 209int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 210{
914b32f6
VD		 211 int err;
212
fad09c73 213 assert_reg_lock(chip);
91da11f8 214
fad09c73 215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 216 if (err)
217 return err;
218
fad09c73 219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 220 addr, reg, val);
221
914b32f6
VD		 222 return 0;
223}
224
e57e5e77
VD		 225static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
226 int reg, u16 *val)
227{
228 int addr = phy; /* PHY devices addresses start at 0x0 */
229
b3469dd8 230 if (!chip->info->ops->phy_read)
e57e5e77
VD		 231 return -EOPNOTSUPP;
232
b3469dd8 233 return chip->info->ops->phy_read(chip, addr, reg, val);
e57e5e77
VD		 234}
235
236static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
237 int reg, u16 val)
238{
239 int addr = phy; /* PHY devices addresses start at 0x0 */
240
b3469dd8 241 if (!chip->info->ops->phy_write)
e57e5e77
VD		 242 return -EOPNOTSUPP;
243
b3469dd8 244 return chip->info->ops->phy_write(chip, addr, reg, val);
e57e5e77
VD		 245}
246
09cb7dfd
VD		 247static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
248{
249 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
250 return -EOPNOTSUPP;
251
252 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
253}
254
255static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
256{
257 int err;
258
259 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
260 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
261 if (unlikely(err)) {
262 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
263 phy, err);
264 }
265}
266
267static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
268 u8 page, int reg, u16 *val)
269{
270 int err;
271
272 /* There is no paging for registers 22 */
273 if (reg == PHY_PAGE)
274 return -EINVAL;
275
276 err = mv88e6xxx_phy_page_get(chip, phy, page);
277 if (!err) {
278 err = mv88e6xxx_phy_read(chip, phy, reg, val);
279 mv88e6xxx_phy_page_put(chip, phy);
280 }
281
282 return err;
283}
284
285static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
286 u8 page, int reg, u16 val)
287{
288 int err;
289
290 /* There is no paging for registers 22 */
291 if (reg == PHY_PAGE)
292 return -EINVAL;
293
294 err = mv88e6xxx_phy_page_get(chip, phy, page);
295 if (!err) {
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
297 mv88e6xxx_phy_page_put(chip, phy);
298 }
299
300 return err;
301}
302
303static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
304{
305 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
306 reg, val);
307}
308
309static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
310{
311 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
312 reg, val);
313}
314
dc30c35b
AL		 315static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
316{
317 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
318 unsigned int n = d->hwirq;
319
320 chip->g1_irq.masked |= (1 << n);
321}
322
323static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
324{
325 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
326 unsigned int n = d->hwirq;
327
328 chip->g1_irq.masked &= ~(1 << n);
329}
330
331static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
332{
333 struct mv88e6xxx_chip *chip = dev_id;
334 unsigned int nhandled = 0;
335 unsigned int sub_irq;
336 unsigned int n;
337 u16 reg;
338 int err;
339
340 mutex_lock(&chip->reg_lock);
341 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
342 mutex_unlock(&chip->reg_lock);
343
344 if (err)
345 goto out;
346
347 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
348 if (reg & (1 << n)) {
349 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
350 handle_nested_irq(sub_irq);
351 ++nhandled;
352 }
353 }
354out:
355 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
356}
357
358static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
359{
360 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
361
362 mutex_lock(&chip->reg_lock);
363}
364
365static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
366{
367 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
368 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
369 u16 reg;
370 int err;
371
372 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
373 if (err)
374 goto out;
375
376 reg &= ~mask;
377 reg |= (~chip->g1_irq.masked & mask);
378
379 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
380 if (err)
381 goto out;
382
383out:
384 mutex_unlock(&chip->reg_lock);
385}
386
387static struct irq_chip mv88e6xxx_g1_irq_chip = {
388 .name = "mv88e6xxx-g1",
389 .irq_mask = mv88e6xxx_g1_irq_mask,
390 .irq_unmask = mv88e6xxx_g1_irq_unmask,
391 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
392 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
393};
394
395static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
396 unsigned int irq,
397 irq_hw_number_t hwirq)
398{
399 struct mv88e6xxx_chip *chip = d->host_data;
400
401 irq_set_chip_data(irq, d->host_data);
402 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
403 irq_set_noprobe(irq);
404
405 return 0;
406}
407
408static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
409 .map = mv88e6xxx_g1_irq_domain_map,
410 .xlate = irq_domain_xlate_twocell,
411};
412
413static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
414{
415 int irq, virq;
3460a577
AL		 416 u16 mask;
417
418 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
419 mask |= GENMASK(chip->g1_irq.nirqs, 0);
420 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
421
422 free_irq(chip->irq, chip);
dc30c35b 423
5edef2f2 424 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
a3db3d3a 425 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 426 irq_dispose_mapping(virq);
427 }
428
a3db3d3a 429 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 430}
431
432static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
433{
3dd0ef05
AL		 434 int err, irq, virq;
435 u16 reg, mask;
dc30c35b
AL		 436
437 chip->g1_irq.nirqs = chip->info->g1_irqs;
438 chip->g1_irq.domain = irq_domain_add_simple(
439 NULL, chip->g1_irq.nirqs, 0,
440 &mv88e6xxx_g1_irq_domain_ops, chip);
441 if (!chip->g1_irq.domain)
442 return -ENOMEM;
443
444 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
445 irq_create_mapping(chip->g1_irq.domain, irq);
446
447 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
448 chip->g1_irq.masked = ~0;
449
3dd0ef05 450 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
dc30c35b 451 if (err)
3dd0ef05 452 goto out_mapping;
dc30c35b 453
3dd0ef05 454 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 455
3dd0ef05 456 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
dc30c35b 457 if (err)
3dd0ef05 458 goto out_disable;
dc30c35b
AL		 459
460 /* Reading the interrupt status clears (most of) them */
461 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
462 if (err)
3dd0ef05 463 goto out_disable;
dc30c35b
AL		 464
465 err = request_threaded_irq(chip->irq, NULL,
466 mv88e6xxx_g1_irq_thread_fn,
467 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
468 dev_name(chip->dev), chip);
469 if (err)
3dd0ef05 470 goto out_disable;
dc30c35b
AL		 471
472 return 0;
473
3dd0ef05
AL		 474out_disable:
475 mask |= GENMASK(chip->g1_irq.nirqs, 0);
476 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
477
478out_mapping:
479 for (irq = 0; irq < 16; irq++) {
480 virq = irq_find_mapping(chip->g1_irq.domain, irq);
481 irq_dispose_mapping(virq);
482 }
483
484 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 485
486 return err;
487}
488
ec561276 489int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 490{
6441e669 491 int i;
2d79af6e 492
6441e669 493 for (i = 0; i < 16; i++) {
2d79af6e
VD		 494 u16 val;
495 int err;
496
497 err = mv88e6xxx_read(chip, addr, reg, &val);
498 if (err)
499 return err;
500
501 if (!(val & mask))
502 return 0;
503
504 usleep_range(1000, 2000);
505 }
506
30853553 507 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 508 return -ETIMEDOUT;
509}
510
f22ab641 511/* Indirect write to single pointer-data register with an Update bit */
ec561276 512int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 513{
514 u16 val;
0f02b4f7 515 int err;
f22ab641
VD		 516
517 /* Wait until the previous operation is completed */
0f02b4f7
AL		 518 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
519 if (err)
520 return err;
f22ab641
VD		 521
522 /* Set the Update bit to trigger a write operation */
523 val = BIT(15) | update;
524
525 return mv88e6xxx_write(chip, addr, reg, val);
526}
527
a935c052 528static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
914b32f6 529{
a199d8b6
VD		 530 if (!chip->info->ops->ppu_disable)
531 return 0;
2e5f0320 532
a199d8b6 533 return chip->info->ops->ppu_disable(chip);
2e5f0320
LB		 534}
535
fad09c73 536static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 537{
a199d8b6
VD		 538 if (!chip->info->ops->ppu_enable)
539 return 0;
2e5f0320 540
a199d8b6 541 return chip->info->ops->ppu_enable(chip);
2e5f0320
LB		 542}
543
544static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
545{
fad09c73 546 struct mv88e6xxx_chip *chip;
2e5f0320 547
fad09c73 548 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 549
fad09c73 550 mutex_lock(&chip->reg_lock);
762eb67b 551
fad09c73
VD		 552 if (mutex_trylock(&chip->ppu_mutex)) {
553 if (mv88e6xxx_ppu_enable(chip) == 0)
554 chip->ppu_disabled = 0;
555 mutex_unlock(&chip->ppu_mutex);
2e5f0320 556 }
762eb67b 557
fad09c73 558 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 559}
560
561static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
562{
fad09c73 563 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 564
fad09c73 565 schedule_work(&chip->ppu_work);
2e5f0320
LB		 566}
567
fad09c73 568static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 569{
2e5f0320
LB		 570 int ret;
571
fad09c73 572 mutex_lock(&chip->ppu_mutex);
2e5f0320 573
3675c8d7 574 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 575 * we can access the PHY registers. If it was already
576 * disabled, cancel the timer that is going to re-enable
577 * it.
578 */
fad09c73
VD		 579 if (!chip->ppu_disabled) {
580 ret = mv88e6xxx_ppu_disable(chip);
85686581 581 if (ret < 0) {
fad09c73 582 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 583 return ret;
584 }
fad09c73 585 chip->ppu_disabled = 1;
2e5f0320 586 } else {
fad09c73 587 del_timer(&chip->ppu_timer);
85686581 588 ret = 0;
2e5f0320
LB		 589 }
590
591 return ret;
592}
593
fad09c73 594static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 595{
3675c8d7 596 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 597 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
598 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 599}
600
fad09c73 601static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 602{
fad09c73
VD		 603 mutex_init(&chip->ppu_mutex);
604 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
68497a87
WY		 605 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
606 (unsigned long)chip);
2e5f0320
LB		 607}
608
930188ce
AL		 609static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
610{
611 del_timer_sync(&chip->ppu_timer);
612}
613
e57e5e77
VD		 614static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
615 int reg, u16 *val)
2e5f0320 616{
e57e5e77 617 int err;
2e5f0320 618
e57e5e77
VD		 619 err = mv88e6xxx_ppu_access_get(chip);
620 if (!err) {
621 err = mv88e6xxx_read(chip, addr, reg, val);
fad09c73 622 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 623 }
624
e57e5e77 625 return err;
2e5f0320
LB		 626}
627
e57e5e77
VD		 628static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
629 int reg, u16 val)
2e5f0320 630{
e57e5e77 631 int err;
2e5f0320 632
e57e5e77
VD		 633 err = mv88e6xxx_ppu_access_get(chip);
634 if (!err) {
635 err = mv88e6xxx_write(chip, addr, reg, val);
fad09c73 636 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 637 }
638
e57e5e77 639 return err;
2e5f0320 640}
2e5f0320 641
fad09c73 642static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
54d792f2 643{
fad09c73 644 return chip->info->family == MV88E6XXX_FAMILY_6095;
54d792f2
AL		 645}
646
fad09c73 647static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 648{
fad09c73 649 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 650}
651
fad09c73 652static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 653{
fad09c73 654 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 655}
656
fad09c73 657static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
54d792f2 658{
fad09c73 659 return chip->info->family == MV88E6XXX_FAMILY_6185;
54d792f2
AL		 660}
661
fad09c73 662static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
7c3d0d67 663{
fad09c73 664 return chip->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 665}
666
fad09c73 667static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 668{
fad09c73 669 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 670}
671
fad09c73 672static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 673{
fad09c73 674 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 675}
676
d78343d2
VD		 677static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
678 int link, int speed, int duplex,
679 phy_interface_t mode)
680{
681 int err;
682
683 if (!chip->info->ops->port_set_link)
684 return 0;
685
686 /* Port's MAC control must not be changed unless the link is down */
687 err = chip->info->ops->port_set_link(chip, port, 0);
688 if (err)
689 return err;
690
691 if (chip->info->ops->port_set_speed) {
692 err = chip->info->ops->port_set_speed(chip, port, speed);
693 if (err && err != -EOPNOTSUPP)
694 goto restore_link;
695 }
696
697 if (chip->info->ops->port_set_duplex) {
698 err = chip->info->ops->port_set_duplex(chip, port, duplex);
699 if (err && err != -EOPNOTSUPP)
700 goto restore_link;
701 }
702
703 if (chip->info->ops->port_set_rgmii_delay) {
704 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
705 if (err && err != -EOPNOTSUPP)
706 goto restore_link;
707 }
708
709 err = 0;
710restore_link:
711 if (chip->info->ops->port_set_link(chip, port, link))
712 netdev_err(chip->ds->ports[port].netdev,
713 "failed to restore MAC's link\n");
714
715 return err;
716}
717
dea87024
AL		 718/* We expect the switch to perform auto negotiation if there is a real
719 * phy. However, in the case of a fixed link phy, we force the port
720 * settings from the fixed link settings.
721 */
f81ec90f
VD		 722static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
723 struct phy_device *phydev)
dea87024 724{
04bed143 725 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 726 int err;
dea87024
AL		 727
728 if (!phy_is_pseudo_fixed_link(phydev))
729 return;
730
fad09c73 731 mutex_lock(&chip->reg_lock);
d78343d2
VD		 732 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
733 phydev->duplex, phydev->interface);
fad09c73 734 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 735
736 if (err && err != -EOPNOTSUPP)
737 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
dea87024
AL		 738}
739
a605a0fe 740static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 741{
a605a0fe
AL		 742 if (!chip->info->ops->stats_snapshot)
743 return -EOPNOTSUPP;
91da11f8 744
a605a0fe 745 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 746}
747
e413e7e1 748static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 749 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
750 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
751 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
752 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
753 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
754 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
755 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
756 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
757 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
758 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
759 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
760 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
761 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
762 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
763 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
764 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
765 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
766 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
767 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
768 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
769 { "single", 4, 0x14, STATS_TYPE_BANK0, },
770 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
771 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
772 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
773 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
774 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
775 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
776 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
777 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
778 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
779 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
780 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
781 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
782 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
783 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
784 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
785 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
786 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
787 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
788 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
789 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
790 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
791 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
792 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
793 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
794 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
795 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
796 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
797 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
798 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
799 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
800 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
801 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
802 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
803 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
804 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
805 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
806 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
807 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 808};
809
fad09c73 810static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 811 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 812 int port, u16 bank1_select,
813 u16 histogram)
80c4627b 814{
80c4627b
AL		 815 u32 low;
816 u32 high = 0;
dfafe449 817 u16 reg = 0;
0e7b9925 818 int err;
80c4627b
AL		 819 u64 value;
820
f5e2ed02 821 switch (s->type) {
dfafe449 822 case STATS_TYPE_PORT:
0e7b9925
AL		 823 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
824 if (err)
80c4627b
AL		 825 return UINT64_MAX;
826
0e7b9925 827 low = reg;
80c4627b 828 if (s->sizeof_stat == 4) {
0e7b9925
AL		 829 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
830 if (err)
80c4627b 831 return UINT64_MAX;
0e7b9925 832 high = reg;
80c4627b 833 }
f5e2ed02 834 break;
dfafe449 835 case STATS_TYPE_BANK1:
e0d8b615 836 reg = bank1_select;
dfafe449
AL		 837 /* fall through */
838 case STATS_TYPE_BANK0:
e0d8b615 839 reg |= s->reg | histogram;
7f9ef3af 840 mv88e6xxx_g1_stats_read(chip, reg, &low);
80c4627b 841 if (s->sizeof_stat == 8)
7f9ef3af 842 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
80c4627b
AL		 843 }
844 value = (((u64)high) << 16) | low;
845 return value;
846}
847
dfafe449
AL		 848static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
849 uint8_t *data, int types)
91da11f8 850{
f5e2ed02
AL		 851 struct mv88e6xxx_hw_stat *stat;
852 int i, j;
91da11f8 853
f5e2ed02
AL		 854 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
855 stat = &mv88e6xxx_hw_stats[i];
dfafe449 856 if (stat->type & types) {
f5e2ed02
AL		 857 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
858 ETH_GSTRING_LEN);
859 j++;
860 }
91da11f8 861 }
e413e7e1
AL		 862}
863
dfafe449
AL		 864static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
865 uint8_t *data)
866{
867 mv88e6xxx_stats_get_strings(chip, data,
868 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
869}
870
871static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
872 uint8_t *data)
873{
874 mv88e6xxx_stats_get_strings(chip, data,
875 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
876}
877
878static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
879 uint8_t *data)
e413e7e1 880{
04bed143 881 struct mv88e6xxx_chip *chip = ds->priv;
dfafe449
AL		 882
883 if (chip->info->ops->stats_get_strings)
884 chip->info->ops->stats_get_strings(chip, data);
885}
886
887static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
888 int types)
889{
f5e2ed02
AL		 890 struct mv88e6xxx_hw_stat *stat;
891 int i, j;
892
893 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
894 stat = &mv88e6xxx_hw_stats[i];
dfafe449 895 if (stat->type & types)
f5e2ed02
AL		 896 j++;
897 }
898 return j;
e413e7e1
AL		 899}
900
dfafe449
AL		 901static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
902{
903 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
904 STATS_TYPE_PORT);
905}
906
907static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
908{
909 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
910 STATS_TYPE_BANK1);
911}
912
913static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
914{
915 struct mv88e6xxx_chip *chip = ds->priv;
916
917 if (chip->info->ops->stats_get_sset_count)
918 return chip->info->ops->stats_get_sset_count(chip);
919
920 return 0;
921}
922
052f947f 923static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
e0d8b615
AL		 924 uint64_t *data, int types,
925 u16 bank1_select, u16 histogram)
052f947f
AL		 926{
927 struct mv88e6xxx_hw_stat *stat;
928 int i, j;
929
930 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
931 stat = &mv88e6xxx_hw_stats[i];
932 if (stat->type & types) {
e0d8b615
AL		 933 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
934 bank1_select,
935 histogram);
052f947f
AL		 936 j++;
937 }
938 }
939}
940
941static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
942 uint64_t *data)
943{
944 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 945 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
946 0, GLOBAL_STATS_OP_HIST_RX_TX);
052f947f
AL		 947}
948
949static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
950 uint64_t *data)
951{
952 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 953 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
954 GLOBAL_STATS_OP_BANK_1_BIT_9,
955 GLOBAL_STATS_OP_HIST_RX_TX);
956}
957
958static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
959 uint64_t *data)
960{
961 return mv88e6xxx_stats_get_stats(chip, port, data,
962 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
963 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
052f947f
AL		 964}
965
966static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
967 uint64_t *data)
968{
969 if (chip->info->ops->stats_get_stats)
970 chip->info->ops->stats_get_stats(chip, port, data);
971}
972
f81ec90f
VD		 973static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
974 uint64_t *data)
e413e7e1 975{
04bed143 976 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 977 int ret;
f5e2ed02 978
fad09c73 979 mutex_lock(&chip->reg_lock);
f5e2ed02 980
a605a0fe 981 ret = mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 982 if (ret < 0) {
fad09c73 983 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 984 return;
985 }
052f947f
AL		 986
987 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 988
fad09c73 989 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 990}
991
de227387
AL		 992static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
993{
994 if (chip->info->ops->stats_set_histogram)
995 return chip->info->ops->stats_set_histogram(chip);
996
997 return 0;
998}
999
f81ec90f 1000static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 1001{
1002 return 32 * sizeof(u16);
1003}
1004
f81ec90f
VD		 1005static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1006 struct ethtool_regs *regs, void *_p)
a1ab91f3 1007{
04bed143 1008 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 1009 int err;
1010 u16 reg;
a1ab91f3
GR		 1011 u16 *p = _p;
1012 int i;
1013
1014 regs->version = 0;
1015
1016 memset(p, 0xff, 32 * sizeof(u16));
1017
fad09c73 1018 mutex_lock(&chip->reg_lock);
23062513 1019
a1ab91f3 1020 for (i = 0; i < 32; i++) {
a1ab91f3 1021
0e7b9925
AL		 1022 err = mv88e6xxx_port_read(chip, port, i, &reg);
1023 if (!err)
1024 p[i] = reg;
a1ab91f3 1025 }
23062513 1026
fad09c73 1027 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 1028}
1029
fad09c73 1030static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
facd95b2 1031{
a935c052 1032 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 1033}
1034
f81ec90f
VD		 1035static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1036 struct ethtool_eee *e)
11b3b45d 1037{
04bed143 1038 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1039 u16 reg;
1040 int err;
11b3b45d 1041
fad09c73 1042 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1043 return -EOPNOTSUPP;
1044
fad09c73 1045 mutex_lock(&chip->reg_lock);
2f40c698 1046
9c93829c
VD		 1047 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1048 if (err)
2f40c698 1049 goto out;
11b3b45d
GR		 1050
1051 e->eee_enabled = !!(reg & 0x0200);
1052 e->tx_lpi_enabled = !!(reg & 0x0100);
1053
0e7b9925 1054 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
9c93829c 1055 if (err)
2f40c698 1056 goto out;
11b3b45d 1057
cca8b133 1058 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1059out:
fad09c73 1060 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 1061
1062 return err;
11b3b45d
GR		 1063}
1064
f81ec90f
VD		 1065static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1066 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 1067{
04bed143 1068 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1069 u16 reg;
1070 int err;
11b3b45d 1071
fad09c73 1072 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1073 return -EOPNOTSUPP;
1074
fad09c73 1075 mutex_lock(&chip->reg_lock);
11b3b45d 1076
9c93829c
VD		 1077 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1078 if (err)
2f40c698
AL		 1079 goto out;
1080
9c93829c 1081 reg &= ~0x0300;
2f40c698
AL		 1082 if (e->eee_enabled)
1083 reg |= 0x0200;
1084 if (e->tx_lpi_enabled)
1085 reg |= 0x0100;
1086
9c93829c 1087 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 1088out:
fad09c73 1089 mutex_unlock(&chip->reg_lock);
2f40c698 1090
9c93829c 1091 return err;
11b3b45d
GR		 1092}
1093
fad09c73 1094static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
facd95b2 1095{
a935c052
VD		 1096 u16 val;
1097 int err;
facd95b2 1098
6dc10bbc 1099 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
a935c052
VD		 1100 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
1101 if (err)
1102 return err;
fad09c73 1103 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f 1104 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
a935c052
VD		 1105 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
1106 if (err)
1107 return err;
11ea809f 1108
a935c052
VD		 1109 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
1110 (val & 0xfff) | ((fid << 8) & 0xf000));
1111 if (err)
1112 return err;
11ea809f
VD		 1113
1114 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1115 cmd |= fid & 0xf;
b426e5f7
VD		 1116 }
1117
a935c052
VD		 1118 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
1119 if (err)
1120 return err;
facd95b2 1121
fad09c73 1122 return _mv88e6xxx_atu_wait(chip);
facd95b2
GR		 1123}
1124
fad09c73 1125static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
37705b73
VD		 1126 struct mv88e6xxx_atu_entry *entry)
1127{
1128 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1129
1130 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1131 unsigned int mask, shift;
1132
1133 if (entry->trunk) {
1134 data |= GLOBAL_ATU_DATA_TRUNK;
1135 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1136 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1137 } else {
1138 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1139 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1140 }
1141
1142 data |= (entry->portv_trunkid << shift) & mask;
1143 }
1144
a935c052 1145 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
37705b73
VD		 1146}
1147
fad09c73 1148static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
7fb5e755
VD		 1149 struct mv88e6xxx_atu_entry *entry,
1150 bool static_too)
facd95b2 1151{
7fb5e755
VD		 1152 int op;
1153 int err;
facd95b2 1154
fad09c73 1155 err = _mv88e6xxx_atu_wait(chip);
7fb5e755
VD		 1156 if (err)
1157 return err;
facd95b2 1158
fad09c73 1159 err = _mv88e6xxx_atu_data_write(chip, entry);
7fb5e755
VD		 1160 if (err)
1161 return err;
1162
1163 if (entry->fid) {
7fb5e755
VD		 1164 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1165 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1166 } else {
1167 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1168 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1169 }
1170
fad09c73 1171 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
7fb5e755
VD		 1172}
1173
fad09c73 1174static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
158bc065 1175 u16 fid, bool static_too)
7fb5e755
VD		 1176{
1177 struct mv88e6xxx_atu_entry entry = {
1178 .fid = fid,
1179 .state = 0, /* EntryState bits must be 0 */
1180 };
70cc99d1 1181
fad09c73 1182 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
7fb5e755
VD		 1183}
1184
fad09c73 1185static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1186 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1187{
1188 struct mv88e6xxx_atu_entry entry = {
1189 .trunk = false,
1190 .fid = fid,
1191 };
1192
1193 /* EntryState bits must be 0xF */
1194 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1195
1196 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1197 entry.portv_trunkid = (to_port & 0x0f) << 4;
1198 entry.portv_trunkid |= from_port & 0x0f;
1199
fad09c73 1200 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
9f4d55d2
VD		 1201}
1202
fad09c73 1203static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1204 int port, bool static_too)
9f4d55d2
VD		 1205{
1206 /* Destination port 0xF means remove the entries */
fad09c73 1207 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1208}
1209
fad09c73 1210static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1211{
fad09c73 1212 struct net_device *bridge = chip->ports[port].bridge_dev;
fad09c73 1213 struct dsa_switch *ds = chip->ds;
b7666efe 1214 u16 output_ports = 0;
b7666efe
VD		 1215 int i;
1216
1217 /* allow CPU port or DSA link(s) to send frames to every port */
1218 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
5a7921f4 1219 output_ports = ~0;
b7666efe 1220 } else {
370b4ffb 1221 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b7666efe 1222 /* allow sending frames to every group member */
fad09c73 1223 if (bridge && chip->ports[i].bridge_dev == bridge)
b7666efe
VD		 1224 output_ports |= BIT(i);
1225
1226 /* allow sending frames to CPU port and DSA link(s) */
1227 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1228 output_ports |= BIT(i);
1229 }
1230 }
1231
1232 /* prevent frames from going back out of the port they came in on */
1233 output_ports &= ~BIT(port);
facd95b2 1234
5a7921f4 1235 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 1236}
1237
f81ec90f
VD		 1238static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1239 u8 state)
facd95b2 1240{
04bed143 1241 struct mv88e6xxx_chip *chip = ds->priv;
facd95b2 1242 int stp_state;
553eb544 1243 int err;
facd95b2
GR		 1244
1245 switch (state) {
1246 case BR_STATE_DISABLED:
cca8b133 1247 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1248 break;
1249 case BR_STATE_BLOCKING:
1250 case BR_STATE_LISTENING:
cca8b133 1251 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1252 break;
1253 case BR_STATE_LEARNING:
cca8b133 1254 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1255 break;
1256 case BR_STATE_FORWARDING:
1257 default:
cca8b133 1258 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1259 break;
1260 }
1261
fad09c73 1262 mutex_lock(&chip->reg_lock);
e28def33 1263 err = mv88e6xxx_port_set_state(chip, port, stp_state);
fad09c73 1264 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1265
1266 if (err)
e28def33 1267 netdev_err(ds->ports[port].netdev, "failed to update state\n");
facd95b2
GR		 1268}
1269
749efcb8
VD		 1270static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1271{
1272 struct mv88e6xxx_chip *chip = ds->priv;
1273 int err;
1274
1275 mutex_lock(&chip->reg_lock);
1276 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1277 mutex_unlock(&chip->reg_lock);
1278
1279 if (err)
1280 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1281}
1282
fad09c73 1283static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1284{
a935c052 1285 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
6b17e864
VD		 1286}
1287
fad09c73 1288static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864 1289{
a935c052 1290 int err;
6b17e864 1291
a935c052
VD		 1292 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1293 if (err)
1294 return err;
6b17e864 1295
fad09c73 1296 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1297}
1298
fad09c73 1299static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1300{
1301 int ret;
1302
fad09c73 1303 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1304 if (ret < 0)
1305 return ret;
1306
fad09c73 1307 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1308}
1309
fad09c73 1310static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1311 struct mv88e6xxx_vtu_entry *entry,
b8fee957
VD		 1312 unsigned int nibble_offset)
1313{
b8fee957 1314 u16 regs[3];
a935c052 1315 int i, err;
b8fee957
VD		 1316
1317 for (i = 0; i < 3; ++i) {
a935c052 1318 u16 *reg = &regs[i];
b8fee957 1319
a935c052
VD		 1320 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1321 if (err)
1322 return err;
b8fee957
VD		 1323 }
1324
370b4ffb 1325 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b8fee957
VD		 1326 unsigned int shift = (i % 4) * 4 + nibble_offset;
1327 u16 reg = regs[i / 4];
1328
1329 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1330 }
1331
1332 return 0;
1333}
1334
fad09c73 1335static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1336 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1337{
fad09c73 1338 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1339}
1340
fad09c73 1341static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1342 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1343{
fad09c73 1344 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1345}
1346
fad09c73 1347static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1348 struct mv88e6xxx_vtu_entry *entry,
7dad08d7
VD		 1349 unsigned int nibble_offset)
1350{
7dad08d7 1351 u16 regs[3] = { 0 };
a935c052 1352 int i, err;
7dad08d7 1353
370b4ffb 1354 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7dad08d7
VD		 1355 unsigned int shift = (i % 4) * 4 + nibble_offset;
1356 u8 data = entry->data[i];
1357
1358 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1359 }
1360
1361 for (i = 0; i < 3; ++i) {
a935c052
VD		 1362 u16 reg = regs[i];
1363
1364 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1365 if (err)
1366 return err;
7dad08d7
VD		 1367 }
1368
1369 return 0;
1370}
1371
fad09c73 1372static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1373 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1374{
fad09c73 1375 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1376}
1377
fad09c73 1378static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1379 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1380{
fad09c73 1381 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1382}
1383
fad09c73 1384static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1385{
a935c052
VD		 1386 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1387 vid & GLOBAL_VTU_VID_MASK);
36d04ba1
VD		 1388}
1389
fad09c73 1390static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b4e47c0f 1391 struct mv88e6xxx_vtu_entry *entry)
b8fee957 1392{
b4e47c0f 1393 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1394 u16 val;
1395 int err;
b8fee957 1396
a935c052
VD		 1397 err = _mv88e6xxx_vtu_wait(chip);
1398 if (err)
1399 return err;
b8fee957 1400
a935c052
VD		 1401 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1402 if (err)
1403 return err;
b8fee957 1404
a935c052
VD		 1405 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1406 if (err)
1407 return err;
b8fee957 1408
a935c052
VD		 1409 next.vid = val & GLOBAL_VTU_VID_MASK;
1410 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
b8fee957
VD		 1411
1412 if (next.valid) {
a935c052
VD		 1413 err = mv88e6xxx_vtu_data_read(chip, &next);
1414 if (err)
1415 return err;
b8fee957 1416
6dc10bbc 1417 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
a935c052
VD		 1418 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1419 if (err)
1420 return err;
b8fee957 1421
a935c052 1422 next.fid = val & GLOBAL_VTU_FID_MASK;
fad09c73 1423 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1424 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1425 * VTU DBNum[3:0] are located in VTU Operation 3:0
1426 */
a935c052
VD		 1427 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1428 if (err)
1429 return err;
11ea809f 1430
a935c052
VD		 1431 next.fid = (val & 0xf00) >> 4;
1432 next.fid |= val & 0xf;
2e7bd5ef 1433 }
b8fee957 1434
fad09c73 1435 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
a935c052
VD		 1436 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1437 if (err)
1438 return err;
b8fee957 1439
a935c052 1440 next.sid = val & GLOBAL_VTU_SID_MASK;
b8fee957
VD		 1441 }
1442 }
1443
1444 *entry = next;
1445 return 0;
1446}
1447
f81ec90f
VD		 1448static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1449 struct switchdev_obj_port_vlan *vlan,
1450 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1451{
04bed143 1452 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1453 struct mv88e6xxx_vtu_entry next;
ceff5eff
VD		 1454 u16 pvid;
1455 int err;
1456
fad09c73 1457 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1458 return -EOPNOTSUPP;
1459
fad09c73 1460 mutex_lock(&chip->reg_lock);
ceff5eff 1461
77064f37 1462 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
ceff5eff
VD		 1463 if (err)
1464 goto unlock;
1465
fad09c73 1466 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1467 if (err)
1468 goto unlock;
1469
1470 do {
fad09c73 1471 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1472 if (err)
1473 break;
1474
1475 if (!next.valid)
1476 break;
1477
1478 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1479 continue;
1480
1481 /* reinit and dump this VLAN obj */
57d32310
VD		 1482 vlan->vid_begin = next.vid;
1483 vlan->vid_end = next.vid;
ceff5eff
VD		 1484 vlan->flags = 0;
1485
1486 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1487 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1488
1489 if (next.vid == pvid)
1490 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1491
1492 err = cb(&vlan->obj);
1493 if (err)
1494 break;
1495 } while (next.vid < GLOBAL_VTU_VID_MASK);
1496
1497unlock:
fad09c73 1498 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1499
1500 return err;
1501}
1502
fad09c73 1503static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1504 struct mv88e6xxx_vtu_entry *entry)
7dad08d7 1505{
11ea809f 1506 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7 1507 u16 reg = 0;
a935c052 1508 int err;
7dad08d7 1509
a935c052
VD		 1510 err = _mv88e6xxx_vtu_wait(chip);
1511 if (err)
1512 return err;
7dad08d7
VD		 1513
1514 if (!entry->valid)
1515 goto loadpurge;
1516
1517 /* Write port member tags */
a935c052
VD		 1518 err = mv88e6xxx_vtu_data_write(chip, entry);
1519 if (err)
1520 return err;
7dad08d7 1521
fad09c73 1522 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1523 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1524 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1525 if (err)
1526 return err;
b426e5f7 1527 }
7dad08d7 1528
6dc10bbc 1529 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
7dad08d7 1530 reg = entry->fid & GLOBAL_VTU_FID_MASK;
a935c052
VD		 1531 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1532 if (err)
1533 return err;
fad09c73 1534 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1535 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1536 * VTU DBNum[3:0] are located in VTU Operation 3:0
1537 */
1538 op |= (entry->fid & 0xf0) << 8;
1539 op |= entry->fid & 0xf;
7dad08d7
VD		 1540 }
1541
1542 reg = GLOBAL_VTU_VID_VALID;
1543loadpurge:
1544 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
a935c052
VD		 1545 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1546 if (err)
1547 return err;
7dad08d7 1548
fad09c73 1549 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1550}
1551
fad09c73 1552static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
b4e47c0f 1553 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1554{
b4e47c0f 1555 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1556 u16 val;
1557 int err;
0d3b33e6 1558
a935c052
VD		 1559 err = _mv88e6xxx_vtu_wait(chip);
1560 if (err)
1561 return err;
0d3b33e6 1562
a935c052
VD		 1563 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1564 sid & GLOBAL_VTU_SID_MASK);
1565 if (err)
1566 return err;
0d3b33e6 1567
a935c052
VD		 1568 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1569 if (err)
1570 return err;
0d3b33e6 1571
a935c052
VD		 1572 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1573 if (err)
1574 return err;
0d3b33e6 1575
a935c052 1576 next.sid = val & GLOBAL_VTU_SID_MASK;
0d3b33e6 1577
a935c052
VD		 1578 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1579 if (err)
1580 return err;
0d3b33e6 1581
a935c052 1582 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
0d3b33e6
VD		 1583
1584 if (next.valid) {
a935c052
VD		 1585 err = mv88e6xxx_stu_data_read(chip, &next);
1586 if (err)
1587 return err;
0d3b33e6
VD		 1588 }
1589
1590 *entry = next;
1591 return 0;
1592}
1593
fad09c73 1594static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1595 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6
VD		 1596{
1597 u16 reg = 0;
a935c052 1598 int err;
0d3b33e6 1599
a935c052
VD		 1600 err = _mv88e6xxx_vtu_wait(chip);
1601 if (err)
1602 return err;
0d3b33e6
VD		 1603
1604 if (!entry->valid)
1605 goto loadpurge;
1606
1607 /* Write port states */
a935c052
VD		 1608 err = mv88e6xxx_stu_data_write(chip, entry);
1609 if (err)
1610 return err;
0d3b33e6
VD		 1611
1612 reg = GLOBAL_VTU_VID_VALID;
1613loadpurge:
a935c052
VD		 1614 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1615 if (err)
1616 return err;
0d3b33e6
VD		 1617
1618 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1619 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1620 if (err)
1621 return err;
0d3b33e6 1622
fad09c73 1623 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1624}
1625
fad09c73 1626static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1627{
1628 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
b4e47c0f 1629 struct mv88e6xxx_vtu_entry vlan;
2db9ce1f 1630 int i, err;
3285f9e8
VD		 1631
1632 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1633
2db9ce1f 1634 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1635 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1636 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1637 if (err)
1638 return err;
1639
1640 set_bit(*fid, fid_bitmap);
1641 }
1642
3285f9e8 1643 /* Set every FID bit used by the VLAN entries */
fad09c73 1644 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1645 if (err)
1646 return err;
1647
1648 do {
fad09c73 1649 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1650 if (err)
1651 return err;
1652
1653 if (!vlan.valid)
1654 break;
1655
1656 set_bit(vlan.fid, fid_bitmap);
1657 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1658
1659 /* The reset value 0x000 is used to indicate that multiple address
1660 * databases are not needed. Return the next positive available.
1661 */
1662 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1663 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1664 return -ENOSPC;
1665
1666 /* Clear the database */
fad09c73 1667 return _mv88e6xxx_atu_flush(chip, *fid, true);
3285f9e8
VD		 1668}
1669
fad09c73 1670static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1671 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1672{
fad09c73 1673 struct dsa_switch *ds = chip->ds;
b4e47c0f 1674 struct mv88e6xxx_vtu_entry vlan = {
0d3b33e6
VD		 1675 .valid = true,
1676 .vid = vid,
1677 };
3285f9e8
VD		 1678 int i, err;
1679
fad09c73 1680 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
3285f9e8
VD		 1681 if (err)
1682 return err;
0d3b33e6 1683
3d131f07 1684 /* exclude all ports except the CPU and DSA ports */
370b4ffb 1685 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
3d131f07
VD		 1686 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1687 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1688 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1689
fad09c73
VD		 1690 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1691 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
b4e47c0f 1692 struct mv88e6xxx_vtu_entry vstp;
0d3b33e6
VD		 1693
1694 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1695 * implemented, only one STU entry is needed to cover all VTU
1696 * entries. Thus, validate the SID 0.
1697 */
1698 vlan.sid = 0;
fad09c73 1699 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1700 if (err)
1701 return err;
1702
1703 if (vstp.sid != vlan.sid || !vstp.valid) {
1704 memset(&vstp, 0, sizeof(vstp));
1705 vstp.valid = true;
1706 vstp.sid = vlan.sid;
1707
fad09c73 1708 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1709 if (err)
1710 return err;
1711 }
0d3b33e6
VD		 1712 }
1713
1714 *entry = vlan;
1715 return 0;
1716}
1717
fad09c73 1718static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1719 struct mv88e6xxx_vtu_entry *entry, bool creat)
2fb5ef09
VD		 1720{
1721 int err;
1722
1723 if (!vid)
1724 return -EINVAL;
1725
fad09c73 1726 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1727 if (err)
1728 return err;
1729
fad09c73 1730 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1731 if (err)
1732 return err;
1733
1734 if (entry->vid != vid || !entry->valid) {
1735 if (!creat)
1736 return -EOPNOTSUPP;
1737 /* -ENOENT would've been more appropriate, but switchdev expects
1738 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1739 */
1740
fad09c73 1741 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1742 }
1743
1744 return err;
1745}
1746
da9c359e
VD		 1747static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1748 u16 vid_begin, u16 vid_end)
1749{
04bed143 1750 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1751 struct mv88e6xxx_vtu_entry vlan;
da9c359e
VD		 1752 int i, err;
1753
1754 if (!vid_begin)
1755 return -EOPNOTSUPP;
1756
fad09c73 1757 mutex_lock(&chip->reg_lock);
da9c359e 1758
fad09c73 1759 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1760 if (err)
1761 goto unlock;
1762
1763 do {
fad09c73 1764 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1765 if (err)
1766 goto unlock;
1767
1768 if (!vlan.valid)
1769 break;
1770
1771 if (vlan.vid > vid_end)
1772 break;
1773
370b4ffb 1774 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1775 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1776 continue;
1777
66e2809d
AL		 1778 if (!ds->ports[port].netdev)
1779 continue;
1780
da9c359e
VD		 1781 if (vlan.data[i] ==
1782 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1783 continue;
1784
fad09c73
VD		 1785 if (chip->ports[i].bridge_dev ==
1786 chip->ports[port].bridge_dev)
da9c359e
VD		 1787 break; /* same bridge, check next VLAN */
1788
66e2809d
AL		 1789 if (!chip->ports[i].bridge_dev)
1790 continue;
1791
c8b09808 1792 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1793 "hardware VLAN %d already used by %s\n",
1794 vlan.vid,
fad09c73 1795 netdev_name(chip->ports[i].bridge_dev));
da9c359e
VD		 1796 err = -EOPNOTSUPP;
1797 goto unlock;
1798 }
1799 } while (vlan.vid < vid_end);
1800
1801unlock:
fad09c73 1802 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1803
1804 return err;
1805}
1806
f81ec90f
VD		 1807static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1808 bool vlan_filtering)
214cdb99 1809{
04bed143 1810 struct mv88e6xxx_chip *chip = ds->priv;
385a0995 1811 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
214cdb99 1812 PORT_CONTROL_2_8021Q_DISABLED;
0e7b9925 1813 int err;
214cdb99 1814
fad09c73 1815 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1816 return -EOPNOTSUPP;
1817
fad09c73 1818 mutex_lock(&chip->reg_lock);
385a0995 1819 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1820 mutex_unlock(&chip->reg_lock);
214cdb99 1821
0e7b9925 1822 return err;
214cdb99
VD		 1823}
1824
57d32310
VD		 1825static int
1826mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1827 const struct switchdev_obj_port_vlan *vlan,
1828 struct switchdev_trans *trans)
76e398a6 1829{
04bed143 1830 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1831 int err;
1832
fad09c73 1833 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1834 return -EOPNOTSUPP;
1835
da9c359e
VD		 1836 /* If the requested port doesn't belong to the same bridge as the VLAN
1837 * members, do not support it (yet) and fallback to software VLAN.
1838 */
1839 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1840 vlan->vid_end);
1841 if (err)
1842 return err;
1843
76e398a6
VD		 1844 /* We don't need any dynamic resource from the kernel (yet),
1845 * so skip the prepare phase.
1846 */
1847 return 0;
1848}
1849
fad09c73 1850static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1851 u16 vid, bool untagged)
0d3b33e6 1852{
b4e47c0f 1853 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1854 int err;
1855
fad09c73 1856 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1857 if (err)
76e398a6 1858 return err;
0d3b33e6 1859
0d3b33e6
VD		 1860 vlan.data[port] = untagged ?
1861 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1862 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1863
fad09c73 1864 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1865}
1866
f81ec90f
VD		 1867static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1868 const struct switchdev_obj_port_vlan *vlan,
1869 struct switchdev_trans *trans)
76e398a6 1870{
04bed143 1871 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1872 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1873 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1874 u16 vid;
76e398a6 1875
fad09c73 1876 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1877 return;
1878
fad09c73 1879 mutex_lock(&chip->reg_lock);
76e398a6 1880
4d5770b3 1881 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1882 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1883 netdev_err(ds->ports[port].netdev,
1884 "failed to add VLAN %d%c\n",
4d5770b3 1885 vid, untagged ? 'u' : 't');
76e398a6 1886
77064f37 1887 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
c8b09808 1888 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1889 vlan->vid_end);
0d3b33e6 1890
fad09c73 1891 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1892}
1893
fad09c73 1894static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1895 int port, u16 vid)
7dad08d7 1896{
fad09c73 1897 struct dsa_switch *ds = chip->ds;
b4e47c0f 1898 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1899 int i, err;
1900
fad09c73 1901 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1902 if (err)
76e398a6 1903 return err;
7dad08d7 1904
2fb5ef09
VD		 1905 /* Tell switchdev if this VLAN is handled in software */
1906 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1907 return -EOPNOTSUPP;
7dad08d7
VD		 1908
1909 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1910
1911 /* keep the VLAN unless all ports are excluded */
f02bdffc 1912 vlan.valid = false;
370b4ffb 1913 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
3d131f07 1914 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1915 continue;
1916
1917 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1918 vlan.valid = true;
7dad08d7
VD		 1919 break;
1920 }
1921 }
1922
fad09c73 1923 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1924 if (err)
1925 return err;
1926
fad09c73 1927 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1928}
1929
f81ec90f
VD		 1930static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1931 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1932{
04bed143 1933 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1934 u16 pvid, vid;
1935 int err = 0;
1936
fad09c73 1937 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1938 return -EOPNOTSUPP;
1939
fad09c73 1940 mutex_lock(&chip->reg_lock);
76e398a6 1941
77064f37 1942 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1943 if (err)
1944 goto unlock;
1945
76e398a6 1946 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1947 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1948 if (err)
1949 goto unlock;
1950
1951 if (vid == pvid) {
77064f37 1952 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1953 if (err)
1954 goto unlock;
1955 }
1956 }
1957
7dad08d7 1958unlock:
fad09c73 1959 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 1960
1961 return err;
1962}
1963
fad09c73 1964static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
c5723ac5 1965 const unsigned char *addr)
defb05b9 1966{
a935c052 1967 int i, err;
defb05b9
GR		 1968
1969 for (i = 0; i < 3; i++) {
a935c052
VD		 1970 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
1971 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1972 if (err)
1973 return err;
defb05b9
GR		 1974 }
1975
1976 return 0;
1977}
1978
fad09c73 1979static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
158bc065 1980 unsigned char *addr)
defb05b9 1981{
a935c052
VD		 1982 u16 val;
1983 int i, err;
defb05b9
GR		 1984
1985 for (i = 0; i < 3; i++) {
a935c052
VD		 1986 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
1987 if (err)
1988 return err;
1989
1990 addr[i * 2] = val >> 8;
1991 addr[i * 2 + 1] = val & 0xff;
defb05b9
GR		 1992 }
1993
1994 return 0;
1995}
1996
fad09c73 1997static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
fd231c82 1998 struct mv88e6xxx_atu_entry *entry)
defb05b9 1999{
6630e236
VD		 2000 int ret;
2001
fad09c73 2002 ret = _mv88e6xxx_atu_wait(chip);
defb05b9
GR		 2003 if (ret < 0)
2004 return ret;
2005
fad09c73 2006 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
defb05b9
GR		 2007 if (ret < 0)
2008 return ret;
2009
fad09c73 2010 ret = _mv88e6xxx_atu_data_write(chip, entry);
fd231c82 2011 if (ret < 0)
87820510
VD		 2012 return ret;
2013
fad09c73 2014 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2015}
87820510 2016
88472939
VD		 2017static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2018 struct mv88e6xxx_atu_entry *entry);
2019
2020static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2021 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2022{
2023 struct mv88e6xxx_atu_entry next;
2024 int err;
2025
59527581
AL		 2026 memcpy(next.mac, addr, ETH_ALEN);
2027 eth_addr_dec(next.mac);
88472939
VD		 2028
2029 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2030 if (err)
2031 return err;
2032
2033 do {
2034 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2035 if (err)
2036 return err;
2037
2038 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2039 break;
2040
2041 if (ether_addr_equal(next.mac, addr)) {
2042 *entry = next;
2043 return 0;
2044 }
59527581 2045 } while (ether_addr_greater(addr, next.mac));
88472939
VD		 2046
2047 memset(entry, 0, sizeof(*entry));
2048 entry->fid = fid;
2049 ether_addr_copy(entry->mac, addr);
2050
2051 return 0;
2052}
2053
83dabd1f
VD		 2054static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2055 const unsigned char *addr, u16 vid,
2056 u8 state)
fd231c82 2057{
b4e47c0f 2058 struct mv88e6xxx_vtu_entry vlan;
88472939 2059 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 2060 int err;
2061
2db9ce1f
VD		 2062 /* Null VLAN ID corresponds to the port private database */
2063 if (vid == 0)
b4e48c50 2064 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2db9ce1f 2065 else
fad09c73 2066 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 2067 if (err)
2068 return err;
fd231c82 2069
88472939
VD		 2070 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2071 if (err)
2072 return err;
2073
2074 /* Purge the ATU entry only if no port is using it anymore */
2075 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2076 entry.portv_trunkid &= ~BIT(port);
2077 if (!entry.portv_trunkid)
2078 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2079 } else {
2080 entry.portv_trunkid |= BIT(port);
2081 entry.state = state;
fd231c82
VD		 2082 }
2083
fad09c73 2084 return _mv88e6xxx_atu_load(chip, &entry);
87820510
VD		 2085}
2086
f81ec90f
VD		 2087static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2088 const struct switchdev_obj_port_fdb *fdb,
2089 struct switchdev_trans *trans)
146a3206
VD		 2090{
2091 /* We don't need any dynamic resource from the kernel (yet),
2092 * so skip the prepare phase.
2093 */
2094 return 0;
2095}
2096
f81ec90f
VD		 2097static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2098 const struct switchdev_obj_port_fdb *fdb,
2099 struct switchdev_trans *trans)
87820510 2100{
04bed143 2101 struct mv88e6xxx_chip *chip = ds->priv;
87820510 2102
fad09c73 2103 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2104 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2105 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2106 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
fad09c73 2107 mutex_unlock(&chip->reg_lock);
87820510
VD		 2108}
2109
f81ec90f
VD		 2110static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2111 const struct switchdev_obj_port_fdb *fdb)
87820510 2112{
04bed143 2113 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 2114 int err;
87820510 2115
fad09c73 2116 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2117 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2118 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 2119 mutex_unlock(&chip->reg_lock);
87820510 2120
83dabd1f 2121 return err;
87820510
VD		 2122}
2123
fad09c73 2124static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
1d194046 2125 struct mv88e6xxx_atu_entry *entry)
6630e236 2126{
1d194046 2127 struct mv88e6xxx_atu_entry next = { 0 };
a935c052
VD		 2128 u16 val;
2129 int err;
1d194046
VD		 2130
2131 next.fid = fid;
defb05b9 2132
a935c052
VD		 2133 err = _mv88e6xxx_atu_wait(chip);
2134 if (err)
2135 return err;
6630e236 2136
a935c052
VD		 2137 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2138 if (err)
2139 return err;
6630e236 2140
a935c052
VD		 2141 err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2142 if (err)
2143 return err;
6630e236 2144
a935c052
VD		 2145 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2146 if (err)
2147 return err;
6630e236 2148
a935c052 2149 next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
1d194046
VD		 2150 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2151 unsigned int mask, shift;
2152
a935c052 2153 if (val & GLOBAL_ATU_DATA_TRUNK) {
1d194046
VD		 2154 next.trunk = true;
2155 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2156 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2157 } else {
2158 next.trunk = false;
2159 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2160 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2161 }
2162
a935c052 2163 next.portv_trunkid = (val & mask) >> shift;
1d194046 2164 }
cdf09697 2165
1d194046 2166 *entry = next;
cdf09697
DM		 2167 return 0;
2168}
2169
83dabd1f
VD		 2170static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2171 u16 fid, u16 vid, int port,
2172 struct switchdev_obj *obj,
2173 int (*cb)(struct switchdev_obj *obj))
74b6ba0d
VD		 2174{
2175 struct mv88e6xxx_atu_entry addr = {
2176 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2177 };
2178 int err;
2179
fad09c73 2180 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
74b6ba0d
VD		 2181 if (err)
2182 return err;
2183
2184 do {
fad09c73 2185 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
74b6ba0d 2186 if (err)
83dabd1f 2187 return err;
74b6ba0d
VD		 2188
2189 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2190 break;
2191
83dabd1f
VD		 2192 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2193 continue;
2194
2195 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2196 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 2197
83dabd1f
VD		 2198 if (!is_unicast_ether_addr(addr.mac))
2199 continue;
2200
2201 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 2202 fdb->vid = vid;
2203 ether_addr_copy(fdb->addr, addr.mac);
83dabd1f
VD		 2204 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2205 fdb->ndm_state = NUD_NOARP;
2206 else
2207 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 2208 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2209 struct switchdev_obj_port_mdb *mdb;
2210
2211 if (!is_multicast_ether_addr(addr.mac))
2212 continue;
2213
2214 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2215 mdb->vid = vid;
2216 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 2217 } else {
2218 return -EOPNOTSUPP;
74b6ba0d 2219 }
83dabd1f
VD		 2220
2221 err = cb(obj);
2222 if (err)
2223 return err;
74b6ba0d
VD		 2224 } while (!is_broadcast_ether_addr(addr.mac));
2225
2226 return err;
2227}
2228
83dabd1f
VD		 2229static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2230 struct switchdev_obj *obj,
2231 int (*cb)(struct switchdev_obj *obj))
f33475bd 2232{
b4e47c0f 2233 struct mv88e6xxx_vtu_entry vlan = {
f33475bd
VD		 2234 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2235 };
2db9ce1f 2236 u16 fid;
f33475bd
VD		 2237 int err;
2238
2db9ce1f 2239 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 2240 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 2241 if (err)
83dabd1f 2242 return err;
2db9ce1f 2243
83dabd1f 2244 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 2245 if (err)
83dabd1f 2246 return err;
2db9ce1f 2247
74b6ba0d 2248 /* Dump VLANs' Filtering Information Databases */
fad09c73 2249 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd 2250 if (err)
83dabd1f 2251 return err;
f33475bd
VD		 2252
2253 do {
fad09c73 2254 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2255 if (err)
83dabd1f 2256 return err;
f33475bd
VD		 2257
2258 if (!vlan.valid)
2259 break;
2260
83dabd1f
VD		 2261 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2262 obj, cb);
f33475bd 2263 if (err)
83dabd1f 2264 return err;
f33475bd
VD		 2265 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2266
83dabd1f
VD		 2267 return err;
2268}
2269
2270static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2271 struct switchdev_obj_port_fdb *fdb,
2272 int (*cb)(struct switchdev_obj *obj))
2273{
04bed143 2274 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 2275 int err;
2276
2277 mutex_lock(&chip->reg_lock);
2278 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 2279 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2280
2281 return err;
2282}
2283
f81ec90f
VD		 2284static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2285 struct net_device *bridge)
e79a8bcb 2286{
04bed143 2287 struct mv88e6xxx_chip *chip = ds->priv;
1d9619d5 2288 int i, err = 0;
466dfa07 2289
fad09c73 2290 mutex_lock(&chip->reg_lock);
466dfa07 2291
b7666efe 2292 /* Assign the bridge and remap each port's VLANTable */
fad09c73 2293 chip->ports[port].bridge_dev = bridge;
b7666efe 2294
370b4ffb 2295 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
fad09c73
VD		 2296 if (chip->ports[i].bridge_dev == bridge) {
2297 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2298 if (err)
2299 break;
2300 }
2301 }
2302
fad09c73 2303 mutex_unlock(&chip->reg_lock);
a6692754 2304
466dfa07 2305 return err;
e79a8bcb
VD		 2306}
2307
f81ec90f 2308static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2309{
04bed143 2310 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 2311 struct net_device *bridge = chip->ports[port].bridge_dev;
16bfa702 2312 int i;
466dfa07 2313
fad09c73 2314 mutex_lock(&chip->reg_lock);
466dfa07 2315
b7666efe 2316 /* Unassign the bridge and remap each port's VLANTable */
fad09c73 2317 chip->ports[port].bridge_dev = NULL;
b7666efe 2318
370b4ffb 2319 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
fad09c73
VD		 2320 if (i == port || chip->ports[i].bridge_dev == bridge)
2321 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2322 netdev_warn(ds->ports[i].netdev,
2323 "failed to remap\n");
b7666efe 2324
fad09c73 2325 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2326}
2327
17e708ba
VD		 2328static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2329{
2330 if (chip->info->ops->reset)
2331 return chip->info->ops->reset(chip);
2332
2333 return 0;
2334}
2335
309eca6d
VD		 2336static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2337{
2338 struct gpio_desc *gpiod = chip->reset;
2339
2340 /* If there is a GPIO connected to the reset pin, toggle it */
2341 if (gpiod) {
2342 gpiod_set_value_cansleep(gpiod, 1);
2343 usleep_range(10000, 20000);
2344 gpiod_set_value_cansleep(gpiod, 0);
2345 usleep_range(10000, 20000);
2346 }
2347}
2348
4ac4b5a6 2349static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
552238b5 2350{
4ac4b5a6 2351 int i, err;
552238b5 2352
4ac4b5a6 2353 /* Set all ports to the Disabled state */
370b4ffb 2354 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
e28def33
VD		 2355 err = mv88e6xxx_port_set_state(chip, i,
2356 PORT_CONTROL_STATE_DISABLED);
0e7b9925
AL		 2357 if (err)
2358 return err;
552238b5
VD		 2359 }
2360
4ac4b5a6
VD		 2361 /* Wait for transmit queues to drain,
2362 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2363 */
552238b5
VD		 2364 usleep_range(2000, 4000);
2365
4ac4b5a6
VD		 2366 return 0;
2367}
2368
2369static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2370{
4ac4b5a6
VD		 2371 int err;
2372
2373 err = mv88e6xxx_disable_ports(chip);
2374 if (err)
2375 return err;
2376
309eca6d 2377 mv88e6xxx_hardware_reset(chip);
552238b5 2378
17e708ba 2379 return mv88e6xxx_software_reset(chip);
552238b5
VD		 2380}
2381
09cb7dfd 2382static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
13a7ebb3 2383{
09cb7dfd
VD		 2384 u16 val;
2385 int err;
13a7ebb3 2386
09cb7dfd
VD		 2387 /* Clear Power Down bit */
2388 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2389 if (err)
2390 return err;
13a7ebb3 2391
09cb7dfd
VD		 2392 if (val & BMCR_PDOWN) {
2393 val &= ~BMCR_PDOWN;
2394 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
13a7ebb3
PU		 2395 }
2396
09cb7dfd 2397 return err;
13a7ebb3
PU		 2398}
2399
56995cbc
AL		 2400static int mv88e6xxx_setup_port_dsa(struct mv88e6xxx_chip *chip, int port,
2401 int upstream_port)
2402{
2403 int err;
2404
2405 err = chip->info->ops->port_set_frame_mode(
2406 chip, port, MV88E6XXX_FRAME_MODE_DSA);
2407 if (err)
2408 return err;
2409
2410 return chip->info->ops->port_set_egress_unknowns(
2411 chip, port, port == upstream_port);
2412}
2413
2414static int mv88e6xxx_setup_port_cpu(struct mv88e6xxx_chip *chip, int port)
2415{
2416 int err;
2417
2418 switch (chip->info->tag_protocol) {
2419 case DSA_TAG_PROTO_EDSA:
2420 err = chip->info->ops->port_set_frame_mode(
2421 chip, port, MV88E6XXX_FRAME_MODE_ETHERTYPE);
2422 if (err)
2423 return err;
2424
2425 err = mv88e6xxx_port_set_egress_mode(
2426 chip, port, PORT_CONTROL_EGRESS_ADD_TAG);
2427 if (err)
2428 return err;
2429
2430 if (chip->info->ops->port_set_ether_type)
2431 err = chip->info->ops->port_set_ether_type(
2432 chip, port, ETH_P_EDSA);
2433 break;
2434
2435 case DSA_TAG_PROTO_DSA:
2436 err = chip->info->ops->port_set_frame_mode(
2437 chip, port, MV88E6XXX_FRAME_MODE_DSA);
2438 if (err)
2439 return err;
2440
2441 err = mv88e6xxx_port_set_egress_mode(
2442 chip, port, PORT_CONTROL_EGRESS_UNMODIFIED);
2443 break;
2444 default:
2445 err = -EINVAL;
2446 }
2447
2448 if (err)
2449 return err;
2450
2451 return chip->info->ops->port_set_egress_unknowns(chip, port, true);
2452}
2453
2454static int mv88e6xxx_setup_port_normal(struct mv88e6xxx_chip *chip, int port)
2455{
2456 int err;
2457
2458 err = chip->info->ops->port_set_frame_mode(
2459 chip, port, MV88E6XXX_FRAME_MODE_NORMAL);
2460 if (err)
2461 return err;
2462
2463 return chip->info->ops->port_set_egress_unknowns(chip, port, false);
2464}
2465
fad09c73 2466static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2467{
fad09c73 2468 struct dsa_switch *ds = chip->ds;
0e7b9925 2469 int err;
54d792f2 2470 u16 reg;
d827e88a 2471
d78343d2
VD		 2472 /* MAC Forcing register: don't force link, speed, duplex or flow control
2473 * state to any particular values on physical ports, but force the CPU
2474 * port and all DSA ports to their maximum bandwidth and full duplex.
2475 */
2476 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2477 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2478 SPEED_MAX, DUPLEX_FULL,
2479 PHY_INTERFACE_MODE_NA);
2480 else
2481 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2482 SPEED_UNFORCED, DUPLEX_UNFORCED,
2483 PHY_INTERFACE_MODE_NA);
2484 if (err)
2485 return err;
54d792f2
AL		 2486
2487 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2488 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2489 * tunneling, determine priority by looking at 802.1p and IP
2490 * priority fields (IP prio has precedence), and set STP state
2491 * to Forwarding.
2492 *
2493 * If this is the CPU link, use DSA or EDSA tagging depending
2494 * on which tagging mode was configured.
2495 *
2496 * If this is a link to another switch, use DSA tagging mode.
2497 *
2498 * If this is the upstream port for this switch, enable
2499 * forwarding of unknown unicasts and multicasts.
2500 */
56995cbc 2501 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
54d792f2
AL		 2502 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2503 PORT_CONTROL_STATE_FORWARDING;
56995cbc
AL		 2504 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2505 if (err)
2506 return err;
6083ce71 2507
56995cbc
AL		 2508 if (dsa_is_cpu_port(ds, port)) {
2509 err = mv88e6xxx_setup_port_cpu(chip, port);
2510 } else if (dsa_is_dsa_port(ds, port)) {
2511 err = mv88e6xxx_setup_port_dsa(chip, port,
2512 dsa_upstream_port(ds));
2513 } else {
2514 err = mv88e6xxx_setup_port_normal(chip, port);
54d792f2 2515 }
56995cbc
AL		 2516 if (err)
2517 return err;
54d792f2 2518
13a7ebb3
PU		 2519 /* If this port is connected to a SerDes, make sure the SerDes is not
2520 * powered down.
2521 */
09cb7dfd 2522 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
0e7b9925
AL		 2523 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2524 if (err)
2525 return err;
2526 reg &= PORT_STATUS_CMODE_MASK;
2527 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2528 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2529 (reg == PORT_STATUS_CMODE_SGMII)) {
2530 err = mv88e6xxx_serdes_power_on(chip);
2531 if (err < 0)
2532 return err;
13a7ebb3
PU		 2533 }
2534 }
2535
8efdda4a 2536 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2537 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2538 * untagged frames on this port, do a destination address lookup on all
2539 * received packets as usual, disable ARP mirroring and don't send a
2540 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2541 */
2542 reg = 0;
fad09c73
VD		 2543 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2544 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2545 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2546 mv88e6xxx_6185_family(chip))
54d792f2
AL		 2547 reg = PORT_CONTROL_2_MAP_DA;
2548
fad09c73 2549 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
54d792f2
AL		 2550 /* Set the upstream port this port should use */
2551 reg |= dsa_upstream_port(ds);
2552 /* enable forwarding of unknown multicast addresses to
2553 * the upstream port
2554 */
2555 if (port == dsa_upstream_port(ds))
2556 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2557 }
2558
46fbe5e5 2559 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2560
54d792f2 2561 if (reg) {
0e7b9925
AL		 2562 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
2563 if (err)
2564 return err;
54d792f2
AL		 2565 }
2566
5f436666
AL		 2567 if (chip->info->ops->port_jumbo_config) {
2568 err = chip->info->ops->port_jumbo_config(chip, port);
2569 if (err)
2570 return err;
2571 }
2572
54d792f2
AL		 2573 /* Port Association Vector: when learning source addresses
2574 * of packets, add the address to the address database using
2575 * a port bitmap that has only the bit for this port set and
2576 * the other bits clear.
2577 */
4c7ea3c0 2578 reg = 1 << port;
996ecb82
VD		 2579 /* Disable learning for CPU port */
2580 if (dsa_is_cpu_port(ds, port))
65fa4027 2581 reg = 0;
4c7ea3c0 2582
0e7b9925
AL		 2583 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2584 if (err)
2585 return err;
54d792f2
AL		 2586
2587 /* Egress rate control 2: disable egress rate control. */
0e7b9925
AL		 2588 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2589 if (err)
2590 return err;
54d792f2 2591
b35d322a
AL		 2592 if (chip->info->ops->port_pause_config) {
2593 err = chip->info->ops->port_pause_config(chip, port);
0e7b9925
AL		 2594 if (err)
2595 return err;
b35d322a 2596 }
54d792f2 2597
b35d322a
AL		 2598 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2599 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2600 mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2601 /* Port ATU control: disable limiting the number of
2602 * address database entries that this port is allowed
2603 * to use.
2604 */
0e7b9925
AL		 2605 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2606 0x0000);
54d792f2
AL		 2607 /* Priority Override: disable DA, SA and VTU priority
2608 * override.
2609 */
0e7b9925
AL		 2610 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2611 0x0000);
2612 if (err)
2613 return err;
ef0a7318 2614 }
2bbb33be 2615
ef0a7318
AL		 2616 if (chip->info->ops->port_tag_remap) {
2617 err = chip->info->ops->port_tag_remap(chip, port);
0e7b9925
AL		 2618 if (err)
2619 return err;
54d792f2
AL		 2620 }
2621
ef70b111
AL		 2622 if (chip->info->ops->port_egress_rate_limiting) {
2623 err = chip->info->ops->port_egress_rate_limiting(chip, port);
0e7b9925
AL		 2624 if (err)
2625 return err;
54d792f2
AL		 2626 }
2627
366f0a0f
GR		 2628 /* Port Control 1: disable trunking, disable sending
2629 * learning messages to this port.
d827e88a 2630 */
0e7b9925
AL		 2631 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2632 if (err)
2633 return err;
d827e88a 2634
207afda1 2635 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2636 * database, and allow bidirectional communication between the
2637 * CPU and DSA port(s), and the other ports.
d827e88a 2638 */
b4e48c50 2639 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 2640 if (err)
2641 return err;
2db9ce1f 2642
0e7b9925
AL		 2643 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2644 if (err)
2645 return err;
d827e88a
GR		 2646
2647 /* Default VLAN ID and priority: don't set a default VLAN
2648 * ID, and set the default packet priority to zero.
2649 */
0e7b9925 2650 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
dbde9e66
AL		 2651}
2652
aa0938c6 2653static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3b4caa1b
VD		 2654{
2655 int err;
2656
a935c052 2657 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
3b4caa1b
VD		 2658 if (err)
2659 return err;
2660
a935c052 2661 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
3b4caa1b
VD		 2662 if (err)
2663 return err;
2664
a935c052
VD		 2665 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2666 if (err)
2667 return err;
2668
2669 return 0;
3b4caa1b
VD		 2670}
2671
acddbd21
VD		 2672static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2673 unsigned int msecs)
2674{
2675 const unsigned int coeff = chip->info->age_time_coeff;
2676 const unsigned int min = 0x01 * coeff;
2677 const unsigned int max = 0xff * coeff;
2678 u8 age_time;
2679 u16 val;
2680 int err;
2681
2682 if (msecs < min || msecs > max)
2683 return -ERANGE;
2684
2685 /* Round to nearest multiple of coeff */
2686 age_time = (msecs + coeff / 2) / coeff;
2687
a935c052 2688 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
acddbd21
VD		 2689 if (err)
2690 return err;
2691
2692 /* AgeTime is 11:4 bits */
2693 val &= ~0xff0;
2694 val |= age_time << 4;
2695
a935c052 2696 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
acddbd21
VD		 2697}
2698
2cfcd964
VD		 2699static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2700 unsigned int ageing_time)
2701{
04bed143 2702 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2703 int err;
2704
2705 mutex_lock(&chip->reg_lock);
2706 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2707 mutex_unlock(&chip->reg_lock);
2708
2709 return err;
2710}
2711
9729934c 2712static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2713{
fad09c73 2714 struct dsa_switch *ds = chip->ds;
b0745e87 2715 u32 upstream_port = dsa_upstream_port(ds);
552238b5 2716 int err;
54d792f2 2717
119477bd
VD		 2718 /* Enable the PHY Polling Unit if present, don't discard any packets,
2719 * and mask all interrupt sources.
2720 */
a199d8b6 2721 err = mv88e6xxx_ppu_enable(chip);
119477bd
VD		 2722 if (err)
2723 return err;
2724
33641994
AL		 2725 if (chip->info->ops->g1_set_cpu_port) {
2726 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port);
2727 if (err)
2728 return err;
2729 }
2730
2731 if (chip->info->ops->g1_set_egress_port) {
2732 err = chip->info->ops->g1_set_egress_port(chip, upstream_port);
2733 if (err)
2734 return err;
2735 }
b0745e87 2736
50484ff4 2737 /* Disable remote management, and set the switch's DSA device number. */
a935c052
VD		 2738 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2739 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2740 (ds->index & 0x1f));
50484ff4
VD		 2741 if (err)
2742 return err;
2743
acddbd21
VD		 2744 /* Clear all the VTU and STU entries */
2745 err = _mv88e6xxx_vtu_stu_flush(chip);
2746 if (err < 0)
2747 return err;
2748
54d792f2
AL		 2749 /* Set the default address aging time to 5 minutes, and
2750 * enable address learn messages to be sent to all message
2751 * ports.
2752 */
a935c052
VD		 2753 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2754 GLOBAL_ATU_CONTROL_LEARN2ALL);
48ace4ef 2755 if (err)
08a01261 2756 return err;
54d792f2 2757
acddbd21
VD		 2758 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2759 if (err)
9729934c
VD		 2760 return err;
2761
2762 /* Clear all ATU entries */
2763 err = _mv88e6xxx_atu_flush(chip, 0, true);
2764 if (err)
2765 return err;
2766
54d792f2 2767 /* Configure the IP ToS mapping registers. */
a935c052 2768 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2769 if (err)
08a01261 2770 return err;
a935c052 2771 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2772 if (err)
08a01261 2773 return err;
a935c052 2774 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2775 if (err)
08a01261 2776 return err;
a935c052 2777 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2778 if (err)
08a01261 2779 return err;
a935c052 2780 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2781 if (err)
08a01261 2782 return err;
a935c052 2783 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2784 if (err)
08a01261 2785 return err;
a935c052 2786 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2787 if (err)
08a01261 2788 return err;
a935c052 2789 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2790 if (err)
08a01261 2791 return err;
54d792f2
AL		 2792
2793 /* Configure the IEEE 802.1p priority mapping register. */
a935c052 2794 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2795 if (err)
08a01261 2796 return err;
54d792f2 2797
de227387
AL		 2798 /* Initialize the statistics unit */
2799 err = mv88e6xxx_stats_set_histogram(chip);
2800 if (err)
2801 return err;
2802
9729934c 2803 /* Clear the statistics counters for all ports */
a935c052
VD		 2804 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2805 GLOBAL_STATS_OP_FLUSH_ALL);
9729934c
VD		 2806 if (err)
2807 return err;
2808
2809 /* Wait for the flush to complete. */
7f9ef3af 2810 err = mv88e6xxx_g1_stats_wait(chip);
9729934c
VD		 2811 if (err)
2812 return err;
2813
2814 return 0;
2815}
2816
f81ec90f 2817static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2818{
04bed143 2819 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2820 int err;
a1a6a4d1
VD		 2821 int i;
2822
fad09c73
VD		 2823 chip->ds = ds;
2824 ds->slave_mii_bus = chip->mdio_bus;
08a01261 2825
fad09c73 2826 mutex_lock(&chip->reg_lock);
08a01261 2827
9729934c 2828 /* Setup Switch Port Registers */
370b4ffb 2829 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
9729934c
VD		 2830 err = mv88e6xxx_setup_port(chip, i);
2831 if (err)
2832 goto unlock;
2833 }
2834
2835 /* Setup Switch Global 1 Registers */
2836 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2837 if (err)
2838 goto unlock;
2839
9729934c
VD		 2840 /* Setup Switch Global 2 Registers */
2841 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2842 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2843 if (err)
2844 goto unlock;
2845 }
08a01261 2846
6e55f698
AL		 2847 /* Some generations have the configuration of sending reserved
2848 * management frames to the CPU in global2, others in
2849 * global1. Hence it does not fit the two setup functions
2850 * above.
2851 */
2852 if (chip->info->ops->mgmt_rsvd2cpu) {
2853 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2854 if (err)
2855 goto unlock;
2856 }
2857
6b17e864 2858unlock:
fad09c73 2859 mutex_unlock(&chip->reg_lock);
db687a56 2860
48ace4ef 2861 return err;
54d792f2
AL		 2862}
2863
3b4caa1b
VD		 2864static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2865{
04bed143 2866 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2867 int err;
2868
b073d4e2
VD		 2869 if (!chip->info->ops->set_switch_mac)
2870 return -EOPNOTSUPP;
3b4caa1b 2871
b073d4e2
VD		 2872 mutex_lock(&chip->reg_lock);
2873 err = chip->info->ops->set_switch_mac(chip, addr);
3b4caa1b
VD		 2874 mutex_unlock(&chip->reg_lock);
2875
2876 return err;
2877}
2878
e57e5e77 2879static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2880{
fad09c73 2881 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77
VD		 2882 u16 val;
2883 int err;
fd3a0ee4 2884
370b4ffb 2885 if (phy >= mv88e6xxx_num_ports(chip))
158bc065 2886 return 0xffff;
fd3a0ee4 2887
fad09c73 2888 mutex_lock(&chip->reg_lock);
e57e5e77 2889 err = mv88e6xxx_phy_read(chip, phy, reg, &val);
fad09c73 2890 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2891
2892 return err ? err : val;
fd3a0ee4
AL		 2893}
2894
e57e5e77 2895static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2896{
fad09c73 2897 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77 2898 int err;
fd3a0ee4 2899
370b4ffb 2900 if (phy >= mv88e6xxx_num_ports(chip))
158bc065 2901 return 0xffff;
fd3a0ee4 2902
fad09c73 2903 mutex_lock(&chip->reg_lock);
e57e5e77 2904 err = mv88e6xxx_phy_write(chip, phy, reg, val);
fad09c73 2905 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2906
2907 return err;
fd3a0ee4
AL		 2908}
2909
fad09c73 2910static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
b516d453
AL		 2911 struct device_node *np)
2912{
2913 static int index;
2914 struct mii_bus *bus;
2915 int err;
2916
b516d453 2917 if (np)
fad09c73 2918 chip->mdio_np = of_get_child_by_name(np, "mdio");
b516d453 2919
fad09c73 2920 bus = devm_mdiobus_alloc(chip->dev);
b516d453
AL		 2921 if (!bus)
2922 return -ENOMEM;
2923
fad09c73 2924 bus->priv = (void *)chip;
b516d453
AL		 2925 if (np) {
2926 bus->name = np->full_name;
2927 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2928 } else {
2929 bus->name = "mv88e6xxx SMI";
2930 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2931 }
2932
2933 bus->read = mv88e6xxx_mdio_read;
2934 bus->write = mv88e6xxx_mdio_write;
fad09c73 2935 bus->parent = chip->dev;
b516d453 2936
fad09c73
VD		 2937 if (chip->mdio_np)
2938 err = of_mdiobus_register(bus, chip->mdio_np);
b516d453
AL		 2939 else
2940 err = mdiobus_register(bus);
2941 if (err) {
fad09c73 2942 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
b516d453
AL		 2943 goto out;
2944 }
fad09c73 2945 chip->mdio_bus = bus;
b516d453
AL		 2946
2947 return 0;
2948
2949out:
fad09c73
VD		 2950 if (chip->mdio_np)
2951 of_node_put(chip->mdio_np);
b516d453
AL		 2952
2953 return err;
2954}
2955
fad09c73 2956static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 2957
2958{
fad09c73 2959 struct mii_bus *bus = chip->mdio_bus;
b516d453
AL		 2960
2961 mdiobus_unregister(bus);
2962
fad09c73
VD		 2963 if (chip->mdio_np)
2964 of_node_put(chip->mdio_np);
b516d453
AL		 2965}
2966
c22995c5
GR		 2967#ifdef CONFIG_NET_DSA_HWMON
2968
2969static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2970{
04bed143 2971 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c 2972 u16 val;
c22995c5 2973 int ret;
c22995c5
GR		 2974
2975 *temp = 0;
2976
fad09c73 2977 mutex_lock(&chip->reg_lock);
c22995c5 2978
9c93829c 2979 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
c22995c5
GR		 2980 if (ret < 0)
2981 goto error;
2982
2983 /* Enable temperature sensor */
9c93829c 2984 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
c22995c5
GR		 2985 if (ret < 0)
2986 goto error;
2987
9c93829c 2988 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
c22995c5
GR		 2989 if (ret < 0)
2990 goto error;
2991
2992 /* Wait for temperature to stabilize */
2993 usleep_range(10000, 12000);
2994
9c93829c
VD		 2995 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
2996 if (ret < 0)
c22995c5 2997 goto error;
c22995c5
GR		 2998
2999 /* Disable temperature sensor */
9c93829c 3000 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
c22995c5
GR		 3001 if (ret < 0)
3002 goto error;
3003
3004 *temp = ((val & 0x1f) - 5) * 5;
3005
3006error:
9c93829c 3007 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
fad09c73 3008 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3009 return ret;
3010}
3011
3012static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3013{
04bed143 3014 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3015 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3016 u16 val;
c22995c5
GR		 3017 int ret;
3018
3019 *temp = 0;
3020
9c93829c
VD		 3021 mutex_lock(&chip->reg_lock);
3022 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3023 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3024 if (ret < 0)
3025 return ret;
3026
9c93829c 3027 *temp = (val & 0xff) - 25;
c22995c5
GR		 3028
3029 return 0;
3030}
3031
f81ec90f 3032static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
c22995c5 3033{
04bed143 3034 struct mv88e6xxx_chip *chip = ds->priv;
158bc065 3035
fad09c73 3036 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
6594f615
VD		 3037 return -EOPNOTSUPP;
3038
fad09c73 3039 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
c22995c5
GR		 3040 return mv88e63xx_get_temp(ds, temp);
3041
3042 return mv88e61xx_get_temp(ds, temp);
3043}
3044
f81ec90f 3045static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
c22995c5 3046{
04bed143 3047 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3048 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3049 u16 val;
c22995c5
GR		 3050 int ret;
3051
fad09c73 3052 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3053 return -EOPNOTSUPP;
3054
3055 *temp = 0;
3056
9c93829c
VD		 3057 mutex_lock(&chip->reg_lock);
3058 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3059 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3060 if (ret < 0)
3061 return ret;
3062
9c93829c 3063 *temp = (((val >> 8) & 0x1f) * 5) - 25;
c22995c5
GR		 3064
3065 return 0;
3066}
3067
f81ec90f 3068static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
c22995c5 3069{
04bed143 3070 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3071 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c
VD		 3072 u16 val;
3073 int err;
c22995c5 3074
fad09c73 3075 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3076 return -EOPNOTSUPP;
3077
9c93829c
VD		 3078 mutex_lock(&chip->reg_lock);
3079 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3080 if (err)
3081 goto unlock;
c22995c5 3082 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
9c93829c
VD		 3083 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3084 (val & 0xe0ff) | (temp << 8));
3085unlock:
3086 mutex_unlock(&chip->reg_lock);
3087
3088 return err;
c22995c5
GR		 3089}
3090
f81ec90f 3091static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
c22995c5 3092{
04bed143 3093 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3094 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3095 u16 val;
c22995c5
GR		 3096 int ret;
3097
fad09c73 3098 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3099 return -EOPNOTSUPP;
3100
3101 *alarm = false;
3102
9c93829c
VD		 3103 mutex_lock(&chip->reg_lock);
3104 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3105 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3106 if (ret < 0)
3107 return ret;
3108
9c93829c 3109 *alarm = !!(val & 0x40);
c22995c5
GR		 3110
3111 return 0;
3112}
3113#endif /* CONFIG_NET_DSA_HWMON */
3114
855b1932
VD		 3115static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3116{
04bed143 3117 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3118
3119 return chip->eeprom_len;
3120}
3121
855b1932
VD		 3122static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3123 struct ethtool_eeprom *eeprom, u8 *data)
3124{
04bed143 3125 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3126 int err;
3127
ee4dc2e7
VD		 3128 if (!chip->info->ops->get_eeprom)
3129 return -EOPNOTSUPP;
855b1932 3130
ee4dc2e7
VD		 3131 mutex_lock(&chip->reg_lock);
3132 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 3133 mutex_unlock(&chip->reg_lock);
3134
3135 if (err)
3136 return err;
3137
3138 eeprom->magic = 0xc3ec4951;
3139
3140 return 0;
3141}
3142
855b1932
VD		 3143static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3144 struct ethtool_eeprom *eeprom, u8 *data)
3145{
04bed143 3146 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3147 int err;
3148
ee4dc2e7
VD		 3149 if (!chip->info->ops->set_eeprom)
3150 return -EOPNOTSUPP;
3151
855b1932
VD		 3152 if (eeprom->magic != 0xc3ec4951)
3153 return -EINVAL;
3154
3155 mutex_lock(&chip->reg_lock);
ee4dc2e7 3156 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 3157 mutex_unlock(&chip->reg_lock);
3158
3159 return err;
3160}
3161
b3469dd8 3162static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 3163 /* MV88E6XXX_FAMILY_6097 */
b073d4e2 3164 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3165 .phy_read = mv88e6xxx_phy_ppu_read,
3166 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3167 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3168 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3169 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3170 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3171 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3172 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3173 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 3174 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3175 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3176 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3177 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3178 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3179 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3180 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3181 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3182 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3183 .ppu_enable = mv88e6185_g1_ppu_enable,
3184 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3185 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3186};
3187
3188static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 3189 /* MV88E6XXX_FAMILY_6095 */
b073d4e2 3190 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3191 .phy_read = mv88e6xxx_phy_ppu_read,
3192 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3193 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3194 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3195 .port_set_speed = mv88e6185_port_set_speed,
56995cbc
AL		 3196 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3197 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,
a605a0fe 3198 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3199 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3200 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3201 .stats_get_stats = mv88e6095_stats_get_stats,
6e55f698 3202 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3203 .ppu_enable = mv88e6185_g1_ppu_enable,
3204 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3205 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3206};
3207
7d381a02 3208static const struct mv88e6xxx_ops mv88e6097_ops = {
15da3cc8 3209 /* MV88E6XXX_FAMILY_6097 */
7d381a02
SE		 3210 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3211 .phy_read = mv88e6xxx_g2_smi_phy_read,
3212 .phy_write = mv88e6xxx_g2_smi_phy_write,
3213 .port_set_link = mv88e6xxx_port_set_link,
3214 .port_set_duplex = mv88e6xxx_port_set_duplex,
3215 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3216 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3217 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3218 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3219 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3220 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3221 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
b35d322a 3222 .port_pause_config = mv88e6097_port_pause_config,
7d381a02
SE		 3223 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3224 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3225 .stats_get_strings = mv88e6095_stats_get_strings,
3226 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3227 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3228 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3229 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3230 .reset = mv88e6352_g1_reset,
7d381a02
SE		 3231};
3232
b3469dd8 3233static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 3234 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3235 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3236 .phy_read = mv88e6xxx_read,
3237 .phy_write = mv88e6xxx_write,
08ef7f10 3238 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3239 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3240 .port_set_speed = mv88e6185_port_set_speed,
56995cbc
AL		 3241 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3242 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,
a605a0fe 3243 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3244 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3245 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3246 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3247 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3248 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3249 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3250 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3251};
3252
3253static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 3254 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3255 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3256 .phy_read = mv88e6xxx_phy_ppu_read,
3257 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3258 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3259 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3260 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3261 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3262 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3263 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3264 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3265 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3266 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3267 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3268 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3269 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3270 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3271 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3272 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3273 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3274 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3275 .ppu_enable = mv88e6185_g1_ppu_enable,
3276 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3277 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3278};
3279
3280static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 3281 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3282 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3283 .phy_read = mv88e6xxx_read,
3284 .phy_write = mv88e6xxx_write,
08ef7f10 3285 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3286 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3287 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3288 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3289 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3290 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3291 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3292 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3293 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3294 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3295 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3296 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3297 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3298 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3299 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3300 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3301 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3302 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3303};
3304
3305static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 3306 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3307 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3308 .phy_read = mv88e6xxx_read,
3309 .phy_write = mv88e6xxx_write,
08ef7f10 3310 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3311 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3312 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3313 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3314 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3315 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3316 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3317 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3318 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3319 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3320 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3321};
3322
3323static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 3324 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3325 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3326 .phy_read = mv88e6xxx_g2_smi_phy_read,
3327 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3328 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3329 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3330 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3331 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3332 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3333 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3334 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3335 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3336 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3337 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3338 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3339 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3340 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3341 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3342 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3343 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3344 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3345 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3346 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3347};
3348
3349static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 3350 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3351 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3352 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3353 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3354 .phy_read = mv88e6xxx_g2_smi_phy_read,
3355 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3356 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3357 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3358 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3359 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3360 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3361 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3362 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3363 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3364 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3365 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3366 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3367 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3368 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3369 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3370 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3371 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3372 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3373 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3374 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3375};
3376
3377static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 3378 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3379 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3380 .phy_read = mv88e6xxx_g2_smi_phy_read,
3381 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3382 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3383 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3384 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3385 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3386 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3387 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3388 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3389 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3390 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3391 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3392 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3393 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3394 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3395 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3396 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3397 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3398 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3399 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3400 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3401};
3402
3403static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 3404 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3405 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3406 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3407 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3408 .phy_read = mv88e6xxx_g2_smi_phy_read,
3409 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3410 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3411 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3412 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3413 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3414 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3415 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3416 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3417 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3418 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3419 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3420 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3421 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3422 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3423 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3424 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3425 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3426 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3427 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3428 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3429};
3430
3431static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 3432 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3433 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3434 .phy_read = mv88e6xxx_phy_ppu_read,
3435 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3436 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3437 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3438 .port_set_speed = mv88e6185_port_set_speed,
56995cbc
AL		 3439 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3440 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,
ef70b111 3441 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
a605a0fe 3442 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3443 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3444 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3445 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3446 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3447 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3448 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3449 .ppu_enable = mv88e6185_g1_ppu_enable,
3450 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3451 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3452};
3453
1a3b39ec 3454static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 3455 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3456 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3457 .phy_read = mv88e6xxx_g2_smi_phy_read,
3458 .phy_write = mv88e6xxx_g2_smi_phy_write,
3459 .port_set_link = mv88e6xxx_port_set_link,
3460 .port_set_duplex = mv88e6xxx_port_set_duplex,
3461 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3462 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3463 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3464 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3465 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3466 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3467 .port_pause_config = mv88e6390_port_pause_config,
79523473 3468 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3469 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3470 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3471 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3472 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3473 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3474 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3475 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3476 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3477};
3478
3479static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 3480 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3481 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3482 .phy_read = mv88e6xxx_g2_smi_phy_read,
3483 .phy_write = mv88e6xxx_g2_smi_phy_write,
3484 .port_set_link = mv88e6xxx_port_set_link,
3485 .port_set_duplex = mv88e6xxx_port_set_duplex,
3486 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3487 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3488 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3489 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3490 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3491 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3492 .port_pause_config = mv88e6390_port_pause_config,
79523473 3493 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3494 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3495 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3496 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3497 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3498 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3499 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3500 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3501 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3502};
3503
3504static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 3505 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3506 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3507 .phy_read = mv88e6xxx_g2_smi_phy_read,
3508 .phy_write = mv88e6xxx_g2_smi_phy_write,
3509 .port_set_link = mv88e6xxx_port_set_link,
3510 .port_set_duplex = mv88e6xxx_port_set_duplex,
3511 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3512 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3513 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3514 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3515 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3516 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3517 .port_pause_config = mv88e6390_port_pause_config,
79523473 3518 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3519 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3520 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3521 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3522 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3523 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3524 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3525 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3526 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3527};
3528
b3469dd8 3529static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 3530 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3531 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3532 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3533 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3534 .phy_read = mv88e6xxx_g2_smi_phy_read,
3535 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3536 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3537 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3538 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3539 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3540 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3541 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3542 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3543 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3544 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3545 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3546 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3547 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3548 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3549 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3550 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3551 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3552 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3553 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3554 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3555};
3556
1a3b39ec 3557static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 3558 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3559 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3560 .phy_read = mv88e6xxx_g2_smi_phy_read,
3561 .phy_write = mv88e6xxx_g2_smi_phy_write,
3562 .port_set_link = mv88e6xxx_port_set_link,
3563 .port_set_duplex = mv88e6xxx_port_set_duplex,
3564 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3565 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3566 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3567 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3568 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3569 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3570 .port_pause_config = mv88e6390_port_pause_config,
79523473 3571 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3572 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3573 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3574 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3575 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3576 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3577 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3578 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3579 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3580};
3581
b3469dd8 3582static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 3583 /* MV88E6XXX_FAMILY_6320 */
ee4dc2e7
VD		 3584 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3585 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3586 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3587 .phy_read = mv88e6xxx_g2_smi_phy_read,
3588 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3589 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3590 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3591 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3592 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3593 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3594 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3595 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3596 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3597 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3598 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3599 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3600 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3601 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3602 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3603 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3604 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3605 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3606 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3607};
3608
3609static const struct mv88e6xxx_ops mv88e6321_ops = {
4b325d8c 3610 /* MV88E6XXX_FAMILY_6321 */
ee4dc2e7
VD		 3611 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3612 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3613 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3614 .phy_read = mv88e6xxx_g2_smi_phy_read,
3615 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3616 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3617 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3618 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3619 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3620 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3621 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3622 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3623 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3624 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3625 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3626 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3627 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3628 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3629 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3630 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3631 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
17e708ba 3632 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3633};
3634
3635static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 3636 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3637 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3638 .phy_read = mv88e6xxx_g2_smi_phy_read,
3639 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3640 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3641 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3642 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3643 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3644 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3645 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3646 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3647 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3648 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3649 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3650 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3651 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3652 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3653 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3654 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3655 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3656 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3657 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3658 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3659};
3660
3661static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 3662 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3663 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3664 .phy_read = mv88e6xxx_g2_smi_phy_read,
3665 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3666 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3667 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3668 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3669 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3670 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3671 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3672 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3673 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3674 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3675 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3676 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3677 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3678 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3679 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3680 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3681 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3682 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3683 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3684 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3685};
3686
3687static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 3688 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3689 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3690 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3691 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3692 .phy_read = mv88e6xxx_g2_smi_phy_read,
3693 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3694 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3695 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3696 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3697 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3698 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3699 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3700 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3701 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3702 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3703 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3704 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3705 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3706 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3707 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3708 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3709 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3710 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3711 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3712 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3713};
3714
1a3b39ec 3715static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 3716 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3717 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3718 .phy_read = mv88e6xxx_g2_smi_phy_read,
3719 .phy_write = mv88e6xxx_g2_smi_phy_write,
3720 .port_set_link = mv88e6xxx_port_set_link,
3721 .port_set_duplex = mv88e6xxx_port_set_duplex,
3722 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3723 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3724 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3725 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3726 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3727 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3728 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3729 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3730 .port_pause_config = mv88e6390_port_pause_config,
79523473 3731 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3732 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3733 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3734 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3735 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3736 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3737 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3738 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3739 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3740};
3741
3742static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 3743 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3744 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3745 .phy_read = mv88e6xxx_g2_smi_phy_read,
3746 .phy_write = mv88e6xxx_g2_smi_phy_write,
3747 .port_set_link = mv88e6xxx_port_set_link,
3748 .port_set_duplex = mv88e6xxx_port_set_duplex,
3749 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3750 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3751 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3752 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3753 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3754 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3755 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3756 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3757 .port_pause_config = mv88e6390_port_pause_config,
79523473 3758 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3759 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3760 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3761 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3762 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3763 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3764 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3765 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3766 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3767};
3768
3769static const struct mv88e6xxx_ops mv88e6391_ops = {
4b325d8c 3770 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3771 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3772 .phy_read = mv88e6xxx_g2_smi_phy_read,
3773 .phy_write = mv88e6xxx_g2_smi_phy_write,
3774 .port_set_link = mv88e6xxx_port_set_link,
3775 .port_set_duplex = mv88e6xxx_port_set_duplex,
3776 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3777 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3778 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3779 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3780 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3781 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3782 .port_pause_config = mv88e6390_port_pause_config,
79523473 3783 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3784 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3785 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3786 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3787 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3788 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3789 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3790 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3791 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3792};
3793
56995cbc
AL		 3794static int mv88e6xxx_verify_madatory_ops(struct mv88e6xxx_chip *chip,
3795 const struct mv88e6xxx_ops *ops)
3796{
3797 if (!ops->port_set_frame_mode) {
3798 dev_err(chip->dev, "Missing port_set_frame_mode");
3799 return -EINVAL;
3800 }
3801
3802 if (!ops->port_set_egress_unknowns) {
3803 dev_err(chip->dev, "Missing port_set_egress_mode");
3804 return -EINVAL;
3805 }
3806
3807 return 0;
3808}
3809
f81ec90f
VD		 3810static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3811 [MV88E6085] = {
3812 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3813 .family = MV88E6XXX_FAMILY_6097,
3814 .name = "Marvell 88E6085",
3815 .num_databases = 4096,
3816 .num_ports = 10,
9dddd478 3817 .port_base_addr = 0x10,
a935c052 3818 .global1_addr = 0x1b,
acddbd21 3819 .age_time_coeff = 15000,
dc30c35b 3820 .g1_irqs = 8,
443d5a1b 3821 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3822 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
b3469dd8 3823 .ops = &mv88e6085_ops,
f81ec90f
VD		 3824 },
3825
3826 [MV88E6095] = {
3827 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3828 .family = MV88E6XXX_FAMILY_6095,
3829 .name = "Marvell 88E6095/88E6095F",
3830 .num_databases = 256,
3831 .num_ports = 11,
9dddd478 3832 .port_base_addr = 0x10,
a935c052 3833 .global1_addr = 0x1b,
acddbd21 3834 .age_time_coeff = 15000,
dc30c35b 3835 .g1_irqs = 8,
443d5a1b 3836 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3837 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
b3469dd8 3838 .ops = &mv88e6095_ops,
f81ec90f
VD		 3839 },
3840
7d381a02
SE		 3841 [MV88E6097] = {
3842 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
3843 .family = MV88E6XXX_FAMILY_6097,
3844 .name = "Marvell 88E6097/88E6097F",
3845 .num_databases = 4096,
3846 .num_ports = 11,
3847 .port_base_addr = 0x10,
3848 .global1_addr = 0x1b,
3849 .age_time_coeff = 15000,
c534178b 3850 .g1_irqs = 8,
2bfcfcd3 3851 .tag_protocol = DSA_TAG_PROTO_EDSA,
7d381a02
SE		 3852 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3853 .ops = &mv88e6097_ops,
3854 },
3855
f81ec90f
VD		 3856 [MV88E6123] = {
3857 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3858 .family = MV88E6XXX_FAMILY_6165,
3859 .name = "Marvell 88E6123",
3860 .num_databases = 4096,
3861 .num_ports = 3,
9dddd478 3862 .port_base_addr = 0x10,
a935c052 3863 .global1_addr = 0x1b,
acddbd21 3864 .age_time_coeff = 15000,
dc30c35b 3865 .g1_irqs = 9,
443d5a1b 3866 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3867 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3868 .ops = &mv88e6123_ops,
f81ec90f
VD		 3869 },
3870
3871 [MV88E6131] = {
3872 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3873 .family = MV88E6XXX_FAMILY_6185,
3874 .name = "Marvell 88E6131",
3875 .num_databases = 256,
3876 .num_ports = 8,
9dddd478 3877 .port_base_addr = 0x10,
a935c052 3878 .global1_addr = 0x1b,
acddbd21 3879 .age_time_coeff = 15000,
dc30c35b 3880 .g1_irqs = 9,
443d5a1b 3881 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3882 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3883 .ops = &mv88e6131_ops,
f81ec90f
VD		 3884 },
3885
3886 [MV88E6161] = {
3887 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3888 .family = MV88E6XXX_FAMILY_6165,
3889 .name = "Marvell 88E6161",
3890 .num_databases = 4096,
3891 .num_ports = 6,
9dddd478 3892 .port_base_addr = 0x10,
a935c052 3893 .global1_addr = 0x1b,
acddbd21 3894 .age_time_coeff = 15000,
dc30c35b 3895 .g1_irqs = 9,
443d5a1b 3896 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3897 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3898 .ops = &mv88e6161_ops,
f81ec90f
VD		 3899 },
3900
3901 [MV88E6165] = {
3902 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3903 .family = MV88E6XXX_FAMILY_6165,
3904 .name = "Marvell 88E6165",
3905 .num_databases = 4096,
3906 .num_ports = 6,
9dddd478 3907 .port_base_addr = 0x10,
a935c052 3908 .global1_addr = 0x1b,
acddbd21 3909 .age_time_coeff = 15000,
dc30c35b 3910 .g1_irqs = 9,
443d5a1b 3911 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3912 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3913 .ops = &mv88e6165_ops,
f81ec90f
VD		 3914 },
3915
3916 [MV88E6171] = {
3917 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3918 .family = MV88E6XXX_FAMILY_6351,
3919 .name = "Marvell 88E6171",
3920 .num_databases = 4096,
3921 .num_ports = 7,
9dddd478 3922 .port_base_addr = 0x10,
a935c052 3923 .global1_addr = 0x1b,
acddbd21 3924 .age_time_coeff = 15000,
dc30c35b 3925 .g1_irqs = 9,
443d5a1b 3926 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3927 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3928 .ops = &mv88e6171_ops,
f81ec90f
VD		 3929 },
3930
3931 [MV88E6172] = {
3932 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3933 .family = MV88E6XXX_FAMILY_6352,
3934 .name = "Marvell 88E6172",
3935 .num_databases = 4096,
3936 .num_ports = 7,
9dddd478 3937 .port_base_addr = 0x10,
a935c052 3938 .global1_addr = 0x1b,
acddbd21 3939 .age_time_coeff = 15000,
dc30c35b 3940 .g1_irqs = 9,
443d5a1b 3941 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3942 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3943 .ops = &mv88e6172_ops,
f81ec90f
VD		 3944 },
3945
3946 [MV88E6175] = {
3947 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3948 .family = MV88E6XXX_FAMILY_6351,
3949 .name = "Marvell 88E6175",
3950 .num_databases = 4096,
3951 .num_ports = 7,
9dddd478 3952 .port_base_addr = 0x10,
a935c052 3953 .global1_addr = 0x1b,
acddbd21 3954 .age_time_coeff = 15000,
dc30c35b 3955 .g1_irqs = 9,
443d5a1b 3956 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3957 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3958 .ops = &mv88e6175_ops,
f81ec90f
VD		 3959 },
3960
3961 [MV88E6176] = {
3962 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3963 .family = MV88E6XXX_FAMILY_6352,
3964 .name = "Marvell 88E6176",
3965 .num_databases = 4096,
3966 .num_ports = 7,
9dddd478 3967 .port_base_addr = 0x10,
a935c052 3968 .global1_addr = 0x1b,
acddbd21 3969 .age_time_coeff = 15000,
dc30c35b 3970 .g1_irqs = 9,
443d5a1b 3971 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3972 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3973 .ops = &mv88e6176_ops,
f81ec90f
VD		 3974 },
3975
3976 [MV88E6185] = {
3977 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3978 .family = MV88E6XXX_FAMILY_6185,
3979 .name = "Marvell 88E6185",
3980 .num_databases = 256,
3981 .num_ports = 10,
9dddd478 3982 .port_base_addr = 0x10,
a935c052 3983 .global1_addr = 0x1b,
acddbd21 3984 .age_time_coeff = 15000,
dc30c35b 3985 .g1_irqs = 8,
443d5a1b 3986 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3987 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3988 .ops = &mv88e6185_ops,
f81ec90f
VD		 3989 },
3990
1a3b39ec
AL		 3991 [MV88E6190] = {
3992 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
3993 .family = MV88E6XXX_FAMILY_6390,
3994 .name = "Marvell 88E6190",
3995 .num_databases = 4096,
3996 .num_ports = 11, /* 10 + Z80 */
3997 .port_base_addr = 0x0,
3998 .global1_addr = 0x1b,
443d5a1b 3999 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4000 .age_time_coeff = 15000,
4001 .g1_irqs = 9,
4002 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4003 .ops = &mv88e6190_ops,
4004 },
4005
4006 [MV88E6190X] = {
4007 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
4008 .family = MV88E6XXX_FAMILY_6390,
4009 .name = "Marvell 88E6190X",
4010 .num_databases = 4096,
4011 .num_ports = 11, /* 10 + Z80 */
4012 .port_base_addr = 0x0,
4013 .global1_addr = 0x1b,
4014 .age_time_coeff = 15000,
4015 .g1_irqs = 9,
443d5a1b 4016 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4017 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4018 .ops = &mv88e6190x_ops,
4019 },
4020
4021 [MV88E6191] = {
4022 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
4023 .family = MV88E6XXX_FAMILY_6390,
4024 .name = "Marvell 88E6191",
4025 .num_databases = 4096,
4026 .num_ports = 11, /* 10 + Z80 */
4027 .port_base_addr = 0x0,
4028 .global1_addr = 0x1b,
4029 .age_time_coeff = 15000,
443d5a1b
AL		 4030 .g1_irqs = 9,
4031 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4032 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4033 .ops = &mv88e6391_ops,
4034 },
4035
f81ec90f
VD		 4036 [MV88E6240] = {
4037 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
4038 .family = MV88E6XXX_FAMILY_6352,
4039 .name = "Marvell 88E6240",
4040 .num_databases = 4096,
4041 .num_ports = 7,
9dddd478 4042 .port_base_addr = 0x10,
a935c052 4043 .global1_addr = 0x1b,
acddbd21 4044 .age_time_coeff = 15000,
dc30c35b 4045 .g1_irqs = 9,
443d5a1b 4046 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4047 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 4048 .ops = &mv88e6240_ops,
f81ec90f
VD		 4049 },
4050
1a3b39ec
AL		 4051 [MV88E6290] = {
4052 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
4053 .family = MV88E6XXX_FAMILY_6390,
4054 .name = "Marvell 88E6290",
4055 .num_databases = 4096,
4056 .num_ports = 11, /* 10 + Z80 */
4057 .port_base_addr = 0x0,
4058 .global1_addr = 0x1b,
4059 .age_time_coeff = 15000,
4060 .g1_irqs = 9,
443d5a1b 4061 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4062 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4063 .ops = &mv88e6290_ops,
4064 },
4065
f81ec90f
VD		 4066 [MV88E6320] = {
4067 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
4068 .family = MV88E6XXX_FAMILY_6320,
4069 .name = "Marvell 88E6320",
4070 .num_databases = 4096,
4071 .num_ports = 7,
9dddd478 4072 .port_base_addr = 0x10,
a935c052 4073 .global1_addr = 0x1b,
acddbd21 4074 .age_time_coeff = 15000,
dc30c35b 4075 .g1_irqs = 8,
443d5a1b 4076 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4077 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 4078 .ops = &mv88e6320_ops,
f81ec90f
VD		 4079 },
4080
4081 [MV88E6321] = {
4082 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
4083 .family = MV88E6XXX_FAMILY_6320,
4084 .name = "Marvell 88E6321",
4085 .num_databases = 4096,
4086 .num_ports = 7,
9dddd478 4087 .port_base_addr = 0x10,
a935c052 4088 .global1_addr = 0x1b,
acddbd21 4089 .age_time_coeff = 15000,
dc30c35b 4090 .g1_irqs = 8,
443d5a1b 4091 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4092 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 4093 .ops = &mv88e6321_ops,
f81ec90f
VD		 4094 },
4095
4096 [MV88E6350] = {
4097 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
4098 .family = MV88E6XXX_FAMILY_6351,
4099 .name = "Marvell 88E6350",
4100 .num_databases = 4096,
4101 .num_ports = 7,
9dddd478 4102 .port_base_addr = 0x10,
a935c052 4103 .global1_addr = 0x1b,
acddbd21 4104 .age_time_coeff = 15000,
dc30c35b 4105 .g1_irqs = 9,
443d5a1b 4106 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4107 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 4108 .ops = &mv88e6350_ops,
f81ec90f
VD		 4109 },
4110
4111 [MV88E6351] = {
4112 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
4113 .family = MV88E6XXX_FAMILY_6351,
4114 .name = "Marvell 88E6351",
4115 .num_databases = 4096,
4116 .num_ports = 7,
9dddd478 4117 .port_base_addr = 0x10,
a935c052 4118 .global1_addr = 0x1b,
acddbd21 4119 .age_time_coeff = 15000,
dc30c35b 4120 .g1_irqs = 9,
443d5a1b 4121 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4122 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 4123 .ops = &mv88e6351_ops,
f81ec90f
VD		 4124 },
4125
4126 [MV88E6352] = {
4127 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
4128 .family = MV88E6XXX_FAMILY_6352,
4129 .name = "Marvell 88E6352",
4130 .num_databases = 4096,
4131 .num_ports = 7,
9dddd478 4132 .port_base_addr = 0x10,
a935c052 4133 .global1_addr = 0x1b,
acddbd21 4134 .age_time_coeff = 15000,
dc30c35b 4135 .g1_irqs = 9,
443d5a1b 4136 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4137 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 4138 .ops = &mv88e6352_ops,
f81ec90f 4139 },
1a3b39ec
AL		 4140 [MV88E6390] = {
4141 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
4142 .family = MV88E6XXX_FAMILY_6390,
4143 .name = "Marvell 88E6390",
4144 .num_databases = 4096,
4145 .num_ports = 11, /* 10 + Z80 */
4146 .port_base_addr = 0x0,
4147 .global1_addr = 0x1b,
4148 .age_time_coeff = 15000,
4149 .g1_irqs = 9,
443d5a1b 4150 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4151 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4152 .ops = &mv88e6390_ops,
4153 },
4154 [MV88E6390X] = {
4155 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
4156 .family = MV88E6XXX_FAMILY_6390,
4157 .name = "Marvell 88E6390X",
4158 .num_databases = 4096,
4159 .num_ports = 11, /* 10 + Z80 */
4160 .port_base_addr = 0x0,
4161 .global1_addr = 0x1b,
4162 .age_time_coeff = 15000,
4163 .g1_irqs = 9,
443d5a1b 4164 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4165 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4166 .ops = &mv88e6390x_ops,
4167 },
f81ec90f
VD		 4168};
4169
5f7c0367 4170static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 4171{
a439c061 4172 int i;
b9b37713 4173
5f7c0367
VD		 4174 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4175 if (mv88e6xxx_table[i].prod_num == prod_num)
4176 return &mv88e6xxx_table[i];
b9b37713 4177
b9b37713
VD		 4178 return NULL;
4179}
4180
fad09c73 4181static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 4182{
4183 const struct mv88e6xxx_info *info;
8f6345b2
VD		 4184 unsigned int prod_num, rev;
4185 u16 id;
4186 int err;
bc46a3d5 4187
8f6345b2
VD		 4188 mutex_lock(&chip->reg_lock);
4189 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
4190 mutex_unlock(&chip->reg_lock);
4191 if (err)
4192 return err;
bc46a3d5
VD		 4193
4194 prod_num = (id & 0xfff0) >> 4;
4195 rev = id & 0x000f;
4196
4197 info = mv88e6xxx_lookup_info(prod_num);
4198 if (!info)
4199 return -ENODEV;
4200
caac8545 4201 /* Update the compatible info with the probed one */
fad09c73 4202 chip->info = info;
bc46a3d5 4203
ca070c10
VD		 4204 err = mv88e6xxx_g2_require(chip);
4205 if (err)
4206 return err;
4207
fad09c73
VD		 4208 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4209 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 4210
4211 return 0;
4212}
4213
fad09c73 4214static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 4215{
fad09c73 4216 struct mv88e6xxx_chip *chip;
469d729f 4217
fad09c73
VD		 4218 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4219 if (!chip)
469d729f
VD		 4220 return NULL;
4221
fad09c73 4222 chip->dev = dev;
469d729f 4223
fad09c73 4224 mutex_init(&chip->reg_lock);
469d729f 4225
fad09c73 4226 return chip;
469d729f
VD		 4227}
4228
e57e5e77
VD		 4229static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
4230{
a199d8b6 4231 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
e57e5e77 4232 mv88e6xxx_ppu_state_init(chip);
e57e5e77
VD		 4233}
4234
930188ce
AL		 4235static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
4236{
a199d8b6 4237 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
930188ce 4238 mv88e6xxx_ppu_state_destroy(chip);
930188ce
AL		 4239}
4240
fad09c73 4241static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 4242 struct mii_bus *bus, int sw_addr)
4243{
914b32f6 4244 if (sw_addr == 0)
fad09c73 4245 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 4246 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 4247 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 4248 else
4249 return -EINVAL;
4250
fad09c73
VD		 4251 chip->bus = bus;
4252 chip->sw_addr = sw_addr;
4a70c4ab
VD		 4253
4254 return 0;
4255}
4256
7b314362
AL		 4257static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
4258{
04bed143 4259 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be 4260
443d5a1b 4261 return chip->info->tag_protocol;
7b314362
AL		 4262}
4263
fcdce7d0
AL		 4264static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4265 struct device *host_dev, int sw_addr,
4266 void **priv)
a77d43f1 4267{
fad09c73 4268 struct mv88e6xxx_chip *chip;
a439c061 4269 struct mii_bus *bus;
b516d453 4270 int err;
a77d43f1 4271
a439c061 4272 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 4273 if (!bus)
4274 return NULL;
4275
fad09c73
VD		 4276 chip = mv88e6xxx_alloc_chip(dsa_dev);
4277 if (!chip)
469d729f
VD		 4278 return NULL;
4279
caac8545 4280 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 4281 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 4282
fad09c73 4283 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 4284 if (err)
4285 goto free;
4286
fad09c73 4287 err = mv88e6xxx_detect(chip);
bc46a3d5 4288 if (err)
469d729f 4289 goto free;
a439c061 4290
dc30c35b
AL		 4291 mutex_lock(&chip->reg_lock);
4292 err = mv88e6xxx_switch_reset(chip);
4293 mutex_unlock(&chip->reg_lock);
4294 if (err)
4295 goto free;
4296
e57e5e77
VD		 4297 mv88e6xxx_phy_init(chip);
4298
fad09c73 4299 err = mv88e6xxx_mdio_register(chip, NULL);
b516d453 4300 if (err)
469d729f 4301 goto free;
b516d453 4302
fad09c73 4303 *priv = chip;
a439c061 4304
fad09c73 4305 return chip->info->name;
469d729f 4306free:
fad09c73 4307 devm_kfree(dsa_dev, chip);
469d729f
VD		 4308
4309 return NULL;
a77d43f1
AL		 4310}
4311
7df8fbdd
VD		 4312static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4313 const struct switchdev_obj_port_mdb *mdb,
4314 struct switchdev_trans *trans)
4315{
4316 /* We don't need any dynamic resource from the kernel (yet),
4317 * so skip the prepare phase.
4318 */
4319
4320 return 0;
4321}
4322
4323static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4324 const struct switchdev_obj_port_mdb *mdb,
4325 struct switchdev_trans *trans)
4326{
04bed143 4327 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4328
4329 mutex_lock(&chip->reg_lock);
4330 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4331 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4332 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4333 mutex_unlock(&chip->reg_lock);
4334}
4335
4336static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4337 const struct switchdev_obj_port_mdb *mdb)
4338{
04bed143 4339 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4340 int err;
4341
4342 mutex_lock(&chip->reg_lock);
4343 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4344 GLOBAL_ATU_DATA_STATE_UNUSED);
4345 mutex_unlock(&chip->reg_lock);
4346
4347 return err;
4348}
4349
4350static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4351 struct switchdev_obj_port_mdb *mdb,
4352 int (*cb)(struct switchdev_obj *obj))
4353{
04bed143 4354 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4355 int err;
4356
4357 mutex_lock(&chip->reg_lock);
4358 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4359 mutex_unlock(&chip->reg_lock);
4360
4361 return err;
4362}
4363
9d490b4e 4364static struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 4365 .probe = mv88e6xxx_drv_probe,
7b314362 4366 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 4367 .setup = mv88e6xxx_setup,
4368 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 4369 .adjust_link = mv88e6xxx_adjust_link,
4370 .get_strings = mv88e6xxx_get_strings,
4371 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4372 .get_sset_count = mv88e6xxx_get_sset_count,
4373 .set_eee = mv88e6xxx_set_eee,
4374 .get_eee = mv88e6xxx_get_eee,
4375#ifdef CONFIG_NET_DSA_HWMON
4376 .get_temp = mv88e6xxx_get_temp,
4377 .get_temp_limit = mv88e6xxx_get_temp_limit,
4378 .set_temp_limit = mv88e6xxx_set_temp_limit,
4379 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
4380#endif
f8cd8753 4381 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 4382 .get_eeprom = mv88e6xxx_get_eeprom,
4383 .set_eeprom = mv88e6xxx_set_eeprom,
4384 .get_regs_len = mv88e6xxx_get_regs_len,
4385 .get_regs = mv88e6xxx_get_regs,
2cfcd964 4386 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 4387 .port_bridge_join = mv88e6xxx_port_bridge_join,
4388 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4389 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 4390 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 4391 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4392 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4393 .port_vlan_add = mv88e6xxx_port_vlan_add,
4394 .port_vlan_del = mv88e6xxx_port_vlan_del,
4395 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4396 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4397 .port_fdb_add = mv88e6xxx_port_fdb_add,
4398 .port_fdb_del = mv88e6xxx_port_fdb_del,
4399 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 4400 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4401 .port_mdb_add = mv88e6xxx_port_mdb_add,
4402 .port_mdb_del = mv88e6xxx_port_mdb_del,
4403 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
f81ec90f
VD		 4404};
4405
fad09c73 4406static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
b7e66a5f
VD		 4407 struct device_node *np)
4408{
fad09c73 4409 struct device *dev = chip->dev;
b7e66a5f
VD		 4410 struct dsa_switch *ds;
4411
4412 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4413 if (!ds)
4414 return -ENOMEM;
4415
4416 ds->dev = dev;
fad09c73 4417 ds->priv = chip;
9d490b4e 4418 ds->ops = &mv88e6xxx_switch_ops;
b7e66a5f
VD		 4419
4420 dev_set_drvdata(dev, ds);
4421
4422 return dsa_register_switch(ds, np);
4423}
4424
fad09c73 4425static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4426{
fad09c73 4427 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 4428}
4429
57d32310 4430static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 4431{
14c7b3c3 4432 struct device *dev = &mdiodev->dev;
f8cd8753 4433 struct device_node *np = dev->of_node;
caac8545 4434 const struct mv88e6xxx_info *compat_info;
fad09c73 4435 struct mv88e6xxx_chip *chip;
f8cd8753 4436 u32 eeprom_len;
52638f71 4437 int err;
14c7b3c3 4438
caac8545
VD		 4439 compat_info = of_device_get_match_data(dev);
4440 if (!compat_info)
4441 return -EINVAL;
4442
fad09c73
VD		 4443 chip = mv88e6xxx_alloc_chip(dev);
4444 if (!chip)
14c7b3c3
AL		 4445 return -ENOMEM;
4446
fad09c73 4447 chip->info = compat_info;
caac8545 4448
56995cbc
AL		 4449 err = mv88e6xxx_verify_madatory_ops(chip, chip->info->ops);
4450 if (err)
4451 return err;
4452
fad09c73 4453 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4454 if (err)
4455 return err;
14c7b3c3 4456
b4308f04
AL		 4457 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4458 if (IS_ERR(chip->reset))
4459 return PTR_ERR(chip->reset);
4460
fad09c73 4461 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4462 if (err)
4463 return err;
14c7b3c3 4464
e57e5e77
VD		 4465 mv88e6xxx_phy_init(chip);
4466
ee4dc2e7 4467 if (chip->info->ops->get_eeprom &&
f8cd8753 4468 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4469 chip->eeprom_len = eeprom_len;
f8cd8753 4470
dc30c35b
AL		 4471 mutex_lock(&chip->reg_lock);
4472 err = mv88e6xxx_switch_reset(chip);
4473 mutex_unlock(&chip->reg_lock);
4474 if (err)
4475 goto out;
4476
4477 chip->irq = of_irq_get(np, 0);
4478 if (chip->irq == -EPROBE_DEFER) {
4479 err = chip->irq;
4480 goto out;
4481 }
4482
4483 if (chip->irq > 0) {
4484 /* Has to be performed before the MDIO bus is created,
4485 * because the PHYs will link there interrupts to these
4486 * interrupt controllers
4487 */
4488 mutex_lock(&chip->reg_lock);
4489 err = mv88e6xxx_g1_irq_setup(chip);
4490 mutex_unlock(&chip->reg_lock);
4491
4492 if (err)
4493 goto out;
4494
4495 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4496 err = mv88e6xxx_g2_irq_setup(chip);
4497 if (err)
4498 goto out_g1_irq;
4499 }
4500 }
4501
fad09c73 4502 err = mv88e6xxx_mdio_register(chip, np);
b516d453 4503 if (err)
dc30c35b 4504 goto out_g2_irq;
b516d453 4505
fad09c73 4506 err = mv88e6xxx_register_switch(chip, np);
dc30c35b
AL		 4507 if (err)
4508 goto out_mdio;
83c0afae 4509
98e67308 4510 return 0;
dc30c35b
AL		 4511
4512out_mdio:
4513 mv88e6xxx_mdio_unregister(chip);
4514out_g2_irq:
46712644 4515 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
dc30c35b
AL		 4516 mv88e6xxx_g2_irq_free(chip);
4517out_g1_irq:
61f7c3f8
AL		 4518 if (chip->irq > 0) {
4519 mutex_lock(&chip->reg_lock);
46712644 4520 mv88e6xxx_g1_irq_free(chip);
61f7c3f8
AL		 4521 mutex_unlock(&chip->reg_lock);
4522 }
dc30c35b
AL		 4523out:
4524 return err;
98e67308 4525}
14c7b3c3
AL		 4526
4527static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4528{
4529 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 4530 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 4531
930188ce 4532 mv88e6xxx_phy_destroy(chip);
fad09c73
VD		 4533 mv88e6xxx_unregister_switch(chip);
4534 mv88e6xxx_mdio_unregister(chip);
dc30c35b 4535
46712644
AL		 4536 if (chip->irq > 0) {
4537 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4538 mv88e6xxx_g2_irq_free(chip);
4539 mv88e6xxx_g1_irq_free(chip);
4540 }
14c7b3c3
AL		 4541}
4542
4543static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4544 {
4545 .compatible = "marvell,mv88e6085",
4546 .data = &mv88e6xxx_table[MV88E6085],
4547 },
1a3b39ec
AL		 4548 {
4549 .compatible = "marvell,mv88e6190",
4550 .data = &mv88e6xxx_table[MV88E6190],
4551 },
14c7b3c3
AL		 4552 { /* sentinel */ },
4553};
4554
4555MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4556
4557static struct mdio_driver mv88e6xxx_driver = {
4558 .probe = mv88e6xxx_probe,
4559 .remove = mv88e6xxx_remove,
4560 .mdiodrv.driver = {
4561 .name = "mv88e6085",
4562 .of_match_table = mv88e6xxx_of_match,
4563 },
4564};
4565
4566static int __init mv88e6xxx_init(void)
4567{
9d490b4e 4568 register_switch_driver(&mv88e6xxx_switch_ops);
14c7b3c3
AL		 4569 return mdio_driver_register(&mv88e6xxx_driver);
4570}
98e67308
BH		 4571module_init(mv88e6xxx_init);
4572
4573static void __exit mv88e6xxx_cleanup(void)
4574{
14c7b3c3 4575 mdio_driver_unregister(&mv88e6xxx_driver);
9d490b4e 4576 unregister_switch_driver(&mv88e6xxx_switch_ops);
98e67308
BH		 4577}
4578module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4579
4580MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4581MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4582MODULE_LICENSE("GPL");
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