]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/net/dsa/mv88e6xxx/chip.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: dsa: mv88e6xxx: add port PVID accessors
[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
1f36faf2 35#include <net/switchdev.h>
ec561276 36
91da11f8 37#include "mv88e6xxx.h"
a935c052 38#include "global1.h"
ec561276 39#include "global2.h"
18abed21 40#include "port.h"
91da11f8 41
fad09c73 42static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 43{
fad09c73
VD		 44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 46 dump_stack();
47 }
48}
49
914b32f6
VD		 50/* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
52 *
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
56 *
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 60 */
914b32f6 61
fad09c73 62static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 63 int addr, int reg, u16 *val)
64{
fad09c73 65 if (!chip->smi_ops)
914b32f6
VD		 66 return -EOPNOTSUPP;
67
fad09c73 68 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 69}
70
fad09c73 71static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 72 int addr, int reg, u16 val)
73{
fad09c73 74 if (!chip->smi_ops)
914b32f6
VD		 75 return -EOPNOTSUPP;
76
fad09c73 77 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 78}
79
fad09c73 80static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 81 int addr, int reg, u16 *val)
82{
83 int ret;
84
fad09c73 85 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 86 if (ret < 0)
87 return ret;
88
89 *val = ret & 0xffff;
90
91 return 0;
92}
93
fad09c73 94static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 95 int addr, int reg, u16 val)
96{
97 int ret;
98
fad09c73 99 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 100 if (ret < 0)
101 return ret;
102
103 return 0;
104}
105
c08026ab 106static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
109};
110
fad09c73 111static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 112{
113 int ret;
114 int i;
115
116 for (i = 0; i < 16; i++) {
fad09c73 117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 118 if (ret < 0)
119 return ret;
120
cca8b133 121 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 122 return 0;
123 }
124
125 return -ETIMEDOUT;
126}
127
fad09c73 128static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 129 int addr, int reg, u16 *val)
91da11f8
LB		 130{
131 int ret;
132
3675c8d7 133 /* Wait for the bus to become free. */
fad09c73 134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 135 if (ret < 0)
136 return ret;
137
3675c8d7 138 /* Transmit the read command. */
fad09c73 139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 141 if (ret < 0)
142 return ret;
143
3675c8d7 144 /* Wait for the read command to complete. */
fad09c73 145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 146 if (ret < 0)
147 return ret;
148
3675c8d7 149 /* Read the data. */
fad09c73 150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 151 if (ret < 0)
152 return ret;
153
914b32f6 154 *val = ret & 0xffff;
91da11f8 155
914b32f6 156 return 0;
8d6d09e7
GR		 157}
158
fad09c73 159static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 160 int addr, int reg, u16 val)
91da11f8
LB		 161{
162 int ret;
163
3675c8d7 164 /* Wait for the bus to become free. */
fad09c73 165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 166 if (ret < 0)
167 return ret;
168
3675c8d7 169 /* Transmit the data to write. */
fad09c73 170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 171 if (ret < 0)
172 return ret;
173
3675c8d7 174 /* Transmit the write command. */
fad09c73 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 177 if (ret < 0)
178 return ret;
179
3675c8d7 180 /* Wait for the write command to complete. */
fad09c73 181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 182 if (ret < 0)
183 return ret;
184
185 return 0;
186}
187
c08026ab 188static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
191};
192
ec561276 193int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 194{
195 int err;
196
fad09c73 197 assert_reg_lock(chip);
914b32f6 198
fad09c73 199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 200 if (err)
201 return err;
202
fad09c73 203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 204 addr, reg, *val);
205
206 return 0;
207}
208
ec561276 209int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 210{
914b32f6
VD		 211 int err;
212
fad09c73 213 assert_reg_lock(chip);
91da11f8 214
fad09c73 215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 216 if (err)
217 return err;
218
fad09c73 219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 220 addr, reg, val);
221
914b32f6
VD		 222 return 0;
223}
224
e57e5e77
VD		 225static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
226 int reg, u16 *val)
227{
228 int addr = phy; /* PHY devices addresses start at 0x0 */
229
b3469dd8 230 if (!chip->info->ops->phy_read)
e57e5e77
VD		 231 return -EOPNOTSUPP;
232
b3469dd8 233 return chip->info->ops->phy_read(chip, addr, reg, val);
e57e5e77
VD		 234}
235
236static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
237 int reg, u16 val)
238{
239 int addr = phy; /* PHY devices addresses start at 0x0 */
240
b3469dd8 241 if (!chip->info->ops->phy_write)
e57e5e77
VD		 242 return -EOPNOTSUPP;
243
b3469dd8 244 return chip->info->ops->phy_write(chip, addr, reg, val);
e57e5e77
VD		 245}
246
09cb7dfd
VD		 247static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
248{
249 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
250 return -EOPNOTSUPP;
251
252 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
253}
254
255static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
256{
257 int err;
258
259 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
260 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
261 if (unlikely(err)) {
262 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
263 phy, err);
264 }
265}
266
267static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
268 u8 page, int reg, u16 *val)
269{
270 int err;
271
272 /* There is no paging for registers 22 */
273 if (reg == PHY_PAGE)
274 return -EINVAL;
275
276 err = mv88e6xxx_phy_page_get(chip, phy, page);
277 if (!err) {
278 err = mv88e6xxx_phy_read(chip, phy, reg, val);
279 mv88e6xxx_phy_page_put(chip, phy);
280 }
281
282 return err;
283}
284
285static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
286 u8 page, int reg, u16 val)
287{
288 int err;
289
290 /* There is no paging for registers 22 */
291 if (reg == PHY_PAGE)
292 return -EINVAL;
293
294 err = mv88e6xxx_phy_page_get(chip, phy, page);
295 if (!err) {
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
297 mv88e6xxx_phy_page_put(chip, phy);
298 }
299
300 return err;
301}
302
303static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
304{
305 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
306 reg, val);
307}
308
309static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
310{
311 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
312 reg, val);
313}
314
dc30c35b
AL		 315static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
316{
317 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
318 unsigned int n = d->hwirq;
319
320 chip->g1_irq.masked |= (1 << n);
321}
322
323static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
324{
325 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
326 unsigned int n = d->hwirq;
327
328 chip->g1_irq.masked &= ~(1 << n);
329}
330
331static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
332{
333 struct mv88e6xxx_chip *chip = dev_id;
334 unsigned int nhandled = 0;
335 unsigned int sub_irq;
336 unsigned int n;
337 u16 reg;
338 int err;
339
340 mutex_lock(&chip->reg_lock);
341 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
342 mutex_unlock(&chip->reg_lock);
343
344 if (err)
345 goto out;
346
347 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
348 if (reg & (1 << n)) {
349 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
350 handle_nested_irq(sub_irq);
351 ++nhandled;
352 }
353 }
354out:
355 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
356}
357
358static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
359{
360 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
361
362 mutex_lock(&chip->reg_lock);
363}
364
365static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
366{
367 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
368 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
369 u16 reg;
370 int err;
371
372 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
373 if (err)
374 goto out;
375
376 reg &= ~mask;
377 reg |= (~chip->g1_irq.masked & mask);
378
379 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
380 if (err)
381 goto out;
382
383out:
384 mutex_unlock(&chip->reg_lock);
385}
386
387static struct irq_chip mv88e6xxx_g1_irq_chip = {
388 .name = "mv88e6xxx-g1",
389 .irq_mask = mv88e6xxx_g1_irq_mask,
390 .irq_unmask = mv88e6xxx_g1_irq_unmask,
391 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
392 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
393};
394
395static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
396 unsigned int irq,
397 irq_hw_number_t hwirq)
398{
399 struct mv88e6xxx_chip *chip = d->host_data;
400
401 irq_set_chip_data(irq, d->host_data);
402 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
403 irq_set_noprobe(irq);
404
405 return 0;
406}
407
408static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
409 .map = mv88e6xxx_g1_irq_domain_map,
410 .xlate = irq_domain_xlate_twocell,
411};
412
413static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
414{
415 int irq, virq;
416
417 for (irq = 0; irq < 16; irq++) {
418 virq = irq_find_mapping(chip->g2_irq.domain, irq);
419 irq_dispose_mapping(virq);
420 }
421
422 irq_domain_remove(chip->g2_irq.domain);
423}
424
425static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
426{
427 int err, irq;
428 u16 reg;
429
430 chip->g1_irq.nirqs = chip->info->g1_irqs;
431 chip->g1_irq.domain = irq_domain_add_simple(
432 NULL, chip->g1_irq.nirqs, 0,
433 &mv88e6xxx_g1_irq_domain_ops, chip);
434 if (!chip->g1_irq.domain)
435 return -ENOMEM;
436
437 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
438 irq_create_mapping(chip->g1_irq.domain, irq);
439
440 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
441 chip->g1_irq.masked = ~0;
442
443 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
444 if (err)
445 goto out;
446
447 reg &= ~GENMASK(chip->g1_irq.nirqs, 0);
448
449 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
450 if (err)
451 goto out;
452
453 /* Reading the interrupt status clears (most of) them */
454 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
455 if (err)
456 goto out;
457
458 err = request_threaded_irq(chip->irq, NULL,
459 mv88e6xxx_g1_irq_thread_fn,
460 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
461 dev_name(chip->dev), chip);
462 if (err)
463 goto out;
464
465 return 0;
466
467out:
468 mv88e6xxx_g1_irq_free(chip);
469
470 return err;
471}
472
ec561276 473int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 474{
6441e669 475 int i;
2d79af6e 476
6441e669 477 for (i = 0; i < 16; i++) {
2d79af6e
VD		 478 u16 val;
479 int err;
480
481 err = mv88e6xxx_read(chip, addr, reg, &val);
482 if (err)
483 return err;
484
485 if (!(val & mask))
486 return 0;
487
488 usleep_range(1000, 2000);
489 }
490
30853553 491 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 492 return -ETIMEDOUT;
493}
494
f22ab641 495/* Indirect write to single pointer-data register with an Update bit */
ec561276 496int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 497{
498 u16 val;
0f02b4f7 499 int err;
f22ab641
VD		 500
501 /* Wait until the previous operation is completed */
0f02b4f7
AL		 502 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
503 if (err)
504 return err;
f22ab641
VD		 505
506 /* Set the Update bit to trigger a write operation */
507 val = BIT(15) | update;
508
509 return mv88e6xxx_write(chip, addr, reg, val);
510}
511
a935c052 512static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
914b32f6
VD		 513{
514 u16 val;
a935c052 515 int i, err;
914b32f6 516
a935c052 517 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
914b32f6
VD		 518 if (err)
519 return err;
520
a935c052
VD		 521 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
522 val & ~GLOBAL_CONTROL_PPU_ENABLE);
523 if (err)
524 return err;
2e5f0320 525
6441e669 526 for (i = 0; i < 16; i++) {
a935c052
VD		 527 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
528 if (err)
529 return err;
48ace4ef 530
19b2f97e 531 usleep_range(1000, 2000);
a935c052 532 if ((val & GLOBAL_STATUS_PPU_MASK) != GLOBAL_STATUS_PPU_POLLING)
85686581 533 return 0;
2e5f0320
LB		 534 }
535
536 return -ETIMEDOUT;
537}
538
fad09c73 539static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 540{
a935c052
VD		 541 u16 val;
542 int i, err;
2e5f0320 543
a935c052
VD		 544 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
545 if (err)
546 return err;
48ace4ef 547
a935c052
VD		 548 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
549 val | GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 550 if (err)
551 return err;
2e5f0320 552
6441e669 553 for (i = 0; i < 16; i++) {
a935c052
VD		 554 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
555 if (err)
556 return err;
48ace4ef 557
19b2f97e 558 usleep_range(1000, 2000);
a935c052 559 if ((val & GLOBAL_STATUS_PPU_MASK) == GLOBAL_STATUS_PPU_POLLING)
85686581 560 return 0;
2e5f0320
LB		 561 }
562
563 return -ETIMEDOUT;
564}
565
566static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
567{
fad09c73 568 struct mv88e6xxx_chip *chip;
2e5f0320 569
fad09c73 570 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 571
fad09c73 572 mutex_lock(&chip->reg_lock);
762eb67b 573
fad09c73
VD		 574 if (mutex_trylock(&chip->ppu_mutex)) {
575 if (mv88e6xxx_ppu_enable(chip) == 0)
576 chip->ppu_disabled = 0;
577 mutex_unlock(&chip->ppu_mutex);
2e5f0320 578 }
762eb67b 579
fad09c73 580 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 581}
582
583static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
584{
fad09c73 585 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 586
fad09c73 587 schedule_work(&chip->ppu_work);
2e5f0320
LB		 588}
589
fad09c73 590static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 591{
2e5f0320
LB		 592 int ret;
593
fad09c73 594 mutex_lock(&chip->ppu_mutex);
2e5f0320 595
3675c8d7 596 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 597 * we can access the PHY registers. If it was already
598 * disabled, cancel the timer that is going to re-enable
599 * it.
600 */
fad09c73
VD		 601 if (!chip->ppu_disabled) {
602 ret = mv88e6xxx_ppu_disable(chip);
85686581 603 if (ret < 0) {
fad09c73 604 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 605 return ret;
606 }
fad09c73 607 chip->ppu_disabled = 1;
2e5f0320 608 } else {
fad09c73 609 del_timer(&chip->ppu_timer);
85686581 610 ret = 0;
2e5f0320
LB		 611 }
612
613 return ret;
614}
615
fad09c73 616static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 617{
3675c8d7 618 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 619 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
620 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 621}
622
fad09c73 623static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 624{
fad09c73
VD		 625 mutex_init(&chip->ppu_mutex);
626 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
68497a87
WY		 627 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
628 (unsigned long)chip);
2e5f0320
LB		 629}
630
930188ce
AL		 631static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
632{
633 del_timer_sync(&chip->ppu_timer);
634}
635
e57e5e77
VD		 636static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
637 int reg, u16 *val)
2e5f0320 638{
e57e5e77 639 int err;
2e5f0320 640
e57e5e77
VD		 641 err = mv88e6xxx_ppu_access_get(chip);
642 if (!err) {
643 err = mv88e6xxx_read(chip, addr, reg, val);
fad09c73 644 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 645 }
646
e57e5e77 647 return err;
2e5f0320
LB		 648}
649
e57e5e77
VD		 650static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
651 int reg, u16 val)
2e5f0320 652{
e57e5e77 653 int err;
2e5f0320 654
e57e5e77
VD		 655 err = mv88e6xxx_ppu_access_get(chip);
656 if (!err) {
657 err = mv88e6xxx_write(chip, addr, reg, val);
fad09c73 658 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 659 }
660
e57e5e77 661 return err;
2e5f0320 662}
2e5f0320 663
fad09c73 664static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
54d792f2 665{
fad09c73 666 return chip->info->family == MV88E6XXX_FAMILY_6065;
54d792f2
AL		 667}
668
fad09c73 669static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
54d792f2 670{
fad09c73 671 return chip->info->family == MV88E6XXX_FAMILY_6095;
54d792f2
AL		 672}
673
fad09c73 674static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 675{
fad09c73 676 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 677}
678
fad09c73 679static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 680{
fad09c73 681 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 682}
683
fad09c73 684static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
54d792f2 685{
fad09c73 686 return chip->info->family == MV88E6XXX_FAMILY_6185;
54d792f2
AL		 687}
688
fad09c73 689static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
7c3d0d67 690{
fad09c73 691 return chip->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 692}
693
fad09c73 694static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 695{
fad09c73 696 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 697}
698
fad09c73 699static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 700{
fad09c73 701 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 702}
703
dea87024
AL		 704/* We expect the switch to perform auto negotiation if there is a real
705 * phy. However, in the case of a fixed link phy, we force the port
706 * settings from the fixed link settings.
707 */
f81ec90f
VD		 708static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
709 struct phy_device *phydev)
dea87024 710{
04bed143 711 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 712 u16 reg;
713 int err;
dea87024
AL		 714
715 if (!phy_is_pseudo_fixed_link(phydev))
716 return;
717
fad09c73 718 mutex_lock(&chip->reg_lock);
dea87024 719
0e7b9925
AL		 720 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
721 if (err)
dea87024
AL		 722 goto out;
723
0e7b9925
AL		 724 reg &= ~(PORT_PCS_CTRL_LINK_UP |
725 PORT_PCS_CTRL_FORCE_LINK |
726 PORT_PCS_CTRL_DUPLEX_FULL |
727 PORT_PCS_CTRL_FORCE_DUPLEX |
728 PORT_PCS_CTRL_UNFORCED);
dea87024
AL		 729
730 reg |= PORT_PCS_CTRL_FORCE_LINK;
731 if (phydev->link)
57d32310 732 reg |= PORT_PCS_CTRL_LINK_UP;
dea87024 733
fad09c73 734 if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
dea87024
AL		 735 goto out;
736
737 switch (phydev->speed) {
738 case SPEED_1000:
739 reg |= PORT_PCS_CTRL_1000;
740 break;
741 case SPEED_100:
742 reg |= PORT_PCS_CTRL_100;
743 break;
744 case SPEED_10:
745 reg |= PORT_PCS_CTRL_10;
746 break;
747 default:
748 pr_info("Unknown speed");
749 goto out;
750 }
751
752 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
753 if (phydev->duplex == DUPLEX_FULL)
754 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
755
fad09c73 756 if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
370b4ffb 757 (port >= mv88e6xxx_num_ports(chip) - 2)) {
e7e72ac0
AL		 758 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
759 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
760 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
761 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
762 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
763 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
764 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
765 }
0e7b9925 766 mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
dea87024
AL		 767
768out:
fad09c73 769 mutex_unlock(&chip->reg_lock);
dea87024
AL		 770}
771
fad09c73 772static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
91da11f8 773{
a935c052
VD		 774 u16 val;
775 int i, err;
91da11f8
LB		 776
777 for (i = 0; i < 10; i++) {
a935c052
VD		 778 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_OP, &val);
779 if ((val & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 780 return 0;
781 }
782
783 return -ETIMEDOUT;
784}
785
fad09c73 786static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 787{
a935c052 788 int err;
91da11f8 789
fad09c73 790 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
f3a8b6b6
AL		 791 port = (port + 1) << 5;
792
3675c8d7 793 /* Snapshot the hardware statistics counters for this port. */
a935c052
VD		 794 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
795 GLOBAL_STATS_OP_CAPTURE_PORT |
796 GLOBAL_STATS_OP_HIST_RX_TX | port);
797 if (err)
798 return err;
91da11f8 799
3675c8d7 800 /* Wait for the snapshotting to complete. */
a935c052 801 return _mv88e6xxx_stats_wait(chip);
91da11f8
LB		 802}
803
fad09c73 804static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
158bc065 805 int stat, u32 *val)
91da11f8 806{
a935c052
VD		 807 u32 value;
808 u16 reg;
809 int err;
91da11f8
LB		 810
811 *val = 0;
812
a935c052
VD		 813 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
814 GLOBAL_STATS_OP_READ_CAPTURED |
815 GLOBAL_STATS_OP_HIST_RX_TX | stat);
816 if (err)
91da11f8
LB		 817 return;
818
a935c052
VD		 819 err = _mv88e6xxx_stats_wait(chip);
820 if (err)
91da11f8
LB		 821 return;
822
a935c052
VD		 823 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_32, &reg);
824 if (err)
91da11f8
LB		 825 return;
826
a935c052 827 value = reg << 16;
91da11f8 828
a935c052
VD		 829 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_01, &reg);
830 if (err)
91da11f8
LB		 831 return;
832
a935c052 833 *val = value | reg;
91da11f8
LB		 834}
835
e413e7e1 836static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 837 { "in_good_octets", 8, 0x00, BANK0, },
838 { "in_bad_octets", 4, 0x02, BANK0, },
839 { "in_unicast", 4, 0x04, BANK0, },
840 { "in_broadcasts", 4, 0x06, BANK0, },
841 { "in_multicasts", 4, 0x07, BANK0, },
842 { "in_pause", 4, 0x16, BANK0, },
843 { "in_undersize", 4, 0x18, BANK0, },
844 { "in_fragments", 4, 0x19, BANK0, },
845 { "in_oversize", 4, 0x1a, BANK0, },
846 { "in_jabber", 4, 0x1b, BANK0, },
847 { "in_rx_error", 4, 0x1c, BANK0, },
848 { "in_fcs_error", 4, 0x1d, BANK0, },
849 { "out_octets", 8, 0x0e, BANK0, },
850 { "out_unicast", 4, 0x10, BANK0, },
851 { "out_broadcasts", 4, 0x13, BANK0, },
852 { "out_multicasts", 4, 0x12, BANK0, },
853 { "out_pause", 4, 0x15, BANK0, },
854 { "excessive", 4, 0x11, BANK0, },
855 { "collisions", 4, 0x1e, BANK0, },
856 { "deferred", 4, 0x05, BANK0, },
857 { "single", 4, 0x14, BANK0, },
858 { "multiple", 4, 0x17, BANK0, },
859 { "out_fcs_error", 4, 0x03, BANK0, },
860 { "late", 4, 0x1f, BANK0, },
861 { "hist_64bytes", 4, 0x08, BANK0, },
862 { "hist_65_127bytes", 4, 0x09, BANK0, },
863 { "hist_128_255bytes", 4, 0x0a, BANK0, },
864 { "hist_256_511bytes", 4, 0x0b, BANK0, },
865 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
866 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
867 { "sw_in_discards", 4, 0x10, PORT, },
868 { "sw_in_filtered", 2, 0x12, PORT, },
869 { "sw_out_filtered", 2, 0x13, PORT, },
870 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
871 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
872 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
873 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
874 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
875 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
876 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
877 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
878 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
879 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
880 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
881 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
882 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
883 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
884 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
885 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
886 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
887 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
888 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
889 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
890 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
891 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
892 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
893 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
894 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
895 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 896};
897
fad09c73 898static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 899 struct mv88e6xxx_hw_stat *stat)
e413e7e1 900{
f5e2ed02
AL		 901 switch (stat->type) {
902 case BANK0:
e413e7e1 903 return true;
f5e2ed02 904 case BANK1:
fad09c73 905 return mv88e6xxx_6320_family(chip);
f5e2ed02 906 case PORT:
fad09c73
VD		 907 return mv88e6xxx_6095_family(chip) ||
908 mv88e6xxx_6185_family(chip) ||
909 mv88e6xxx_6097_family(chip) ||
910 mv88e6xxx_6165_family(chip) ||
911 mv88e6xxx_6351_family(chip) ||
912 mv88e6xxx_6352_family(chip);
91da11f8 913 }
f5e2ed02 914 return false;
91da11f8
LB		 915}
916
fad09c73 917static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 918 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 919 int port)
920{
80c4627b
AL		 921 u32 low;
922 u32 high = 0;
0e7b9925
AL		 923 int err;
924 u16 reg;
80c4627b
AL		 925 u64 value;
926
f5e2ed02
AL		 927 switch (s->type) {
928 case PORT:
0e7b9925
AL		 929 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
930 if (err)
80c4627b
AL		 931 return UINT64_MAX;
932
0e7b9925 933 low = reg;
80c4627b 934 if (s->sizeof_stat == 4) {
0e7b9925
AL		 935 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
936 if (err)
80c4627b 937 return UINT64_MAX;
0e7b9925 938 high = reg;
80c4627b 939 }
f5e2ed02
AL		 940 break;
941 case BANK0:
942 case BANK1:
fad09c73 943 _mv88e6xxx_stats_read(chip, s->reg, &low);
80c4627b 944 if (s->sizeof_stat == 8)
fad09c73 945 _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
80c4627b
AL		 946 }
947 value = (((u64)high) << 16) | low;
948 return value;
949}
950
f81ec90f
VD		 951static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
952 uint8_t *data)
91da11f8 953{
04bed143 954 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02
AL		 955 struct mv88e6xxx_hw_stat *stat;
956 int i, j;
91da11f8 957
f5e2ed02
AL		 958 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
959 stat = &mv88e6xxx_hw_stats[i];
fad09c73 960 if (mv88e6xxx_has_stat(chip, stat)) {
f5e2ed02
AL		 961 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
962 ETH_GSTRING_LEN);
963 j++;
964 }
91da11f8 965 }
e413e7e1
AL		 966}
967
f81ec90f 968static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
e413e7e1 969{
04bed143 970 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02
AL		 971 struct mv88e6xxx_hw_stat *stat;
972 int i, j;
973
974 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
975 stat = &mv88e6xxx_hw_stats[i];
fad09c73 976 if (mv88e6xxx_has_stat(chip, stat))
f5e2ed02
AL		 977 j++;
978 }
979 return j;
e413e7e1
AL		 980}
981
f81ec90f
VD		 982static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
983 uint64_t *data)
e413e7e1 984{
04bed143 985 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02
AL		 986 struct mv88e6xxx_hw_stat *stat;
987 int ret;
988 int i, j;
989
fad09c73 990 mutex_lock(&chip->reg_lock);
f5e2ed02 991
fad09c73 992 ret = _mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 993 if (ret < 0) {
fad09c73 994 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 995 return;
996 }
997 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
998 stat = &mv88e6xxx_hw_stats[i];
fad09c73
VD		 999 if (mv88e6xxx_has_stat(chip, stat)) {
1000 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
f5e2ed02
AL		 1001 j++;
1002 }
1003 }
1004
fad09c73 1005 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 1006}
1007
f81ec90f 1008static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 1009{
1010 return 32 * sizeof(u16);
1011}
1012
f81ec90f
VD		 1013static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1014 struct ethtool_regs *regs, void *_p)
a1ab91f3 1015{
04bed143 1016 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 1017 int err;
1018 u16 reg;
a1ab91f3
GR		 1019 u16 *p = _p;
1020 int i;
1021
1022 regs->version = 0;
1023
1024 memset(p, 0xff, 32 * sizeof(u16));
1025
fad09c73 1026 mutex_lock(&chip->reg_lock);
23062513 1027
a1ab91f3 1028 for (i = 0; i < 32; i++) {
a1ab91f3 1029
0e7b9925
AL		 1030 err = mv88e6xxx_port_read(chip, port, i, &reg);
1031 if (!err)
1032 p[i] = reg;
a1ab91f3 1033 }
23062513 1034
fad09c73 1035 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 1036}
1037
fad09c73 1038static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
facd95b2 1039{
a935c052 1040 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 1041}
1042
f81ec90f
VD		 1043static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1044 struct ethtool_eee *e)
11b3b45d 1045{
04bed143 1046 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1047 u16 reg;
1048 int err;
11b3b45d 1049
fad09c73 1050 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1051 return -EOPNOTSUPP;
1052
fad09c73 1053 mutex_lock(&chip->reg_lock);
2f40c698 1054
9c93829c
VD		 1055 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1056 if (err)
2f40c698 1057 goto out;
11b3b45d
GR		 1058
1059 e->eee_enabled = !!(reg & 0x0200);
1060 e->tx_lpi_enabled = !!(reg & 0x0100);
1061
0e7b9925 1062 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
9c93829c 1063 if (err)
2f40c698 1064 goto out;
11b3b45d 1065
cca8b133 1066 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1067out:
fad09c73 1068 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 1069
1070 return err;
11b3b45d
GR		 1071}
1072
f81ec90f
VD		 1073static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1074 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 1075{
04bed143 1076 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1077 u16 reg;
1078 int err;
11b3b45d 1079
fad09c73 1080 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1081 return -EOPNOTSUPP;
1082
fad09c73 1083 mutex_lock(&chip->reg_lock);
11b3b45d 1084
9c93829c
VD		 1085 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1086 if (err)
2f40c698
AL		 1087 goto out;
1088
9c93829c 1089 reg &= ~0x0300;
2f40c698
AL		 1090 if (e->eee_enabled)
1091 reg |= 0x0200;
1092 if (e->tx_lpi_enabled)
1093 reg |= 0x0100;
1094
9c93829c 1095 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 1096out:
fad09c73 1097 mutex_unlock(&chip->reg_lock);
2f40c698 1098
9c93829c 1099 return err;
11b3b45d
GR		 1100}
1101
fad09c73 1102static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
facd95b2 1103{
a935c052
VD		 1104 u16 val;
1105 int err;
facd95b2 1106
6dc10bbc 1107 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
a935c052
VD		 1108 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
1109 if (err)
1110 return err;
fad09c73 1111 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f 1112 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
a935c052
VD		 1113 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
1114 if (err)
1115 return err;
11ea809f 1116
a935c052
VD		 1117 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
1118 (val & 0xfff) | ((fid << 8) & 0xf000));
1119 if (err)
1120 return err;
11ea809f
VD		 1121
1122 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1123 cmd |= fid & 0xf;
b426e5f7
VD		 1124 }
1125
a935c052
VD		 1126 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
1127 if (err)
1128 return err;
facd95b2 1129
fad09c73 1130 return _mv88e6xxx_atu_wait(chip);
facd95b2
GR		 1131}
1132
fad09c73 1133static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
37705b73
VD		 1134 struct mv88e6xxx_atu_entry *entry)
1135{
1136 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1137
1138 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1139 unsigned int mask, shift;
1140
1141 if (entry->trunk) {
1142 data |= GLOBAL_ATU_DATA_TRUNK;
1143 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1144 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1145 } else {
1146 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1147 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1148 }
1149
1150 data |= (entry->portv_trunkid << shift) & mask;
1151 }
1152
a935c052 1153 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
37705b73
VD		 1154}
1155
fad09c73 1156static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
7fb5e755
VD		 1157 struct mv88e6xxx_atu_entry *entry,
1158 bool static_too)
facd95b2 1159{
7fb5e755
VD		 1160 int op;
1161 int err;
facd95b2 1162
fad09c73 1163 err = _mv88e6xxx_atu_wait(chip);
7fb5e755
VD		 1164 if (err)
1165 return err;
facd95b2 1166
fad09c73 1167 err = _mv88e6xxx_atu_data_write(chip, entry);
7fb5e755
VD		 1168 if (err)
1169 return err;
1170
1171 if (entry->fid) {
7fb5e755
VD		 1172 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1173 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1174 } else {
1175 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1176 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1177 }
1178
fad09c73 1179 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
7fb5e755
VD		 1180}
1181
fad09c73 1182static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
158bc065 1183 u16 fid, bool static_too)
7fb5e755
VD		 1184{
1185 struct mv88e6xxx_atu_entry entry = {
1186 .fid = fid,
1187 .state = 0, /* EntryState bits must be 0 */
1188 };
70cc99d1 1189
fad09c73 1190 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
7fb5e755
VD		 1191}
1192
fad09c73 1193static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1194 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1195{
1196 struct mv88e6xxx_atu_entry entry = {
1197 .trunk = false,
1198 .fid = fid,
1199 };
1200
1201 /* EntryState bits must be 0xF */
1202 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1203
1204 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1205 entry.portv_trunkid = (to_port & 0x0f) << 4;
1206 entry.portv_trunkid |= from_port & 0x0f;
1207
fad09c73 1208 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
9f4d55d2
VD		 1209}
1210
fad09c73 1211static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1212 int port, bool static_too)
9f4d55d2
VD		 1213{
1214 /* Destination port 0xF means remove the entries */
fad09c73 1215 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1216}
1217
fad09c73 1218static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1219{
fad09c73 1220 struct net_device *bridge = chip->ports[port].bridge_dev;
fad09c73 1221 struct dsa_switch *ds = chip->ds;
b7666efe 1222 u16 output_ports = 0;
b7666efe
VD		 1223 int i;
1224
1225 /* allow CPU port or DSA link(s) to send frames to every port */
1226 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
5a7921f4 1227 output_ports = ~0;
b7666efe 1228 } else {
370b4ffb 1229 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b7666efe 1230 /* allow sending frames to every group member */
fad09c73 1231 if (bridge && chip->ports[i].bridge_dev == bridge)
b7666efe
VD		 1232 output_ports |= BIT(i);
1233
1234 /* allow sending frames to CPU port and DSA link(s) */
1235 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1236 output_ports |= BIT(i);
1237 }
1238 }
1239
1240 /* prevent frames from going back out of the port they came in on */
1241 output_ports &= ~BIT(port);
facd95b2 1242
5a7921f4 1243 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 1244}
1245
f81ec90f
VD		 1246static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1247 u8 state)
facd95b2 1248{
04bed143 1249 struct mv88e6xxx_chip *chip = ds->priv;
facd95b2 1250 int stp_state;
553eb544 1251 int err;
facd95b2
GR		 1252
1253 switch (state) {
1254 case BR_STATE_DISABLED:
cca8b133 1255 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1256 break;
1257 case BR_STATE_BLOCKING:
1258 case BR_STATE_LISTENING:
cca8b133 1259 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1260 break;
1261 case BR_STATE_LEARNING:
cca8b133 1262 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1263 break;
1264 case BR_STATE_FORWARDING:
1265 default:
cca8b133 1266 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1267 break;
1268 }
1269
fad09c73 1270 mutex_lock(&chip->reg_lock);
e28def33 1271 err = mv88e6xxx_port_set_state(chip, port, stp_state);
fad09c73 1272 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1273
1274 if (err)
e28def33 1275 netdev_err(ds->ports[port].netdev, "failed to update state\n");
facd95b2
GR		 1276}
1277
749efcb8
VD		 1278static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1279{
1280 struct mv88e6xxx_chip *chip = ds->priv;
1281 int err;
1282
1283 mutex_lock(&chip->reg_lock);
1284 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1285 mutex_unlock(&chip->reg_lock);
1286
1287 if (err)
1288 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1289}
1290
fad09c73 1291static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1292{
a935c052 1293 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
6b17e864
VD		 1294}
1295
fad09c73 1296static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864 1297{
a935c052 1298 int err;
6b17e864 1299
a935c052
VD		 1300 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1301 if (err)
1302 return err;
6b17e864 1303
fad09c73 1304 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1305}
1306
fad09c73 1307static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1308{
1309 int ret;
1310
fad09c73 1311 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1312 if (ret < 0)
1313 return ret;
1314
fad09c73 1315 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1316}
1317
fad09c73 1318static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1319 struct mv88e6xxx_vtu_entry *entry,
b8fee957
VD		 1320 unsigned int nibble_offset)
1321{
b8fee957 1322 u16 regs[3];
a935c052 1323 int i, err;
b8fee957
VD		 1324
1325 for (i = 0; i < 3; ++i) {
a935c052 1326 u16 *reg = &regs[i];
b8fee957 1327
a935c052
VD		 1328 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1329 if (err)
1330 return err;
b8fee957
VD		 1331 }
1332
370b4ffb 1333 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b8fee957
VD		 1334 unsigned int shift = (i % 4) * 4 + nibble_offset;
1335 u16 reg = regs[i / 4];
1336
1337 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1338 }
1339
1340 return 0;
1341}
1342
fad09c73 1343static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1344 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1345{
fad09c73 1346 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1347}
1348
fad09c73 1349static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1350 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1351{
fad09c73 1352 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1353}
1354
fad09c73 1355static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1356 struct mv88e6xxx_vtu_entry *entry,
7dad08d7
VD		 1357 unsigned int nibble_offset)
1358{
7dad08d7 1359 u16 regs[3] = { 0 };
a935c052 1360 int i, err;
7dad08d7 1361
370b4ffb 1362 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7dad08d7
VD		 1363 unsigned int shift = (i % 4) * 4 + nibble_offset;
1364 u8 data = entry->data[i];
1365
1366 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1367 }
1368
1369 for (i = 0; i < 3; ++i) {
a935c052
VD		 1370 u16 reg = regs[i];
1371
1372 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1373 if (err)
1374 return err;
7dad08d7
VD		 1375 }
1376
1377 return 0;
1378}
1379
fad09c73 1380static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1381 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1382{
fad09c73 1383 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1384}
1385
fad09c73 1386static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1387 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1388{
fad09c73 1389 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1390}
1391
fad09c73 1392static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1393{
a935c052
VD		 1394 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1395 vid & GLOBAL_VTU_VID_MASK);
36d04ba1
VD		 1396}
1397
fad09c73 1398static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b4e47c0f 1399 struct mv88e6xxx_vtu_entry *entry)
b8fee957 1400{
b4e47c0f 1401 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1402 u16 val;
1403 int err;
b8fee957 1404
a935c052
VD		 1405 err = _mv88e6xxx_vtu_wait(chip);
1406 if (err)
1407 return err;
b8fee957 1408
a935c052
VD		 1409 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1410 if (err)
1411 return err;
b8fee957 1412
a935c052
VD		 1413 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1414 if (err)
1415 return err;
b8fee957 1416
a935c052
VD		 1417 next.vid = val & GLOBAL_VTU_VID_MASK;
1418 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
b8fee957
VD		 1419
1420 if (next.valid) {
a935c052
VD		 1421 err = mv88e6xxx_vtu_data_read(chip, &next);
1422 if (err)
1423 return err;
b8fee957 1424
6dc10bbc 1425 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
a935c052
VD		 1426 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1427 if (err)
1428 return err;
b8fee957 1429
a935c052 1430 next.fid = val & GLOBAL_VTU_FID_MASK;
fad09c73 1431 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1432 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1433 * VTU DBNum[3:0] are located in VTU Operation 3:0
1434 */
a935c052
VD		 1435 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1436 if (err)
1437 return err;
11ea809f 1438
a935c052
VD		 1439 next.fid = (val & 0xf00) >> 4;
1440 next.fid |= val & 0xf;
2e7bd5ef 1441 }
b8fee957 1442
fad09c73 1443 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
a935c052
VD		 1444 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1445 if (err)
1446 return err;
b8fee957 1447
a935c052 1448 next.sid = val & GLOBAL_VTU_SID_MASK;
b8fee957
VD		 1449 }
1450 }
1451
1452 *entry = next;
1453 return 0;
1454}
1455
f81ec90f
VD		 1456static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1457 struct switchdev_obj_port_vlan *vlan,
1458 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1459{
04bed143 1460 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1461 struct mv88e6xxx_vtu_entry next;
ceff5eff
VD		 1462 u16 pvid;
1463 int err;
1464
fad09c73 1465 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1466 return -EOPNOTSUPP;
1467
fad09c73 1468 mutex_lock(&chip->reg_lock);
ceff5eff 1469
77064f37 1470 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
ceff5eff
VD		 1471 if (err)
1472 goto unlock;
1473
fad09c73 1474 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1475 if (err)
1476 goto unlock;
1477
1478 do {
fad09c73 1479 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1480 if (err)
1481 break;
1482
1483 if (!next.valid)
1484 break;
1485
1486 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1487 continue;
1488
1489 /* reinit and dump this VLAN obj */
57d32310
VD		 1490 vlan->vid_begin = next.vid;
1491 vlan->vid_end = next.vid;
ceff5eff
VD		 1492 vlan->flags = 0;
1493
1494 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1495 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1496
1497 if (next.vid == pvid)
1498 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1499
1500 err = cb(&vlan->obj);
1501 if (err)
1502 break;
1503 } while (next.vid < GLOBAL_VTU_VID_MASK);
1504
1505unlock:
fad09c73 1506 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1507
1508 return err;
1509}
1510
fad09c73 1511static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1512 struct mv88e6xxx_vtu_entry *entry)
7dad08d7 1513{
11ea809f 1514 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7 1515 u16 reg = 0;
a935c052 1516 int err;
7dad08d7 1517
a935c052
VD		 1518 err = _mv88e6xxx_vtu_wait(chip);
1519 if (err)
1520 return err;
7dad08d7
VD		 1521
1522 if (!entry->valid)
1523 goto loadpurge;
1524
1525 /* Write port member tags */
a935c052
VD		 1526 err = mv88e6xxx_vtu_data_write(chip, entry);
1527 if (err)
1528 return err;
7dad08d7 1529
fad09c73 1530 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1531 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1532 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1533 if (err)
1534 return err;
b426e5f7 1535 }
7dad08d7 1536
6dc10bbc 1537 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
7dad08d7 1538 reg = entry->fid & GLOBAL_VTU_FID_MASK;
a935c052
VD		 1539 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1540 if (err)
1541 return err;
fad09c73 1542 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1543 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1544 * VTU DBNum[3:0] are located in VTU Operation 3:0
1545 */
1546 op |= (entry->fid & 0xf0) << 8;
1547 op |= entry->fid & 0xf;
7dad08d7
VD		 1548 }
1549
1550 reg = GLOBAL_VTU_VID_VALID;
1551loadpurge:
1552 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
a935c052
VD		 1553 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1554 if (err)
1555 return err;
7dad08d7 1556
fad09c73 1557 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1558}
1559
fad09c73 1560static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
b4e47c0f 1561 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1562{
b4e47c0f 1563 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1564 u16 val;
1565 int err;
0d3b33e6 1566
a935c052
VD		 1567 err = _mv88e6xxx_vtu_wait(chip);
1568 if (err)
1569 return err;
0d3b33e6 1570
a935c052
VD		 1571 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1572 sid & GLOBAL_VTU_SID_MASK);
1573 if (err)
1574 return err;
0d3b33e6 1575
a935c052
VD		 1576 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1577 if (err)
1578 return err;
0d3b33e6 1579
a935c052
VD		 1580 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1581 if (err)
1582 return err;
0d3b33e6 1583
a935c052 1584 next.sid = val & GLOBAL_VTU_SID_MASK;
0d3b33e6 1585
a935c052
VD		 1586 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1587 if (err)
1588 return err;
0d3b33e6 1589
a935c052 1590 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
0d3b33e6
VD		 1591
1592 if (next.valid) {
a935c052
VD		 1593 err = mv88e6xxx_stu_data_read(chip, &next);
1594 if (err)
1595 return err;
0d3b33e6
VD		 1596 }
1597
1598 *entry = next;
1599 return 0;
1600}
1601
fad09c73 1602static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1603 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6
VD		 1604{
1605 u16 reg = 0;
a935c052 1606 int err;
0d3b33e6 1607
a935c052
VD		 1608 err = _mv88e6xxx_vtu_wait(chip);
1609 if (err)
1610 return err;
0d3b33e6
VD		 1611
1612 if (!entry->valid)
1613 goto loadpurge;
1614
1615 /* Write port states */
a935c052
VD		 1616 err = mv88e6xxx_stu_data_write(chip, entry);
1617 if (err)
1618 return err;
0d3b33e6
VD		 1619
1620 reg = GLOBAL_VTU_VID_VALID;
1621loadpurge:
a935c052
VD		 1622 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1623 if (err)
1624 return err;
0d3b33e6
VD		 1625
1626 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1627 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1628 if (err)
1629 return err;
0d3b33e6 1630
fad09c73 1631 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1632}
1633
fad09c73 1634static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1635{
1636 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
b4e47c0f 1637 struct mv88e6xxx_vtu_entry vlan;
2db9ce1f 1638 int i, err;
3285f9e8
VD		 1639
1640 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1641
2db9ce1f 1642 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1643 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1644 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1645 if (err)
1646 return err;
1647
1648 set_bit(*fid, fid_bitmap);
1649 }
1650
3285f9e8 1651 /* Set every FID bit used by the VLAN entries */
fad09c73 1652 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1653 if (err)
1654 return err;
1655
1656 do {
fad09c73 1657 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1658 if (err)
1659 return err;
1660
1661 if (!vlan.valid)
1662 break;
1663
1664 set_bit(vlan.fid, fid_bitmap);
1665 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1666
1667 /* The reset value 0x000 is used to indicate that multiple address
1668 * databases are not needed. Return the next positive available.
1669 */
1670 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1671 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1672 return -ENOSPC;
1673
1674 /* Clear the database */
fad09c73 1675 return _mv88e6xxx_atu_flush(chip, *fid, true);
3285f9e8
VD		 1676}
1677
fad09c73 1678static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1679 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1680{
fad09c73 1681 struct dsa_switch *ds = chip->ds;
b4e47c0f 1682 struct mv88e6xxx_vtu_entry vlan = {
0d3b33e6
VD		 1683 .valid = true,
1684 .vid = vid,
1685 };
3285f9e8
VD		 1686 int i, err;
1687
fad09c73 1688 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
3285f9e8
VD		 1689 if (err)
1690 return err;
0d3b33e6 1691
3d131f07 1692 /* exclude all ports except the CPU and DSA ports */
370b4ffb 1693 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
3d131f07
VD		 1694 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1695 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1696 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1697
fad09c73
VD		 1698 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1699 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
b4e47c0f 1700 struct mv88e6xxx_vtu_entry vstp;
0d3b33e6
VD		 1701
1702 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1703 * implemented, only one STU entry is needed to cover all VTU
1704 * entries. Thus, validate the SID 0.
1705 */
1706 vlan.sid = 0;
fad09c73 1707 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1708 if (err)
1709 return err;
1710
1711 if (vstp.sid != vlan.sid || !vstp.valid) {
1712 memset(&vstp, 0, sizeof(vstp));
1713 vstp.valid = true;
1714 vstp.sid = vlan.sid;
1715
fad09c73 1716 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1717 if (err)
1718 return err;
1719 }
0d3b33e6
VD		 1720 }
1721
1722 *entry = vlan;
1723 return 0;
1724}
1725
fad09c73 1726static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1727 struct mv88e6xxx_vtu_entry *entry, bool creat)
2fb5ef09
VD		 1728{
1729 int err;
1730
1731 if (!vid)
1732 return -EINVAL;
1733
fad09c73 1734 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1735 if (err)
1736 return err;
1737
fad09c73 1738 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1739 if (err)
1740 return err;
1741
1742 if (entry->vid != vid || !entry->valid) {
1743 if (!creat)
1744 return -EOPNOTSUPP;
1745 /* -ENOENT would've been more appropriate, but switchdev expects
1746 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1747 */
1748
fad09c73 1749 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1750 }
1751
1752 return err;
1753}
1754
da9c359e
VD		 1755static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1756 u16 vid_begin, u16 vid_end)
1757{
04bed143 1758 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1759 struct mv88e6xxx_vtu_entry vlan;
da9c359e
VD		 1760 int i, err;
1761
1762 if (!vid_begin)
1763 return -EOPNOTSUPP;
1764
fad09c73 1765 mutex_lock(&chip->reg_lock);
da9c359e 1766
fad09c73 1767 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1768 if (err)
1769 goto unlock;
1770
1771 do {
fad09c73 1772 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1773 if (err)
1774 goto unlock;
1775
1776 if (!vlan.valid)
1777 break;
1778
1779 if (vlan.vid > vid_end)
1780 break;
1781
370b4ffb 1782 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1783 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1784 continue;
1785
1786 if (vlan.data[i] ==
1787 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1788 continue;
1789
fad09c73
VD		 1790 if (chip->ports[i].bridge_dev ==
1791 chip->ports[port].bridge_dev)
da9c359e
VD		 1792 break; /* same bridge, check next VLAN */
1793
c8b09808 1794 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1795 "hardware VLAN %d already used by %s\n",
1796 vlan.vid,
fad09c73 1797 netdev_name(chip->ports[i].bridge_dev));
da9c359e
VD		 1798 err = -EOPNOTSUPP;
1799 goto unlock;
1800 }
1801 } while (vlan.vid < vid_end);
1802
1803unlock:
fad09c73 1804 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1805
1806 return err;
1807}
1808
214cdb99
VD		 1809static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1810 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1811 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1812 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1813 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1814};
1815
f81ec90f
VD		 1816static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1817 bool vlan_filtering)
214cdb99 1818{
04bed143 1819 struct mv88e6xxx_chip *chip = ds->priv;
214cdb99
VD		 1820 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1821 PORT_CONTROL_2_8021Q_DISABLED;
0e7b9925
AL		 1822 u16 reg;
1823 int err;
214cdb99 1824
fad09c73 1825 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1826 return -EOPNOTSUPP;
1827
fad09c73 1828 mutex_lock(&chip->reg_lock);
214cdb99 1829
0e7b9925
AL		 1830 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, &reg);
1831 if (err)
214cdb99
VD		 1832 goto unlock;
1833
0e7b9925 1834 old = reg & PORT_CONTROL_2_8021Q_MASK;
214cdb99 1835
5220ef1e 1836 if (new != old) {
0e7b9925
AL		 1837 reg &= ~PORT_CONTROL_2_8021Q_MASK;
1838 reg |= new & PORT_CONTROL_2_8021Q_MASK;
214cdb99 1839
0e7b9925
AL		 1840 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
1841 if (err)
5220ef1e
VD		 1842 goto unlock;
1843
c8b09808 1844 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
5220ef1e
VD		 1845 mv88e6xxx_port_8021q_mode_names[new],
1846 mv88e6xxx_port_8021q_mode_names[old]);
1847 }
214cdb99 1848
0e7b9925 1849 err = 0;
214cdb99 1850unlock:
fad09c73 1851 mutex_unlock(&chip->reg_lock);
214cdb99 1852
0e7b9925 1853 return err;
214cdb99
VD		 1854}
1855
57d32310
VD		 1856static int
1857mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1858 const struct switchdev_obj_port_vlan *vlan,
1859 struct switchdev_trans *trans)
76e398a6 1860{
04bed143 1861 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1862 int err;
1863
fad09c73 1864 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1865 return -EOPNOTSUPP;
1866
da9c359e
VD		 1867 /* If the requested port doesn't belong to the same bridge as the VLAN
1868 * members, do not support it (yet) and fallback to software VLAN.
1869 */
1870 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1871 vlan->vid_end);
1872 if (err)
1873 return err;
1874
76e398a6
VD		 1875 /* We don't need any dynamic resource from the kernel (yet),
1876 * so skip the prepare phase.
1877 */
1878 return 0;
1879}
1880
fad09c73 1881static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1882 u16 vid, bool untagged)
0d3b33e6 1883{
b4e47c0f 1884 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1885 int err;
1886
fad09c73 1887 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1888 if (err)
76e398a6 1889 return err;
0d3b33e6 1890
0d3b33e6
VD		 1891 vlan.data[port] = untagged ?
1892 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1893 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1894
fad09c73 1895 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1896}
1897
f81ec90f
VD		 1898static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1899 const struct switchdev_obj_port_vlan *vlan,
1900 struct switchdev_trans *trans)
76e398a6 1901{
04bed143 1902 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1903 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1904 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1905 u16 vid;
76e398a6 1906
fad09c73 1907 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1908 return;
1909
fad09c73 1910 mutex_lock(&chip->reg_lock);
76e398a6 1911
4d5770b3 1912 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1913 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1914 netdev_err(ds->ports[port].netdev,
1915 "failed to add VLAN %d%c\n",
4d5770b3 1916 vid, untagged ? 'u' : 't');
76e398a6 1917
77064f37 1918 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
c8b09808 1919 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1920 vlan->vid_end);
0d3b33e6 1921
fad09c73 1922 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1923}
1924
fad09c73 1925static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1926 int port, u16 vid)
7dad08d7 1927{
fad09c73 1928 struct dsa_switch *ds = chip->ds;
b4e47c0f 1929 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1930 int i, err;
1931
fad09c73 1932 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1933 if (err)
76e398a6 1934 return err;
7dad08d7 1935
2fb5ef09
VD		 1936 /* Tell switchdev if this VLAN is handled in software */
1937 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1938 return -EOPNOTSUPP;
7dad08d7
VD		 1939
1940 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1941
1942 /* keep the VLAN unless all ports are excluded */
f02bdffc 1943 vlan.valid = false;
370b4ffb 1944 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
3d131f07 1945 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1946 continue;
1947
1948 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1949 vlan.valid = true;
7dad08d7
VD		 1950 break;
1951 }
1952 }
1953
fad09c73 1954 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1955 if (err)
1956 return err;
1957
fad09c73 1958 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1959}
1960
f81ec90f
VD		 1961static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1962 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1963{
04bed143 1964 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1965 u16 pvid, vid;
1966 int err = 0;
1967
fad09c73 1968 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1969 return -EOPNOTSUPP;
1970
fad09c73 1971 mutex_lock(&chip->reg_lock);
76e398a6 1972
77064f37 1973 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1974 if (err)
1975 goto unlock;
1976
76e398a6 1977 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1978 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1979 if (err)
1980 goto unlock;
1981
1982 if (vid == pvid) {
77064f37 1983 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1984 if (err)
1985 goto unlock;
1986 }
1987 }
1988
7dad08d7 1989unlock:
fad09c73 1990 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 1991
1992 return err;
1993}
1994
fad09c73 1995static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
c5723ac5 1996 const unsigned char *addr)
defb05b9 1997{
a935c052 1998 int i, err;
defb05b9
GR		 1999
2000 for (i = 0; i < 3; i++) {
a935c052
VD		 2001 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
2002 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2003 if (err)
2004 return err;
defb05b9
GR		 2005 }
2006
2007 return 0;
2008}
2009
fad09c73 2010static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
158bc065 2011 unsigned char *addr)
defb05b9 2012{
a935c052
VD		 2013 u16 val;
2014 int i, err;
defb05b9
GR		 2015
2016 for (i = 0; i < 3; i++) {
a935c052
VD		 2017 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
2018 if (err)
2019 return err;
2020
2021 addr[i * 2] = val >> 8;
2022 addr[i * 2 + 1] = val & 0xff;
defb05b9
GR		 2023 }
2024
2025 return 0;
2026}
2027
fad09c73 2028static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
fd231c82 2029 struct mv88e6xxx_atu_entry *entry)
defb05b9 2030{
6630e236
VD		 2031 int ret;
2032
fad09c73 2033 ret = _mv88e6xxx_atu_wait(chip);
defb05b9
GR		 2034 if (ret < 0)
2035 return ret;
2036
fad09c73 2037 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
defb05b9
GR		 2038 if (ret < 0)
2039 return ret;
2040
fad09c73 2041 ret = _mv88e6xxx_atu_data_write(chip, entry);
fd231c82 2042 if (ret < 0)
87820510
VD		 2043 return ret;
2044
fad09c73 2045 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2046}
87820510 2047
88472939
VD		 2048static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2049 struct mv88e6xxx_atu_entry *entry);
2050
2051static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2052 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2053{
2054 struct mv88e6xxx_atu_entry next;
2055 int err;
2056
2057 eth_broadcast_addr(next.mac);
2058
2059 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2060 if (err)
2061 return err;
2062
2063 do {
2064 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2065 if (err)
2066 return err;
2067
2068 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2069 break;
2070
2071 if (ether_addr_equal(next.mac, addr)) {
2072 *entry = next;
2073 return 0;
2074 }
2075 } while (!is_broadcast_ether_addr(next.mac));
2076
2077 memset(entry, 0, sizeof(*entry));
2078 entry->fid = fid;
2079 ether_addr_copy(entry->mac, addr);
2080
2081 return 0;
2082}
2083
83dabd1f
VD		 2084static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2085 const unsigned char *addr, u16 vid,
2086 u8 state)
fd231c82 2087{
b4e47c0f 2088 struct mv88e6xxx_vtu_entry vlan;
88472939 2089 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 2090 int err;
2091
2db9ce1f
VD		 2092 /* Null VLAN ID corresponds to the port private database */
2093 if (vid == 0)
b4e48c50 2094 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2db9ce1f 2095 else
fad09c73 2096 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 2097 if (err)
2098 return err;
fd231c82 2099
88472939
VD		 2100 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2101 if (err)
2102 return err;
2103
2104 /* Purge the ATU entry only if no port is using it anymore */
2105 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2106 entry.portv_trunkid &= ~BIT(port);
2107 if (!entry.portv_trunkid)
2108 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2109 } else {
2110 entry.portv_trunkid |= BIT(port);
2111 entry.state = state;
fd231c82
VD		 2112 }
2113
fad09c73 2114 return _mv88e6xxx_atu_load(chip, &entry);
87820510
VD		 2115}
2116
f81ec90f
VD		 2117static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2118 const struct switchdev_obj_port_fdb *fdb,
2119 struct switchdev_trans *trans)
146a3206
VD		 2120{
2121 /* We don't need any dynamic resource from the kernel (yet),
2122 * so skip the prepare phase.
2123 */
2124 return 0;
2125}
2126
f81ec90f
VD		 2127static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2128 const struct switchdev_obj_port_fdb *fdb,
2129 struct switchdev_trans *trans)
87820510 2130{
04bed143 2131 struct mv88e6xxx_chip *chip = ds->priv;
87820510 2132
fad09c73 2133 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2134 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2135 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2136 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
fad09c73 2137 mutex_unlock(&chip->reg_lock);
87820510
VD		 2138}
2139
f81ec90f
VD		 2140static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2141 const struct switchdev_obj_port_fdb *fdb)
87820510 2142{
04bed143 2143 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 2144 int err;
87820510 2145
fad09c73 2146 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2147 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2148 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 2149 mutex_unlock(&chip->reg_lock);
87820510 2150
83dabd1f 2151 return err;
87820510
VD		 2152}
2153
fad09c73 2154static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
1d194046 2155 struct mv88e6xxx_atu_entry *entry)
6630e236 2156{
1d194046 2157 struct mv88e6xxx_atu_entry next = { 0 };
a935c052
VD		 2158 u16 val;
2159 int err;
1d194046
VD		 2160
2161 next.fid = fid;
defb05b9 2162
a935c052
VD		 2163 err = _mv88e6xxx_atu_wait(chip);
2164 if (err)
2165 return err;
6630e236 2166
a935c052
VD		 2167 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2168 if (err)
2169 return err;
6630e236 2170
a935c052
VD		 2171 err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2172 if (err)
2173 return err;
6630e236 2174
a935c052
VD		 2175 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2176 if (err)
2177 return err;
6630e236 2178
a935c052 2179 next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
1d194046
VD		 2180 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2181 unsigned int mask, shift;
2182
a935c052 2183 if (val & GLOBAL_ATU_DATA_TRUNK) {
1d194046
VD		 2184 next.trunk = true;
2185 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2186 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2187 } else {
2188 next.trunk = false;
2189 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2190 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2191 }
2192
a935c052 2193 next.portv_trunkid = (val & mask) >> shift;
1d194046 2194 }
cdf09697 2195
1d194046 2196 *entry = next;
cdf09697
DM		 2197 return 0;
2198}
2199
83dabd1f
VD		 2200static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2201 u16 fid, u16 vid, int port,
2202 struct switchdev_obj *obj,
2203 int (*cb)(struct switchdev_obj *obj))
74b6ba0d
VD		 2204{
2205 struct mv88e6xxx_atu_entry addr = {
2206 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2207 };
2208 int err;
2209
fad09c73 2210 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
74b6ba0d
VD		 2211 if (err)
2212 return err;
2213
2214 do {
fad09c73 2215 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
74b6ba0d 2216 if (err)
83dabd1f 2217 return err;
74b6ba0d
VD		 2218
2219 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2220 break;
2221
83dabd1f
VD		 2222 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2223 continue;
2224
2225 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2226 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 2227
83dabd1f
VD		 2228 if (!is_unicast_ether_addr(addr.mac))
2229 continue;
2230
2231 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 2232 fdb->vid = vid;
2233 ether_addr_copy(fdb->addr, addr.mac);
83dabd1f
VD		 2234 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2235 fdb->ndm_state = NUD_NOARP;
2236 else
2237 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 2238 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2239 struct switchdev_obj_port_mdb *mdb;
2240
2241 if (!is_multicast_ether_addr(addr.mac))
2242 continue;
2243
2244 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2245 mdb->vid = vid;
2246 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 2247 } else {
2248 return -EOPNOTSUPP;
74b6ba0d 2249 }
83dabd1f
VD		 2250
2251 err = cb(obj);
2252 if (err)
2253 return err;
74b6ba0d
VD		 2254 } while (!is_broadcast_ether_addr(addr.mac));
2255
2256 return err;
2257}
2258
83dabd1f
VD		 2259static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2260 struct switchdev_obj *obj,
2261 int (*cb)(struct switchdev_obj *obj))
f33475bd 2262{
b4e47c0f 2263 struct mv88e6xxx_vtu_entry vlan = {
f33475bd
VD		 2264 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2265 };
2db9ce1f 2266 u16 fid;
f33475bd
VD		 2267 int err;
2268
2db9ce1f 2269 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 2270 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 2271 if (err)
83dabd1f 2272 return err;
2db9ce1f 2273
83dabd1f 2274 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 2275 if (err)
83dabd1f 2276 return err;
2db9ce1f 2277
74b6ba0d 2278 /* Dump VLANs' Filtering Information Databases */
fad09c73 2279 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd 2280 if (err)
83dabd1f 2281 return err;
f33475bd
VD		 2282
2283 do {
fad09c73 2284 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2285 if (err)
83dabd1f 2286 return err;
f33475bd
VD		 2287
2288 if (!vlan.valid)
2289 break;
2290
83dabd1f
VD		 2291 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2292 obj, cb);
f33475bd 2293 if (err)
83dabd1f 2294 return err;
f33475bd
VD		 2295 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2296
83dabd1f
VD		 2297 return err;
2298}
2299
2300static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2301 struct switchdev_obj_port_fdb *fdb,
2302 int (*cb)(struct switchdev_obj *obj))
2303{
04bed143 2304 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 2305 int err;
2306
2307 mutex_lock(&chip->reg_lock);
2308 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 2309 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2310
2311 return err;
2312}
2313
f81ec90f
VD		 2314static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2315 struct net_device *bridge)
e79a8bcb 2316{
04bed143 2317 struct mv88e6xxx_chip *chip = ds->priv;
1d9619d5 2318 int i, err = 0;
466dfa07 2319
fad09c73 2320 mutex_lock(&chip->reg_lock);
466dfa07 2321
b7666efe 2322 /* Assign the bridge and remap each port's VLANTable */
fad09c73 2323 chip->ports[port].bridge_dev = bridge;
b7666efe 2324
370b4ffb 2325 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
fad09c73
VD		 2326 if (chip->ports[i].bridge_dev == bridge) {
2327 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2328 if (err)
2329 break;
2330 }
2331 }
2332
fad09c73 2333 mutex_unlock(&chip->reg_lock);
a6692754 2334
466dfa07 2335 return err;
e79a8bcb
VD		 2336}
2337
f81ec90f 2338static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2339{
04bed143 2340 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 2341 struct net_device *bridge = chip->ports[port].bridge_dev;
16bfa702 2342 int i;
466dfa07 2343
fad09c73 2344 mutex_lock(&chip->reg_lock);
466dfa07 2345
b7666efe 2346 /* Unassign the bridge and remap each port's VLANTable */
fad09c73 2347 chip->ports[port].bridge_dev = NULL;
b7666efe 2348
370b4ffb 2349 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
fad09c73
VD		 2350 if (i == port || chip->ports[i].bridge_dev == bridge)
2351 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2352 netdev_warn(ds->ports[i].netdev,
2353 "failed to remap\n");
b7666efe 2354
fad09c73 2355 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2356}
2357
fad09c73 2358static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
552238b5 2359{
fad09c73 2360 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
552238b5 2361 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
fad09c73 2362 struct gpio_desc *gpiod = chip->reset;
552238b5 2363 unsigned long timeout;
0e7b9925 2364 u16 reg;
a935c052 2365 int err;
552238b5
VD		 2366 int i;
2367
2368 /* Set all ports to the disabled state. */
370b4ffb 2369 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
e28def33
VD		 2370 err = mv88e6xxx_port_set_state(chip, i,
2371 PORT_CONTROL_STATE_DISABLED);
0e7b9925
AL		 2372 if (err)
2373 return err;
552238b5
VD		 2374 }
2375
2376 /* Wait for transmit queues to drain. */
2377 usleep_range(2000, 4000);
2378
2379 /* If there is a gpio connected to the reset pin, toggle it */
2380 if (gpiod) {
2381 gpiod_set_value_cansleep(gpiod, 1);
2382 usleep_range(10000, 20000);
2383 gpiod_set_value_cansleep(gpiod, 0);
2384 usleep_range(10000, 20000);
2385 }
2386
2387 /* Reset the switch. Keep the PPU active if requested. The PPU
2388 * needs to be active to support indirect phy register access
2389 * through global registers 0x18 and 0x19.
2390 */
2391 if (ppu_active)
a935c052 2392 err = mv88e6xxx_g1_write(chip, 0x04, 0xc000);
552238b5 2393 else
a935c052 2394 err = mv88e6xxx_g1_write(chip, 0x04, 0xc400);
0e7b9925
AL		 2395 if (err)
2396 return err;
552238b5
VD		 2397
2398 /* Wait up to one second for reset to complete. */
2399 timeout = jiffies + 1 * HZ;
2400 while (time_before(jiffies, timeout)) {
a935c052
VD		 2401 err = mv88e6xxx_g1_read(chip, 0x00, &reg);
2402 if (err)
2403 return err;
552238b5 2404
a935c052 2405 if ((reg & is_reset) == is_reset)
552238b5
VD		 2406 break;
2407 usleep_range(1000, 2000);
2408 }
2409 if (time_after(jiffies, timeout))
0e7b9925 2410 err = -ETIMEDOUT;
552238b5 2411 else
0e7b9925 2412 err = 0;
552238b5 2413
0e7b9925 2414 return err;
552238b5
VD		 2415}
2416
09cb7dfd 2417static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
13a7ebb3 2418{
09cb7dfd
VD		 2419 u16 val;
2420 int err;
13a7ebb3 2421
09cb7dfd
VD		 2422 /* Clear Power Down bit */
2423 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2424 if (err)
2425 return err;
13a7ebb3 2426
09cb7dfd
VD		 2427 if (val & BMCR_PDOWN) {
2428 val &= ~BMCR_PDOWN;
2429 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
13a7ebb3
PU		 2430 }
2431
09cb7dfd 2432 return err;
13a7ebb3
PU		 2433}
2434
fad09c73 2435static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2436{
fad09c73 2437 struct dsa_switch *ds = chip->ds;
0e7b9925 2438 int err;
54d792f2 2439 u16 reg;
d827e88a 2440
fad09c73
VD		 2441 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2442 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2443 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2444 mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2445 /* MAC Forcing register: don't force link, speed,
2446 * duplex or flow control state to any particular
2447 * values on physical ports, but force the CPU port
2448 * and all DSA ports to their maximum bandwidth and
2449 * full duplex.
2450 */
0e7b9925 2451 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
60045cbf 2452 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 2453 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 2454 reg |= PORT_PCS_CTRL_FORCE_LINK |
2455 PORT_PCS_CTRL_LINK_UP |
2456 PORT_PCS_CTRL_DUPLEX_FULL |
2457 PORT_PCS_CTRL_FORCE_DUPLEX;
fad09c73 2458 if (mv88e6xxx_6065_family(chip))
54d792f2
AL		 2459 reg |= PORT_PCS_CTRL_100;
2460 else
2461 reg |= PORT_PCS_CTRL_1000;
2462 } else {
2463 reg |= PORT_PCS_CTRL_UNFORCED;
2464 }
2465
0e7b9925
AL		 2466 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
2467 if (err)
2468 return err;
54d792f2
AL		 2469 }
2470
2471 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2472 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2473 * tunneling, determine priority by looking at 802.1p and IP
2474 * priority fields (IP prio has precedence), and set STP state
2475 * to Forwarding.
2476 *
2477 * If this is the CPU link, use DSA or EDSA tagging depending
2478 * on which tagging mode was configured.
2479 *
2480 * If this is a link to another switch, use DSA tagging mode.
2481 *
2482 * If this is the upstream port for this switch, enable
2483 * forwarding of unknown unicasts and multicasts.
2484 */
2485 reg = 0;
fad09c73
VD		 2486 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2487 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2488 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2489 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2490 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2491 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2492 PORT_CONTROL_STATE_FORWARDING;
2493 if (dsa_is_cpu_port(ds, port)) {
2bbb33be 2494 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
5377b802 2495 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
c047a1f9 2496 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2bbb33be
AL		 2497 else
2498 reg |= PORT_CONTROL_DSA_TAG;
f027e0cc
JL		 2499 reg |= PORT_CONTROL_EGRESS_ADD_TAG |
2500 PORT_CONTROL_FORWARD_UNKNOWN;
54d792f2 2501 }
6083ce71 2502 if (dsa_is_dsa_port(ds, port)) {
fad09c73
VD		 2503 if (mv88e6xxx_6095_family(chip) ||
2504 mv88e6xxx_6185_family(chip))
6083ce71 2505 reg |= PORT_CONTROL_DSA_TAG;
fad09c73
VD		 2506 if (mv88e6xxx_6352_family(chip) ||
2507 mv88e6xxx_6351_family(chip) ||
2508 mv88e6xxx_6165_family(chip) ||
2509 mv88e6xxx_6097_family(chip) ||
2510 mv88e6xxx_6320_family(chip)) {
54d792f2 2511 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2512 }
2513
54d792f2
AL		 2514 if (port == dsa_upstream_port(ds))
2515 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2516 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2517 }
2518 if (reg) {
0e7b9925
AL		 2519 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2520 if (err)
2521 return err;
54d792f2
AL		 2522 }
2523
13a7ebb3
PU		 2524 /* If this port is connected to a SerDes, make sure the SerDes is not
2525 * powered down.
2526 */
09cb7dfd 2527 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
0e7b9925
AL		 2528 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2529 if (err)
2530 return err;
2531 reg &= PORT_STATUS_CMODE_MASK;
2532 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2533 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2534 (reg == PORT_STATUS_CMODE_SGMII)) {
2535 err = mv88e6xxx_serdes_power_on(chip);
2536 if (err < 0)
2537 return err;
13a7ebb3
PU		 2538 }
2539 }
2540
8efdda4a 2541 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2542 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2543 * untagged frames on this port, do a destination address lookup on all
2544 * received packets as usual, disable ARP mirroring and don't send a
2545 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2546 */
2547 reg = 0;
fad09c73
VD		 2548 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2549 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2550 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2551 mv88e6xxx_6185_family(chip))
54d792f2
AL		 2552 reg = PORT_CONTROL_2_MAP_DA;
2553
fad09c73
VD		 2554 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2555 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2556 reg |= PORT_CONTROL_2_JUMBO_10240;
2557
fad09c73 2558 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
54d792f2
AL		 2559 /* Set the upstream port this port should use */
2560 reg |= dsa_upstream_port(ds);
2561 /* enable forwarding of unknown multicast addresses to
2562 * the upstream port
2563 */
2564 if (port == dsa_upstream_port(ds))
2565 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2566 }
2567
46fbe5e5 2568 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2569
54d792f2 2570 if (reg) {
0e7b9925
AL		 2571 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
2572 if (err)
2573 return err;
54d792f2
AL		 2574 }
2575
2576 /* Port Association Vector: when learning source addresses
2577 * of packets, add the address to the address database using
2578 * a port bitmap that has only the bit for this port set and
2579 * the other bits clear.
2580 */
4c7ea3c0 2581 reg = 1 << port;
996ecb82
VD		 2582 /* Disable learning for CPU port */
2583 if (dsa_is_cpu_port(ds, port))
65fa4027 2584 reg = 0;
4c7ea3c0 2585
0e7b9925
AL		 2586 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2587 if (err)
2588 return err;
54d792f2
AL		 2589
2590 /* Egress rate control 2: disable egress rate control. */
0e7b9925
AL		 2591 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2592 if (err)
2593 return err;
54d792f2 2594
fad09c73
VD		 2595 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2596 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2597 mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2598 /* Do not limit the period of time that this port can
2599 * be paused for by the remote end or the period of
2600 * time that this port can pause the remote end.
2601 */
0e7b9925
AL		 2602 err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000);
2603 if (err)
2604 return err;
54d792f2
AL		 2605
2606 /* Port ATU control: disable limiting the number of
2607 * address database entries that this port is allowed
2608 * to use.
2609 */
0e7b9925
AL		 2610 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2611 0x0000);
54d792f2
AL		 2612 /* Priority Override: disable DA, SA and VTU priority
2613 * override.
2614 */
0e7b9925
AL		 2615 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2616 0x0000);
2617 if (err)
2618 return err;
54d792f2
AL		 2619
2620 /* Port Ethertype: use the Ethertype DSA Ethertype
2621 * value.
2622 */
2bbb33be 2623 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) {
0e7b9925
AL		 2624 err = mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE,
2625 ETH_P_EDSA);
2626 if (err)
2627 return err;
2bbb33be
AL		 2628 }
2629
54d792f2
AL		 2630 /* Tag Remap: use an identity 802.1p prio -> switch
2631 * prio mapping.
2632 */
0e7b9925
AL		 2633 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123,
2634 0x3210);
2635 if (err)
2636 return err;
54d792f2
AL		 2637
2638 /* Tag Remap 2: use an identity 802.1p prio -> switch
2639 * prio mapping.
2640 */
0e7b9925
AL		 2641 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567,
2642 0x7654);
2643 if (err)
2644 return err;
54d792f2
AL		 2645 }
2646
1bc261fa 2647 /* Rate Control: disable ingress rate limiting. */
fad09c73
VD		 2648 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2649 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
fad09c73 2650 mv88e6xxx_6320_family(chip)) {
0e7b9925
AL		 2651 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2652 0x0001);
2653 if (err)
2654 return err;
1bc261fa 2655 } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {
0e7b9925
AL		 2656 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2657 0x0000);
2658 if (err)
2659 return err;
54d792f2
AL		 2660 }
2661
366f0a0f
GR		 2662 /* Port Control 1: disable trunking, disable sending
2663 * learning messages to this port.
d827e88a 2664 */
0e7b9925
AL		 2665 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2666 if (err)
2667 return err;
d827e88a 2668
207afda1 2669 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2670 * database, and allow bidirectional communication between the
2671 * CPU and DSA port(s), and the other ports.
d827e88a 2672 */
b4e48c50 2673 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 2674 if (err)
2675 return err;
2db9ce1f 2676
0e7b9925
AL		 2677 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2678 if (err)
2679 return err;
d827e88a
GR		 2680
2681 /* Default VLAN ID and priority: don't set a default VLAN
2682 * ID, and set the default packet priority to zero.
2683 */
0e7b9925 2684 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
dbde9e66
AL		 2685}
2686
aa0938c6 2687static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3b4caa1b
VD		 2688{
2689 int err;
2690
a935c052 2691 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
3b4caa1b
VD		 2692 if (err)
2693 return err;
2694
a935c052 2695 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
3b4caa1b
VD		 2696 if (err)
2697 return err;
2698
a935c052
VD		 2699 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2700 if (err)
2701 return err;
2702
2703 return 0;
3b4caa1b
VD		 2704}
2705
acddbd21
VD		 2706static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2707 unsigned int msecs)
2708{
2709 const unsigned int coeff = chip->info->age_time_coeff;
2710 const unsigned int min = 0x01 * coeff;
2711 const unsigned int max = 0xff * coeff;
2712 u8 age_time;
2713 u16 val;
2714 int err;
2715
2716 if (msecs < min || msecs > max)
2717 return -ERANGE;
2718
2719 /* Round to nearest multiple of coeff */
2720 age_time = (msecs + coeff / 2) / coeff;
2721
a935c052 2722 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
acddbd21
VD		 2723 if (err)
2724 return err;
2725
2726 /* AgeTime is 11:4 bits */
2727 val &= ~0xff0;
2728 val |= age_time << 4;
2729
a935c052 2730 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
acddbd21
VD		 2731}
2732
2cfcd964
VD		 2733static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2734 unsigned int ageing_time)
2735{
04bed143 2736 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2737 int err;
2738
2739 mutex_lock(&chip->reg_lock);
2740 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2741 mutex_unlock(&chip->reg_lock);
2742
2743 return err;
2744}
2745
9729934c 2746static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2747{
fad09c73 2748 struct dsa_switch *ds = chip->ds;
b0745e87 2749 u32 upstream_port = dsa_upstream_port(ds);
119477bd 2750 u16 reg;
552238b5 2751 int err;
54d792f2 2752
119477bd
VD		 2753 /* Enable the PHY Polling Unit if present, don't discard any packets,
2754 * and mask all interrupt sources.
2755 */
dc30c35b
AL		 2756 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
2757 if (err < 0)
2758 return err;
2759
2760 reg &= ~GLOBAL_CONTROL_PPU_ENABLE;
fad09c73
VD		 2761 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2762 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
119477bd
VD		 2763 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2764
a935c052 2765 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
119477bd
VD		 2766 if (err)
2767 return err;
2768
b0745e87
VD		 2769 /* Configure the upstream port, and configure it as the port to which
2770 * ingress and egress and ARP monitor frames are to be sent.
2771 */
2772 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2773 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2774 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
a935c052 2775 err = mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
b0745e87
VD		 2776 if (err)
2777 return err;
2778
50484ff4 2779 /* Disable remote management, and set the switch's DSA device number. */
a935c052
VD		 2780 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2781 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2782 (ds->index & 0x1f));
50484ff4
VD		 2783 if (err)
2784 return err;
2785
acddbd21
VD		 2786 /* Clear all the VTU and STU entries */
2787 err = _mv88e6xxx_vtu_stu_flush(chip);
2788 if (err < 0)
2789 return err;
2790
54d792f2
AL		 2791 /* Set the default address aging time to 5 minutes, and
2792 * enable address learn messages to be sent to all message
2793 * ports.
2794 */
a935c052
VD		 2795 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2796 GLOBAL_ATU_CONTROL_LEARN2ALL);
48ace4ef 2797 if (err)
08a01261 2798 return err;
54d792f2 2799
acddbd21
VD		 2800 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2801 if (err)
9729934c
VD		 2802 return err;
2803
2804 /* Clear all ATU entries */
2805 err = _mv88e6xxx_atu_flush(chip, 0, true);
2806 if (err)
2807 return err;
2808
54d792f2 2809 /* Configure the IP ToS mapping registers. */
a935c052 2810 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2811 if (err)
08a01261 2812 return err;
a935c052 2813 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2814 if (err)
08a01261 2815 return err;
a935c052 2816 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2817 if (err)
08a01261 2818 return err;
a935c052 2819 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2820 if (err)
08a01261 2821 return err;
a935c052 2822 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2823 if (err)
08a01261 2824 return err;
a935c052 2825 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2826 if (err)
08a01261 2827 return err;
a935c052 2828 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2829 if (err)
08a01261 2830 return err;
a935c052 2831 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2832 if (err)
08a01261 2833 return err;
54d792f2
AL		 2834
2835 /* Configure the IEEE 802.1p priority mapping register. */
a935c052 2836 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2837 if (err)
08a01261 2838 return err;
54d792f2 2839
9729934c 2840 /* Clear the statistics counters for all ports */
a935c052
VD		 2841 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2842 GLOBAL_STATS_OP_FLUSH_ALL);
9729934c
VD		 2843 if (err)
2844 return err;
2845
2846 /* Wait for the flush to complete. */
2847 err = _mv88e6xxx_stats_wait(chip);
2848 if (err)
2849 return err;
2850
2851 return 0;
2852}
2853
f81ec90f 2854static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2855{
04bed143 2856 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2857 int err;
a1a6a4d1
VD		 2858 int i;
2859
fad09c73
VD		 2860 chip->ds = ds;
2861 ds->slave_mii_bus = chip->mdio_bus;
08a01261 2862
fad09c73 2863 mutex_lock(&chip->reg_lock);
08a01261 2864
9729934c 2865 /* Setup Switch Port Registers */
370b4ffb 2866 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
9729934c
VD		 2867 err = mv88e6xxx_setup_port(chip, i);
2868 if (err)
2869 goto unlock;
2870 }
2871
2872 /* Setup Switch Global 1 Registers */
2873 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2874 if (err)
2875 goto unlock;
2876
9729934c
VD		 2877 /* Setup Switch Global 2 Registers */
2878 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2879 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2880 if (err)
2881 goto unlock;
2882 }
08a01261 2883
6b17e864 2884unlock:
fad09c73 2885 mutex_unlock(&chip->reg_lock);
db687a56 2886
48ace4ef 2887 return err;
54d792f2
AL		 2888}
2889
3b4caa1b
VD		 2890static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2891{
04bed143 2892 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2893 int err;
2894
b073d4e2
VD		 2895 if (!chip->info->ops->set_switch_mac)
2896 return -EOPNOTSUPP;
3b4caa1b 2897
b073d4e2
VD		 2898 mutex_lock(&chip->reg_lock);
2899 err = chip->info->ops->set_switch_mac(chip, addr);
3b4caa1b
VD		 2900 mutex_unlock(&chip->reg_lock);
2901
2902 return err;
2903}
2904
e57e5e77 2905static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2906{
fad09c73 2907 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77
VD		 2908 u16 val;
2909 int err;
fd3a0ee4 2910
370b4ffb 2911 if (phy >= mv88e6xxx_num_ports(chip))
158bc065 2912 return 0xffff;
fd3a0ee4 2913
fad09c73 2914 mutex_lock(&chip->reg_lock);
e57e5e77 2915 err = mv88e6xxx_phy_read(chip, phy, reg, &val);
fad09c73 2916 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2917
2918 return err ? err : val;
fd3a0ee4
AL		 2919}
2920
e57e5e77 2921static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2922{
fad09c73 2923 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77 2924 int err;
fd3a0ee4 2925
370b4ffb 2926 if (phy >= mv88e6xxx_num_ports(chip))
158bc065 2927 return 0xffff;
fd3a0ee4 2928
fad09c73 2929 mutex_lock(&chip->reg_lock);
e57e5e77 2930 err = mv88e6xxx_phy_write(chip, phy, reg, val);
fad09c73 2931 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2932
2933 return err;
fd3a0ee4
AL		 2934}
2935
fad09c73 2936static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
b516d453
AL		 2937 struct device_node *np)
2938{
2939 static int index;
2940 struct mii_bus *bus;
2941 int err;
2942
b516d453 2943 if (np)
fad09c73 2944 chip->mdio_np = of_get_child_by_name(np, "mdio");
b516d453 2945
fad09c73 2946 bus = devm_mdiobus_alloc(chip->dev);
b516d453
AL		 2947 if (!bus)
2948 return -ENOMEM;
2949
fad09c73 2950 bus->priv = (void *)chip;
b516d453
AL		 2951 if (np) {
2952 bus->name = np->full_name;
2953 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2954 } else {
2955 bus->name = "mv88e6xxx SMI";
2956 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2957 }
2958
2959 bus->read = mv88e6xxx_mdio_read;
2960 bus->write = mv88e6xxx_mdio_write;
fad09c73 2961 bus->parent = chip->dev;
b516d453 2962
fad09c73
VD		 2963 if (chip->mdio_np)
2964 err = of_mdiobus_register(bus, chip->mdio_np);
b516d453
AL		 2965 else
2966 err = mdiobus_register(bus);
2967 if (err) {
fad09c73 2968 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
b516d453
AL		 2969 goto out;
2970 }
fad09c73 2971 chip->mdio_bus = bus;
b516d453
AL		 2972
2973 return 0;
2974
2975out:
fad09c73
VD		 2976 if (chip->mdio_np)
2977 of_node_put(chip->mdio_np);
b516d453
AL		 2978
2979 return err;
2980}
2981
fad09c73 2982static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 2983
2984{
fad09c73 2985 struct mii_bus *bus = chip->mdio_bus;
b516d453
AL		 2986
2987 mdiobus_unregister(bus);
2988
fad09c73
VD		 2989 if (chip->mdio_np)
2990 of_node_put(chip->mdio_np);
b516d453
AL		 2991}
2992
c22995c5
GR		 2993#ifdef CONFIG_NET_DSA_HWMON
2994
2995static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2996{
04bed143 2997 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c 2998 u16 val;
c22995c5 2999 int ret;
c22995c5
GR		 3000
3001 *temp = 0;
3002
fad09c73 3003 mutex_lock(&chip->reg_lock);
c22995c5 3004
9c93829c 3005 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
c22995c5
GR		 3006 if (ret < 0)
3007 goto error;
3008
3009 /* Enable temperature sensor */
9c93829c 3010 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
c22995c5
GR		 3011 if (ret < 0)
3012 goto error;
3013
9c93829c 3014 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
c22995c5
GR		 3015 if (ret < 0)
3016 goto error;
3017
3018 /* Wait for temperature to stabilize */
3019 usleep_range(10000, 12000);
3020
9c93829c
VD		 3021 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3022 if (ret < 0)
c22995c5 3023 goto error;
c22995c5
GR		 3024
3025 /* Disable temperature sensor */
9c93829c 3026 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
c22995c5
GR		 3027 if (ret < 0)
3028 goto error;
3029
3030 *temp = ((val & 0x1f) - 5) * 5;
3031
3032error:
9c93829c 3033 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
fad09c73 3034 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3035 return ret;
3036}
3037
3038static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3039{
04bed143 3040 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3041 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3042 u16 val;
c22995c5
GR		 3043 int ret;
3044
3045 *temp = 0;
3046
9c93829c
VD		 3047 mutex_lock(&chip->reg_lock);
3048 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3049 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3050 if (ret < 0)
3051 return ret;
3052
9c93829c 3053 *temp = (val & 0xff) - 25;
c22995c5
GR		 3054
3055 return 0;
3056}
3057
f81ec90f 3058static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
c22995c5 3059{
04bed143 3060 struct mv88e6xxx_chip *chip = ds->priv;
158bc065 3061
fad09c73 3062 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
6594f615
VD		 3063 return -EOPNOTSUPP;
3064
fad09c73 3065 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
c22995c5
GR		 3066 return mv88e63xx_get_temp(ds, temp);
3067
3068 return mv88e61xx_get_temp(ds, temp);
3069}
3070
f81ec90f 3071static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
c22995c5 3072{
04bed143 3073 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3074 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3075 u16 val;
c22995c5
GR		 3076 int ret;
3077
fad09c73 3078 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3079 return -EOPNOTSUPP;
3080
3081 *temp = 0;
3082
9c93829c
VD		 3083 mutex_lock(&chip->reg_lock);
3084 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3085 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3086 if (ret < 0)
3087 return ret;
3088
9c93829c 3089 *temp = (((val >> 8) & 0x1f) * 5) - 25;
c22995c5
GR		 3090
3091 return 0;
3092}
3093
f81ec90f 3094static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
c22995c5 3095{
04bed143 3096 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3097 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c
VD		 3098 u16 val;
3099 int err;
c22995c5 3100
fad09c73 3101 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3102 return -EOPNOTSUPP;
3103
9c93829c
VD		 3104 mutex_lock(&chip->reg_lock);
3105 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3106 if (err)
3107 goto unlock;
c22995c5 3108 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
9c93829c
VD		 3109 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3110 (val & 0xe0ff) | (temp << 8));
3111unlock:
3112 mutex_unlock(&chip->reg_lock);
3113
3114 return err;
c22995c5
GR		 3115}
3116
f81ec90f 3117static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
c22995c5 3118{
04bed143 3119 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3120 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3121 u16 val;
c22995c5
GR		 3122 int ret;
3123
fad09c73 3124 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3125 return -EOPNOTSUPP;
3126
3127 *alarm = false;
3128
9c93829c
VD		 3129 mutex_lock(&chip->reg_lock);
3130 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3131 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3132 if (ret < 0)
3133 return ret;
3134
9c93829c 3135 *alarm = !!(val & 0x40);
c22995c5
GR		 3136
3137 return 0;
3138}
3139#endif /* CONFIG_NET_DSA_HWMON */
3140
855b1932
VD		 3141static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3142{
04bed143 3143 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3144
3145 return chip->eeprom_len;
3146}
3147
855b1932
VD		 3148static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3149 struct ethtool_eeprom *eeprom, u8 *data)
3150{
04bed143 3151 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3152 int err;
3153
ee4dc2e7
VD		 3154 if (!chip->info->ops->get_eeprom)
3155 return -EOPNOTSUPP;
855b1932 3156
ee4dc2e7
VD		 3157 mutex_lock(&chip->reg_lock);
3158 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 3159 mutex_unlock(&chip->reg_lock);
3160
3161 if (err)
3162 return err;
3163
3164 eeprom->magic = 0xc3ec4951;
3165
3166 return 0;
3167}
3168
855b1932
VD		 3169static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3170 struct ethtool_eeprom *eeprom, u8 *data)
3171{
04bed143 3172 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3173 int err;
3174
ee4dc2e7
VD		 3175 if (!chip->info->ops->set_eeprom)
3176 return -EOPNOTSUPP;
3177
855b1932
VD		 3178 if (eeprom->magic != 0xc3ec4951)
3179 return -EINVAL;
3180
3181 mutex_lock(&chip->reg_lock);
ee4dc2e7 3182 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 3183 mutex_unlock(&chip->reg_lock);
3184
3185 return err;
3186}
3187
b3469dd8 3188static const struct mv88e6xxx_ops mv88e6085_ops = {
b073d4e2 3189 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3190 .phy_read = mv88e6xxx_phy_ppu_read,
3191 .phy_write = mv88e6xxx_phy_ppu_write,
3192};
3193
3194static const struct mv88e6xxx_ops mv88e6095_ops = {
b073d4e2 3195 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3196 .phy_read = mv88e6xxx_phy_ppu_read,
3197 .phy_write = mv88e6xxx_phy_ppu_write,
3198};
3199
3200static const struct mv88e6xxx_ops mv88e6123_ops = {
b073d4e2 3201 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3202 .phy_read = mv88e6xxx_read,
3203 .phy_write = mv88e6xxx_write,
3204};
3205
3206static const struct mv88e6xxx_ops mv88e6131_ops = {
b073d4e2 3207 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3208 .phy_read = mv88e6xxx_phy_ppu_read,
3209 .phy_write = mv88e6xxx_phy_ppu_write,
3210};
3211
3212static const struct mv88e6xxx_ops mv88e6161_ops = {
b073d4e2 3213 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3214 .phy_read = mv88e6xxx_read,
3215 .phy_write = mv88e6xxx_write,
3216};
3217
3218static const struct mv88e6xxx_ops mv88e6165_ops = {
b073d4e2 3219 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3220 .phy_read = mv88e6xxx_read,
3221 .phy_write = mv88e6xxx_write,
3222};
3223
3224static const struct mv88e6xxx_ops mv88e6171_ops = {
b073d4e2 3225 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3226 .phy_read = mv88e6xxx_g2_smi_phy_read,
3227 .phy_write = mv88e6xxx_g2_smi_phy_write,
3228};
3229
3230static const struct mv88e6xxx_ops mv88e6172_ops = {
ee4dc2e7
VD		 3231 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3232 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3233 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3234 .phy_read = mv88e6xxx_g2_smi_phy_read,
3235 .phy_write = mv88e6xxx_g2_smi_phy_write,
3236};
3237
3238static const struct mv88e6xxx_ops mv88e6175_ops = {
b073d4e2 3239 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3240 .phy_read = mv88e6xxx_g2_smi_phy_read,
3241 .phy_write = mv88e6xxx_g2_smi_phy_write,
3242};
3243
3244static const struct mv88e6xxx_ops mv88e6176_ops = {
ee4dc2e7
VD		 3245 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3246 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3247 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3248 .phy_read = mv88e6xxx_g2_smi_phy_read,
3249 .phy_write = mv88e6xxx_g2_smi_phy_write,
3250};
3251
3252static const struct mv88e6xxx_ops mv88e6185_ops = {
b073d4e2 3253 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3254 .phy_read = mv88e6xxx_phy_ppu_read,
3255 .phy_write = mv88e6xxx_phy_ppu_write,
3256};
3257
3258static const struct mv88e6xxx_ops mv88e6240_ops = {
ee4dc2e7
VD		 3259 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3260 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3261 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3262 .phy_read = mv88e6xxx_g2_smi_phy_read,
3263 .phy_write = mv88e6xxx_g2_smi_phy_write,
3264};
3265
3266static const struct mv88e6xxx_ops mv88e6320_ops = {
ee4dc2e7
VD		 3267 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3268 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3269 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3270 .phy_read = mv88e6xxx_g2_smi_phy_read,
3271 .phy_write = mv88e6xxx_g2_smi_phy_write,
3272};
3273
3274static const struct mv88e6xxx_ops mv88e6321_ops = {
ee4dc2e7
VD		 3275 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3276 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3277 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3278 .phy_read = mv88e6xxx_g2_smi_phy_read,
3279 .phy_write = mv88e6xxx_g2_smi_phy_write,
3280};
3281
3282static const struct mv88e6xxx_ops mv88e6350_ops = {
b073d4e2 3283 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3284 .phy_read = mv88e6xxx_g2_smi_phy_read,
3285 .phy_write = mv88e6xxx_g2_smi_phy_write,
3286};
3287
3288static const struct mv88e6xxx_ops mv88e6351_ops = {
b073d4e2 3289 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3290 .phy_read = mv88e6xxx_g2_smi_phy_read,
3291 .phy_write = mv88e6xxx_g2_smi_phy_write,
3292};
3293
3294static const struct mv88e6xxx_ops mv88e6352_ops = {
ee4dc2e7
VD		 3295 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3296 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3297 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3298 .phy_read = mv88e6xxx_g2_smi_phy_read,
3299 .phy_write = mv88e6xxx_g2_smi_phy_write,
3300};
3301
f81ec90f
VD		 3302static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3303 [MV88E6085] = {
3304 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3305 .family = MV88E6XXX_FAMILY_6097,
3306 .name = "Marvell 88E6085",
3307 .num_databases = 4096,
3308 .num_ports = 10,
9dddd478 3309 .port_base_addr = 0x10,
a935c052 3310 .global1_addr = 0x1b,
acddbd21 3311 .age_time_coeff = 15000,
dc30c35b 3312 .g1_irqs = 8,
f81ec90f 3313 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
b3469dd8 3314 .ops = &mv88e6085_ops,
f81ec90f
VD		 3315 },
3316
3317 [MV88E6095] = {
3318 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3319 .family = MV88E6XXX_FAMILY_6095,
3320 .name = "Marvell 88E6095/88E6095F",
3321 .num_databases = 256,
3322 .num_ports = 11,
9dddd478 3323 .port_base_addr = 0x10,
a935c052 3324 .global1_addr = 0x1b,
acddbd21 3325 .age_time_coeff = 15000,
dc30c35b 3326 .g1_irqs = 8,
f81ec90f 3327 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
b3469dd8 3328 .ops = &mv88e6095_ops,
f81ec90f
VD		 3329 },
3330
3331 [MV88E6123] = {
3332 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3333 .family = MV88E6XXX_FAMILY_6165,
3334 .name = "Marvell 88E6123",
3335 .num_databases = 4096,
3336 .num_ports = 3,
9dddd478 3337 .port_base_addr = 0x10,
a935c052 3338 .global1_addr = 0x1b,
acddbd21 3339 .age_time_coeff = 15000,
dc30c35b 3340 .g1_irqs = 9,
f81ec90f 3341 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3342 .ops = &mv88e6123_ops,
f81ec90f
VD		 3343 },
3344
3345 [MV88E6131] = {
3346 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3347 .family = MV88E6XXX_FAMILY_6185,
3348 .name = "Marvell 88E6131",
3349 .num_databases = 256,
3350 .num_ports = 8,
9dddd478 3351 .port_base_addr = 0x10,
a935c052 3352 .global1_addr = 0x1b,
acddbd21 3353 .age_time_coeff = 15000,
dc30c35b 3354 .g1_irqs = 9,
f81ec90f 3355 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3356 .ops = &mv88e6131_ops,
f81ec90f
VD		 3357 },
3358
3359 [MV88E6161] = {
3360 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3361 .family = MV88E6XXX_FAMILY_6165,
3362 .name = "Marvell 88E6161",
3363 .num_databases = 4096,
3364 .num_ports = 6,
9dddd478 3365 .port_base_addr = 0x10,
a935c052 3366 .global1_addr = 0x1b,
acddbd21 3367 .age_time_coeff = 15000,
dc30c35b 3368 .g1_irqs = 9,
f81ec90f 3369 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3370 .ops = &mv88e6161_ops,
f81ec90f
VD		 3371 },
3372
3373 [MV88E6165] = {
3374 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3375 .family = MV88E6XXX_FAMILY_6165,
3376 .name = "Marvell 88E6165",
3377 .num_databases = 4096,
3378 .num_ports = 6,
9dddd478 3379 .port_base_addr = 0x10,
a935c052 3380 .global1_addr = 0x1b,
acddbd21 3381 .age_time_coeff = 15000,
dc30c35b 3382 .g1_irqs = 9,
f81ec90f 3383 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3384 .ops = &mv88e6165_ops,
f81ec90f
VD		 3385 },
3386
3387 [MV88E6171] = {
3388 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3389 .family = MV88E6XXX_FAMILY_6351,
3390 .name = "Marvell 88E6171",
3391 .num_databases = 4096,
3392 .num_ports = 7,
9dddd478 3393 .port_base_addr = 0x10,
a935c052 3394 .global1_addr = 0x1b,
acddbd21 3395 .age_time_coeff = 15000,
dc30c35b 3396 .g1_irqs = 9,
f81ec90f 3397 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3398 .ops = &mv88e6171_ops,
f81ec90f
VD		 3399 },
3400
3401 [MV88E6172] = {
3402 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3403 .family = MV88E6XXX_FAMILY_6352,
3404 .name = "Marvell 88E6172",
3405 .num_databases = 4096,
3406 .num_ports = 7,
9dddd478 3407 .port_base_addr = 0x10,
a935c052 3408 .global1_addr = 0x1b,
acddbd21 3409 .age_time_coeff = 15000,
dc30c35b 3410 .g1_irqs = 9,
f81ec90f 3411 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3412 .ops = &mv88e6172_ops,
f81ec90f
VD		 3413 },
3414
3415 [MV88E6175] = {
3416 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3417 .family = MV88E6XXX_FAMILY_6351,
3418 .name = "Marvell 88E6175",
3419 .num_databases = 4096,
3420 .num_ports = 7,
9dddd478 3421 .port_base_addr = 0x10,
a935c052 3422 .global1_addr = 0x1b,
acddbd21 3423 .age_time_coeff = 15000,
dc30c35b 3424 .g1_irqs = 9,
f81ec90f 3425 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3426 .ops = &mv88e6175_ops,
f81ec90f
VD		 3427 },
3428
3429 [MV88E6176] = {
3430 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3431 .family = MV88E6XXX_FAMILY_6352,
3432 .name = "Marvell 88E6176",
3433 .num_databases = 4096,
3434 .num_ports = 7,
9dddd478 3435 .port_base_addr = 0x10,
a935c052 3436 .global1_addr = 0x1b,
acddbd21 3437 .age_time_coeff = 15000,
dc30c35b 3438 .g1_irqs = 9,
f81ec90f 3439 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3440 .ops = &mv88e6176_ops,
f81ec90f
VD		 3441 },
3442
3443 [MV88E6185] = {
3444 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3445 .family = MV88E6XXX_FAMILY_6185,
3446 .name = "Marvell 88E6185",
3447 .num_databases = 256,
3448 .num_ports = 10,
9dddd478 3449 .port_base_addr = 0x10,
a935c052 3450 .global1_addr = 0x1b,
acddbd21 3451 .age_time_coeff = 15000,
dc30c35b 3452 .g1_irqs = 8,
f81ec90f 3453 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3454 .ops = &mv88e6185_ops,
f81ec90f
VD		 3455 },
3456
3457 [MV88E6240] = {
3458 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3459 .family = MV88E6XXX_FAMILY_6352,
3460 .name = "Marvell 88E6240",
3461 .num_databases = 4096,
3462 .num_ports = 7,
9dddd478 3463 .port_base_addr = 0x10,
a935c052 3464 .global1_addr = 0x1b,
acddbd21 3465 .age_time_coeff = 15000,
dc30c35b 3466 .g1_irqs = 9,
f81ec90f 3467 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3468 .ops = &mv88e6240_ops,
f81ec90f
VD		 3469 },
3470
3471 [MV88E6320] = {
3472 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3473 .family = MV88E6XXX_FAMILY_6320,
3474 .name = "Marvell 88E6320",
3475 .num_databases = 4096,
3476 .num_ports = 7,
9dddd478 3477 .port_base_addr = 0x10,
a935c052 3478 .global1_addr = 0x1b,
acddbd21 3479 .age_time_coeff = 15000,
dc30c35b 3480 .g1_irqs = 8,
f81ec90f 3481 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3482 .ops = &mv88e6320_ops,
f81ec90f
VD		 3483 },
3484
3485 [MV88E6321] = {
3486 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3487 .family = MV88E6XXX_FAMILY_6320,
3488 .name = "Marvell 88E6321",
3489 .num_databases = 4096,
3490 .num_ports = 7,
9dddd478 3491 .port_base_addr = 0x10,
a935c052 3492 .global1_addr = 0x1b,
acddbd21 3493 .age_time_coeff = 15000,
dc30c35b 3494 .g1_irqs = 8,
f81ec90f 3495 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3496 .ops = &mv88e6321_ops,
f81ec90f
VD		 3497 },
3498
3499 [MV88E6350] = {
3500 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3501 .family = MV88E6XXX_FAMILY_6351,
3502 .name = "Marvell 88E6350",
3503 .num_databases = 4096,
3504 .num_ports = 7,
9dddd478 3505 .port_base_addr = 0x10,
a935c052 3506 .global1_addr = 0x1b,
acddbd21 3507 .age_time_coeff = 15000,
dc30c35b 3508 .g1_irqs = 9,
f81ec90f 3509 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3510 .ops = &mv88e6350_ops,
f81ec90f
VD		 3511 },
3512
3513 [MV88E6351] = {
3514 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3515 .family = MV88E6XXX_FAMILY_6351,
3516 .name = "Marvell 88E6351",
3517 .num_databases = 4096,
3518 .num_ports = 7,
9dddd478 3519 .port_base_addr = 0x10,
a935c052 3520 .global1_addr = 0x1b,
acddbd21 3521 .age_time_coeff = 15000,
dc30c35b 3522 .g1_irqs = 9,
f81ec90f 3523 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3524 .ops = &mv88e6351_ops,
f81ec90f
VD		 3525 },
3526
3527 [MV88E6352] = {
3528 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3529 .family = MV88E6XXX_FAMILY_6352,
3530 .name = "Marvell 88E6352",
3531 .num_databases = 4096,
3532 .num_ports = 7,
9dddd478 3533 .port_base_addr = 0x10,
a935c052 3534 .global1_addr = 0x1b,
acddbd21 3535 .age_time_coeff = 15000,
dc30c35b 3536 .g1_irqs = 9,
f81ec90f 3537 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3538 .ops = &mv88e6352_ops,
f81ec90f
VD		 3539 },
3540};
3541
5f7c0367 3542static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3543{
a439c061 3544 int i;
b9b37713 3545
5f7c0367
VD		 3546 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3547 if (mv88e6xxx_table[i].prod_num == prod_num)
3548 return &mv88e6xxx_table[i];
b9b37713 3549
b9b37713
VD		 3550 return NULL;
3551}
3552
fad09c73 3553static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3554{
3555 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3556 unsigned int prod_num, rev;
3557 u16 id;
3558 int err;
bc46a3d5 3559
8f6345b2
VD		 3560 mutex_lock(&chip->reg_lock);
3561 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3562 mutex_unlock(&chip->reg_lock);
3563 if (err)
3564 return err;
bc46a3d5
VD		 3565
3566 prod_num = (id & 0xfff0) >> 4;
3567 rev = id & 0x000f;
3568
3569 info = mv88e6xxx_lookup_info(prod_num);
3570 if (!info)
3571 return -ENODEV;
3572
caac8545 3573 /* Update the compatible info with the probed one */
fad09c73 3574 chip->info = info;
bc46a3d5 3575
ca070c10
VD		 3576 err = mv88e6xxx_g2_require(chip);
3577 if (err)
3578 return err;
3579
fad09c73
VD		 3580 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3581 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 3582
3583 return 0;
3584}
3585
fad09c73 3586static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 3587{
fad09c73 3588 struct mv88e6xxx_chip *chip;
469d729f 3589
fad09c73
VD		 3590 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3591 if (!chip)
469d729f
VD		 3592 return NULL;
3593
fad09c73 3594 chip->dev = dev;
469d729f 3595
fad09c73 3596 mutex_init(&chip->reg_lock);
469d729f 3597
fad09c73 3598 return chip;
469d729f
VD		 3599}
3600
e57e5e77
VD		 3601static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3602{
b3469dd8 3603 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
e57e5e77 3604 mv88e6xxx_ppu_state_init(chip);
e57e5e77
VD		 3605}
3606
930188ce
AL		 3607static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
3608{
b3469dd8 3609 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
930188ce 3610 mv88e6xxx_ppu_state_destroy(chip);
930188ce
AL		 3611}
3612
fad09c73 3613static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 3614 struct mii_bus *bus, int sw_addr)
3615{
3616 /* ADDR[0] pin is unavailable externally and considered zero */
3617 if (sw_addr & 0x1)
3618 return -EINVAL;
3619
914b32f6 3620 if (sw_addr == 0)
fad09c73 3621 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 3622 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 3623 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 3624 else
3625 return -EINVAL;
3626
fad09c73
VD		 3627 chip->bus = bus;
3628 chip->sw_addr = sw_addr;
4a70c4ab
VD		 3629
3630 return 0;
3631}
3632
7b314362
AL		 3633static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3634{
04bed143 3635 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be
AL		 3636
3637 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
3638 return DSA_TAG_PROTO_EDSA;
3639
3640 return DSA_TAG_PROTO_DSA;
7b314362
AL		 3641}
3642
fcdce7d0
AL		 3643static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3644 struct device *host_dev, int sw_addr,
3645 void **priv)
a77d43f1 3646{
fad09c73 3647 struct mv88e6xxx_chip *chip;
a439c061 3648 struct mii_bus *bus;
b516d453 3649 int err;
a77d43f1 3650
a439c061 3651 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3652 if (!bus)
3653 return NULL;
3654
fad09c73
VD		 3655 chip = mv88e6xxx_alloc_chip(dsa_dev);
3656 if (!chip)
469d729f
VD		 3657 return NULL;
3658
caac8545 3659 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 3660 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 3661
fad09c73 3662 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 3663 if (err)
3664 goto free;
3665
fad09c73 3666 err = mv88e6xxx_detect(chip);
bc46a3d5 3667 if (err)
469d729f 3668 goto free;
a439c061 3669
dc30c35b
AL		 3670 mutex_lock(&chip->reg_lock);
3671 err = mv88e6xxx_switch_reset(chip);
3672 mutex_unlock(&chip->reg_lock);
3673 if (err)
3674 goto free;
3675
e57e5e77
VD		 3676 mv88e6xxx_phy_init(chip);
3677
fad09c73 3678 err = mv88e6xxx_mdio_register(chip, NULL);
b516d453 3679 if (err)
469d729f 3680 goto free;
b516d453 3681
fad09c73 3682 *priv = chip;
a439c061 3683
fad09c73 3684 return chip->info->name;
469d729f 3685free:
fad09c73 3686 devm_kfree(dsa_dev, chip);
469d729f
VD		 3687
3688 return NULL;
a77d43f1
AL		 3689}
3690
7df8fbdd
VD		 3691static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3692 const struct switchdev_obj_port_mdb *mdb,
3693 struct switchdev_trans *trans)
3694{
3695 /* We don't need any dynamic resource from the kernel (yet),
3696 * so skip the prepare phase.
3697 */
3698
3699 return 0;
3700}
3701
3702static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3703 const struct switchdev_obj_port_mdb *mdb,
3704 struct switchdev_trans *trans)
3705{
04bed143 3706 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3707
3708 mutex_lock(&chip->reg_lock);
3709 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3710 GLOBAL_ATU_DATA_STATE_MC_STATIC))
3711 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
3712 mutex_unlock(&chip->reg_lock);
3713}
3714
3715static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3716 const struct switchdev_obj_port_mdb *mdb)
3717{
04bed143 3718 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3719 int err;
3720
3721 mutex_lock(&chip->reg_lock);
3722 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3723 GLOBAL_ATU_DATA_STATE_UNUSED);
3724 mutex_unlock(&chip->reg_lock);
3725
3726 return err;
3727}
3728
3729static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
3730 struct switchdev_obj_port_mdb *mdb,
3731 int (*cb)(struct switchdev_obj *obj))
3732{
04bed143 3733 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3734 int err;
3735
3736 mutex_lock(&chip->reg_lock);
3737 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
3738 mutex_unlock(&chip->reg_lock);
3739
3740 return err;
3741}
3742
9d490b4e 3743static struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 3744 .probe = mv88e6xxx_drv_probe,
7b314362 3745 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 3746 .setup = mv88e6xxx_setup,
3747 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 3748 .adjust_link = mv88e6xxx_adjust_link,
3749 .get_strings = mv88e6xxx_get_strings,
3750 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3751 .get_sset_count = mv88e6xxx_get_sset_count,
3752 .set_eee = mv88e6xxx_set_eee,
3753 .get_eee = mv88e6xxx_get_eee,
3754#ifdef CONFIG_NET_DSA_HWMON
3755 .get_temp = mv88e6xxx_get_temp,
3756 .get_temp_limit = mv88e6xxx_get_temp_limit,
3757 .set_temp_limit = mv88e6xxx_set_temp_limit,
3758 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
3759#endif
f8cd8753 3760 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 3761 .get_eeprom = mv88e6xxx_get_eeprom,
3762 .set_eeprom = mv88e6xxx_set_eeprom,
3763 .get_regs_len = mv88e6xxx_get_regs_len,
3764 .get_regs = mv88e6xxx_get_regs,
2cfcd964 3765 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 3766 .port_bridge_join = mv88e6xxx_port_bridge_join,
3767 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3768 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 3769 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 3770 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3771 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3772 .port_vlan_add = mv88e6xxx_port_vlan_add,
3773 .port_vlan_del = mv88e6xxx_port_vlan_del,
3774 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3775 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3776 .port_fdb_add = mv88e6xxx_port_fdb_add,
3777 .port_fdb_del = mv88e6xxx_port_fdb_del,
3778 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 3779 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3780 .port_mdb_add = mv88e6xxx_port_mdb_add,
3781 .port_mdb_del = mv88e6xxx_port_mdb_del,
3782 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
f81ec90f
VD		 3783};
3784
fad09c73 3785static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
b7e66a5f
VD		 3786 struct device_node *np)
3787{
fad09c73 3788 struct device *dev = chip->dev;
b7e66a5f
VD		 3789 struct dsa_switch *ds;
3790
3791 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3792 if (!ds)
3793 return -ENOMEM;
3794
3795 ds->dev = dev;
fad09c73 3796 ds->priv = chip;
9d490b4e 3797 ds->ops = &mv88e6xxx_switch_ops;
b7e66a5f
VD		 3798
3799 dev_set_drvdata(dev, ds);
3800
3801 return dsa_register_switch(ds, np);
3802}
3803
fad09c73 3804static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 3805{
fad09c73 3806 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 3807}
3808
57d32310 3809static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 3810{
14c7b3c3 3811 struct device *dev = &mdiodev->dev;
f8cd8753 3812 struct device_node *np = dev->of_node;
caac8545 3813 const struct mv88e6xxx_info *compat_info;
fad09c73 3814 struct mv88e6xxx_chip *chip;
f8cd8753 3815 u32 eeprom_len;
52638f71 3816 int err;
14c7b3c3 3817
caac8545
VD		 3818 compat_info = of_device_get_match_data(dev);
3819 if (!compat_info)
3820 return -EINVAL;
3821
fad09c73
VD		 3822 chip = mv88e6xxx_alloc_chip(dev);
3823 if (!chip)
14c7b3c3
AL		 3824 return -ENOMEM;
3825
fad09c73 3826 chip->info = compat_info;
caac8545 3827
fad09c73 3828 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 3829 if (err)
3830 return err;
14c7b3c3 3831
fad09c73 3832 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 3833 if (err)
3834 return err;
14c7b3c3 3835
e57e5e77
VD		 3836 mv88e6xxx_phy_init(chip);
3837
fad09c73
VD		 3838 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
3839 if (IS_ERR(chip->reset))
3840 return PTR_ERR(chip->reset);
52638f71 3841
ee4dc2e7 3842 if (chip->info->ops->get_eeprom &&
f8cd8753 3843 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 3844 chip->eeprom_len = eeprom_len;
f8cd8753 3845
dc30c35b
AL		 3846 mutex_lock(&chip->reg_lock);
3847 err = mv88e6xxx_switch_reset(chip);
3848 mutex_unlock(&chip->reg_lock);
3849 if (err)
3850 goto out;
3851
3852 chip->irq = of_irq_get(np, 0);
3853 if (chip->irq == -EPROBE_DEFER) {
3854 err = chip->irq;
3855 goto out;
3856 }
3857
3858 if (chip->irq > 0) {
3859 /* Has to be performed before the MDIO bus is created,
3860 * because the PHYs will link there interrupts to these
3861 * interrupt controllers
3862 */
3863 mutex_lock(&chip->reg_lock);
3864 err = mv88e6xxx_g1_irq_setup(chip);
3865 mutex_unlock(&chip->reg_lock);
3866
3867 if (err)
3868 goto out;
3869
3870 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
3871 err = mv88e6xxx_g2_irq_setup(chip);
3872 if (err)
3873 goto out_g1_irq;
3874 }
3875 }
3876
fad09c73 3877 err = mv88e6xxx_mdio_register(chip, np);
b516d453 3878 if (err)
dc30c35b 3879 goto out_g2_irq;
b516d453 3880
fad09c73 3881 err = mv88e6xxx_register_switch(chip, np);
dc30c35b
AL		 3882 if (err)
3883 goto out_mdio;
83c0afae 3884
98e67308 3885 return 0;
dc30c35b
AL		 3886
3887out_mdio:
3888 mv88e6xxx_mdio_unregister(chip);
3889out_g2_irq:
3890 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
3891 mv88e6xxx_g2_irq_free(chip);
3892out_g1_irq:
3893 mv88e6xxx_g1_irq_free(chip);
3894out:
3895 return err;
98e67308 3896}
14c7b3c3
AL		 3897
3898static void mv88e6xxx_remove(struct mdio_device *mdiodev)
3899{
3900 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 3901 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 3902
930188ce 3903 mv88e6xxx_phy_destroy(chip);
fad09c73
VD		 3904 mv88e6xxx_unregister_switch(chip);
3905 mv88e6xxx_mdio_unregister(chip);
dc30c35b
AL		 3906
3907 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
3908 mv88e6xxx_g2_irq_free(chip);
3909 mv88e6xxx_g1_irq_free(chip);
14c7b3c3
AL		 3910}
3911
3912static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 3913 {
3914 .compatible = "marvell,mv88e6085",
3915 .data = &mv88e6xxx_table[MV88E6085],
3916 },
14c7b3c3
AL		 3917 { /* sentinel */ },
3918};
3919
3920MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
3921
3922static struct mdio_driver mv88e6xxx_driver = {
3923 .probe = mv88e6xxx_probe,
3924 .remove = mv88e6xxx_remove,
3925 .mdiodrv.driver = {
3926 .name = "mv88e6085",
3927 .of_match_table = mv88e6xxx_of_match,
3928 },
3929};
3930
3931static int __init mv88e6xxx_init(void)
3932{
9d490b4e 3933 register_switch_driver(&mv88e6xxx_switch_ops);
14c7b3c3
AL		 3934 return mdio_driver_register(&mv88e6xxx_driver);
3935}
98e67308
BH		 3936module_init(mv88e6xxx_init);
3937
3938static void __exit mv88e6xxx_cleanup(void)
3939{
14c7b3c3 3940 mdio_driver_unregister(&mv88e6xxx_driver);
9d490b4e 3941 unregister_switch_driver(&mv88e6xxx_switch_ops);
98e67308
BH		 3942}
3943module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 3944
3945MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3946MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3947MODULE_LICENSE("GPL");
ubuntu-bionic-kernel mirror