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net: dsa: Allow the DSA driver to indicate the tag protocol
[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
19b2f97e 21#include <linux/jiffies.h>
91da11f8 22#include <linux/list.h>
14c7b3c3 23#include <linux/mdio.h>
2bbba277 24#include <linux/module.h>
caac8545 25#include <linux/of_device.h>
b516d453 26#include <linux/of_mdio.h>
91da11f8 27#include <linux/netdevice.h>
c8c1b39a 28#include <linux/gpio/consumer.h>
91da11f8 29#include <linux/phy.h>
c8f0b869 30#include <net/dsa.h>
1f36faf2 31#include <net/switchdev.h>
91da11f8
LB		 32#include "mv88e6xxx.h"
33
fad09c73 34static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 35{
fad09c73
VD		 36 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
37 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 38 dump_stack();
39 }
40}
41
914b32f6
VD		 42/* The switch ADDR[4:1] configuration pins define the chip SMI device address
43 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
44 *
45 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
46 * is the only device connected to the SMI master. In this mode it responds to
47 * all 32 possible SMI addresses, and thus maps directly the internal devices.
48 *
49 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
50 * multiple devices to share the SMI interface. In this mode it responds to only
51 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 52 */
914b32f6 53
fad09c73 54static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 55 int addr, int reg, u16 *val)
56{
fad09c73 57 if (!chip->smi_ops)
914b32f6
VD		 58 return -EOPNOTSUPP;
59
fad09c73 60 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 61}
62
fad09c73 63static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 64 int addr, int reg, u16 val)
65{
fad09c73 66 if (!chip->smi_ops)
914b32f6
VD		 67 return -EOPNOTSUPP;
68
fad09c73 69 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 70}
71
fad09c73 72static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 73 int addr, int reg, u16 *val)
74{
75 int ret;
76
fad09c73 77 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 78 if (ret < 0)
79 return ret;
80
81 *val = ret & 0xffff;
82
83 return 0;
84}
85
fad09c73 86static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 87 int addr, int reg, u16 val)
88{
89 int ret;
90
fad09c73 91 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 92 if (ret < 0)
93 return ret;
94
95 return 0;
96}
97
98static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
99 .read = mv88e6xxx_smi_single_chip_read,
100 .write = mv88e6xxx_smi_single_chip_write,
101};
102
fad09c73 103static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 104{
105 int ret;
106 int i;
107
108 for (i = 0; i < 16; i++) {
fad09c73 109 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 110 if (ret < 0)
111 return ret;
112
cca8b133 113 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 114 return 0;
115 }
116
117 return -ETIMEDOUT;
118}
119
fad09c73 120static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 121 int addr, int reg, u16 *val)
91da11f8
LB		 122{
123 int ret;
124
3675c8d7 125 /* Wait for the bus to become free. */
fad09c73 126 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 127 if (ret < 0)
128 return ret;
129
3675c8d7 130 /* Transmit the read command. */
fad09c73 131 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 132 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 133 if (ret < 0)
134 return ret;
135
3675c8d7 136 /* Wait for the read command to complete. */
fad09c73 137 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 138 if (ret < 0)
139 return ret;
140
3675c8d7 141 /* Read the data. */
fad09c73 142 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 143 if (ret < 0)
144 return ret;
145
914b32f6 146 *val = ret & 0xffff;
91da11f8 147
914b32f6 148 return 0;
8d6d09e7
GR		 149}
150
fad09c73 151static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 152 int addr, int reg, u16 val)
91da11f8
LB		 153{
154 int ret;
155
3675c8d7 156 /* Wait for the bus to become free. */
fad09c73 157 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 158 if (ret < 0)
159 return ret;
160
3675c8d7 161 /* Transmit the data to write. */
fad09c73 162 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 163 if (ret < 0)
164 return ret;
165
3675c8d7 166 /* Transmit the write command. */
fad09c73 167 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 168 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 169 if (ret < 0)
170 return ret;
171
3675c8d7 172 /* Wait for the write command to complete. */
fad09c73 173 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 174 if (ret < 0)
175 return ret;
176
177 return 0;
178}
179
914b32f6
VD		 180static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
181 .read = mv88e6xxx_smi_multi_chip_read,
182 .write = mv88e6xxx_smi_multi_chip_write,
183};
184
fad09c73 185static int mv88e6xxx_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 186 int addr, int reg, u16 *val)
187{
188 int err;
189
fad09c73 190 assert_reg_lock(chip);
914b32f6 191
fad09c73 192 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 193 if (err)
194 return err;
195
fad09c73 196 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 197 addr, reg, *val);
198
199 return 0;
200}
201
fad09c73 202static int mv88e6xxx_write(struct mv88e6xxx_chip *chip,
914b32f6 203 int addr, int reg, u16 val)
91da11f8 204{
914b32f6
VD		 205 int err;
206
fad09c73 207 assert_reg_lock(chip);
91da11f8 208
fad09c73 209 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 210 if (err)
211 return err;
212
fad09c73 213 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 214 addr, reg, val);
215
914b32f6
VD		 216 return 0;
217}
218
e57e5e77
VD		 219static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
220 int reg, u16 *val)
221{
222 int addr = phy; /* PHY devices addresses start at 0x0 */
223
224 if (!chip->phy_ops)
225 return -EOPNOTSUPP;
226
227 return chip->phy_ops->read(chip, addr, reg, val);
228}
229
230static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
231 int reg, u16 val)
232{
233 int addr = phy; /* PHY devices addresses start at 0x0 */
234
235 if (!chip->phy_ops)
236 return -EOPNOTSUPP;
237
238 return chip->phy_ops->write(chip, addr, reg, val);
239}
240
09cb7dfd
VD		 241static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
242{
243 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
244 return -EOPNOTSUPP;
245
246 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
247}
248
249static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
250{
251 int err;
252
253 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
254 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
255 if (unlikely(err)) {
256 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
257 phy, err);
258 }
259}
260
261static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
262 u8 page, int reg, u16 *val)
263{
264 int err;
265
266 /* There is no paging for registers 22 */
267 if (reg == PHY_PAGE)
268 return -EINVAL;
269
270 err = mv88e6xxx_phy_page_get(chip, phy, page);
271 if (!err) {
272 err = mv88e6xxx_phy_read(chip, phy, reg, val);
273 mv88e6xxx_phy_page_put(chip, phy);
274 }
275
276 return err;
277}
278
279static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
280 u8 page, int reg, u16 val)
281{
282 int err;
283
284 /* There is no paging for registers 22 */
285 if (reg == PHY_PAGE)
286 return -EINVAL;
287
288 err = mv88e6xxx_phy_page_get(chip, phy, page);
289 if (!err) {
290 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
291 mv88e6xxx_phy_page_put(chip, phy);
292 }
293
294 return err;
295}
296
297static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
298{
299 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
300 reg, val);
301}
302
303static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
304{
305 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
306 reg, val);
307}
308
2d79af6e
VD		 309static int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg,
310 u16 mask)
311{
6441e669 312 int i;
2d79af6e 313
6441e669 314 for (i = 0; i < 16; i++) {
2d79af6e
VD		 315 u16 val;
316 int err;
317
318 err = mv88e6xxx_read(chip, addr, reg, &val);
319 if (err)
320 return err;
321
322 if (!(val & mask))
323 return 0;
324
325 usleep_range(1000, 2000);
326 }
327
30853553 328 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 329 return -ETIMEDOUT;
330}
331
f22ab641
VD		 332/* Indirect write to single pointer-data register with an Update bit */
333static int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
334 u16 update)
335{
336 u16 val;
0f02b4f7 337 int err;
f22ab641
VD		 338
339 /* Wait until the previous operation is completed */
0f02b4f7
AL		 340 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
341 if (err)
342 return err;
f22ab641
VD		 343
344 /* Set the Update bit to trigger a write operation */
345 val = BIT(15) | update;
346
347 return mv88e6xxx_write(chip, addr, reg, val);
348}
349
fad09c73 350static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
914b32f6
VD		 351{
352 u16 val;
353 int err;
354
fad09c73 355 err = mv88e6xxx_read(chip, addr, reg, &val);
914b32f6
VD		 356 if (err)
357 return err;
358
359 return val;
360}
361
fad09c73 362static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
914b32f6
VD		 363 int reg, u16 val)
364{
fad09c73 365 return mv88e6xxx_write(chip, addr, reg, val);
8d6d09e7
GR		 366}
367
fad09c73 368static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
2e5f0320
LB		 369{
370 int ret;
6441e669 371 int i;
2e5f0320 372
fad09c73 373 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 374 if (ret < 0)
375 return ret;
376
fad09c73 377 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
8c9983a2 378 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 379 if (ret)
380 return ret;
2e5f0320 381
6441e669 382 for (i = 0; i < 16; i++) {
fad09c73 383 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 384 if (ret < 0)
385 return ret;
386
19b2f97e 387 usleep_range(1000, 2000);
cca8b133
AL		 388 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
389 GLOBAL_STATUS_PPU_POLLING)
85686581 390 return 0;
2e5f0320
LB		 391 }
392
393 return -ETIMEDOUT;
394}
395
fad09c73 396static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 397{
6441e669 398 int ret, err, i;
2e5f0320 399
fad09c73 400 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 401 if (ret < 0)
402 return ret;
403
fad09c73 404 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
762eb67b 405 ret | GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 406 if (err)
407 return err;
2e5f0320 408
6441e669 409 for (i = 0; i < 16; i++) {
fad09c73 410 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 411 if (ret < 0)
412 return ret;
413
19b2f97e 414 usleep_range(1000, 2000);
cca8b133
AL		 415 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
416 GLOBAL_STATUS_PPU_POLLING)
85686581 417 return 0;
2e5f0320
LB		 418 }
419
420 return -ETIMEDOUT;
421}
422
423static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
424{
fad09c73 425 struct mv88e6xxx_chip *chip;
2e5f0320 426
fad09c73 427 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 428
fad09c73 429 mutex_lock(&chip->reg_lock);
762eb67b 430
fad09c73
VD		 431 if (mutex_trylock(&chip->ppu_mutex)) {
432 if (mv88e6xxx_ppu_enable(chip) == 0)
433 chip->ppu_disabled = 0;
434 mutex_unlock(&chip->ppu_mutex);
2e5f0320 435 }
762eb67b 436
fad09c73 437 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 438}
439
440static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
441{
fad09c73 442 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 443
fad09c73 444 schedule_work(&chip->ppu_work);
2e5f0320
LB		 445}
446
fad09c73 447static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 448{
2e5f0320
LB		 449 int ret;
450
fad09c73 451 mutex_lock(&chip->ppu_mutex);
2e5f0320 452
3675c8d7 453 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 454 * we can access the PHY registers. If it was already
455 * disabled, cancel the timer that is going to re-enable
456 * it.
457 */
fad09c73
VD		 458 if (!chip->ppu_disabled) {
459 ret = mv88e6xxx_ppu_disable(chip);
85686581 460 if (ret < 0) {
fad09c73 461 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 462 return ret;
463 }
fad09c73 464 chip->ppu_disabled = 1;
2e5f0320 465 } else {
fad09c73 466 del_timer(&chip->ppu_timer);
85686581 467 ret = 0;
2e5f0320
LB		 468 }
469
470 return ret;
471}
472
fad09c73 473static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 474{
3675c8d7 475 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 476 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
477 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 478}
479
fad09c73 480static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 481{
fad09c73
VD		 482 mutex_init(&chip->ppu_mutex);
483 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
484 init_timer(&chip->ppu_timer);
485 chip->ppu_timer.data = (unsigned long)chip;
486 chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
2e5f0320
LB		 487}
488
e57e5e77
VD		 489static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
490 int reg, u16 *val)
2e5f0320 491{
e57e5e77 492 int err;
2e5f0320 493
e57e5e77
VD		 494 err = mv88e6xxx_ppu_access_get(chip);
495 if (!err) {
496 err = mv88e6xxx_read(chip, addr, reg, val);
fad09c73 497 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 498 }
499
e57e5e77 500 return err;
2e5f0320
LB		 501}
502
e57e5e77
VD		 503static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
504 int reg, u16 val)
2e5f0320 505{
e57e5e77 506 int err;
2e5f0320 507
e57e5e77
VD		 508 err = mv88e6xxx_ppu_access_get(chip);
509 if (!err) {
510 err = mv88e6xxx_write(chip, addr, reg, val);
fad09c73 511 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 512 }
513
e57e5e77 514 return err;
2e5f0320 515}
2e5f0320 516
e57e5e77
VD		 517static const struct mv88e6xxx_ops mv88e6xxx_phy_ppu_ops = {
518 .read = mv88e6xxx_phy_ppu_read,
519 .write = mv88e6xxx_phy_ppu_write,
520};
521
fad09c73 522static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
54d792f2 523{
fad09c73 524 return chip->info->family == MV88E6XXX_FAMILY_6065;
54d792f2
AL		 525}
526
fad09c73 527static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
54d792f2 528{
fad09c73 529 return chip->info->family == MV88E6XXX_FAMILY_6095;
54d792f2
AL		 530}
531
fad09c73 532static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 533{
fad09c73 534 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 535}
536
fad09c73 537static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 538{
fad09c73 539 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 540}
541
fad09c73 542static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
54d792f2 543{
fad09c73 544 return chip->info->family == MV88E6XXX_FAMILY_6185;
54d792f2
AL		 545}
546
fad09c73 547static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
7c3d0d67 548{
fad09c73 549 return chip->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 550}
551
fad09c73 552static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 553{
fad09c73 554 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 555}
556
fad09c73 557static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 558{
fad09c73 559 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 560}
561
fad09c73 562static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
f74df0be 563{
fad09c73 564 return chip->info->num_databases;
f74df0be
VD		 565}
566
fad09c73 567static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
b426e5f7
VD		 568{
569 /* Does the device have dedicated FID registers for ATU and VTU ops? */
fad09c73
VD		 570 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
571 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
b426e5f7
VD		 572 return true;
573
574 return false;
575}
576
dea87024
AL		 577/* We expect the switch to perform auto negotiation if there is a real
578 * phy. However, in the case of a fixed link phy, we force the port
579 * settings from the fixed link settings.
580 */
f81ec90f
VD		 581static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
582 struct phy_device *phydev)
dea87024 583{
fad09c73 584 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
49052871
AL		 585 u32 reg;
586 int ret;
dea87024
AL		 587
588 if (!phy_is_pseudo_fixed_link(phydev))
589 return;
590
fad09c73 591 mutex_lock(&chip->reg_lock);
dea87024 592
fad09c73 593 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
dea87024
AL		 594 if (ret < 0)
595 goto out;
596
597 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
598 PORT_PCS_CTRL_FORCE_LINK |
599 PORT_PCS_CTRL_DUPLEX_FULL |
600 PORT_PCS_CTRL_FORCE_DUPLEX |
601 PORT_PCS_CTRL_UNFORCED);
602
603 reg |= PORT_PCS_CTRL_FORCE_LINK;
604 if (phydev->link)
57d32310 605 reg |= PORT_PCS_CTRL_LINK_UP;
dea87024 606
fad09c73 607 if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
dea87024
AL		 608 goto out;
609
610 switch (phydev->speed) {
611 case SPEED_1000:
612 reg |= PORT_PCS_CTRL_1000;
613 break;
614 case SPEED_100:
615 reg |= PORT_PCS_CTRL_100;
616 break;
617 case SPEED_10:
618 reg |= PORT_PCS_CTRL_10;
619 break;
620 default:
621 pr_info("Unknown speed");
622 goto out;
623 }
624
625 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
626 if (phydev->duplex == DUPLEX_FULL)
627 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
628
fad09c73
VD		 629 if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
630 (port >= chip->info->num_ports - 2)) {
e7e72ac0
AL		 631 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
632 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
633 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
634 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
635 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
636 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
637 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
638 }
fad09c73 639 _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
dea87024
AL		 640
641out:
fad09c73 642 mutex_unlock(&chip->reg_lock);
dea87024
AL		 643}
644
fad09c73 645static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 646{
647 int ret;
648 int i;
649
650 for (i = 0; i < 10; i++) {
fad09c73 651 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
cca8b133 652 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 653 return 0;
654 }
655
656 return -ETIMEDOUT;
657}
658
fad09c73 659static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8
LB		 660{
661 int ret;
662
fad09c73 663 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
f3a8b6b6
AL		 664 port = (port + 1) << 5;
665
3675c8d7 666 /* Snapshot the hardware statistics counters for this port. */
fad09c73 667 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 668 GLOBAL_STATS_OP_CAPTURE_PORT |
669 GLOBAL_STATS_OP_HIST_RX_TX | port);
670 if (ret < 0)
671 return ret;
91da11f8 672
3675c8d7 673 /* Wait for the snapshotting to complete. */
fad09c73 674 ret = _mv88e6xxx_stats_wait(chip);
91da11f8
LB		 675 if (ret < 0)
676 return ret;
677
678 return 0;
679}
680
fad09c73 681static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
158bc065 682 int stat, u32 *val)
91da11f8
LB		 683{
684 u32 _val;
685 int ret;
686
687 *val = 0;
688
fad09c73 689 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 690 GLOBAL_STATS_OP_READ_CAPTURED |
691 GLOBAL_STATS_OP_HIST_RX_TX | stat);
91da11f8
LB		 692 if (ret < 0)
693 return;
694
fad09c73 695 ret = _mv88e6xxx_stats_wait(chip);
91da11f8
LB		 696 if (ret < 0)
697 return;
698
fad09c73 699 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
91da11f8
LB		 700 if (ret < 0)
701 return;
702
703 _val = ret << 16;
704
fad09c73 705 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
91da11f8
LB		 706 if (ret < 0)
707 return;
708
709 *val = _val | ret;
710}
711
e413e7e1 712static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 713 { "in_good_octets", 8, 0x00, BANK0, },
714 { "in_bad_octets", 4, 0x02, BANK0, },
715 { "in_unicast", 4, 0x04, BANK0, },
716 { "in_broadcasts", 4, 0x06, BANK0, },
717 { "in_multicasts", 4, 0x07, BANK0, },
718 { "in_pause", 4, 0x16, BANK0, },
719 { "in_undersize", 4, 0x18, BANK0, },
720 { "in_fragments", 4, 0x19, BANK0, },
721 { "in_oversize", 4, 0x1a, BANK0, },
722 { "in_jabber", 4, 0x1b, BANK0, },
723 { "in_rx_error", 4, 0x1c, BANK0, },
724 { "in_fcs_error", 4, 0x1d, BANK0, },
725 { "out_octets", 8, 0x0e, BANK0, },
726 { "out_unicast", 4, 0x10, BANK0, },
727 { "out_broadcasts", 4, 0x13, BANK0, },
728 { "out_multicasts", 4, 0x12, BANK0, },
729 { "out_pause", 4, 0x15, BANK0, },
730 { "excessive", 4, 0x11, BANK0, },
731 { "collisions", 4, 0x1e, BANK0, },
732 { "deferred", 4, 0x05, BANK0, },
733 { "single", 4, 0x14, BANK0, },
734 { "multiple", 4, 0x17, BANK0, },
735 { "out_fcs_error", 4, 0x03, BANK0, },
736 { "late", 4, 0x1f, BANK0, },
737 { "hist_64bytes", 4, 0x08, BANK0, },
738 { "hist_65_127bytes", 4, 0x09, BANK0, },
739 { "hist_128_255bytes", 4, 0x0a, BANK0, },
740 { "hist_256_511bytes", 4, 0x0b, BANK0, },
741 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
742 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
743 { "sw_in_discards", 4, 0x10, PORT, },
744 { "sw_in_filtered", 2, 0x12, PORT, },
745 { "sw_out_filtered", 2, 0x13, PORT, },
746 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
747 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
748 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
749 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
750 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
751 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
752 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
753 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
754 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
755 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
756 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
757 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
758 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
759 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
760 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
761 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
762 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
763 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
764 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
765 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
766 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
767 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
768 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
769 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
770 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
771 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 772};
773
fad09c73 774static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 775 struct mv88e6xxx_hw_stat *stat)
e413e7e1 776{
f5e2ed02
AL		 777 switch (stat->type) {
778 case BANK0:
e413e7e1 779 return true;
f5e2ed02 780 case BANK1:
fad09c73 781 return mv88e6xxx_6320_family(chip);
f5e2ed02 782 case PORT:
fad09c73
VD		 783 return mv88e6xxx_6095_family(chip) ||
784 mv88e6xxx_6185_family(chip) ||
785 mv88e6xxx_6097_family(chip) ||
786 mv88e6xxx_6165_family(chip) ||
787 mv88e6xxx_6351_family(chip) ||
788 mv88e6xxx_6352_family(chip);
91da11f8 789 }
f5e2ed02 790 return false;
91da11f8
LB		 791}
792
fad09c73 793static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 794 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 795 int port)
796{
80c4627b
AL		 797 u32 low;
798 u32 high = 0;
799 int ret;
800 u64 value;
801
f5e2ed02
AL		 802 switch (s->type) {
803 case PORT:
fad09c73 804 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
80c4627b
AL		 805 if (ret < 0)
806 return UINT64_MAX;
807
808 low = ret;
809 if (s->sizeof_stat == 4) {
fad09c73 810 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
f5e2ed02 811 s->reg + 1);
80c4627b
AL		 812 if (ret < 0)
813 return UINT64_MAX;
814 high = ret;
815 }
f5e2ed02
AL		 816 break;
817 case BANK0:
818 case BANK1:
fad09c73 819 _mv88e6xxx_stats_read(chip, s->reg, &low);
80c4627b 820 if (s->sizeof_stat == 8)
fad09c73 821 _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
80c4627b
AL		 822 }
823 value = (((u64)high) << 16) | low;
824 return value;
825}
826
f81ec90f
VD		 827static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
828 uint8_t *data)
91da11f8 829{
fad09c73 830 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f5e2ed02
AL		 831 struct mv88e6xxx_hw_stat *stat;
832 int i, j;
91da11f8 833
f5e2ed02
AL		 834 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
835 stat = &mv88e6xxx_hw_stats[i];
fad09c73 836 if (mv88e6xxx_has_stat(chip, stat)) {
f5e2ed02
AL		 837 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
838 ETH_GSTRING_LEN);
839 j++;
840 }
91da11f8 841 }
e413e7e1
AL		 842}
843
f81ec90f 844static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
e413e7e1 845{
fad09c73 846 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f5e2ed02
AL		 847 struct mv88e6xxx_hw_stat *stat;
848 int i, j;
849
850 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
851 stat = &mv88e6xxx_hw_stats[i];
fad09c73 852 if (mv88e6xxx_has_stat(chip, stat))
f5e2ed02
AL		 853 j++;
854 }
855 return j;
e413e7e1
AL		 856}
857
f81ec90f
VD		 858static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
859 uint64_t *data)
e413e7e1 860{
fad09c73 861 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f5e2ed02
AL		 862 struct mv88e6xxx_hw_stat *stat;
863 int ret;
864 int i, j;
865
fad09c73 866 mutex_lock(&chip->reg_lock);
f5e2ed02 867
fad09c73 868 ret = _mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 869 if (ret < 0) {
fad09c73 870 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 871 return;
872 }
873 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
874 stat = &mv88e6xxx_hw_stats[i];
fad09c73
VD		 875 if (mv88e6xxx_has_stat(chip, stat)) {
876 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
f5e2ed02
AL		 877 j++;
878 }
879 }
880
fad09c73 881 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 882}
883
f81ec90f 884static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 885{
886 return 32 * sizeof(u16);
887}
888
f81ec90f
VD		 889static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
890 struct ethtool_regs *regs, void *_p)
a1ab91f3 891{
fad09c73 892 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
a1ab91f3
GR		 893 u16 *p = _p;
894 int i;
895
896 regs->version = 0;
897
898 memset(p, 0xff, 32 * sizeof(u16));
899
fad09c73 900 mutex_lock(&chip->reg_lock);
23062513 901
a1ab91f3
GR		 902 for (i = 0; i < 32; i++) {
903 int ret;
904
fad09c73 905 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
a1ab91f3
GR		 906 if (ret >= 0)
907 p[i] = ret;
908 }
23062513 909
fad09c73 910 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 911}
912
fad09c73 913static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
facd95b2 914{
2d79af6e
VD		 915 return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
916 GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 917}
918
f81ec90f
VD		 919static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
920 struct ethtool_eee *e)
11b3b45d 921{
fad09c73 922 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
9c93829c
VD		 923 u16 reg;
924 int err;
11b3b45d 925
fad09c73 926 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 927 return -EOPNOTSUPP;
928
fad09c73 929 mutex_lock(&chip->reg_lock);
2f40c698 930
9c93829c
VD		 931 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
932 if (err)
2f40c698 933 goto out;
11b3b45d
GR		 934
935 e->eee_enabled = !!(reg & 0x0200);
936 e->tx_lpi_enabled = !!(reg & 0x0100);
937
9c93829c
VD		 938 err = mv88e6xxx_read(chip, REG_PORT(port), PORT_STATUS, &reg);
939 if (err)
2f40c698 940 goto out;
11b3b45d 941
cca8b133 942 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 943out:
fad09c73 944 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 945
946 return err;
11b3b45d
GR		 947}
948
f81ec90f
VD		 949static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
950 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 951{
fad09c73 952 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
9c93829c
VD		 953 u16 reg;
954 int err;
11b3b45d 955
fad09c73 956 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 957 return -EOPNOTSUPP;
958
fad09c73 959 mutex_lock(&chip->reg_lock);
11b3b45d 960
9c93829c
VD		 961 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
962 if (err)
2f40c698
AL		 963 goto out;
964
9c93829c 965 reg &= ~0x0300;
2f40c698
AL		 966 if (e->eee_enabled)
967 reg |= 0x0200;
968 if (e->tx_lpi_enabled)
969 reg |= 0x0100;
970
9c93829c 971 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 972out:
fad09c73 973 mutex_unlock(&chip->reg_lock);
2f40c698 974
9c93829c 975 return err;
11b3b45d
GR		 976}
977
fad09c73 978static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
facd95b2
GR		 979{
980 int ret;
981
fad09c73
VD		 982 if (mv88e6xxx_has_fid_reg(chip)) {
983 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
984 fid);
b426e5f7
VD		 985 if (ret < 0)
986 return ret;
fad09c73 987 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f 988 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
fad09c73 989 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
11ea809f
VD		 990 if (ret < 0)
991 return ret;
992
fad09c73 993 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
11ea809f
VD		 994 (ret & 0xfff) |
995 ((fid << 8) & 0xf000));
996 if (ret < 0)
997 return ret;
998
999 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1000 cmd |= fid & 0xf;
b426e5f7
VD		 1001 }
1002
fad09c73 1003 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
facd95b2
GR		 1004 if (ret < 0)
1005 return ret;
1006
fad09c73 1007 return _mv88e6xxx_atu_wait(chip);
facd95b2
GR		 1008}
1009
fad09c73 1010static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
37705b73
VD		 1011 struct mv88e6xxx_atu_entry *entry)
1012{
1013 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1014
1015 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1016 unsigned int mask, shift;
1017
1018 if (entry->trunk) {
1019 data |= GLOBAL_ATU_DATA_TRUNK;
1020 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1021 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1022 } else {
1023 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1024 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1025 }
1026
1027 data |= (entry->portv_trunkid << shift) & mask;
1028 }
1029
fad09c73 1030 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
37705b73
VD		 1031}
1032
fad09c73 1033static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
7fb5e755
VD		 1034 struct mv88e6xxx_atu_entry *entry,
1035 bool static_too)
facd95b2 1036{
7fb5e755
VD		 1037 int op;
1038 int err;
facd95b2 1039
fad09c73 1040 err = _mv88e6xxx_atu_wait(chip);
7fb5e755
VD		 1041 if (err)
1042 return err;
facd95b2 1043
fad09c73 1044 err = _mv88e6xxx_atu_data_write(chip, entry);
7fb5e755
VD		 1045 if (err)
1046 return err;
1047
1048 if (entry->fid) {
7fb5e755
VD		 1049 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1050 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1051 } else {
1052 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1053 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1054 }
1055
fad09c73 1056 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
7fb5e755
VD		 1057}
1058
fad09c73 1059static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
158bc065 1060 u16 fid, bool static_too)
7fb5e755
VD		 1061{
1062 struct mv88e6xxx_atu_entry entry = {
1063 .fid = fid,
1064 .state = 0, /* EntryState bits must be 0 */
1065 };
70cc99d1 1066
fad09c73 1067 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
7fb5e755
VD		 1068}
1069
fad09c73 1070static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1071 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1072{
1073 struct mv88e6xxx_atu_entry entry = {
1074 .trunk = false,
1075 .fid = fid,
1076 };
1077
1078 /* EntryState bits must be 0xF */
1079 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1080
1081 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1082 entry.portv_trunkid = (to_port & 0x0f) << 4;
1083 entry.portv_trunkid |= from_port & 0x0f;
1084
fad09c73 1085 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
9f4d55d2
VD		 1086}
1087
fad09c73 1088static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1089 int port, bool static_too)
9f4d55d2
VD		 1090{
1091 /* Destination port 0xF means remove the entries */
fad09c73 1092 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1093}
1094
2d9deae4
VD		 1095static const char * const mv88e6xxx_port_state_names[] = {
1096 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1097 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1098 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1099 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1100};
1101
fad09c73 1102static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
158bc065 1103 u8 state)
facd95b2 1104{
fad09c73 1105 struct dsa_switch *ds = chip->ds;
c3ffe6d2 1106 int reg, ret = 0;
facd95b2
GR		 1107 u8 oldstate;
1108
fad09c73 1109 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
2d9deae4
VD		 1110 if (reg < 0)
1111 return reg;
facd95b2 1112
cca8b133 1113 oldstate = reg & PORT_CONTROL_STATE_MASK;
2d9deae4 1114
facd95b2
GR		 1115 if (oldstate != state) {
1116 /* Flush forwarding database if we're moving a port
1117 * from Learning or Forwarding state to Disabled or
1118 * Blocking or Listening state.
1119 */
2d9deae4 1120 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
57d32310
VD		 1121 oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1122 (state == PORT_CONTROL_STATE_DISABLED ||
1123 state == PORT_CONTROL_STATE_BLOCKING)) {
fad09c73 1124 ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
facd95b2 1125 if (ret)
2d9deae4 1126 return ret;
facd95b2 1127 }
2d9deae4 1128
cca8b133 1129 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
fad09c73 1130 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
cca8b133 1131 reg);
2d9deae4
VD		 1132 if (ret)
1133 return ret;
1134
c8b09808 1135 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
2d9deae4
VD		 1136 mv88e6xxx_port_state_names[state],
1137 mv88e6xxx_port_state_names[oldstate]);
facd95b2
GR		 1138 }
1139
facd95b2
GR		 1140 return ret;
1141}
1142
fad09c73 1143static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1144{
fad09c73
VD		 1145 struct net_device *bridge = chip->ports[port].bridge_dev;
1146 const u16 mask = (1 << chip->info->num_ports) - 1;
1147 struct dsa_switch *ds = chip->ds;
b7666efe 1148 u16 output_ports = 0;
ede8098d 1149 int reg;
b7666efe
VD		 1150 int i;
1151
1152 /* allow CPU port or DSA link(s) to send frames to every port */
1153 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1154 output_ports = mask;
1155 } else {
fad09c73 1156 for (i = 0; i < chip->info->num_ports; ++i) {
b7666efe 1157 /* allow sending frames to every group member */
fad09c73 1158 if (bridge && chip->ports[i].bridge_dev == bridge)
b7666efe
VD		 1159 output_ports |= BIT(i);
1160
1161 /* allow sending frames to CPU port and DSA link(s) */
1162 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1163 output_ports |= BIT(i);
1164 }
1165 }
1166
1167 /* prevent frames from going back out of the port they came in on */
1168 output_ports &= ~BIT(port);
facd95b2 1169
fad09c73 1170 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
ede8098d
VD		 1171 if (reg < 0)
1172 return reg;
facd95b2 1173
ede8098d
VD		 1174 reg &= ~mask;
1175 reg |= output_ports & mask;
facd95b2 1176
fad09c73 1177 return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
facd95b2
GR		 1178}
1179
f81ec90f
VD		 1180static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1181 u8 state)
facd95b2 1182{
fad09c73 1183 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
facd95b2 1184 int stp_state;
553eb544 1185 int err;
facd95b2
GR		 1186
1187 switch (state) {
1188 case BR_STATE_DISABLED:
cca8b133 1189 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1190 break;
1191 case BR_STATE_BLOCKING:
1192 case BR_STATE_LISTENING:
cca8b133 1193 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1194 break;
1195 case BR_STATE_LEARNING:
cca8b133 1196 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1197 break;
1198 case BR_STATE_FORWARDING:
1199 default:
cca8b133 1200 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1201 break;
1202 }
1203
fad09c73
VD		 1204 mutex_lock(&chip->reg_lock);
1205 err = _mv88e6xxx_port_state(chip, port, stp_state);
1206 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1207
1208 if (err)
c8b09808
AL		 1209 netdev_err(ds->ports[port].netdev,
1210 "failed to update state to %s\n",
553eb544 1211 mv88e6xxx_port_state_names[stp_state]);
facd95b2
GR		 1212}
1213
fad09c73 1214static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
158bc065 1215 u16 *new, u16 *old)
76e398a6 1216{
fad09c73 1217 struct dsa_switch *ds = chip->ds;
5da96031 1218 u16 pvid;
76e398a6
VD		 1219 int ret;
1220
fad09c73 1221 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
76e398a6
VD		 1222 if (ret < 0)
1223 return ret;
1224
5da96031
VD		 1225 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1226
1227 if (new) {
1228 ret &= ~PORT_DEFAULT_VLAN_MASK;
1229 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1230
fad09c73 1231 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
5da96031
VD		 1232 PORT_DEFAULT_VLAN, ret);
1233 if (ret < 0)
1234 return ret;
1235
c8b09808
AL		 1236 netdev_dbg(ds->ports[port].netdev,
1237 "DefaultVID %d (was %d)\n", *new, pvid);
5da96031
VD		 1238 }
1239
1240 if (old)
1241 *old = pvid;
76e398a6
VD		 1242
1243 return 0;
1244}
1245
fad09c73 1246static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
158bc065 1247 int port, u16 *pvid)
5da96031 1248{
fad09c73 1249 return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
5da96031
VD		 1250}
1251
fad09c73 1252static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
158bc065 1253 int port, u16 pvid)
0d3b33e6 1254{
fad09c73 1255 return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
0d3b33e6
VD		 1256}
1257
fad09c73 1258static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1259{
2d79af6e
VD		 1260 return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
1261 GLOBAL_VTU_OP_BUSY);
6b17e864
VD		 1262}
1263
fad09c73 1264static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864
VD		 1265{
1266 int ret;
1267
fad09c73 1268 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
6b17e864
VD		 1269 if (ret < 0)
1270 return ret;
1271
fad09c73 1272 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1273}
1274
fad09c73 1275static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1276{
1277 int ret;
1278
fad09c73 1279 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1280 if (ret < 0)
1281 return ret;
1282
fad09c73 1283 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1284}
1285
fad09c73 1286static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b8fee957
VD		 1287 struct mv88e6xxx_vtu_stu_entry *entry,
1288 unsigned int nibble_offset)
1289{
b8fee957
VD		 1290 u16 regs[3];
1291 int i;
1292 int ret;
1293
1294 for (i = 0; i < 3; ++i) {
fad09c73 1295 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
b8fee957
VD		 1296 GLOBAL_VTU_DATA_0_3 + i);
1297 if (ret < 0)
1298 return ret;
1299
1300 regs[i] = ret;
1301 }
1302
fad09c73 1303 for (i = 0; i < chip->info->num_ports; ++i) {
b8fee957
VD		 1304 unsigned int shift = (i % 4) * 4 + nibble_offset;
1305 u16 reg = regs[i / 4];
1306
1307 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1308 }
1309
1310 return 0;
1311}
1312
fad09c73 1313static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1314 struct mv88e6xxx_vtu_stu_entry *entry)
1315{
fad09c73 1316 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1317}
1318
fad09c73 1319static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1320 struct mv88e6xxx_vtu_stu_entry *entry)
1321{
fad09c73 1322 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1323}
1324
fad09c73 1325static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
7dad08d7
VD		 1326 struct mv88e6xxx_vtu_stu_entry *entry,
1327 unsigned int nibble_offset)
1328{
7dad08d7
VD		 1329 u16 regs[3] = { 0 };
1330 int i;
1331 int ret;
1332
fad09c73 1333 for (i = 0; i < chip->info->num_ports; ++i) {
7dad08d7
VD		 1334 unsigned int shift = (i % 4) * 4 + nibble_offset;
1335 u8 data = entry->data[i];
1336
1337 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1338 }
1339
1340 for (i = 0; i < 3; ++i) {
fad09c73 1341 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
7dad08d7
VD		 1342 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1343 if (ret < 0)
1344 return ret;
1345 }
1346
1347 return 0;
1348}
1349
fad09c73 1350static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1351 struct mv88e6xxx_vtu_stu_entry *entry)
1352{
fad09c73 1353 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1354}
1355
fad09c73 1356static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1357 struct mv88e6xxx_vtu_stu_entry *entry)
1358{
fad09c73 1359 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1360}
1361
fad09c73 1362static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1363{
fad09c73 1364 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
36d04ba1
VD		 1365 vid & GLOBAL_VTU_VID_MASK);
1366}
1367
fad09c73 1368static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b8fee957
VD		 1369 struct mv88e6xxx_vtu_stu_entry *entry)
1370{
1371 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1372 int ret;
1373
fad09c73 1374 ret = _mv88e6xxx_vtu_wait(chip);
b8fee957
VD		 1375 if (ret < 0)
1376 return ret;
1377
fad09c73 1378 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
b8fee957
VD		 1379 if (ret < 0)
1380 return ret;
1381
fad09c73 1382 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
b8fee957
VD		 1383 if (ret < 0)
1384 return ret;
1385
1386 next.vid = ret & GLOBAL_VTU_VID_MASK;
1387 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1388
1389 if (next.valid) {
fad09c73 1390 ret = mv88e6xxx_vtu_data_read(chip, &next);
b8fee957
VD		 1391 if (ret < 0)
1392 return ret;
1393
fad09c73
VD		 1394 if (mv88e6xxx_has_fid_reg(chip)) {
1395 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
b8fee957
VD		 1396 GLOBAL_VTU_FID);
1397 if (ret < 0)
1398 return ret;
1399
1400 next.fid = ret & GLOBAL_VTU_FID_MASK;
fad09c73 1401 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1402 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1403 * VTU DBNum[3:0] are located in VTU Operation 3:0
1404 */
fad09c73 1405 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
11ea809f
VD		 1406 GLOBAL_VTU_OP);
1407 if (ret < 0)
1408 return ret;
1409
1410 next.fid = (ret & 0xf00) >> 4;
1411 next.fid |= ret & 0xf;
2e7bd5ef 1412 }
b8fee957 1413
fad09c73
VD		 1414 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1415 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
b8fee957
VD		 1416 GLOBAL_VTU_SID);
1417 if (ret < 0)
1418 return ret;
1419
1420 next.sid = ret & GLOBAL_VTU_SID_MASK;
1421 }
1422 }
1423
1424 *entry = next;
1425 return 0;
1426}
1427
f81ec90f
VD		 1428static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1429 struct switchdev_obj_port_vlan *vlan,
1430 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1431{
fad09c73 1432 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
ceff5eff
VD		 1433 struct mv88e6xxx_vtu_stu_entry next;
1434 u16 pvid;
1435 int err;
1436
fad09c73 1437 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1438 return -EOPNOTSUPP;
1439
fad09c73 1440 mutex_lock(&chip->reg_lock);
ceff5eff 1441
fad09c73 1442 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
ceff5eff
VD		 1443 if (err)
1444 goto unlock;
1445
fad09c73 1446 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1447 if (err)
1448 goto unlock;
1449
1450 do {
fad09c73 1451 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1452 if (err)
1453 break;
1454
1455 if (!next.valid)
1456 break;
1457
1458 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1459 continue;
1460
1461 /* reinit and dump this VLAN obj */
57d32310
VD		 1462 vlan->vid_begin = next.vid;
1463 vlan->vid_end = next.vid;
ceff5eff
VD		 1464 vlan->flags = 0;
1465
1466 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1467 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1468
1469 if (next.vid == pvid)
1470 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1471
1472 err = cb(&vlan->obj);
1473 if (err)
1474 break;
1475 } while (next.vid < GLOBAL_VTU_VID_MASK);
1476
1477unlock:
fad09c73 1478 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1479
1480 return err;
1481}
1482
fad09c73 1483static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
7dad08d7
VD		 1484 struct mv88e6xxx_vtu_stu_entry *entry)
1485{
11ea809f 1486 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7
VD		 1487 u16 reg = 0;
1488 int ret;
1489
fad09c73 1490 ret = _mv88e6xxx_vtu_wait(chip);
7dad08d7
VD		 1491 if (ret < 0)
1492 return ret;
1493
1494 if (!entry->valid)
1495 goto loadpurge;
1496
1497 /* Write port member tags */
fad09c73 1498 ret = mv88e6xxx_vtu_data_write(chip, entry);
7dad08d7
VD		 1499 if (ret < 0)
1500 return ret;
1501
fad09c73 1502 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1503 reg = entry->sid & GLOBAL_VTU_SID_MASK;
fad09c73
VD		 1504 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1505 reg);
7dad08d7
VD		 1506 if (ret < 0)
1507 return ret;
b426e5f7 1508 }
7dad08d7 1509
fad09c73 1510 if (mv88e6xxx_has_fid_reg(chip)) {
7dad08d7 1511 reg = entry->fid & GLOBAL_VTU_FID_MASK;
fad09c73
VD		 1512 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1513 reg);
7dad08d7
VD		 1514 if (ret < 0)
1515 return ret;
fad09c73 1516 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1517 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1518 * VTU DBNum[3:0] are located in VTU Operation 3:0
1519 */
1520 op |= (entry->fid & 0xf0) << 8;
1521 op |= entry->fid & 0xf;
7dad08d7
VD		 1522 }
1523
1524 reg = GLOBAL_VTU_VID_VALID;
1525loadpurge:
1526 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
fad09c73 1527 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
7dad08d7
VD		 1528 if (ret < 0)
1529 return ret;
1530
fad09c73 1531 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1532}
1533
fad09c73 1534static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
0d3b33e6
VD		 1535 struct mv88e6xxx_vtu_stu_entry *entry)
1536{
1537 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1538 int ret;
1539
fad09c73 1540 ret = _mv88e6xxx_vtu_wait(chip);
0d3b33e6
VD		 1541 if (ret < 0)
1542 return ret;
1543
fad09c73 1544 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
0d3b33e6
VD		 1545 sid & GLOBAL_VTU_SID_MASK);
1546 if (ret < 0)
1547 return ret;
1548
fad09c73 1549 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
0d3b33e6
VD		 1550 if (ret < 0)
1551 return ret;
1552
fad09c73 1553 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
0d3b33e6
VD		 1554 if (ret < 0)
1555 return ret;
1556
1557 next.sid = ret & GLOBAL_VTU_SID_MASK;
1558
fad09c73 1559 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
0d3b33e6
VD		 1560 if (ret < 0)
1561 return ret;
1562
1563 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1564
1565 if (next.valid) {
fad09c73 1566 ret = mv88e6xxx_stu_data_read(chip, &next);
0d3b33e6
VD		 1567 if (ret < 0)
1568 return ret;
1569 }
1570
1571 *entry = next;
1572 return 0;
1573}
1574
fad09c73 1575static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
0d3b33e6
VD		 1576 struct mv88e6xxx_vtu_stu_entry *entry)
1577{
1578 u16 reg = 0;
1579 int ret;
1580
fad09c73 1581 ret = _mv88e6xxx_vtu_wait(chip);
0d3b33e6
VD		 1582 if (ret < 0)
1583 return ret;
1584
1585 if (!entry->valid)
1586 goto loadpurge;
1587
1588 /* Write port states */
fad09c73 1589 ret = mv88e6xxx_stu_data_write(chip, entry);
0d3b33e6
VD		 1590 if (ret < 0)
1591 return ret;
1592
1593 reg = GLOBAL_VTU_VID_VALID;
1594loadpurge:
fad09c73 1595 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
0d3b33e6
VD		 1596 if (ret < 0)
1597 return ret;
1598
1599 reg = entry->sid & GLOBAL_VTU_SID_MASK;
fad09c73 1600 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
0d3b33e6
VD		 1601 if (ret < 0)
1602 return ret;
1603
fad09c73 1604 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1605}
1606
fad09c73 1607static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
158bc065 1608 u16 *new, u16 *old)
2db9ce1f 1609{
fad09c73 1610 struct dsa_switch *ds = chip->ds;
f74df0be 1611 u16 upper_mask;
2db9ce1f
VD		 1612 u16 fid;
1613 int ret;
1614
fad09c73 1615 if (mv88e6xxx_num_databases(chip) == 4096)
f74df0be 1616 upper_mask = 0xff;
fad09c73 1617 else if (mv88e6xxx_num_databases(chip) == 256)
11ea809f 1618 upper_mask = 0xf;
f74df0be
VD		 1619 else
1620 return -EOPNOTSUPP;
1621
2db9ce1f 1622 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
fad09c73 1623 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
2db9ce1f
VD		 1624 if (ret < 0)
1625 return ret;
1626
1627 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1628
1629 if (new) {
1630 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1631 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1632
fad09c73 1633 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
2db9ce1f
VD		 1634 ret);
1635 if (ret < 0)
1636 return ret;
1637 }
1638
1639 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
fad09c73 1640 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
2db9ce1f
VD		 1641 if (ret < 0)
1642 return ret;
1643
f74df0be 1644 fid |= (ret & upper_mask) << 4;
2db9ce1f
VD		 1645
1646 if (new) {
f74df0be
VD		 1647 ret &= ~upper_mask;
1648 ret |= (*new >> 4) & upper_mask;
2db9ce1f 1649
fad09c73 1650 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2db9ce1f
VD		 1651 ret);
1652 if (ret < 0)
1653 return ret;
1654
c8b09808
AL		 1655 netdev_dbg(ds->ports[port].netdev,
1656 "FID %d (was %d)\n", *new, fid);
2db9ce1f
VD		 1657 }
1658
1659 if (old)
1660 *old = fid;
1661
1662 return 0;
1663}
1664
fad09c73 1665static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
158bc065 1666 int port, u16 *fid)
2db9ce1f 1667{
fad09c73 1668 return _mv88e6xxx_port_fid(chip, port, NULL, fid);
2db9ce1f
VD		 1669}
1670
fad09c73 1671static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
158bc065 1672 int port, u16 fid)
2db9ce1f 1673{
fad09c73 1674 return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
2db9ce1f
VD		 1675}
1676
fad09c73 1677static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1678{
1679 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1680 struct mv88e6xxx_vtu_stu_entry vlan;
2db9ce1f 1681 int i, err;
3285f9e8
VD		 1682
1683 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1684
2db9ce1f 1685 /* Set every FID bit used by the (un)bridged ports */
fad09c73
VD		 1686 for (i = 0; i < chip->info->num_ports; ++i) {
1687 err = _mv88e6xxx_port_fid_get(chip, i, fid);
2db9ce1f
VD		 1688 if (err)
1689 return err;
1690
1691 set_bit(*fid, fid_bitmap);
1692 }
1693
3285f9e8 1694 /* Set every FID bit used by the VLAN entries */
fad09c73 1695 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1696 if (err)
1697 return err;
1698
1699 do {
fad09c73 1700 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1701 if (err)
1702 return err;
1703
1704 if (!vlan.valid)
1705 break;
1706
1707 set_bit(vlan.fid, fid_bitmap);
1708 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1709
1710 /* The reset value 0x000 is used to indicate that multiple address
1711 * databases are not needed. Return the next positive available.
1712 */
1713 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1714 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1715 return -ENOSPC;
1716
1717 /* Clear the database */
fad09c73 1718 return _mv88e6xxx_atu_flush(chip, *fid, true);
3285f9e8
VD		 1719}
1720
fad09c73 1721static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
2fb5ef09 1722 struct mv88e6xxx_vtu_stu_entry *entry)
0d3b33e6 1723{
fad09c73 1724 struct dsa_switch *ds = chip->ds;
0d3b33e6
VD		 1725 struct mv88e6xxx_vtu_stu_entry vlan = {
1726 .valid = true,
1727 .vid = vid,
1728 };
3285f9e8
VD		 1729 int i, err;
1730
fad09c73 1731 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
3285f9e8
VD		 1732 if (err)
1733 return err;
0d3b33e6 1734
3d131f07 1735 /* exclude all ports except the CPU and DSA ports */
fad09c73 1736 for (i = 0; i < chip->info->num_ports; ++i)
3d131f07
VD		 1737 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1738 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1739 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1740
fad09c73
VD		 1741 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1742 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
0d3b33e6 1743 struct mv88e6xxx_vtu_stu_entry vstp;
0d3b33e6
VD		 1744
1745 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1746 * implemented, only one STU entry is needed to cover all VTU
1747 * entries. Thus, validate the SID 0.
1748 */
1749 vlan.sid = 0;
fad09c73 1750 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1751 if (err)
1752 return err;
1753
1754 if (vstp.sid != vlan.sid || !vstp.valid) {
1755 memset(&vstp, 0, sizeof(vstp));
1756 vstp.valid = true;
1757 vstp.sid = vlan.sid;
1758
fad09c73 1759 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1760 if (err)
1761 return err;
1762 }
0d3b33e6
VD		 1763 }
1764
1765 *entry = vlan;
1766 return 0;
1767}
1768
fad09c73 1769static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
2fb5ef09
VD		 1770 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1771{
1772 int err;
1773
1774 if (!vid)
1775 return -EINVAL;
1776
fad09c73 1777 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1778 if (err)
1779 return err;
1780
fad09c73 1781 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1782 if (err)
1783 return err;
1784
1785 if (entry->vid != vid || !entry->valid) {
1786 if (!creat)
1787 return -EOPNOTSUPP;
1788 /* -ENOENT would've been more appropriate, but switchdev expects
1789 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1790 */
1791
fad09c73 1792 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1793 }
1794
1795 return err;
1796}
1797
da9c359e
VD		 1798static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1799 u16 vid_begin, u16 vid_end)
1800{
fad09c73 1801 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
da9c359e
VD		 1802 struct mv88e6xxx_vtu_stu_entry vlan;
1803 int i, err;
1804
1805 if (!vid_begin)
1806 return -EOPNOTSUPP;
1807
fad09c73 1808 mutex_lock(&chip->reg_lock);
da9c359e 1809
fad09c73 1810 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1811 if (err)
1812 goto unlock;
1813
1814 do {
fad09c73 1815 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1816 if (err)
1817 goto unlock;
1818
1819 if (!vlan.valid)
1820 break;
1821
1822 if (vlan.vid > vid_end)
1823 break;
1824
fad09c73 1825 for (i = 0; i < chip->info->num_ports; ++i) {
da9c359e
VD		 1826 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1827 continue;
1828
1829 if (vlan.data[i] ==
1830 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1831 continue;
1832
fad09c73
VD		 1833 if (chip->ports[i].bridge_dev ==
1834 chip->ports[port].bridge_dev)
da9c359e
VD		 1835 break; /* same bridge, check next VLAN */
1836
c8b09808 1837 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1838 "hardware VLAN %d already used by %s\n",
1839 vlan.vid,
fad09c73 1840 netdev_name(chip->ports[i].bridge_dev));
da9c359e
VD		 1841 err = -EOPNOTSUPP;
1842 goto unlock;
1843 }
1844 } while (vlan.vid < vid_end);
1845
1846unlock:
fad09c73 1847 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1848
1849 return err;
1850}
1851
214cdb99
VD		 1852static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1853 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1854 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1855 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1856 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1857};
1858
f81ec90f
VD		 1859static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1860 bool vlan_filtering)
214cdb99 1861{
fad09c73 1862 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
214cdb99
VD		 1863 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1864 PORT_CONTROL_2_8021Q_DISABLED;
1865 int ret;
1866
fad09c73 1867 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1868 return -EOPNOTSUPP;
1869
fad09c73 1870 mutex_lock(&chip->reg_lock);
214cdb99 1871
fad09c73 1872 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
214cdb99
VD		 1873 if (ret < 0)
1874 goto unlock;
1875
1876 old = ret & PORT_CONTROL_2_8021Q_MASK;
1877
5220ef1e
VD		 1878 if (new != old) {
1879 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1880 ret |= new & PORT_CONTROL_2_8021Q_MASK;
214cdb99 1881
fad09c73 1882 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
5220ef1e
VD		 1883 ret);
1884 if (ret < 0)
1885 goto unlock;
1886
c8b09808 1887 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
5220ef1e
VD		 1888 mv88e6xxx_port_8021q_mode_names[new],
1889 mv88e6xxx_port_8021q_mode_names[old]);
1890 }
214cdb99 1891
5220ef1e 1892 ret = 0;
214cdb99 1893unlock:
fad09c73 1894 mutex_unlock(&chip->reg_lock);
214cdb99
VD		 1895
1896 return ret;
1897}
1898
57d32310
VD		 1899static int
1900mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1901 const struct switchdev_obj_port_vlan *vlan,
1902 struct switchdev_trans *trans)
76e398a6 1903{
fad09c73 1904 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
da9c359e
VD		 1905 int err;
1906
fad09c73 1907 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1908 return -EOPNOTSUPP;
1909
da9c359e
VD		 1910 /* If the requested port doesn't belong to the same bridge as the VLAN
1911 * members, do not support it (yet) and fallback to software VLAN.
1912 */
1913 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1914 vlan->vid_end);
1915 if (err)
1916 return err;
1917
76e398a6
VD		 1918 /* We don't need any dynamic resource from the kernel (yet),
1919 * so skip the prepare phase.
1920 */
1921 return 0;
1922}
1923
fad09c73 1924static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1925 u16 vid, bool untagged)
0d3b33e6 1926{
0d3b33e6
VD		 1927 struct mv88e6xxx_vtu_stu_entry vlan;
1928 int err;
1929
fad09c73 1930 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1931 if (err)
76e398a6 1932 return err;
0d3b33e6 1933
0d3b33e6
VD		 1934 vlan.data[port] = untagged ?
1935 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1936 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1937
fad09c73 1938 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1939}
1940
f81ec90f
VD		 1941static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1942 const struct switchdev_obj_port_vlan *vlan,
1943 struct switchdev_trans *trans)
76e398a6 1944{
fad09c73 1945 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
76e398a6
VD		 1946 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1947 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1948 u16 vid;
76e398a6 1949
fad09c73 1950 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1951 return;
1952
fad09c73 1953 mutex_lock(&chip->reg_lock);
76e398a6 1954
4d5770b3 1955 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1956 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1957 netdev_err(ds->ports[port].netdev,
1958 "failed to add VLAN %d%c\n",
4d5770b3 1959 vid, untagged ? 'u' : 't');
76e398a6 1960
fad09c73 1961 if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
c8b09808 1962 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1963 vlan->vid_end);
0d3b33e6 1964
fad09c73 1965 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1966}
1967
fad09c73 1968static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1969 int port, u16 vid)
7dad08d7 1970{
fad09c73 1971 struct dsa_switch *ds = chip->ds;
7dad08d7 1972 struct mv88e6xxx_vtu_stu_entry vlan;
7dad08d7
VD		 1973 int i, err;
1974
fad09c73 1975 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1976 if (err)
76e398a6 1977 return err;
7dad08d7 1978
2fb5ef09
VD		 1979 /* Tell switchdev if this VLAN is handled in software */
1980 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1981 return -EOPNOTSUPP;
7dad08d7
VD		 1982
1983 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1984
1985 /* keep the VLAN unless all ports are excluded */
f02bdffc 1986 vlan.valid = false;
fad09c73 1987 for (i = 0; i < chip->info->num_ports; ++i) {
3d131f07 1988 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1989 continue;
1990
1991 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1992 vlan.valid = true;
7dad08d7
VD		 1993 break;
1994 }
1995 }
1996
fad09c73 1997 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1998 if (err)
1999 return err;
2000
fad09c73 2001 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 2002}
2003
f81ec90f
VD		 2004static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2005 const struct switchdev_obj_port_vlan *vlan)
76e398a6 2006{
fad09c73 2007 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
76e398a6
VD		 2008 u16 pvid, vid;
2009 int err = 0;
2010
fad09c73 2011 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 2012 return -EOPNOTSUPP;
2013
fad09c73 2014 mutex_lock(&chip->reg_lock);
76e398a6 2015
fad09c73 2016 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
7dad08d7
VD		 2017 if (err)
2018 goto unlock;
2019
76e398a6 2020 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 2021 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 2022 if (err)
2023 goto unlock;
2024
2025 if (vid == pvid) {
fad09c73 2026 err = _mv88e6xxx_port_pvid_set(chip, port, 0);
76e398a6
VD		 2027 if (err)
2028 goto unlock;
2029 }
2030 }
2031
7dad08d7 2032unlock:
fad09c73 2033 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 2034
2035 return err;
2036}
2037
fad09c73 2038static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
c5723ac5 2039 const unsigned char *addr)
defb05b9
GR		 2040{
2041 int i, ret;
2042
2043 for (i = 0; i < 3; i++) {
cca8b133 2044 ret = _mv88e6xxx_reg_write(
fad09c73 2045 chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
cca8b133 2046 (addr[i * 2] << 8) | addr[i * 2 + 1]);
defb05b9
GR		 2047 if (ret < 0)
2048 return ret;
2049 }
2050
2051 return 0;
2052}
2053
fad09c73 2054static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
158bc065 2055 unsigned char *addr)
defb05b9
GR		 2056{
2057 int i, ret;
2058
2059 for (i = 0; i < 3; i++) {
fad09c73 2060 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
cca8b133 2061 GLOBAL_ATU_MAC_01 + i);
defb05b9
GR		 2062 if (ret < 0)
2063 return ret;
2064 addr[i * 2] = ret >> 8;
2065 addr[i * 2 + 1] = ret & 0xff;
2066 }
2067
2068 return 0;
2069}
2070
fad09c73 2071static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
fd231c82 2072 struct mv88e6xxx_atu_entry *entry)
defb05b9 2073{
6630e236
VD		 2074 int ret;
2075
fad09c73 2076 ret = _mv88e6xxx_atu_wait(chip);
defb05b9
GR		 2077 if (ret < 0)
2078 return ret;
2079
fad09c73 2080 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
defb05b9
GR		 2081 if (ret < 0)
2082 return ret;
2083
fad09c73 2084 ret = _mv88e6xxx_atu_data_write(chip, entry);
fd231c82 2085 if (ret < 0)
87820510
VD		 2086 return ret;
2087
fad09c73 2088 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2089}
87820510 2090
fad09c73 2091static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_chip *chip, int port,
fd231c82
VD		 2092 const unsigned char *addr, u16 vid,
2093 u8 state)
2094{
2095 struct mv88e6xxx_atu_entry entry = { 0 };
3285f9e8
VD		 2096 struct mv88e6xxx_vtu_stu_entry vlan;
2097 int err;
2098
2db9ce1f
VD		 2099 /* Null VLAN ID corresponds to the port private database */
2100 if (vid == 0)
fad09c73 2101 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2db9ce1f 2102 else
fad09c73 2103 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 2104 if (err)
2105 return err;
fd231c82 2106
3285f9e8 2107 entry.fid = vlan.fid;
fd231c82
VD		 2108 entry.state = state;
2109 ether_addr_copy(entry.mac, addr);
2110 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2111 entry.trunk = false;
2112 entry.portv_trunkid = BIT(port);
2113 }
2114
fad09c73 2115 return _mv88e6xxx_atu_load(chip, &entry);
87820510
VD		 2116}
2117
f81ec90f
VD		 2118static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2119 const struct switchdev_obj_port_fdb *fdb,
2120 struct switchdev_trans *trans)
146a3206
VD		 2121{
2122 /* We don't need any dynamic resource from the kernel (yet),
2123 * so skip the prepare phase.
2124 */
2125 return 0;
2126}
2127
f81ec90f
VD		 2128static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2129 const struct switchdev_obj_port_fdb *fdb,
2130 struct switchdev_trans *trans)
87820510 2131{
1f36faf2 2132 int state = is_multicast_ether_addr(fdb->addr) ?
87820510
VD		 2133 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2134 GLOBAL_ATU_DATA_STATE_UC_STATIC;
fad09c73 2135 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
87820510 2136
fad09c73
VD		 2137 mutex_lock(&chip->reg_lock);
2138 if (_mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, state))
c8b09808
AL		 2139 netdev_err(ds->ports[port].netdev,
2140 "failed to load MAC address\n");
fad09c73 2141 mutex_unlock(&chip->reg_lock);
87820510
VD		 2142}
2143
f81ec90f
VD		 2144static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2145 const struct switchdev_obj_port_fdb *fdb)
87820510 2146{
fad09c73 2147 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
87820510
VD		 2148 int ret;
2149
fad09c73
VD		 2150 mutex_lock(&chip->reg_lock);
2151 ret = _mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid,
cdf09697 2152 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 2153 mutex_unlock(&chip->reg_lock);
87820510
VD		 2154
2155 return ret;
2156}
2157
fad09c73 2158static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
1d194046 2159 struct mv88e6xxx_atu_entry *entry)
6630e236 2160{
1d194046
VD		 2161 struct mv88e6xxx_atu_entry next = { 0 };
2162 int ret;
2163
2164 next.fid = fid;
defb05b9 2165
fad09c73 2166 ret = _mv88e6xxx_atu_wait(chip);
cdf09697
DM		 2167 if (ret < 0)
2168 return ret;
6630e236 2169
fad09c73 2170 ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
1d194046
VD		 2171 if (ret < 0)
2172 return ret;
6630e236 2173
fad09c73 2174 ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
1d194046
VD		 2175 if (ret < 0)
2176 return ret;
6630e236 2177
fad09c73 2178 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
cdf09697
DM		 2179 if (ret < 0)
2180 return ret;
6630e236 2181
1d194046
VD		 2182 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2183 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2184 unsigned int mask, shift;
2185
2186 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2187 next.trunk = true;
2188 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2189 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2190 } else {
2191 next.trunk = false;
2192 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2193 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2194 }
2195
2196 next.portv_trunkid = (ret & mask) >> shift;
2197 }
cdf09697 2198
1d194046 2199 *entry = next;
cdf09697
DM		 2200 return 0;
2201}
2202
fad09c73 2203static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_chip *chip,
158bc065 2204 u16 fid, u16 vid, int port,
74b6ba0d
VD		 2205 struct switchdev_obj_port_fdb *fdb,
2206 int (*cb)(struct switchdev_obj *obj))
2207{
2208 struct mv88e6xxx_atu_entry addr = {
2209 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2210 };
2211 int err;
2212
fad09c73 2213 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
74b6ba0d
VD		 2214 if (err)
2215 return err;
2216
2217 do {
fad09c73 2218 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
74b6ba0d
VD		 2219 if (err)
2220 break;
2221
2222 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2223 break;
2224
2225 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2226 bool is_static = addr.state ==
2227 (is_multicast_ether_addr(addr.mac) ?
2228 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2229 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2230
2231 fdb->vid = vid;
2232 ether_addr_copy(fdb->addr, addr.mac);
2233 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2234
2235 err = cb(&fdb->obj);
2236 if (err)
2237 break;
2238 }
2239 } while (!is_broadcast_ether_addr(addr.mac));
2240
2241 return err;
2242}
2243
f81ec90f
VD		 2244static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2245 struct switchdev_obj_port_fdb *fdb,
2246 int (*cb)(struct switchdev_obj *obj))
f33475bd 2247{
fad09c73 2248 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f33475bd
VD		 2249 struct mv88e6xxx_vtu_stu_entry vlan = {
2250 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2251 };
2db9ce1f 2252 u16 fid;
f33475bd
VD		 2253 int err;
2254
fad09c73 2255 mutex_lock(&chip->reg_lock);
f33475bd 2256
2db9ce1f 2257 /* Dump port's default Filtering Information Database (VLAN ID 0) */
fad09c73 2258 err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2db9ce1f
VD		 2259 if (err)
2260 goto unlock;
2261
fad09c73 2262 err = _mv88e6xxx_port_fdb_dump_one(chip, fid, 0, port, fdb, cb);
2db9ce1f
VD		 2263 if (err)
2264 goto unlock;
2265
74b6ba0d 2266 /* Dump VLANs' Filtering Information Databases */
fad09c73 2267 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd
VD		 2268 if (err)
2269 goto unlock;
2270
2271 do {
fad09c73 2272 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2273 if (err)
74b6ba0d 2274 break;
f33475bd
VD		 2275
2276 if (!vlan.valid)
2277 break;
2278
fad09c73
VD		 2279 err = _mv88e6xxx_port_fdb_dump_one(chip, vlan.fid, vlan.vid,
2280 port, fdb, cb);
f33475bd 2281 if (err)
74b6ba0d 2282 break;
f33475bd
VD		 2283 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2284
2285unlock:
fad09c73 2286 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2287
2288 return err;
2289}
2290
f81ec90f
VD		 2291static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2292 struct net_device *bridge)
e79a8bcb 2293{
fad09c73 2294 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1d9619d5 2295 int i, err = 0;
466dfa07 2296
fad09c73 2297 mutex_lock(&chip->reg_lock);
466dfa07 2298
b7666efe 2299 /* Assign the bridge and remap each port's VLANTable */
fad09c73 2300 chip->ports[port].bridge_dev = bridge;
b7666efe 2301
fad09c73
VD		 2302 for (i = 0; i < chip->info->num_ports; ++i) {
2303 if (chip->ports[i].bridge_dev == bridge) {
2304 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2305 if (err)
2306 break;
2307 }
2308 }
2309
fad09c73 2310 mutex_unlock(&chip->reg_lock);
a6692754 2311
466dfa07 2312 return err;
e79a8bcb
VD		 2313}
2314
f81ec90f 2315static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2316{
fad09c73
VD		 2317 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2318 struct net_device *bridge = chip->ports[port].bridge_dev;
16bfa702 2319 int i;
466dfa07 2320
fad09c73 2321 mutex_lock(&chip->reg_lock);
466dfa07 2322
b7666efe 2323 /* Unassign the bridge and remap each port's VLANTable */
fad09c73 2324 chip->ports[port].bridge_dev = NULL;
b7666efe 2325
fad09c73
VD		 2326 for (i = 0; i < chip->info->num_ports; ++i)
2327 if (i == port || chip->ports[i].bridge_dev == bridge)
2328 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2329 netdev_warn(ds->ports[i].netdev,
2330 "failed to remap\n");
b7666efe 2331
fad09c73 2332 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2333}
2334
fad09c73 2335static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
552238b5 2336{
fad09c73 2337 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
552238b5 2338 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
fad09c73 2339 struct gpio_desc *gpiod = chip->reset;
552238b5
VD		 2340 unsigned long timeout;
2341 int ret;
2342 int i;
2343
2344 /* Set all ports to the disabled state. */
fad09c73
VD		 2345 for (i = 0; i < chip->info->num_ports; i++) {
2346 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
552238b5
VD		 2347 if (ret < 0)
2348 return ret;
2349
fad09c73 2350 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
552238b5
VD		 2351 ret & 0xfffc);
2352 if (ret)
2353 return ret;
2354 }
2355
2356 /* Wait for transmit queues to drain. */
2357 usleep_range(2000, 4000);
2358
2359 /* If there is a gpio connected to the reset pin, toggle it */
2360 if (gpiod) {
2361 gpiod_set_value_cansleep(gpiod, 1);
2362 usleep_range(10000, 20000);
2363 gpiod_set_value_cansleep(gpiod, 0);
2364 usleep_range(10000, 20000);
2365 }
2366
2367 /* Reset the switch. Keep the PPU active if requested. The PPU
2368 * needs to be active to support indirect phy register access
2369 * through global registers 0x18 and 0x19.
2370 */
2371 if (ppu_active)
fad09c73 2372 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
552238b5 2373 else
fad09c73 2374 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
552238b5
VD		 2375 if (ret)
2376 return ret;
2377
2378 /* Wait up to one second for reset to complete. */
2379 timeout = jiffies + 1 * HZ;
2380 while (time_before(jiffies, timeout)) {
fad09c73 2381 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
552238b5
VD		 2382 if (ret < 0)
2383 return ret;
2384
2385 if ((ret & is_reset) == is_reset)
2386 break;
2387 usleep_range(1000, 2000);
2388 }
2389 if (time_after(jiffies, timeout))
2390 ret = -ETIMEDOUT;
2391 else
2392 ret = 0;
2393
2394 return ret;
2395}
2396
09cb7dfd 2397static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
13a7ebb3 2398{
09cb7dfd
VD		 2399 u16 val;
2400 int err;
13a7ebb3 2401
09cb7dfd
VD		 2402 /* Clear Power Down bit */
2403 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2404 if (err)
2405 return err;
13a7ebb3 2406
09cb7dfd
VD		 2407 if (val & BMCR_PDOWN) {
2408 val &= ~BMCR_PDOWN;
2409 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
13a7ebb3
PU		 2410 }
2411
09cb7dfd 2412 return err;
13a7ebb3
PU		 2413}
2414
8f6345b2
VD		 2415static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port,
2416 int reg, u16 *val)
2417{
2418 int addr = chip->info->port_base_addr + port;
2419
2420 if (port >= chip->info->num_ports)
2421 return -EINVAL;
2422
2423 return mv88e6xxx_read(chip, addr, reg, val);
2424}
2425
fad09c73 2426static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2427{
fad09c73 2428 struct dsa_switch *ds = chip->ds;
f02bdffc 2429 int ret;
54d792f2 2430 u16 reg;
d827e88a 2431
fad09c73
VD		 2432 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2433 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2434 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2435 mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2436 /* MAC Forcing register: don't force link, speed,
2437 * duplex or flow control state to any particular
2438 * values on physical ports, but force the CPU port
2439 * and all DSA ports to their maximum bandwidth and
2440 * full duplex.
2441 */
fad09c73 2442 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
60045cbf 2443 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 2444 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 2445 reg |= PORT_PCS_CTRL_FORCE_LINK |
2446 PORT_PCS_CTRL_LINK_UP |
2447 PORT_PCS_CTRL_DUPLEX_FULL |
2448 PORT_PCS_CTRL_FORCE_DUPLEX;
fad09c73 2449 if (mv88e6xxx_6065_family(chip))
54d792f2
AL		 2450 reg |= PORT_PCS_CTRL_100;
2451 else
2452 reg |= PORT_PCS_CTRL_1000;
2453 } else {
2454 reg |= PORT_PCS_CTRL_UNFORCED;
2455 }
2456
fad09c73 2457 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2458 PORT_PCS_CTRL, reg);
2459 if (ret)
a1a6a4d1 2460 return ret;
54d792f2
AL		 2461 }
2462
2463 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2464 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2465 * tunneling, determine priority by looking at 802.1p and IP
2466 * priority fields (IP prio has precedence), and set STP state
2467 * to Forwarding.
2468 *
2469 * If this is the CPU link, use DSA or EDSA tagging depending
2470 * on which tagging mode was configured.
2471 *
2472 * If this is a link to another switch, use DSA tagging mode.
2473 *
2474 * If this is the upstream port for this switch, enable
2475 * forwarding of unknown unicasts and multicasts.
2476 */
2477 reg = 0;
fad09c73
VD		 2478 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2479 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2480 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2481 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2482 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2483 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2484 PORT_CONTROL_STATE_FORWARDING;
2485 if (dsa_is_cpu_port(ds, port)) {
fad09c73 2486 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip))
54d792f2 2487 reg |= PORT_CONTROL_DSA_TAG;
fad09c73
VD		 2488 if (mv88e6xxx_6352_family(chip) ||
2489 mv88e6xxx_6351_family(chip) ||
2490 mv88e6xxx_6165_family(chip) ||
2491 mv88e6xxx_6097_family(chip) ||
2492 mv88e6xxx_6320_family(chip)) {
5377b802
AL		 2493 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2494 PORT_CONTROL_FORWARD_UNKNOWN |
c047a1f9 2495 PORT_CONTROL_FORWARD_UNKNOWN_MC;
54d792f2
AL		 2496 }
2497
fad09c73
VD		 2498 if (mv88e6xxx_6352_family(chip) ||
2499 mv88e6xxx_6351_family(chip) ||
2500 mv88e6xxx_6165_family(chip) ||
2501 mv88e6xxx_6097_family(chip) ||
2502 mv88e6xxx_6095_family(chip) ||
2503 mv88e6xxx_6065_family(chip) ||
2504 mv88e6xxx_6185_family(chip) ||
2505 mv88e6xxx_6320_family(chip)) {
57d32310 2506 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
54d792f2
AL		 2507 }
2508 }
6083ce71 2509 if (dsa_is_dsa_port(ds, port)) {
fad09c73
VD		 2510 if (mv88e6xxx_6095_family(chip) ||
2511 mv88e6xxx_6185_family(chip))
6083ce71 2512 reg |= PORT_CONTROL_DSA_TAG;
fad09c73
VD		 2513 if (mv88e6xxx_6352_family(chip) ||
2514 mv88e6xxx_6351_family(chip) ||
2515 mv88e6xxx_6165_family(chip) ||
2516 mv88e6xxx_6097_family(chip) ||
2517 mv88e6xxx_6320_family(chip)) {
54d792f2 2518 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2519 }
2520
54d792f2
AL		 2521 if (port == dsa_upstream_port(ds))
2522 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2523 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2524 }
2525 if (reg) {
fad09c73 2526 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2527 PORT_CONTROL, reg);
2528 if (ret)
a1a6a4d1 2529 return ret;
54d792f2
AL		 2530 }
2531
13a7ebb3
PU		 2532 /* If this port is connected to a SerDes, make sure the SerDes is not
2533 * powered down.
2534 */
09cb7dfd 2535 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
fad09c73 2536 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
13a7ebb3 2537 if (ret < 0)
a1a6a4d1 2538 return ret;
13a7ebb3
PU		 2539 ret &= PORT_STATUS_CMODE_MASK;
2540 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2541 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2542 (ret == PORT_STATUS_CMODE_SGMII)) {
09cb7dfd 2543 ret = mv88e6xxx_serdes_power_on(chip);
13a7ebb3 2544 if (ret < 0)
a1a6a4d1 2545 return ret;
13a7ebb3
PU		 2546 }
2547 }
2548
8efdda4a 2549 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2550 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2551 * untagged frames on this port, do a destination address lookup on all
2552 * received packets as usual, disable ARP mirroring and don't send a
2553 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2554 */
2555 reg = 0;
fad09c73
VD		 2556 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2557 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2558 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2559 mv88e6xxx_6185_family(chip))
54d792f2
AL		 2560 reg = PORT_CONTROL_2_MAP_DA;
2561
fad09c73
VD		 2562 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2563 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2564 reg |= PORT_CONTROL_2_JUMBO_10240;
2565
fad09c73 2566 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
54d792f2
AL		 2567 /* Set the upstream port this port should use */
2568 reg |= dsa_upstream_port(ds);
2569 /* enable forwarding of unknown multicast addresses to
2570 * the upstream port
2571 */
2572 if (port == dsa_upstream_port(ds))
2573 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2574 }
2575
46fbe5e5 2576 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2577
54d792f2 2578 if (reg) {
fad09c73 2579 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2580 PORT_CONTROL_2, reg);
2581 if (ret)
a1a6a4d1 2582 return ret;
54d792f2
AL		 2583 }
2584
2585 /* Port Association Vector: when learning source addresses
2586 * of packets, add the address to the address database using
2587 * a port bitmap that has only the bit for this port set and
2588 * the other bits clear.
2589 */
4c7ea3c0 2590 reg = 1 << port;
996ecb82
VD		 2591 /* Disable learning for CPU port */
2592 if (dsa_is_cpu_port(ds, port))
65fa4027 2593 reg = 0;
4c7ea3c0 2594
fad09c73
VD		 2595 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2596 reg);
54d792f2 2597 if (ret)
a1a6a4d1 2598 return ret;
54d792f2
AL		 2599
2600 /* Egress rate control 2: disable egress rate control. */
fad09c73 2601 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
54d792f2
AL		 2602 0x0000);
2603 if (ret)
a1a6a4d1 2604 return ret;
54d792f2 2605
fad09c73
VD		 2606 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2607 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2608 mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2609 /* Do not limit the period of time that this port can
2610 * be paused for by the remote end or the period of
2611 * time that this port can pause the remote end.
2612 */
fad09c73 2613 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2614 PORT_PAUSE_CTRL, 0x0000);
2615 if (ret)
a1a6a4d1 2616 return ret;
54d792f2
AL		 2617
2618 /* Port ATU control: disable limiting the number of
2619 * address database entries that this port is allowed
2620 * to use.
2621 */
fad09c73 2622 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2623 PORT_ATU_CONTROL, 0x0000);
2624 /* Priority Override: disable DA, SA and VTU priority
2625 * override.
2626 */
fad09c73 2627 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2628 PORT_PRI_OVERRIDE, 0x0000);
2629 if (ret)
a1a6a4d1 2630 return ret;
54d792f2
AL		 2631
2632 /* Port Ethertype: use the Ethertype DSA Ethertype
2633 * value.
2634 */
fad09c73 2635 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2636 PORT_ETH_TYPE, ETH_P_EDSA);
2637 if (ret)
a1a6a4d1 2638 return ret;
54d792f2
AL		 2639 /* Tag Remap: use an identity 802.1p prio -> switch
2640 * prio mapping.
2641 */
fad09c73 2642 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2643 PORT_TAG_REGMAP_0123, 0x3210);
2644 if (ret)
a1a6a4d1 2645 return ret;
54d792f2
AL		 2646
2647 /* Tag Remap 2: use an identity 802.1p prio -> switch
2648 * prio mapping.
2649 */
fad09c73 2650 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2651 PORT_TAG_REGMAP_4567, 0x7654);
2652 if (ret)
a1a6a4d1 2653 return ret;
54d792f2
AL		 2654 }
2655
fad09c73
VD		 2656 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2657 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2658 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2659 mv88e6xxx_6320_family(chip)) {
54d792f2 2660 /* Rate Control: disable ingress rate limiting. */
fad09c73 2661 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2662 PORT_RATE_CONTROL, 0x0001);
2663 if (ret)
a1a6a4d1 2664 return ret;
54d792f2
AL		 2665 }
2666
366f0a0f
GR		 2667 /* Port Control 1: disable trunking, disable sending
2668 * learning messages to this port.
d827e88a 2669 */
fad09c73
VD		 2670 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2671 0x0000);
d827e88a 2672 if (ret)
a1a6a4d1 2673 return ret;
d827e88a 2674
207afda1 2675 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2676 * database, and allow bidirectional communication between the
2677 * CPU and DSA port(s), and the other ports.
d827e88a 2678 */
fad09c73 2679 ret = _mv88e6xxx_port_fid_set(chip, port, 0);
2db9ce1f 2680 if (ret)
a1a6a4d1 2681 return ret;
2db9ce1f 2682
fad09c73 2683 ret = _mv88e6xxx_port_based_vlan_map(chip, port);
d827e88a 2684 if (ret)
a1a6a4d1 2685 return ret;
d827e88a
GR		 2686
2687 /* Default VLAN ID and priority: don't set a default VLAN
2688 * ID, and set the default packet priority to zero.
2689 */
fad09c73 2690 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
47cf1e65 2691 0x0000);
a1a6a4d1
VD		 2692 if (ret)
2693 return ret;
dbde9e66 2694
dbde9e66
AL		 2695 return 0;
2696}
2697
3b4caa1b
VD		 2698static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2699{
2700 int err;
2701
2702 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
2703 (addr[0] << 8) | addr[1]);
2704 if (err)
2705 return err;
2706
2707 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
2708 (addr[2] << 8) | addr[3]);
2709 if (err)
2710 return err;
2711
2712 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
2713 (addr[4] << 8) | addr[5]);
2714}
2715
acddbd21
VD		 2716static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2717 unsigned int msecs)
2718{
2719 const unsigned int coeff = chip->info->age_time_coeff;
2720 const unsigned int min = 0x01 * coeff;
2721 const unsigned int max = 0xff * coeff;
2722 u8 age_time;
2723 u16 val;
2724 int err;
2725
2726 if (msecs < min || msecs > max)
2727 return -ERANGE;
2728
2729 /* Round to nearest multiple of coeff */
2730 age_time = (msecs + coeff / 2) / coeff;
2731
2732 err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val);
2733 if (err)
2734 return err;
2735
2736 /* AgeTime is 11:4 bits */
2737 val &= ~0xff0;
2738 val |= age_time << 4;
2739
2740 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val);
2741}
2742
2cfcd964
VD		 2743static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2744 unsigned int ageing_time)
2745{
2746 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2747 int err;
2748
2749 mutex_lock(&chip->reg_lock);
2750 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2751 mutex_unlock(&chip->reg_lock);
2752
2753 return err;
2754}
2755
9729934c 2756static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2757{
fad09c73 2758 struct dsa_switch *ds = chip->ds;
b0745e87 2759 u32 upstream_port = dsa_upstream_port(ds);
119477bd 2760 u16 reg;
552238b5 2761 int err;
54d792f2 2762
119477bd
VD		 2763 /* Enable the PHY Polling Unit if present, don't discard any packets,
2764 * and mask all interrupt sources.
2765 */
2766 reg = 0;
fad09c73
VD		 2767 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2768 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
119477bd
VD		 2769 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2770
fad09c73 2771 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
119477bd
VD		 2772 if (err)
2773 return err;
2774
b0745e87
VD		 2775 /* Configure the upstream port, and configure it as the port to which
2776 * ingress and egress and ARP monitor frames are to be sent.
2777 */
2778 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2779 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2780 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
fad09c73
VD		 2781 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
2782 reg);
b0745e87
VD		 2783 if (err)
2784 return err;
2785
50484ff4 2786 /* Disable remote management, and set the switch's DSA device number. */
fad09c73 2787 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
50484ff4
VD		 2788 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2789 (ds->index & 0x1f));
2790 if (err)
2791 return err;
2792
acddbd21
VD		 2793 /* Clear all the VTU and STU entries */
2794 err = _mv88e6xxx_vtu_stu_flush(chip);
2795 if (err < 0)
2796 return err;
2797
54d792f2
AL		 2798 /* Set the default address aging time to 5 minutes, and
2799 * enable address learn messages to be sent to all message
2800 * ports.
2801 */
acddbd21
VD		 2802 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2803 GLOBAL_ATU_CONTROL_LEARN2ALL);
48ace4ef 2804 if (err)
08a01261 2805 return err;
54d792f2 2806
acddbd21
VD		 2807 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2808 if (err)
9729934c
VD		 2809 return err;
2810
2811 /* Clear all ATU entries */
2812 err = _mv88e6xxx_atu_flush(chip, 0, true);
2813 if (err)
2814 return err;
2815
54d792f2 2816 /* Configure the IP ToS mapping registers. */
fad09c73 2817 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2818 if (err)
08a01261 2819 return err;
fad09c73 2820 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2821 if (err)
08a01261 2822 return err;
fad09c73 2823 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2824 if (err)
08a01261 2825 return err;
fad09c73 2826 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2827 if (err)
08a01261 2828 return err;
fad09c73 2829 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2830 if (err)
08a01261 2831 return err;
fad09c73 2832 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2833 if (err)
08a01261 2834 return err;
fad09c73 2835 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2836 if (err)
08a01261 2837 return err;
fad09c73 2838 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2839 if (err)
08a01261 2840 return err;
54d792f2
AL		 2841
2842 /* Configure the IEEE 802.1p priority mapping register. */
fad09c73 2843 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2844 if (err)
08a01261 2845 return err;
54d792f2 2846
9729934c
VD		 2847 /* Clear the statistics counters for all ports */
2848 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
2849 GLOBAL_STATS_OP_FLUSH_ALL);
2850 if (err)
2851 return err;
2852
2853 /* Wait for the flush to complete. */
2854 err = _mv88e6xxx_stats_wait(chip);
2855 if (err)
2856 return err;
2857
2858 return 0;
2859}
2860
f22ab641
VD		 2861static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
2862 int target, int port)
2863{
2864 u16 val = (target << 8) | (port & 0xf);
2865
2866 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val);
2867}
2868
2869static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
2870{
2871 int target, port;
2872 int err;
2873
2874 /* Initialize the routing port to the 32 possible target devices */
2875 for (target = 0; target < 32; ++target) {
2876 port = 0xf;
2877
2878 if (target < DSA_MAX_SWITCHES) {
2879 port = chip->ds->rtable[target];
2880 if (port == DSA_RTABLE_NONE)
2881 port = 0xf;
2882 }
2883
2884 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
2885 if (err)
2886 break;
2887 }
2888
2889 return err;
2890}
2891
5154041f
VD		 2892static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
2893 bool hask, u16 mask)
2894{
2895 const u16 port_mask = BIT(chip->info->num_ports) - 1;
2896 u16 val = (num << 12) | (mask & port_mask);
2897
2898 if (hask)
2899 val |= GLOBAL2_TRUNK_MASK_HASK;
2900
2901 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val);
2902}
2903
2904static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
2905 u16 map)
2906{
2907 const u16 port_mask = BIT(chip->info->num_ports) - 1;
2908 u16 val = (id << 11) | (map & port_mask);
2909
2910 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val);
2911}
2912
2913static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
2914{
2915 const u16 port_mask = BIT(chip->info->num_ports) - 1;
2916 int i, err;
2917
2918 /* Clear all eight possible Trunk Mask vectors */
2919 for (i = 0; i < 8; ++i) {
2920 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
2921 if (err)
2922 return err;
2923 }
2924
2925 /* Clear all sixteen possible Trunk ID routing vectors */
2926 for (i = 0; i < 16; ++i) {
2927 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
2928 if (err)
2929 return err;
2930 }
2931
2932 return 0;
2933}
2934
8ec61c7f
VD		 2935static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
2936{
2937 int port, err;
2938
2939 /* Init all Ingress Rate Limit resources of all ports */
2940 for (port = 0; port < chip->info->num_ports; ++port) {
2941 /* XXX newer chips (like 88E6390) have different 2-bit ops */
2942 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2943 GLOBAL2_IRL_CMD_OP_INIT_ALL |
2944 (port << 8));
2945 if (err)
2946 break;
2947
2948 /* Wait for the operation to complete */
2d79af6e
VD		 2949 err = mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2950 GLOBAL2_IRL_CMD_BUSY);
8ec61c7f
VD		 2951 if (err)
2952 break;
2953 }
2954
2955 return err;
2956}
2957
3b4caa1b
VD		 2958/* Indirect write to the Switch MAC/WoL/WoF register */
2959static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
2960 unsigned int pointer, u8 data)
2961{
2962 u16 val = (pointer << 8) | data;
2963
2964 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val);
2965}
2966
2967static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2968{
2969 int i, err;
2970
2971 for (i = 0; i < 6; i++) {
2972 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
2973 if (err)
2974 break;
2975 }
2976
2977 return err;
2978}
2979
9bda889f
VD		 2980static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
2981 u8 data)
2982{
2983 u16 val = (pointer << 8) | (data & 0x7);
2984
2985 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, val);
2986}
2987
2988static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
2989{
2990 int i, err;
2991
2992 /* Clear all sixteen possible Priority Override entries */
2993 for (i = 0; i < 16; i++) {
2994 err = mv88e6xxx_g2_pot_write(chip, i, 0);
2995 if (err)
2996 break;
2997 }
2998
2999 return err;
3000}
3001
855b1932
VD		 3002static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
3003{
2d79af6e
VD		 3004 return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD,
3005 GLOBAL2_EEPROM_CMD_BUSY |
3006 GLOBAL2_EEPROM_CMD_RUNNING);
855b1932
VD		 3007}
3008
3009static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3010{
3011 int err;
3012
3013 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, cmd);
3014 if (err)
3015 return err;
3016
3017 return mv88e6xxx_g2_eeprom_wait(chip);
3018}
3019
3020static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
3021 u8 addr, u16 *data)
3022{
3023 u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr;
3024 int err;
3025
3026 err = mv88e6xxx_g2_eeprom_wait(chip);
3027 if (err)
3028 return err;
3029
3030 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3031 if (err)
3032 return err;
3033
3034 return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3035}
3036
3037static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
3038 u8 addr, u16 data)
3039{
3040 u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr;
3041 int err;
3042
3043 err = mv88e6xxx_g2_eeprom_wait(chip);
3044 if (err)
3045 return err;
3046
3047 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3048 if (err)
3049 return err;
3050
3051 return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3052}
3053
57c67cf5
VD		 3054static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
3055{
3056 return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD,
3057 GLOBAL2_SMI_PHY_CMD_BUSY);
3058}
3059
3060static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3061{
3062 int err;
3063
3064 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD, cmd);
3065 if (err)
3066 return err;
3067
3068 return mv88e6xxx_g2_smi_phy_wait(chip);
3069}
3070
3071static int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, int addr,
3072 int reg, u16 *val)
3073{
3074 u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA | (addr << 5) | reg;
3075 int err;
3076
3077 err = mv88e6xxx_g2_smi_phy_wait(chip);
3078 if (err)
3079 return err;
3080
3081 err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
3082 if (err)
3083 return err;
3084
3085 return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
3086}
3087
3088static int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, int addr,
3089 int reg, u16 val)
3090{
3091 u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA | (addr << 5) | reg;
3092 int err;
3093
3094 err = mv88e6xxx_g2_smi_phy_wait(chip);
3095 if (err)
3096 return err;
3097
3098 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
3099 if (err)
3100 return err;
3101
3102 return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
3103}
3104
e57e5e77
VD		 3105static const struct mv88e6xxx_ops mv88e6xxx_g2_smi_phy_ops = {
3106 .read = mv88e6xxx_g2_smi_phy_read,
3107 .write = mv88e6xxx_g2_smi_phy_write,
3108};
3109
9729934c
VD		 3110static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
3111{
47395ed2 3112 u16 reg;
9729934c 3113 int err;
9729934c 3114
47395ed2
VD		 3115 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
3116 /* Consider the frames with reserved multicast destination
3117 * addresses matching 01:80:c2:00:00:2x as MGMT.
3118 */
3119 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
3120 0xffff);
3121 if (err)
3122 return err;
3123 }
3124
3125 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
3126 /* Consider the frames with reserved multicast destination
3127 * addresses matching 01:80:c2:00:00:0x as MGMT.
3128 */
3129 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
3130 0xffff);
3131 if (err)
3132 return err;
3133 }
54d792f2
AL		 3134
3135 /* Ignore removed tag data on doubly tagged packets, disable
3136 * flow control messages, force flow control priority to the
3137 * highest, and send all special multicast frames to the CPU
3138 * port at the highest priority.
3139 */
47395ed2
VD		 3140 reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
3141 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
3142 mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
3143 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
3144 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
48ace4ef 3145 if (err)
08a01261 3146 return err;
54d792f2
AL		 3147
3148 /* Program the DSA routing table. */
f22ab641
VD		 3149 err = mv88e6xxx_g2_set_device_mapping(chip);
3150 if (err)
3151 return err;
54d792f2 3152
5154041f
VD		 3153 /* Clear all trunk masks and mapping. */
3154 err = mv88e6xxx_g2_clear_trunk(chip);
3155 if (err)
3156 return err;
54d792f2 3157
8ec61c7f
VD		 3158 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
3159 /* Disable ingress rate limiting by resetting all per port
3160 * ingress rate limit resources to their initial state.
3161 */
3162 err = mv88e6xxx_g2_clear_irl(chip);
3163 if (err)
3164 return err;
3165 }
3166
63ed880d
VD		 3167 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
3168 /* Initialize Cross-chip Port VLAN Table to reset defaults */
3169 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR,
3170 GLOBAL2_PVT_ADDR_OP_INIT_ONES);
48ace4ef 3171 if (err)
08a01261 3172 return err;
63ed880d 3173 }
54d792f2 3174
9bda889f 3175 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
54d792f2 3176 /* Clear the priority override table. */
9bda889f
VD		 3177 err = mv88e6xxx_g2_clear_pot(chip);
3178 if (err)
3179 return err;
54d792f2
AL		 3180 }
3181
9729934c 3182 return 0;
08a01261
VD		 3183}
3184
f81ec90f 3185static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 3186{
fad09c73 3187 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
08a01261 3188 int err;
a1a6a4d1
VD		 3189 int i;
3190
fad09c73
VD		 3191 chip->ds = ds;
3192 ds->slave_mii_bus = chip->mdio_bus;
08a01261 3193
fad09c73 3194 mutex_lock(&chip->reg_lock);
08a01261 3195
fad09c73 3196 err = mv88e6xxx_switch_reset(chip);
08a01261
VD		 3197 if (err)
3198 goto unlock;
3199
9729934c
VD		 3200 /* Setup Switch Port Registers */
3201 for (i = 0; i < chip->info->num_ports; i++) {
3202 err = mv88e6xxx_setup_port(chip, i);
3203 if (err)
3204 goto unlock;
3205 }
3206
3207 /* Setup Switch Global 1 Registers */
3208 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 3209 if (err)
3210 goto unlock;
3211
9729934c
VD		 3212 /* Setup Switch Global 2 Registers */
3213 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
3214 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 3215 if (err)
3216 goto unlock;
3217 }
08a01261 3218
6b17e864 3219unlock:
fad09c73 3220 mutex_unlock(&chip->reg_lock);
db687a56 3221
48ace4ef 3222 return err;
54d792f2
AL		 3223}
3224
3b4caa1b
VD		 3225static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
3226{
3227 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3228 int err;
3229
3230 mutex_lock(&chip->reg_lock);
3231
3232 /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
3233 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
3234 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
3235 else
3236 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
3237
3238 mutex_unlock(&chip->reg_lock);
3239
3240 return err;
3241}
3242
e57e5e77 3243static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 3244{
fad09c73 3245 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77
VD		 3246 u16 val;
3247 int err;
fd3a0ee4 3248
e57e5e77 3249 if (phy >= chip->info->num_ports)
158bc065 3250 return 0xffff;
fd3a0ee4 3251
fad09c73 3252 mutex_lock(&chip->reg_lock);
e57e5e77 3253 err = mv88e6xxx_phy_read(chip, phy, reg, &val);
fad09c73 3254 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 3255
3256 return err ? err : val;
fd3a0ee4
AL		 3257}
3258
e57e5e77 3259static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 3260{
fad09c73 3261 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77 3262 int err;
fd3a0ee4 3263
e57e5e77 3264 if (phy >= chip->info->num_ports)
158bc065 3265 return 0xffff;
fd3a0ee4 3266
fad09c73 3267 mutex_lock(&chip->reg_lock);
e57e5e77 3268 err = mv88e6xxx_phy_write(chip, phy, reg, val);
fad09c73 3269 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 3270
3271 return err;
fd3a0ee4
AL		 3272}
3273
fad09c73 3274static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
b516d453
AL		 3275 struct device_node *np)
3276{
3277 static int index;
3278 struct mii_bus *bus;
3279 int err;
3280
b516d453 3281 if (np)
fad09c73 3282 chip->mdio_np = of_get_child_by_name(np, "mdio");
b516d453 3283
fad09c73 3284 bus = devm_mdiobus_alloc(chip->dev);
b516d453
AL		 3285 if (!bus)
3286 return -ENOMEM;
3287
fad09c73 3288 bus->priv = (void *)chip;
b516d453
AL		 3289 if (np) {
3290 bus->name = np->full_name;
3291 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3292 } else {
3293 bus->name = "mv88e6xxx SMI";
3294 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3295 }
3296
3297 bus->read = mv88e6xxx_mdio_read;
3298 bus->write = mv88e6xxx_mdio_write;
fad09c73 3299 bus->parent = chip->dev;
b516d453 3300
fad09c73
VD		 3301 if (chip->mdio_np)
3302 err = of_mdiobus_register(bus, chip->mdio_np);
b516d453
AL		 3303 else
3304 err = mdiobus_register(bus);
3305 if (err) {
fad09c73 3306 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
b516d453
AL		 3307 goto out;
3308 }
fad09c73 3309 chip->mdio_bus = bus;
b516d453
AL		 3310
3311 return 0;
3312
3313out:
fad09c73
VD		 3314 if (chip->mdio_np)
3315 of_node_put(chip->mdio_np);
b516d453
AL		 3316
3317 return err;
3318}
3319
fad09c73 3320static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 3321
3322{
fad09c73 3323 struct mii_bus *bus = chip->mdio_bus;
b516d453
AL		 3324
3325 mdiobus_unregister(bus);
3326
fad09c73
VD		 3327 if (chip->mdio_np)
3328 of_node_put(chip->mdio_np);
b516d453
AL		 3329}
3330
c22995c5
GR		 3331#ifdef CONFIG_NET_DSA_HWMON
3332
3333static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3334{
fad09c73 3335 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
9c93829c 3336 u16 val;
c22995c5 3337 int ret;
c22995c5
GR		 3338
3339 *temp = 0;
3340
fad09c73 3341 mutex_lock(&chip->reg_lock);
c22995c5 3342
9c93829c 3343 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
c22995c5
GR		 3344 if (ret < 0)
3345 goto error;
3346
3347 /* Enable temperature sensor */
9c93829c 3348 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
c22995c5
GR		 3349 if (ret < 0)
3350 goto error;
3351
9c93829c 3352 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
c22995c5
GR		 3353 if (ret < 0)
3354 goto error;
3355
3356 /* Wait for temperature to stabilize */
3357 usleep_range(10000, 12000);
3358
9c93829c
VD		 3359 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3360 if (ret < 0)
c22995c5 3361 goto error;
c22995c5
GR		 3362
3363 /* Disable temperature sensor */
9c93829c 3364 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
c22995c5
GR		 3365 if (ret < 0)
3366 goto error;
3367
3368 *temp = ((val & 0x1f) - 5) * 5;
3369
3370error:
9c93829c 3371 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
fad09c73 3372 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3373 return ret;
3374}
3375
3376static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3377{
fad09c73
VD		 3378 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3379 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3380 u16 val;
c22995c5
GR		 3381 int ret;
3382
3383 *temp = 0;
3384
9c93829c
VD		 3385 mutex_lock(&chip->reg_lock);
3386 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3387 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3388 if (ret < 0)
3389 return ret;
3390
9c93829c 3391 *temp = (val & 0xff) - 25;
c22995c5
GR		 3392
3393 return 0;
3394}
3395
f81ec90f 3396static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
c22995c5 3397{
fad09c73 3398 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
158bc065 3399
fad09c73 3400 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
6594f615
VD		 3401 return -EOPNOTSUPP;
3402
fad09c73 3403 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
c22995c5
GR		 3404 return mv88e63xx_get_temp(ds, temp);
3405
3406 return mv88e61xx_get_temp(ds, temp);
3407}
3408
f81ec90f 3409static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
c22995c5 3410{
fad09c73
VD		 3411 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3412 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3413 u16 val;
c22995c5
GR		 3414 int ret;
3415
fad09c73 3416 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3417 return -EOPNOTSUPP;
3418
3419 *temp = 0;
3420
9c93829c
VD		 3421 mutex_lock(&chip->reg_lock);
3422 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3423 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3424 if (ret < 0)
3425 return ret;
3426
9c93829c 3427 *temp = (((val >> 8) & 0x1f) * 5) - 25;
c22995c5
GR		 3428
3429 return 0;
3430}
3431
f81ec90f 3432static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
c22995c5 3433{
fad09c73
VD		 3434 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3435 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c
VD		 3436 u16 val;
3437 int err;
c22995c5 3438
fad09c73 3439 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3440 return -EOPNOTSUPP;
3441
9c93829c
VD		 3442 mutex_lock(&chip->reg_lock);
3443 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3444 if (err)
3445 goto unlock;
c22995c5 3446 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
9c93829c
VD		 3447 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3448 (val & 0xe0ff) | (temp << 8));
3449unlock:
3450 mutex_unlock(&chip->reg_lock);
3451
3452 return err;
c22995c5
GR		 3453}
3454
f81ec90f 3455static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
c22995c5 3456{
fad09c73
VD		 3457 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3458 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3459 u16 val;
c22995c5
GR		 3460 int ret;
3461
fad09c73 3462 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3463 return -EOPNOTSUPP;
3464
3465 *alarm = false;
3466
9c93829c
VD		 3467 mutex_lock(&chip->reg_lock);
3468 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3469 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3470 if (ret < 0)
3471 return ret;
3472
9c93829c 3473 *alarm = !!(val & 0x40);
c22995c5
GR		 3474
3475 return 0;
3476}
3477#endif /* CONFIG_NET_DSA_HWMON */
3478
855b1932
VD		 3479static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3480{
3481 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3482
3483 return chip->eeprom_len;
3484}
3485
3486static int mv88e6xxx_get_eeprom16(struct mv88e6xxx_chip *chip,
3487 struct ethtool_eeprom *eeprom, u8 *data)
3488{
3489 unsigned int offset = eeprom->offset;
3490 unsigned int len = eeprom->len;
3491 u16 val;
3492 int err;
3493
3494 eeprom->len = 0;
3495
3496 if (offset & 1) {
3497 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3498 if (err)
3499 return err;
3500
3501 *data++ = (val >> 8) & 0xff;
3502
3503 offset++;
3504 len--;
3505 eeprom->len++;
3506 }
3507
3508 while (len >= 2) {
3509 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3510 if (err)
3511 return err;
3512
3513 *data++ = val & 0xff;
3514 *data++ = (val >> 8) & 0xff;
3515
3516 offset += 2;
3517 len -= 2;
3518 eeprom->len += 2;
3519 }
3520
3521 if (len) {
3522 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3523 if (err)
3524 return err;
3525
3526 *data++ = val & 0xff;
3527
3528 offset++;
3529 len--;
3530 eeprom->len++;
3531 }
3532
3533 return 0;
3534}
3535
3536static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3537 struct ethtool_eeprom *eeprom, u8 *data)
3538{
3539 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3540 int err;
3541
3542 mutex_lock(&chip->reg_lock);
3543
3544 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3545 err = mv88e6xxx_get_eeprom16(chip, eeprom, data);
3546 else
3547 err = -EOPNOTSUPP;
3548
3549 mutex_unlock(&chip->reg_lock);
3550
3551 if (err)
3552 return err;
3553
3554 eeprom->magic = 0xc3ec4951;
3555
3556 return 0;
3557}
3558
3559static int mv88e6xxx_set_eeprom16(struct mv88e6xxx_chip *chip,
3560 struct ethtool_eeprom *eeprom, u8 *data)
3561{
3562 unsigned int offset = eeprom->offset;
3563 unsigned int len = eeprom->len;
3564 u16 val;
3565 int err;
3566
3567 /* Ensure the RO WriteEn bit is set */
3568 err = mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, &val);
3569 if (err)
3570 return err;
3571
3572 if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN))
3573 return -EROFS;
3574
3575 eeprom->len = 0;
3576
3577 if (offset & 1) {
3578 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3579 if (err)
3580 return err;
3581
3582 val = (*data++ << 8) | (val & 0xff);
3583
3584 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3585 if (err)
3586 return err;
3587
3588 offset++;
3589 len--;
3590 eeprom->len++;
3591 }
3592
3593 while (len >= 2) {
3594 val = *data++;
3595 val |= *data++ << 8;
3596
3597 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3598 if (err)
3599 return err;
3600
3601 offset += 2;
3602 len -= 2;
3603 eeprom->len += 2;
3604 }
3605
3606 if (len) {
3607 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3608 if (err)
3609 return err;
3610
3611 val = (val & 0xff00) | *data++;
3612
3613 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3614 if (err)
3615 return err;
3616
3617 offset++;
3618 len--;
3619 eeprom->len++;
3620 }
3621
3622 return 0;
3623}
3624
3625static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3626 struct ethtool_eeprom *eeprom, u8 *data)
3627{
3628 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3629 int err;
3630
3631 if (eeprom->magic != 0xc3ec4951)
3632 return -EINVAL;
3633
3634 mutex_lock(&chip->reg_lock);
3635
3636 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3637 err = mv88e6xxx_set_eeprom16(chip, eeprom, data);
3638 else
3639 err = -EOPNOTSUPP;
3640
3641 mutex_unlock(&chip->reg_lock);
3642
3643 return err;
3644}
3645
f81ec90f
VD		 3646static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3647 [MV88E6085] = {
3648 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3649 .family = MV88E6XXX_FAMILY_6097,
3650 .name = "Marvell 88E6085",
3651 .num_databases = 4096,
3652 .num_ports = 10,
9dddd478 3653 .port_base_addr = 0x10,
acddbd21 3654 .age_time_coeff = 15000,
f81ec90f
VD		 3655 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3656 },
3657
3658 [MV88E6095] = {
3659 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3660 .family = MV88E6XXX_FAMILY_6095,
3661 .name = "Marvell 88E6095/88E6095F",
3662 .num_databases = 256,
3663 .num_ports = 11,
9dddd478 3664 .port_base_addr = 0x10,
acddbd21 3665 .age_time_coeff = 15000,
f81ec90f
VD		 3666 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3667 },
3668
3669 [MV88E6123] = {
3670 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3671 .family = MV88E6XXX_FAMILY_6165,
3672 .name = "Marvell 88E6123",
3673 .num_databases = 4096,
3674 .num_ports = 3,
9dddd478 3675 .port_base_addr = 0x10,
acddbd21 3676 .age_time_coeff = 15000,
f81ec90f
VD		 3677 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3678 },
3679
3680 [MV88E6131] = {
3681 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3682 .family = MV88E6XXX_FAMILY_6185,
3683 .name = "Marvell 88E6131",
3684 .num_databases = 256,
3685 .num_ports = 8,
9dddd478 3686 .port_base_addr = 0x10,
acddbd21 3687 .age_time_coeff = 15000,
f81ec90f
VD		 3688 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3689 },
3690
3691 [MV88E6161] = {
3692 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3693 .family = MV88E6XXX_FAMILY_6165,
3694 .name = "Marvell 88E6161",
3695 .num_databases = 4096,
3696 .num_ports = 6,
9dddd478 3697 .port_base_addr = 0x10,
acddbd21 3698 .age_time_coeff = 15000,
f81ec90f
VD		 3699 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3700 },
3701
3702 [MV88E6165] = {
3703 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3704 .family = MV88E6XXX_FAMILY_6165,
3705 .name = "Marvell 88E6165",
3706 .num_databases = 4096,
3707 .num_ports = 6,
9dddd478 3708 .port_base_addr = 0x10,
acddbd21 3709 .age_time_coeff = 15000,
f81ec90f
VD		 3710 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3711 },
3712
3713 [MV88E6171] = {
3714 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3715 .family = MV88E6XXX_FAMILY_6351,
3716 .name = "Marvell 88E6171",
3717 .num_databases = 4096,
3718 .num_ports = 7,
9dddd478 3719 .port_base_addr = 0x10,
acddbd21 3720 .age_time_coeff = 15000,
f81ec90f
VD		 3721 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3722 },
3723
3724 [MV88E6172] = {
3725 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3726 .family = MV88E6XXX_FAMILY_6352,
3727 .name = "Marvell 88E6172",
3728 .num_databases = 4096,
3729 .num_ports = 7,
9dddd478 3730 .port_base_addr = 0x10,
acddbd21 3731 .age_time_coeff = 15000,
f81ec90f
VD		 3732 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3733 },
3734
3735 [MV88E6175] = {
3736 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3737 .family = MV88E6XXX_FAMILY_6351,
3738 .name = "Marvell 88E6175",
3739 .num_databases = 4096,
3740 .num_ports = 7,
9dddd478 3741 .port_base_addr = 0x10,
acddbd21 3742 .age_time_coeff = 15000,
f81ec90f
VD		 3743 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3744 },
3745
3746 [MV88E6176] = {
3747 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3748 .family = MV88E6XXX_FAMILY_6352,
3749 .name = "Marvell 88E6176",
3750 .num_databases = 4096,
3751 .num_ports = 7,
9dddd478 3752 .port_base_addr = 0x10,
acddbd21 3753 .age_time_coeff = 15000,
f81ec90f
VD		 3754 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3755 },
3756
3757 [MV88E6185] = {
3758 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3759 .family = MV88E6XXX_FAMILY_6185,
3760 .name = "Marvell 88E6185",
3761 .num_databases = 256,
3762 .num_ports = 10,
9dddd478 3763 .port_base_addr = 0x10,
acddbd21 3764 .age_time_coeff = 15000,
f81ec90f
VD		 3765 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3766 },
3767
3768 [MV88E6240] = {
3769 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3770 .family = MV88E6XXX_FAMILY_6352,
3771 .name = "Marvell 88E6240",
3772 .num_databases = 4096,
3773 .num_ports = 7,
9dddd478 3774 .port_base_addr = 0x10,
acddbd21 3775 .age_time_coeff = 15000,
f81ec90f
VD		 3776 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3777 },
3778
3779 [MV88E6320] = {
3780 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3781 .family = MV88E6XXX_FAMILY_6320,
3782 .name = "Marvell 88E6320",
3783 .num_databases = 4096,
3784 .num_ports = 7,
9dddd478 3785 .port_base_addr = 0x10,
acddbd21 3786 .age_time_coeff = 15000,
f81ec90f
VD		 3787 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3788 },
3789
3790 [MV88E6321] = {
3791 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3792 .family = MV88E6XXX_FAMILY_6320,
3793 .name = "Marvell 88E6321",
3794 .num_databases = 4096,
3795 .num_ports = 7,
9dddd478 3796 .port_base_addr = 0x10,
acddbd21 3797 .age_time_coeff = 15000,
f81ec90f
VD		 3798 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3799 },
3800
3801 [MV88E6350] = {
3802 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3803 .family = MV88E6XXX_FAMILY_6351,
3804 .name = "Marvell 88E6350",
3805 .num_databases = 4096,
3806 .num_ports = 7,
9dddd478 3807 .port_base_addr = 0x10,
acddbd21 3808 .age_time_coeff = 15000,
f81ec90f
VD		 3809 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3810 },
3811
3812 [MV88E6351] = {
3813 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3814 .family = MV88E6XXX_FAMILY_6351,
3815 .name = "Marvell 88E6351",
3816 .num_databases = 4096,
3817 .num_ports = 7,
9dddd478 3818 .port_base_addr = 0x10,
acddbd21 3819 .age_time_coeff = 15000,
f81ec90f
VD		 3820 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3821 },
3822
3823 [MV88E6352] = {
3824 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3825 .family = MV88E6XXX_FAMILY_6352,
3826 .name = "Marvell 88E6352",
3827 .num_databases = 4096,
3828 .num_ports = 7,
9dddd478 3829 .port_base_addr = 0x10,
acddbd21 3830 .age_time_coeff = 15000,
f81ec90f
VD		 3831 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3832 },
3833};
3834
5f7c0367 3835static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3836{
a439c061 3837 int i;
b9b37713 3838
5f7c0367
VD		 3839 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3840 if (mv88e6xxx_table[i].prod_num == prod_num)
3841 return &mv88e6xxx_table[i];
b9b37713 3842
b9b37713
VD		 3843 return NULL;
3844}
3845
fad09c73 3846static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3847{
3848 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3849 unsigned int prod_num, rev;
3850 u16 id;
3851 int err;
bc46a3d5 3852
8f6345b2
VD		 3853 mutex_lock(&chip->reg_lock);
3854 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3855 mutex_unlock(&chip->reg_lock);
3856 if (err)
3857 return err;
bc46a3d5
VD		 3858
3859 prod_num = (id & 0xfff0) >> 4;
3860 rev = id & 0x000f;
3861
3862 info = mv88e6xxx_lookup_info(prod_num);
3863 if (!info)
3864 return -ENODEV;
3865
caac8545 3866 /* Update the compatible info with the probed one */
fad09c73 3867 chip->info = info;
bc46a3d5 3868
fad09c73
VD		 3869 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3870 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 3871
3872 return 0;
3873}
3874
fad09c73 3875static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 3876{
fad09c73 3877 struct mv88e6xxx_chip *chip;
469d729f 3878
fad09c73
VD		 3879 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3880 if (!chip)
469d729f
VD		 3881 return NULL;
3882
fad09c73 3883 chip->dev = dev;
469d729f 3884
fad09c73 3885 mutex_init(&chip->reg_lock);
469d729f 3886
fad09c73 3887 return chip;
469d729f
VD		 3888}
3889
e57e5e77
VD		 3890static const struct mv88e6xxx_ops mv88e6xxx_phy_ops = {
3891 .read = mv88e6xxx_read,
3892 .write = mv88e6xxx_write,
3893};
3894
3895static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3896{
3897 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SMI_PHY)) {
3898 chip->phy_ops = &mv88e6xxx_g2_smi_phy_ops;
3899 } else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3900 chip->phy_ops = &mv88e6xxx_phy_ppu_ops;
3901 mv88e6xxx_ppu_state_init(chip);
3902 } else {
3903 chip->phy_ops = &mv88e6xxx_phy_ops;
3904 }
3905}
3906
fad09c73 3907static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 3908 struct mii_bus *bus, int sw_addr)
3909{
3910 /* ADDR[0] pin is unavailable externally and considered zero */
3911 if (sw_addr & 0x1)
3912 return -EINVAL;
3913
914b32f6 3914 if (sw_addr == 0)
fad09c73 3915 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 3916 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 3917 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 3918 else
3919 return -EINVAL;
3920
fad09c73
VD		 3921 chip->bus = bus;
3922 chip->sw_addr = sw_addr;
4a70c4ab
VD		 3923
3924 return 0;
3925}
3926
7b314362
AL		 3927static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3928{
3929 return DSA_TAG_PROTO_EDSA;
3930}
3931
fcdce7d0
AL		 3932static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3933 struct device *host_dev, int sw_addr,
3934 void **priv)
a77d43f1 3935{
fad09c73 3936 struct mv88e6xxx_chip *chip;
a439c061 3937 struct mii_bus *bus;
b516d453 3938 int err;
a77d43f1 3939
a439c061 3940 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3941 if (!bus)
3942 return NULL;
3943
fad09c73
VD		 3944 chip = mv88e6xxx_alloc_chip(dsa_dev);
3945 if (!chip)
469d729f
VD		 3946 return NULL;
3947
caac8545 3948 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 3949 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 3950
fad09c73 3951 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 3952 if (err)
3953 goto free;
3954
fad09c73 3955 err = mv88e6xxx_detect(chip);
bc46a3d5 3956 if (err)
469d729f 3957 goto free;
a439c061 3958
e57e5e77
VD		 3959 mv88e6xxx_phy_init(chip);
3960
fad09c73 3961 err = mv88e6xxx_mdio_register(chip, NULL);
b516d453 3962 if (err)
469d729f 3963 goto free;
b516d453 3964
fad09c73 3965 *priv = chip;
a439c061 3966
fad09c73 3967 return chip->info->name;
469d729f 3968free:
fad09c73 3969 devm_kfree(dsa_dev, chip);
469d729f
VD		 3970
3971 return NULL;
a77d43f1
AL		 3972}
3973
57d32310 3974static struct dsa_switch_driver mv88e6xxx_switch_driver = {
fcdce7d0 3975 .probe = mv88e6xxx_drv_probe,
7b314362 3976 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 3977 .setup = mv88e6xxx_setup,
3978 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 3979 .adjust_link = mv88e6xxx_adjust_link,
3980 .get_strings = mv88e6xxx_get_strings,
3981 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3982 .get_sset_count = mv88e6xxx_get_sset_count,
3983 .set_eee = mv88e6xxx_set_eee,
3984 .get_eee = mv88e6xxx_get_eee,
3985#ifdef CONFIG_NET_DSA_HWMON
3986 .get_temp = mv88e6xxx_get_temp,
3987 .get_temp_limit = mv88e6xxx_get_temp_limit,
3988 .set_temp_limit = mv88e6xxx_set_temp_limit,
3989 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
3990#endif
f8cd8753 3991 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 3992 .get_eeprom = mv88e6xxx_get_eeprom,
3993 .set_eeprom = mv88e6xxx_set_eeprom,
3994 .get_regs_len = mv88e6xxx_get_regs_len,
3995 .get_regs = mv88e6xxx_get_regs,
2cfcd964 3996 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 3997 .port_bridge_join = mv88e6xxx_port_bridge_join,
3998 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3999 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
4000 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4001 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4002 .port_vlan_add = mv88e6xxx_port_vlan_add,
4003 .port_vlan_del = mv88e6xxx_port_vlan_del,
4004 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4005 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4006 .port_fdb_add = mv88e6xxx_port_fdb_add,
4007 .port_fdb_del = mv88e6xxx_port_fdb_del,
4008 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
4009};
4010
fad09c73 4011static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
b7e66a5f
VD		 4012 struct device_node *np)
4013{
fad09c73 4014 struct device *dev = chip->dev;
b7e66a5f
VD		 4015 struct dsa_switch *ds;
4016
4017 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4018 if (!ds)
4019 return -ENOMEM;
4020
4021 ds->dev = dev;
fad09c73 4022 ds->priv = chip;
b7e66a5f
VD		 4023 ds->drv = &mv88e6xxx_switch_driver;
4024
4025 dev_set_drvdata(dev, ds);
4026
4027 return dsa_register_switch(ds, np);
4028}
4029
fad09c73 4030static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4031{
fad09c73 4032 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 4033}
4034
57d32310 4035static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 4036{
14c7b3c3 4037 struct device *dev = &mdiodev->dev;
f8cd8753 4038 struct device_node *np = dev->of_node;
caac8545 4039 const struct mv88e6xxx_info *compat_info;
fad09c73 4040 struct mv88e6xxx_chip *chip;
f8cd8753 4041 u32 eeprom_len;
52638f71 4042 int err;
14c7b3c3 4043
caac8545
VD		 4044 compat_info = of_device_get_match_data(dev);
4045 if (!compat_info)
4046 return -EINVAL;
4047
fad09c73
VD		 4048 chip = mv88e6xxx_alloc_chip(dev);
4049 if (!chip)
14c7b3c3
AL		 4050 return -ENOMEM;
4051
fad09c73 4052 chip->info = compat_info;
caac8545 4053
fad09c73 4054 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4055 if (err)
4056 return err;
14c7b3c3 4057
fad09c73 4058 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4059 if (err)
4060 return err;
14c7b3c3 4061
e57e5e77
VD		 4062 mv88e6xxx_phy_init(chip);
4063
fad09c73
VD		 4064 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
4065 if (IS_ERR(chip->reset))
4066 return PTR_ERR(chip->reset);
52638f71 4067
855b1932 4068 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
f8cd8753 4069 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4070 chip->eeprom_len = eeprom_len;
f8cd8753 4071
fad09c73 4072 err = mv88e6xxx_mdio_register(chip, np);
b516d453
AL		 4073 if (err)
4074 return err;
4075
fad09c73 4076 err = mv88e6xxx_register_switch(chip, np);
83c0afae 4077 if (err) {
fad09c73 4078 mv88e6xxx_mdio_unregister(chip);
83c0afae
AL		 4079 return err;
4080 }
4081
98e67308
BH		 4082 return 0;
4083}
14c7b3c3
AL		 4084
4085static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4086{
4087 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
fad09c73 4088 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
14c7b3c3 4089
fad09c73
VD		 4090 mv88e6xxx_unregister_switch(chip);
4091 mv88e6xxx_mdio_unregister(chip);
14c7b3c3
AL		 4092}
4093
4094static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4095 {
4096 .compatible = "marvell,mv88e6085",
4097 .data = &mv88e6xxx_table[MV88E6085],
4098 },
14c7b3c3
AL		 4099 { /* sentinel */ },
4100};
4101
4102MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4103
4104static struct mdio_driver mv88e6xxx_driver = {
4105 .probe = mv88e6xxx_probe,
4106 .remove = mv88e6xxx_remove,
4107 .mdiodrv.driver = {
4108 .name = "mv88e6085",
4109 .of_match_table = mv88e6xxx_of_match,
4110 },
4111};
4112
4113static int __init mv88e6xxx_init(void)
4114{
4115 register_switch_driver(&mv88e6xxx_switch_driver);
4116 return mdio_driver_register(&mv88e6xxx_driver);
4117}
98e67308
BH		 4118module_init(mv88e6xxx_init);
4119
4120static void __exit mv88e6xxx_cleanup(void)
4121{
14c7b3c3 4122 mdio_driver_unregister(&mv88e6xxx_driver);
f81ec90f 4123 unregister_switch_driver(&mv88e6xxx_switch_driver);
98e67308
BH		 4124}
4125module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4126
4127MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4128MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4129MODULE_LICENSE("GPL");
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