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net: dsa: mv88e6xxx: make switchdev DB ops generic
[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
19b2f97e 21#include <linux/jiffies.h>
91da11f8 22#include <linux/list.h>
14c7b3c3 23#include <linux/mdio.h>
2bbba277 24#include <linux/module.h>
caac8545 25#include <linux/of_device.h>
b516d453 26#include <linux/of_mdio.h>
91da11f8 27#include <linux/netdevice.h>
c8c1b39a 28#include <linux/gpio/consumer.h>
91da11f8 29#include <linux/phy.h>
c8f0b869 30#include <net/dsa.h>
1f36faf2 31#include <net/switchdev.h>
91da11f8
LB		 32#include "mv88e6xxx.h"
33
fad09c73 34static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 35{
fad09c73
VD		 36 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
37 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 38 dump_stack();
39 }
40}
41
914b32f6
VD		 42/* The switch ADDR[4:1] configuration pins define the chip SMI device address
43 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
44 *
45 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
46 * is the only device connected to the SMI master. In this mode it responds to
47 * all 32 possible SMI addresses, and thus maps directly the internal devices.
48 *
49 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
50 * multiple devices to share the SMI interface. In this mode it responds to only
51 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 52 */
914b32f6 53
fad09c73 54static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 55 int addr, int reg, u16 *val)
56{
fad09c73 57 if (!chip->smi_ops)
914b32f6
VD		 58 return -EOPNOTSUPP;
59
fad09c73 60 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 61}
62
fad09c73 63static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 64 int addr, int reg, u16 val)
65{
fad09c73 66 if (!chip->smi_ops)
914b32f6
VD		 67 return -EOPNOTSUPP;
68
fad09c73 69 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 70}
71
fad09c73 72static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 73 int addr, int reg, u16 *val)
74{
75 int ret;
76
fad09c73 77 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 78 if (ret < 0)
79 return ret;
80
81 *val = ret & 0xffff;
82
83 return 0;
84}
85
fad09c73 86static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 87 int addr, int reg, u16 val)
88{
89 int ret;
90
fad09c73 91 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 92 if (ret < 0)
93 return ret;
94
95 return 0;
96}
97
98static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
99 .read = mv88e6xxx_smi_single_chip_read,
100 .write = mv88e6xxx_smi_single_chip_write,
101};
102
fad09c73 103static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 104{
105 int ret;
106 int i;
107
108 for (i = 0; i < 16; i++) {
fad09c73 109 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 110 if (ret < 0)
111 return ret;
112
cca8b133 113 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 114 return 0;
115 }
116
117 return -ETIMEDOUT;
118}
119
fad09c73 120static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 121 int addr, int reg, u16 *val)
91da11f8
LB		 122{
123 int ret;
124
3675c8d7 125 /* Wait for the bus to become free. */
fad09c73 126 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 127 if (ret < 0)
128 return ret;
129
3675c8d7 130 /* Transmit the read command. */
fad09c73 131 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 132 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 133 if (ret < 0)
134 return ret;
135
3675c8d7 136 /* Wait for the read command to complete. */
fad09c73 137 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 138 if (ret < 0)
139 return ret;
140
3675c8d7 141 /* Read the data. */
fad09c73 142 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 143 if (ret < 0)
144 return ret;
145
914b32f6 146 *val = ret & 0xffff;
91da11f8 147
914b32f6 148 return 0;
8d6d09e7
GR		 149}
150
fad09c73 151static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 152 int addr, int reg, u16 val)
91da11f8
LB		 153{
154 int ret;
155
3675c8d7 156 /* Wait for the bus to become free. */
fad09c73 157 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 158 if (ret < 0)
159 return ret;
160
3675c8d7 161 /* Transmit the data to write. */
fad09c73 162 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 163 if (ret < 0)
164 return ret;
165
3675c8d7 166 /* Transmit the write command. */
fad09c73 167 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 168 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 169 if (ret < 0)
170 return ret;
171
3675c8d7 172 /* Wait for the write command to complete. */
fad09c73 173 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 174 if (ret < 0)
175 return ret;
176
177 return 0;
178}
179
914b32f6
VD		 180static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
181 .read = mv88e6xxx_smi_multi_chip_read,
182 .write = mv88e6xxx_smi_multi_chip_write,
183};
184
fad09c73 185static int mv88e6xxx_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 186 int addr, int reg, u16 *val)
187{
188 int err;
189
fad09c73 190 assert_reg_lock(chip);
914b32f6 191
fad09c73 192 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 193 if (err)
194 return err;
195
fad09c73 196 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 197 addr, reg, *val);
198
199 return 0;
200}
201
fad09c73 202static int mv88e6xxx_write(struct mv88e6xxx_chip *chip,
914b32f6 203 int addr, int reg, u16 val)
91da11f8 204{
914b32f6
VD		 205 int err;
206
fad09c73 207 assert_reg_lock(chip);
91da11f8 208
fad09c73 209 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 210 if (err)
211 return err;
212
fad09c73 213 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 214 addr, reg, val);
215
914b32f6
VD		 216 return 0;
217}
218
e57e5e77
VD		 219static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
220 int reg, u16 *val)
221{
222 int addr = phy; /* PHY devices addresses start at 0x0 */
223
224 if (!chip->phy_ops)
225 return -EOPNOTSUPP;
226
227 return chip->phy_ops->read(chip, addr, reg, val);
228}
229
230static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
231 int reg, u16 val)
232{
233 int addr = phy; /* PHY devices addresses start at 0x0 */
234
235 if (!chip->phy_ops)
236 return -EOPNOTSUPP;
237
238 return chip->phy_ops->write(chip, addr, reg, val);
239}
240
09cb7dfd
VD		 241static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
242{
243 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
244 return -EOPNOTSUPP;
245
246 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
247}
248
249static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
250{
251 int err;
252
253 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
254 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
255 if (unlikely(err)) {
256 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
257 phy, err);
258 }
259}
260
261static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
262 u8 page, int reg, u16 *val)
263{
264 int err;
265
266 /* There is no paging for registers 22 */
267 if (reg == PHY_PAGE)
268 return -EINVAL;
269
270 err = mv88e6xxx_phy_page_get(chip, phy, page);
271 if (!err) {
272 err = mv88e6xxx_phy_read(chip, phy, reg, val);
273 mv88e6xxx_phy_page_put(chip, phy);
274 }
275
276 return err;
277}
278
279static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
280 u8 page, int reg, u16 val)
281{
282 int err;
283
284 /* There is no paging for registers 22 */
285 if (reg == PHY_PAGE)
286 return -EINVAL;
287
288 err = mv88e6xxx_phy_page_get(chip, phy, page);
289 if (!err) {
290 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
291 mv88e6xxx_phy_page_put(chip, phy);
292 }
293
294 return err;
295}
296
297static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
298{
299 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
300 reg, val);
301}
302
303static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
304{
305 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
306 reg, val);
307}
308
2d79af6e
VD		 309static int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg,
310 u16 mask)
311{
6441e669 312 int i;
2d79af6e 313
6441e669 314 for (i = 0; i < 16; i++) {
2d79af6e
VD		 315 u16 val;
316 int err;
317
318 err = mv88e6xxx_read(chip, addr, reg, &val);
319 if (err)
320 return err;
321
322 if (!(val & mask))
323 return 0;
324
325 usleep_range(1000, 2000);
326 }
327
30853553 328 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 329 return -ETIMEDOUT;
330}
331
f22ab641
VD		 332/* Indirect write to single pointer-data register with an Update bit */
333static int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
334 u16 update)
335{
336 u16 val;
0f02b4f7 337 int err;
f22ab641
VD		 338
339 /* Wait until the previous operation is completed */
0f02b4f7
AL		 340 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
341 if (err)
342 return err;
f22ab641
VD		 343
344 /* Set the Update bit to trigger a write operation */
345 val = BIT(15) | update;
346
347 return mv88e6xxx_write(chip, addr, reg, val);
348}
349
fad09c73 350static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
914b32f6
VD		 351{
352 u16 val;
353 int err;
354
fad09c73 355 err = mv88e6xxx_read(chip, addr, reg, &val);
914b32f6
VD		 356 if (err)
357 return err;
358
359 return val;
360}
361
fad09c73 362static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
914b32f6
VD		 363 int reg, u16 val)
364{
fad09c73 365 return mv88e6xxx_write(chip, addr, reg, val);
8d6d09e7
GR		 366}
367
fad09c73 368static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
2e5f0320
LB		 369{
370 int ret;
6441e669 371 int i;
2e5f0320 372
fad09c73 373 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 374 if (ret < 0)
375 return ret;
376
fad09c73 377 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
8c9983a2 378 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 379 if (ret)
380 return ret;
2e5f0320 381
6441e669 382 for (i = 0; i < 16; i++) {
fad09c73 383 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 384 if (ret < 0)
385 return ret;
386
19b2f97e 387 usleep_range(1000, 2000);
cca8b133
AL		 388 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
389 GLOBAL_STATUS_PPU_POLLING)
85686581 390 return 0;
2e5f0320
LB		 391 }
392
393 return -ETIMEDOUT;
394}
395
fad09c73 396static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 397{
6441e669 398 int ret, err, i;
2e5f0320 399
fad09c73 400 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 401 if (ret < 0)
402 return ret;
403
fad09c73 404 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
762eb67b 405 ret | GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 406 if (err)
407 return err;
2e5f0320 408
6441e669 409 for (i = 0; i < 16; i++) {
fad09c73 410 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 411 if (ret < 0)
412 return ret;
413
19b2f97e 414 usleep_range(1000, 2000);
cca8b133
AL		 415 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
416 GLOBAL_STATUS_PPU_POLLING)
85686581 417 return 0;
2e5f0320
LB		 418 }
419
420 return -ETIMEDOUT;
421}
422
423static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
424{
fad09c73 425 struct mv88e6xxx_chip *chip;
2e5f0320 426
fad09c73 427 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 428
fad09c73 429 mutex_lock(&chip->reg_lock);
762eb67b 430
fad09c73
VD		 431 if (mutex_trylock(&chip->ppu_mutex)) {
432 if (mv88e6xxx_ppu_enable(chip) == 0)
433 chip->ppu_disabled = 0;
434 mutex_unlock(&chip->ppu_mutex);
2e5f0320 435 }
762eb67b 436
fad09c73 437 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 438}
439
440static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
441{
fad09c73 442 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 443
fad09c73 444 schedule_work(&chip->ppu_work);
2e5f0320
LB		 445}
446
fad09c73 447static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 448{
2e5f0320
LB		 449 int ret;
450
fad09c73 451 mutex_lock(&chip->ppu_mutex);
2e5f0320 452
3675c8d7 453 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 454 * we can access the PHY registers. If it was already
455 * disabled, cancel the timer that is going to re-enable
456 * it.
457 */
fad09c73
VD		 458 if (!chip->ppu_disabled) {
459 ret = mv88e6xxx_ppu_disable(chip);
85686581 460 if (ret < 0) {
fad09c73 461 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 462 return ret;
463 }
fad09c73 464 chip->ppu_disabled = 1;
2e5f0320 465 } else {
fad09c73 466 del_timer(&chip->ppu_timer);
85686581 467 ret = 0;
2e5f0320
LB		 468 }
469
470 return ret;
471}
472
fad09c73 473static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 474{
3675c8d7 475 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 476 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
477 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 478}
479
fad09c73 480static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 481{
fad09c73
VD		 482 mutex_init(&chip->ppu_mutex);
483 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
484 init_timer(&chip->ppu_timer);
485 chip->ppu_timer.data = (unsigned long)chip;
486 chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
2e5f0320
LB		 487}
488
930188ce
AL		 489static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
490{
491 del_timer_sync(&chip->ppu_timer);
492}
493
e57e5e77
VD		 494static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
495 int reg, u16 *val)
2e5f0320 496{
e57e5e77 497 int err;
2e5f0320 498
e57e5e77
VD		 499 err = mv88e6xxx_ppu_access_get(chip);
500 if (!err) {
501 err = mv88e6xxx_read(chip, addr, reg, val);
fad09c73 502 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 503 }
504
e57e5e77 505 return err;
2e5f0320
LB		 506}
507
e57e5e77
VD		 508static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
509 int reg, u16 val)
2e5f0320 510{
e57e5e77 511 int err;
2e5f0320 512
e57e5e77
VD		 513 err = mv88e6xxx_ppu_access_get(chip);
514 if (!err) {
515 err = mv88e6xxx_write(chip, addr, reg, val);
fad09c73 516 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 517 }
518
e57e5e77 519 return err;
2e5f0320 520}
2e5f0320 521
e57e5e77
VD		 522static const struct mv88e6xxx_ops mv88e6xxx_phy_ppu_ops = {
523 .read = mv88e6xxx_phy_ppu_read,
524 .write = mv88e6xxx_phy_ppu_write,
525};
526
fad09c73 527static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
54d792f2 528{
fad09c73 529 return chip->info->family == MV88E6XXX_FAMILY_6065;
54d792f2
AL		 530}
531
fad09c73 532static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
54d792f2 533{
fad09c73 534 return chip->info->family == MV88E6XXX_FAMILY_6095;
54d792f2
AL		 535}
536
fad09c73 537static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 538{
fad09c73 539 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 540}
541
fad09c73 542static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 543{
fad09c73 544 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 545}
546
fad09c73 547static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
54d792f2 548{
fad09c73 549 return chip->info->family == MV88E6XXX_FAMILY_6185;
54d792f2
AL		 550}
551
fad09c73 552static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
7c3d0d67 553{
fad09c73 554 return chip->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 555}
556
fad09c73 557static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 558{
fad09c73 559 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 560}
561
fad09c73 562static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 563{
fad09c73 564 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 565}
566
fad09c73 567static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
f74df0be 568{
fad09c73 569 return chip->info->num_databases;
f74df0be
VD		 570}
571
fad09c73 572static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
b426e5f7
VD		 573{
574 /* Does the device have dedicated FID registers for ATU and VTU ops? */
fad09c73
VD		 575 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
576 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
b426e5f7
VD		 577 return true;
578
579 return false;
580}
581
dea87024
AL		 582/* We expect the switch to perform auto negotiation if there is a real
583 * phy. However, in the case of a fixed link phy, we force the port
584 * settings from the fixed link settings.
585 */
f81ec90f
VD		 586static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
587 struct phy_device *phydev)
dea87024 588{
fad09c73 589 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
49052871
AL		 590 u32 reg;
591 int ret;
dea87024
AL		 592
593 if (!phy_is_pseudo_fixed_link(phydev))
594 return;
595
fad09c73 596 mutex_lock(&chip->reg_lock);
dea87024 597
fad09c73 598 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
dea87024
AL		 599 if (ret < 0)
600 goto out;
601
602 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
603 PORT_PCS_CTRL_FORCE_LINK |
604 PORT_PCS_CTRL_DUPLEX_FULL |
605 PORT_PCS_CTRL_FORCE_DUPLEX |
606 PORT_PCS_CTRL_UNFORCED);
607
608 reg |= PORT_PCS_CTRL_FORCE_LINK;
609 if (phydev->link)
57d32310 610 reg |= PORT_PCS_CTRL_LINK_UP;
dea87024 611
fad09c73 612 if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
dea87024
AL		 613 goto out;
614
615 switch (phydev->speed) {
616 case SPEED_1000:
617 reg |= PORT_PCS_CTRL_1000;
618 break;
619 case SPEED_100:
620 reg |= PORT_PCS_CTRL_100;
621 break;
622 case SPEED_10:
623 reg |= PORT_PCS_CTRL_10;
624 break;
625 default:
626 pr_info("Unknown speed");
627 goto out;
628 }
629
630 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
631 if (phydev->duplex == DUPLEX_FULL)
632 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
633
fad09c73
VD		 634 if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
635 (port >= chip->info->num_ports - 2)) {
e7e72ac0
AL		 636 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
637 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
638 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
639 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
640 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
641 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
642 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
643 }
fad09c73 644 _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
dea87024
AL		 645
646out:
fad09c73 647 mutex_unlock(&chip->reg_lock);
dea87024
AL		 648}
649
fad09c73 650static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 651{
652 int ret;
653 int i;
654
655 for (i = 0; i < 10; i++) {
fad09c73 656 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
cca8b133 657 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 658 return 0;
659 }
660
661 return -ETIMEDOUT;
662}
663
fad09c73 664static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8
LB		 665{
666 int ret;
667
fad09c73 668 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
f3a8b6b6
AL		 669 port = (port + 1) << 5;
670
3675c8d7 671 /* Snapshot the hardware statistics counters for this port. */
fad09c73 672 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 673 GLOBAL_STATS_OP_CAPTURE_PORT |
674 GLOBAL_STATS_OP_HIST_RX_TX | port);
675 if (ret < 0)
676 return ret;
91da11f8 677
3675c8d7 678 /* Wait for the snapshotting to complete. */
fad09c73 679 ret = _mv88e6xxx_stats_wait(chip);
91da11f8
LB		 680 if (ret < 0)
681 return ret;
682
683 return 0;
684}
685
fad09c73 686static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
158bc065 687 int stat, u32 *val)
91da11f8
LB		 688{
689 u32 _val;
690 int ret;
691
692 *val = 0;
693
fad09c73 694 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 695 GLOBAL_STATS_OP_READ_CAPTURED |
696 GLOBAL_STATS_OP_HIST_RX_TX | stat);
91da11f8
LB		 697 if (ret < 0)
698 return;
699
fad09c73 700 ret = _mv88e6xxx_stats_wait(chip);
91da11f8
LB		 701 if (ret < 0)
702 return;
703
fad09c73 704 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
91da11f8
LB		 705 if (ret < 0)
706 return;
707
708 _val = ret << 16;
709
fad09c73 710 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
91da11f8
LB		 711 if (ret < 0)
712 return;
713
714 *val = _val | ret;
715}
716
e413e7e1 717static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 718 { "in_good_octets", 8, 0x00, BANK0, },
719 { "in_bad_octets", 4, 0x02, BANK0, },
720 { "in_unicast", 4, 0x04, BANK0, },
721 { "in_broadcasts", 4, 0x06, BANK0, },
722 { "in_multicasts", 4, 0x07, BANK0, },
723 { "in_pause", 4, 0x16, BANK0, },
724 { "in_undersize", 4, 0x18, BANK0, },
725 { "in_fragments", 4, 0x19, BANK0, },
726 { "in_oversize", 4, 0x1a, BANK0, },
727 { "in_jabber", 4, 0x1b, BANK0, },
728 { "in_rx_error", 4, 0x1c, BANK0, },
729 { "in_fcs_error", 4, 0x1d, BANK0, },
730 { "out_octets", 8, 0x0e, BANK0, },
731 { "out_unicast", 4, 0x10, BANK0, },
732 { "out_broadcasts", 4, 0x13, BANK0, },
733 { "out_multicasts", 4, 0x12, BANK0, },
734 { "out_pause", 4, 0x15, BANK0, },
735 { "excessive", 4, 0x11, BANK0, },
736 { "collisions", 4, 0x1e, BANK0, },
737 { "deferred", 4, 0x05, BANK0, },
738 { "single", 4, 0x14, BANK0, },
739 { "multiple", 4, 0x17, BANK0, },
740 { "out_fcs_error", 4, 0x03, BANK0, },
741 { "late", 4, 0x1f, BANK0, },
742 { "hist_64bytes", 4, 0x08, BANK0, },
743 { "hist_65_127bytes", 4, 0x09, BANK0, },
744 { "hist_128_255bytes", 4, 0x0a, BANK0, },
745 { "hist_256_511bytes", 4, 0x0b, BANK0, },
746 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
747 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
748 { "sw_in_discards", 4, 0x10, PORT, },
749 { "sw_in_filtered", 2, 0x12, PORT, },
750 { "sw_out_filtered", 2, 0x13, PORT, },
751 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
752 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
753 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
754 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
755 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
756 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
757 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
758 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
759 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
760 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
761 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
762 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
763 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
764 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
765 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
766 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
767 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
768 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
769 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
770 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
771 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
772 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
773 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
774 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
775 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
776 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 777};
778
fad09c73 779static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 780 struct mv88e6xxx_hw_stat *stat)
e413e7e1 781{
f5e2ed02
AL		 782 switch (stat->type) {
783 case BANK0:
e413e7e1 784 return true;
f5e2ed02 785 case BANK1:
fad09c73 786 return mv88e6xxx_6320_family(chip);
f5e2ed02 787 case PORT:
fad09c73
VD		 788 return mv88e6xxx_6095_family(chip) ||
789 mv88e6xxx_6185_family(chip) ||
790 mv88e6xxx_6097_family(chip) ||
791 mv88e6xxx_6165_family(chip) ||
792 mv88e6xxx_6351_family(chip) ||
793 mv88e6xxx_6352_family(chip);
91da11f8 794 }
f5e2ed02 795 return false;
91da11f8
LB		 796}
797
fad09c73 798static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 799 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 800 int port)
801{
80c4627b
AL		 802 u32 low;
803 u32 high = 0;
804 int ret;
805 u64 value;
806
f5e2ed02
AL		 807 switch (s->type) {
808 case PORT:
fad09c73 809 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
80c4627b
AL		 810 if (ret < 0)
811 return UINT64_MAX;
812
813 low = ret;
814 if (s->sizeof_stat == 4) {
fad09c73 815 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
f5e2ed02 816 s->reg + 1);
80c4627b
AL		 817 if (ret < 0)
818 return UINT64_MAX;
819 high = ret;
820 }
f5e2ed02
AL		 821 break;
822 case BANK0:
823 case BANK1:
fad09c73 824 _mv88e6xxx_stats_read(chip, s->reg, &low);
80c4627b 825 if (s->sizeof_stat == 8)
fad09c73 826 _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
80c4627b
AL		 827 }
828 value = (((u64)high) << 16) | low;
829 return value;
830}
831
f81ec90f
VD		 832static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
833 uint8_t *data)
91da11f8 834{
fad09c73 835 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f5e2ed02
AL		 836 struct mv88e6xxx_hw_stat *stat;
837 int i, j;
91da11f8 838
f5e2ed02
AL		 839 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
840 stat = &mv88e6xxx_hw_stats[i];
fad09c73 841 if (mv88e6xxx_has_stat(chip, stat)) {
f5e2ed02
AL		 842 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
843 ETH_GSTRING_LEN);
844 j++;
845 }
91da11f8 846 }
e413e7e1
AL		 847}
848
f81ec90f 849static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
e413e7e1 850{
fad09c73 851 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f5e2ed02
AL		 852 struct mv88e6xxx_hw_stat *stat;
853 int i, j;
854
855 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
856 stat = &mv88e6xxx_hw_stats[i];
fad09c73 857 if (mv88e6xxx_has_stat(chip, stat))
f5e2ed02
AL		 858 j++;
859 }
860 return j;
e413e7e1
AL		 861}
862
f81ec90f
VD		 863static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
864 uint64_t *data)
e413e7e1 865{
fad09c73 866 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f5e2ed02
AL		 867 struct mv88e6xxx_hw_stat *stat;
868 int ret;
869 int i, j;
870
fad09c73 871 mutex_lock(&chip->reg_lock);
f5e2ed02 872
fad09c73 873 ret = _mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 874 if (ret < 0) {
fad09c73 875 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 876 return;
877 }
878 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
879 stat = &mv88e6xxx_hw_stats[i];
fad09c73
VD		 880 if (mv88e6xxx_has_stat(chip, stat)) {
881 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
f5e2ed02
AL		 882 j++;
883 }
884 }
885
fad09c73 886 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 887}
888
f81ec90f 889static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 890{
891 return 32 * sizeof(u16);
892}
893
f81ec90f
VD		 894static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
895 struct ethtool_regs *regs, void *_p)
a1ab91f3 896{
fad09c73 897 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
a1ab91f3
GR		 898 u16 *p = _p;
899 int i;
900
901 regs->version = 0;
902
903 memset(p, 0xff, 32 * sizeof(u16));
904
fad09c73 905 mutex_lock(&chip->reg_lock);
23062513 906
a1ab91f3
GR		 907 for (i = 0; i < 32; i++) {
908 int ret;
909
fad09c73 910 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
a1ab91f3
GR		 911 if (ret >= 0)
912 p[i] = ret;
913 }
23062513 914
fad09c73 915 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 916}
917
fad09c73 918static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
facd95b2 919{
2d79af6e
VD		 920 return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
921 GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 922}
923
f81ec90f
VD		 924static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
925 struct ethtool_eee *e)
11b3b45d 926{
fad09c73 927 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
9c93829c
VD		 928 u16 reg;
929 int err;
11b3b45d 930
fad09c73 931 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 932 return -EOPNOTSUPP;
933
fad09c73 934 mutex_lock(&chip->reg_lock);
2f40c698 935
9c93829c
VD		 936 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
937 if (err)
2f40c698 938 goto out;
11b3b45d
GR		 939
940 e->eee_enabled = !!(reg & 0x0200);
941 e->tx_lpi_enabled = !!(reg & 0x0100);
942
9c93829c
VD		 943 err = mv88e6xxx_read(chip, REG_PORT(port), PORT_STATUS, &reg);
944 if (err)
2f40c698 945 goto out;
11b3b45d 946
cca8b133 947 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 948out:
fad09c73 949 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 950
951 return err;
11b3b45d
GR		 952}
953
f81ec90f
VD		 954static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
955 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 956{
fad09c73 957 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
9c93829c
VD		 958 u16 reg;
959 int err;
11b3b45d 960
fad09c73 961 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 962 return -EOPNOTSUPP;
963
fad09c73 964 mutex_lock(&chip->reg_lock);
11b3b45d 965
9c93829c
VD		 966 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
967 if (err)
2f40c698
AL		 968 goto out;
969
9c93829c 970 reg &= ~0x0300;
2f40c698
AL		 971 if (e->eee_enabled)
972 reg |= 0x0200;
973 if (e->tx_lpi_enabled)
974 reg |= 0x0100;
975
9c93829c 976 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 977out:
fad09c73 978 mutex_unlock(&chip->reg_lock);
2f40c698 979
9c93829c 980 return err;
11b3b45d
GR		 981}
982
fad09c73 983static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
facd95b2
GR		 984{
985 int ret;
986
fad09c73
VD		 987 if (mv88e6xxx_has_fid_reg(chip)) {
988 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
989 fid);
b426e5f7
VD		 990 if (ret < 0)
991 return ret;
fad09c73 992 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f 993 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
fad09c73 994 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
11ea809f
VD		 995 if (ret < 0)
996 return ret;
997
fad09c73 998 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
11ea809f
VD		 999 (ret & 0xfff) |
1000 ((fid << 8) & 0xf000));
1001 if (ret < 0)
1002 return ret;
1003
1004 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1005 cmd |= fid & 0xf;
b426e5f7
VD		 1006 }
1007
fad09c73 1008 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
facd95b2
GR		 1009 if (ret < 0)
1010 return ret;
1011
fad09c73 1012 return _mv88e6xxx_atu_wait(chip);
facd95b2
GR		 1013}
1014
fad09c73 1015static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
37705b73
VD		 1016 struct mv88e6xxx_atu_entry *entry)
1017{
1018 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1019
1020 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1021 unsigned int mask, shift;
1022
1023 if (entry->trunk) {
1024 data |= GLOBAL_ATU_DATA_TRUNK;
1025 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1026 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1027 } else {
1028 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1029 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1030 }
1031
1032 data |= (entry->portv_trunkid << shift) & mask;
1033 }
1034
fad09c73 1035 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
37705b73
VD		 1036}
1037
fad09c73 1038static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
7fb5e755
VD		 1039 struct mv88e6xxx_atu_entry *entry,
1040 bool static_too)
facd95b2 1041{
7fb5e755
VD		 1042 int op;
1043 int err;
facd95b2 1044
fad09c73 1045 err = _mv88e6xxx_atu_wait(chip);
7fb5e755
VD		 1046 if (err)
1047 return err;
facd95b2 1048
fad09c73 1049 err = _mv88e6xxx_atu_data_write(chip, entry);
7fb5e755
VD		 1050 if (err)
1051 return err;
1052
1053 if (entry->fid) {
7fb5e755
VD		 1054 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1055 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1056 } else {
1057 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1058 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1059 }
1060
fad09c73 1061 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
7fb5e755
VD		 1062}
1063
fad09c73 1064static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
158bc065 1065 u16 fid, bool static_too)
7fb5e755
VD		 1066{
1067 struct mv88e6xxx_atu_entry entry = {
1068 .fid = fid,
1069 .state = 0, /* EntryState bits must be 0 */
1070 };
70cc99d1 1071
fad09c73 1072 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
7fb5e755
VD		 1073}
1074
fad09c73 1075static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1076 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1077{
1078 struct mv88e6xxx_atu_entry entry = {
1079 .trunk = false,
1080 .fid = fid,
1081 };
1082
1083 /* EntryState bits must be 0xF */
1084 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1085
1086 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1087 entry.portv_trunkid = (to_port & 0x0f) << 4;
1088 entry.portv_trunkid |= from_port & 0x0f;
1089
fad09c73 1090 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
9f4d55d2
VD		 1091}
1092
fad09c73 1093static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1094 int port, bool static_too)
9f4d55d2
VD		 1095{
1096 /* Destination port 0xF means remove the entries */
fad09c73 1097 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1098}
1099
2d9deae4
VD		 1100static const char * const mv88e6xxx_port_state_names[] = {
1101 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1102 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1103 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1104 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1105};
1106
fad09c73 1107static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
158bc065 1108 u8 state)
facd95b2 1109{
fad09c73 1110 struct dsa_switch *ds = chip->ds;
c3ffe6d2 1111 int reg, ret = 0;
facd95b2
GR		 1112 u8 oldstate;
1113
fad09c73 1114 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
2d9deae4
VD		 1115 if (reg < 0)
1116 return reg;
facd95b2 1117
cca8b133 1118 oldstate = reg & PORT_CONTROL_STATE_MASK;
2d9deae4 1119
facd95b2
GR		 1120 if (oldstate != state) {
1121 /* Flush forwarding database if we're moving a port
1122 * from Learning or Forwarding state to Disabled or
1123 * Blocking or Listening state.
1124 */
2d9deae4 1125 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
57d32310
VD		 1126 oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1127 (state == PORT_CONTROL_STATE_DISABLED ||
1128 state == PORT_CONTROL_STATE_BLOCKING)) {
fad09c73 1129 ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
facd95b2 1130 if (ret)
2d9deae4 1131 return ret;
facd95b2 1132 }
2d9deae4 1133
cca8b133 1134 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
fad09c73 1135 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
cca8b133 1136 reg);
2d9deae4
VD		 1137 if (ret)
1138 return ret;
1139
c8b09808 1140 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
2d9deae4
VD		 1141 mv88e6xxx_port_state_names[state],
1142 mv88e6xxx_port_state_names[oldstate]);
facd95b2
GR		 1143 }
1144
facd95b2
GR		 1145 return ret;
1146}
1147
fad09c73 1148static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1149{
fad09c73
VD		 1150 struct net_device *bridge = chip->ports[port].bridge_dev;
1151 const u16 mask = (1 << chip->info->num_ports) - 1;
1152 struct dsa_switch *ds = chip->ds;
b7666efe 1153 u16 output_ports = 0;
ede8098d 1154 int reg;
b7666efe
VD		 1155 int i;
1156
1157 /* allow CPU port or DSA link(s) to send frames to every port */
1158 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1159 output_ports = mask;
1160 } else {
fad09c73 1161 for (i = 0; i < chip->info->num_ports; ++i) {
b7666efe 1162 /* allow sending frames to every group member */
fad09c73 1163 if (bridge && chip->ports[i].bridge_dev == bridge)
b7666efe
VD		 1164 output_ports |= BIT(i);
1165
1166 /* allow sending frames to CPU port and DSA link(s) */
1167 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1168 output_ports |= BIT(i);
1169 }
1170 }
1171
1172 /* prevent frames from going back out of the port they came in on */
1173 output_ports &= ~BIT(port);
facd95b2 1174
fad09c73 1175 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
ede8098d
VD		 1176 if (reg < 0)
1177 return reg;
facd95b2 1178
ede8098d
VD		 1179 reg &= ~mask;
1180 reg |= output_ports & mask;
facd95b2 1181
fad09c73 1182 return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
facd95b2
GR		 1183}
1184
f81ec90f
VD		 1185static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1186 u8 state)
facd95b2 1187{
fad09c73 1188 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
facd95b2 1189 int stp_state;
553eb544 1190 int err;
facd95b2
GR		 1191
1192 switch (state) {
1193 case BR_STATE_DISABLED:
cca8b133 1194 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1195 break;
1196 case BR_STATE_BLOCKING:
1197 case BR_STATE_LISTENING:
cca8b133 1198 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1199 break;
1200 case BR_STATE_LEARNING:
cca8b133 1201 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1202 break;
1203 case BR_STATE_FORWARDING:
1204 default:
cca8b133 1205 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1206 break;
1207 }
1208
fad09c73
VD		 1209 mutex_lock(&chip->reg_lock);
1210 err = _mv88e6xxx_port_state(chip, port, stp_state);
1211 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1212
1213 if (err)
c8b09808
AL		 1214 netdev_err(ds->ports[port].netdev,
1215 "failed to update state to %s\n",
553eb544 1216 mv88e6xxx_port_state_names[stp_state]);
facd95b2
GR		 1217}
1218
fad09c73 1219static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
158bc065 1220 u16 *new, u16 *old)
76e398a6 1221{
fad09c73 1222 struct dsa_switch *ds = chip->ds;
5da96031 1223 u16 pvid;
76e398a6
VD		 1224 int ret;
1225
fad09c73 1226 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
76e398a6
VD		 1227 if (ret < 0)
1228 return ret;
1229
5da96031
VD		 1230 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1231
1232 if (new) {
1233 ret &= ~PORT_DEFAULT_VLAN_MASK;
1234 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1235
fad09c73 1236 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
5da96031
VD		 1237 PORT_DEFAULT_VLAN, ret);
1238 if (ret < 0)
1239 return ret;
1240
c8b09808
AL		 1241 netdev_dbg(ds->ports[port].netdev,
1242 "DefaultVID %d (was %d)\n", *new, pvid);
5da96031
VD		 1243 }
1244
1245 if (old)
1246 *old = pvid;
76e398a6
VD		 1247
1248 return 0;
1249}
1250
fad09c73 1251static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
158bc065 1252 int port, u16 *pvid)
5da96031 1253{
fad09c73 1254 return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
5da96031
VD		 1255}
1256
fad09c73 1257static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
158bc065 1258 int port, u16 pvid)
0d3b33e6 1259{
fad09c73 1260 return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
0d3b33e6
VD		 1261}
1262
fad09c73 1263static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1264{
2d79af6e
VD		 1265 return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
1266 GLOBAL_VTU_OP_BUSY);
6b17e864
VD		 1267}
1268
fad09c73 1269static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864
VD		 1270{
1271 int ret;
1272
fad09c73 1273 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
6b17e864
VD		 1274 if (ret < 0)
1275 return ret;
1276
fad09c73 1277 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1278}
1279
fad09c73 1280static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1281{
1282 int ret;
1283
fad09c73 1284 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1285 if (ret < 0)
1286 return ret;
1287
fad09c73 1288 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1289}
1290
fad09c73 1291static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b8fee957
VD		 1292 struct mv88e6xxx_vtu_stu_entry *entry,
1293 unsigned int nibble_offset)
1294{
b8fee957
VD		 1295 u16 regs[3];
1296 int i;
1297 int ret;
1298
1299 for (i = 0; i < 3; ++i) {
fad09c73 1300 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
b8fee957
VD		 1301 GLOBAL_VTU_DATA_0_3 + i);
1302 if (ret < 0)
1303 return ret;
1304
1305 regs[i] = ret;
1306 }
1307
fad09c73 1308 for (i = 0; i < chip->info->num_ports; ++i) {
b8fee957
VD		 1309 unsigned int shift = (i % 4) * 4 + nibble_offset;
1310 u16 reg = regs[i / 4];
1311
1312 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1313 }
1314
1315 return 0;
1316}
1317
fad09c73 1318static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1319 struct mv88e6xxx_vtu_stu_entry *entry)
1320{
fad09c73 1321 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1322}
1323
fad09c73 1324static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1325 struct mv88e6xxx_vtu_stu_entry *entry)
1326{
fad09c73 1327 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1328}
1329
fad09c73 1330static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
7dad08d7
VD		 1331 struct mv88e6xxx_vtu_stu_entry *entry,
1332 unsigned int nibble_offset)
1333{
7dad08d7
VD		 1334 u16 regs[3] = { 0 };
1335 int i;
1336 int ret;
1337
fad09c73 1338 for (i = 0; i < chip->info->num_ports; ++i) {
7dad08d7
VD		 1339 unsigned int shift = (i % 4) * 4 + nibble_offset;
1340 u8 data = entry->data[i];
1341
1342 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1343 }
1344
1345 for (i = 0; i < 3; ++i) {
fad09c73 1346 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
7dad08d7
VD		 1347 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1348 if (ret < 0)
1349 return ret;
1350 }
1351
1352 return 0;
1353}
1354
fad09c73 1355static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1356 struct mv88e6xxx_vtu_stu_entry *entry)
1357{
fad09c73 1358 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1359}
1360
fad09c73 1361static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1362 struct mv88e6xxx_vtu_stu_entry *entry)
1363{
fad09c73 1364 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1365}
1366
fad09c73 1367static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1368{
fad09c73 1369 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
36d04ba1
VD		 1370 vid & GLOBAL_VTU_VID_MASK);
1371}
1372
fad09c73 1373static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b8fee957
VD		 1374 struct mv88e6xxx_vtu_stu_entry *entry)
1375{
1376 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1377 int ret;
1378
fad09c73 1379 ret = _mv88e6xxx_vtu_wait(chip);
b8fee957
VD		 1380 if (ret < 0)
1381 return ret;
1382
fad09c73 1383 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
b8fee957
VD		 1384 if (ret < 0)
1385 return ret;
1386
fad09c73 1387 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
b8fee957
VD		 1388 if (ret < 0)
1389 return ret;
1390
1391 next.vid = ret & GLOBAL_VTU_VID_MASK;
1392 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1393
1394 if (next.valid) {
fad09c73 1395 ret = mv88e6xxx_vtu_data_read(chip, &next);
b8fee957
VD		 1396 if (ret < 0)
1397 return ret;
1398
fad09c73
VD		 1399 if (mv88e6xxx_has_fid_reg(chip)) {
1400 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
b8fee957
VD		 1401 GLOBAL_VTU_FID);
1402 if (ret < 0)
1403 return ret;
1404
1405 next.fid = ret & GLOBAL_VTU_FID_MASK;
fad09c73 1406 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1407 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1408 * VTU DBNum[3:0] are located in VTU Operation 3:0
1409 */
fad09c73 1410 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
11ea809f
VD		 1411 GLOBAL_VTU_OP);
1412 if (ret < 0)
1413 return ret;
1414
1415 next.fid = (ret & 0xf00) >> 4;
1416 next.fid |= ret & 0xf;
2e7bd5ef 1417 }
b8fee957 1418
fad09c73
VD		 1419 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1420 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
b8fee957
VD		 1421 GLOBAL_VTU_SID);
1422 if (ret < 0)
1423 return ret;
1424
1425 next.sid = ret & GLOBAL_VTU_SID_MASK;
1426 }
1427 }
1428
1429 *entry = next;
1430 return 0;
1431}
1432
f81ec90f
VD		 1433static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1434 struct switchdev_obj_port_vlan *vlan,
1435 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1436{
fad09c73 1437 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
ceff5eff
VD		 1438 struct mv88e6xxx_vtu_stu_entry next;
1439 u16 pvid;
1440 int err;
1441
fad09c73 1442 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1443 return -EOPNOTSUPP;
1444
fad09c73 1445 mutex_lock(&chip->reg_lock);
ceff5eff 1446
fad09c73 1447 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
ceff5eff
VD		 1448 if (err)
1449 goto unlock;
1450
fad09c73 1451 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1452 if (err)
1453 goto unlock;
1454
1455 do {
fad09c73 1456 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1457 if (err)
1458 break;
1459
1460 if (!next.valid)
1461 break;
1462
1463 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1464 continue;
1465
1466 /* reinit and dump this VLAN obj */
57d32310
VD		 1467 vlan->vid_begin = next.vid;
1468 vlan->vid_end = next.vid;
ceff5eff
VD		 1469 vlan->flags = 0;
1470
1471 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1472 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1473
1474 if (next.vid == pvid)
1475 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1476
1477 err = cb(&vlan->obj);
1478 if (err)
1479 break;
1480 } while (next.vid < GLOBAL_VTU_VID_MASK);
1481
1482unlock:
fad09c73 1483 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1484
1485 return err;
1486}
1487
fad09c73 1488static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
7dad08d7
VD		 1489 struct mv88e6xxx_vtu_stu_entry *entry)
1490{
11ea809f 1491 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7
VD		 1492 u16 reg = 0;
1493 int ret;
1494
fad09c73 1495 ret = _mv88e6xxx_vtu_wait(chip);
7dad08d7
VD		 1496 if (ret < 0)
1497 return ret;
1498
1499 if (!entry->valid)
1500 goto loadpurge;
1501
1502 /* Write port member tags */
fad09c73 1503 ret = mv88e6xxx_vtu_data_write(chip, entry);
7dad08d7
VD		 1504 if (ret < 0)
1505 return ret;
1506
fad09c73 1507 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1508 reg = entry->sid & GLOBAL_VTU_SID_MASK;
fad09c73
VD		 1509 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1510 reg);
7dad08d7
VD		 1511 if (ret < 0)
1512 return ret;
b426e5f7 1513 }
7dad08d7 1514
fad09c73 1515 if (mv88e6xxx_has_fid_reg(chip)) {
7dad08d7 1516 reg = entry->fid & GLOBAL_VTU_FID_MASK;
fad09c73
VD		 1517 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1518 reg);
7dad08d7
VD		 1519 if (ret < 0)
1520 return ret;
fad09c73 1521 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1522 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1523 * VTU DBNum[3:0] are located in VTU Operation 3:0
1524 */
1525 op |= (entry->fid & 0xf0) << 8;
1526 op |= entry->fid & 0xf;
7dad08d7
VD		 1527 }
1528
1529 reg = GLOBAL_VTU_VID_VALID;
1530loadpurge:
1531 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
fad09c73 1532 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
7dad08d7
VD		 1533 if (ret < 0)
1534 return ret;
1535
fad09c73 1536 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1537}
1538
fad09c73 1539static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
0d3b33e6
VD		 1540 struct mv88e6xxx_vtu_stu_entry *entry)
1541{
1542 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1543 int ret;
1544
fad09c73 1545 ret = _mv88e6xxx_vtu_wait(chip);
0d3b33e6
VD		 1546 if (ret < 0)
1547 return ret;
1548
fad09c73 1549 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
0d3b33e6
VD		 1550 sid & GLOBAL_VTU_SID_MASK);
1551 if (ret < 0)
1552 return ret;
1553
fad09c73 1554 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
0d3b33e6
VD		 1555 if (ret < 0)
1556 return ret;
1557
fad09c73 1558 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
0d3b33e6
VD		 1559 if (ret < 0)
1560 return ret;
1561
1562 next.sid = ret & GLOBAL_VTU_SID_MASK;
1563
fad09c73 1564 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
0d3b33e6
VD		 1565 if (ret < 0)
1566 return ret;
1567
1568 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1569
1570 if (next.valid) {
fad09c73 1571 ret = mv88e6xxx_stu_data_read(chip, &next);
0d3b33e6
VD		 1572 if (ret < 0)
1573 return ret;
1574 }
1575
1576 *entry = next;
1577 return 0;
1578}
1579
fad09c73 1580static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
0d3b33e6
VD		 1581 struct mv88e6xxx_vtu_stu_entry *entry)
1582{
1583 u16 reg = 0;
1584 int ret;
1585
fad09c73 1586 ret = _mv88e6xxx_vtu_wait(chip);
0d3b33e6
VD		 1587 if (ret < 0)
1588 return ret;
1589
1590 if (!entry->valid)
1591 goto loadpurge;
1592
1593 /* Write port states */
fad09c73 1594 ret = mv88e6xxx_stu_data_write(chip, entry);
0d3b33e6
VD		 1595 if (ret < 0)
1596 return ret;
1597
1598 reg = GLOBAL_VTU_VID_VALID;
1599loadpurge:
fad09c73 1600 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
0d3b33e6
VD		 1601 if (ret < 0)
1602 return ret;
1603
1604 reg = entry->sid & GLOBAL_VTU_SID_MASK;
fad09c73 1605 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
0d3b33e6
VD		 1606 if (ret < 0)
1607 return ret;
1608
fad09c73 1609 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1610}
1611
fad09c73 1612static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
158bc065 1613 u16 *new, u16 *old)
2db9ce1f 1614{
fad09c73 1615 struct dsa_switch *ds = chip->ds;
f74df0be 1616 u16 upper_mask;
2db9ce1f
VD		 1617 u16 fid;
1618 int ret;
1619
fad09c73 1620 if (mv88e6xxx_num_databases(chip) == 4096)
f74df0be 1621 upper_mask = 0xff;
fad09c73 1622 else if (mv88e6xxx_num_databases(chip) == 256)
11ea809f 1623 upper_mask = 0xf;
f74df0be
VD		 1624 else
1625 return -EOPNOTSUPP;
1626
2db9ce1f 1627 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
fad09c73 1628 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
2db9ce1f
VD		 1629 if (ret < 0)
1630 return ret;
1631
1632 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1633
1634 if (new) {
1635 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1636 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1637
fad09c73 1638 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
2db9ce1f
VD		 1639 ret);
1640 if (ret < 0)
1641 return ret;
1642 }
1643
1644 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
fad09c73 1645 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
2db9ce1f
VD		 1646 if (ret < 0)
1647 return ret;
1648
f74df0be 1649 fid |= (ret & upper_mask) << 4;
2db9ce1f
VD		 1650
1651 if (new) {
f74df0be
VD		 1652 ret &= ~upper_mask;
1653 ret |= (*new >> 4) & upper_mask;
2db9ce1f 1654
fad09c73 1655 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2db9ce1f
VD		 1656 ret);
1657 if (ret < 0)
1658 return ret;
1659
c8b09808
AL		 1660 netdev_dbg(ds->ports[port].netdev,
1661 "FID %d (was %d)\n", *new, fid);
2db9ce1f
VD		 1662 }
1663
1664 if (old)
1665 *old = fid;
1666
1667 return 0;
1668}
1669
fad09c73 1670static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
158bc065 1671 int port, u16 *fid)
2db9ce1f 1672{
fad09c73 1673 return _mv88e6xxx_port_fid(chip, port, NULL, fid);
2db9ce1f
VD		 1674}
1675
fad09c73 1676static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
158bc065 1677 int port, u16 fid)
2db9ce1f 1678{
fad09c73 1679 return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
2db9ce1f
VD		 1680}
1681
fad09c73 1682static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1683{
1684 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1685 struct mv88e6xxx_vtu_stu_entry vlan;
2db9ce1f 1686 int i, err;
3285f9e8
VD		 1687
1688 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1689
2db9ce1f 1690 /* Set every FID bit used by the (un)bridged ports */
fad09c73
VD		 1691 for (i = 0; i < chip->info->num_ports; ++i) {
1692 err = _mv88e6xxx_port_fid_get(chip, i, fid);
2db9ce1f
VD		 1693 if (err)
1694 return err;
1695
1696 set_bit(*fid, fid_bitmap);
1697 }
1698
3285f9e8 1699 /* Set every FID bit used by the VLAN entries */
fad09c73 1700 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1701 if (err)
1702 return err;
1703
1704 do {
fad09c73 1705 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1706 if (err)
1707 return err;
1708
1709 if (!vlan.valid)
1710 break;
1711
1712 set_bit(vlan.fid, fid_bitmap);
1713 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1714
1715 /* The reset value 0x000 is used to indicate that multiple address
1716 * databases are not needed. Return the next positive available.
1717 */
1718 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1719 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1720 return -ENOSPC;
1721
1722 /* Clear the database */
fad09c73 1723 return _mv88e6xxx_atu_flush(chip, *fid, true);
3285f9e8
VD		 1724}
1725
fad09c73 1726static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
2fb5ef09 1727 struct mv88e6xxx_vtu_stu_entry *entry)
0d3b33e6 1728{
fad09c73 1729 struct dsa_switch *ds = chip->ds;
0d3b33e6
VD		 1730 struct mv88e6xxx_vtu_stu_entry vlan = {
1731 .valid = true,
1732 .vid = vid,
1733 };
3285f9e8
VD		 1734 int i, err;
1735
fad09c73 1736 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
3285f9e8
VD		 1737 if (err)
1738 return err;
0d3b33e6 1739
3d131f07 1740 /* exclude all ports except the CPU and DSA ports */
fad09c73 1741 for (i = 0; i < chip->info->num_ports; ++i)
3d131f07
VD		 1742 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1743 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1744 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1745
fad09c73
VD		 1746 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1747 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
0d3b33e6 1748 struct mv88e6xxx_vtu_stu_entry vstp;
0d3b33e6
VD		 1749
1750 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1751 * implemented, only one STU entry is needed to cover all VTU
1752 * entries. Thus, validate the SID 0.
1753 */
1754 vlan.sid = 0;
fad09c73 1755 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1756 if (err)
1757 return err;
1758
1759 if (vstp.sid != vlan.sid || !vstp.valid) {
1760 memset(&vstp, 0, sizeof(vstp));
1761 vstp.valid = true;
1762 vstp.sid = vlan.sid;
1763
fad09c73 1764 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1765 if (err)
1766 return err;
1767 }
0d3b33e6
VD		 1768 }
1769
1770 *entry = vlan;
1771 return 0;
1772}
1773
fad09c73 1774static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
2fb5ef09
VD		 1775 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1776{
1777 int err;
1778
1779 if (!vid)
1780 return -EINVAL;
1781
fad09c73 1782 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1783 if (err)
1784 return err;
1785
fad09c73 1786 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1787 if (err)
1788 return err;
1789
1790 if (entry->vid != vid || !entry->valid) {
1791 if (!creat)
1792 return -EOPNOTSUPP;
1793 /* -ENOENT would've been more appropriate, but switchdev expects
1794 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1795 */
1796
fad09c73 1797 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1798 }
1799
1800 return err;
1801}
1802
da9c359e
VD		 1803static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1804 u16 vid_begin, u16 vid_end)
1805{
fad09c73 1806 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
da9c359e
VD		 1807 struct mv88e6xxx_vtu_stu_entry vlan;
1808 int i, err;
1809
1810 if (!vid_begin)
1811 return -EOPNOTSUPP;
1812
fad09c73 1813 mutex_lock(&chip->reg_lock);
da9c359e 1814
fad09c73 1815 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1816 if (err)
1817 goto unlock;
1818
1819 do {
fad09c73 1820 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1821 if (err)
1822 goto unlock;
1823
1824 if (!vlan.valid)
1825 break;
1826
1827 if (vlan.vid > vid_end)
1828 break;
1829
fad09c73 1830 for (i = 0; i < chip->info->num_ports; ++i) {
da9c359e
VD		 1831 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1832 continue;
1833
1834 if (vlan.data[i] ==
1835 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1836 continue;
1837
fad09c73
VD		 1838 if (chip->ports[i].bridge_dev ==
1839 chip->ports[port].bridge_dev)
da9c359e
VD		 1840 break; /* same bridge, check next VLAN */
1841
c8b09808 1842 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1843 "hardware VLAN %d already used by %s\n",
1844 vlan.vid,
fad09c73 1845 netdev_name(chip->ports[i].bridge_dev));
da9c359e
VD		 1846 err = -EOPNOTSUPP;
1847 goto unlock;
1848 }
1849 } while (vlan.vid < vid_end);
1850
1851unlock:
fad09c73 1852 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1853
1854 return err;
1855}
1856
214cdb99
VD		 1857static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1858 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1859 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1860 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1861 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1862};
1863
f81ec90f
VD		 1864static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1865 bool vlan_filtering)
214cdb99 1866{
fad09c73 1867 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
214cdb99
VD		 1868 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1869 PORT_CONTROL_2_8021Q_DISABLED;
1870 int ret;
1871
fad09c73 1872 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1873 return -EOPNOTSUPP;
1874
fad09c73 1875 mutex_lock(&chip->reg_lock);
214cdb99 1876
fad09c73 1877 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
214cdb99
VD		 1878 if (ret < 0)
1879 goto unlock;
1880
1881 old = ret & PORT_CONTROL_2_8021Q_MASK;
1882
5220ef1e
VD		 1883 if (new != old) {
1884 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1885 ret |= new & PORT_CONTROL_2_8021Q_MASK;
214cdb99 1886
fad09c73 1887 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
5220ef1e
VD		 1888 ret);
1889 if (ret < 0)
1890 goto unlock;
1891
c8b09808 1892 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
5220ef1e
VD		 1893 mv88e6xxx_port_8021q_mode_names[new],
1894 mv88e6xxx_port_8021q_mode_names[old]);
1895 }
214cdb99 1896
5220ef1e 1897 ret = 0;
214cdb99 1898unlock:
fad09c73 1899 mutex_unlock(&chip->reg_lock);
214cdb99
VD		 1900
1901 return ret;
1902}
1903
57d32310
VD		 1904static int
1905mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1906 const struct switchdev_obj_port_vlan *vlan,
1907 struct switchdev_trans *trans)
76e398a6 1908{
fad09c73 1909 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
da9c359e
VD		 1910 int err;
1911
fad09c73 1912 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1913 return -EOPNOTSUPP;
1914
da9c359e
VD		 1915 /* If the requested port doesn't belong to the same bridge as the VLAN
1916 * members, do not support it (yet) and fallback to software VLAN.
1917 */
1918 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1919 vlan->vid_end);
1920 if (err)
1921 return err;
1922
76e398a6
VD		 1923 /* We don't need any dynamic resource from the kernel (yet),
1924 * so skip the prepare phase.
1925 */
1926 return 0;
1927}
1928
fad09c73 1929static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1930 u16 vid, bool untagged)
0d3b33e6 1931{
0d3b33e6
VD		 1932 struct mv88e6xxx_vtu_stu_entry vlan;
1933 int err;
1934
fad09c73 1935 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1936 if (err)
76e398a6 1937 return err;
0d3b33e6 1938
0d3b33e6
VD		 1939 vlan.data[port] = untagged ?
1940 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1941 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1942
fad09c73 1943 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1944}
1945
f81ec90f
VD		 1946static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1947 const struct switchdev_obj_port_vlan *vlan,
1948 struct switchdev_trans *trans)
76e398a6 1949{
fad09c73 1950 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
76e398a6
VD		 1951 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1952 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1953 u16 vid;
76e398a6 1954
fad09c73 1955 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1956 return;
1957
fad09c73 1958 mutex_lock(&chip->reg_lock);
76e398a6 1959
4d5770b3 1960 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1961 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1962 netdev_err(ds->ports[port].netdev,
1963 "failed to add VLAN %d%c\n",
4d5770b3 1964 vid, untagged ? 'u' : 't');
76e398a6 1965
fad09c73 1966 if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
c8b09808 1967 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1968 vlan->vid_end);
0d3b33e6 1969
fad09c73 1970 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1971}
1972
fad09c73 1973static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1974 int port, u16 vid)
7dad08d7 1975{
fad09c73 1976 struct dsa_switch *ds = chip->ds;
7dad08d7 1977 struct mv88e6xxx_vtu_stu_entry vlan;
7dad08d7
VD		 1978 int i, err;
1979
fad09c73 1980 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1981 if (err)
76e398a6 1982 return err;
7dad08d7 1983
2fb5ef09
VD		 1984 /* Tell switchdev if this VLAN is handled in software */
1985 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1986 return -EOPNOTSUPP;
7dad08d7
VD		 1987
1988 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1989
1990 /* keep the VLAN unless all ports are excluded */
f02bdffc 1991 vlan.valid = false;
fad09c73 1992 for (i = 0; i < chip->info->num_ports; ++i) {
3d131f07 1993 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1994 continue;
1995
1996 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1997 vlan.valid = true;
7dad08d7
VD		 1998 break;
1999 }
2000 }
2001
fad09c73 2002 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 2003 if (err)
2004 return err;
2005
fad09c73 2006 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 2007}
2008
f81ec90f
VD		 2009static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2010 const struct switchdev_obj_port_vlan *vlan)
76e398a6 2011{
fad09c73 2012 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
76e398a6
VD		 2013 u16 pvid, vid;
2014 int err = 0;
2015
fad09c73 2016 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 2017 return -EOPNOTSUPP;
2018
fad09c73 2019 mutex_lock(&chip->reg_lock);
76e398a6 2020
fad09c73 2021 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
7dad08d7
VD		 2022 if (err)
2023 goto unlock;
2024
76e398a6 2025 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 2026 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 2027 if (err)
2028 goto unlock;
2029
2030 if (vid == pvid) {
fad09c73 2031 err = _mv88e6xxx_port_pvid_set(chip, port, 0);
76e398a6
VD		 2032 if (err)
2033 goto unlock;
2034 }
2035 }
2036
7dad08d7 2037unlock:
fad09c73 2038 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 2039
2040 return err;
2041}
2042
fad09c73 2043static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
c5723ac5 2044 const unsigned char *addr)
defb05b9
GR		 2045{
2046 int i, ret;
2047
2048 for (i = 0; i < 3; i++) {
cca8b133 2049 ret = _mv88e6xxx_reg_write(
fad09c73 2050 chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
cca8b133 2051 (addr[i * 2] << 8) | addr[i * 2 + 1]);
defb05b9
GR		 2052 if (ret < 0)
2053 return ret;
2054 }
2055
2056 return 0;
2057}
2058
fad09c73 2059static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
158bc065 2060 unsigned char *addr)
defb05b9
GR		 2061{
2062 int i, ret;
2063
2064 for (i = 0; i < 3; i++) {
fad09c73 2065 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
cca8b133 2066 GLOBAL_ATU_MAC_01 + i);
defb05b9
GR		 2067 if (ret < 0)
2068 return ret;
2069 addr[i * 2] = ret >> 8;
2070 addr[i * 2 + 1] = ret & 0xff;
2071 }
2072
2073 return 0;
2074}
2075
fad09c73 2076static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
fd231c82 2077 struct mv88e6xxx_atu_entry *entry)
defb05b9 2078{
6630e236
VD		 2079 int ret;
2080
fad09c73 2081 ret = _mv88e6xxx_atu_wait(chip);
defb05b9
GR		 2082 if (ret < 0)
2083 return ret;
2084
fad09c73 2085 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
defb05b9
GR		 2086 if (ret < 0)
2087 return ret;
2088
fad09c73 2089 ret = _mv88e6xxx_atu_data_write(chip, entry);
fd231c82 2090 if (ret < 0)
87820510
VD		 2091 return ret;
2092
fad09c73 2093 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2094}
87820510 2095
83dabd1f
VD		 2096static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2097 const unsigned char *addr, u16 vid,
2098 u8 state)
fd231c82
VD		 2099{
2100 struct mv88e6xxx_atu_entry entry = { 0 };
3285f9e8
VD		 2101 struct mv88e6xxx_vtu_stu_entry vlan;
2102 int err;
2103
2db9ce1f
VD		 2104 /* Null VLAN ID corresponds to the port private database */
2105 if (vid == 0)
fad09c73 2106 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2db9ce1f 2107 else
fad09c73 2108 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 2109 if (err)
2110 return err;
fd231c82 2111
3285f9e8 2112 entry.fid = vlan.fid;
fd231c82
VD		 2113 entry.state = state;
2114 ether_addr_copy(entry.mac, addr);
2115 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2116 entry.trunk = false;
2117 entry.portv_trunkid = BIT(port);
2118 }
2119
fad09c73 2120 return _mv88e6xxx_atu_load(chip, &entry);
87820510
VD		 2121}
2122
f81ec90f
VD		 2123static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2124 const struct switchdev_obj_port_fdb *fdb,
2125 struct switchdev_trans *trans)
146a3206
VD		 2126{
2127 /* We don't need any dynamic resource from the kernel (yet),
2128 * so skip the prepare phase.
2129 */
2130 return 0;
2131}
2132
f81ec90f
VD		 2133static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2134 const struct switchdev_obj_port_fdb *fdb,
2135 struct switchdev_trans *trans)
87820510 2136{
fad09c73 2137 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
87820510 2138
fad09c73 2139 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2140 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2141 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2142 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
fad09c73 2143 mutex_unlock(&chip->reg_lock);
87820510
VD		 2144}
2145
f81ec90f
VD		 2146static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2147 const struct switchdev_obj_port_fdb *fdb)
87820510 2148{
fad09c73 2149 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
83dabd1f 2150 int err;
87820510 2151
fad09c73 2152 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2153 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2154 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 2155 mutex_unlock(&chip->reg_lock);
87820510 2156
83dabd1f 2157 return err;
87820510
VD		 2158}
2159
fad09c73 2160static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
1d194046 2161 struct mv88e6xxx_atu_entry *entry)
6630e236 2162{
1d194046
VD		 2163 struct mv88e6xxx_atu_entry next = { 0 };
2164 int ret;
2165
2166 next.fid = fid;
defb05b9 2167
fad09c73 2168 ret = _mv88e6xxx_atu_wait(chip);
cdf09697
DM		 2169 if (ret < 0)
2170 return ret;
6630e236 2171
fad09c73 2172 ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
1d194046
VD		 2173 if (ret < 0)
2174 return ret;
6630e236 2175
fad09c73 2176 ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
1d194046
VD		 2177 if (ret < 0)
2178 return ret;
6630e236 2179
fad09c73 2180 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
cdf09697
DM		 2181 if (ret < 0)
2182 return ret;
6630e236 2183
1d194046
VD		 2184 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2185 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2186 unsigned int mask, shift;
2187
2188 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2189 next.trunk = true;
2190 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2191 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2192 } else {
2193 next.trunk = false;
2194 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2195 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2196 }
2197
2198 next.portv_trunkid = (ret & mask) >> shift;
2199 }
cdf09697 2200
1d194046 2201 *entry = next;
cdf09697
DM		 2202 return 0;
2203}
2204
83dabd1f
VD		 2205static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2206 u16 fid, u16 vid, int port,
2207 struct switchdev_obj *obj,
2208 int (*cb)(struct switchdev_obj *obj))
74b6ba0d
VD		 2209{
2210 struct mv88e6xxx_atu_entry addr = {
2211 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2212 };
2213 int err;
2214
fad09c73 2215 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
74b6ba0d
VD		 2216 if (err)
2217 return err;
2218
2219 do {
fad09c73 2220 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
74b6ba0d 2221 if (err)
83dabd1f 2222 return err;
74b6ba0d
VD		 2223
2224 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2225 break;
2226
83dabd1f
VD		 2227 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2228 continue;
2229
2230 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2231 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 2232
83dabd1f
VD		 2233 if (!is_unicast_ether_addr(addr.mac))
2234 continue;
2235
2236 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 2237 fdb->vid = vid;
2238 ether_addr_copy(fdb->addr, addr.mac);
83dabd1f
VD		 2239 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2240 fdb->ndm_state = NUD_NOARP;
2241 else
2242 fdb->ndm_state = NUD_REACHABLE;
2243 } else {
2244 return -EOPNOTSUPP;
74b6ba0d 2245 }
83dabd1f
VD		 2246
2247 err = cb(obj);
2248 if (err)
2249 return err;
74b6ba0d
VD		 2250 } while (!is_broadcast_ether_addr(addr.mac));
2251
2252 return err;
2253}
2254
83dabd1f
VD		 2255static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2256 struct switchdev_obj *obj,
2257 int (*cb)(struct switchdev_obj *obj))
f33475bd 2258{
f33475bd
VD		 2259 struct mv88e6xxx_vtu_stu_entry vlan = {
2260 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2261 };
2db9ce1f 2262 u16 fid;
f33475bd
VD		 2263 int err;
2264
2db9ce1f 2265 /* Dump port's default Filtering Information Database (VLAN ID 0) */
fad09c73 2266 err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2db9ce1f 2267 if (err)
83dabd1f 2268 return err;
2db9ce1f 2269
83dabd1f 2270 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 2271 if (err)
83dabd1f 2272 return err;
2db9ce1f 2273
74b6ba0d 2274 /* Dump VLANs' Filtering Information Databases */
fad09c73 2275 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd 2276 if (err)
83dabd1f 2277 return err;
f33475bd
VD		 2278
2279 do {
fad09c73 2280 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2281 if (err)
83dabd1f 2282 return err;
f33475bd
VD		 2283
2284 if (!vlan.valid)
2285 break;
2286
83dabd1f
VD		 2287 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2288 obj, cb);
f33475bd 2289 if (err)
83dabd1f 2290 return err;
f33475bd
VD		 2291 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2292
83dabd1f
VD		 2293 return err;
2294}
2295
2296static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2297 struct switchdev_obj_port_fdb *fdb,
2298 int (*cb)(struct switchdev_obj *obj))
2299{
2300 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2301 int err;
2302
2303 mutex_lock(&chip->reg_lock);
2304 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 2305 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2306
2307 return err;
2308}
2309
f81ec90f
VD		 2310static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2311 struct net_device *bridge)
e79a8bcb 2312{
fad09c73 2313 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1d9619d5 2314 int i, err = 0;
466dfa07 2315
fad09c73 2316 mutex_lock(&chip->reg_lock);
466dfa07 2317
b7666efe 2318 /* Assign the bridge and remap each port's VLANTable */
fad09c73 2319 chip->ports[port].bridge_dev = bridge;
b7666efe 2320
fad09c73
VD		 2321 for (i = 0; i < chip->info->num_ports; ++i) {
2322 if (chip->ports[i].bridge_dev == bridge) {
2323 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2324 if (err)
2325 break;
2326 }
2327 }
2328
fad09c73 2329 mutex_unlock(&chip->reg_lock);
a6692754 2330
466dfa07 2331 return err;
e79a8bcb
VD		 2332}
2333
f81ec90f 2334static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2335{
fad09c73
VD		 2336 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2337 struct net_device *bridge = chip->ports[port].bridge_dev;
16bfa702 2338 int i;
466dfa07 2339
fad09c73 2340 mutex_lock(&chip->reg_lock);
466dfa07 2341
b7666efe 2342 /* Unassign the bridge and remap each port's VLANTable */
fad09c73 2343 chip->ports[port].bridge_dev = NULL;
b7666efe 2344
fad09c73
VD		 2345 for (i = 0; i < chip->info->num_ports; ++i)
2346 if (i == port || chip->ports[i].bridge_dev == bridge)
2347 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2348 netdev_warn(ds->ports[i].netdev,
2349 "failed to remap\n");
b7666efe 2350
fad09c73 2351 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2352}
2353
fad09c73 2354static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
552238b5 2355{
fad09c73 2356 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
552238b5 2357 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
fad09c73 2358 struct gpio_desc *gpiod = chip->reset;
552238b5
VD		 2359 unsigned long timeout;
2360 int ret;
2361 int i;
2362
2363 /* Set all ports to the disabled state. */
fad09c73
VD		 2364 for (i = 0; i < chip->info->num_ports; i++) {
2365 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
552238b5
VD		 2366 if (ret < 0)
2367 return ret;
2368
fad09c73 2369 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
552238b5
VD		 2370 ret & 0xfffc);
2371 if (ret)
2372 return ret;
2373 }
2374
2375 /* Wait for transmit queues to drain. */
2376 usleep_range(2000, 4000);
2377
2378 /* If there is a gpio connected to the reset pin, toggle it */
2379 if (gpiod) {
2380 gpiod_set_value_cansleep(gpiod, 1);
2381 usleep_range(10000, 20000);
2382 gpiod_set_value_cansleep(gpiod, 0);
2383 usleep_range(10000, 20000);
2384 }
2385
2386 /* Reset the switch. Keep the PPU active if requested. The PPU
2387 * needs to be active to support indirect phy register access
2388 * through global registers 0x18 and 0x19.
2389 */
2390 if (ppu_active)
fad09c73 2391 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
552238b5 2392 else
fad09c73 2393 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
552238b5
VD		 2394 if (ret)
2395 return ret;
2396
2397 /* Wait up to one second for reset to complete. */
2398 timeout = jiffies + 1 * HZ;
2399 while (time_before(jiffies, timeout)) {
fad09c73 2400 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
552238b5
VD		 2401 if (ret < 0)
2402 return ret;
2403
2404 if ((ret & is_reset) == is_reset)
2405 break;
2406 usleep_range(1000, 2000);
2407 }
2408 if (time_after(jiffies, timeout))
2409 ret = -ETIMEDOUT;
2410 else
2411 ret = 0;
2412
2413 return ret;
2414}
2415
09cb7dfd 2416static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
13a7ebb3 2417{
09cb7dfd
VD		 2418 u16 val;
2419 int err;
13a7ebb3 2420
09cb7dfd
VD		 2421 /* Clear Power Down bit */
2422 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2423 if (err)
2424 return err;
13a7ebb3 2425
09cb7dfd
VD		 2426 if (val & BMCR_PDOWN) {
2427 val &= ~BMCR_PDOWN;
2428 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
13a7ebb3
PU		 2429 }
2430
09cb7dfd 2431 return err;
13a7ebb3
PU		 2432}
2433
8f6345b2
VD		 2434static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port,
2435 int reg, u16 *val)
2436{
2437 int addr = chip->info->port_base_addr + port;
2438
2439 if (port >= chip->info->num_ports)
2440 return -EINVAL;
2441
2442 return mv88e6xxx_read(chip, addr, reg, val);
2443}
2444
fad09c73 2445static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2446{
fad09c73 2447 struct dsa_switch *ds = chip->ds;
f02bdffc 2448 int ret;
54d792f2 2449 u16 reg;
d827e88a 2450
fad09c73
VD		 2451 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2452 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2453 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2454 mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2455 /* MAC Forcing register: don't force link, speed,
2456 * duplex or flow control state to any particular
2457 * values on physical ports, but force the CPU port
2458 * and all DSA ports to their maximum bandwidth and
2459 * full duplex.
2460 */
fad09c73 2461 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
60045cbf 2462 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 2463 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 2464 reg |= PORT_PCS_CTRL_FORCE_LINK |
2465 PORT_PCS_CTRL_LINK_UP |
2466 PORT_PCS_CTRL_DUPLEX_FULL |
2467 PORT_PCS_CTRL_FORCE_DUPLEX;
fad09c73 2468 if (mv88e6xxx_6065_family(chip))
54d792f2
AL		 2469 reg |= PORT_PCS_CTRL_100;
2470 else
2471 reg |= PORT_PCS_CTRL_1000;
2472 } else {
2473 reg |= PORT_PCS_CTRL_UNFORCED;
2474 }
2475
fad09c73 2476 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2477 PORT_PCS_CTRL, reg);
2478 if (ret)
a1a6a4d1 2479 return ret;
54d792f2
AL		 2480 }
2481
2482 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2483 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2484 * tunneling, determine priority by looking at 802.1p and IP
2485 * priority fields (IP prio has precedence), and set STP state
2486 * to Forwarding.
2487 *
2488 * If this is the CPU link, use DSA or EDSA tagging depending
2489 * on which tagging mode was configured.
2490 *
2491 * If this is a link to another switch, use DSA tagging mode.
2492 *
2493 * If this is the upstream port for this switch, enable
2494 * forwarding of unknown unicasts and multicasts.
2495 */
2496 reg = 0;
fad09c73
VD		 2497 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2498 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2499 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2500 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2501 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2502 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2503 PORT_CONTROL_STATE_FORWARDING;
2504 if (dsa_is_cpu_port(ds, port)) {
2bbb33be 2505 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
5377b802 2506 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
c047a1f9 2507 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2bbb33be
AL		 2508 else
2509 reg |= PORT_CONTROL_DSA_TAG;
f027e0cc
JL		 2510 reg |= PORT_CONTROL_EGRESS_ADD_TAG |
2511 PORT_CONTROL_FORWARD_UNKNOWN;
54d792f2 2512 }
6083ce71 2513 if (dsa_is_dsa_port(ds, port)) {
fad09c73
VD		 2514 if (mv88e6xxx_6095_family(chip) ||
2515 mv88e6xxx_6185_family(chip))
6083ce71 2516 reg |= PORT_CONTROL_DSA_TAG;
fad09c73
VD		 2517 if (mv88e6xxx_6352_family(chip) ||
2518 mv88e6xxx_6351_family(chip) ||
2519 mv88e6xxx_6165_family(chip) ||
2520 mv88e6xxx_6097_family(chip) ||
2521 mv88e6xxx_6320_family(chip)) {
54d792f2 2522 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2523 }
2524
54d792f2
AL		 2525 if (port == dsa_upstream_port(ds))
2526 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2527 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2528 }
2529 if (reg) {
fad09c73 2530 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2531 PORT_CONTROL, reg);
2532 if (ret)
a1a6a4d1 2533 return ret;
54d792f2
AL		 2534 }
2535
13a7ebb3
PU		 2536 /* If this port is connected to a SerDes, make sure the SerDes is not
2537 * powered down.
2538 */
09cb7dfd 2539 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
fad09c73 2540 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
13a7ebb3 2541 if (ret < 0)
a1a6a4d1 2542 return ret;
13a7ebb3
PU		 2543 ret &= PORT_STATUS_CMODE_MASK;
2544 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2545 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2546 (ret == PORT_STATUS_CMODE_SGMII)) {
09cb7dfd 2547 ret = mv88e6xxx_serdes_power_on(chip);
13a7ebb3 2548 if (ret < 0)
a1a6a4d1 2549 return ret;
13a7ebb3
PU		 2550 }
2551 }
2552
8efdda4a 2553 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2554 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2555 * untagged frames on this port, do a destination address lookup on all
2556 * received packets as usual, disable ARP mirroring and don't send a
2557 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2558 */
2559 reg = 0;
fad09c73
VD		 2560 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2561 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2562 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2563 mv88e6xxx_6185_family(chip))
54d792f2
AL		 2564 reg = PORT_CONTROL_2_MAP_DA;
2565
fad09c73
VD		 2566 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2567 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2568 reg |= PORT_CONTROL_2_JUMBO_10240;
2569
fad09c73 2570 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
54d792f2
AL		 2571 /* Set the upstream port this port should use */
2572 reg |= dsa_upstream_port(ds);
2573 /* enable forwarding of unknown multicast addresses to
2574 * the upstream port
2575 */
2576 if (port == dsa_upstream_port(ds))
2577 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2578 }
2579
46fbe5e5 2580 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2581
54d792f2 2582 if (reg) {
fad09c73 2583 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2584 PORT_CONTROL_2, reg);
2585 if (ret)
a1a6a4d1 2586 return ret;
54d792f2
AL		 2587 }
2588
2589 /* Port Association Vector: when learning source addresses
2590 * of packets, add the address to the address database using
2591 * a port bitmap that has only the bit for this port set and
2592 * the other bits clear.
2593 */
4c7ea3c0 2594 reg = 1 << port;
996ecb82
VD		 2595 /* Disable learning for CPU port */
2596 if (dsa_is_cpu_port(ds, port))
65fa4027 2597 reg = 0;
4c7ea3c0 2598
fad09c73
VD		 2599 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2600 reg);
54d792f2 2601 if (ret)
a1a6a4d1 2602 return ret;
54d792f2
AL		 2603
2604 /* Egress rate control 2: disable egress rate control. */
fad09c73 2605 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
54d792f2
AL		 2606 0x0000);
2607 if (ret)
a1a6a4d1 2608 return ret;
54d792f2 2609
fad09c73
VD		 2610 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2611 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2612 mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2613 /* Do not limit the period of time that this port can
2614 * be paused for by the remote end or the period of
2615 * time that this port can pause the remote end.
2616 */
fad09c73 2617 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2618 PORT_PAUSE_CTRL, 0x0000);
2619 if (ret)
a1a6a4d1 2620 return ret;
54d792f2
AL		 2621
2622 /* Port ATU control: disable limiting the number of
2623 * address database entries that this port is allowed
2624 * to use.
2625 */
fad09c73 2626 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2627 PORT_ATU_CONTROL, 0x0000);
2628 /* Priority Override: disable DA, SA and VTU priority
2629 * override.
2630 */
fad09c73 2631 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2632 PORT_PRI_OVERRIDE, 0x0000);
2633 if (ret)
a1a6a4d1 2634 return ret;
54d792f2
AL		 2635
2636 /* Port Ethertype: use the Ethertype DSA Ethertype
2637 * value.
2638 */
2bbb33be
AL		 2639 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) {
2640 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2641 PORT_ETH_TYPE, ETH_P_EDSA);
2642 if (ret)
2643 return ret;
2644 }
2645
54d792f2
AL		 2646 /* Tag Remap: use an identity 802.1p prio -> switch
2647 * prio mapping.
2648 */
fad09c73 2649 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2650 PORT_TAG_REGMAP_0123, 0x3210);
2651 if (ret)
a1a6a4d1 2652 return ret;
54d792f2
AL		 2653
2654 /* Tag Remap 2: use an identity 802.1p prio -> switch
2655 * prio mapping.
2656 */
fad09c73 2657 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2658 PORT_TAG_REGMAP_4567, 0x7654);
2659 if (ret)
a1a6a4d1 2660 return ret;
54d792f2
AL		 2661 }
2662
1bc261fa 2663 /* Rate Control: disable ingress rate limiting. */
fad09c73
VD		 2664 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2665 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
fad09c73 2666 mv88e6xxx_6320_family(chip)) {
fad09c73 2667 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2668 PORT_RATE_CONTROL, 0x0001);
2669 if (ret)
a1a6a4d1 2670 return ret;
1bc261fa
JL		 2671 } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {
2672 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2673 PORT_RATE_CONTROL, 0x0000);
2674 if (ret)
2675 return ret;
54d792f2
AL		 2676 }
2677
366f0a0f
GR		 2678 /* Port Control 1: disable trunking, disable sending
2679 * learning messages to this port.
d827e88a 2680 */
fad09c73
VD		 2681 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2682 0x0000);
d827e88a 2683 if (ret)
a1a6a4d1 2684 return ret;
d827e88a 2685
207afda1 2686 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2687 * database, and allow bidirectional communication between the
2688 * CPU and DSA port(s), and the other ports.
d827e88a 2689 */
fad09c73 2690 ret = _mv88e6xxx_port_fid_set(chip, port, 0);
2db9ce1f 2691 if (ret)
a1a6a4d1 2692 return ret;
2db9ce1f 2693
fad09c73 2694 ret = _mv88e6xxx_port_based_vlan_map(chip, port);
d827e88a 2695 if (ret)
a1a6a4d1 2696 return ret;
d827e88a
GR		 2697
2698 /* Default VLAN ID and priority: don't set a default VLAN
2699 * ID, and set the default packet priority to zero.
2700 */
fad09c73 2701 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
47cf1e65 2702 0x0000);
a1a6a4d1
VD		 2703 if (ret)
2704 return ret;
dbde9e66 2705
dbde9e66
AL		 2706 return 0;
2707}
2708
3b4caa1b
VD		 2709static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2710{
2711 int err;
2712
2713 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
2714 (addr[0] << 8) | addr[1]);
2715 if (err)
2716 return err;
2717
2718 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
2719 (addr[2] << 8) | addr[3]);
2720 if (err)
2721 return err;
2722
2723 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
2724 (addr[4] << 8) | addr[5]);
2725}
2726
acddbd21
VD		 2727static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2728 unsigned int msecs)
2729{
2730 const unsigned int coeff = chip->info->age_time_coeff;
2731 const unsigned int min = 0x01 * coeff;
2732 const unsigned int max = 0xff * coeff;
2733 u8 age_time;
2734 u16 val;
2735 int err;
2736
2737 if (msecs < min || msecs > max)
2738 return -ERANGE;
2739
2740 /* Round to nearest multiple of coeff */
2741 age_time = (msecs + coeff / 2) / coeff;
2742
2743 err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val);
2744 if (err)
2745 return err;
2746
2747 /* AgeTime is 11:4 bits */
2748 val &= ~0xff0;
2749 val |= age_time << 4;
2750
2751 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val);
2752}
2753
2cfcd964
VD		 2754static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2755 unsigned int ageing_time)
2756{
2757 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2758 int err;
2759
2760 mutex_lock(&chip->reg_lock);
2761 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2762 mutex_unlock(&chip->reg_lock);
2763
2764 return err;
2765}
2766
9729934c 2767static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2768{
fad09c73 2769 struct dsa_switch *ds = chip->ds;
b0745e87 2770 u32 upstream_port = dsa_upstream_port(ds);
119477bd 2771 u16 reg;
552238b5 2772 int err;
54d792f2 2773
119477bd
VD		 2774 /* Enable the PHY Polling Unit if present, don't discard any packets,
2775 * and mask all interrupt sources.
2776 */
2777 reg = 0;
fad09c73
VD		 2778 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2779 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
119477bd
VD		 2780 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2781
fad09c73 2782 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
119477bd
VD		 2783 if (err)
2784 return err;
2785
b0745e87
VD		 2786 /* Configure the upstream port, and configure it as the port to which
2787 * ingress and egress and ARP monitor frames are to be sent.
2788 */
2789 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2790 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2791 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
fad09c73
VD		 2792 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
2793 reg);
b0745e87
VD		 2794 if (err)
2795 return err;
2796
50484ff4 2797 /* Disable remote management, and set the switch's DSA device number. */
fad09c73 2798 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
50484ff4
VD		 2799 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2800 (ds->index & 0x1f));
2801 if (err)
2802 return err;
2803
acddbd21
VD		 2804 /* Clear all the VTU and STU entries */
2805 err = _mv88e6xxx_vtu_stu_flush(chip);
2806 if (err < 0)
2807 return err;
2808
54d792f2
AL		 2809 /* Set the default address aging time to 5 minutes, and
2810 * enable address learn messages to be sent to all message
2811 * ports.
2812 */
acddbd21
VD		 2813 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2814 GLOBAL_ATU_CONTROL_LEARN2ALL);
48ace4ef 2815 if (err)
08a01261 2816 return err;
54d792f2 2817
acddbd21
VD		 2818 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2819 if (err)
9729934c
VD		 2820 return err;
2821
2822 /* Clear all ATU entries */
2823 err = _mv88e6xxx_atu_flush(chip, 0, true);
2824 if (err)
2825 return err;
2826
54d792f2 2827 /* Configure the IP ToS mapping registers. */
fad09c73 2828 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2829 if (err)
08a01261 2830 return err;
fad09c73 2831 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2832 if (err)
08a01261 2833 return err;
fad09c73 2834 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2835 if (err)
08a01261 2836 return err;
fad09c73 2837 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2838 if (err)
08a01261 2839 return err;
fad09c73 2840 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2841 if (err)
08a01261 2842 return err;
fad09c73 2843 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2844 if (err)
08a01261 2845 return err;
fad09c73 2846 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2847 if (err)
08a01261 2848 return err;
fad09c73 2849 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2850 if (err)
08a01261 2851 return err;
54d792f2
AL		 2852
2853 /* Configure the IEEE 802.1p priority mapping register. */
fad09c73 2854 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2855 if (err)
08a01261 2856 return err;
54d792f2 2857
9729934c
VD		 2858 /* Clear the statistics counters for all ports */
2859 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
2860 GLOBAL_STATS_OP_FLUSH_ALL);
2861 if (err)
2862 return err;
2863
2864 /* Wait for the flush to complete. */
2865 err = _mv88e6xxx_stats_wait(chip);
2866 if (err)
2867 return err;
2868
2869 return 0;
2870}
2871
f22ab641
VD		 2872static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
2873 int target, int port)
2874{
2875 u16 val = (target << 8) | (port & 0xf);
2876
2877 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val);
2878}
2879
2880static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
2881{
2882 int target, port;
2883 int err;
2884
2885 /* Initialize the routing port to the 32 possible target devices */
2886 for (target = 0; target < 32; ++target) {
2887 port = 0xf;
2888
2889 if (target < DSA_MAX_SWITCHES) {
2890 port = chip->ds->rtable[target];
2891 if (port == DSA_RTABLE_NONE)
2892 port = 0xf;
2893 }
2894
2895 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
2896 if (err)
2897 break;
2898 }
2899
2900 return err;
2901}
2902
5154041f
VD		 2903static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
2904 bool hask, u16 mask)
2905{
2906 const u16 port_mask = BIT(chip->info->num_ports) - 1;
2907 u16 val = (num << 12) | (mask & port_mask);
2908
2909 if (hask)
2910 val |= GLOBAL2_TRUNK_MASK_HASK;
2911
2912 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val);
2913}
2914
2915static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
2916 u16 map)
2917{
2918 const u16 port_mask = BIT(chip->info->num_ports) - 1;
2919 u16 val = (id << 11) | (map & port_mask);
2920
2921 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val);
2922}
2923
2924static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
2925{
2926 const u16 port_mask = BIT(chip->info->num_ports) - 1;
2927 int i, err;
2928
2929 /* Clear all eight possible Trunk Mask vectors */
2930 for (i = 0; i < 8; ++i) {
2931 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
2932 if (err)
2933 return err;
2934 }
2935
2936 /* Clear all sixteen possible Trunk ID routing vectors */
2937 for (i = 0; i < 16; ++i) {
2938 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
2939 if (err)
2940 return err;
2941 }
2942
2943 return 0;
2944}
2945
8ec61c7f
VD		 2946static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
2947{
2948 int port, err;
2949
2950 /* Init all Ingress Rate Limit resources of all ports */
2951 for (port = 0; port < chip->info->num_ports; ++port) {
2952 /* XXX newer chips (like 88E6390) have different 2-bit ops */
2953 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2954 GLOBAL2_IRL_CMD_OP_INIT_ALL |
2955 (port << 8));
2956 if (err)
2957 break;
2958
2959 /* Wait for the operation to complete */
2d79af6e
VD		 2960 err = mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2961 GLOBAL2_IRL_CMD_BUSY);
8ec61c7f
VD		 2962 if (err)
2963 break;
2964 }
2965
2966 return err;
2967}
2968
3b4caa1b
VD		 2969/* Indirect write to the Switch MAC/WoL/WoF register */
2970static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
2971 unsigned int pointer, u8 data)
2972{
2973 u16 val = (pointer << 8) | data;
2974
2975 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val);
2976}
2977
2978static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2979{
2980 int i, err;
2981
2982 for (i = 0; i < 6; i++) {
2983 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
2984 if (err)
2985 break;
2986 }
2987
2988 return err;
2989}
2990
9bda889f
VD		 2991static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
2992 u8 data)
2993{
2994 u16 val = (pointer << 8) | (data & 0x7);
2995
2996 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, val);
2997}
2998
2999static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
3000{
3001 int i, err;
3002
3003 /* Clear all sixteen possible Priority Override entries */
3004 for (i = 0; i < 16; i++) {
3005 err = mv88e6xxx_g2_pot_write(chip, i, 0);
3006 if (err)
3007 break;
3008 }
3009
3010 return err;
3011}
3012
855b1932
VD		 3013static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
3014{
2d79af6e
VD		 3015 return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD,
3016 GLOBAL2_EEPROM_CMD_BUSY |
3017 GLOBAL2_EEPROM_CMD_RUNNING);
855b1932
VD		 3018}
3019
3020static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3021{
3022 int err;
3023
3024 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, cmd);
3025 if (err)
3026 return err;
3027
3028 return mv88e6xxx_g2_eeprom_wait(chip);
3029}
3030
3031static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
3032 u8 addr, u16 *data)
3033{
3034 u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr;
3035 int err;
3036
3037 err = mv88e6xxx_g2_eeprom_wait(chip);
3038 if (err)
3039 return err;
3040
3041 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3042 if (err)
3043 return err;
3044
3045 return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3046}
3047
3048static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
3049 u8 addr, u16 data)
3050{
3051 u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr;
3052 int err;
3053
3054 err = mv88e6xxx_g2_eeprom_wait(chip);
3055 if (err)
3056 return err;
3057
3058 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3059 if (err)
3060 return err;
3061
3062 return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3063}
3064
57c67cf5
VD		 3065static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
3066{
3067 return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD,
3068 GLOBAL2_SMI_PHY_CMD_BUSY);
3069}
3070
3071static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3072{
3073 int err;
3074
3075 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD, cmd);
3076 if (err)
3077 return err;
3078
3079 return mv88e6xxx_g2_smi_phy_wait(chip);
3080}
3081
3082static int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, int addr,
3083 int reg, u16 *val)
3084{
3085 u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA | (addr << 5) | reg;
3086 int err;
3087
3088 err = mv88e6xxx_g2_smi_phy_wait(chip);
3089 if (err)
3090 return err;
3091
3092 err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
3093 if (err)
3094 return err;
3095
3096 return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
3097}
3098
3099static int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, int addr,
3100 int reg, u16 val)
3101{
3102 u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA | (addr << 5) | reg;
3103 int err;
3104
3105 err = mv88e6xxx_g2_smi_phy_wait(chip);
3106 if (err)
3107 return err;
3108
3109 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
3110 if (err)
3111 return err;
3112
3113 return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
3114}
3115
e57e5e77
VD		 3116static const struct mv88e6xxx_ops mv88e6xxx_g2_smi_phy_ops = {
3117 .read = mv88e6xxx_g2_smi_phy_read,
3118 .write = mv88e6xxx_g2_smi_phy_write,
3119};
3120
9729934c
VD		 3121static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
3122{
47395ed2 3123 u16 reg;
9729934c 3124 int err;
9729934c 3125
47395ed2
VD		 3126 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
3127 /* Consider the frames with reserved multicast destination
3128 * addresses matching 01:80:c2:00:00:2x as MGMT.
3129 */
3130 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
3131 0xffff);
3132 if (err)
3133 return err;
3134 }
3135
3136 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
3137 /* Consider the frames with reserved multicast destination
3138 * addresses matching 01:80:c2:00:00:0x as MGMT.
3139 */
3140 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
3141 0xffff);
3142 if (err)
3143 return err;
3144 }
54d792f2
AL		 3145
3146 /* Ignore removed tag data on doubly tagged packets, disable
3147 * flow control messages, force flow control priority to the
3148 * highest, and send all special multicast frames to the CPU
3149 * port at the highest priority.
3150 */
47395ed2
VD		 3151 reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
3152 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
3153 mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
3154 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
3155 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
48ace4ef 3156 if (err)
08a01261 3157 return err;
54d792f2
AL		 3158
3159 /* Program the DSA routing table. */
f22ab641
VD		 3160 err = mv88e6xxx_g2_set_device_mapping(chip);
3161 if (err)
3162 return err;
54d792f2 3163
5154041f
VD		 3164 /* Clear all trunk masks and mapping. */
3165 err = mv88e6xxx_g2_clear_trunk(chip);
3166 if (err)
3167 return err;
54d792f2 3168
8ec61c7f
VD		 3169 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
3170 /* Disable ingress rate limiting by resetting all per port
3171 * ingress rate limit resources to their initial state.
3172 */
3173 err = mv88e6xxx_g2_clear_irl(chip);
3174 if (err)
3175 return err;
3176 }
3177
63ed880d
VD		 3178 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
3179 /* Initialize Cross-chip Port VLAN Table to reset defaults */
3180 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR,
3181 GLOBAL2_PVT_ADDR_OP_INIT_ONES);
48ace4ef 3182 if (err)
08a01261 3183 return err;
63ed880d 3184 }
54d792f2 3185
9bda889f 3186 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
54d792f2 3187 /* Clear the priority override table. */
9bda889f
VD		 3188 err = mv88e6xxx_g2_clear_pot(chip);
3189 if (err)
3190 return err;
54d792f2
AL		 3191 }
3192
9729934c 3193 return 0;
08a01261
VD		 3194}
3195
f81ec90f 3196static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 3197{
fad09c73 3198 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
08a01261 3199 int err;
a1a6a4d1
VD		 3200 int i;
3201
fad09c73
VD		 3202 chip->ds = ds;
3203 ds->slave_mii_bus = chip->mdio_bus;
08a01261 3204
fad09c73 3205 mutex_lock(&chip->reg_lock);
08a01261 3206
fad09c73 3207 err = mv88e6xxx_switch_reset(chip);
08a01261
VD		 3208 if (err)
3209 goto unlock;
3210
9729934c
VD		 3211 /* Setup Switch Port Registers */
3212 for (i = 0; i < chip->info->num_ports; i++) {
3213 err = mv88e6xxx_setup_port(chip, i);
3214 if (err)
3215 goto unlock;
3216 }
3217
3218 /* Setup Switch Global 1 Registers */
3219 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 3220 if (err)
3221 goto unlock;
3222
9729934c
VD		 3223 /* Setup Switch Global 2 Registers */
3224 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
3225 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 3226 if (err)
3227 goto unlock;
3228 }
08a01261 3229
6b17e864 3230unlock:
fad09c73 3231 mutex_unlock(&chip->reg_lock);
db687a56 3232
48ace4ef 3233 return err;
54d792f2
AL		 3234}
3235
3b4caa1b
VD		 3236static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
3237{
3238 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3239 int err;
3240
3241 mutex_lock(&chip->reg_lock);
3242
3243 /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
3244 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
3245 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
3246 else
3247 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
3248
3249 mutex_unlock(&chip->reg_lock);
3250
3251 return err;
3252}
3253
e57e5e77 3254static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 3255{
fad09c73 3256 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77
VD		 3257 u16 val;
3258 int err;
fd3a0ee4 3259
e57e5e77 3260 if (phy >= chip->info->num_ports)
158bc065 3261 return 0xffff;
fd3a0ee4 3262
fad09c73 3263 mutex_lock(&chip->reg_lock);
e57e5e77 3264 err = mv88e6xxx_phy_read(chip, phy, reg, &val);
fad09c73 3265 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 3266
3267 return err ? err : val;
fd3a0ee4
AL		 3268}
3269
e57e5e77 3270static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 3271{
fad09c73 3272 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77 3273 int err;
fd3a0ee4 3274
e57e5e77 3275 if (phy >= chip->info->num_ports)
158bc065 3276 return 0xffff;
fd3a0ee4 3277
fad09c73 3278 mutex_lock(&chip->reg_lock);
e57e5e77 3279 err = mv88e6xxx_phy_write(chip, phy, reg, val);
fad09c73 3280 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 3281
3282 return err;
fd3a0ee4
AL		 3283}
3284
fad09c73 3285static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
b516d453
AL		 3286 struct device_node *np)
3287{
3288 static int index;
3289 struct mii_bus *bus;
3290 int err;
3291
b516d453 3292 if (np)
fad09c73 3293 chip->mdio_np = of_get_child_by_name(np, "mdio");
b516d453 3294
fad09c73 3295 bus = devm_mdiobus_alloc(chip->dev);
b516d453
AL		 3296 if (!bus)
3297 return -ENOMEM;
3298
fad09c73 3299 bus->priv = (void *)chip;
b516d453
AL		 3300 if (np) {
3301 bus->name = np->full_name;
3302 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3303 } else {
3304 bus->name = "mv88e6xxx SMI";
3305 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3306 }
3307
3308 bus->read = mv88e6xxx_mdio_read;
3309 bus->write = mv88e6xxx_mdio_write;
fad09c73 3310 bus->parent = chip->dev;
b516d453 3311
fad09c73
VD		 3312 if (chip->mdio_np)
3313 err = of_mdiobus_register(bus, chip->mdio_np);
b516d453
AL		 3314 else
3315 err = mdiobus_register(bus);
3316 if (err) {
fad09c73 3317 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
b516d453
AL		 3318 goto out;
3319 }
fad09c73 3320 chip->mdio_bus = bus;
b516d453
AL		 3321
3322 return 0;
3323
3324out:
fad09c73
VD		 3325 if (chip->mdio_np)
3326 of_node_put(chip->mdio_np);
b516d453
AL		 3327
3328 return err;
3329}
3330
fad09c73 3331static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 3332
3333{
fad09c73 3334 struct mii_bus *bus = chip->mdio_bus;
b516d453
AL		 3335
3336 mdiobus_unregister(bus);
3337
fad09c73
VD		 3338 if (chip->mdio_np)
3339 of_node_put(chip->mdio_np);
b516d453
AL		 3340}
3341
c22995c5
GR		 3342#ifdef CONFIG_NET_DSA_HWMON
3343
3344static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3345{
fad09c73 3346 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
9c93829c 3347 u16 val;
c22995c5 3348 int ret;
c22995c5
GR		 3349
3350 *temp = 0;
3351
fad09c73 3352 mutex_lock(&chip->reg_lock);
c22995c5 3353
9c93829c 3354 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
c22995c5
GR		 3355 if (ret < 0)
3356 goto error;
3357
3358 /* Enable temperature sensor */
9c93829c 3359 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
c22995c5
GR		 3360 if (ret < 0)
3361 goto error;
3362
9c93829c 3363 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
c22995c5
GR		 3364 if (ret < 0)
3365 goto error;
3366
3367 /* Wait for temperature to stabilize */
3368 usleep_range(10000, 12000);
3369
9c93829c
VD		 3370 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3371 if (ret < 0)
c22995c5 3372 goto error;
c22995c5
GR		 3373
3374 /* Disable temperature sensor */
9c93829c 3375 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
c22995c5
GR		 3376 if (ret < 0)
3377 goto error;
3378
3379 *temp = ((val & 0x1f) - 5) * 5;
3380
3381error:
9c93829c 3382 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
fad09c73 3383 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3384 return ret;
3385}
3386
3387static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3388{
fad09c73
VD		 3389 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3390 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3391 u16 val;
c22995c5
GR		 3392 int ret;
3393
3394 *temp = 0;
3395
9c93829c
VD		 3396 mutex_lock(&chip->reg_lock);
3397 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3398 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3399 if (ret < 0)
3400 return ret;
3401
9c93829c 3402 *temp = (val & 0xff) - 25;
c22995c5
GR		 3403
3404 return 0;
3405}
3406
f81ec90f 3407static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
c22995c5 3408{
fad09c73 3409 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
158bc065 3410
fad09c73 3411 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
6594f615
VD		 3412 return -EOPNOTSUPP;
3413
fad09c73 3414 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
c22995c5
GR		 3415 return mv88e63xx_get_temp(ds, temp);
3416
3417 return mv88e61xx_get_temp(ds, temp);
3418}
3419
f81ec90f 3420static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
c22995c5 3421{
fad09c73
VD		 3422 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3423 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3424 u16 val;
c22995c5
GR		 3425 int ret;
3426
fad09c73 3427 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3428 return -EOPNOTSUPP;
3429
3430 *temp = 0;
3431
9c93829c
VD		 3432 mutex_lock(&chip->reg_lock);
3433 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3434 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3435 if (ret < 0)
3436 return ret;
3437
9c93829c 3438 *temp = (((val >> 8) & 0x1f) * 5) - 25;
c22995c5
GR		 3439
3440 return 0;
3441}
3442
f81ec90f 3443static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
c22995c5 3444{
fad09c73
VD		 3445 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3446 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c
VD		 3447 u16 val;
3448 int err;
c22995c5 3449
fad09c73 3450 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3451 return -EOPNOTSUPP;
3452
9c93829c
VD		 3453 mutex_lock(&chip->reg_lock);
3454 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3455 if (err)
3456 goto unlock;
c22995c5 3457 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
9c93829c
VD		 3458 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3459 (val & 0xe0ff) | (temp << 8));
3460unlock:
3461 mutex_unlock(&chip->reg_lock);
3462
3463 return err;
c22995c5
GR		 3464}
3465
f81ec90f 3466static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
c22995c5 3467{
fad09c73
VD		 3468 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3469 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3470 u16 val;
c22995c5
GR		 3471 int ret;
3472
fad09c73 3473 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3474 return -EOPNOTSUPP;
3475
3476 *alarm = false;
3477
9c93829c
VD		 3478 mutex_lock(&chip->reg_lock);
3479 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3480 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3481 if (ret < 0)
3482 return ret;
3483
9c93829c 3484 *alarm = !!(val & 0x40);
c22995c5
GR		 3485
3486 return 0;
3487}
3488#endif /* CONFIG_NET_DSA_HWMON */
3489
855b1932
VD		 3490static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3491{
3492 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3493
3494 return chip->eeprom_len;
3495}
3496
3497static int mv88e6xxx_get_eeprom16(struct mv88e6xxx_chip *chip,
3498 struct ethtool_eeprom *eeprom, u8 *data)
3499{
3500 unsigned int offset = eeprom->offset;
3501 unsigned int len = eeprom->len;
3502 u16 val;
3503 int err;
3504
3505 eeprom->len = 0;
3506
3507 if (offset & 1) {
3508 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3509 if (err)
3510 return err;
3511
3512 *data++ = (val >> 8) & 0xff;
3513
3514 offset++;
3515 len--;
3516 eeprom->len++;
3517 }
3518
3519 while (len >= 2) {
3520 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3521 if (err)
3522 return err;
3523
3524 *data++ = val & 0xff;
3525 *data++ = (val >> 8) & 0xff;
3526
3527 offset += 2;
3528 len -= 2;
3529 eeprom->len += 2;
3530 }
3531
3532 if (len) {
3533 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3534 if (err)
3535 return err;
3536
3537 *data++ = val & 0xff;
3538
3539 offset++;
3540 len--;
3541 eeprom->len++;
3542 }
3543
3544 return 0;
3545}
3546
3547static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3548 struct ethtool_eeprom *eeprom, u8 *data)
3549{
3550 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3551 int err;
3552
3553 mutex_lock(&chip->reg_lock);
3554
3555 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3556 err = mv88e6xxx_get_eeprom16(chip, eeprom, data);
3557 else
3558 err = -EOPNOTSUPP;
3559
3560 mutex_unlock(&chip->reg_lock);
3561
3562 if (err)
3563 return err;
3564
3565 eeprom->magic = 0xc3ec4951;
3566
3567 return 0;
3568}
3569
3570static int mv88e6xxx_set_eeprom16(struct mv88e6xxx_chip *chip,
3571 struct ethtool_eeprom *eeprom, u8 *data)
3572{
3573 unsigned int offset = eeprom->offset;
3574 unsigned int len = eeprom->len;
3575 u16 val;
3576 int err;
3577
3578 /* Ensure the RO WriteEn bit is set */
3579 err = mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, &val);
3580 if (err)
3581 return err;
3582
3583 if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN))
3584 return -EROFS;
3585
3586 eeprom->len = 0;
3587
3588 if (offset & 1) {
3589 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3590 if (err)
3591 return err;
3592
3593 val = (*data++ << 8) | (val & 0xff);
3594
3595 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3596 if (err)
3597 return err;
3598
3599 offset++;
3600 len--;
3601 eeprom->len++;
3602 }
3603
3604 while (len >= 2) {
3605 val = *data++;
3606 val |= *data++ << 8;
3607
3608 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3609 if (err)
3610 return err;
3611
3612 offset += 2;
3613 len -= 2;
3614 eeprom->len += 2;
3615 }
3616
3617 if (len) {
3618 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3619 if (err)
3620 return err;
3621
3622 val = (val & 0xff00) | *data++;
3623
3624 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3625 if (err)
3626 return err;
3627
3628 offset++;
3629 len--;
3630 eeprom->len++;
3631 }
3632
3633 return 0;
3634}
3635
3636static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3637 struct ethtool_eeprom *eeprom, u8 *data)
3638{
3639 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3640 int err;
3641
3642 if (eeprom->magic != 0xc3ec4951)
3643 return -EINVAL;
3644
3645 mutex_lock(&chip->reg_lock);
3646
3647 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3648 err = mv88e6xxx_set_eeprom16(chip, eeprom, data);
3649 else
3650 err = -EOPNOTSUPP;
3651
3652 mutex_unlock(&chip->reg_lock);
3653
3654 return err;
3655}
3656
f81ec90f
VD		 3657static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3658 [MV88E6085] = {
3659 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3660 .family = MV88E6XXX_FAMILY_6097,
3661 .name = "Marvell 88E6085",
3662 .num_databases = 4096,
3663 .num_ports = 10,
9dddd478 3664 .port_base_addr = 0x10,
acddbd21 3665 .age_time_coeff = 15000,
f81ec90f
VD		 3666 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3667 },
3668
3669 [MV88E6095] = {
3670 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3671 .family = MV88E6XXX_FAMILY_6095,
3672 .name = "Marvell 88E6095/88E6095F",
3673 .num_databases = 256,
3674 .num_ports = 11,
9dddd478 3675 .port_base_addr = 0x10,
acddbd21 3676 .age_time_coeff = 15000,
f81ec90f
VD		 3677 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3678 },
3679
3680 [MV88E6123] = {
3681 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3682 .family = MV88E6XXX_FAMILY_6165,
3683 .name = "Marvell 88E6123",
3684 .num_databases = 4096,
3685 .num_ports = 3,
9dddd478 3686 .port_base_addr = 0x10,
acddbd21 3687 .age_time_coeff = 15000,
f81ec90f
VD		 3688 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3689 },
3690
3691 [MV88E6131] = {
3692 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3693 .family = MV88E6XXX_FAMILY_6185,
3694 .name = "Marvell 88E6131",
3695 .num_databases = 256,
3696 .num_ports = 8,
9dddd478 3697 .port_base_addr = 0x10,
acddbd21 3698 .age_time_coeff = 15000,
f81ec90f
VD		 3699 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3700 },
3701
3702 [MV88E6161] = {
3703 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3704 .family = MV88E6XXX_FAMILY_6165,
3705 .name = "Marvell 88E6161",
3706 .num_databases = 4096,
3707 .num_ports = 6,
9dddd478 3708 .port_base_addr = 0x10,
acddbd21 3709 .age_time_coeff = 15000,
f81ec90f
VD		 3710 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3711 },
3712
3713 [MV88E6165] = {
3714 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3715 .family = MV88E6XXX_FAMILY_6165,
3716 .name = "Marvell 88E6165",
3717 .num_databases = 4096,
3718 .num_ports = 6,
9dddd478 3719 .port_base_addr = 0x10,
acddbd21 3720 .age_time_coeff = 15000,
f81ec90f
VD		 3721 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3722 },
3723
3724 [MV88E6171] = {
3725 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3726 .family = MV88E6XXX_FAMILY_6351,
3727 .name = "Marvell 88E6171",
3728 .num_databases = 4096,
3729 .num_ports = 7,
9dddd478 3730 .port_base_addr = 0x10,
acddbd21 3731 .age_time_coeff = 15000,
f81ec90f
VD		 3732 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3733 },
3734
3735 [MV88E6172] = {
3736 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3737 .family = MV88E6XXX_FAMILY_6352,
3738 .name = "Marvell 88E6172",
3739 .num_databases = 4096,
3740 .num_ports = 7,
9dddd478 3741 .port_base_addr = 0x10,
acddbd21 3742 .age_time_coeff = 15000,
f81ec90f
VD		 3743 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3744 },
3745
3746 [MV88E6175] = {
3747 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3748 .family = MV88E6XXX_FAMILY_6351,
3749 .name = "Marvell 88E6175",
3750 .num_databases = 4096,
3751 .num_ports = 7,
9dddd478 3752 .port_base_addr = 0x10,
acddbd21 3753 .age_time_coeff = 15000,
f81ec90f
VD		 3754 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3755 },
3756
3757 [MV88E6176] = {
3758 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3759 .family = MV88E6XXX_FAMILY_6352,
3760 .name = "Marvell 88E6176",
3761 .num_databases = 4096,
3762 .num_ports = 7,
9dddd478 3763 .port_base_addr = 0x10,
acddbd21 3764 .age_time_coeff = 15000,
f81ec90f
VD		 3765 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3766 },
3767
3768 [MV88E6185] = {
3769 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3770 .family = MV88E6XXX_FAMILY_6185,
3771 .name = "Marvell 88E6185",
3772 .num_databases = 256,
3773 .num_ports = 10,
9dddd478 3774 .port_base_addr = 0x10,
acddbd21 3775 .age_time_coeff = 15000,
f81ec90f
VD		 3776 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3777 },
3778
3779 [MV88E6240] = {
3780 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3781 .family = MV88E6XXX_FAMILY_6352,
3782 .name = "Marvell 88E6240",
3783 .num_databases = 4096,
3784 .num_ports = 7,
9dddd478 3785 .port_base_addr = 0x10,
acddbd21 3786 .age_time_coeff = 15000,
f81ec90f
VD		 3787 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3788 },
3789
3790 [MV88E6320] = {
3791 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3792 .family = MV88E6XXX_FAMILY_6320,
3793 .name = "Marvell 88E6320",
3794 .num_databases = 4096,
3795 .num_ports = 7,
9dddd478 3796 .port_base_addr = 0x10,
acddbd21 3797 .age_time_coeff = 15000,
f81ec90f
VD		 3798 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3799 },
3800
3801 [MV88E6321] = {
3802 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3803 .family = MV88E6XXX_FAMILY_6320,
3804 .name = "Marvell 88E6321",
3805 .num_databases = 4096,
3806 .num_ports = 7,
9dddd478 3807 .port_base_addr = 0x10,
acddbd21 3808 .age_time_coeff = 15000,
f81ec90f
VD		 3809 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3810 },
3811
3812 [MV88E6350] = {
3813 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3814 .family = MV88E6XXX_FAMILY_6351,
3815 .name = "Marvell 88E6350",
3816 .num_databases = 4096,
3817 .num_ports = 7,
9dddd478 3818 .port_base_addr = 0x10,
acddbd21 3819 .age_time_coeff = 15000,
f81ec90f
VD		 3820 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3821 },
3822
3823 [MV88E6351] = {
3824 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3825 .family = MV88E6XXX_FAMILY_6351,
3826 .name = "Marvell 88E6351",
3827 .num_databases = 4096,
3828 .num_ports = 7,
9dddd478 3829 .port_base_addr = 0x10,
acddbd21 3830 .age_time_coeff = 15000,
f81ec90f
VD		 3831 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3832 },
3833
3834 [MV88E6352] = {
3835 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3836 .family = MV88E6XXX_FAMILY_6352,
3837 .name = "Marvell 88E6352",
3838 .num_databases = 4096,
3839 .num_ports = 7,
9dddd478 3840 .port_base_addr = 0x10,
acddbd21 3841 .age_time_coeff = 15000,
f81ec90f
VD		 3842 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3843 },
3844};
3845
5f7c0367 3846static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3847{
a439c061 3848 int i;
b9b37713 3849
5f7c0367
VD		 3850 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3851 if (mv88e6xxx_table[i].prod_num == prod_num)
3852 return &mv88e6xxx_table[i];
b9b37713 3853
b9b37713
VD		 3854 return NULL;
3855}
3856
fad09c73 3857static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3858{
3859 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3860 unsigned int prod_num, rev;
3861 u16 id;
3862 int err;
bc46a3d5 3863
8f6345b2
VD		 3864 mutex_lock(&chip->reg_lock);
3865 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3866 mutex_unlock(&chip->reg_lock);
3867 if (err)
3868 return err;
bc46a3d5
VD		 3869
3870 prod_num = (id & 0xfff0) >> 4;
3871 rev = id & 0x000f;
3872
3873 info = mv88e6xxx_lookup_info(prod_num);
3874 if (!info)
3875 return -ENODEV;
3876
caac8545 3877 /* Update the compatible info with the probed one */
fad09c73 3878 chip->info = info;
bc46a3d5 3879
fad09c73
VD		 3880 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3881 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 3882
3883 return 0;
3884}
3885
fad09c73 3886static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 3887{
fad09c73 3888 struct mv88e6xxx_chip *chip;
469d729f 3889
fad09c73
VD		 3890 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3891 if (!chip)
469d729f
VD		 3892 return NULL;
3893
fad09c73 3894 chip->dev = dev;
469d729f 3895
fad09c73 3896 mutex_init(&chip->reg_lock);
469d729f 3897
fad09c73 3898 return chip;
469d729f
VD		 3899}
3900
e57e5e77
VD		 3901static const struct mv88e6xxx_ops mv88e6xxx_phy_ops = {
3902 .read = mv88e6xxx_read,
3903 .write = mv88e6xxx_write,
3904};
3905
3906static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3907{
3908 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SMI_PHY)) {
3909 chip->phy_ops = &mv88e6xxx_g2_smi_phy_ops;
3910 } else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3911 chip->phy_ops = &mv88e6xxx_phy_ppu_ops;
3912 mv88e6xxx_ppu_state_init(chip);
3913 } else {
3914 chip->phy_ops = &mv88e6xxx_phy_ops;
3915 }
3916}
3917
930188ce
AL		 3918static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
3919{
3920 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3921 mv88e6xxx_ppu_state_destroy(chip);
3922 }
3923}
3924
fad09c73 3925static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 3926 struct mii_bus *bus, int sw_addr)
3927{
3928 /* ADDR[0] pin is unavailable externally and considered zero */
3929 if (sw_addr & 0x1)
3930 return -EINVAL;
3931
914b32f6 3932 if (sw_addr == 0)
fad09c73 3933 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 3934 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 3935 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 3936 else
3937 return -EINVAL;
3938
fad09c73
VD		 3939 chip->bus = bus;
3940 chip->sw_addr = sw_addr;
4a70c4ab
VD		 3941
3942 return 0;
3943}
3944
7b314362
AL		 3945static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3946{
2bbb33be
AL		 3947 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3948
3949 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
3950 return DSA_TAG_PROTO_EDSA;
3951
3952 return DSA_TAG_PROTO_DSA;
7b314362
AL		 3953}
3954
fcdce7d0
AL		 3955static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3956 struct device *host_dev, int sw_addr,
3957 void **priv)
a77d43f1 3958{
fad09c73 3959 struct mv88e6xxx_chip *chip;
a439c061 3960 struct mii_bus *bus;
b516d453 3961 int err;
a77d43f1 3962
a439c061 3963 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3964 if (!bus)
3965 return NULL;
3966
fad09c73
VD		 3967 chip = mv88e6xxx_alloc_chip(dsa_dev);
3968 if (!chip)
469d729f
VD		 3969 return NULL;
3970
caac8545 3971 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 3972 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 3973
fad09c73 3974 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 3975 if (err)
3976 goto free;
3977
fad09c73 3978 err = mv88e6xxx_detect(chip);
bc46a3d5 3979 if (err)
469d729f 3980 goto free;
a439c061 3981
e57e5e77
VD		 3982 mv88e6xxx_phy_init(chip);
3983
fad09c73 3984 err = mv88e6xxx_mdio_register(chip, NULL);
b516d453 3985 if (err)
469d729f 3986 goto free;
b516d453 3987
fad09c73 3988 *priv = chip;
a439c061 3989
fad09c73 3990 return chip->info->name;
469d729f 3991free:
fad09c73 3992 devm_kfree(dsa_dev, chip);
469d729f
VD		 3993
3994 return NULL;
a77d43f1
AL		 3995}
3996
9d490b4e 3997static struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 3998 .probe = mv88e6xxx_drv_probe,
7b314362 3999 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 4000 .setup = mv88e6xxx_setup,
4001 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 4002 .adjust_link = mv88e6xxx_adjust_link,
4003 .get_strings = mv88e6xxx_get_strings,
4004 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4005 .get_sset_count = mv88e6xxx_get_sset_count,
4006 .set_eee = mv88e6xxx_set_eee,
4007 .get_eee = mv88e6xxx_get_eee,
4008#ifdef CONFIG_NET_DSA_HWMON
4009 .get_temp = mv88e6xxx_get_temp,
4010 .get_temp_limit = mv88e6xxx_get_temp_limit,
4011 .set_temp_limit = mv88e6xxx_set_temp_limit,
4012 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
4013#endif
f8cd8753 4014 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 4015 .get_eeprom = mv88e6xxx_get_eeprom,
4016 .set_eeprom = mv88e6xxx_set_eeprom,
4017 .get_regs_len = mv88e6xxx_get_regs_len,
4018 .get_regs = mv88e6xxx_get_regs,
2cfcd964 4019 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 4020 .port_bridge_join = mv88e6xxx_port_bridge_join,
4021 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4022 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
4023 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4024 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4025 .port_vlan_add = mv88e6xxx_port_vlan_add,
4026 .port_vlan_del = mv88e6xxx_port_vlan_del,
4027 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4028 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4029 .port_fdb_add = mv88e6xxx_port_fdb_add,
4030 .port_fdb_del = mv88e6xxx_port_fdb_del,
4031 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
4032};
4033
fad09c73 4034static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
b7e66a5f
VD		 4035 struct device_node *np)
4036{
fad09c73 4037 struct device *dev = chip->dev;
b7e66a5f
VD		 4038 struct dsa_switch *ds;
4039
4040 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4041 if (!ds)
4042 return -ENOMEM;
4043
4044 ds->dev = dev;
fad09c73 4045 ds->priv = chip;
9d490b4e 4046 ds->ops = &mv88e6xxx_switch_ops;
b7e66a5f
VD		 4047
4048 dev_set_drvdata(dev, ds);
4049
4050 return dsa_register_switch(ds, np);
4051}
4052
fad09c73 4053static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4054{
fad09c73 4055 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 4056}
4057
57d32310 4058static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 4059{
14c7b3c3 4060 struct device *dev = &mdiodev->dev;
f8cd8753 4061 struct device_node *np = dev->of_node;
caac8545 4062 const struct mv88e6xxx_info *compat_info;
fad09c73 4063 struct mv88e6xxx_chip *chip;
f8cd8753 4064 u32 eeprom_len;
52638f71 4065 int err;
14c7b3c3 4066
caac8545
VD		 4067 compat_info = of_device_get_match_data(dev);
4068 if (!compat_info)
4069 return -EINVAL;
4070
fad09c73
VD		 4071 chip = mv88e6xxx_alloc_chip(dev);
4072 if (!chip)
14c7b3c3
AL		 4073 return -ENOMEM;
4074
fad09c73 4075 chip->info = compat_info;
caac8545 4076
fad09c73 4077 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4078 if (err)
4079 return err;
14c7b3c3 4080
fad09c73 4081 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4082 if (err)
4083 return err;
14c7b3c3 4084
e57e5e77
VD		 4085 mv88e6xxx_phy_init(chip);
4086
fad09c73
VD		 4087 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
4088 if (IS_ERR(chip->reset))
4089 return PTR_ERR(chip->reset);
52638f71 4090
855b1932 4091 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
f8cd8753 4092 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4093 chip->eeprom_len = eeprom_len;
f8cd8753 4094
fad09c73 4095 err = mv88e6xxx_mdio_register(chip, np);
b516d453
AL		 4096 if (err)
4097 return err;
4098
fad09c73 4099 err = mv88e6xxx_register_switch(chip, np);
83c0afae 4100 if (err) {
fad09c73 4101 mv88e6xxx_mdio_unregister(chip);
83c0afae
AL		 4102 return err;
4103 }
4104
98e67308
BH		 4105 return 0;
4106}
14c7b3c3
AL		 4107
4108static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4109{
4110 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
fad09c73 4111 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
14c7b3c3 4112
930188ce 4113 mv88e6xxx_phy_destroy(chip);
fad09c73
VD		 4114 mv88e6xxx_unregister_switch(chip);
4115 mv88e6xxx_mdio_unregister(chip);
14c7b3c3
AL		 4116}
4117
4118static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4119 {
4120 .compatible = "marvell,mv88e6085",
4121 .data = &mv88e6xxx_table[MV88E6085],
4122 },
14c7b3c3
AL		 4123 { /* sentinel */ },
4124};
4125
4126MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4127
4128static struct mdio_driver mv88e6xxx_driver = {
4129 .probe = mv88e6xxx_probe,
4130 .remove = mv88e6xxx_remove,
4131 .mdiodrv.driver = {
4132 .name = "mv88e6085",
4133 .of_match_table = mv88e6xxx_of_match,
4134 },
4135};
4136
4137static int __init mv88e6xxx_init(void)
4138{
9d490b4e 4139 register_switch_driver(&mv88e6xxx_switch_ops);
14c7b3c3
AL		 4140 return mdio_driver_register(&mv88e6xxx_driver);
4141}
98e67308
BH		 4142module_init(mv88e6xxx_init);
4143
4144static void __exit mv88e6xxx_cleanup(void)
4145{
14c7b3c3 4146 mdio_driver_unregister(&mv88e6xxx_driver);
9d490b4e 4147 unregister_switch_driver(&mv88e6xxx_switch_ops);
98e67308
BH		 4148}
4149module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4150
4151MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4152MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4153MODULE_LICENSE("GPL");
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