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Commit | Line | Data |
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91da11f8 | 1 | /* |
0d3cd4b6 VD |
2 | * Marvell 88e6xxx Ethernet switch single-chip support |
3 | * | |
91da11f8 LB |
4 | * Copyright (c) 2008 Marvell Semiconductor |
5 | * | |
b8fee957 VD |
6 | * Copyright (c) 2015 CMC Electronics, Inc. |
7 | * Added support for VLAN Table Unit operations | |
8 | * | |
14c7b3c3 AL |
9 | * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> |
10 | * | |
91da11f8 LB |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
19b2f97e | 17 | #include <linux/delay.h> |
defb05b9 | 18 | #include <linux/etherdevice.h> |
dea87024 | 19 | #include <linux/ethtool.h> |
facd95b2 | 20 | #include <linux/if_bridge.h> |
dc30c35b AL |
21 | #include <linux/interrupt.h> |
22 | #include <linux/irq.h> | |
23 | #include <linux/irqdomain.h> | |
19b2f97e | 24 | #include <linux/jiffies.h> |
91da11f8 | 25 | #include <linux/list.h> |
14c7b3c3 | 26 | #include <linux/mdio.h> |
2bbba277 | 27 | #include <linux/module.h> |
caac8545 | 28 | #include <linux/of_device.h> |
dc30c35b | 29 | #include <linux/of_irq.h> |
b516d453 | 30 | #include <linux/of_mdio.h> |
91da11f8 | 31 | #include <linux/netdevice.h> |
c8c1b39a | 32 | #include <linux/gpio/consumer.h> |
91da11f8 | 33 | #include <linux/phy.h> |
c8f0b869 | 34 | #include <net/dsa.h> |
1f36faf2 | 35 | #include <net/switchdev.h> |
ec561276 | 36 | |
91da11f8 | 37 | #include "mv88e6xxx.h" |
a935c052 | 38 | #include "global1.h" |
ec561276 | 39 | #include "global2.h" |
18abed21 | 40 | #include "port.h" |
91da11f8 | 41 | |
fad09c73 | 42 | static void assert_reg_lock(struct mv88e6xxx_chip *chip) |
3996a4ff | 43 | { |
fad09c73 VD |
44 | if (unlikely(!mutex_is_locked(&chip->reg_lock))) { |
45 | dev_err(chip->dev, "Switch registers lock not held!\n"); | |
3996a4ff VD |
46 | dump_stack(); |
47 | } | |
48 | } | |
49 | ||
914b32f6 VD |
50 | /* The switch ADDR[4:1] configuration pins define the chip SMI device address |
51 | * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). | |
52 | * | |
53 | * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it | |
54 | * is the only device connected to the SMI master. In this mode it responds to | |
55 | * all 32 possible SMI addresses, and thus maps directly the internal devices. | |
56 | * | |
57 | * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing | |
58 | * multiple devices to share the SMI interface. In this mode it responds to only | |
59 | * 2 registers, used to indirectly access the internal SMI devices. | |
91da11f8 | 60 | */ |
914b32f6 | 61 | |
fad09c73 | 62 | static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
63 | int addr, int reg, u16 *val) |
64 | { | |
fad09c73 | 65 | if (!chip->smi_ops) |
914b32f6 VD |
66 | return -EOPNOTSUPP; |
67 | ||
fad09c73 | 68 | return chip->smi_ops->read(chip, addr, reg, val); |
914b32f6 VD |
69 | } |
70 | ||
fad09c73 | 71 | static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
72 | int addr, int reg, u16 val) |
73 | { | |
fad09c73 | 74 | if (!chip->smi_ops) |
914b32f6 VD |
75 | return -EOPNOTSUPP; |
76 | ||
fad09c73 | 77 | return chip->smi_ops->write(chip, addr, reg, val); |
914b32f6 VD |
78 | } |
79 | ||
fad09c73 | 80 | static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
81 | int addr, int reg, u16 *val) |
82 | { | |
83 | int ret; | |
84 | ||
fad09c73 | 85 | ret = mdiobus_read_nested(chip->bus, addr, reg); |
914b32f6 VD |
86 | if (ret < 0) |
87 | return ret; | |
88 | ||
89 | *val = ret & 0xffff; | |
90 | ||
91 | return 0; | |
92 | } | |
93 | ||
fad09c73 | 94 | static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
95 | int addr, int reg, u16 val) |
96 | { | |
97 | int ret; | |
98 | ||
fad09c73 | 99 | ret = mdiobus_write_nested(chip->bus, addr, reg, val); |
914b32f6 VD |
100 | if (ret < 0) |
101 | return ret; | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
c08026ab | 106 | static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { |
914b32f6 VD |
107 | .read = mv88e6xxx_smi_single_chip_read, |
108 | .write = mv88e6xxx_smi_single_chip_write, | |
109 | }; | |
110 | ||
fad09c73 | 111 | static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) |
91da11f8 LB |
112 | { |
113 | int ret; | |
114 | int i; | |
115 | ||
116 | for (i = 0; i < 16; i++) { | |
fad09c73 | 117 | ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); |
91da11f8 LB |
118 | if (ret < 0) |
119 | return ret; | |
120 | ||
cca8b133 | 121 | if ((ret & SMI_CMD_BUSY) == 0) |
91da11f8 LB |
122 | return 0; |
123 | } | |
124 | ||
125 | return -ETIMEDOUT; | |
126 | } | |
127 | ||
fad09c73 | 128 | static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, |
914b32f6 | 129 | int addr, int reg, u16 *val) |
91da11f8 LB |
130 | { |
131 | int ret; | |
132 | ||
3675c8d7 | 133 | /* Wait for the bus to become free. */ |
fad09c73 | 134 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
135 | if (ret < 0) |
136 | return ret; | |
137 | ||
3675c8d7 | 138 | /* Transmit the read command. */ |
fad09c73 | 139 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, |
6e899e6c | 140 | SMI_CMD_OP_22_READ | (addr << 5) | reg); |
91da11f8 LB |
141 | if (ret < 0) |
142 | return ret; | |
143 | ||
3675c8d7 | 144 | /* Wait for the read command to complete. */ |
fad09c73 | 145 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
146 | if (ret < 0) |
147 | return ret; | |
148 | ||
3675c8d7 | 149 | /* Read the data. */ |
fad09c73 | 150 | ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); |
bb92ea5e VD |
151 | if (ret < 0) |
152 | return ret; | |
153 | ||
914b32f6 | 154 | *val = ret & 0xffff; |
91da11f8 | 155 | |
914b32f6 | 156 | return 0; |
8d6d09e7 GR |
157 | } |
158 | ||
fad09c73 | 159 | static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, |
914b32f6 | 160 | int addr, int reg, u16 val) |
91da11f8 LB |
161 | { |
162 | int ret; | |
163 | ||
3675c8d7 | 164 | /* Wait for the bus to become free. */ |
fad09c73 | 165 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
166 | if (ret < 0) |
167 | return ret; | |
168 | ||
3675c8d7 | 169 | /* Transmit the data to write. */ |
fad09c73 | 170 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); |
91da11f8 LB |
171 | if (ret < 0) |
172 | return ret; | |
173 | ||
3675c8d7 | 174 | /* Transmit the write command. */ |
fad09c73 | 175 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, |
6e899e6c | 176 | SMI_CMD_OP_22_WRITE | (addr << 5) | reg); |
91da11f8 LB |
177 | if (ret < 0) |
178 | return ret; | |
179 | ||
3675c8d7 | 180 | /* Wait for the write command to complete. */ |
fad09c73 | 181 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
182 | if (ret < 0) |
183 | return ret; | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
c08026ab | 188 | static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { |
914b32f6 VD |
189 | .read = mv88e6xxx_smi_multi_chip_read, |
190 | .write = mv88e6xxx_smi_multi_chip_write, | |
191 | }; | |
192 | ||
ec561276 | 193 | int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) |
914b32f6 VD |
194 | { |
195 | int err; | |
196 | ||
fad09c73 | 197 | assert_reg_lock(chip); |
914b32f6 | 198 | |
fad09c73 | 199 | err = mv88e6xxx_smi_read(chip, addr, reg, val); |
914b32f6 VD |
200 | if (err) |
201 | return err; | |
202 | ||
fad09c73 | 203 | dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
914b32f6 VD |
204 | addr, reg, *val); |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
ec561276 | 209 | int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) |
91da11f8 | 210 | { |
914b32f6 VD |
211 | int err; |
212 | ||
fad09c73 | 213 | assert_reg_lock(chip); |
91da11f8 | 214 | |
fad09c73 | 215 | err = mv88e6xxx_smi_write(chip, addr, reg, val); |
914b32f6 VD |
216 | if (err) |
217 | return err; | |
218 | ||
fad09c73 | 219 | dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
bb92ea5e VD |
220 | addr, reg, val); |
221 | ||
914b32f6 VD |
222 | return 0; |
223 | } | |
224 | ||
e57e5e77 VD |
225 | static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy, |
226 | int reg, u16 *val) | |
227 | { | |
228 | int addr = phy; /* PHY devices addresses start at 0x0 */ | |
229 | ||
b3469dd8 | 230 | if (!chip->info->ops->phy_read) |
e57e5e77 VD |
231 | return -EOPNOTSUPP; |
232 | ||
b3469dd8 | 233 | return chip->info->ops->phy_read(chip, addr, reg, val); |
e57e5e77 VD |
234 | } |
235 | ||
236 | static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, | |
237 | int reg, u16 val) | |
238 | { | |
239 | int addr = phy; /* PHY devices addresses start at 0x0 */ | |
240 | ||
b3469dd8 | 241 | if (!chip->info->ops->phy_write) |
e57e5e77 VD |
242 | return -EOPNOTSUPP; |
243 | ||
b3469dd8 | 244 | return chip->info->ops->phy_write(chip, addr, reg, val); |
e57e5e77 VD |
245 | } |
246 | ||
09cb7dfd VD |
247 | static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page) |
248 | { | |
249 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE)) | |
250 | return -EOPNOTSUPP; | |
251 | ||
252 | return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); | |
253 | } | |
254 | ||
255 | static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy) | |
256 | { | |
257 | int err; | |
258 | ||
259 | /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */ | |
260 | err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER); | |
261 | if (unlikely(err)) { | |
262 | dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n", | |
263 | phy, err); | |
264 | } | |
265 | } | |
266 | ||
267 | static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy, | |
268 | u8 page, int reg, u16 *val) | |
269 | { | |
270 | int err; | |
271 | ||
272 | /* There is no paging for registers 22 */ | |
273 | if (reg == PHY_PAGE) | |
274 | return -EINVAL; | |
275 | ||
276 | err = mv88e6xxx_phy_page_get(chip, phy, page); | |
277 | if (!err) { | |
278 | err = mv88e6xxx_phy_read(chip, phy, reg, val); | |
279 | mv88e6xxx_phy_page_put(chip, phy); | |
280 | } | |
281 | ||
282 | return err; | |
283 | } | |
284 | ||
285 | static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy, | |
286 | u8 page, int reg, u16 val) | |
287 | { | |
288 | int err; | |
289 | ||
290 | /* There is no paging for registers 22 */ | |
291 | if (reg == PHY_PAGE) | |
292 | return -EINVAL; | |
293 | ||
294 | err = mv88e6xxx_phy_page_get(chip, phy, page); | |
295 | if (!err) { | |
296 | err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); | |
297 | mv88e6xxx_phy_page_put(chip, phy); | |
298 | } | |
299 | ||
300 | return err; | |
301 | } | |
302 | ||
303 | static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) | |
304 | { | |
305 | return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER, | |
306 | reg, val); | |
307 | } | |
308 | ||
309 | static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val) | |
310 | { | |
311 | return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER, | |
312 | reg, val); | |
313 | } | |
314 | ||
dc30c35b AL |
315 | static void mv88e6xxx_g1_irq_mask(struct irq_data *d) |
316 | { | |
317 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
318 | unsigned int n = d->hwirq; | |
319 | ||
320 | chip->g1_irq.masked |= (1 << n); | |
321 | } | |
322 | ||
323 | static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) | |
324 | { | |
325 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
326 | unsigned int n = d->hwirq; | |
327 | ||
328 | chip->g1_irq.masked &= ~(1 << n); | |
329 | } | |
330 | ||
331 | static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) | |
332 | { | |
333 | struct mv88e6xxx_chip *chip = dev_id; | |
334 | unsigned int nhandled = 0; | |
335 | unsigned int sub_irq; | |
336 | unsigned int n; | |
337 | u16 reg; | |
338 | int err; | |
339 | ||
340 | mutex_lock(&chip->reg_lock); | |
341 | err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®); | |
342 | mutex_unlock(&chip->reg_lock); | |
343 | ||
344 | if (err) | |
345 | goto out; | |
346 | ||
347 | for (n = 0; n < chip->g1_irq.nirqs; ++n) { | |
348 | if (reg & (1 << n)) { | |
349 | sub_irq = irq_find_mapping(chip->g1_irq.domain, n); | |
350 | handle_nested_irq(sub_irq); | |
351 | ++nhandled; | |
352 | } | |
353 | } | |
354 | out: | |
355 | return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); | |
356 | } | |
357 | ||
358 | static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) | |
359 | { | |
360 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
361 | ||
362 | mutex_lock(&chip->reg_lock); | |
363 | } | |
364 | ||
365 | static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) | |
366 | { | |
367 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
368 | u16 mask = GENMASK(chip->g1_irq.nirqs, 0); | |
369 | u16 reg; | |
370 | int err; | |
371 | ||
372 | err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®); | |
373 | if (err) | |
374 | goto out; | |
375 | ||
376 | reg &= ~mask; | |
377 | reg |= (~chip->g1_irq.masked & mask); | |
378 | ||
379 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg); | |
380 | if (err) | |
381 | goto out; | |
382 | ||
383 | out: | |
384 | mutex_unlock(&chip->reg_lock); | |
385 | } | |
386 | ||
387 | static struct irq_chip mv88e6xxx_g1_irq_chip = { | |
388 | .name = "mv88e6xxx-g1", | |
389 | .irq_mask = mv88e6xxx_g1_irq_mask, | |
390 | .irq_unmask = mv88e6xxx_g1_irq_unmask, | |
391 | .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, | |
392 | .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, | |
393 | }; | |
394 | ||
395 | static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, | |
396 | unsigned int irq, | |
397 | irq_hw_number_t hwirq) | |
398 | { | |
399 | struct mv88e6xxx_chip *chip = d->host_data; | |
400 | ||
401 | irq_set_chip_data(irq, d->host_data); | |
402 | irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); | |
403 | irq_set_noprobe(irq); | |
404 | ||
405 | return 0; | |
406 | } | |
407 | ||
408 | static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { | |
409 | .map = mv88e6xxx_g1_irq_domain_map, | |
410 | .xlate = irq_domain_xlate_twocell, | |
411 | }; | |
412 | ||
413 | static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) | |
414 | { | |
415 | int irq, virq; | |
416 | ||
417 | for (irq = 0; irq < 16; irq++) { | |
418 | virq = irq_find_mapping(chip->g2_irq.domain, irq); | |
419 | irq_dispose_mapping(virq); | |
420 | } | |
421 | ||
422 | irq_domain_remove(chip->g2_irq.domain); | |
423 | } | |
424 | ||
425 | static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) | |
426 | { | |
427 | int err, irq; | |
428 | u16 reg; | |
429 | ||
430 | chip->g1_irq.nirqs = chip->info->g1_irqs; | |
431 | chip->g1_irq.domain = irq_domain_add_simple( | |
432 | NULL, chip->g1_irq.nirqs, 0, | |
433 | &mv88e6xxx_g1_irq_domain_ops, chip); | |
434 | if (!chip->g1_irq.domain) | |
435 | return -ENOMEM; | |
436 | ||
437 | for (irq = 0; irq < chip->g1_irq.nirqs; irq++) | |
438 | irq_create_mapping(chip->g1_irq.domain, irq); | |
439 | ||
440 | chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; | |
441 | chip->g1_irq.masked = ~0; | |
442 | ||
443 | err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®); | |
444 | if (err) | |
445 | goto out; | |
446 | ||
447 | reg &= ~GENMASK(chip->g1_irq.nirqs, 0); | |
448 | ||
449 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg); | |
450 | if (err) | |
451 | goto out; | |
452 | ||
453 | /* Reading the interrupt status clears (most of) them */ | |
454 | err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®); | |
455 | if (err) | |
456 | goto out; | |
457 | ||
458 | err = request_threaded_irq(chip->irq, NULL, | |
459 | mv88e6xxx_g1_irq_thread_fn, | |
460 | IRQF_ONESHOT | IRQF_TRIGGER_FALLING, | |
461 | dev_name(chip->dev), chip); | |
462 | if (err) | |
463 | goto out; | |
464 | ||
465 | return 0; | |
466 | ||
467 | out: | |
468 | mv88e6xxx_g1_irq_free(chip); | |
469 | ||
470 | return err; | |
471 | } | |
472 | ||
ec561276 | 473 | int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) |
2d79af6e | 474 | { |
6441e669 | 475 | int i; |
2d79af6e | 476 | |
6441e669 | 477 | for (i = 0; i < 16; i++) { |
2d79af6e VD |
478 | u16 val; |
479 | int err; | |
480 | ||
481 | err = mv88e6xxx_read(chip, addr, reg, &val); | |
482 | if (err) | |
483 | return err; | |
484 | ||
485 | if (!(val & mask)) | |
486 | return 0; | |
487 | ||
488 | usleep_range(1000, 2000); | |
489 | } | |
490 | ||
30853553 | 491 | dev_err(chip->dev, "Timeout while waiting for switch\n"); |
2d79af6e VD |
492 | return -ETIMEDOUT; |
493 | } | |
494 | ||
f22ab641 | 495 | /* Indirect write to single pointer-data register with an Update bit */ |
ec561276 | 496 | int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) |
f22ab641 VD |
497 | { |
498 | u16 val; | |
0f02b4f7 | 499 | int err; |
f22ab641 VD |
500 | |
501 | /* Wait until the previous operation is completed */ | |
0f02b4f7 AL |
502 | err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); |
503 | if (err) | |
504 | return err; | |
f22ab641 VD |
505 | |
506 | /* Set the Update bit to trigger a write operation */ | |
507 | val = BIT(15) | update; | |
508 | ||
509 | return mv88e6xxx_write(chip, addr, reg, val); | |
510 | } | |
511 | ||
a935c052 | 512 | static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip) |
914b32f6 VD |
513 | { |
514 | u16 val; | |
a935c052 | 515 | int i, err; |
914b32f6 | 516 | |
a935c052 | 517 | err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val); |
914b32f6 VD |
518 | if (err) |
519 | return err; | |
520 | ||
a935c052 VD |
521 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, |
522 | val & ~GLOBAL_CONTROL_PPU_ENABLE); | |
523 | if (err) | |
524 | return err; | |
2e5f0320 | 525 | |
6441e669 | 526 | for (i = 0; i < 16; i++) { |
a935c052 VD |
527 | err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val); |
528 | if (err) | |
529 | return err; | |
48ace4ef | 530 | |
19b2f97e | 531 | usleep_range(1000, 2000); |
a935c052 | 532 | if ((val & GLOBAL_STATUS_PPU_MASK) != GLOBAL_STATUS_PPU_POLLING) |
85686581 | 533 | return 0; |
2e5f0320 LB |
534 | } |
535 | ||
536 | return -ETIMEDOUT; | |
537 | } | |
538 | ||
fad09c73 | 539 | static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip) |
2e5f0320 | 540 | { |
a935c052 VD |
541 | u16 val; |
542 | int i, err; | |
2e5f0320 | 543 | |
a935c052 VD |
544 | err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val); |
545 | if (err) | |
546 | return err; | |
48ace4ef | 547 | |
a935c052 VD |
548 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, |
549 | val | GLOBAL_CONTROL_PPU_ENABLE); | |
48ace4ef AL |
550 | if (err) |
551 | return err; | |
2e5f0320 | 552 | |
6441e669 | 553 | for (i = 0; i < 16; i++) { |
a935c052 VD |
554 | err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val); |
555 | if (err) | |
556 | return err; | |
48ace4ef | 557 | |
19b2f97e | 558 | usleep_range(1000, 2000); |
a935c052 | 559 | if ((val & GLOBAL_STATUS_PPU_MASK) == GLOBAL_STATUS_PPU_POLLING) |
85686581 | 560 | return 0; |
2e5f0320 LB |
561 | } |
562 | ||
563 | return -ETIMEDOUT; | |
564 | } | |
565 | ||
566 | static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) | |
567 | { | |
fad09c73 | 568 | struct mv88e6xxx_chip *chip; |
2e5f0320 | 569 | |
fad09c73 | 570 | chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work); |
762eb67b | 571 | |
fad09c73 | 572 | mutex_lock(&chip->reg_lock); |
762eb67b | 573 | |
fad09c73 VD |
574 | if (mutex_trylock(&chip->ppu_mutex)) { |
575 | if (mv88e6xxx_ppu_enable(chip) == 0) | |
576 | chip->ppu_disabled = 0; | |
577 | mutex_unlock(&chip->ppu_mutex); | |
2e5f0320 | 578 | } |
762eb67b | 579 | |
fad09c73 | 580 | mutex_unlock(&chip->reg_lock); |
2e5f0320 LB |
581 | } |
582 | ||
583 | static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) | |
584 | { | |
fad09c73 | 585 | struct mv88e6xxx_chip *chip = (void *)_ps; |
2e5f0320 | 586 | |
fad09c73 | 587 | schedule_work(&chip->ppu_work); |
2e5f0320 LB |
588 | } |
589 | ||
fad09c73 | 590 | static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip) |
2e5f0320 | 591 | { |
2e5f0320 LB |
592 | int ret; |
593 | ||
fad09c73 | 594 | mutex_lock(&chip->ppu_mutex); |
2e5f0320 | 595 | |
3675c8d7 | 596 | /* If the PHY polling unit is enabled, disable it so that |
2e5f0320 LB |
597 | * we can access the PHY registers. If it was already |
598 | * disabled, cancel the timer that is going to re-enable | |
599 | * it. | |
600 | */ | |
fad09c73 VD |
601 | if (!chip->ppu_disabled) { |
602 | ret = mv88e6xxx_ppu_disable(chip); | |
85686581 | 603 | if (ret < 0) { |
fad09c73 | 604 | mutex_unlock(&chip->ppu_mutex); |
85686581 BG |
605 | return ret; |
606 | } | |
fad09c73 | 607 | chip->ppu_disabled = 1; |
2e5f0320 | 608 | } else { |
fad09c73 | 609 | del_timer(&chip->ppu_timer); |
85686581 | 610 | ret = 0; |
2e5f0320 LB |
611 | } |
612 | ||
613 | return ret; | |
614 | } | |
615 | ||
fad09c73 | 616 | static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip) |
2e5f0320 | 617 | { |
3675c8d7 | 618 | /* Schedule a timer to re-enable the PHY polling unit. */ |
fad09c73 VD |
619 | mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10)); |
620 | mutex_unlock(&chip->ppu_mutex); | |
2e5f0320 LB |
621 | } |
622 | ||
fad09c73 | 623 | static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip) |
2e5f0320 | 624 | { |
fad09c73 VD |
625 | mutex_init(&chip->ppu_mutex); |
626 | INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work); | |
68497a87 WY |
627 | setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer, |
628 | (unsigned long)chip); | |
2e5f0320 LB |
629 | } |
630 | ||
930188ce AL |
631 | static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip) |
632 | { | |
633 | del_timer_sync(&chip->ppu_timer); | |
634 | } | |
635 | ||
e57e5e77 VD |
636 | static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr, |
637 | int reg, u16 *val) | |
2e5f0320 | 638 | { |
e57e5e77 | 639 | int err; |
2e5f0320 | 640 | |
e57e5e77 VD |
641 | err = mv88e6xxx_ppu_access_get(chip); |
642 | if (!err) { | |
643 | err = mv88e6xxx_read(chip, addr, reg, val); | |
fad09c73 | 644 | mv88e6xxx_ppu_access_put(chip); |
2e5f0320 LB |
645 | } |
646 | ||
e57e5e77 | 647 | return err; |
2e5f0320 LB |
648 | } |
649 | ||
e57e5e77 VD |
650 | static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr, |
651 | int reg, u16 val) | |
2e5f0320 | 652 | { |
e57e5e77 | 653 | int err; |
2e5f0320 | 654 | |
e57e5e77 VD |
655 | err = mv88e6xxx_ppu_access_get(chip); |
656 | if (!err) { | |
657 | err = mv88e6xxx_write(chip, addr, reg, val); | |
fad09c73 | 658 | mv88e6xxx_ppu_access_put(chip); |
2e5f0320 LB |
659 | } |
660 | ||
e57e5e77 | 661 | return err; |
2e5f0320 | 662 | } |
2e5f0320 | 663 | |
fad09c73 | 664 | static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip) |
54d792f2 | 665 | { |
fad09c73 | 666 | return chip->info->family == MV88E6XXX_FAMILY_6065; |
54d792f2 AL |
667 | } |
668 | ||
fad09c73 | 669 | static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip) |
54d792f2 | 670 | { |
fad09c73 | 671 | return chip->info->family == MV88E6XXX_FAMILY_6095; |
54d792f2 AL |
672 | } |
673 | ||
fad09c73 | 674 | static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip) |
54d792f2 | 675 | { |
fad09c73 | 676 | return chip->info->family == MV88E6XXX_FAMILY_6097; |
54d792f2 AL |
677 | } |
678 | ||
fad09c73 | 679 | static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip) |
54d792f2 | 680 | { |
fad09c73 | 681 | return chip->info->family == MV88E6XXX_FAMILY_6165; |
54d792f2 AL |
682 | } |
683 | ||
fad09c73 | 684 | static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip) |
54d792f2 | 685 | { |
fad09c73 | 686 | return chip->info->family == MV88E6XXX_FAMILY_6185; |
54d792f2 AL |
687 | } |
688 | ||
fad09c73 | 689 | static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip) |
7c3d0d67 | 690 | { |
fad09c73 | 691 | return chip->info->family == MV88E6XXX_FAMILY_6320; |
7c3d0d67 AK |
692 | } |
693 | ||
fad09c73 | 694 | static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip) |
54d792f2 | 695 | { |
fad09c73 | 696 | return chip->info->family == MV88E6XXX_FAMILY_6351; |
54d792f2 AL |
697 | } |
698 | ||
fad09c73 | 699 | static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip) |
f3a8b6b6 | 700 | { |
fad09c73 | 701 | return chip->info->family == MV88E6XXX_FAMILY_6352; |
f3a8b6b6 AL |
702 | } |
703 | ||
dea87024 AL |
704 | /* We expect the switch to perform auto negotiation if there is a real |
705 | * phy. However, in the case of a fixed link phy, we force the port | |
706 | * settings from the fixed link settings. | |
707 | */ | |
f81ec90f VD |
708 | static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, |
709 | struct phy_device *phydev) | |
dea87024 | 710 | { |
04bed143 | 711 | struct mv88e6xxx_chip *chip = ds->priv; |
0e7b9925 AL |
712 | u16 reg; |
713 | int err; | |
dea87024 AL |
714 | |
715 | if (!phy_is_pseudo_fixed_link(phydev)) | |
716 | return; | |
717 | ||
fad09c73 | 718 | mutex_lock(&chip->reg_lock); |
dea87024 | 719 | |
0e7b9925 AL |
720 | err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®); |
721 | if (err) | |
dea87024 AL |
722 | goto out; |
723 | ||
0e7b9925 AL |
724 | reg &= ~(PORT_PCS_CTRL_LINK_UP | |
725 | PORT_PCS_CTRL_FORCE_LINK | | |
726 | PORT_PCS_CTRL_DUPLEX_FULL | | |
727 | PORT_PCS_CTRL_FORCE_DUPLEX | | |
728 | PORT_PCS_CTRL_UNFORCED); | |
dea87024 AL |
729 | |
730 | reg |= PORT_PCS_CTRL_FORCE_LINK; | |
731 | if (phydev->link) | |
57d32310 | 732 | reg |= PORT_PCS_CTRL_LINK_UP; |
dea87024 | 733 | |
fad09c73 | 734 | if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100) |
dea87024 AL |
735 | goto out; |
736 | ||
737 | switch (phydev->speed) { | |
738 | case SPEED_1000: | |
739 | reg |= PORT_PCS_CTRL_1000; | |
740 | break; | |
741 | case SPEED_100: | |
742 | reg |= PORT_PCS_CTRL_100; | |
743 | break; | |
744 | case SPEED_10: | |
745 | reg |= PORT_PCS_CTRL_10; | |
746 | break; | |
747 | default: | |
748 | pr_info("Unknown speed"); | |
749 | goto out; | |
750 | } | |
751 | ||
752 | reg |= PORT_PCS_CTRL_FORCE_DUPLEX; | |
753 | if (phydev->duplex == DUPLEX_FULL) | |
754 | reg |= PORT_PCS_CTRL_DUPLEX_FULL; | |
755 | ||
fad09c73 | 756 | if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) && |
370b4ffb | 757 | (port >= mv88e6xxx_num_ports(chip) - 2)) { |
e7e72ac0 AL |
758 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) |
759 | reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK; | |
760 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) | |
761 | reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK; | |
762 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) | |
763 | reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK | | |
764 | PORT_PCS_CTRL_RGMII_DELAY_TXCLK); | |
765 | } | |
0e7b9925 | 766 | mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg); |
dea87024 AL |
767 | |
768 | out: | |
fad09c73 | 769 | mutex_unlock(&chip->reg_lock); |
dea87024 AL |
770 | } |
771 | ||
fad09c73 | 772 | static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip) |
91da11f8 | 773 | { |
a935c052 VD |
774 | u16 val; |
775 | int i, err; | |
91da11f8 LB |
776 | |
777 | for (i = 0; i < 10; i++) { | |
a935c052 VD |
778 | err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_OP, &val); |
779 | if ((val & GLOBAL_STATS_OP_BUSY) == 0) | |
91da11f8 LB |
780 | return 0; |
781 | } | |
782 | ||
783 | return -ETIMEDOUT; | |
784 | } | |
785 | ||
fad09c73 | 786 | static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) |
91da11f8 | 787 | { |
a935c052 | 788 | int err; |
91da11f8 | 789 | |
fad09c73 | 790 | if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip)) |
f3a8b6b6 AL |
791 | port = (port + 1) << 5; |
792 | ||
3675c8d7 | 793 | /* Snapshot the hardware statistics counters for this port. */ |
a935c052 VD |
794 | err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP, |
795 | GLOBAL_STATS_OP_CAPTURE_PORT | | |
796 | GLOBAL_STATS_OP_HIST_RX_TX | port); | |
797 | if (err) | |
798 | return err; | |
91da11f8 | 799 | |
3675c8d7 | 800 | /* Wait for the snapshotting to complete. */ |
a935c052 | 801 | return _mv88e6xxx_stats_wait(chip); |
91da11f8 LB |
802 | } |
803 | ||
fad09c73 | 804 | static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip, |
158bc065 | 805 | int stat, u32 *val) |
91da11f8 | 806 | { |
a935c052 VD |
807 | u32 value; |
808 | u16 reg; | |
809 | int err; | |
91da11f8 LB |
810 | |
811 | *val = 0; | |
812 | ||
a935c052 VD |
813 | err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP, |
814 | GLOBAL_STATS_OP_READ_CAPTURED | | |
815 | GLOBAL_STATS_OP_HIST_RX_TX | stat); | |
816 | if (err) | |
91da11f8 LB |
817 | return; |
818 | ||
a935c052 VD |
819 | err = _mv88e6xxx_stats_wait(chip); |
820 | if (err) | |
91da11f8 LB |
821 | return; |
822 | ||
a935c052 VD |
823 | err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_32, ®); |
824 | if (err) | |
91da11f8 LB |
825 | return; |
826 | ||
a935c052 | 827 | value = reg << 16; |
91da11f8 | 828 | |
a935c052 VD |
829 | err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_01, ®); |
830 | if (err) | |
91da11f8 LB |
831 | return; |
832 | ||
a935c052 | 833 | *val = value | reg; |
91da11f8 LB |
834 | } |
835 | ||
e413e7e1 | 836 | static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { |
f5e2ed02 AL |
837 | { "in_good_octets", 8, 0x00, BANK0, }, |
838 | { "in_bad_octets", 4, 0x02, BANK0, }, | |
839 | { "in_unicast", 4, 0x04, BANK0, }, | |
840 | { "in_broadcasts", 4, 0x06, BANK0, }, | |
841 | { "in_multicasts", 4, 0x07, BANK0, }, | |
842 | { "in_pause", 4, 0x16, BANK0, }, | |
843 | { "in_undersize", 4, 0x18, BANK0, }, | |
844 | { "in_fragments", 4, 0x19, BANK0, }, | |
845 | { "in_oversize", 4, 0x1a, BANK0, }, | |
846 | { "in_jabber", 4, 0x1b, BANK0, }, | |
847 | { "in_rx_error", 4, 0x1c, BANK0, }, | |
848 | { "in_fcs_error", 4, 0x1d, BANK0, }, | |
849 | { "out_octets", 8, 0x0e, BANK0, }, | |
850 | { "out_unicast", 4, 0x10, BANK0, }, | |
851 | { "out_broadcasts", 4, 0x13, BANK0, }, | |
852 | { "out_multicasts", 4, 0x12, BANK0, }, | |
853 | { "out_pause", 4, 0x15, BANK0, }, | |
854 | { "excessive", 4, 0x11, BANK0, }, | |
855 | { "collisions", 4, 0x1e, BANK0, }, | |
856 | { "deferred", 4, 0x05, BANK0, }, | |
857 | { "single", 4, 0x14, BANK0, }, | |
858 | { "multiple", 4, 0x17, BANK0, }, | |
859 | { "out_fcs_error", 4, 0x03, BANK0, }, | |
860 | { "late", 4, 0x1f, BANK0, }, | |
861 | { "hist_64bytes", 4, 0x08, BANK0, }, | |
862 | { "hist_65_127bytes", 4, 0x09, BANK0, }, | |
863 | { "hist_128_255bytes", 4, 0x0a, BANK0, }, | |
864 | { "hist_256_511bytes", 4, 0x0b, BANK0, }, | |
865 | { "hist_512_1023bytes", 4, 0x0c, BANK0, }, | |
866 | { "hist_1024_max_bytes", 4, 0x0d, BANK0, }, | |
867 | { "sw_in_discards", 4, 0x10, PORT, }, | |
868 | { "sw_in_filtered", 2, 0x12, PORT, }, | |
869 | { "sw_out_filtered", 2, 0x13, PORT, }, | |
870 | { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
871 | { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
872 | { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
873 | { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
874 | { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
875 | { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
876 | { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
877 | { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
878 | { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
879 | { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
880 | { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
881 | { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
882 | { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
883 | { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
884 | { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
885 | { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
886 | { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
887 | { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
888 | { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
889 | { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
890 | { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
891 | { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
892 | { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
893 | { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
894 | { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
895 | { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
e413e7e1 AL |
896 | }; |
897 | ||
fad09c73 | 898 | static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip, |
f5e2ed02 | 899 | struct mv88e6xxx_hw_stat *stat) |
e413e7e1 | 900 | { |
f5e2ed02 AL |
901 | switch (stat->type) { |
902 | case BANK0: | |
e413e7e1 | 903 | return true; |
f5e2ed02 | 904 | case BANK1: |
fad09c73 | 905 | return mv88e6xxx_6320_family(chip); |
f5e2ed02 | 906 | case PORT: |
fad09c73 VD |
907 | return mv88e6xxx_6095_family(chip) || |
908 | mv88e6xxx_6185_family(chip) || | |
909 | mv88e6xxx_6097_family(chip) || | |
910 | mv88e6xxx_6165_family(chip) || | |
911 | mv88e6xxx_6351_family(chip) || | |
912 | mv88e6xxx_6352_family(chip); | |
91da11f8 | 913 | } |
f5e2ed02 | 914 | return false; |
91da11f8 LB |
915 | } |
916 | ||
fad09c73 | 917 | static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, |
f5e2ed02 | 918 | struct mv88e6xxx_hw_stat *s, |
80c4627b AL |
919 | int port) |
920 | { | |
80c4627b AL |
921 | u32 low; |
922 | u32 high = 0; | |
0e7b9925 AL |
923 | int err; |
924 | u16 reg; | |
80c4627b AL |
925 | u64 value; |
926 | ||
f5e2ed02 AL |
927 | switch (s->type) { |
928 | case PORT: | |
0e7b9925 AL |
929 | err = mv88e6xxx_port_read(chip, port, s->reg, ®); |
930 | if (err) | |
80c4627b AL |
931 | return UINT64_MAX; |
932 | ||
0e7b9925 | 933 | low = reg; |
80c4627b | 934 | if (s->sizeof_stat == 4) { |
0e7b9925 AL |
935 | err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); |
936 | if (err) | |
80c4627b | 937 | return UINT64_MAX; |
0e7b9925 | 938 | high = reg; |
80c4627b | 939 | } |
f5e2ed02 AL |
940 | break; |
941 | case BANK0: | |
942 | case BANK1: | |
fad09c73 | 943 | _mv88e6xxx_stats_read(chip, s->reg, &low); |
80c4627b | 944 | if (s->sizeof_stat == 8) |
fad09c73 | 945 | _mv88e6xxx_stats_read(chip, s->reg + 1, &high); |
80c4627b AL |
946 | } |
947 | value = (((u64)high) << 16) | low; | |
948 | return value; | |
949 | } | |
950 | ||
f81ec90f VD |
951 | static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, |
952 | uint8_t *data) | |
91da11f8 | 953 | { |
04bed143 | 954 | struct mv88e6xxx_chip *chip = ds->priv; |
f5e2ed02 AL |
955 | struct mv88e6xxx_hw_stat *stat; |
956 | int i, j; | |
91da11f8 | 957 | |
f5e2ed02 AL |
958 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { |
959 | stat = &mv88e6xxx_hw_stats[i]; | |
fad09c73 | 960 | if (mv88e6xxx_has_stat(chip, stat)) { |
f5e2ed02 AL |
961 | memcpy(data + j * ETH_GSTRING_LEN, stat->string, |
962 | ETH_GSTRING_LEN); | |
963 | j++; | |
964 | } | |
91da11f8 | 965 | } |
e413e7e1 AL |
966 | } |
967 | ||
f81ec90f | 968 | static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) |
e413e7e1 | 969 | { |
04bed143 | 970 | struct mv88e6xxx_chip *chip = ds->priv; |
f5e2ed02 AL |
971 | struct mv88e6xxx_hw_stat *stat; |
972 | int i, j; | |
973 | ||
974 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { | |
975 | stat = &mv88e6xxx_hw_stats[i]; | |
fad09c73 | 976 | if (mv88e6xxx_has_stat(chip, stat)) |
f5e2ed02 AL |
977 | j++; |
978 | } | |
979 | return j; | |
e413e7e1 AL |
980 | } |
981 | ||
f81ec90f VD |
982 | static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, |
983 | uint64_t *data) | |
e413e7e1 | 984 | { |
04bed143 | 985 | struct mv88e6xxx_chip *chip = ds->priv; |
f5e2ed02 AL |
986 | struct mv88e6xxx_hw_stat *stat; |
987 | int ret; | |
988 | int i, j; | |
989 | ||
fad09c73 | 990 | mutex_lock(&chip->reg_lock); |
f5e2ed02 | 991 | |
fad09c73 | 992 | ret = _mv88e6xxx_stats_snapshot(chip, port); |
f5e2ed02 | 993 | if (ret < 0) { |
fad09c73 | 994 | mutex_unlock(&chip->reg_lock); |
f5e2ed02 AL |
995 | return; |
996 | } | |
997 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { | |
998 | stat = &mv88e6xxx_hw_stats[i]; | |
fad09c73 VD |
999 | if (mv88e6xxx_has_stat(chip, stat)) { |
1000 | data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port); | |
f5e2ed02 AL |
1001 | j++; |
1002 | } | |
1003 | } | |
1004 | ||
fad09c73 | 1005 | mutex_unlock(&chip->reg_lock); |
e413e7e1 AL |
1006 | } |
1007 | ||
f81ec90f | 1008 | static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) |
a1ab91f3 GR |
1009 | { |
1010 | return 32 * sizeof(u16); | |
1011 | } | |
1012 | ||
f81ec90f VD |
1013 | static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, |
1014 | struct ethtool_regs *regs, void *_p) | |
a1ab91f3 | 1015 | { |
04bed143 | 1016 | struct mv88e6xxx_chip *chip = ds->priv; |
0e7b9925 AL |
1017 | int err; |
1018 | u16 reg; | |
a1ab91f3 GR |
1019 | u16 *p = _p; |
1020 | int i; | |
1021 | ||
1022 | regs->version = 0; | |
1023 | ||
1024 | memset(p, 0xff, 32 * sizeof(u16)); | |
1025 | ||
fad09c73 | 1026 | mutex_lock(&chip->reg_lock); |
23062513 | 1027 | |
a1ab91f3 | 1028 | for (i = 0; i < 32; i++) { |
a1ab91f3 | 1029 | |
0e7b9925 AL |
1030 | err = mv88e6xxx_port_read(chip, port, i, ®); |
1031 | if (!err) | |
1032 | p[i] = reg; | |
a1ab91f3 | 1033 | } |
23062513 | 1034 | |
fad09c73 | 1035 | mutex_unlock(&chip->reg_lock); |
a1ab91f3 GR |
1036 | } |
1037 | ||
fad09c73 | 1038 | static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip) |
facd95b2 | 1039 | { |
a935c052 | 1040 | return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY); |
facd95b2 GR |
1041 | } |
1042 | ||
f81ec90f VD |
1043 | static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, |
1044 | struct ethtool_eee *e) | |
11b3b45d | 1045 | { |
04bed143 | 1046 | struct mv88e6xxx_chip *chip = ds->priv; |
9c93829c VD |
1047 | u16 reg; |
1048 | int err; | |
11b3b45d | 1049 | |
fad09c73 | 1050 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) |
aadbdb8a VD |
1051 | return -EOPNOTSUPP; |
1052 | ||
fad09c73 | 1053 | mutex_lock(&chip->reg_lock); |
2f40c698 | 1054 | |
9c93829c VD |
1055 | err = mv88e6xxx_phy_read(chip, port, 16, ®); |
1056 | if (err) | |
2f40c698 | 1057 | goto out; |
11b3b45d GR |
1058 | |
1059 | e->eee_enabled = !!(reg & 0x0200); | |
1060 | e->tx_lpi_enabled = !!(reg & 0x0100); | |
1061 | ||
0e7b9925 | 1062 | err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®); |
9c93829c | 1063 | if (err) |
2f40c698 | 1064 | goto out; |
11b3b45d | 1065 | |
cca8b133 | 1066 | e->eee_active = !!(reg & PORT_STATUS_EEE); |
2f40c698 | 1067 | out: |
fad09c73 | 1068 | mutex_unlock(&chip->reg_lock); |
9c93829c VD |
1069 | |
1070 | return err; | |
11b3b45d GR |
1071 | } |
1072 | ||
f81ec90f VD |
1073 | static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, |
1074 | struct phy_device *phydev, struct ethtool_eee *e) | |
11b3b45d | 1075 | { |
04bed143 | 1076 | struct mv88e6xxx_chip *chip = ds->priv; |
9c93829c VD |
1077 | u16 reg; |
1078 | int err; | |
11b3b45d | 1079 | |
fad09c73 | 1080 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) |
aadbdb8a VD |
1081 | return -EOPNOTSUPP; |
1082 | ||
fad09c73 | 1083 | mutex_lock(&chip->reg_lock); |
11b3b45d | 1084 | |
9c93829c VD |
1085 | err = mv88e6xxx_phy_read(chip, port, 16, ®); |
1086 | if (err) | |
2f40c698 AL |
1087 | goto out; |
1088 | ||
9c93829c | 1089 | reg &= ~0x0300; |
2f40c698 AL |
1090 | if (e->eee_enabled) |
1091 | reg |= 0x0200; | |
1092 | if (e->tx_lpi_enabled) | |
1093 | reg |= 0x0100; | |
1094 | ||
9c93829c | 1095 | err = mv88e6xxx_phy_write(chip, port, 16, reg); |
2f40c698 | 1096 | out: |
fad09c73 | 1097 | mutex_unlock(&chip->reg_lock); |
2f40c698 | 1098 | |
9c93829c | 1099 | return err; |
11b3b45d GR |
1100 | } |
1101 | ||
fad09c73 | 1102 | static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd) |
facd95b2 | 1103 | { |
a935c052 VD |
1104 | u16 val; |
1105 | int err; | |
facd95b2 | 1106 | |
6dc10bbc | 1107 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) { |
a935c052 VD |
1108 | err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid); |
1109 | if (err) | |
1110 | return err; | |
fad09c73 | 1111 | } else if (mv88e6xxx_num_databases(chip) == 256) { |
11ea809f | 1112 | /* ATU DBNum[7:4] are located in ATU Control 15:12 */ |
a935c052 VD |
1113 | err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val); |
1114 | if (err) | |
1115 | return err; | |
11ea809f | 1116 | |
a935c052 VD |
1117 | err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, |
1118 | (val & 0xfff) | ((fid << 8) & 0xf000)); | |
1119 | if (err) | |
1120 | return err; | |
11ea809f VD |
1121 | |
1122 | /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ | |
1123 | cmd |= fid & 0xf; | |
b426e5f7 VD |
1124 | } |
1125 | ||
a935c052 VD |
1126 | err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd); |
1127 | if (err) | |
1128 | return err; | |
facd95b2 | 1129 | |
fad09c73 | 1130 | return _mv88e6xxx_atu_wait(chip); |
facd95b2 GR |
1131 | } |
1132 | ||
fad09c73 | 1133 | static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip, |
37705b73 VD |
1134 | struct mv88e6xxx_atu_entry *entry) |
1135 | { | |
1136 | u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK; | |
1137 | ||
1138 | if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) { | |
1139 | unsigned int mask, shift; | |
1140 | ||
1141 | if (entry->trunk) { | |
1142 | data |= GLOBAL_ATU_DATA_TRUNK; | |
1143 | mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; | |
1144 | shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; | |
1145 | } else { | |
1146 | mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; | |
1147 | shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; | |
1148 | } | |
1149 | ||
1150 | data |= (entry->portv_trunkid << shift) & mask; | |
1151 | } | |
1152 | ||
a935c052 | 1153 | return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data); |
37705b73 VD |
1154 | } |
1155 | ||
fad09c73 | 1156 | static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip, |
7fb5e755 VD |
1157 | struct mv88e6xxx_atu_entry *entry, |
1158 | bool static_too) | |
facd95b2 | 1159 | { |
7fb5e755 VD |
1160 | int op; |
1161 | int err; | |
facd95b2 | 1162 | |
fad09c73 | 1163 | err = _mv88e6xxx_atu_wait(chip); |
7fb5e755 VD |
1164 | if (err) |
1165 | return err; | |
facd95b2 | 1166 | |
fad09c73 | 1167 | err = _mv88e6xxx_atu_data_write(chip, entry); |
7fb5e755 VD |
1168 | if (err) |
1169 | return err; | |
1170 | ||
1171 | if (entry->fid) { | |
7fb5e755 VD |
1172 | op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB : |
1173 | GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; | |
1174 | } else { | |
1175 | op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL : | |
1176 | GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC; | |
1177 | } | |
1178 | ||
fad09c73 | 1179 | return _mv88e6xxx_atu_cmd(chip, entry->fid, op); |
7fb5e755 VD |
1180 | } |
1181 | ||
fad09c73 | 1182 | static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip, |
158bc065 | 1183 | u16 fid, bool static_too) |
7fb5e755 VD |
1184 | { |
1185 | struct mv88e6xxx_atu_entry entry = { | |
1186 | .fid = fid, | |
1187 | .state = 0, /* EntryState bits must be 0 */ | |
1188 | }; | |
70cc99d1 | 1189 | |
fad09c73 | 1190 | return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); |
7fb5e755 VD |
1191 | } |
1192 | ||
fad09c73 | 1193 | static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid, |
158bc065 | 1194 | int from_port, int to_port, bool static_too) |
9f4d55d2 VD |
1195 | { |
1196 | struct mv88e6xxx_atu_entry entry = { | |
1197 | .trunk = false, | |
1198 | .fid = fid, | |
1199 | }; | |
1200 | ||
1201 | /* EntryState bits must be 0xF */ | |
1202 | entry.state = GLOBAL_ATU_DATA_STATE_MASK; | |
1203 | ||
1204 | /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */ | |
1205 | entry.portv_trunkid = (to_port & 0x0f) << 4; | |
1206 | entry.portv_trunkid |= from_port & 0x0f; | |
1207 | ||
fad09c73 | 1208 | return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); |
9f4d55d2 VD |
1209 | } |
1210 | ||
fad09c73 | 1211 | static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, |
158bc065 | 1212 | int port, bool static_too) |
9f4d55d2 VD |
1213 | { |
1214 | /* Destination port 0xF means remove the entries */ | |
fad09c73 | 1215 | return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too); |
9f4d55d2 VD |
1216 | } |
1217 | ||
fad09c73 | 1218 | static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port) |
facd95b2 | 1219 | { |
fad09c73 | 1220 | struct net_device *bridge = chip->ports[port].bridge_dev; |
fad09c73 | 1221 | struct dsa_switch *ds = chip->ds; |
b7666efe | 1222 | u16 output_ports = 0; |
b7666efe VD |
1223 | int i; |
1224 | ||
1225 | /* allow CPU port or DSA link(s) to send frames to every port */ | |
1226 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { | |
5a7921f4 | 1227 | output_ports = ~0; |
b7666efe | 1228 | } else { |
370b4ffb | 1229 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
b7666efe | 1230 | /* allow sending frames to every group member */ |
fad09c73 | 1231 | if (bridge && chip->ports[i].bridge_dev == bridge) |
b7666efe VD |
1232 | output_ports |= BIT(i); |
1233 | ||
1234 | /* allow sending frames to CPU port and DSA link(s) */ | |
1235 | if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) | |
1236 | output_ports |= BIT(i); | |
1237 | } | |
1238 | } | |
1239 | ||
1240 | /* prevent frames from going back out of the port they came in on */ | |
1241 | output_ports &= ~BIT(port); | |
facd95b2 | 1242 | |
5a7921f4 | 1243 | return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); |
facd95b2 GR |
1244 | } |
1245 | ||
f81ec90f VD |
1246 | static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, |
1247 | u8 state) | |
facd95b2 | 1248 | { |
04bed143 | 1249 | struct mv88e6xxx_chip *chip = ds->priv; |
facd95b2 | 1250 | int stp_state; |
553eb544 | 1251 | int err; |
facd95b2 GR |
1252 | |
1253 | switch (state) { | |
1254 | case BR_STATE_DISABLED: | |
cca8b133 | 1255 | stp_state = PORT_CONTROL_STATE_DISABLED; |
facd95b2 GR |
1256 | break; |
1257 | case BR_STATE_BLOCKING: | |
1258 | case BR_STATE_LISTENING: | |
cca8b133 | 1259 | stp_state = PORT_CONTROL_STATE_BLOCKING; |
facd95b2 GR |
1260 | break; |
1261 | case BR_STATE_LEARNING: | |
cca8b133 | 1262 | stp_state = PORT_CONTROL_STATE_LEARNING; |
facd95b2 GR |
1263 | break; |
1264 | case BR_STATE_FORWARDING: | |
1265 | default: | |
cca8b133 | 1266 | stp_state = PORT_CONTROL_STATE_FORWARDING; |
facd95b2 GR |
1267 | break; |
1268 | } | |
1269 | ||
fad09c73 | 1270 | mutex_lock(&chip->reg_lock); |
e28def33 | 1271 | err = mv88e6xxx_port_set_state(chip, port, stp_state); |
fad09c73 | 1272 | mutex_unlock(&chip->reg_lock); |
553eb544 VD |
1273 | |
1274 | if (err) | |
e28def33 | 1275 | netdev_err(ds->ports[port].netdev, "failed to update state\n"); |
facd95b2 GR |
1276 | } |
1277 | ||
749efcb8 VD |
1278 | static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) |
1279 | { | |
1280 | struct mv88e6xxx_chip *chip = ds->priv; | |
1281 | int err; | |
1282 | ||
1283 | mutex_lock(&chip->reg_lock); | |
1284 | err = _mv88e6xxx_atu_remove(chip, 0, port, false); | |
1285 | mutex_unlock(&chip->reg_lock); | |
1286 | ||
1287 | if (err) | |
1288 | netdev_err(ds->ports[port].netdev, "failed to flush ATU\n"); | |
1289 | } | |
1290 | ||
fad09c73 | 1291 | static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip) |
6b17e864 | 1292 | { |
a935c052 | 1293 | return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY); |
6b17e864 VD |
1294 | } |
1295 | ||
fad09c73 | 1296 | static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op) |
6b17e864 | 1297 | { |
a935c052 | 1298 | int err; |
6b17e864 | 1299 | |
a935c052 VD |
1300 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op); |
1301 | if (err) | |
1302 | return err; | |
6b17e864 | 1303 | |
fad09c73 | 1304 | return _mv88e6xxx_vtu_wait(chip); |
6b17e864 VD |
1305 | } |
1306 | ||
fad09c73 | 1307 | static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip) |
6b17e864 VD |
1308 | { |
1309 | int ret; | |
1310 | ||
fad09c73 | 1311 | ret = _mv88e6xxx_vtu_wait(chip); |
6b17e864 VD |
1312 | if (ret < 0) |
1313 | return ret; | |
1314 | ||
fad09c73 | 1315 | return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL); |
6b17e864 VD |
1316 | } |
1317 | ||
fad09c73 | 1318 | static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1319 | struct mv88e6xxx_vtu_entry *entry, |
b8fee957 VD |
1320 | unsigned int nibble_offset) |
1321 | { | |
b8fee957 | 1322 | u16 regs[3]; |
a935c052 | 1323 | int i, err; |
b8fee957 VD |
1324 | |
1325 | for (i = 0; i < 3; ++i) { | |
a935c052 | 1326 | u16 *reg = ®s[i]; |
b8fee957 | 1327 | |
a935c052 VD |
1328 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg); |
1329 | if (err) | |
1330 | return err; | |
b8fee957 VD |
1331 | } |
1332 | ||
370b4ffb | 1333 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
b8fee957 VD |
1334 | unsigned int shift = (i % 4) * 4 + nibble_offset; |
1335 | u16 reg = regs[i / 4]; | |
1336 | ||
1337 | entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK; | |
1338 | } | |
1339 | ||
1340 | return 0; | |
1341 | } | |
1342 | ||
fad09c73 | 1343 | static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1344 | struct mv88e6xxx_vtu_entry *entry) |
15d7d7d4 | 1345 | { |
fad09c73 | 1346 | return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0); |
15d7d7d4 VD |
1347 | } |
1348 | ||
fad09c73 | 1349 | static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1350 | struct mv88e6xxx_vtu_entry *entry) |
15d7d7d4 | 1351 | { |
fad09c73 | 1352 | return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2); |
15d7d7d4 VD |
1353 | } |
1354 | ||
fad09c73 | 1355 | static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1356 | struct mv88e6xxx_vtu_entry *entry, |
7dad08d7 VD |
1357 | unsigned int nibble_offset) |
1358 | { | |
7dad08d7 | 1359 | u16 regs[3] = { 0 }; |
a935c052 | 1360 | int i, err; |
7dad08d7 | 1361 | |
370b4ffb | 1362 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
7dad08d7 VD |
1363 | unsigned int shift = (i % 4) * 4 + nibble_offset; |
1364 | u8 data = entry->data[i]; | |
1365 | ||
1366 | regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift; | |
1367 | } | |
1368 | ||
1369 | for (i = 0; i < 3; ++i) { | |
a935c052 VD |
1370 | u16 reg = regs[i]; |
1371 | ||
1372 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg); | |
1373 | if (err) | |
1374 | return err; | |
7dad08d7 VD |
1375 | } |
1376 | ||
1377 | return 0; | |
1378 | } | |
1379 | ||
fad09c73 | 1380 | static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1381 | struct mv88e6xxx_vtu_entry *entry) |
15d7d7d4 | 1382 | { |
fad09c73 | 1383 | return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0); |
15d7d7d4 VD |
1384 | } |
1385 | ||
fad09c73 | 1386 | static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1387 | struct mv88e6xxx_vtu_entry *entry) |
15d7d7d4 | 1388 | { |
fad09c73 | 1389 | return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2); |
15d7d7d4 VD |
1390 | } |
1391 | ||
fad09c73 | 1392 | static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid) |
36d04ba1 | 1393 | { |
a935c052 VD |
1394 | return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, |
1395 | vid & GLOBAL_VTU_VID_MASK); | |
36d04ba1 VD |
1396 | } |
1397 | ||
fad09c73 | 1398 | static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1399 | struct mv88e6xxx_vtu_entry *entry) |
b8fee957 | 1400 | { |
b4e47c0f | 1401 | struct mv88e6xxx_vtu_entry next = { 0 }; |
a935c052 VD |
1402 | u16 val; |
1403 | int err; | |
b8fee957 | 1404 | |
a935c052 VD |
1405 | err = _mv88e6xxx_vtu_wait(chip); |
1406 | if (err) | |
1407 | return err; | |
b8fee957 | 1408 | |
a935c052 VD |
1409 | err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT); |
1410 | if (err) | |
1411 | return err; | |
b8fee957 | 1412 | |
a935c052 VD |
1413 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val); |
1414 | if (err) | |
1415 | return err; | |
b8fee957 | 1416 | |
a935c052 VD |
1417 | next.vid = val & GLOBAL_VTU_VID_MASK; |
1418 | next.valid = !!(val & GLOBAL_VTU_VID_VALID); | |
b8fee957 VD |
1419 | |
1420 | if (next.valid) { | |
a935c052 VD |
1421 | err = mv88e6xxx_vtu_data_read(chip, &next); |
1422 | if (err) | |
1423 | return err; | |
b8fee957 | 1424 | |
6dc10bbc | 1425 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) { |
a935c052 VD |
1426 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val); |
1427 | if (err) | |
1428 | return err; | |
b8fee957 | 1429 | |
a935c052 | 1430 | next.fid = val & GLOBAL_VTU_FID_MASK; |
fad09c73 | 1431 | } else if (mv88e6xxx_num_databases(chip) == 256) { |
11ea809f VD |
1432 | /* VTU DBNum[7:4] are located in VTU Operation 11:8, and |
1433 | * VTU DBNum[3:0] are located in VTU Operation 3:0 | |
1434 | */ | |
a935c052 VD |
1435 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val); |
1436 | if (err) | |
1437 | return err; | |
11ea809f | 1438 | |
a935c052 VD |
1439 | next.fid = (val & 0xf00) >> 4; |
1440 | next.fid |= val & 0xf; | |
2e7bd5ef | 1441 | } |
b8fee957 | 1442 | |
fad09c73 | 1443 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { |
a935c052 VD |
1444 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val); |
1445 | if (err) | |
1446 | return err; | |
b8fee957 | 1447 | |
a935c052 | 1448 | next.sid = val & GLOBAL_VTU_SID_MASK; |
b8fee957 VD |
1449 | } |
1450 | } | |
1451 | ||
1452 | *entry = next; | |
1453 | return 0; | |
1454 | } | |
1455 | ||
f81ec90f VD |
1456 | static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port, |
1457 | struct switchdev_obj_port_vlan *vlan, | |
1458 | int (*cb)(struct switchdev_obj *obj)) | |
ceff5eff | 1459 | { |
04bed143 | 1460 | struct mv88e6xxx_chip *chip = ds->priv; |
b4e47c0f | 1461 | struct mv88e6xxx_vtu_entry next; |
ceff5eff VD |
1462 | u16 pvid; |
1463 | int err; | |
1464 | ||
fad09c73 | 1465 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
54d77b5b VD |
1466 | return -EOPNOTSUPP; |
1467 | ||
fad09c73 | 1468 | mutex_lock(&chip->reg_lock); |
ceff5eff | 1469 | |
77064f37 | 1470 | err = mv88e6xxx_port_get_pvid(chip, port, &pvid); |
ceff5eff VD |
1471 | if (err) |
1472 | goto unlock; | |
1473 | ||
fad09c73 | 1474 | err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); |
ceff5eff VD |
1475 | if (err) |
1476 | goto unlock; | |
1477 | ||
1478 | do { | |
fad09c73 | 1479 | err = _mv88e6xxx_vtu_getnext(chip, &next); |
ceff5eff VD |
1480 | if (err) |
1481 | break; | |
1482 | ||
1483 | if (!next.valid) | |
1484 | break; | |
1485 | ||
1486 | if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) | |
1487 | continue; | |
1488 | ||
1489 | /* reinit and dump this VLAN obj */ | |
57d32310 VD |
1490 | vlan->vid_begin = next.vid; |
1491 | vlan->vid_end = next.vid; | |
ceff5eff VD |
1492 | vlan->flags = 0; |
1493 | ||
1494 | if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED) | |
1495 | vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED; | |
1496 | ||
1497 | if (next.vid == pvid) | |
1498 | vlan->flags |= BRIDGE_VLAN_INFO_PVID; | |
1499 | ||
1500 | err = cb(&vlan->obj); | |
1501 | if (err) | |
1502 | break; | |
1503 | } while (next.vid < GLOBAL_VTU_VID_MASK); | |
1504 | ||
1505 | unlock: | |
fad09c73 | 1506 | mutex_unlock(&chip->reg_lock); |
ceff5eff VD |
1507 | |
1508 | return err; | |
1509 | } | |
1510 | ||
fad09c73 | 1511 | static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1512 | struct mv88e6xxx_vtu_entry *entry) |
7dad08d7 | 1513 | { |
11ea809f | 1514 | u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE; |
7dad08d7 | 1515 | u16 reg = 0; |
a935c052 | 1516 | int err; |
7dad08d7 | 1517 | |
a935c052 VD |
1518 | err = _mv88e6xxx_vtu_wait(chip); |
1519 | if (err) | |
1520 | return err; | |
7dad08d7 VD |
1521 | |
1522 | if (!entry->valid) | |
1523 | goto loadpurge; | |
1524 | ||
1525 | /* Write port member tags */ | |
a935c052 VD |
1526 | err = mv88e6xxx_vtu_data_write(chip, entry); |
1527 | if (err) | |
1528 | return err; | |
7dad08d7 | 1529 | |
fad09c73 | 1530 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { |
7dad08d7 | 1531 | reg = entry->sid & GLOBAL_VTU_SID_MASK; |
a935c052 VD |
1532 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg); |
1533 | if (err) | |
1534 | return err; | |
b426e5f7 | 1535 | } |
7dad08d7 | 1536 | |
6dc10bbc | 1537 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) { |
7dad08d7 | 1538 | reg = entry->fid & GLOBAL_VTU_FID_MASK; |
a935c052 VD |
1539 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg); |
1540 | if (err) | |
1541 | return err; | |
fad09c73 | 1542 | } else if (mv88e6xxx_num_databases(chip) == 256) { |
11ea809f VD |
1543 | /* VTU DBNum[7:4] are located in VTU Operation 11:8, and |
1544 | * VTU DBNum[3:0] are located in VTU Operation 3:0 | |
1545 | */ | |
1546 | op |= (entry->fid & 0xf0) << 8; | |
1547 | op |= entry->fid & 0xf; | |
7dad08d7 VD |
1548 | } |
1549 | ||
1550 | reg = GLOBAL_VTU_VID_VALID; | |
1551 | loadpurge: | |
1552 | reg |= entry->vid & GLOBAL_VTU_VID_MASK; | |
a935c052 VD |
1553 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg); |
1554 | if (err) | |
1555 | return err; | |
7dad08d7 | 1556 | |
fad09c73 | 1557 | return _mv88e6xxx_vtu_cmd(chip, op); |
7dad08d7 VD |
1558 | } |
1559 | ||
fad09c73 | 1560 | static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid, |
b4e47c0f | 1561 | struct mv88e6xxx_vtu_entry *entry) |
0d3b33e6 | 1562 | { |
b4e47c0f | 1563 | struct mv88e6xxx_vtu_entry next = { 0 }; |
a935c052 VD |
1564 | u16 val; |
1565 | int err; | |
0d3b33e6 | 1566 | |
a935c052 VD |
1567 | err = _mv88e6xxx_vtu_wait(chip); |
1568 | if (err) | |
1569 | return err; | |
0d3b33e6 | 1570 | |
a935c052 VD |
1571 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, |
1572 | sid & GLOBAL_VTU_SID_MASK); | |
1573 | if (err) | |
1574 | return err; | |
0d3b33e6 | 1575 | |
a935c052 VD |
1576 | err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT); |
1577 | if (err) | |
1578 | return err; | |
0d3b33e6 | 1579 | |
a935c052 VD |
1580 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val); |
1581 | if (err) | |
1582 | return err; | |
0d3b33e6 | 1583 | |
a935c052 | 1584 | next.sid = val & GLOBAL_VTU_SID_MASK; |
0d3b33e6 | 1585 | |
a935c052 VD |
1586 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val); |
1587 | if (err) | |
1588 | return err; | |
0d3b33e6 | 1589 | |
a935c052 | 1590 | next.valid = !!(val & GLOBAL_VTU_VID_VALID); |
0d3b33e6 VD |
1591 | |
1592 | if (next.valid) { | |
a935c052 VD |
1593 | err = mv88e6xxx_stu_data_read(chip, &next); |
1594 | if (err) | |
1595 | return err; | |
0d3b33e6 VD |
1596 | } |
1597 | ||
1598 | *entry = next; | |
1599 | return 0; | |
1600 | } | |
1601 | ||
fad09c73 | 1602 | static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1603 | struct mv88e6xxx_vtu_entry *entry) |
0d3b33e6 VD |
1604 | { |
1605 | u16 reg = 0; | |
a935c052 | 1606 | int err; |
0d3b33e6 | 1607 | |
a935c052 VD |
1608 | err = _mv88e6xxx_vtu_wait(chip); |
1609 | if (err) | |
1610 | return err; | |
0d3b33e6 VD |
1611 | |
1612 | if (!entry->valid) | |
1613 | goto loadpurge; | |
1614 | ||
1615 | /* Write port states */ | |
a935c052 VD |
1616 | err = mv88e6xxx_stu_data_write(chip, entry); |
1617 | if (err) | |
1618 | return err; | |
0d3b33e6 VD |
1619 | |
1620 | reg = GLOBAL_VTU_VID_VALID; | |
1621 | loadpurge: | |
a935c052 VD |
1622 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg); |
1623 | if (err) | |
1624 | return err; | |
0d3b33e6 VD |
1625 | |
1626 | reg = entry->sid & GLOBAL_VTU_SID_MASK; | |
a935c052 VD |
1627 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg); |
1628 | if (err) | |
1629 | return err; | |
0d3b33e6 | 1630 | |
fad09c73 | 1631 | return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE); |
0d3b33e6 VD |
1632 | } |
1633 | ||
fad09c73 | 1634 | static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid) |
3285f9e8 VD |
1635 | { |
1636 | DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); | |
b4e47c0f | 1637 | struct mv88e6xxx_vtu_entry vlan; |
2db9ce1f | 1638 | int i, err; |
3285f9e8 VD |
1639 | |
1640 | bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); | |
1641 | ||
2db9ce1f | 1642 | /* Set every FID bit used by the (un)bridged ports */ |
370b4ffb | 1643 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
b4e48c50 | 1644 | err = mv88e6xxx_port_get_fid(chip, i, fid); |
2db9ce1f VD |
1645 | if (err) |
1646 | return err; | |
1647 | ||
1648 | set_bit(*fid, fid_bitmap); | |
1649 | } | |
1650 | ||
3285f9e8 | 1651 | /* Set every FID bit used by the VLAN entries */ |
fad09c73 | 1652 | err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); |
3285f9e8 VD |
1653 | if (err) |
1654 | return err; | |
1655 | ||
1656 | do { | |
fad09c73 | 1657 | err = _mv88e6xxx_vtu_getnext(chip, &vlan); |
3285f9e8 VD |
1658 | if (err) |
1659 | return err; | |
1660 | ||
1661 | if (!vlan.valid) | |
1662 | break; | |
1663 | ||
1664 | set_bit(vlan.fid, fid_bitmap); | |
1665 | } while (vlan.vid < GLOBAL_VTU_VID_MASK); | |
1666 | ||
1667 | /* The reset value 0x000 is used to indicate that multiple address | |
1668 | * databases are not needed. Return the next positive available. | |
1669 | */ | |
1670 | *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); | |
fad09c73 | 1671 | if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) |
3285f9e8 VD |
1672 | return -ENOSPC; |
1673 | ||
1674 | /* Clear the database */ | |
fad09c73 | 1675 | return _mv88e6xxx_atu_flush(chip, *fid, true); |
3285f9e8 VD |
1676 | } |
1677 | ||
fad09c73 | 1678 | static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid, |
b4e47c0f | 1679 | struct mv88e6xxx_vtu_entry *entry) |
0d3b33e6 | 1680 | { |
fad09c73 | 1681 | struct dsa_switch *ds = chip->ds; |
b4e47c0f | 1682 | struct mv88e6xxx_vtu_entry vlan = { |
0d3b33e6 VD |
1683 | .valid = true, |
1684 | .vid = vid, | |
1685 | }; | |
3285f9e8 VD |
1686 | int i, err; |
1687 | ||
fad09c73 | 1688 | err = _mv88e6xxx_fid_new(chip, &vlan.fid); |
3285f9e8 VD |
1689 | if (err) |
1690 | return err; | |
0d3b33e6 | 1691 | |
3d131f07 | 1692 | /* exclude all ports except the CPU and DSA ports */ |
370b4ffb | 1693 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) |
3d131f07 VD |
1694 | vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i) |
1695 | ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED | |
1696 | : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; | |
0d3b33e6 | 1697 | |
fad09c73 VD |
1698 | if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) || |
1699 | mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) { | |
b4e47c0f | 1700 | struct mv88e6xxx_vtu_entry vstp; |
0d3b33e6 VD |
1701 | |
1702 | /* Adding a VTU entry requires a valid STU entry. As VSTP is not | |
1703 | * implemented, only one STU entry is needed to cover all VTU | |
1704 | * entries. Thus, validate the SID 0. | |
1705 | */ | |
1706 | vlan.sid = 0; | |
fad09c73 | 1707 | err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp); |
0d3b33e6 VD |
1708 | if (err) |
1709 | return err; | |
1710 | ||
1711 | if (vstp.sid != vlan.sid || !vstp.valid) { | |
1712 | memset(&vstp, 0, sizeof(vstp)); | |
1713 | vstp.valid = true; | |
1714 | vstp.sid = vlan.sid; | |
1715 | ||
fad09c73 | 1716 | err = _mv88e6xxx_stu_loadpurge(chip, &vstp); |
0d3b33e6 VD |
1717 | if (err) |
1718 | return err; | |
1719 | } | |
0d3b33e6 VD |
1720 | } |
1721 | ||
1722 | *entry = vlan; | |
1723 | return 0; | |
1724 | } | |
1725 | ||
fad09c73 | 1726 | static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, |
b4e47c0f | 1727 | struct mv88e6xxx_vtu_entry *entry, bool creat) |
2fb5ef09 VD |
1728 | { |
1729 | int err; | |
1730 | ||
1731 | if (!vid) | |
1732 | return -EINVAL; | |
1733 | ||
fad09c73 | 1734 | err = _mv88e6xxx_vtu_vid_write(chip, vid - 1); |
2fb5ef09 VD |
1735 | if (err) |
1736 | return err; | |
1737 | ||
fad09c73 | 1738 | err = _mv88e6xxx_vtu_getnext(chip, entry); |
2fb5ef09 VD |
1739 | if (err) |
1740 | return err; | |
1741 | ||
1742 | if (entry->vid != vid || !entry->valid) { | |
1743 | if (!creat) | |
1744 | return -EOPNOTSUPP; | |
1745 | /* -ENOENT would've been more appropriate, but switchdev expects | |
1746 | * -EOPNOTSUPP to inform bridge about an eventual software VLAN. | |
1747 | */ | |
1748 | ||
fad09c73 | 1749 | err = _mv88e6xxx_vtu_new(chip, vid, entry); |
2fb5ef09 VD |
1750 | } |
1751 | ||
1752 | return err; | |
1753 | } | |
1754 | ||
da9c359e VD |
1755 | static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, |
1756 | u16 vid_begin, u16 vid_end) | |
1757 | { | |
04bed143 | 1758 | struct mv88e6xxx_chip *chip = ds->priv; |
b4e47c0f | 1759 | struct mv88e6xxx_vtu_entry vlan; |
da9c359e VD |
1760 | int i, err; |
1761 | ||
1762 | if (!vid_begin) | |
1763 | return -EOPNOTSUPP; | |
1764 | ||
fad09c73 | 1765 | mutex_lock(&chip->reg_lock); |
da9c359e | 1766 | |
fad09c73 | 1767 | err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1); |
da9c359e VD |
1768 | if (err) |
1769 | goto unlock; | |
1770 | ||
1771 | do { | |
fad09c73 | 1772 | err = _mv88e6xxx_vtu_getnext(chip, &vlan); |
da9c359e VD |
1773 | if (err) |
1774 | goto unlock; | |
1775 | ||
1776 | if (!vlan.valid) | |
1777 | break; | |
1778 | ||
1779 | if (vlan.vid > vid_end) | |
1780 | break; | |
1781 | ||
370b4ffb | 1782 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
da9c359e VD |
1783 | if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) |
1784 | continue; | |
1785 | ||
1786 | if (vlan.data[i] == | |
1787 | GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) | |
1788 | continue; | |
1789 | ||
fad09c73 VD |
1790 | if (chip->ports[i].bridge_dev == |
1791 | chip->ports[port].bridge_dev) | |
da9c359e VD |
1792 | break; /* same bridge, check next VLAN */ |
1793 | ||
c8b09808 | 1794 | netdev_warn(ds->ports[port].netdev, |
da9c359e VD |
1795 | "hardware VLAN %d already used by %s\n", |
1796 | vlan.vid, | |
fad09c73 | 1797 | netdev_name(chip->ports[i].bridge_dev)); |
da9c359e VD |
1798 | err = -EOPNOTSUPP; |
1799 | goto unlock; | |
1800 | } | |
1801 | } while (vlan.vid < vid_end); | |
1802 | ||
1803 | unlock: | |
fad09c73 | 1804 | mutex_unlock(&chip->reg_lock); |
da9c359e VD |
1805 | |
1806 | return err; | |
1807 | } | |
1808 | ||
f81ec90f VD |
1809 | static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, |
1810 | bool vlan_filtering) | |
214cdb99 | 1811 | { |
04bed143 | 1812 | struct mv88e6xxx_chip *chip = ds->priv; |
385a0995 | 1813 | u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE : |
214cdb99 | 1814 | PORT_CONTROL_2_8021Q_DISABLED; |
0e7b9925 | 1815 | int err; |
214cdb99 | 1816 | |
fad09c73 | 1817 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
54d77b5b VD |
1818 | return -EOPNOTSUPP; |
1819 | ||
fad09c73 | 1820 | mutex_lock(&chip->reg_lock); |
385a0995 | 1821 | err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); |
fad09c73 | 1822 | mutex_unlock(&chip->reg_lock); |
214cdb99 | 1823 | |
0e7b9925 | 1824 | return err; |
214cdb99 VD |
1825 | } |
1826 | ||
57d32310 VD |
1827 | static int |
1828 | mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, | |
1829 | const struct switchdev_obj_port_vlan *vlan, | |
1830 | struct switchdev_trans *trans) | |
76e398a6 | 1831 | { |
04bed143 | 1832 | struct mv88e6xxx_chip *chip = ds->priv; |
da9c359e VD |
1833 | int err; |
1834 | ||
fad09c73 | 1835 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
54d77b5b VD |
1836 | return -EOPNOTSUPP; |
1837 | ||
da9c359e VD |
1838 | /* If the requested port doesn't belong to the same bridge as the VLAN |
1839 | * members, do not support it (yet) and fallback to software VLAN. | |
1840 | */ | |
1841 | err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, | |
1842 | vlan->vid_end); | |
1843 | if (err) | |
1844 | return err; | |
1845 | ||
76e398a6 VD |
1846 | /* We don't need any dynamic resource from the kernel (yet), |
1847 | * so skip the prepare phase. | |
1848 | */ | |
1849 | return 0; | |
1850 | } | |
1851 | ||
fad09c73 | 1852 | static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, |
158bc065 | 1853 | u16 vid, bool untagged) |
0d3b33e6 | 1854 | { |
b4e47c0f | 1855 | struct mv88e6xxx_vtu_entry vlan; |
0d3b33e6 VD |
1856 | int err; |
1857 | ||
fad09c73 | 1858 | err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true); |
0d3b33e6 | 1859 | if (err) |
76e398a6 | 1860 | return err; |
0d3b33e6 | 1861 | |
0d3b33e6 VD |
1862 | vlan.data[port] = untagged ? |
1863 | GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED : | |
1864 | GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED; | |
1865 | ||
fad09c73 | 1866 | return _mv88e6xxx_vtu_loadpurge(chip, &vlan); |
76e398a6 VD |
1867 | } |
1868 | ||
f81ec90f VD |
1869 | static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, |
1870 | const struct switchdev_obj_port_vlan *vlan, | |
1871 | struct switchdev_trans *trans) | |
76e398a6 | 1872 | { |
04bed143 | 1873 | struct mv88e6xxx_chip *chip = ds->priv; |
76e398a6 VD |
1874 | bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; |
1875 | bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; | |
1876 | u16 vid; | |
76e398a6 | 1877 | |
fad09c73 | 1878 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
54d77b5b VD |
1879 | return; |
1880 | ||
fad09c73 | 1881 | mutex_lock(&chip->reg_lock); |
76e398a6 | 1882 | |
4d5770b3 | 1883 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) |
fad09c73 | 1884 | if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged)) |
c8b09808 AL |
1885 | netdev_err(ds->ports[port].netdev, |
1886 | "failed to add VLAN %d%c\n", | |
4d5770b3 | 1887 | vid, untagged ? 'u' : 't'); |
76e398a6 | 1888 | |
77064f37 | 1889 | if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) |
c8b09808 | 1890 | netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n", |
4d5770b3 | 1891 | vlan->vid_end); |
0d3b33e6 | 1892 | |
fad09c73 | 1893 | mutex_unlock(&chip->reg_lock); |
0d3b33e6 VD |
1894 | } |
1895 | ||
fad09c73 | 1896 | static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, |
158bc065 | 1897 | int port, u16 vid) |
7dad08d7 | 1898 | { |
fad09c73 | 1899 | struct dsa_switch *ds = chip->ds; |
b4e47c0f | 1900 | struct mv88e6xxx_vtu_entry vlan; |
7dad08d7 VD |
1901 | int i, err; |
1902 | ||
fad09c73 | 1903 | err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); |
7dad08d7 | 1904 | if (err) |
76e398a6 | 1905 | return err; |
7dad08d7 | 1906 | |
2fb5ef09 VD |
1907 | /* Tell switchdev if this VLAN is handled in software */ |
1908 | if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) | |
3c06f08b | 1909 | return -EOPNOTSUPP; |
7dad08d7 VD |
1910 | |
1911 | vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; | |
1912 | ||
1913 | /* keep the VLAN unless all ports are excluded */ | |
f02bdffc | 1914 | vlan.valid = false; |
370b4ffb | 1915 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
3d131f07 | 1916 | if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) |
7dad08d7 VD |
1917 | continue; |
1918 | ||
1919 | if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) { | |
f02bdffc | 1920 | vlan.valid = true; |
7dad08d7 VD |
1921 | break; |
1922 | } | |
1923 | } | |
1924 | ||
fad09c73 | 1925 | err = _mv88e6xxx_vtu_loadpurge(chip, &vlan); |
76e398a6 VD |
1926 | if (err) |
1927 | return err; | |
1928 | ||
fad09c73 | 1929 | return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false); |
76e398a6 VD |
1930 | } |
1931 | ||
f81ec90f VD |
1932 | static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, |
1933 | const struct switchdev_obj_port_vlan *vlan) | |
76e398a6 | 1934 | { |
04bed143 | 1935 | struct mv88e6xxx_chip *chip = ds->priv; |
76e398a6 VD |
1936 | u16 pvid, vid; |
1937 | int err = 0; | |
1938 | ||
fad09c73 | 1939 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
54d77b5b VD |
1940 | return -EOPNOTSUPP; |
1941 | ||
fad09c73 | 1942 | mutex_lock(&chip->reg_lock); |
76e398a6 | 1943 | |
77064f37 | 1944 | err = mv88e6xxx_port_get_pvid(chip, port, &pvid); |
7dad08d7 VD |
1945 | if (err) |
1946 | goto unlock; | |
1947 | ||
76e398a6 | 1948 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { |
fad09c73 | 1949 | err = _mv88e6xxx_port_vlan_del(chip, port, vid); |
76e398a6 VD |
1950 | if (err) |
1951 | goto unlock; | |
1952 | ||
1953 | if (vid == pvid) { | |
77064f37 | 1954 | err = mv88e6xxx_port_set_pvid(chip, port, 0); |
76e398a6 VD |
1955 | if (err) |
1956 | goto unlock; | |
1957 | } | |
1958 | } | |
1959 | ||
7dad08d7 | 1960 | unlock: |
fad09c73 | 1961 | mutex_unlock(&chip->reg_lock); |
7dad08d7 VD |
1962 | |
1963 | return err; | |
1964 | } | |
1965 | ||
fad09c73 | 1966 | static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip, |
c5723ac5 | 1967 | const unsigned char *addr) |
defb05b9 | 1968 | { |
a935c052 | 1969 | int i, err; |
defb05b9 GR |
1970 | |
1971 | for (i = 0; i < 3; i++) { | |
a935c052 VD |
1972 | err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i, |
1973 | (addr[i * 2] << 8) | addr[i * 2 + 1]); | |
1974 | if (err) | |
1975 | return err; | |
defb05b9 GR |
1976 | } |
1977 | ||
1978 | return 0; | |
1979 | } | |
1980 | ||
fad09c73 | 1981 | static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip, |
158bc065 | 1982 | unsigned char *addr) |
defb05b9 | 1983 | { |
a935c052 VD |
1984 | u16 val; |
1985 | int i, err; | |
defb05b9 GR |
1986 | |
1987 | for (i = 0; i < 3; i++) { | |
a935c052 VD |
1988 | err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val); |
1989 | if (err) | |
1990 | return err; | |
1991 | ||
1992 | addr[i * 2] = val >> 8; | |
1993 | addr[i * 2 + 1] = val & 0xff; | |
defb05b9 GR |
1994 | } |
1995 | ||
1996 | return 0; | |
1997 | } | |
1998 | ||
fad09c73 | 1999 | static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip, |
fd231c82 | 2000 | struct mv88e6xxx_atu_entry *entry) |
defb05b9 | 2001 | { |
6630e236 VD |
2002 | int ret; |
2003 | ||
fad09c73 | 2004 | ret = _mv88e6xxx_atu_wait(chip); |
defb05b9 GR |
2005 | if (ret < 0) |
2006 | return ret; | |
2007 | ||
fad09c73 | 2008 | ret = _mv88e6xxx_atu_mac_write(chip, entry->mac); |
defb05b9 GR |
2009 | if (ret < 0) |
2010 | return ret; | |
2011 | ||
fad09c73 | 2012 | ret = _mv88e6xxx_atu_data_write(chip, entry); |
fd231c82 | 2013 | if (ret < 0) |
87820510 VD |
2014 | return ret; |
2015 | ||
fad09c73 | 2016 | return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB); |
fd231c82 | 2017 | } |
87820510 | 2018 | |
88472939 VD |
2019 | static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, |
2020 | struct mv88e6xxx_atu_entry *entry); | |
2021 | ||
2022 | static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid, | |
2023 | const u8 *addr, struct mv88e6xxx_atu_entry *entry) | |
2024 | { | |
2025 | struct mv88e6xxx_atu_entry next; | |
2026 | int err; | |
2027 | ||
2028 | eth_broadcast_addr(next.mac); | |
2029 | ||
2030 | err = _mv88e6xxx_atu_mac_write(chip, next.mac); | |
2031 | if (err) | |
2032 | return err; | |
2033 | ||
2034 | do { | |
2035 | err = _mv88e6xxx_atu_getnext(chip, fid, &next); | |
2036 | if (err) | |
2037 | return err; | |
2038 | ||
2039 | if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED) | |
2040 | break; | |
2041 | ||
2042 | if (ether_addr_equal(next.mac, addr)) { | |
2043 | *entry = next; | |
2044 | return 0; | |
2045 | } | |
2046 | } while (!is_broadcast_ether_addr(next.mac)); | |
2047 | ||
2048 | memset(entry, 0, sizeof(*entry)); | |
2049 | entry->fid = fid; | |
2050 | ether_addr_copy(entry->mac, addr); | |
2051 | ||
2052 | return 0; | |
2053 | } | |
2054 | ||
83dabd1f VD |
2055 | static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, |
2056 | const unsigned char *addr, u16 vid, | |
2057 | u8 state) | |
fd231c82 | 2058 | { |
b4e47c0f | 2059 | struct mv88e6xxx_vtu_entry vlan; |
88472939 | 2060 | struct mv88e6xxx_atu_entry entry; |
3285f9e8 VD |
2061 | int err; |
2062 | ||
2db9ce1f VD |
2063 | /* Null VLAN ID corresponds to the port private database */ |
2064 | if (vid == 0) | |
b4e48c50 | 2065 | err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); |
2db9ce1f | 2066 | else |
fad09c73 | 2067 | err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); |
3285f9e8 VD |
2068 | if (err) |
2069 | return err; | |
fd231c82 | 2070 | |
88472939 VD |
2071 | err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry); |
2072 | if (err) | |
2073 | return err; | |
2074 | ||
2075 | /* Purge the ATU entry only if no port is using it anymore */ | |
2076 | if (state == GLOBAL_ATU_DATA_STATE_UNUSED) { | |
2077 | entry.portv_trunkid &= ~BIT(port); | |
2078 | if (!entry.portv_trunkid) | |
2079 | entry.state = GLOBAL_ATU_DATA_STATE_UNUSED; | |
2080 | } else { | |
2081 | entry.portv_trunkid |= BIT(port); | |
2082 | entry.state = state; | |
fd231c82 VD |
2083 | } |
2084 | ||
fad09c73 | 2085 | return _mv88e6xxx_atu_load(chip, &entry); |
87820510 VD |
2086 | } |
2087 | ||
f81ec90f VD |
2088 | static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, |
2089 | const struct switchdev_obj_port_fdb *fdb, | |
2090 | struct switchdev_trans *trans) | |
146a3206 VD |
2091 | { |
2092 | /* We don't need any dynamic resource from the kernel (yet), | |
2093 | * so skip the prepare phase. | |
2094 | */ | |
2095 | return 0; | |
2096 | } | |
2097 | ||
f81ec90f VD |
2098 | static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, |
2099 | const struct switchdev_obj_port_fdb *fdb, | |
2100 | struct switchdev_trans *trans) | |
87820510 | 2101 | { |
04bed143 | 2102 | struct mv88e6xxx_chip *chip = ds->priv; |
87820510 | 2103 | |
fad09c73 | 2104 | mutex_lock(&chip->reg_lock); |
83dabd1f VD |
2105 | if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, |
2106 | GLOBAL_ATU_DATA_STATE_UC_STATIC)) | |
2107 | netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n"); | |
fad09c73 | 2108 | mutex_unlock(&chip->reg_lock); |
87820510 VD |
2109 | } |
2110 | ||
f81ec90f VD |
2111 | static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, |
2112 | const struct switchdev_obj_port_fdb *fdb) | |
87820510 | 2113 | { |
04bed143 | 2114 | struct mv88e6xxx_chip *chip = ds->priv; |
83dabd1f | 2115 | int err; |
87820510 | 2116 | |
fad09c73 | 2117 | mutex_lock(&chip->reg_lock); |
83dabd1f VD |
2118 | err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, |
2119 | GLOBAL_ATU_DATA_STATE_UNUSED); | |
fad09c73 | 2120 | mutex_unlock(&chip->reg_lock); |
87820510 | 2121 | |
83dabd1f | 2122 | return err; |
87820510 VD |
2123 | } |
2124 | ||
fad09c73 | 2125 | static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, |
1d194046 | 2126 | struct mv88e6xxx_atu_entry *entry) |
6630e236 | 2127 | { |
1d194046 | 2128 | struct mv88e6xxx_atu_entry next = { 0 }; |
a935c052 VD |
2129 | u16 val; |
2130 | int err; | |
1d194046 VD |
2131 | |
2132 | next.fid = fid; | |
defb05b9 | 2133 | |
a935c052 VD |
2134 | err = _mv88e6xxx_atu_wait(chip); |
2135 | if (err) | |
2136 | return err; | |
6630e236 | 2137 | |
a935c052 VD |
2138 | err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB); |
2139 | if (err) | |
2140 | return err; | |
6630e236 | 2141 | |
a935c052 VD |
2142 | err = _mv88e6xxx_atu_mac_read(chip, next.mac); |
2143 | if (err) | |
2144 | return err; | |
6630e236 | 2145 | |
a935c052 VD |
2146 | err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val); |
2147 | if (err) | |
2148 | return err; | |
6630e236 | 2149 | |
a935c052 | 2150 | next.state = val & GLOBAL_ATU_DATA_STATE_MASK; |
1d194046 VD |
2151 | if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) { |
2152 | unsigned int mask, shift; | |
2153 | ||
a935c052 | 2154 | if (val & GLOBAL_ATU_DATA_TRUNK) { |
1d194046 VD |
2155 | next.trunk = true; |
2156 | mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; | |
2157 | shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; | |
2158 | } else { | |
2159 | next.trunk = false; | |
2160 | mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; | |
2161 | shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; | |
2162 | } | |
2163 | ||
a935c052 | 2164 | next.portv_trunkid = (val & mask) >> shift; |
1d194046 | 2165 | } |
cdf09697 | 2166 | |
1d194046 | 2167 | *entry = next; |
cdf09697 DM |
2168 | return 0; |
2169 | } | |
2170 | ||
83dabd1f VD |
2171 | static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, |
2172 | u16 fid, u16 vid, int port, | |
2173 | struct switchdev_obj *obj, | |
2174 | int (*cb)(struct switchdev_obj *obj)) | |
74b6ba0d VD |
2175 | { |
2176 | struct mv88e6xxx_atu_entry addr = { | |
2177 | .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, | |
2178 | }; | |
2179 | int err; | |
2180 | ||
fad09c73 | 2181 | err = _mv88e6xxx_atu_mac_write(chip, addr.mac); |
74b6ba0d VD |
2182 | if (err) |
2183 | return err; | |
2184 | ||
2185 | do { | |
fad09c73 | 2186 | err = _mv88e6xxx_atu_getnext(chip, fid, &addr); |
74b6ba0d | 2187 | if (err) |
83dabd1f | 2188 | return err; |
74b6ba0d VD |
2189 | |
2190 | if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED) | |
2191 | break; | |
2192 | ||
83dabd1f VD |
2193 | if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0) |
2194 | continue; | |
2195 | ||
2196 | if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) { | |
2197 | struct switchdev_obj_port_fdb *fdb; | |
74b6ba0d | 2198 | |
83dabd1f VD |
2199 | if (!is_unicast_ether_addr(addr.mac)) |
2200 | continue; | |
2201 | ||
2202 | fdb = SWITCHDEV_OBJ_PORT_FDB(obj); | |
74b6ba0d VD |
2203 | fdb->vid = vid; |
2204 | ether_addr_copy(fdb->addr, addr.mac); | |
83dabd1f VD |
2205 | if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC) |
2206 | fdb->ndm_state = NUD_NOARP; | |
2207 | else | |
2208 | fdb->ndm_state = NUD_REACHABLE; | |
7df8fbdd VD |
2209 | } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) { |
2210 | struct switchdev_obj_port_mdb *mdb; | |
2211 | ||
2212 | if (!is_multicast_ether_addr(addr.mac)) | |
2213 | continue; | |
2214 | ||
2215 | mdb = SWITCHDEV_OBJ_PORT_MDB(obj); | |
2216 | mdb->vid = vid; | |
2217 | ether_addr_copy(mdb->addr, addr.mac); | |
83dabd1f VD |
2218 | } else { |
2219 | return -EOPNOTSUPP; | |
74b6ba0d | 2220 | } |
83dabd1f VD |
2221 | |
2222 | err = cb(obj); | |
2223 | if (err) | |
2224 | return err; | |
74b6ba0d VD |
2225 | } while (!is_broadcast_ether_addr(addr.mac)); |
2226 | ||
2227 | return err; | |
2228 | } | |
2229 | ||
83dabd1f VD |
2230 | static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, |
2231 | struct switchdev_obj *obj, | |
2232 | int (*cb)(struct switchdev_obj *obj)) | |
f33475bd | 2233 | { |
b4e47c0f | 2234 | struct mv88e6xxx_vtu_entry vlan = { |
f33475bd VD |
2235 | .vid = GLOBAL_VTU_VID_MASK, /* all ones */ |
2236 | }; | |
2db9ce1f | 2237 | u16 fid; |
f33475bd VD |
2238 | int err; |
2239 | ||
2db9ce1f | 2240 | /* Dump port's default Filtering Information Database (VLAN ID 0) */ |
b4e48c50 | 2241 | err = mv88e6xxx_port_get_fid(chip, port, &fid); |
2db9ce1f | 2242 | if (err) |
83dabd1f | 2243 | return err; |
2db9ce1f | 2244 | |
83dabd1f | 2245 | err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb); |
2db9ce1f | 2246 | if (err) |
83dabd1f | 2247 | return err; |
2db9ce1f | 2248 | |
74b6ba0d | 2249 | /* Dump VLANs' Filtering Information Databases */ |
fad09c73 | 2250 | err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid); |
f33475bd | 2251 | if (err) |
83dabd1f | 2252 | return err; |
f33475bd VD |
2253 | |
2254 | do { | |
fad09c73 | 2255 | err = _mv88e6xxx_vtu_getnext(chip, &vlan); |
f33475bd | 2256 | if (err) |
83dabd1f | 2257 | return err; |
f33475bd VD |
2258 | |
2259 | if (!vlan.valid) | |
2260 | break; | |
2261 | ||
83dabd1f VD |
2262 | err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, |
2263 | obj, cb); | |
f33475bd | 2264 | if (err) |
83dabd1f | 2265 | return err; |
f33475bd VD |
2266 | } while (vlan.vid < GLOBAL_VTU_VID_MASK); |
2267 | ||
83dabd1f VD |
2268 | return err; |
2269 | } | |
2270 | ||
2271 | static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, | |
2272 | struct switchdev_obj_port_fdb *fdb, | |
2273 | int (*cb)(struct switchdev_obj *obj)) | |
2274 | { | |
04bed143 | 2275 | struct mv88e6xxx_chip *chip = ds->priv; |
83dabd1f VD |
2276 | int err; |
2277 | ||
2278 | mutex_lock(&chip->reg_lock); | |
2279 | err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb); | |
fad09c73 | 2280 | mutex_unlock(&chip->reg_lock); |
f33475bd VD |
2281 | |
2282 | return err; | |
2283 | } | |
2284 | ||
f81ec90f VD |
2285 | static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, |
2286 | struct net_device *bridge) | |
e79a8bcb | 2287 | { |
04bed143 | 2288 | struct mv88e6xxx_chip *chip = ds->priv; |
1d9619d5 | 2289 | int i, err = 0; |
466dfa07 | 2290 | |
fad09c73 | 2291 | mutex_lock(&chip->reg_lock); |
466dfa07 | 2292 | |
b7666efe | 2293 | /* Assign the bridge and remap each port's VLANTable */ |
fad09c73 | 2294 | chip->ports[port].bridge_dev = bridge; |
b7666efe | 2295 | |
370b4ffb | 2296 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
fad09c73 VD |
2297 | if (chip->ports[i].bridge_dev == bridge) { |
2298 | err = _mv88e6xxx_port_based_vlan_map(chip, i); | |
b7666efe VD |
2299 | if (err) |
2300 | break; | |
2301 | } | |
2302 | } | |
2303 | ||
fad09c73 | 2304 | mutex_unlock(&chip->reg_lock); |
a6692754 | 2305 | |
466dfa07 | 2306 | return err; |
e79a8bcb VD |
2307 | } |
2308 | ||
f81ec90f | 2309 | static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port) |
66d9cd0f | 2310 | { |
04bed143 | 2311 | struct mv88e6xxx_chip *chip = ds->priv; |
fad09c73 | 2312 | struct net_device *bridge = chip->ports[port].bridge_dev; |
16bfa702 | 2313 | int i; |
466dfa07 | 2314 | |
fad09c73 | 2315 | mutex_lock(&chip->reg_lock); |
466dfa07 | 2316 | |
b7666efe | 2317 | /* Unassign the bridge and remap each port's VLANTable */ |
fad09c73 | 2318 | chip->ports[port].bridge_dev = NULL; |
b7666efe | 2319 | |
370b4ffb | 2320 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) |
fad09c73 VD |
2321 | if (i == port || chip->ports[i].bridge_dev == bridge) |
2322 | if (_mv88e6xxx_port_based_vlan_map(chip, i)) | |
c8b09808 AL |
2323 | netdev_warn(ds->ports[i].netdev, |
2324 | "failed to remap\n"); | |
b7666efe | 2325 | |
fad09c73 | 2326 | mutex_unlock(&chip->reg_lock); |
66d9cd0f VD |
2327 | } |
2328 | ||
fad09c73 | 2329 | static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) |
552238b5 | 2330 | { |
fad09c73 | 2331 | bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE); |
552238b5 | 2332 | u16 is_reset = (ppu_active ? 0x8800 : 0xc800); |
fad09c73 | 2333 | struct gpio_desc *gpiod = chip->reset; |
552238b5 | 2334 | unsigned long timeout; |
0e7b9925 | 2335 | u16 reg; |
a935c052 | 2336 | int err; |
552238b5 VD |
2337 | int i; |
2338 | ||
2339 | /* Set all ports to the disabled state. */ | |
370b4ffb | 2340 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { |
e28def33 VD |
2341 | err = mv88e6xxx_port_set_state(chip, i, |
2342 | PORT_CONTROL_STATE_DISABLED); | |
0e7b9925 AL |
2343 | if (err) |
2344 | return err; | |
552238b5 VD |
2345 | } |
2346 | ||
2347 | /* Wait for transmit queues to drain. */ | |
2348 | usleep_range(2000, 4000); | |
2349 | ||
2350 | /* If there is a gpio connected to the reset pin, toggle it */ | |
2351 | if (gpiod) { | |
2352 | gpiod_set_value_cansleep(gpiod, 1); | |
2353 | usleep_range(10000, 20000); | |
2354 | gpiod_set_value_cansleep(gpiod, 0); | |
2355 | usleep_range(10000, 20000); | |
2356 | } | |
2357 | ||
2358 | /* Reset the switch. Keep the PPU active if requested. The PPU | |
2359 | * needs to be active to support indirect phy register access | |
2360 | * through global registers 0x18 and 0x19. | |
2361 | */ | |
2362 | if (ppu_active) | |
a935c052 | 2363 | err = mv88e6xxx_g1_write(chip, 0x04, 0xc000); |
552238b5 | 2364 | else |
a935c052 | 2365 | err = mv88e6xxx_g1_write(chip, 0x04, 0xc400); |
0e7b9925 AL |
2366 | if (err) |
2367 | return err; | |
552238b5 VD |
2368 | |
2369 | /* Wait up to one second for reset to complete. */ | |
2370 | timeout = jiffies + 1 * HZ; | |
2371 | while (time_before(jiffies, timeout)) { | |
a935c052 VD |
2372 | err = mv88e6xxx_g1_read(chip, 0x00, ®); |
2373 | if (err) | |
2374 | return err; | |
552238b5 | 2375 | |
a935c052 | 2376 | if ((reg & is_reset) == is_reset) |
552238b5 VD |
2377 | break; |
2378 | usleep_range(1000, 2000); | |
2379 | } | |
2380 | if (time_after(jiffies, timeout)) | |
0e7b9925 | 2381 | err = -ETIMEDOUT; |
552238b5 | 2382 | else |
0e7b9925 | 2383 | err = 0; |
552238b5 | 2384 | |
0e7b9925 | 2385 | return err; |
552238b5 VD |
2386 | } |
2387 | ||
09cb7dfd | 2388 | static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip) |
13a7ebb3 | 2389 | { |
09cb7dfd VD |
2390 | u16 val; |
2391 | int err; | |
13a7ebb3 | 2392 | |
09cb7dfd VD |
2393 | /* Clear Power Down bit */ |
2394 | err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val); | |
2395 | if (err) | |
2396 | return err; | |
13a7ebb3 | 2397 | |
09cb7dfd VD |
2398 | if (val & BMCR_PDOWN) { |
2399 | val &= ~BMCR_PDOWN; | |
2400 | err = mv88e6xxx_serdes_write(chip, MII_BMCR, val); | |
13a7ebb3 PU |
2401 | } |
2402 | ||
09cb7dfd | 2403 | return err; |
13a7ebb3 PU |
2404 | } |
2405 | ||
fad09c73 | 2406 | static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) |
d827e88a | 2407 | { |
fad09c73 | 2408 | struct dsa_switch *ds = chip->ds; |
0e7b9925 | 2409 | int err; |
54d792f2 | 2410 | u16 reg; |
d827e88a | 2411 | |
fad09c73 VD |
2412 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
2413 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || | |
2414 | mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) || | |
2415 | mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) { | |
54d792f2 AL |
2416 | /* MAC Forcing register: don't force link, speed, |
2417 | * duplex or flow control state to any particular | |
2418 | * values on physical ports, but force the CPU port | |
2419 | * and all DSA ports to their maximum bandwidth and | |
2420 | * full duplex. | |
2421 | */ | |
0e7b9925 | 2422 | err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®); |
60045cbf | 2423 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { |
53adc9e8 | 2424 | reg &= ~PORT_PCS_CTRL_UNFORCED; |
54d792f2 AL |
2425 | reg |= PORT_PCS_CTRL_FORCE_LINK | |
2426 | PORT_PCS_CTRL_LINK_UP | | |
2427 | PORT_PCS_CTRL_DUPLEX_FULL | | |
2428 | PORT_PCS_CTRL_FORCE_DUPLEX; | |
fad09c73 | 2429 | if (mv88e6xxx_6065_family(chip)) |
54d792f2 AL |
2430 | reg |= PORT_PCS_CTRL_100; |
2431 | else | |
2432 | reg |= PORT_PCS_CTRL_1000; | |
2433 | } else { | |
2434 | reg |= PORT_PCS_CTRL_UNFORCED; | |
2435 | } | |
2436 | ||
0e7b9925 AL |
2437 | err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg); |
2438 | if (err) | |
2439 | return err; | |
54d792f2 AL |
2440 | } |
2441 | ||
2442 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, | |
2443 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN | |
2444 | * tunneling, determine priority by looking at 802.1p and IP | |
2445 | * priority fields (IP prio has precedence), and set STP state | |
2446 | * to Forwarding. | |
2447 | * | |
2448 | * If this is the CPU link, use DSA or EDSA tagging depending | |
2449 | * on which tagging mode was configured. | |
2450 | * | |
2451 | * If this is a link to another switch, use DSA tagging mode. | |
2452 | * | |
2453 | * If this is the upstream port for this switch, enable | |
2454 | * forwarding of unknown unicasts and multicasts. | |
2455 | */ | |
2456 | reg = 0; | |
fad09c73 VD |
2457 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
2458 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || | |
2459 | mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) || | |
2460 | mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip)) | |
54d792f2 AL |
2461 | reg = PORT_CONTROL_IGMP_MLD_SNOOP | |
2462 | PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | | |
2463 | PORT_CONTROL_STATE_FORWARDING; | |
2464 | if (dsa_is_cpu_port(ds, port)) { | |
2bbb33be | 2465 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) |
5377b802 | 2466 | reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA | |
c047a1f9 | 2467 | PORT_CONTROL_FORWARD_UNKNOWN_MC; |
2bbb33be AL |
2468 | else |
2469 | reg |= PORT_CONTROL_DSA_TAG; | |
f027e0cc JL |
2470 | reg |= PORT_CONTROL_EGRESS_ADD_TAG | |
2471 | PORT_CONTROL_FORWARD_UNKNOWN; | |
54d792f2 | 2472 | } |
6083ce71 | 2473 | if (dsa_is_dsa_port(ds, port)) { |
fad09c73 VD |
2474 | if (mv88e6xxx_6095_family(chip) || |
2475 | mv88e6xxx_6185_family(chip)) | |
6083ce71 | 2476 | reg |= PORT_CONTROL_DSA_TAG; |
fad09c73 VD |
2477 | if (mv88e6xxx_6352_family(chip) || |
2478 | mv88e6xxx_6351_family(chip) || | |
2479 | mv88e6xxx_6165_family(chip) || | |
2480 | mv88e6xxx_6097_family(chip) || | |
2481 | mv88e6xxx_6320_family(chip)) { | |
54d792f2 | 2482 | reg |= PORT_CONTROL_FRAME_MODE_DSA; |
6083ce71 AL |
2483 | } |
2484 | ||
54d792f2 AL |
2485 | if (port == dsa_upstream_port(ds)) |
2486 | reg |= PORT_CONTROL_FORWARD_UNKNOWN | | |
2487 | PORT_CONTROL_FORWARD_UNKNOWN_MC; | |
2488 | } | |
2489 | if (reg) { | |
0e7b9925 AL |
2490 | err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg); |
2491 | if (err) | |
2492 | return err; | |
54d792f2 AL |
2493 | } |
2494 | ||
13a7ebb3 PU |
2495 | /* If this port is connected to a SerDes, make sure the SerDes is not |
2496 | * powered down. | |
2497 | */ | |
09cb7dfd | 2498 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) { |
0e7b9925 AL |
2499 | err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®); |
2500 | if (err) | |
2501 | return err; | |
2502 | reg &= PORT_STATUS_CMODE_MASK; | |
2503 | if ((reg == PORT_STATUS_CMODE_100BASE_X) || | |
2504 | (reg == PORT_STATUS_CMODE_1000BASE_X) || | |
2505 | (reg == PORT_STATUS_CMODE_SGMII)) { | |
2506 | err = mv88e6xxx_serdes_power_on(chip); | |
2507 | if (err < 0) | |
2508 | return err; | |
13a7ebb3 PU |
2509 | } |
2510 | } | |
2511 | ||
8efdda4a | 2512 | /* Port Control 2: don't force a good FCS, set the maximum frame size to |
46fbe5e5 | 2513 | * 10240 bytes, disable 802.1q tags checking, don't discard tagged or |
8efdda4a VD |
2514 | * untagged frames on this port, do a destination address lookup on all |
2515 | * received packets as usual, disable ARP mirroring and don't send a | |
2516 | * copy of all transmitted/received frames on this port to the CPU. | |
54d792f2 AL |
2517 | */ |
2518 | reg = 0; | |
fad09c73 VD |
2519 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
2520 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || | |
2521 | mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) || | |
2522 | mv88e6xxx_6185_family(chip)) | |
54d792f2 AL |
2523 | reg = PORT_CONTROL_2_MAP_DA; |
2524 | ||
fad09c73 VD |
2525 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
2526 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip)) | |
54d792f2 AL |
2527 | reg |= PORT_CONTROL_2_JUMBO_10240; |
2528 | ||
fad09c73 | 2529 | if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) { |
54d792f2 AL |
2530 | /* Set the upstream port this port should use */ |
2531 | reg |= dsa_upstream_port(ds); | |
2532 | /* enable forwarding of unknown multicast addresses to | |
2533 | * the upstream port | |
2534 | */ | |
2535 | if (port == dsa_upstream_port(ds)) | |
2536 | reg |= PORT_CONTROL_2_FORWARD_UNKNOWN; | |
2537 | } | |
2538 | ||
46fbe5e5 | 2539 | reg |= PORT_CONTROL_2_8021Q_DISABLED; |
8efdda4a | 2540 | |
54d792f2 | 2541 | if (reg) { |
0e7b9925 AL |
2542 | err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg); |
2543 | if (err) | |
2544 | return err; | |
54d792f2 AL |
2545 | } |
2546 | ||
2547 | /* Port Association Vector: when learning source addresses | |
2548 | * of packets, add the address to the address database using | |
2549 | * a port bitmap that has only the bit for this port set and | |
2550 | * the other bits clear. | |
2551 | */ | |
4c7ea3c0 | 2552 | reg = 1 << port; |
996ecb82 VD |
2553 | /* Disable learning for CPU port */ |
2554 | if (dsa_is_cpu_port(ds, port)) | |
65fa4027 | 2555 | reg = 0; |
4c7ea3c0 | 2556 | |
0e7b9925 AL |
2557 | err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg); |
2558 | if (err) | |
2559 | return err; | |
54d792f2 AL |
2560 | |
2561 | /* Egress rate control 2: disable egress rate control. */ | |
0e7b9925 AL |
2562 | err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000); |
2563 | if (err) | |
2564 | return err; | |
54d792f2 | 2565 | |
fad09c73 VD |
2566 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
2567 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || | |
2568 | mv88e6xxx_6320_family(chip)) { | |
54d792f2 AL |
2569 | /* Do not limit the period of time that this port can |
2570 | * be paused for by the remote end or the period of | |
2571 | * time that this port can pause the remote end. | |
2572 | */ | |
0e7b9925 AL |
2573 | err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000); |
2574 | if (err) | |
2575 | return err; | |
54d792f2 AL |
2576 | |
2577 | /* Port ATU control: disable limiting the number of | |
2578 | * address database entries that this port is allowed | |
2579 | * to use. | |
2580 | */ | |
0e7b9925 AL |
2581 | err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL, |
2582 | 0x0000); | |
54d792f2 AL |
2583 | /* Priority Override: disable DA, SA and VTU priority |
2584 | * override. | |
2585 | */ | |
0e7b9925 AL |
2586 | err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE, |
2587 | 0x0000); | |
2588 | if (err) | |
2589 | return err; | |
54d792f2 AL |
2590 | |
2591 | /* Port Ethertype: use the Ethertype DSA Ethertype | |
2592 | * value. | |
2593 | */ | |
2bbb33be | 2594 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) { |
0e7b9925 AL |
2595 | err = mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE, |
2596 | ETH_P_EDSA); | |
2597 | if (err) | |
2598 | return err; | |
2bbb33be AL |
2599 | } |
2600 | ||
54d792f2 AL |
2601 | /* Tag Remap: use an identity 802.1p prio -> switch |
2602 | * prio mapping. | |
2603 | */ | |
0e7b9925 AL |
2604 | err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123, |
2605 | 0x3210); | |
2606 | if (err) | |
2607 | return err; | |
54d792f2 AL |
2608 | |
2609 | /* Tag Remap 2: use an identity 802.1p prio -> switch | |
2610 | * prio mapping. | |
2611 | */ | |
0e7b9925 AL |
2612 | err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567, |
2613 | 0x7654); | |
2614 | if (err) | |
2615 | return err; | |
54d792f2 AL |
2616 | } |
2617 | ||
1bc261fa | 2618 | /* Rate Control: disable ingress rate limiting. */ |
fad09c73 VD |
2619 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
2620 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || | |
fad09c73 | 2621 | mv88e6xxx_6320_family(chip)) { |
0e7b9925 AL |
2622 | err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, |
2623 | 0x0001); | |
2624 | if (err) | |
2625 | return err; | |
1bc261fa | 2626 | } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) { |
0e7b9925 AL |
2627 | err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, |
2628 | 0x0000); | |
2629 | if (err) | |
2630 | return err; | |
54d792f2 AL |
2631 | } |
2632 | ||
366f0a0f GR |
2633 | /* Port Control 1: disable trunking, disable sending |
2634 | * learning messages to this port. | |
d827e88a | 2635 | */ |
0e7b9925 AL |
2636 | err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000); |
2637 | if (err) | |
2638 | return err; | |
d827e88a | 2639 | |
207afda1 | 2640 | /* Port based VLAN map: give each port the same default address |
b7666efe VD |
2641 | * database, and allow bidirectional communication between the |
2642 | * CPU and DSA port(s), and the other ports. | |
d827e88a | 2643 | */ |
b4e48c50 | 2644 | err = mv88e6xxx_port_set_fid(chip, port, 0); |
0e7b9925 AL |
2645 | if (err) |
2646 | return err; | |
2db9ce1f | 2647 | |
0e7b9925 AL |
2648 | err = _mv88e6xxx_port_based_vlan_map(chip, port); |
2649 | if (err) | |
2650 | return err; | |
d827e88a GR |
2651 | |
2652 | /* Default VLAN ID and priority: don't set a default VLAN | |
2653 | * ID, and set the default packet priority to zero. | |
2654 | */ | |
0e7b9925 | 2655 | return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000); |
dbde9e66 AL |
2656 | } |
2657 | ||
aa0938c6 | 2658 | static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) |
3b4caa1b VD |
2659 | { |
2660 | int err; | |
2661 | ||
a935c052 | 2662 | err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]); |
3b4caa1b VD |
2663 | if (err) |
2664 | return err; | |
2665 | ||
a935c052 | 2666 | err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); |
3b4caa1b VD |
2667 | if (err) |
2668 | return err; | |
2669 | ||
a935c052 VD |
2670 | err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); |
2671 | if (err) | |
2672 | return err; | |
2673 | ||
2674 | return 0; | |
3b4caa1b VD |
2675 | } |
2676 | ||
acddbd21 VD |
2677 | static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip, |
2678 | unsigned int msecs) | |
2679 | { | |
2680 | const unsigned int coeff = chip->info->age_time_coeff; | |
2681 | const unsigned int min = 0x01 * coeff; | |
2682 | const unsigned int max = 0xff * coeff; | |
2683 | u8 age_time; | |
2684 | u16 val; | |
2685 | int err; | |
2686 | ||
2687 | if (msecs < min || msecs > max) | |
2688 | return -ERANGE; | |
2689 | ||
2690 | /* Round to nearest multiple of coeff */ | |
2691 | age_time = (msecs + coeff / 2) / coeff; | |
2692 | ||
a935c052 | 2693 | err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val); |
acddbd21 VD |
2694 | if (err) |
2695 | return err; | |
2696 | ||
2697 | /* AgeTime is 11:4 bits */ | |
2698 | val &= ~0xff0; | |
2699 | val |= age_time << 4; | |
2700 | ||
a935c052 | 2701 | return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val); |
acddbd21 VD |
2702 | } |
2703 | ||
2cfcd964 VD |
2704 | static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, |
2705 | unsigned int ageing_time) | |
2706 | { | |
04bed143 | 2707 | struct mv88e6xxx_chip *chip = ds->priv; |
2cfcd964 VD |
2708 | int err; |
2709 | ||
2710 | mutex_lock(&chip->reg_lock); | |
2711 | err = mv88e6xxx_g1_set_age_time(chip, ageing_time); | |
2712 | mutex_unlock(&chip->reg_lock); | |
2713 | ||
2714 | return err; | |
2715 | } | |
2716 | ||
9729934c | 2717 | static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) |
acdaffcc | 2718 | { |
fad09c73 | 2719 | struct dsa_switch *ds = chip->ds; |
b0745e87 | 2720 | u32 upstream_port = dsa_upstream_port(ds); |
119477bd | 2721 | u16 reg; |
552238b5 | 2722 | int err; |
54d792f2 | 2723 | |
119477bd VD |
2724 | /* Enable the PHY Polling Unit if present, don't discard any packets, |
2725 | * and mask all interrupt sources. | |
2726 | */ | |
dc30c35b AL |
2727 | err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®); |
2728 | if (err < 0) | |
2729 | return err; | |
2730 | ||
2731 | reg &= ~GLOBAL_CONTROL_PPU_ENABLE; | |
fad09c73 VD |
2732 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) || |
2733 | mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE)) | |
119477bd VD |
2734 | reg |= GLOBAL_CONTROL_PPU_ENABLE; |
2735 | ||
a935c052 | 2736 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg); |
119477bd VD |
2737 | if (err) |
2738 | return err; | |
2739 | ||
b0745e87 VD |
2740 | /* Configure the upstream port, and configure it as the port to which |
2741 | * ingress and egress and ARP monitor frames are to be sent. | |
2742 | */ | |
2743 | reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT | | |
2744 | upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT | | |
2745 | upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT; | |
a935c052 | 2746 | err = mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg); |
b0745e87 VD |
2747 | if (err) |
2748 | return err; | |
2749 | ||
50484ff4 | 2750 | /* Disable remote management, and set the switch's DSA device number. */ |
a935c052 VD |
2751 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2, |
2752 | GLOBAL_CONTROL_2_MULTIPLE_CASCADE | | |
2753 | (ds->index & 0x1f)); | |
50484ff4 VD |
2754 | if (err) |
2755 | return err; | |
2756 | ||
acddbd21 VD |
2757 | /* Clear all the VTU and STU entries */ |
2758 | err = _mv88e6xxx_vtu_stu_flush(chip); | |
2759 | if (err < 0) | |
2760 | return err; | |
2761 | ||
54d792f2 AL |
2762 | /* Set the default address aging time to 5 minutes, and |
2763 | * enable address learn messages to be sent to all message | |
2764 | * ports. | |
2765 | */ | |
a935c052 VD |
2766 | err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, |
2767 | GLOBAL_ATU_CONTROL_LEARN2ALL); | |
48ace4ef | 2768 | if (err) |
08a01261 | 2769 | return err; |
54d792f2 | 2770 | |
acddbd21 VD |
2771 | err = mv88e6xxx_g1_set_age_time(chip, 300000); |
2772 | if (err) | |
9729934c VD |
2773 | return err; |
2774 | ||
2775 | /* Clear all ATU entries */ | |
2776 | err = _mv88e6xxx_atu_flush(chip, 0, true); | |
2777 | if (err) | |
2778 | return err; | |
2779 | ||
54d792f2 | 2780 | /* Configure the IP ToS mapping registers. */ |
a935c052 | 2781 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000); |
48ace4ef | 2782 | if (err) |
08a01261 | 2783 | return err; |
a935c052 | 2784 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000); |
48ace4ef | 2785 | if (err) |
08a01261 | 2786 | return err; |
a935c052 | 2787 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555); |
48ace4ef | 2788 | if (err) |
08a01261 | 2789 | return err; |
a935c052 | 2790 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555); |
48ace4ef | 2791 | if (err) |
08a01261 | 2792 | return err; |
a935c052 | 2793 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa); |
48ace4ef | 2794 | if (err) |
08a01261 | 2795 | return err; |
a935c052 | 2796 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa); |
48ace4ef | 2797 | if (err) |
08a01261 | 2798 | return err; |
a935c052 | 2799 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff); |
48ace4ef | 2800 | if (err) |
08a01261 | 2801 | return err; |
a935c052 | 2802 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff); |
48ace4ef | 2803 | if (err) |
08a01261 | 2804 | return err; |
54d792f2 AL |
2805 | |
2806 | /* Configure the IEEE 802.1p priority mapping register. */ | |
a935c052 | 2807 | err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41); |
48ace4ef | 2808 | if (err) |
08a01261 | 2809 | return err; |
54d792f2 | 2810 | |
9729934c | 2811 | /* Clear the statistics counters for all ports */ |
a935c052 VD |
2812 | err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP, |
2813 | GLOBAL_STATS_OP_FLUSH_ALL); | |
9729934c VD |
2814 | if (err) |
2815 | return err; | |
2816 | ||
2817 | /* Wait for the flush to complete. */ | |
2818 | err = _mv88e6xxx_stats_wait(chip); | |
2819 | if (err) | |
2820 | return err; | |
2821 | ||
2822 | return 0; | |
2823 | } | |
2824 | ||
f81ec90f | 2825 | static int mv88e6xxx_setup(struct dsa_switch *ds) |
08a01261 | 2826 | { |
04bed143 | 2827 | struct mv88e6xxx_chip *chip = ds->priv; |
08a01261 | 2828 | int err; |
a1a6a4d1 VD |
2829 | int i; |
2830 | ||
fad09c73 VD |
2831 | chip->ds = ds; |
2832 | ds->slave_mii_bus = chip->mdio_bus; | |
08a01261 | 2833 | |
fad09c73 | 2834 | mutex_lock(&chip->reg_lock); |
08a01261 | 2835 | |
9729934c | 2836 | /* Setup Switch Port Registers */ |
370b4ffb | 2837 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { |
9729934c VD |
2838 | err = mv88e6xxx_setup_port(chip, i); |
2839 | if (err) | |
2840 | goto unlock; | |
2841 | } | |
2842 | ||
2843 | /* Setup Switch Global 1 Registers */ | |
2844 | err = mv88e6xxx_g1_setup(chip); | |
a1a6a4d1 VD |
2845 | if (err) |
2846 | goto unlock; | |
2847 | ||
9729934c VD |
2848 | /* Setup Switch Global 2 Registers */ |
2849 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) { | |
2850 | err = mv88e6xxx_g2_setup(chip); | |
a1a6a4d1 VD |
2851 | if (err) |
2852 | goto unlock; | |
2853 | } | |
08a01261 | 2854 | |
6b17e864 | 2855 | unlock: |
fad09c73 | 2856 | mutex_unlock(&chip->reg_lock); |
db687a56 | 2857 | |
48ace4ef | 2858 | return err; |
54d792f2 AL |
2859 | } |
2860 | ||
3b4caa1b VD |
2861 | static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr) |
2862 | { | |
04bed143 | 2863 | struct mv88e6xxx_chip *chip = ds->priv; |
3b4caa1b VD |
2864 | int err; |
2865 | ||
b073d4e2 VD |
2866 | if (!chip->info->ops->set_switch_mac) |
2867 | return -EOPNOTSUPP; | |
3b4caa1b | 2868 | |
b073d4e2 VD |
2869 | mutex_lock(&chip->reg_lock); |
2870 | err = chip->info->ops->set_switch_mac(chip, addr); | |
3b4caa1b VD |
2871 | mutex_unlock(&chip->reg_lock); |
2872 | ||
2873 | return err; | |
2874 | } | |
2875 | ||
e57e5e77 | 2876 | static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) |
fd3a0ee4 | 2877 | { |
fad09c73 | 2878 | struct mv88e6xxx_chip *chip = bus->priv; |
e57e5e77 VD |
2879 | u16 val; |
2880 | int err; | |
fd3a0ee4 | 2881 | |
370b4ffb | 2882 | if (phy >= mv88e6xxx_num_ports(chip)) |
158bc065 | 2883 | return 0xffff; |
fd3a0ee4 | 2884 | |
fad09c73 | 2885 | mutex_lock(&chip->reg_lock); |
e57e5e77 | 2886 | err = mv88e6xxx_phy_read(chip, phy, reg, &val); |
fad09c73 | 2887 | mutex_unlock(&chip->reg_lock); |
e57e5e77 VD |
2888 | |
2889 | return err ? err : val; | |
fd3a0ee4 AL |
2890 | } |
2891 | ||
e57e5e77 | 2892 | static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) |
fd3a0ee4 | 2893 | { |
fad09c73 | 2894 | struct mv88e6xxx_chip *chip = bus->priv; |
e57e5e77 | 2895 | int err; |
fd3a0ee4 | 2896 | |
370b4ffb | 2897 | if (phy >= mv88e6xxx_num_ports(chip)) |
158bc065 | 2898 | return 0xffff; |
fd3a0ee4 | 2899 | |
fad09c73 | 2900 | mutex_lock(&chip->reg_lock); |
e57e5e77 | 2901 | err = mv88e6xxx_phy_write(chip, phy, reg, val); |
fad09c73 | 2902 | mutex_unlock(&chip->reg_lock); |
e57e5e77 VD |
2903 | |
2904 | return err; | |
fd3a0ee4 AL |
2905 | } |
2906 | ||
fad09c73 | 2907 | static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, |
b516d453 AL |
2908 | struct device_node *np) |
2909 | { | |
2910 | static int index; | |
2911 | struct mii_bus *bus; | |
2912 | int err; | |
2913 | ||
b516d453 | 2914 | if (np) |
fad09c73 | 2915 | chip->mdio_np = of_get_child_by_name(np, "mdio"); |
b516d453 | 2916 | |
fad09c73 | 2917 | bus = devm_mdiobus_alloc(chip->dev); |
b516d453 AL |
2918 | if (!bus) |
2919 | return -ENOMEM; | |
2920 | ||
fad09c73 | 2921 | bus->priv = (void *)chip; |
b516d453 AL |
2922 | if (np) { |
2923 | bus->name = np->full_name; | |
2924 | snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name); | |
2925 | } else { | |
2926 | bus->name = "mv88e6xxx SMI"; | |
2927 | snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); | |
2928 | } | |
2929 | ||
2930 | bus->read = mv88e6xxx_mdio_read; | |
2931 | bus->write = mv88e6xxx_mdio_write; | |
fad09c73 | 2932 | bus->parent = chip->dev; |
b516d453 | 2933 | |
fad09c73 VD |
2934 | if (chip->mdio_np) |
2935 | err = of_mdiobus_register(bus, chip->mdio_np); | |
b516d453 AL |
2936 | else |
2937 | err = mdiobus_register(bus); | |
2938 | if (err) { | |
fad09c73 | 2939 | dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); |
b516d453 AL |
2940 | goto out; |
2941 | } | |
fad09c73 | 2942 | chip->mdio_bus = bus; |
b516d453 AL |
2943 | |
2944 | return 0; | |
2945 | ||
2946 | out: | |
fad09c73 VD |
2947 | if (chip->mdio_np) |
2948 | of_node_put(chip->mdio_np); | |
b516d453 AL |
2949 | |
2950 | return err; | |
2951 | } | |
2952 | ||
fad09c73 | 2953 | static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip) |
b516d453 AL |
2954 | |
2955 | { | |
fad09c73 | 2956 | struct mii_bus *bus = chip->mdio_bus; |
b516d453 AL |
2957 | |
2958 | mdiobus_unregister(bus); | |
2959 | ||
fad09c73 VD |
2960 | if (chip->mdio_np) |
2961 | of_node_put(chip->mdio_np); | |
b516d453 AL |
2962 | } |
2963 | ||
c22995c5 GR |
2964 | #ifdef CONFIG_NET_DSA_HWMON |
2965 | ||
2966 | static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp) | |
2967 | { | |
04bed143 | 2968 | struct mv88e6xxx_chip *chip = ds->priv; |
9c93829c | 2969 | u16 val; |
c22995c5 | 2970 | int ret; |
c22995c5 GR |
2971 | |
2972 | *temp = 0; | |
2973 | ||
fad09c73 | 2974 | mutex_lock(&chip->reg_lock); |
c22995c5 | 2975 | |
9c93829c | 2976 | ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6); |
c22995c5 GR |
2977 | if (ret < 0) |
2978 | goto error; | |
2979 | ||
2980 | /* Enable temperature sensor */ | |
9c93829c | 2981 | ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val); |
c22995c5 GR |
2982 | if (ret < 0) |
2983 | goto error; | |
2984 | ||
9c93829c | 2985 | ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5)); |
c22995c5 GR |
2986 | if (ret < 0) |
2987 | goto error; | |
2988 | ||
2989 | /* Wait for temperature to stabilize */ | |
2990 | usleep_range(10000, 12000); | |
2991 | ||
9c93829c VD |
2992 | ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val); |
2993 | if (ret < 0) | |
c22995c5 | 2994 | goto error; |
c22995c5 GR |
2995 | |
2996 | /* Disable temperature sensor */ | |
9c93829c | 2997 | ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5)); |
c22995c5 GR |
2998 | if (ret < 0) |
2999 | goto error; | |
3000 | ||
3001 | *temp = ((val & 0x1f) - 5) * 5; | |
3002 | ||
3003 | error: | |
9c93829c | 3004 | mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0); |
fad09c73 | 3005 | mutex_unlock(&chip->reg_lock); |
c22995c5 GR |
3006 | return ret; |
3007 | } | |
3008 | ||
3009 | static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp) | |
3010 | { | |
04bed143 | 3011 | struct mv88e6xxx_chip *chip = ds->priv; |
fad09c73 | 3012 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
9c93829c | 3013 | u16 val; |
c22995c5 GR |
3014 | int ret; |
3015 | ||
3016 | *temp = 0; | |
3017 | ||
9c93829c VD |
3018 | mutex_lock(&chip->reg_lock); |
3019 | ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val); | |
3020 | mutex_unlock(&chip->reg_lock); | |
c22995c5 GR |
3021 | if (ret < 0) |
3022 | return ret; | |
3023 | ||
9c93829c | 3024 | *temp = (val & 0xff) - 25; |
c22995c5 GR |
3025 | |
3026 | return 0; | |
3027 | } | |
3028 | ||
f81ec90f | 3029 | static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) |
c22995c5 | 3030 | { |
04bed143 | 3031 | struct mv88e6xxx_chip *chip = ds->priv; |
158bc065 | 3032 | |
fad09c73 | 3033 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP)) |
6594f615 VD |
3034 | return -EOPNOTSUPP; |
3035 | ||
fad09c73 | 3036 | if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip)) |
c22995c5 GR |
3037 | return mv88e63xx_get_temp(ds, temp); |
3038 | ||
3039 | return mv88e61xx_get_temp(ds, temp); | |
3040 | } | |
3041 | ||
f81ec90f | 3042 | static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp) |
c22995c5 | 3043 | { |
04bed143 | 3044 | struct mv88e6xxx_chip *chip = ds->priv; |
fad09c73 | 3045 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
9c93829c | 3046 | u16 val; |
c22995c5 GR |
3047 | int ret; |
3048 | ||
fad09c73 | 3049 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) |
c22995c5 GR |
3050 | return -EOPNOTSUPP; |
3051 | ||
3052 | *temp = 0; | |
3053 | ||
9c93829c VD |
3054 | mutex_lock(&chip->reg_lock); |
3055 | ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); | |
3056 | mutex_unlock(&chip->reg_lock); | |
c22995c5 GR |
3057 | if (ret < 0) |
3058 | return ret; | |
3059 | ||
9c93829c | 3060 | *temp = (((val >> 8) & 0x1f) * 5) - 25; |
c22995c5 GR |
3061 | |
3062 | return 0; | |
3063 | } | |
3064 | ||
f81ec90f | 3065 | static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp) |
c22995c5 | 3066 | { |
04bed143 | 3067 | struct mv88e6xxx_chip *chip = ds->priv; |
fad09c73 | 3068 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
9c93829c VD |
3069 | u16 val; |
3070 | int err; | |
c22995c5 | 3071 | |
fad09c73 | 3072 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) |
c22995c5 GR |
3073 | return -EOPNOTSUPP; |
3074 | ||
9c93829c VD |
3075 | mutex_lock(&chip->reg_lock); |
3076 | err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); | |
3077 | if (err) | |
3078 | goto unlock; | |
c22995c5 | 3079 | temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); |
9c93829c VD |
3080 | err = mv88e6xxx_phy_page_write(chip, phy, 6, 26, |
3081 | (val & 0xe0ff) | (temp << 8)); | |
3082 | unlock: | |
3083 | mutex_unlock(&chip->reg_lock); | |
3084 | ||
3085 | return err; | |
c22995c5 GR |
3086 | } |
3087 | ||
f81ec90f | 3088 | static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm) |
c22995c5 | 3089 | { |
04bed143 | 3090 | struct mv88e6xxx_chip *chip = ds->priv; |
fad09c73 | 3091 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
9c93829c | 3092 | u16 val; |
c22995c5 GR |
3093 | int ret; |
3094 | ||
fad09c73 | 3095 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) |
c22995c5 GR |
3096 | return -EOPNOTSUPP; |
3097 | ||
3098 | *alarm = false; | |
3099 | ||
9c93829c VD |
3100 | mutex_lock(&chip->reg_lock); |
3101 | ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); | |
3102 | mutex_unlock(&chip->reg_lock); | |
c22995c5 GR |
3103 | if (ret < 0) |
3104 | return ret; | |
3105 | ||
9c93829c | 3106 | *alarm = !!(val & 0x40); |
c22995c5 GR |
3107 | |
3108 | return 0; | |
3109 | } | |
3110 | #endif /* CONFIG_NET_DSA_HWMON */ | |
3111 | ||
855b1932 VD |
3112 | static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) |
3113 | { | |
04bed143 | 3114 | struct mv88e6xxx_chip *chip = ds->priv; |
855b1932 VD |
3115 | |
3116 | return chip->eeprom_len; | |
3117 | } | |
3118 | ||
855b1932 VD |
3119 | static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, |
3120 | struct ethtool_eeprom *eeprom, u8 *data) | |
3121 | { | |
04bed143 | 3122 | struct mv88e6xxx_chip *chip = ds->priv; |
855b1932 VD |
3123 | int err; |
3124 | ||
ee4dc2e7 VD |
3125 | if (!chip->info->ops->get_eeprom) |
3126 | return -EOPNOTSUPP; | |
855b1932 | 3127 | |
ee4dc2e7 VD |
3128 | mutex_lock(&chip->reg_lock); |
3129 | err = chip->info->ops->get_eeprom(chip, eeprom, data); | |
855b1932 VD |
3130 | mutex_unlock(&chip->reg_lock); |
3131 | ||
3132 | if (err) | |
3133 | return err; | |
3134 | ||
3135 | eeprom->magic = 0xc3ec4951; | |
3136 | ||
3137 | return 0; | |
3138 | } | |
3139 | ||
855b1932 VD |
3140 | static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, |
3141 | struct ethtool_eeprom *eeprom, u8 *data) | |
3142 | { | |
04bed143 | 3143 | struct mv88e6xxx_chip *chip = ds->priv; |
855b1932 VD |
3144 | int err; |
3145 | ||
ee4dc2e7 VD |
3146 | if (!chip->info->ops->set_eeprom) |
3147 | return -EOPNOTSUPP; | |
3148 | ||
855b1932 VD |
3149 | if (eeprom->magic != 0xc3ec4951) |
3150 | return -EINVAL; | |
3151 | ||
3152 | mutex_lock(&chip->reg_lock); | |
ee4dc2e7 | 3153 | err = chip->info->ops->set_eeprom(chip, eeprom, data); |
855b1932 VD |
3154 | mutex_unlock(&chip->reg_lock); |
3155 | ||
3156 | return err; | |
3157 | } | |
3158 | ||
b3469dd8 | 3159 | static const struct mv88e6xxx_ops mv88e6085_ops = { |
b073d4e2 | 3160 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
b3469dd8 VD |
3161 | .phy_read = mv88e6xxx_phy_ppu_read, |
3162 | .phy_write = mv88e6xxx_phy_ppu_write, | |
08ef7f10 | 3163 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3164 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
b3469dd8 VD |
3165 | }; |
3166 | ||
3167 | static const struct mv88e6xxx_ops mv88e6095_ops = { | |
b073d4e2 | 3168 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
b3469dd8 VD |
3169 | .phy_read = mv88e6xxx_phy_ppu_read, |
3170 | .phy_write = mv88e6xxx_phy_ppu_write, | |
08ef7f10 | 3171 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3172 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
b3469dd8 VD |
3173 | }; |
3174 | ||
3175 | static const struct mv88e6xxx_ops mv88e6123_ops = { | |
b073d4e2 | 3176 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3177 | .phy_read = mv88e6xxx_read, |
3178 | .phy_write = mv88e6xxx_write, | |
08ef7f10 | 3179 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3180 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
b3469dd8 VD |
3181 | }; |
3182 | ||
3183 | static const struct mv88e6xxx_ops mv88e6131_ops = { | |
b073d4e2 | 3184 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
b3469dd8 VD |
3185 | .phy_read = mv88e6xxx_phy_ppu_read, |
3186 | .phy_write = mv88e6xxx_phy_ppu_write, | |
08ef7f10 | 3187 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3188 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
b3469dd8 VD |
3189 | }; |
3190 | ||
3191 | static const struct mv88e6xxx_ops mv88e6161_ops = { | |
b073d4e2 | 3192 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3193 | .phy_read = mv88e6xxx_read, |
3194 | .phy_write = mv88e6xxx_write, | |
08ef7f10 | 3195 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3196 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
b3469dd8 VD |
3197 | }; |
3198 | ||
3199 | static const struct mv88e6xxx_ops mv88e6165_ops = { | |
b073d4e2 | 3200 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3201 | .phy_read = mv88e6xxx_read, |
3202 | .phy_write = mv88e6xxx_write, | |
08ef7f10 | 3203 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3204 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
b3469dd8 VD |
3205 | }; |
3206 | ||
3207 | static const struct mv88e6xxx_ops mv88e6171_ops = { | |
b073d4e2 | 3208 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3209 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3210 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3211 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3212 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
b3469dd8 VD |
3213 | }; |
3214 | ||
3215 | static const struct mv88e6xxx_ops mv88e6172_ops = { | |
ee4dc2e7 VD |
3216 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3217 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3218 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3219 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3220 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3221 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3222 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 3223 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
b3469dd8 VD |
3224 | }; |
3225 | ||
3226 | static const struct mv88e6xxx_ops mv88e6175_ops = { | |
b073d4e2 | 3227 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3228 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3229 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3230 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3231 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
b3469dd8 VD |
3232 | }; |
3233 | ||
3234 | static const struct mv88e6xxx_ops mv88e6176_ops = { | |
ee4dc2e7 VD |
3235 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3236 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3237 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3238 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3239 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3240 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3241 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 3242 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
b3469dd8 VD |
3243 | }; |
3244 | ||
3245 | static const struct mv88e6xxx_ops mv88e6185_ops = { | |
b073d4e2 | 3246 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
b3469dd8 VD |
3247 | .phy_read = mv88e6xxx_phy_ppu_read, |
3248 | .phy_write = mv88e6xxx_phy_ppu_write, | |
08ef7f10 | 3249 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3250 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
b3469dd8 VD |
3251 | }; |
3252 | ||
3253 | static const struct mv88e6xxx_ops mv88e6240_ops = { | |
ee4dc2e7 VD |
3254 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3255 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3256 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3257 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3258 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3259 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3260 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 3261 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
b3469dd8 VD |
3262 | }; |
3263 | ||
3264 | static const struct mv88e6xxx_ops mv88e6320_ops = { | |
ee4dc2e7 VD |
3265 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3266 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3267 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3268 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3269 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3270 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3271 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
b3469dd8 VD |
3272 | }; |
3273 | ||
3274 | static const struct mv88e6xxx_ops mv88e6321_ops = { | |
ee4dc2e7 VD |
3275 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3276 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3277 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3278 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3279 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3280 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3281 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
b3469dd8 VD |
3282 | }; |
3283 | ||
3284 | static const struct mv88e6xxx_ops mv88e6350_ops = { | |
b073d4e2 | 3285 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3286 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3287 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3288 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3289 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
b3469dd8 VD |
3290 | }; |
3291 | ||
3292 | static const struct mv88e6xxx_ops mv88e6351_ops = { | |
b073d4e2 | 3293 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3294 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3295 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3296 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3297 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
b3469dd8 VD |
3298 | }; |
3299 | ||
3300 | static const struct mv88e6xxx_ops mv88e6352_ops = { | |
ee4dc2e7 VD |
3301 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3302 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3303 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3304 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3305 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3306 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3307 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 3308 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
b3469dd8 VD |
3309 | }; |
3310 | ||
f81ec90f VD |
3311 | static const struct mv88e6xxx_info mv88e6xxx_table[] = { |
3312 | [MV88E6085] = { | |
3313 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6085, | |
3314 | .family = MV88E6XXX_FAMILY_6097, | |
3315 | .name = "Marvell 88E6085", | |
3316 | .num_databases = 4096, | |
3317 | .num_ports = 10, | |
9dddd478 | 3318 | .port_base_addr = 0x10, |
a935c052 | 3319 | .global1_addr = 0x1b, |
acddbd21 | 3320 | .age_time_coeff = 15000, |
dc30c35b | 3321 | .g1_irqs = 8, |
f81ec90f | 3322 | .flags = MV88E6XXX_FLAGS_FAMILY_6097, |
b3469dd8 | 3323 | .ops = &mv88e6085_ops, |
f81ec90f VD |
3324 | }, |
3325 | ||
3326 | [MV88E6095] = { | |
3327 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6095, | |
3328 | .family = MV88E6XXX_FAMILY_6095, | |
3329 | .name = "Marvell 88E6095/88E6095F", | |
3330 | .num_databases = 256, | |
3331 | .num_ports = 11, | |
9dddd478 | 3332 | .port_base_addr = 0x10, |
a935c052 | 3333 | .global1_addr = 0x1b, |
acddbd21 | 3334 | .age_time_coeff = 15000, |
dc30c35b | 3335 | .g1_irqs = 8, |
f81ec90f | 3336 | .flags = MV88E6XXX_FLAGS_FAMILY_6095, |
b3469dd8 | 3337 | .ops = &mv88e6095_ops, |
f81ec90f VD |
3338 | }, |
3339 | ||
3340 | [MV88E6123] = { | |
3341 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6123, | |
3342 | .family = MV88E6XXX_FAMILY_6165, | |
3343 | .name = "Marvell 88E6123", | |
3344 | .num_databases = 4096, | |
3345 | .num_ports = 3, | |
9dddd478 | 3346 | .port_base_addr = 0x10, |
a935c052 | 3347 | .global1_addr = 0x1b, |
acddbd21 | 3348 | .age_time_coeff = 15000, |
dc30c35b | 3349 | .g1_irqs = 9, |
f81ec90f | 3350 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
b3469dd8 | 3351 | .ops = &mv88e6123_ops, |
f81ec90f VD |
3352 | }, |
3353 | ||
3354 | [MV88E6131] = { | |
3355 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6131, | |
3356 | .family = MV88E6XXX_FAMILY_6185, | |
3357 | .name = "Marvell 88E6131", | |
3358 | .num_databases = 256, | |
3359 | .num_ports = 8, | |
9dddd478 | 3360 | .port_base_addr = 0x10, |
a935c052 | 3361 | .global1_addr = 0x1b, |
acddbd21 | 3362 | .age_time_coeff = 15000, |
dc30c35b | 3363 | .g1_irqs = 9, |
f81ec90f | 3364 | .flags = MV88E6XXX_FLAGS_FAMILY_6185, |
b3469dd8 | 3365 | .ops = &mv88e6131_ops, |
f81ec90f VD |
3366 | }, |
3367 | ||
3368 | [MV88E6161] = { | |
3369 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6161, | |
3370 | .family = MV88E6XXX_FAMILY_6165, | |
3371 | .name = "Marvell 88E6161", | |
3372 | .num_databases = 4096, | |
3373 | .num_ports = 6, | |
9dddd478 | 3374 | .port_base_addr = 0x10, |
a935c052 | 3375 | .global1_addr = 0x1b, |
acddbd21 | 3376 | .age_time_coeff = 15000, |
dc30c35b | 3377 | .g1_irqs = 9, |
f81ec90f | 3378 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
b3469dd8 | 3379 | .ops = &mv88e6161_ops, |
f81ec90f VD |
3380 | }, |
3381 | ||
3382 | [MV88E6165] = { | |
3383 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6165, | |
3384 | .family = MV88E6XXX_FAMILY_6165, | |
3385 | .name = "Marvell 88E6165", | |
3386 | .num_databases = 4096, | |
3387 | .num_ports = 6, | |
9dddd478 | 3388 | .port_base_addr = 0x10, |
a935c052 | 3389 | .global1_addr = 0x1b, |
acddbd21 | 3390 | .age_time_coeff = 15000, |
dc30c35b | 3391 | .g1_irqs = 9, |
f81ec90f | 3392 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
b3469dd8 | 3393 | .ops = &mv88e6165_ops, |
f81ec90f VD |
3394 | }, |
3395 | ||
3396 | [MV88E6171] = { | |
3397 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6171, | |
3398 | .family = MV88E6XXX_FAMILY_6351, | |
3399 | .name = "Marvell 88E6171", | |
3400 | .num_databases = 4096, | |
3401 | .num_ports = 7, | |
9dddd478 | 3402 | .port_base_addr = 0x10, |
a935c052 | 3403 | .global1_addr = 0x1b, |
acddbd21 | 3404 | .age_time_coeff = 15000, |
dc30c35b | 3405 | .g1_irqs = 9, |
f81ec90f | 3406 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
b3469dd8 | 3407 | .ops = &mv88e6171_ops, |
f81ec90f VD |
3408 | }, |
3409 | ||
3410 | [MV88E6172] = { | |
3411 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6172, | |
3412 | .family = MV88E6XXX_FAMILY_6352, | |
3413 | .name = "Marvell 88E6172", | |
3414 | .num_databases = 4096, | |
3415 | .num_ports = 7, | |
9dddd478 | 3416 | .port_base_addr = 0x10, |
a935c052 | 3417 | .global1_addr = 0x1b, |
acddbd21 | 3418 | .age_time_coeff = 15000, |
dc30c35b | 3419 | .g1_irqs = 9, |
f81ec90f | 3420 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
b3469dd8 | 3421 | .ops = &mv88e6172_ops, |
f81ec90f VD |
3422 | }, |
3423 | ||
3424 | [MV88E6175] = { | |
3425 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6175, | |
3426 | .family = MV88E6XXX_FAMILY_6351, | |
3427 | .name = "Marvell 88E6175", | |
3428 | .num_databases = 4096, | |
3429 | .num_ports = 7, | |
9dddd478 | 3430 | .port_base_addr = 0x10, |
a935c052 | 3431 | .global1_addr = 0x1b, |
acddbd21 | 3432 | .age_time_coeff = 15000, |
dc30c35b | 3433 | .g1_irqs = 9, |
f81ec90f | 3434 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
b3469dd8 | 3435 | .ops = &mv88e6175_ops, |
f81ec90f VD |
3436 | }, |
3437 | ||
3438 | [MV88E6176] = { | |
3439 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6176, | |
3440 | .family = MV88E6XXX_FAMILY_6352, | |
3441 | .name = "Marvell 88E6176", | |
3442 | .num_databases = 4096, | |
3443 | .num_ports = 7, | |
9dddd478 | 3444 | .port_base_addr = 0x10, |
a935c052 | 3445 | .global1_addr = 0x1b, |
acddbd21 | 3446 | .age_time_coeff = 15000, |
dc30c35b | 3447 | .g1_irqs = 9, |
f81ec90f | 3448 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
b3469dd8 | 3449 | .ops = &mv88e6176_ops, |
f81ec90f VD |
3450 | }, |
3451 | ||
3452 | [MV88E6185] = { | |
3453 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6185, | |
3454 | .family = MV88E6XXX_FAMILY_6185, | |
3455 | .name = "Marvell 88E6185", | |
3456 | .num_databases = 256, | |
3457 | .num_ports = 10, | |
9dddd478 | 3458 | .port_base_addr = 0x10, |
a935c052 | 3459 | .global1_addr = 0x1b, |
acddbd21 | 3460 | .age_time_coeff = 15000, |
dc30c35b | 3461 | .g1_irqs = 8, |
f81ec90f | 3462 | .flags = MV88E6XXX_FLAGS_FAMILY_6185, |
b3469dd8 | 3463 | .ops = &mv88e6185_ops, |
f81ec90f VD |
3464 | }, |
3465 | ||
3466 | [MV88E6240] = { | |
3467 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6240, | |
3468 | .family = MV88E6XXX_FAMILY_6352, | |
3469 | .name = "Marvell 88E6240", | |
3470 | .num_databases = 4096, | |
3471 | .num_ports = 7, | |
9dddd478 | 3472 | .port_base_addr = 0x10, |
a935c052 | 3473 | .global1_addr = 0x1b, |
acddbd21 | 3474 | .age_time_coeff = 15000, |
dc30c35b | 3475 | .g1_irqs = 9, |
f81ec90f | 3476 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
b3469dd8 | 3477 | .ops = &mv88e6240_ops, |
f81ec90f VD |
3478 | }, |
3479 | ||
3480 | [MV88E6320] = { | |
3481 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6320, | |
3482 | .family = MV88E6XXX_FAMILY_6320, | |
3483 | .name = "Marvell 88E6320", | |
3484 | .num_databases = 4096, | |
3485 | .num_ports = 7, | |
9dddd478 | 3486 | .port_base_addr = 0x10, |
a935c052 | 3487 | .global1_addr = 0x1b, |
acddbd21 | 3488 | .age_time_coeff = 15000, |
dc30c35b | 3489 | .g1_irqs = 8, |
f81ec90f | 3490 | .flags = MV88E6XXX_FLAGS_FAMILY_6320, |
b3469dd8 | 3491 | .ops = &mv88e6320_ops, |
f81ec90f VD |
3492 | }, |
3493 | ||
3494 | [MV88E6321] = { | |
3495 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6321, | |
3496 | .family = MV88E6XXX_FAMILY_6320, | |
3497 | .name = "Marvell 88E6321", | |
3498 | .num_databases = 4096, | |
3499 | .num_ports = 7, | |
9dddd478 | 3500 | .port_base_addr = 0x10, |
a935c052 | 3501 | .global1_addr = 0x1b, |
acddbd21 | 3502 | .age_time_coeff = 15000, |
dc30c35b | 3503 | .g1_irqs = 8, |
f81ec90f | 3504 | .flags = MV88E6XXX_FLAGS_FAMILY_6320, |
b3469dd8 | 3505 | .ops = &mv88e6321_ops, |
f81ec90f VD |
3506 | }, |
3507 | ||
3508 | [MV88E6350] = { | |
3509 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6350, | |
3510 | .family = MV88E6XXX_FAMILY_6351, | |
3511 | .name = "Marvell 88E6350", | |
3512 | .num_databases = 4096, | |
3513 | .num_ports = 7, | |
9dddd478 | 3514 | .port_base_addr = 0x10, |
a935c052 | 3515 | .global1_addr = 0x1b, |
acddbd21 | 3516 | .age_time_coeff = 15000, |
dc30c35b | 3517 | .g1_irqs = 9, |
f81ec90f | 3518 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
b3469dd8 | 3519 | .ops = &mv88e6350_ops, |
f81ec90f VD |
3520 | }, |
3521 | ||
3522 | [MV88E6351] = { | |
3523 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6351, | |
3524 | .family = MV88E6XXX_FAMILY_6351, | |
3525 | .name = "Marvell 88E6351", | |
3526 | .num_databases = 4096, | |
3527 | .num_ports = 7, | |
9dddd478 | 3528 | .port_base_addr = 0x10, |
a935c052 | 3529 | .global1_addr = 0x1b, |
acddbd21 | 3530 | .age_time_coeff = 15000, |
dc30c35b | 3531 | .g1_irqs = 9, |
f81ec90f | 3532 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
b3469dd8 | 3533 | .ops = &mv88e6351_ops, |
f81ec90f VD |
3534 | }, |
3535 | ||
3536 | [MV88E6352] = { | |
3537 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6352, | |
3538 | .family = MV88E6XXX_FAMILY_6352, | |
3539 | .name = "Marvell 88E6352", | |
3540 | .num_databases = 4096, | |
3541 | .num_ports = 7, | |
9dddd478 | 3542 | .port_base_addr = 0x10, |
a935c052 | 3543 | .global1_addr = 0x1b, |
acddbd21 | 3544 | .age_time_coeff = 15000, |
dc30c35b | 3545 | .g1_irqs = 9, |
f81ec90f | 3546 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
b3469dd8 | 3547 | .ops = &mv88e6352_ops, |
f81ec90f VD |
3548 | }, |
3549 | }; | |
3550 | ||
5f7c0367 | 3551 | static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) |
b9b37713 | 3552 | { |
a439c061 | 3553 | int i; |
b9b37713 | 3554 | |
5f7c0367 VD |
3555 | for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) |
3556 | if (mv88e6xxx_table[i].prod_num == prod_num) | |
3557 | return &mv88e6xxx_table[i]; | |
b9b37713 | 3558 | |
b9b37713 VD |
3559 | return NULL; |
3560 | } | |
3561 | ||
fad09c73 | 3562 | static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) |
bc46a3d5 VD |
3563 | { |
3564 | const struct mv88e6xxx_info *info; | |
8f6345b2 VD |
3565 | unsigned int prod_num, rev; |
3566 | u16 id; | |
3567 | int err; | |
bc46a3d5 | 3568 | |
8f6345b2 VD |
3569 | mutex_lock(&chip->reg_lock); |
3570 | err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id); | |
3571 | mutex_unlock(&chip->reg_lock); | |
3572 | if (err) | |
3573 | return err; | |
bc46a3d5 VD |
3574 | |
3575 | prod_num = (id & 0xfff0) >> 4; | |
3576 | rev = id & 0x000f; | |
3577 | ||
3578 | info = mv88e6xxx_lookup_info(prod_num); | |
3579 | if (!info) | |
3580 | return -ENODEV; | |
3581 | ||
caac8545 | 3582 | /* Update the compatible info with the probed one */ |
fad09c73 | 3583 | chip->info = info; |
bc46a3d5 | 3584 | |
ca070c10 VD |
3585 | err = mv88e6xxx_g2_require(chip); |
3586 | if (err) | |
3587 | return err; | |
3588 | ||
fad09c73 VD |
3589 | dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", |
3590 | chip->info->prod_num, chip->info->name, rev); | |
bc46a3d5 VD |
3591 | |
3592 | return 0; | |
3593 | } | |
3594 | ||
fad09c73 | 3595 | static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) |
469d729f | 3596 | { |
fad09c73 | 3597 | struct mv88e6xxx_chip *chip; |
469d729f | 3598 | |
fad09c73 VD |
3599 | chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); |
3600 | if (!chip) | |
469d729f VD |
3601 | return NULL; |
3602 | ||
fad09c73 | 3603 | chip->dev = dev; |
469d729f | 3604 | |
fad09c73 | 3605 | mutex_init(&chip->reg_lock); |
469d729f | 3606 | |
fad09c73 | 3607 | return chip; |
469d729f VD |
3608 | } |
3609 | ||
e57e5e77 VD |
3610 | static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip) |
3611 | { | |
b3469dd8 | 3612 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) |
e57e5e77 | 3613 | mv88e6xxx_ppu_state_init(chip); |
e57e5e77 VD |
3614 | } |
3615 | ||
930188ce AL |
3616 | static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip) |
3617 | { | |
b3469dd8 | 3618 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) |
930188ce | 3619 | mv88e6xxx_ppu_state_destroy(chip); |
930188ce AL |
3620 | } |
3621 | ||
fad09c73 | 3622 | static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, |
4a70c4ab VD |
3623 | struct mii_bus *bus, int sw_addr) |
3624 | { | |
3625 | /* ADDR[0] pin is unavailable externally and considered zero */ | |
3626 | if (sw_addr & 0x1) | |
3627 | return -EINVAL; | |
3628 | ||
914b32f6 | 3629 | if (sw_addr == 0) |
fad09c73 | 3630 | chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; |
a0ffff24 | 3631 | else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP)) |
fad09c73 | 3632 | chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; |
914b32f6 VD |
3633 | else |
3634 | return -EINVAL; | |
3635 | ||
fad09c73 VD |
3636 | chip->bus = bus; |
3637 | chip->sw_addr = sw_addr; | |
4a70c4ab VD |
3638 | |
3639 | return 0; | |
3640 | } | |
3641 | ||
7b314362 AL |
3642 | static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds) |
3643 | { | |
04bed143 | 3644 | struct mv88e6xxx_chip *chip = ds->priv; |
2bbb33be AL |
3645 | |
3646 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) | |
3647 | return DSA_TAG_PROTO_EDSA; | |
3648 | ||
3649 | return DSA_TAG_PROTO_DSA; | |
7b314362 AL |
3650 | } |
3651 | ||
fcdce7d0 AL |
3652 | static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, |
3653 | struct device *host_dev, int sw_addr, | |
3654 | void **priv) | |
a77d43f1 | 3655 | { |
fad09c73 | 3656 | struct mv88e6xxx_chip *chip; |
a439c061 | 3657 | struct mii_bus *bus; |
b516d453 | 3658 | int err; |
a77d43f1 | 3659 | |
a439c061 | 3660 | bus = dsa_host_dev_to_mii_bus(host_dev); |
c156913b AL |
3661 | if (!bus) |
3662 | return NULL; | |
3663 | ||
fad09c73 VD |
3664 | chip = mv88e6xxx_alloc_chip(dsa_dev); |
3665 | if (!chip) | |
469d729f VD |
3666 | return NULL; |
3667 | ||
caac8545 | 3668 | /* Legacy SMI probing will only support chips similar to 88E6085 */ |
fad09c73 | 3669 | chip->info = &mv88e6xxx_table[MV88E6085]; |
caac8545 | 3670 | |
fad09c73 | 3671 | err = mv88e6xxx_smi_init(chip, bus, sw_addr); |
4a70c4ab VD |
3672 | if (err) |
3673 | goto free; | |
3674 | ||
fad09c73 | 3675 | err = mv88e6xxx_detect(chip); |
bc46a3d5 | 3676 | if (err) |
469d729f | 3677 | goto free; |
a439c061 | 3678 | |
dc30c35b AL |
3679 | mutex_lock(&chip->reg_lock); |
3680 | err = mv88e6xxx_switch_reset(chip); | |
3681 | mutex_unlock(&chip->reg_lock); | |
3682 | if (err) | |
3683 | goto free; | |
3684 | ||
e57e5e77 VD |
3685 | mv88e6xxx_phy_init(chip); |
3686 | ||
fad09c73 | 3687 | err = mv88e6xxx_mdio_register(chip, NULL); |
b516d453 | 3688 | if (err) |
469d729f | 3689 | goto free; |
b516d453 | 3690 | |
fad09c73 | 3691 | *priv = chip; |
a439c061 | 3692 | |
fad09c73 | 3693 | return chip->info->name; |
469d729f | 3694 | free: |
fad09c73 | 3695 | devm_kfree(dsa_dev, chip); |
469d729f VD |
3696 | |
3697 | return NULL; | |
a77d43f1 AL |
3698 | } |
3699 | ||
7df8fbdd VD |
3700 | static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, |
3701 | const struct switchdev_obj_port_mdb *mdb, | |
3702 | struct switchdev_trans *trans) | |
3703 | { | |
3704 | /* We don't need any dynamic resource from the kernel (yet), | |
3705 | * so skip the prepare phase. | |
3706 | */ | |
3707 | ||
3708 | return 0; | |
3709 | } | |
3710 | ||
3711 | static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, | |
3712 | const struct switchdev_obj_port_mdb *mdb, | |
3713 | struct switchdev_trans *trans) | |
3714 | { | |
04bed143 | 3715 | struct mv88e6xxx_chip *chip = ds->priv; |
7df8fbdd VD |
3716 | |
3717 | mutex_lock(&chip->reg_lock); | |
3718 | if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, | |
3719 | GLOBAL_ATU_DATA_STATE_MC_STATIC)) | |
3720 | netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n"); | |
3721 | mutex_unlock(&chip->reg_lock); | |
3722 | } | |
3723 | ||
3724 | static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, | |
3725 | const struct switchdev_obj_port_mdb *mdb) | |
3726 | { | |
04bed143 | 3727 | struct mv88e6xxx_chip *chip = ds->priv; |
7df8fbdd VD |
3728 | int err; |
3729 | ||
3730 | mutex_lock(&chip->reg_lock); | |
3731 | err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, | |
3732 | GLOBAL_ATU_DATA_STATE_UNUSED); | |
3733 | mutex_unlock(&chip->reg_lock); | |
3734 | ||
3735 | return err; | |
3736 | } | |
3737 | ||
3738 | static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port, | |
3739 | struct switchdev_obj_port_mdb *mdb, | |
3740 | int (*cb)(struct switchdev_obj *obj)) | |
3741 | { | |
04bed143 | 3742 | struct mv88e6xxx_chip *chip = ds->priv; |
7df8fbdd VD |
3743 | int err; |
3744 | ||
3745 | mutex_lock(&chip->reg_lock); | |
3746 | err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb); | |
3747 | mutex_unlock(&chip->reg_lock); | |
3748 | ||
3749 | return err; | |
3750 | } | |
3751 | ||
9d490b4e | 3752 | static struct dsa_switch_ops mv88e6xxx_switch_ops = { |
fcdce7d0 | 3753 | .probe = mv88e6xxx_drv_probe, |
7b314362 | 3754 | .get_tag_protocol = mv88e6xxx_get_tag_protocol, |
f81ec90f VD |
3755 | .setup = mv88e6xxx_setup, |
3756 | .set_addr = mv88e6xxx_set_addr, | |
f81ec90f VD |
3757 | .adjust_link = mv88e6xxx_adjust_link, |
3758 | .get_strings = mv88e6xxx_get_strings, | |
3759 | .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, | |
3760 | .get_sset_count = mv88e6xxx_get_sset_count, | |
3761 | .set_eee = mv88e6xxx_set_eee, | |
3762 | .get_eee = mv88e6xxx_get_eee, | |
3763 | #ifdef CONFIG_NET_DSA_HWMON | |
3764 | .get_temp = mv88e6xxx_get_temp, | |
3765 | .get_temp_limit = mv88e6xxx_get_temp_limit, | |
3766 | .set_temp_limit = mv88e6xxx_set_temp_limit, | |
3767 | .get_temp_alarm = mv88e6xxx_get_temp_alarm, | |
3768 | #endif | |
f8cd8753 | 3769 | .get_eeprom_len = mv88e6xxx_get_eeprom_len, |
f81ec90f VD |
3770 | .get_eeprom = mv88e6xxx_get_eeprom, |
3771 | .set_eeprom = mv88e6xxx_set_eeprom, | |
3772 | .get_regs_len = mv88e6xxx_get_regs_len, | |
3773 | .get_regs = mv88e6xxx_get_regs, | |
2cfcd964 | 3774 | .set_ageing_time = mv88e6xxx_set_ageing_time, |
f81ec90f VD |
3775 | .port_bridge_join = mv88e6xxx_port_bridge_join, |
3776 | .port_bridge_leave = mv88e6xxx_port_bridge_leave, | |
3777 | .port_stp_state_set = mv88e6xxx_port_stp_state_set, | |
749efcb8 | 3778 | .port_fast_age = mv88e6xxx_port_fast_age, |
f81ec90f VD |
3779 | .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, |
3780 | .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, | |
3781 | .port_vlan_add = mv88e6xxx_port_vlan_add, | |
3782 | .port_vlan_del = mv88e6xxx_port_vlan_del, | |
3783 | .port_vlan_dump = mv88e6xxx_port_vlan_dump, | |
3784 | .port_fdb_prepare = mv88e6xxx_port_fdb_prepare, | |
3785 | .port_fdb_add = mv88e6xxx_port_fdb_add, | |
3786 | .port_fdb_del = mv88e6xxx_port_fdb_del, | |
3787 | .port_fdb_dump = mv88e6xxx_port_fdb_dump, | |
7df8fbdd VD |
3788 | .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, |
3789 | .port_mdb_add = mv88e6xxx_port_mdb_add, | |
3790 | .port_mdb_del = mv88e6xxx_port_mdb_del, | |
3791 | .port_mdb_dump = mv88e6xxx_port_mdb_dump, | |
f81ec90f VD |
3792 | }; |
3793 | ||
fad09c73 | 3794 | static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip, |
b7e66a5f VD |
3795 | struct device_node *np) |
3796 | { | |
fad09c73 | 3797 | struct device *dev = chip->dev; |
b7e66a5f VD |
3798 | struct dsa_switch *ds; |
3799 | ||
3800 | ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); | |
3801 | if (!ds) | |
3802 | return -ENOMEM; | |
3803 | ||
3804 | ds->dev = dev; | |
fad09c73 | 3805 | ds->priv = chip; |
9d490b4e | 3806 | ds->ops = &mv88e6xxx_switch_ops; |
b7e66a5f VD |
3807 | |
3808 | dev_set_drvdata(dev, ds); | |
3809 | ||
3810 | return dsa_register_switch(ds, np); | |
3811 | } | |
3812 | ||
fad09c73 | 3813 | static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) |
b7e66a5f | 3814 | { |
fad09c73 | 3815 | dsa_unregister_switch(chip->ds); |
b7e66a5f VD |
3816 | } |
3817 | ||
57d32310 | 3818 | static int mv88e6xxx_probe(struct mdio_device *mdiodev) |
98e67308 | 3819 | { |
14c7b3c3 | 3820 | struct device *dev = &mdiodev->dev; |
f8cd8753 | 3821 | struct device_node *np = dev->of_node; |
caac8545 | 3822 | const struct mv88e6xxx_info *compat_info; |
fad09c73 | 3823 | struct mv88e6xxx_chip *chip; |
f8cd8753 | 3824 | u32 eeprom_len; |
52638f71 | 3825 | int err; |
14c7b3c3 | 3826 | |
caac8545 VD |
3827 | compat_info = of_device_get_match_data(dev); |
3828 | if (!compat_info) | |
3829 | return -EINVAL; | |
3830 | ||
fad09c73 VD |
3831 | chip = mv88e6xxx_alloc_chip(dev); |
3832 | if (!chip) | |
14c7b3c3 AL |
3833 | return -ENOMEM; |
3834 | ||
fad09c73 | 3835 | chip->info = compat_info; |
caac8545 | 3836 | |
fad09c73 | 3837 | err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); |
4a70c4ab VD |
3838 | if (err) |
3839 | return err; | |
14c7b3c3 | 3840 | |
fad09c73 | 3841 | err = mv88e6xxx_detect(chip); |
bc46a3d5 VD |
3842 | if (err) |
3843 | return err; | |
14c7b3c3 | 3844 | |
e57e5e77 VD |
3845 | mv88e6xxx_phy_init(chip); |
3846 | ||
fad09c73 VD |
3847 | chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS); |
3848 | if (IS_ERR(chip->reset)) | |
3849 | return PTR_ERR(chip->reset); | |
52638f71 | 3850 | |
ee4dc2e7 | 3851 | if (chip->info->ops->get_eeprom && |
f8cd8753 | 3852 | !of_property_read_u32(np, "eeprom-length", &eeprom_len)) |
fad09c73 | 3853 | chip->eeprom_len = eeprom_len; |
f8cd8753 | 3854 | |
dc30c35b AL |
3855 | mutex_lock(&chip->reg_lock); |
3856 | err = mv88e6xxx_switch_reset(chip); | |
3857 | mutex_unlock(&chip->reg_lock); | |
3858 | if (err) | |
3859 | goto out; | |
3860 | ||
3861 | chip->irq = of_irq_get(np, 0); | |
3862 | if (chip->irq == -EPROBE_DEFER) { | |
3863 | err = chip->irq; | |
3864 | goto out; | |
3865 | } | |
3866 | ||
3867 | if (chip->irq > 0) { | |
3868 | /* Has to be performed before the MDIO bus is created, | |
3869 | * because the PHYs will link there interrupts to these | |
3870 | * interrupt controllers | |
3871 | */ | |
3872 | mutex_lock(&chip->reg_lock); | |
3873 | err = mv88e6xxx_g1_irq_setup(chip); | |
3874 | mutex_unlock(&chip->reg_lock); | |
3875 | ||
3876 | if (err) | |
3877 | goto out; | |
3878 | ||
3879 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) { | |
3880 | err = mv88e6xxx_g2_irq_setup(chip); | |
3881 | if (err) | |
3882 | goto out_g1_irq; | |
3883 | } | |
3884 | } | |
3885 | ||
fad09c73 | 3886 | err = mv88e6xxx_mdio_register(chip, np); |
b516d453 | 3887 | if (err) |
dc30c35b | 3888 | goto out_g2_irq; |
b516d453 | 3889 | |
fad09c73 | 3890 | err = mv88e6xxx_register_switch(chip, np); |
dc30c35b AL |
3891 | if (err) |
3892 | goto out_mdio; | |
83c0afae | 3893 | |
98e67308 | 3894 | return 0; |
dc30c35b AL |
3895 | |
3896 | out_mdio: | |
3897 | mv88e6xxx_mdio_unregister(chip); | |
3898 | out_g2_irq: | |
3899 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) | |
3900 | mv88e6xxx_g2_irq_free(chip); | |
3901 | out_g1_irq: | |
3902 | mv88e6xxx_g1_irq_free(chip); | |
3903 | out: | |
3904 | return err; | |
98e67308 | 3905 | } |
14c7b3c3 AL |
3906 | |
3907 | static void mv88e6xxx_remove(struct mdio_device *mdiodev) | |
3908 | { | |
3909 | struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); | |
04bed143 | 3910 | struct mv88e6xxx_chip *chip = ds->priv; |
14c7b3c3 | 3911 | |
930188ce | 3912 | mv88e6xxx_phy_destroy(chip); |
fad09c73 VD |
3913 | mv88e6xxx_unregister_switch(chip); |
3914 | mv88e6xxx_mdio_unregister(chip); | |
dc30c35b AL |
3915 | |
3916 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) | |
3917 | mv88e6xxx_g2_irq_free(chip); | |
3918 | mv88e6xxx_g1_irq_free(chip); | |
14c7b3c3 AL |
3919 | } |
3920 | ||
3921 | static const struct of_device_id mv88e6xxx_of_match[] = { | |
caac8545 VD |
3922 | { |
3923 | .compatible = "marvell,mv88e6085", | |
3924 | .data = &mv88e6xxx_table[MV88E6085], | |
3925 | }, | |
14c7b3c3 AL |
3926 | { /* sentinel */ }, |
3927 | }; | |
3928 | ||
3929 | MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); | |
3930 | ||
3931 | static struct mdio_driver mv88e6xxx_driver = { | |
3932 | .probe = mv88e6xxx_probe, | |
3933 | .remove = mv88e6xxx_remove, | |
3934 | .mdiodrv.driver = { | |
3935 | .name = "mv88e6085", | |
3936 | .of_match_table = mv88e6xxx_of_match, | |
3937 | }, | |
3938 | }; | |
3939 | ||
3940 | static int __init mv88e6xxx_init(void) | |
3941 | { | |
9d490b4e | 3942 | register_switch_driver(&mv88e6xxx_switch_ops); |
14c7b3c3 AL |
3943 | return mdio_driver_register(&mv88e6xxx_driver); |
3944 | } | |
98e67308 BH |
3945 | module_init(mv88e6xxx_init); |
3946 | ||
3947 | static void __exit mv88e6xxx_cleanup(void) | |
3948 | { | |
14c7b3c3 | 3949 | mdio_driver_unregister(&mv88e6xxx_driver); |
9d490b4e | 3950 | unregister_switch_driver(&mv88e6xxx_switch_ops); |
98e67308 BH |
3951 | } |
3952 | module_exit(mv88e6xxx_cleanup); | |
3d825ede BH |
3953 | |
3954 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); | |
3955 | MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); | |
3956 | MODULE_LICENSE("GPL"); |