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Commit | Line | Data |
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91da11f8 | 1 | /* |
0d3cd4b6 VD |
2 | * Marvell 88e6xxx Ethernet switch single-chip support |
3 | * | |
91da11f8 LB |
4 | * Copyright (c) 2008 Marvell Semiconductor |
5 | * | |
b8fee957 VD |
6 | * Copyright (c) 2015 CMC Electronics, Inc. |
7 | * Added support for VLAN Table Unit operations | |
8 | * | |
14c7b3c3 AL |
9 | * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> |
10 | * | |
91da11f8 LB |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
19b2f97e | 17 | #include <linux/delay.h> |
defb05b9 | 18 | #include <linux/etherdevice.h> |
dea87024 | 19 | #include <linux/ethtool.h> |
facd95b2 | 20 | #include <linux/if_bridge.h> |
dc30c35b AL |
21 | #include <linux/interrupt.h> |
22 | #include <linux/irq.h> | |
23 | #include <linux/irqdomain.h> | |
19b2f97e | 24 | #include <linux/jiffies.h> |
91da11f8 | 25 | #include <linux/list.h> |
14c7b3c3 | 26 | #include <linux/mdio.h> |
2bbba277 | 27 | #include <linux/module.h> |
caac8545 | 28 | #include <linux/of_device.h> |
dc30c35b | 29 | #include <linux/of_irq.h> |
b516d453 | 30 | #include <linux/of_mdio.h> |
91da11f8 | 31 | #include <linux/netdevice.h> |
c8c1b39a | 32 | #include <linux/gpio/consumer.h> |
91da11f8 | 33 | #include <linux/phy.h> |
c8f0b869 | 34 | #include <net/dsa.h> |
1f36faf2 | 35 | #include <net/switchdev.h> |
ec561276 | 36 | |
91da11f8 | 37 | #include "mv88e6xxx.h" |
a935c052 | 38 | #include "global1.h" |
ec561276 | 39 | #include "global2.h" |
18abed21 | 40 | #include "port.h" |
91da11f8 | 41 | |
fad09c73 | 42 | static void assert_reg_lock(struct mv88e6xxx_chip *chip) |
3996a4ff | 43 | { |
fad09c73 VD |
44 | if (unlikely(!mutex_is_locked(&chip->reg_lock))) { |
45 | dev_err(chip->dev, "Switch registers lock not held!\n"); | |
3996a4ff VD |
46 | dump_stack(); |
47 | } | |
48 | } | |
49 | ||
914b32f6 VD |
50 | /* The switch ADDR[4:1] configuration pins define the chip SMI device address |
51 | * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). | |
52 | * | |
53 | * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it | |
54 | * is the only device connected to the SMI master. In this mode it responds to | |
55 | * all 32 possible SMI addresses, and thus maps directly the internal devices. | |
56 | * | |
57 | * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing | |
58 | * multiple devices to share the SMI interface. In this mode it responds to only | |
59 | * 2 registers, used to indirectly access the internal SMI devices. | |
91da11f8 | 60 | */ |
914b32f6 | 61 | |
fad09c73 | 62 | static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
63 | int addr, int reg, u16 *val) |
64 | { | |
fad09c73 | 65 | if (!chip->smi_ops) |
914b32f6 VD |
66 | return -EOPNOTSUPP; |
67 | ||
fad09c73 | 68 | return chip->smi_ops->read(chip, addr, reg, val); |
914b32f6 VD |
69 | } |
70 | ||
fad09c73 | 71 | static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
72 | int addr, int reg, u16 val) |
73 | { | |
fad09c73 | 74 | if (!chip->smi_ops) |
914b32f6 VD |
75 | return -EOPNOTSUPP; |
76 | ||
fad09c73 | 77 | return chip->smi_ops->write(chip, addr, reg, val); |
914b32f6 VD |
78 | } |
79 | ||
fad09c73 | 80 | static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
81 | int addr, int reg, u16 *val) |
82 | { | |
83 | int ret; | |
84 | ||
fad09c73 | 85 | ret = mdiobus_read_nested(chip->bus, addr, reg); |
914b32f6 VD |
86 | if (ret < 0) |
87 | return ret; | |
88 | ||
89 | *val = ret & 0xffff; | |
90 | ||
91 | return 0; | |
92 | } | |
93 | ||
fad09c73 | 94 | static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
95 | int addr, int reg, u16 val) |
96 | { | |
97 | int ret; | |
98 | ||
fad09c73 | 99 | ret = mdiobus_write_nested(chip->bus, addr, reg, val); |
914b32f6 VD |
100 | if (ret < 0) |
101 | return ret; | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
c08026ab | 106 | static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { |
914b32f6 VD |
107 | .read = mv88e6xxx_smi_single_chip_read, |
108 | .write = mv88e6xxx_smi_single_chip_write, | |
109 | }; | |
110 | ||
fad09c73 | 111 | static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) |
91da11f8 LB |
112 | { |
113 | int ret; | |
114 | int i; | |
115 | ||
116 | for (i = 0; i < 16; i++) { | |
fad09c73 | 117 | ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); |
91da11f8 LB |
118 | if (ret < 0) |
119 | return ret; | |
120 | ||
cca8b133 | 121 | if ((ret & SMI_CMD_BUSY) == 0) |
91da11f8 LB |
122 | return 0; |
123 | } | |
124 | ||
125 | return -ETIMEDOUT; | |
126 | } | |
127 | ||
fad09c73 | 128 | static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, |
914b32f6 | 129 | int addr, int reg, u16 *val) |
91da11f8 LB |
130 | { |
131 | int ret; | |
132 | ||
3675c8d7 | 133 | /* Wait for the bus to become free. */ |
fad09c73 | 134 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
135 | if (ret < 0) |
136 | return ret; | |
137 | ||
3675c8d7 | 138 | /* Transmit the read command. */ |
fad09c73 | 139 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, |
6e899e6c | 140 | SMI_CMD_OP_22_READ | (addr << 5) | reg); |
91da11f8 LB |
141 | if (ret < 0) |
142 | return ret; | |
143 | ||
3675c8d7 | 144 | /* Wait for the read command to complete. */ |
fad09c73 | 145 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
146 | if (ret < 0) |
147 | return ret; | |
148 | ||
3675c8d7 | 149 | /* Read the data. */ |
fad09c73 | 150 | ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); |
bb92ea5e VD |
151 | if (ret < 0) |
152 | return ret; | |
153 | ||
914b32f6 | 154 | *val = ret & 0xffff; |
91da11f8 | 155 | |
914b32f6 | 156 | return 0; |
8d6d09e7 GR |
157 | } |
158 | ||
fad09c73 | 159 | static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, |
914b32f6 | 160 | int addr, int reg, u16 val) |
91da11f8 LB |
161 | { |
162 | int ret; | |
163 | ||
3675c8d7 | 164 | /* Wait for the bus to become free. */ |
fad09c73 | 165 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
166 | if (ret < 0) |
167 | return ret; | |
168 | ||
3675c8d7 | 169 | /* Transmit the data to write. */ |
fad09c73 | 170 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); |
91da11f8 LB |
171 | if (ret < 0) |
172 | return ret; | |
173 | ||
3675c8d7 | 174 | /* Transmit the write command. */ |
fad09c73 | 175 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, |
6e899e6c | 176 | SMI_CMD_OP_22_WRITE | (addr << 5) | reg); |
91da11f8 LB |
177 | if (ret < 0) |
178 | return ret; | |
179 | ||
3675c8d7 | 180 | /* Wait for the write command to complete. */ |
fad09c73 | 181 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
182 | if (ret < 0) |
183 | return ret; | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
c08026ab | 188 | static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { |
914b32f6 VD |
189 | .read = mv88e6xxx_smi_multi_chip_read, |
190 | .write = mv88e6xxx_smi_multi_chip_write, | |
191 | }; | |
192 | ||
ec561276 | 193 | int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) |
914b32f6 VD |
194 | { |
195 | int err; | |
196 | ||
fad09c73 | 197 | assert_reg_lock(chip); |
914b32f6 | 198 | |
fad09c73 | 199 | err = mv88e6xxx_smi_read(chip, addr, reg, val); |
914b32f6 VD |
200 | if (err) |
201 | return err; | |
202 | ||
fad09c73 | 203 | dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
914b32f6 VD |
204 | addr, reg, *val); |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
ec561276 | 209 | int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) |
91da11f8 | 210 | { |
914b32f6 VD |
211 | int err; |
212 | ||
fad09c73 | 213 | assert_reg_lock(chip); |
91da11f8 | 214 | |
fad09c73 | 215 | err = mv88e6xxx_smi_write(chip, addr, reg, val); |
914b32f6 VD |
216 | if (err) |
217 | return err; | |
218 | ||
fad09c73 | 219 | dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
bb92ea5e VD |
220 | addr, reg, val); |
221 | ||
914b32f6 VD |
222 | return 0; |
223 | } | |
224 | ||
e57e5e77 VD |
225 | static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy, |
226 | int reg, u16 *val) | |
227 | { | |
228 | int addr = phy; /* PHY devices addresses start at 0x0 */ | |
229 | ||
b3469dd8 | 230 | if (!chip->info->ops->phy_read) |
e57e5e77 VD |
231 | return -EOPNOTSUPP; |
232 | ||
b3469dd8 | 233 | return chip->info->ops->phy_read(chip, addr, reg, val); |
e57e5e77 VD |
234 | } |
235 | ||
236 | static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, | |
237 | int reg, u16 val) | |
238 | { | |
239 | int addr = phy; /* PHY devices addresses start at 0x0 */ | |
240 | ||
b3469dd8 | 241 | if (!chip->info->ops->phy_write) |
e57e5e77 VD |
242 | return -EOPNOTSUPP; |
243 | ||
b3469dd8 | 244 | return chip->info->ops->phy_write(chip, addr, reg, val); |
e57e5e77 VD |
245 | } |
246 | ||
09cb7dfd VD |
247 | static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page) |
248 | { | |
249 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE)) | |
250 | return -EOPNOTSUPP; | |
251 | ||
252 | return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); | |
253 | } | |
254 | ||
255 | static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy) | |
256 | { | |
257 | int err; | |
258 | ||
259 | /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */ | |
260 | err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER); | |
261 | if (unlikely(err)) { | |
262 | dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n", | |
263 | phy, err); | |
264 | } | |
265 | } | |
266 | ||
267 | static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy, | |
268 | u8 page, int reg, u16 *val) | |
269 | { | |
270 | int err; | |
271 | ||
272 | /* There is no paging for registers 22 */ | |
273 | if (reg == PHY_PAGE) | |
274 | return -EINVAL; | |
275 | ||
276 | err = mv88e6xxx_phy_page_get(chip, phy, page); | |
277 | if (!err) { | |
278 | err = mv88e6xxx_phy_read(chip, phy, reg, val); | |
279 | mv88e6xxx_phy_page_put(chip, phy); | |
280 | } | |
281 | ||
282 | return err; | |
283 | } | |
284 | ||
285 | static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy, | |
286 | u8 page, int reg, u16 val) | |
287 | { | |
288 | int err; | |
289 | ||
290 | /* There is no paging for registers 22 */ | |
291 | if (reg == PHY_PAGE) | |
292 | return -EINVAL; | |
293 | ||
294 | err = mv88e6xxx_phy_page_get(chip, phy, page); | |
295 | if (!err) { | |
296 | err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); | |
297 | mv88e6xxx_phy_page_put(chip, phy); | |
298 | } | |
299 | ||
300 | return err; | |
301 | } | |
302 | ||
303 | static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) | |
304 | { | |
305 | return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER, | |
306 | reg, val); | |
307 | } | |
308 | ||
309 | static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val) | |
310 | { | |
311 | return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER, | |
312 | reg, val); | |
313 | } | |
314 | ||
dc30c35b AL |
315 | static void mv88e6xxx_g1_irq_mask(struct irq_data *d) |
316 | { | |
317 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
318 | unsigned int n = d->hwirq; | |
319 | ||
320 | chip->g1_irq.masked |= (1 << n); | |
321 | } | |
322 | ||
323 | static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) | |
324 | { | |
325 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
326 | unsigned int n = d->hwirq; | |
327 | ||
328 | chip->g1_irq.masked &= ~(1 << n); | |
329 | } | |
330 | ||
331 | static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) | |
332 | { | |
333 | struct mv88e6xxx_chip *chip = dev_id; | |
334 | unsigned int nhandled = 0; | |
335 | unsigned int sub_irq; | |
336 | unsigned int n; | |
337 | u16 reg; | |
338 | int err; | |
339 | ||
340 | mutex_lock(&chip->reg_lock); | |
341 | err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®); | |
342 | mutex_unlock(&chip->reg_lock); | |
343 | ||
344 | if (err) | |
345 | goto out; | |
346 | ||
347 | for (n = 0; n < chip->g1_irq.nirqs; ++n) { | |
348 | if (reg & (1 << n)) { | |
349 | sub_irq = irq_find_mapping(chip->g1_irq.domain, n); | |
350 | handle_nested_irq(sub_irq); | |
351 | ++nhandled; | |
352 | } | |
353 | } | |
354 | out: | |
355 | return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); | |
356 | } | |
357 | ||
358 | static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) | |
359 | { | |
360 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
361 | ||
362 | mutex_lock(&chip->reg_lock); | |
363 | } | |
364 | ||
365 | static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) | |
366 | { | |
367 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
368 | u16 mask = GENMASK(chip->g1_irq.nirqs, 0); | |
369 | u16 reg; | |
370 | int err; | |
371 | ||
372 | err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®); | |
373 | if (err) | |
374 | goto out; | |
375 | ||
376 | reg &= ~mask; | |
377 | reg |= (~chip->g1_irq.masked & mask); | |
378 | ||
379 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg); | |
380 | if (err) | |
381 | goto out; | |
382 | ||
383 | out: | |
384 | mutex_unlock(&chip->reg_lock); | |
385 | } | |
386 | ||
387 | static struct irq_chip mv88e6xxx_g1_irq_chip = { | |
388 | .name = "mv88e6xxx-g1", | |
389 | .irq_mask = mv88e6xxx_g1_irq_mask, | |
390 | .irq_unmask = mv88e6xxx_g1_irq_unmask, | |
391 | .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, | |
392 | .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, | |
393 | }; | |
394 | ||
395 | static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, | |
396 | unsigned int irq, | |
397 | irq_hw_number_t hwirq) | |
398 | { | |
399 | struct mv88e6xxx_chip *chip = d->host_data; | |
400 | ||
401 | irq_set_chip_data(irq, d->host_data); | |
402 | irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); | |
403 | irq_set_noprobe(irq); | |
404 | ||
405 | return 0; | |
406 | } | |
407 | ||
408 | static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { | |
409 | .map = mv88e6xxx_g1_irq_domain_map, | |
410 | .xlate = irq_domain_xlate_twocell, | |
411 | }; | |
412 | ||
413 | static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) | |
414 | { | |
415 | int irq, virq; | |
3460a577 AL |
416 | u16 mask; |
417 | ||
418 | mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask); | |
419 | mask |= GENMASK(chip->g1_irq.nirqs, 0); | |
420 | mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); | |
421 | ||
422 | free_irq(chip->irq, chip); | |
dc30c35b AL |
423 | |
424 | for (irq = 0; irq < 16; irq++) { | |
a3db3d3a | 425 | virq = irq_find_mapping(chip->g1_irq.domain, irq); |
dc30c35b AL |
426 | irq_dispose_mapping(virq); |
427 | } | |
428 | ||
a3db3d3a | 429 | irq_domain_remove(chip->g1_irq.domain); |
dc30c35b AL |
430 | } |
431 | ||
432 | static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) | |
433 | { | |
3dd0ef05 AL |
434 | int err, irq, virq; |
435 | u16 reg, mask; | |
dc30c35b AL |
436 | |
437 | chip->g1_irq.nirqs = chip->info->g1_irqs; | |
438 | chip->g1_irq.domain = irq_domain_add_simple( | |
439 | NULL, chip->g1_irq.nirqs, 0, | |
440 | &mv88e6xxx_g1_irq_domain_ops, chip); | |
441 | if (!chip->g1_irq.domain) | |
442 | return -ENOMEM; | |
443 | ||
444 | for (irq = 0; irq < chip->g1_irq.nirqs; irq++) | |
445 | irq_create_mapping(chip->g1_irq.domain, irq); | |
446 | ||
447 | chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; | |
448 | chip->g1_irq.masked = ~0; | |
449 | ||
3dd0ef05 | 450 | err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask); |
dc30c35b | 451 | if (err) |
3dd0ef05 | 452 | goto out_mapping; |
dc30c35b | 453 | |
3dd0ef05 | 454 | mask &= ~GENMASK(chip->g1_irq.nirqs, 0); |
dc30c35b | 455 | |
3dd0ef05 | 456 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); |
dc30c35b | 457 | if (err) |
3dd0ef05 | 458 | goto out_disable; |
dc30c35b AL |
459 | |
460 | /* Reading the interrupt status clears (most of) them */ | |
461 | err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®); | |
462 | if (err) | |
3dd0ef05 | 463 | goto out_disable; |
dc30c35b AL |
464 | |
465 | err = request_threaded_irq(chip->irq, NULL, | |
466 | mv88e6xxx_g1_irq_thread_fn, | |
467 | IRQF_ONESHOT | IRQF_TRIGGER_FALLING, | |
468 | dev_name(chip->dev), chip); | |
469 | if (err) | |
3dd0ef05 | 470 | goto out_disable; |
dc30c35b AL |
471 | |
472 | return 0; | |
473 | ||
3dd0ef05 AL |
474 | out_disable: |
475 | mask |= GENMASK(chip->g1_irq.nirqs, 0); | |
476 | mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); | |
477 | ||
478 | out_mapping: | |
479 | for (irq = 0; irq < 16; irq++) { | |
480 | virq = irq_find_mapping(chip->g1_irq.domain, irq); | |
481 | irq_dispose_mapping(virq); | |
482 | } | |
483 | ||
484 | irq_domain_remove(chip->g1_irq.domain); | |
dc30c35b AL |
485 | |
486 | return err; | |
487 | } | |
488 | ||
ec561276 | 489 | int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) |
2d79af6e | 490 | { |
6441e669 | 491 | int i; |
2d79af6e | 492 | |
6441e669 | 493 | for (i = 0; i < 16; i++) { |
2d79af6e VD |
494 | u16 val; |
495 | int err; | |
496 | ||
497 | err = mv88e6xxx_read(chip, addr, reg, &val); | |
498 | if (err) | |
499 | return err; | |
500 | ||
501 | if (!(val & mask)) | |
502 | return 0; | |
503 | ||
504 | usleep_range(1000, 2000); | |
505 | } | |
506 | ||
30853553 | 507 | dev_err(chip->dev, "Timeout while waiting for switch\n"); |
2d79af6e VD |
508 | return -ETIMEDOUT; |
509 | } | |
510 | ||
f22ab641 | 511 | /* Indirect write to single pointer-data register with an Update bit */ |
ec561276 | 512 | int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) |
f22ab641 VD |
513 | { |
514 | u16 val; | |
0f02b4f7 | 515 | int err; |
f22ab641 VD |
516 | |
517 | /* Wait until the previous operation is completed */ | |
0f02b4f7 AL |
518 | err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); |
519 | if (err) | |
520 | return err; | |
f22ab641 VD |
521 | |
522 | /* Set the Update bit to trigger a write operation */ | |
523 | val = BIT(15) | update; | |
524 | ||
525 | return mv88e6xxx_write(chip, addr, reg, val); | |
526 | } | |
527 | ||
a935c052 | 528 | static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip) |
914b32f6 VD |
529 | { |
530 | u16 val; | |
a935c052 | 531 | int i, err; |
914b32f6 | 532 | |
a935c052 | 533 | err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val); |
914b32f6 VD |
534 | if (err) |
535 | return err; | |
536 | ||
a935c052 VD |
537 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, |
538 | val & ~GLOBAL_CONTROL_PPU_ENABLE); | |
539 | if (err) | |
540 | return err; | |
2e5f0320 | 541 | |
6441e669 | 542 | for (i = 0; i < 16; i++) { |
a935c052 VD |
543 | err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val); |
544 | if (err) | |
545 | return err; | |
48ace4ef | 546 | |
19b2f97e | 547 | usleep_range(1000, 2000); |
a935c052 | 548 | if ((val & GLOBAL_STATUS_PPU_MASK) != GLOBAL_STATUS_PPU_POLLING) |
85686581 | 549 | return 0; |
2e5f0320 LB |
550 | } |
551 | ||
552 | return -ETIMEDOUT; | |
553 | } | |
554 | ||
fad09c73 | 555 | static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip) |
2e5f0320 | 556 | { |
a935c052 VD |
557 | u16 val; |
558 | int i, err; | |
2e5f0320 | 559 | |
a935c052 VD |
560 | err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val); |
561 | if (err) | |
562 | return err; | |
48ace4ef | 563 | |
a935c052 VD |
564 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, |
565 | val | GLOBAL_CONTROL_PPU_ENABLE); | |
48ace4ef AL |
566 | if (err) |
567 | return err; | |
2e5f0320 | 568 | |
6441e669 | 569 | for (i = 0; i < 16; i++) { |
a935c052 VD |
570 | err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val); |
571 | if (err) | |
572 | return err; | |
48ace4ef | 573 | |
19b2f97e | 574 | usleep_range(1000, 2000); |
a935c052 | 575 | if ((val & GLOBAL_STATUS_PPU_MASK) == GLOBAL_STATUS_PPU_POLLING) |
85686581 | 576 | return 0; |
2e5f0320 LB |
577 | } |
578 | ||
579 | return -ETIMEDOUT; | |
580 | } | |
581 | ||
582 | static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) | |
583 | { | |
fad09c73 | 584 | struct mv88e6xxx_chip *chip; |
2e5f0320 | 585 | |
fad09c73 | 586 | chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work); |
762eb67b | 587 | |
fad09c73 | 588 | mutex_lock(&chip->reg_lock); |
762eb67b | 589 | |
fad09c73 VD |
590 | if (mutex_trylock(&chip->ppu_mutex)) { |
591 | if (mv88e6xxx_ppu_enable(chip) == 0) | |
592 | chip->ppu_disabled = 0; | |
593 | mutex_unlock(&chip->ppu_mutex); | |
2e5f0320 | 594 | } |
762eb67b | 595 | |
fad09c73 | 596 | mutex_unlock(&chip->reg_lock); |
2e5f0320 LB |
597 | } |
598 | ||
599 | static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) | |
600 | { | |
fad09c73 | 601 | struct mv88e6xxx_chip *chip = (void *)_ps; |
2e5f0320 | 602 | |
fad09c73 | 603 | schedule_work(&chip->ppu_work); |
2e5f0320 LB |
604 | } |
605 | ||
fad09c73 | 606 | static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip) |
2e5f0320 | 607 | { |
2e5f0320 LB |
608 | int ret; |
609 | ||
fad09c73 | 610 | mutex_lock(&chip->ppu_mutex); |
2e5f0320 | 611 | |
3675c8d7 | 612 | /* If the PHY polling unit is enabled, disable it so that |
2e5f0320 LB |
613 | * we can access the PHY registers. If it was already |
614 | * disabled, cancel the timer that is going to re-enable | |
615 | * it. | |
616 | */ | |
fad09c73 VD |
617 | if (!chip->ppu_disabled) { |
618 | ret = mv88e6xxx_ppu_disable(chip); | |
85686581 | 619 | if (ret < 0) { |
fad09c73 | 620 | mutex_unlock(&chip->ppu_mutex); |
85686581 BG |
621 | return ret; |
622 | } | |
fad09c73 | 623 | chip->ppu_disabled = 1; |
2e5f0320 | 624 | } else { |
fad09c73 | 625 | del_timer(&chip->ppu_timer); |
85686581 | 626 | ret = 0; |
2e5f0320 LB |
627 | } |
628 | ||
629 | return ret; | |
630 | } | |
631 | ||
fad09c73 | 632 | static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip) |
2e5f0320 | 633 | { |
3675c8d7 | 634 | /* Schedule a timer to re-enable the PHY polling unit. */ |
fad09c73 VD |
635 | mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10)); |
636 | mutex_unlock(&chip->ppu_mutex); | |
2e5f0320 LB |
637 | } |
638 | ||
fad09c73 | 639 | static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip) |
2e5f0320 | 640 | { |
fad09c73 VD |
641 | mutex_init(&chip->ppu_mutex); |
642 | INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work); | |
68497a87 WY |
643 | setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer, |
644 | (unsigned long)chip); | |
2e5f0320 LB |
645 | } |
646 | ||
930188ce AL |
647 | static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip) |
648 | { | |
649 | del_timer_sync(&chip->ppu_timer); | |
650 | } | |
651 | ||
e57e5e77 VD |
652 | static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr, |
653 | int reg, u16 *val) | |
2e5f0320 | 654 | { |
e57e5e77 | 655 | int err; |
2e5f0320 | 656 | |
e57e5e77 VD |
657 | err = mv88e6xxx_ppu_access_get(chip); |
658 | if (!err) { | |
659 | err = mv88e6xxx_read(chip, addr, reg, val); | |
fad09c73 | 660 | mv88e6xxx_ppu_access_put(chip); |
2e5f0320 LB |
661 | } |
662 | ||
e57e5e77 | 663 | return err; |
2e5f0320 LB |
664 | } |
665 | ||
e57e5e77 VD |
666 | static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr, |
667 | int reg, u16 val) | |
2e5f0320 | 668 | { |
e57e5e77 | 669 | int err; |
2e5f0320 | 670 | |
e57e5e77 VD |
671 | err = mv88e6xxx_ppu_access_get(chip); |
672 | if (!err) { | |
673 | err = mv88e6xxx_write(chip, addr, reg, val); | |
fad09c73 | 674 | mv88e6xxx_ppu_access_put(chip); |
2e5f0320 LB |
675 | } |
676 | ||
e57e5e77 | 677 | return err; |
2e5f0320 | 678 | } |
2e5f0320 | 679 | |
fad09c73 | 680 | static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip) |
54d792f2 | 681 | { |
fad09c73 | 682 | return chip->info->family == MV88E6XXX_FAMILY_6065; |
54d792f2 AL |
683 | } |
684 | ||
fad09c73 | 685 | static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip) |
54d792f2 | 686 | { |
fad09c73 | 687 | return chip->info->family == MV88E6XXX_FAMILY_6095; |
54d792f2 AL |
688 | } |
689 | ||
fad09c73 | 690 | static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip) |
54d792f2 | 691 | { |
fad09c73 | 692 | return chip->info->family == MV88E6XXX_FAMILY_6097; |
54d792f2 AL |
693 | } |
694 | ||
fad09c73 | 695 | static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip) |
54d792f2 | 696 | { |
fad09c73 | 697 | return chip->info->family == MV88E6XXX_FAMILY_6165; |
54d792f2 AL |
698 | } |
699 | ||
fad09c73 | 700 | static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip) |
54d792f2 | 701 | { |
fad09c73 | 702 | return chip->info->family == MV88E6XXX_FAMILY_6185; |
54d792f2 AL |
703 | } |
704 | ||
fad09c73 | 705 | static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip) |
7c3d0d67 | 706 | { |
fad09c73 | 707 | return chip->info->family == MV88E6XXX_FAMILY_6320; |
7c3d0d67 AK |
708 | } |
709 | ||
fad09c73 | 710 | static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip) |
54d792f2 | 711 | { |
fad09c73 | 712 | return chip->info->family == MV88E6XXX_FAMILY_6351; |
54d792f2 AL |
713 | } |
714 | ||
fad09c73 | 715 | static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip) |
f3a8b6b6 | 716 | { |
fad09c73 | 717 | return chip->info->family == MV88E6XXX_FAMILY_6352; |
f3a8b6b6 AL |
718 | } |
719 | ||
d78343d2 VD |
720 | static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, |
721 | int link, int speed, int duplex, | |
722 | phy_interface_t mode) | |
723 | { | |
724 | int err; | |
725 | ||
726 | if (!chip->info->ops->port_set_link) | |
727 | return 0; | |
728 | ||
729 | /* Port's MAC control must not be changed unless the link is down */ | |
730 | err = chip->info->ops->port_set_link(chip, port, 0); | |
731 | if (err) | |
732 | return err; | |
733 | ||
734 | if (chip->info->ops->port_set_speed) { | |
735 | err = chip->info->ops->port_set_speed(chip, port, speed); | |
736 | if (err && err != -EOPNOTSUPP) | |
737 | goto restore_link; | |
738 | } | |
739 | ||
740 | if (chip->info->ops->port_set_duplex) { | |
741 | err = chip->info->ops->port_set_duplex(chip, port, duplex); | |
742 | if (err && err != -EOPNOTSUPP) | |
743 | goto restore_link; | |
744 | } | |
745 | ||
746 | if (chip->info->ops->port_set_rgmii_delay) { | |
747 | err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); | |
748 | if (err && err != -EOPNOTSUPP) | |
749 | goto restore_link; | |
750 | } | |
751 | ||
752 | err = 0; | |
753 | restore_link: | |
754 | if (chip->info->ops->port_set_link(chip, port, link)) | |
755 | netdev_err(chip->ds->ports[port].netdev, | |
756 | "failed to restore MAC's link\n"); | |
757 | ||
758 | return err; | |
759 | } | |
760 | ||
dea87024 AL |
761 | /* We expect the switch to perform auto negotiation if there is a real |
762 | * phy. However, in the case of a fixed link phy, we force the port | |
763 | * settings from the fixed link settings. | |
764 | */ | |
f81ec90f VD |
765 | static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, |
766 | struct phy_device *phydev) | |
dea87024 | 767 | { |
04bed143 | 768 | struct mv88e6xxx_chip *chip = ds->priv; |
0e7b9925 | 769 | int err; |
dea87024 AL |
770 | |
771 | if (!phy_is_pseudo_fixed_link(phydev)) | |
772 | return; | |
773 | ||
fad09c73 | 774 | mutex_lock(&chip->reg_lock); |
d78343d2 VD |
775 | err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, |
776 | phydev->duplex, phydev->interface); | |
fad09c73 | 777 | mutex_unlock(&chip->reg_lock); |
d78343d2 VD |
778 | |
779 | if (err && err != -EOPNOTSUPP) | |
780 | netdev_err(ds->ports[port].netdev, "failed to configure MAC\n"); | |
dea87024 AL |
781 | } |
782 | ||
fad09c73 | 783 | static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip) |
91da11f8 | 784 | { |
a935c052 VD |
785 | u16 val; |
786 | int i, err; | |
91da11f8 LB |
787 | |
788 | for (i = 0; i < 10; i++) { | |
a935c052 | 789 | err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_OP, &val); |
096eea0f AL |
790 | if (err) |
791 | return err; | |
792 | ||
a935c052 | 793 | if ((val & GLOBAL_STATS_OP_BUSY) == 0) |
91da11f8 LB |
794 | return 0; |
795 | } | |
796 | ||
797 | return -ETIMEDOUT; | |
798 | } | |
799 | ||
a605a0fe | 800 | static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) |
91da11f8 | 801 | { |
a605a0fe AL |
802 | if (!chip->info->ops->stats_snapshot) |
803 | return -EOPNOTSUPP; | |
91da11f8 | 804 | |
a605a0fe | 805 | return chip->info->ops->stats_snapshot(chip, port); |
91da11f8 LB |
806 | } |
807 | ||
fad09c73 | 808 | static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip, |
158bc065 | 809 | int stat, u32 *val) |
91da11f8 | 810 | { |
a935c052 VD |
811 | u32 value; |
812 | u16 reg; | |
813 | int err; | |
91da11f8 LB |
814 | |
815 | *val = 0; | |
816 | ||
a935c052 VD |
817 | err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP, |
818 | GLOBAL_STATS_OP_READ_CAPTURED | | |
819 | GLOBAL_STATS_OP_HIST_RX_TX | stat); | |
820 | if (err) | |
91da11f8 LB |
821 | return; |
822 | ||
a935c052 VD |
823 | err = _mv88e6xxx_stats_wait(chip); |
824 | if (err) | |
91da11f8 LB |
825 | return; |
826 | ||
a935c052 VD |
827 | err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_32, ®); |
828 | if (err) | |
91da11f8 LB |
829 | return; |
830 | ||
a935c052 | 831 | value = reg << 16; |
91da11f8 | 832 | |
a935c052 VD |
833 | err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_01, ®); |
834 | if (err) | |
91da11f8 LB |
835 | return; |
836 | ||
a935c052 | 837 | *val = value | reg; |
91da11f8 LB |
838 | } |
839 | ||
e413e7e1 | 840 | static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { |
f5e2ed02 AL |
841 | { "in_good_octets", 8, 0x00, BANK0, }, |
842 | { "in_bad_octets", 4, 0x02, BANK0, }, | |
843 | { "in_unicast", 4, 0x04, BANK0, }, | |
844 | { "in_broadcasts", 4, 0x06, BANK0, }, | |
845 | { "in_multicasts", 4, 0x07, BANK0, }, | |
846 | { "in_pause", 4, 0x16, BANK0, }, | |
847 | { "in_undersize", 4, 0x18, BANK0, }, | |
848 | { "in_fragments", 4, 0x19, BANK0, }, | |
849 | { "in_oversize", 4, 0x1a, BANK0, }, | |
850 | { "in_jabber", 4, 0x1b, BANK0, }, | |
851 | { "in_rx_error", 4, 0x1c, BANK0, }, | |
852 | { "in_fcs_error", 4, 0x1d, BANK0, }, | |
853 | { "out_octets", 8, 0x0e, BANK0, }, | |
854 | { "out_unicast", 4, 0x10, BANK0, }, | |
855 | { "out_broadcasts", 4, 0x13, BANK0, }, | |
856 | { "out_multicasts", 4, 0x12, BANK0, }, | |
857 | { "out_pause", 4, 0x15, BANK0, }, | |
858 | { "excessive", 4, 0x11, BANK0, }, | |
859 | { "collisions", 4, 0x1e, BANK0, }, | |
860 | { "deferred", 4, 0x05, BANK0, }, | |
861 | { "single", 4, 0x14, BANK0, }, | |
862 | { "multiple", 4, 0x17, BANK0, }, | |
863 | { "out_fcs_error", 4, 0x03, BANK0, }, | |
864 | { "late", 4, 0x1f, BANK0, }, | |
865 | { "hist_64bytes", 4, 0x08, BANK0, }, | |
866 | { "hist_65_127bytes", 4, 0x09, BANK0, }, | |
867 | { "hist_128_255bytes", 4, 0x0a, BANK0, }, | |
868 | { "hist_256_511bytes", 4, 0x0b, BANK0, }, | |
869 | { "hist_512_1023bytes", 4, 0x0c, BANK0, }, | |
870 | { "hist_1024_max_bytes", 4, 0x0d, BANK0, }, | |
871 | { "sw_in_discards", 4, 0x10, PORT, }, | |
872 | { "sw_in_filtered", 2, 0x12, PORT, }, | |
873 | { "sw_out_filtered", 2, 0x13, PORT, }, | |
874 | { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
875 | { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
876 | { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
877 | { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
878 | { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
879 | { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
880 | { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
881 | { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
882 | { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
883 | { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
884 | { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
885 | { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
886 | { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
887 | { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
888 | { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
889 | { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
890 | { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
891 | { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
892 | { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
893 | { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
894 | { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
895 | { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
896 | { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
897 | { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
898 | { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
899 | { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
e413e7e1 AL |
900 | }; |
901 | ||
fad09c73 | 902 | static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip, |
f5e2ed02 | 903 | struct mv88e6xxx_hw_stat *stat) |
e413e7e1 | 904 | { |
f5e2ed02 AL |
905 | switch (stat->type) { |
906 | case BANK0: | |
e413e7e1 | 907 | return true; |
f5e2ed02 | 908 | case BANK1: |
fad09c73 | 909 | return mv88e6xxx_6320_family(chip); |
f5e2ed02 | 910 | case PORT: |
fad09c73 VD |
911 | return mv88e6xxx_6095_family(chip) || |
912 | mv88e6xxx_6185_family(chip) || | |
913 | mv88e6xxx_6097_family(chip) || | |
914 | mv88e6xxx_6165_family(chip) || | |
915 | mv88e6xxx_6351_family(chip) || | |
916 | mv88e6xxx_6352_family(chip); | |
91da11f8 | 917 | } |
f5e2ed02 | 918 | return false; |
91da11f8 LB |
919 | } |
920 | ||
fad09c73 | 921 | static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, |
f5e2ed02 | 922 | struct mv88e6xxx_hw_stat *s, |
80c4627b AL |
923 | int port) |
924 | { | |
80c4627b AL |
925 | u32 low; |
926 | u32 high = 0; | |
0e7b9925 AL |
927 | int err; |
928 | u16 reg; | |
80c4627b AL |
929 | u64 value; |
930 | ||
f5e2ed02 AL |
931 | switch (s->type) { |
932 | case PORT: | |
0e7b9925 AL |
933 | err = mv88e6xxx_port_read(chip, port, s->reg, ®); |
934 | if (err) | |
80c4627b AL |
935 | return UINT64_MAX; |
936 | ||
0e7b9925 | 937 | low = reg; |
80c4627b | 938 | if (s->sizeof_stat == 4) { |
0e7b9925 AL |
939 | err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); |
940 | if (err) | |
80c4627b | 941 | return UINT64_MAX; |
0e7b9925 | 942 | high = reg; |
80c4627b | 943 | } |
f5e2ed02 AL |
944 | break; |
945 | case BANK0: | |
946 | case BANK1: | |
fad09c73 | 947 | _mv88e6xxx_stats_read(chip, s->reg, &low); |
80c4627b | 948 | if (s->sizeof_stat == 8) |
fad09c73 | 949 | _mv88e6xxx_stats_read(chip, s->reg + 1, &high); |
80c4627b AL |
950 | } |
951 | value = (((u64)high) << 16) | low; | |
952 | return value; | |
953 | } | |
954 | ||
f81ec90f VD |
955 | static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, |
956 | uint8_t *data) | |
91da11f8 | 957 | { |
04bed143 | 958 | struct mv88e6xxx_chip *chip = ds->priv; |
f5e2ed02 AL |
959 | struct mv88e6xxx_hw_stat *stat; |
960 | int i, j; | |
91da11f8 | 961 | |
f5e2ed02 AL |
962 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { |
963 | stat = &mv88e6xxx_hw_stats[i]; | |
fad09c73 | 964 | if (mv88e6xxx_has_stat(chip, stat)) { |
f5e2ed02 AL |
965 | memcpy(data + j * ETH_GSTRING_LEN, stat->string, |
966 | ETH_GSTRING_LEN); | |
967 | j++; | |
968 | } | |
91da11f8 | 969 | } |
e413e7e1 AL |
970 | } |
971 | ||
f81ec90f | 972 | static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) |
e413e7e1 | 973 | { |
04bed143 | 974 | struct mv88e6xxx_chip *chip = ds->priv; |
f5e2ed02 AL |
975 | struct mv88e6xxx_hw_stat *stat; |
976 | int i, j; | |
977 | ||
978 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { | |
979 | stat = &mv88e6xxx_hw_stats[i]; | |
fad09c73 | 980 | if (mv88e6xxx_has_stat(chip, stat)) |
f5e2ed02 AL |
981 | j++; |
982 | } | |
983 | return j; | |
e413e7e1 AL |
984 | } |
985 | ||
f81ec90f VD |
986 | static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, |
987 | uint64_t *data) | |
e413e7e1 | 988 | { |
04bed143 | 989 | struct mv88e6xxx_chip *chip = ds->priv; |
f5e2ed02 AL |
990 | struct mv88e6xxx_hw_stat *stat; |
991 | int ret; | |
992 | int i, j; | |
993 | ||
fad09c73 | 994 | mutex_lock(&chip->reg_lock); |
f5e2ed02 | 995 | |
a605a0fe | 996 | ret = mv88e6xxx_stats_snapshot(chip, port); |
f5e2ed02 | 997 | if (ret < 0) { |
fad09c73 | 998 | mutex_unlock(&chip->reg_lock); |
f5e2ed02 AL |
999 | return; |
1000 | } | |
1001 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { | |
1002 | stat = &mv88e6xxx_hw_stats[i]; | |
fad09c73 VD |
1003 | if (mv88e6xxx_has_stat(chip, stat)) { |
1004 | data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port); | |
f5e2ed02 AL |
1005 | j++; |
1006 | } | |
1007 | } | |
1008 | ||
fad09c73 | 1009 | mutex_unlock(&chip->reg_lock); |
e413e7e1 AL |
1010 | } |
1011 | ||
de227387 AL |
1012 | static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip) |
1013 | { | |
1014 | if (chip->info->ops->stats_set_histogram) | |
1015 | return chip->info->ops->stats_set_histogram(chip); | |
1016 | ||
1017 | return 0; | |
1018 | } | |
1019 | ||
f81ec90f | 1020 | static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) |
a1ab91f3 GR |
1021 | { |
1022 | return 32 * sizeof(u16); | |
1023 | } | |
1024 | ||
f81ec90f VD |
1025 | static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, |
1026 | struct ethtool_regs *regs, void *_p) | |
a1ab91f3 | 1027 | { |
04bed143 | 1028 | struct mv88e6xxx_chip *chip = ds->priv; |
0e7b9925 AL |
1029 | int err; |
1030 | u16 reg; | |
a1ab91f3 GR |
1031 | u16 *p = _p; |
1032 | int i; | |
1033 | ||
1034 | regs->version = 0; | |
1035 | ||
1036 | memset(p, 0xff, 32 * sizeof(u16)); | |
1037 | ||
fad09c73 | 1038 | mutex_lock(&chip->reg_lock); |
23062513 | 1039 | |
a1ab91f3 | 1040 | for (i = 0; i < 32; i++) { |
a1ab91f3 | 1041 | |
0e7b9925 AL |
1042 | err = mv88e6xxx_port_read(chip, port, i, ®); |
1043 | if (!err) | |
1044 | p[i] = reg; | |
a1ab91f3 | 1045 | } |
23062513 | 1046 | |
fad09c73 | 1047 | mutex_unlock(&chip->reg_lock); |
a1ab91f3 GR |
1048 | } |
1049 | ||
fad09c73 | 1050 | static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip) |
facd95b2 | 1051 | { |
a935c052 | 1052 | return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY); |
facd95b2 GR |
1053 | } |
1054 | ||
f81ec90f VD |
1055 | static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, |
1056 | struct ethtool_eee *e) | |
11b3b45d | 1057 | { |
04bed143 | 1058 | struct mv88e6xxx_chip *chip = ds->priv; |
9c93829c VD |
1059 | u16 reg; |
1060 | int err; | |
11b3b45d | 1061 | |
fad09c73 | 1062 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) |
aadbdb8a VD |
1063 | return -EOPNOTSUPP; |
1064 | ||
fad09c73 | 1065 | mutex_lock(&chip->reg_lock); |
2f40c698 | 1066 | |
9c93829c VD |
1067 | err = mv88e6xxx_phy_read(chip, port, 16, ®); |
1068 | if (err) | |
2f40c698 | 1069 | goto out; |
11b3b45d GR |
1070 | |
1071 | e->eee_enabled = !!(reg & 0x0200); | |
1072 | e->tx_lpi_enabled = !!(reg & 0x0100); | |
1073 | ||
0e7b9925 | 1074 | err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®); |
9c93829c | 1075 | if (err) |
2f40c698 | 1076 | goto out; |
11b3b45d | 1077 | |
cca8b133 | 1078 | e->eee_active = !!(reg & PORT_STATUS_EEE); |
2f40c698 | 1079 | out: |
fad09c73 | 1080 | mutex_unlock(&chip->reg_lock); |
9c93829c VD |
1081 | |
1082 | return err; | |
11b3b45d GR |
1083 | } |
1084 | ||
f81ec90f VD |
1085 | static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, |
1086 | struct phy_device *phydev, struct ethtool_eee *e) | |
11b3b45d | 1087 | { |
04bed143 | 1088 | struct mv88e6xxx_chip *chip = ds->priv; |
9c93829c VD |
1089 | u16 reg; |
1090 | int err; | |
11b3b45d | 1091 | |
fad09c73 | 1092 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) |
aadbdb8a VD |
1093 | return -EOPNOTSUPP; |
1094 | ||
fad09c73 | 1095 | mutex_lock(&chip->reg_lock); |
11b3b45d | 1096 | |
9c93829c VD |
1097 | err = mv88e6xxx_phy_read(chip, port, 16, ®); |
1098 | if (err) | |
2f40c698 AL |
1099 | goto out; |
1100 | ||
9c93829c | 1101 | reg &= ~0x0300; |
2f40c698 AL |
1102 | if (e->eee_enabled) |
1103 | reg |= 0x0200; | |
1104 | if (e->tx_lpi_enabled) | |
1105 | reg |= 0x0100; | |
1106 | ||
9c93829c | 1107 | err = mv88e6xxx_phy_write(chip, port, 16, reg); |
2f40c698 | 1108 | out: |
fad09c73 | 1109 | mutex_unlock(&chip->reg_lock); |
2f40c698 | 1110 | |
9c93829c | 1111 | return err; |
11b3b45d GR |
1112 | } |
1113 | ||
fad09c73 | 1114 | static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd) |
facd95b2 | 1115 | { |
a935c052 VD |
1116 | u16 val; |
1117 | int err; | |
facd95b2 | 1118 | |
6dc10bbc | 1119 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) { |
a935c052 VD |
1120 | err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid); |
1121 | if (err) | |
1122 | return err; | |
fad09c73 | 1123 | } else if (mv88e6xxx_num_databases(chip) == 256) { |
11ea809f | 1124 | /* ATU DBNum[7:4] are located in ATU Control 15:12 */ |
a935c052 VD |
1125 | err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val); |
1126 | if (err) | |
1127 | return err; | |
11ea809f | 1128 | |
a935c052 VD |
1129 | err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, |
1130 | (val & 0xfff) | ((fid << 8) & 0xf000)); | |
1131 | if (err) | |
1132 | return err; | |
11ea809f VD |
1133 | |
1134 | /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ | |
1135 | cmd |= fid & 0xf; | |
b426e5f7 VD |
1136 | } |
1137 | ||
a935c052 VD |
1138 | err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd); |
1139 | if (err) | |
1140 | return err; | |
facd95b2 | 1141 | |
fad09c73 | 1142 | return _mv88e6xxx_atu_wait(chip); |
facd95b2 GR |
1143 | } |
1144 | ||
fad09c73 | 1145 | static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip, |
37705b73 VD |
1146 | struct mv88e6xxx_atu_entry *entry) |
1147 | { | |
1148 | u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK; | |
1149 | ||
1150 | if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) { | |
1151 | unsigned int mask, shift; | |
1152 | ||
1153 | if (entry->trunk) { | |
1154 | data |= GLOBAL_ATU_DATA_TRUNK; | |
1155 | mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; | |
1156 | shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; | |
1157 | } else { | |
1158 | mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; | |
1159 | shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; | |
1160 | } | |
1161 | ||
1162 | data |= (entry->portv_trunkid << shift) & mask; | |
1163 | } | |
1164 | ||
a935c052 | 1165 | return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data); |
37705b73 VD |
1166 | } |
1167 | ||
fad09c73 | 1168 | static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip, |
7fb5e755 VD |
1169 | struct mv88e6xxx_atu_entry *entry, |
1170 | bool static_too) | |
facd95b2 | 1171 | { |
7fb5e755 VD |
1172 | int op; |
1173 | int err; | |
facd95b2 | 1174 | |
fad09c73 | 1175 | err = _mv88e6xxx_atu_wait(chip); |
7fb5e755 VD |
1176 | if (err) |
1177 | return err; | |
facd95b2 | 1178 | |
fad09c73 | 1179 | err = _mv88e6xxx_atu_data_write(chip, entry); |
7fb5e755 VD |
1180 | if (err) |
1181 | return err; | |
1182 | ||
1183 | if (entry->fid) { | |
7fb5e755 VD |
1184 | op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB : |
1185 | GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; | |
1186 | } else { | |
1187 | op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL : | |
1188 | GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC; | |
1189 | } | |
1190 | ||
fad09c73 | 1191 | return _mv88e6xxx_atu_cmd(chip, entry->fid, op); |
7fb5e755 VD |
1192 | } |
1193 | ||
fad09c73 | 1194 | static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip, |
158bc065 | 1195 | u16 fid, bool static_too) |
7fb5e755 VD |
1196 | { |
1197 | struct mv88e6xxx_atu_entry entry = { | |
1198 | .fid = fid, | |
1199 | .state = 0, /* EntryState bits must be 0 */ | |
1200 | }; | |
70cc99d1 | 1201 | |
fad09c73 | 1202 | return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); |
7fb5e755 VD |
1203 | } |
1204 | ||
fad09c73 | 1205 | static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid, |
158bc065 | 1206 | int from_port, int to_port, bool static_too) |
9f4d55d2 VD |
1207 | { |
1208 | struct mv88e6xxx_atu_entry entry = { | |
1209 | .trunk = false, | |
1210 | .fid = fid, | |
1211 | }; | |
1212 | ||
1213 | /* EntryState bits must be 0xF */ | |
1214 | entry.state = GLOBAL_ATU_DATA_STATE_MASK; | |
1215 | ||
1216 | /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */ | |
1217 | entry.portv_trunkid = (to_port & 0x0f) << 4; | |
1218 | entry.portv_trunkid |= from_port & 0x0f; | |
1219 | ||
fad09c73 | 1220 | return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); |
9f4d55d2 VD |
1221 | } |
1222 | ||
fad09c73 | 1223 | static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, |
158bc065 | 1224 | int port, bool static_too) |
9f4d55d2 VD |
1225 | { |
1226 | /* Destination port 0xF means remove the entries */ | |
fad09c73 | 1227 | return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too); |
9f4d55d2 VD |
1228 | } |
1229 | ||
fad09c73 | 1230 | static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port) |
facd95b2 | 1231 | { |
fad09c73 | 1232 | struct net_device *bridge = chip->ports[port].bridge_dev; |
fad09c73 | 1233 | struct dsa_switch *ds = chip->ds; |
b7666efe | 1234 | u16 output_ports = 0; |
b7666efe VD |
1235 | int i; |
1236 | ||
1237 | /* allow CPU port or DSA link(s) to send frames to every port */ | |
1238 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { | |
5a7921f4 | 1239 | output_ports = ~0; |
b7666efe | 1240 | } else { |
370b4ffb | 1241 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
b7666efe | 1242 | /* allow sending frames to every group member */ |
fad09c73 | 1243 | if (bridge && chip->ports[i].bridge_dev == bridge) |
b7666efe VD |
1244 | output_ports |= BIT(i); |
1245 | ||
1246 | /* allow sending frames to CPU port and DSA link(s) */ | |
1247 | if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) | |
1248 | output_ports |= BIT(i); | |
1249 | } | |
1250 | } | |
1251 | ||
1252 | /* prevent frames from going back out of the port they came in on */ | |
1253 | output_ports &= ~BIT(port); | |
facd95b2 | 1254 | |
5a7921f4 | 1255 | return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); |
facd95b2 GR |
1256 | } |
1257 | ||
f81ec90f VD |
1258 | static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, |
1259 | u8 state) | |
facd95b2 | 1260 | { |
04bed143 | 1261 | struct mv88e6xxx_chip *chip = ds->priv; |
facd95b2 | 1262 | int stp_state; |
553eb544 | 1263 | int err; |
facd95b2 GR |
1264 | |
1265 | switch (state) { | |
1266 | case BR_STATE_DISABLED: | |
cca8b133 | 1267 | stp_state = PORT_CONTROL_STATE_DISABLED; |
facd95b2 GR |
1268 | break; |
1269 | case BR_STATE_BLOCKING: | |
1270 | case BR_STATE_LISTENING: | |
cca8b133 | 1271 | stp_state = PORT_CONTROL_STATE_BLOCKING; |
facd95b2 GR |
1272 | break; |
1273 | case BR_STATE_LEARNING: | |
cca8b133 | 1274 | stp_state = PORT_CONTROL_STATE_LEARNING; |
facd95b2 GR |
1275 | break; |
1276 | case BR_STATE_FORWARDING: | |
1277 | default: | |
cca8b133 | 1278 | stp_state = PORT_CONTROL_STATE_FORWARDING; |
facd95b2 GR |
1279 | break; |
1280 | } | |
1281 | ||
fad09c73 | 1282 | mutex_lock(&chip->reg_lock); |
e28def33 | 1283 | err = mv88e6xxx_port_set_state(chip, port, stp_state); |
fad09c73 | 1284 | mutex_unlock(&chip->reg_lock); |
553eb544 VD |
1285 | |
1286 | if (err) | |
e28def33 | 1287 | netdev_err(ds->ports[port].netdev, "failed to update state\n"); |
facd95b2 GR |
1288 | } |
1289 | ||
749efcb8 VD |
1290 | static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) |
1291 | { | |
1292 | struct mv88e6xxx_chip *chip = ds->priv; | |
1293 | int err; | |
1294 | ||
1295 | mutex_lock(&chip->reg_lock); | |
1296 | err = _mv88e6xxx_atu_remove(chip, 0, port, false); | |
1297 | mutex_unlock(&chip->reg_lock); | |
1298 | ||
1299 | if (err) | |
1300 | netdev_err(ds->ports[port].netdev, "failed to flush ATU\n"); | |
1301 | } | |
1302 | ||
fad09c73 | 1303 | static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip) |
6b17e864 | 1304 | { |
a935c052 | 1305 | return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY); |
6b17e864 VD |
1306 | } |
1307 | ||
fad09c73 | 1308 | static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op) |
6b17e864 | 1309 | { |
a935c052 | 1310 | int err; |
6b17e864 | 1311 | |
a935c052 VD |
1312 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op); |
1313 | if (err) | |
1314 | return err; | |
6b17e864 | 1315 | |
fad09c73 | 1316 | return _mv88e6xxx_vtu_wait(chip); |
6b17e864 VD |
1317 | } |
1318 | ||
fad09c73 | 1319 | static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip) |
6b17e864 VD |
1320 | { |
1321 | int ret; | |
1322 | ||
fad09c73 | 1323 | ret = _mv88e6xxx_vtu_wait(chip); |
6b17e864 VD |
1324 | if (ret < 0) |
1325 | return ret; | |
1326 | ||
fad09c73 | 1327 | return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL); |
6b17e864 VD |
1328 | } |
1329 | ||
fad09c73 | 1330 | static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1331 | struct mv88e6xxx_vtu_entry *entry, |
b8fee957 VD |
1332 | unsigned int nibble_offset) |
1333 | { | |
b8fee957 | 1334 | u16 regs[3]; |
a935c052 | 1335 | int i, err; |
b8fee957 VD |
1336 | |
1337 | for (i = 0; i < 3; ++i) { | |
a935c052 | 1338 | u16 *reg = ®s[i]; |
b8fee957 | 1339 | |
a935c052 VD |
1340 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg); |
1341 | if (err) | |
1342 | return err; | |
b8fee957 VD |
1343 | } |
1344 | ||
370b4ffb | 1345 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
b8fee957 VD |
1346 | unsigned int shift = (i % 4) * 4 + nibble_offset; |
1347 | u16 reg = regs[i / 4]; | |
1348 | ||
1349 | entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK; | |
1350 | } | |
1351 | ||
1352 | return 0; | |
1353 | } | |
1354 | ||
fad09c73 | 1355 | static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1356 | struct mv88e6xxx_vtu_entry *entry) |
15d7d7d4 | 1357 | { |
fad09c73 | 1358 | return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0); |
15d7d7d4 VD |
1359 | } |
1360 | ||
fad09c73 | 1361 | static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1362 | struct mv88e6xxx_vtu_entry *entry) |
15d7d7d4 | 1363 | { |
fad09c73 | 1364 | return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2); |
15d7d7d4 VD |
1365 | } |
1366 | ||
fad09c73 | 1367 | static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1368 | struct mv88e6xxx_vtu_entry *entry, |
7dad08d7 VD |
1369 | unsigned int nibble_offset) |
1370 | { | |
7dad08d7 | 1371 | u16 regs[3] = { 0 }; |
a935c052 | 1372 | int i, err; |
7dad08d7 | 1373 | |
370b4ffb | 1374 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
7dad08d7 VD |
1375 | unsigned int shift = (i % 4) * 4 + nibble_offset; |
1376 | u8 data = entry->data[i]; | |
1377 | ||
1378 | regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift; | |
1379 | } | |
1380 | ||
1381 | for (i = 0; i < 3; ++i) { | |
a935c052 VD |
1382 | u16 reg = regs[i]; |
1383 | ||
1384 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg); | |
1385 | if (err) | |
1386 | return err; | |
7dad08d7 VD |
1387 | } |
1388 | ||
1389 | return 0; | |
1390 | } | |
1391 | ||
fad09c73 | 1392 | static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1393 | struct mv88e6xxx_vtu_entry *entry) |
15d7d7d4 | 1394 | { |
fad09c73 | 1395 | return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0); |
15d7d7d4 VD |
1396 | } |
1397 | ||
fad09c73 | 1398 | static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1399 | struct mv88e6xxx_vtu_entry *entry) |
15d7d7d4 | 1400 | { |
fad09c73 | 1401 | return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2); |
15d7d7d4 VD |
1402 | } |
1403 | ||
fad09c73 | 1404 | static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid) |
36d04ba1 | 1405 | { |
a935c052 VD |
1406 | return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, |
1407 | vid & GLOBAL_VTU_VID_MASK); | |
36d04ba1 VD |
1408 | } |
1409 | ||
fad09c73 | 1410 | static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1411 | struct mv88e6xxx_vtu_entry *entry) |
b8fee957 | 1412 | { |
b4e47c0f | 1413 | struct mv88e6xxx_vtu_entry next = { 0 }; |
a935c052 VD |
1414 | u16 val; |
1415 | int err; | |
b8fee957 | 1416 | |
a935c052 VD |
1417 | err = _mv88e6xxx_vtu_wait(chip); |
1418 | if (err) | |
1419 | return err; | |
b8fee957 | 1420 | |
a935c052 VD |
1421 | err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT); |
1422 | if (err) | |
1423 | return err; | |
b8fee957 | 1424 | |
a935c052 VD |
1425 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val); |
1426 | if (err) | |
1427 | return err; | |
b8fee957 | 1428 | |
a935c052 VD |
1429 | next.vid = val & GLOBAL_VTU_VID_MASK; |
1430 | next.valid = !!(val & GLOBAL_VTU_VID_VALID); | |
b8fee957 VD |
1431 | |
1432 | if (next.valid) { | |
a935c052 VD |
1433 | err = mv88e6xxx_vtu_data_read(chip, &next); |
1434 | if (err) | |
1435 | return err; | |
b8fee957 | 1436 | |
6dc10bbc | 1437 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) { |
a935c052 VD |
1438 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val); |
1439 | if (err) | |
1440 | return err; | |
b8fee957 | 1441 | |
a935c052 | 1442 | next.fid = val & GLOBAL_VTU_FID_MASK; |
fad09c73 | 1443 | } else if (mv88e6xxx_num_databases(chip) == 256) { |
11ea809f VD |
1444 | /* VTU DBNum[7:4] are located in VTU Operation 11:8, and |
1445 | * VTU DBNum[3:0] are located in VTU Operation 3:0 | |
1446 | */ | |
a935c052 VD |
1447 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val); |
1448 | if (err) | |
1449 | return err; | |
11ea809f | 1450 | |
a935c052 VD |
1451 | next.fid = (val & 0xf00) >> 4; |
1452 | next.fid |= val & 0xf; | |
2e7bd5ef | 1453 | } |
b8fee957 | 1454 | |
fad09c73 | 1455 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { |
a935c052 VD |
1456 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val); |
1457 | if (err) | |
1458 | return err; | |
b8fee957 | 1459 | |
a935c052 | 1460 | next.sid = val & GLOBAL_VTU_SID_MASK; |
b8fee957 VD |
1461 | } |
1462 | } | |
1463 | ||
1464 | *entry = next; | |
1465 | return 0; | |
1466 | } | |
1467 | ||
f81ec90f VD |
1468 | static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port, |
1469 | struct switchdev_obj_port_vlan *vlan, | |
1470 | int (*cb)(struct switchdev_obj *obj)) | |
ceff5eff | 1471 | { |
04bed143 | 1472 | struct mv88e6xxx_chip *chip = ds->priv; |
b4e47c0f | 1473 | struct mv88e6xxx_vtu_entry next; |
ceff5eff VD |
1474 | u16 pvid; |
1475 | int err; | |
1476 | ||
fad09c73 | 1477 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
54d77b5b VD |
1478 | return -EOPNOTSUPP; |
1479 | ||
fad09c73 | 1480 | mutex_lock(&chip->reg_lock); |
ceff5eff | 1481 | |
77064f37 | 1482 | err = mv88e6xxx_port_get_pvid(chip, port, &pvid); |
ceff5eff VD |
1483 | if (err) |
1484 | goto unlock; | |
1485 | ||
fad09c73 | 1486 | err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); |
ceff5eff VD |
1487 | if (err) |
1488 | goto unlock; | |
1489 | ||
1490 | do { | |
fad09c73 | 1491 | err = _mv88e6xxx_vtu_getnext(chip, &next); |
ceff5eff VD |
1492 | if (err) |
1493 | break; | |
1494 | ||
1495 | if (!next.valid) | |
1496 | break; | |
1497 | ||
1498 | if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) | |
1499 | continue; | |
1500 | ||
1501 | /* reinit and dump this VLAN obj */ | |
57d32310 VD |
1502 | vlan->vid_begin = next.vid; |
1503 | vlan->vid_end = next.vid; | |
ceff5eff VD |
1504 | vlan->flags = 0; |
1505 | ||
1506 | if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED) | |
1507 | vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED; | |
1508 | ||
1509 | if (next.vid == pvid) | |
1510 | vlan->flags |= BRIDGE_VLAN_INFO_PVID; | |
1511 | ||
1512 | err = cb(&vlan->obj); | |
1513 | if (err) | |
1514 | break; | |
1515 | } while (next.vid < GLOBAL_VTU_VID_MASK); | |
1516 | ||
1517 | unlock: | |
fad09c73 | 1518 | mutex_unlock(&chip->reg_lock); |
ceff5eff VD |
1519 | |
1520 | return err; | |
1521 | } | |
1522 | ||
fad09c73 | 1523 | static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1524 | struct mv88e6xxx_vtu_entry *entry) |
7dad08d7 | 1525 | { |
11ea809f | 1526 | u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE; |
7dad08d7 | 1527 | u16 reg = 0; |
a935c052 | 1528 | int err; |
7dad08d7 | 1529 | |
a935c052 VD |
1530 | err = _mv88e6xxx_vtu_wait(chip); |
1531 | if (err) | |
1532 | return err; | |
7dad08d7 VD |
1533 | |
1534 | if (!entry->valid) | |
1535 | goto loadpurge; | |
1536 | ||
1537 | /* Write port member tags */ | |
a935c052 VD |
1538 | err = mv88e6xxx_vtu_data_write(chip, entry); |
1539 | if (err) | |
1540 | return err; | |
7dad08d7 | 1541 | |
fad09c73 | 1542 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { |
7dad08d7 | 1543 | reg = entry->sid & GLOBAL_VTU_SID_MASK; |
a935c052 VD |
1544 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg); |
1545 | if (err) | |
1546 | return err; | |
b426e5f7 | 1547 | } |
7dad08d7 | 1548 | |
6dc10bbc | 1549 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) { |
7dad08d7 | 1550 | reg = entry->fid & GLOBAL_VTU_FID_MASK; |
a935c052 VD |
1551 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg); |
1552 | if (err) | |
1553 | return err; | |
fad09c73 | 1554 | } else if (mv88e6xxx_num_databases(chip) == 256) { |
11ea809f VD |
1555 | /* VTU DBNum[7:4] are located in VTU Operation 11:8, and |
1556 | * VTU DBNum[3:0] are located in VTU Operation 3:0 | |
1557 | */ | |
1558 | op |= (entry->fid & 0xf0) << 8; | |
1559 | op |= entry->fid & 0xf; | |
7dad08d7 VD |
1560 | } |
1561 | ||
1562 | reg = GLOBAL_VTU_VID_VALID; | |
1563 | loadpurge: | |
1564 | reg |= entry->vid & GLOBAL_VTU_VID_MASK; | |
a935c052 VD |
1565 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg); |
1566 | if (err) | |
1567 | return err; | |
7dad08d7 | 1568 | |
fad09c73 | 1569 | return _mv88e6xxx_vtu_cmd(chip, op); |
7dad08d7 VD |
1570 | } |
1571 | ||
fad09c73 | 1572 | static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid, |
b4e47c0f | 1573 | struct mv88e6xxx_vtu_entry *entry) |
0d3b33e6 | 1574 | { |
b4e47c0f | 1575 | struct mv88e6xxx_vtu_entry next = { 0 }; |
a935c052 VD |
1576 | u16 val; |
1577 | int err; | |
0d3b33e6 | 1578 | |
a935c052 VD |
1579 | err = _mv88e6xxx_vtu_wait(chip); |
1580 | if (err) | |
1581 | return err; | |
0d3b33e6 | 1582 | |
a935c052 VD |
1583 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, |
1584 | sid & GLOBAL_VTU_SID_MASK); | |
1585 | if (err) | |
1586 | return err; | |
0d3b33e6 | 1587 | |
a935c052 VD |
1588 | err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT); |
1589 | if (err) | |
1590 | return err; | |
0d3b33e6 | 1591 | |
a935c052 VD |
1592 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val); |
1593 | if (err) | |
1594 | return err; | |
0d3b33e6 | 1595 | |
a935c052 | 1596 | next.sid = val & GLOBAL_VTU_SID_MASK; |
0d3b33e6 | 1597 | |
a935c052 VD |
1598 | err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val); |
1599 | if (err) | |
1600 | return err; | |
0d3b33e6 | 1601 | |
a935c052 | 1602 | next.valid = !!(val & GLOBAL_VTU_VID_VALID); |
0d3b33e6 VD |
1603 | |
1604 | if (next.valid) { | |
a935c052 VD |
1605 | err = mv88e6xxx_stu_data_read(chip, &next); |
1606 | if (err) | |
1607 | return err; | |
0d3b33e6 VD |
1608 | } |
1609 | ||
1610 | *entry = next; | |
1611 | return 0; | |
1612 | } | |
1613 | ||
fad09c73 | 1614 | static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, |
b4e47c0f | 1615 | struct mv88e6xxx_vtu_entry *entry) |
0d3b33e6 VD |
1616 | { |
1617 | u16 reg = 0; | |
a935c052 | 1618 | int err; |
0d3b33e6 | 1619 | |
a935c052 VD |
1620 | err = _mv88e6xxx_vtu_wait(chip); |
1621 | if (err) | |
1622 | return err; | |
0d3b33e6 VD |
1623 | |
1624 | if (!entry->valid) | |
1625 | goto loadpurge; | |
1626 | ||
1627 | /* Write port states */ | |
a935c052 VD |
1628 | err = mv88e6xxx_stu_data_write(chip, entry); |
1629 | if (err) | |
1630 | return err; | |
0d3b33e6 VD |
1631 | |
1632 | reg = GLOBAL_VTU_VID_VALID; | |
1633 | loadpurge: | |
a935c052 VD |
1634 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg); |
1635 | if (err) | |
1636 | return err; | |
0d3b33e6 VD |
1637 | |
1638 | reg = entry->sid & GLOBAL_VTU_SID_MASK; | |
a935c052 VD |
1639 | err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg); |
1640 | if (err) | |
1641 | return err; | |
0d3b33e6 | 1642 | |
fad09c73 | 1643 | return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE); |
0d3b33e6 VD |
1644 | } |
1645 | ||
fad09c73 | 1646 | static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid) |
3285f9e8 VD |
1647 | { |
1648 | DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); | |
b4e47c0f | 1649 | struct mv88e6xxx_vtu_entry vlan; |
2db9ce1f | 1650 | int i, err; |
3285f9e8 VD |
1651 | |
1652 | bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); | |
1653 | ||
2db9ce1f | 1654 | /* Set every FID bit used by the (un)bridged ports */ |
370b4ffb | 1655 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
b4e48c50 | 1656 | err = mv88e6xxx_port_get_fid(chip, i, fid); |
2db9ce1f VD |
1657 | if (err) |
1658 | return err; | |
1659 | ||
1660 | set_bit(*fid, fid_bitmap); | |
1661 | } | |
1662 | ||
3285f9e8 | 1663 | /* Set every FID bit used by the VLAN entries */ |
fad09c73 | 1664 | err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); |
3285f9e8 VD |
1665 | if (err) |
1666 | return err; | |
1667 | ||
1668 | do { | |
fad09c73 | 1669 | err = _mv88e6xxx_vtu_getnext(chip, &vlan); |
3285f9e8 VD |
1670 | if (err) |
1671 | return err; | |
1672 | ||
1673 | if (!vlan.valid) | |
1674 | break; | |
1675 | ||
1676 | set_bit(vlan.fid, fid_bitmap); | |
1677 | } while (vlan.vid < GLOBAL_VTU_VID_MASK); | |
1678 | ||
1679 | /* The reset value 0x000 is used to indicate that multiple address | |
1680 | * databases are not needed. Return the next positive available. | |
1681 | */ | |
1682 | *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); | |
fad09c73 | 1683 | if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) |
3285f9e8 VD |
1684 | return -ENOSPC; |
1685 | ||
1686 | /* Clear the database */ | |
fad09c73 | 1687 | return _mv88e6xxx_atu_flush(chip, *fid, true); |
3285f9e8 VD |
1688 | } |
1689 | ||
fad09c73 | 1690 | static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid, |
b4e47c0f | 1691 | struct mv88e6xxx_vtu_entry *entry) |
0d3b33e6 | 1692 | { |
fad09c73 | 1693 | struct dsa_switch *ds = chip->ds; |
b4e47c0f | 1694 | struct mv88e6xxx_vtu_entry vlan = { |
0d3b33e6 VD |
1695 | .valid = true, |
1696 | .vid = vid, | |
1697 | }; | |
3285f9e8 VD |
1698 | int i, err; |
1699 | ||
fad09c73 | 1700 | err = _mv88e6xxx_fid_new(chip, &vlan.fid); |
3285f9e8 VD |
1701 | if (err) |
1702 | return err; | |
0d3b33e6 | 1703 | |
3d131f07 | 1704 | /* exclude all ports except the CPU and DSA ports */ |
370b4ffb | 1705 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) |
3d131f07 VD |
1706 | vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i) |
1707 | ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED | |
1708 | : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; | |
0d3b33e6 | 1709 | |
fad09c73 VD |
1710 | if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) || |
1711 | mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) { | |
b4e47c0f | 1712 | struct mv88e6xxx_vtu_entry vstp; |
0d3b33e6 VD |
1713 | |
1714 | /* Adding a VTU entry requires a valid STU entry. As VSTP is not | |
1715 | * implemented, only one STU entry is needed to cover all VTU | |
1716 | * entries. Thus, validate the SID 0. | |
1717 | */ | |
1718 | vlan.sid = 0; | |
fad09c73 | 1719 | err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp); |
0d3b33e6 VD |
1720 | if (err) |
1721 | return err; | |
1722 | ||
1723 | if (vstp.sid != vlan.sid || !vstp.valid) { | |
1724 | memset(&vstp, 0, sizeof(vstp)); | |
1725 | vstp.valid = true; | |
1726 | vstp.sid = vlan.sid; | |
1727 | ||
fad09c73 | 1728 | err = _mv88e6xxx_stu_loadpurge(chip, &vstp); |
0d3b33e6 VD |
1729 | if (err) |
1730 | return err; | |
1731 | } | |
0d3b33e6 VD |
1732 | } |
1733 | ||
1734 | *entry = vlan; | |
1735 | return 0; | |
1736 | } | |
1737 | ||
fad09c73 | 1738 | static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, |
b4e47c0f | 1739 | struct mv88e6xxx_vtu_entry *entry, bool creat) |
2fb5ef09 VD |
1740 | { |
1741 | int err; | |
1742 | ||
1743 | if (!vid) | |
1744 | return -EINVAL; | |
1745 | ||
fad09c73 | 1746 | err = _mv88e6xxx_vtu_vid_write(chip, vid - 1); |
2fb5ef09 VD |
1747 | if (err) |
1748 | return err; | |
1749 | ||
fad09c73 | 1750 | err = _mv88e6xxx_vtu_getnext(chip, entry); |
2fb5ef09 VD |
1751 | if (err) |
1752 | return err; | |
1753 | ||
1754 | if (entry->vid != vid || !entry->valid) { | |
1755 | if (!creat) | |
1756 | return -EOPNOTSUPP; | |
1757 | /* -ENOENT would've been more appropriate, but switchdev expects | |
1758 | * -EOPNOTSUPP to inform bridge about an eventual software VLAN. | |
1759 | */ | |
1760 | ||
fad09c73 | 1761 | err = _mv88e6xxx_vtu_new(chip, vid, entry); |
2fb5ef09 VD |
1762 | } |
1763 | ||
1764 | return err; | |
1765 | } | |
1766 | ||
da9c359e VD |
1767 | static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, |
1768 | u16 vid_begin, u16 vid_end) | |
1769 | { | |
04bed143 | 1770 | struct mv88e6xxx_chip *chip = ds->priv; |
b4e47c0f | 1771 | struct mv88e6xxx_vtu_entry vlan; |
da9c359e VD |
1772 | int i, err; |
1773 | ||
1774 | if (!vid_begin) | |
1775 | return -EOPNOTSUPP; | |
1776 | ||
fad09c73 | 1777 | mutex_lock(&chip->reg_lock); |
da9c359e | 1778 | |
fad09c73 | 1779 | err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1); |
da9c359e VD |
1780 | if (err) |
1781 | goto unlock; | |
1782 | ||
1783 | do { | |
fad09c73 | 1784 | err = _mv88e6xxx_vtu_getnext(chip, &vlan); |
da9c359e VD |
1785 | if (err) |
1786 | goto unlock; | |
1787 | ||
1788 | if (!vlan.valid) | |
1789 | break; | |
1790 | ||
1791 | if (vlan.vid > vid_end) | |
1792 | break; | |
1793 | ||
370b4ffb | 1794 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
da9c359e VD |
1795 | if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) |
1796 | continue; | |
1797 | ||
1798 | if (vlan.data[i] == | |
1799 | GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) | |
1800 | continue; | |
1801 | ||
fad09c73 VD |
1802 | if (chip->ports[i].bridge_dev == |
1803 | chip->ports[port].bridge_dev) | |
da9c359e VD |
1804 | break; /* same bridge, check next VLAN */ |
1805 | ||
c8b09808 | 1806 | netdev_warn(ds->ports[port].netdev, |
da9c359e VD |
1807 | "hardware VLAN %d already used by %s\n", |
1808 | vlan.vid, | |
fad09c73 | 1809 | netdev_name(chip->ports[i].bridge_dev)); |
da9c359e VD |
1810 | err = -EOPNOTSUPP; |
1811 | goto unlock; | |
1812 | } | |
1813 | } while (vlan.vid < vid_end); | |
1814 | ||
1815 | unlock: | |
fad09c73 | 1816 | mutex_unlock(&chip->reg_lock); |
da9c359e VD |
1817 | |
1818 | return err; | |
1819 | } | |
1820 | ||
f81ec90f VD |
1821 | static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, |
1822 | bool vlan_filtering) | |
214cdb99 | 1823 | { |
04bed143 | 1824 | struct mv88e6xxx_chip *chip = ds->priv; |
385a0995 | 1825 | u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE : |
214cdb99 | 1826 | PORT_CONTROL_2_8021Q_DISABLED; |
0e7b9925 | 1827 | int err; |
214cdb99 | 1828 | |
fad09c73 | 1829 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
54d77b5b VD |
1830 | return -EOPNOTSUPP; |
1831 | ||
fad09c73 | 1832 | mutex_lock(&chip->reg_lock); |
385a0995 | 1833 | err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); |
fad09c73 | 1834 | mutex_unlock(&chip->reg_lock); |
214cdb99 | 1835 | |
0e7b9925 | 1836 | return err; |
214cdb99 VD |
1837 | } |
1838 | ||
57d32310 VD |
1839 | static int |
1840 | mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, | |
1841 | const struct switchdev_obj_port_vlan *vlan, | |
1842 | struct switchdev_trans *trans) | |
76e398a6 | 1843 | { |
04bed143 | 1844 | struct mv88e6xxx_chip *chip = ds->priv; |
da9c359e VD |
1845 | int err; |
1846 | ||
fad09c73 | 1847 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
54d77b5b VD |
1848 | return -EOPNOTSUPP; |
1849 | ||
da9c359e VD |
1850 | /* If the requested port doesn't belong to the same bridge as the VLAN |
1851 | * members, do not support it (yet) and fallback to software VLAN. | |
1852 | */ | |
1853 | err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, | |
1854 | vlan->vid_end); | |
1855 | if (err) | |
1856 | return err; | |
1857 | ||
76e398a6 VD |
1858 | /* We don't need any dynamic resource from the kernel (yet), |
1859 | * so skip the prepare phase. | |
1860 | */ | |
1861 | return 0; | |
1862 | } | |
1863 | ||
fad09c73 | 1864 | static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, |
158bc065 | 1865 | u16 vid, bool untagged) |
0d3b33e6 | 1866 | { |
b4e47c0f | 1867 | struct mv88e6xxx_vtu_entry vlan; |
0d3b33e6 VD |
1868 | int err; |
1869 | ||
fad09c73 | 1870 | err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true); |
0d3b33e6 | 1871 | if (err) |
76e398a6 | 1872 | return err; |
0d3b33e6 | 1873 | |
0d3b33e6 VD |
1874 | vlan.data[port] = untagged ? |
1875 | GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED : | |
1876 | GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED; | |
1877 | ||
fad09c73 | 1878 | return _mv88e6xxx_vtu_loadpurge(chip, &vlan); |
76e398a6 VD |
1879 | } |
1880 | ||
f81ec90f VD |
1881 | static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, |
1882 | const struct switchdev_obj_port_vlan *vlan, | |
1883 | struct switchdev_trans *trans) | |
76e398a6 | 1884 | { |
04bed143 | 1885 | struct mv88e6xxx_chip *chip = ds->priv; |
76e398a6 VD |
1886 | bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; |
1887 | bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; | |
1888 | u16 vid; | |
76e398a6 | 1889 | |
fad09c73 | 1890 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
54d77b5b VD |
1891 | return; |
1892 | ||
fad09c73 | 1893 | mutex_lock(&chip->reg_lock); |
76e398a6 | 1894 | |
4d5770b3 | 1895 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) |
fad09c73 | 1896 | if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged)) |
c8b09808 AL |
1897 | netdev_err(ds->ports[port].netdev, |
1898 | "failed to add VLAN %d%c\n", | |
4d5770b3 | 1899 | vid, untagged ? 'u' : 't'); |
76e398a6 | 1900 | |
77064f37 | 1901 | if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) |
c8b09808 | 1902 | netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n", |
4d5770b3 | 1903 | vlan->vid_end); |
0d3b33e6 | 1904 | |
fad09c73 | 1905 | mutex_unlock(&chip->reg_lock); |
0d3b33e6 VD |
1906 | } |
1907 | ||
fad09c73 | 1908 | static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, |
158bc065 | 1909 | int port, u16 vid) |
7dad08d7 | 1910 | { |
fad09c73 | 1911 | struct dsa_switch *ds = chip->ds; |
b4e47c0f | 1912 | struct mv88e6xxx_vtu_entry vlan; |
7dad08d7 VD |
1913 | int i, err; |
1914 | ||
fad09c73 | 1915 | err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); |
7dad08d7 | 1916 | if (err) |
76e398a6 | 1917 | return err; |
7dad08d7 | 1918 | |
2fb5ef09 VD |
1919 | /* Tell switchdev if this VLAN is handled in software */ |
1920 | if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) | |
3c06f08b | 1921 | return -EOPNOTSUPP; |
7dad08d7 VD |
1922 | |
1923 | vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; | |
1924 | ||
1925 | /* keep the VLAN unless all ports are excluded */ | |
f02bdffc | 1926 | vlan.valid = false; |
370b4ffb | 1927 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
3d131f07 | 1928 | if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) |
7dad08d7 VD |
1929 | continue; |
1930 | ||
1931 | if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) { | |
f02bdffc | 1932 | vlan.valid = true; |
7dad08d7 VD |
1933 | break; |
1934 | } | |
1935 | } | |
1936 | ||
fad09c73 | 1937 | err = _mv88e6xxx_vtu_loadpurge(chip, &vlan); |
76e398a6 VD |
1938 | if (err) |
1939 | return err; | |
1940 | ||
fad09c73 | 1941 | return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false); |
76e398a6 VD |
1942 | } |
1943 | ||
f81ec90f VD |
1944 | static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, |
1945 | const struct switchdev_obj_port_vlan *vlan) | |
76e398a6 | 1946 | { |
04bed143 | 1947 | struct mv88e6xxx_chip *chip = ds->priv; |
76e398a6 VD |
1948 | u16 pvid, vid; |
1949 | int err = 0; | |
1950 | ||
fad09c73 | 1951 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
54d77b5b VD |
1952 | return -EOPNOTSUPP; |
1953 | ||
fad09c73 | 1954 | mutex_lock(&chip->reg_lock); |
76e398a6 | 1955 | |
77064f37 | 1956 | err = mv88e6xxx_port_get_pvid(chip, port, &pvid); |
7dad08d7 VD |
1957 | if (err) |
1958 | goto unlock; | |
1959 | ||
76e398a6 | 1960 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { |
fad09c73 | 1961 | err = _mv88e6xxx_port_vlan_del(chip, port, vid); |
76e398a6 VD |
1962 | if (err) |
1963 | goto unlock; | |
1964 | ||
1965 | if (vid == pvid) { | |
77064f37 | 1966 | err = mv88e6xxx_port_set_pvid(chip, port, 0); |
76e398a6 VD |
1967 | if (err) |
1968 | goto unlock; | |
1969 | } | |
1970 | } | |
1971 | ||
7dad08d7 | 1972 | unlock: |
fad09c73 | 1973 | mutex_unlock(&chip->reg_lock); |
7dad08d7 VD |
1974 | |
1975 | return err; | |
1976 | } | |
1977 | ||
fad09c73 | 1978 | static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip, |
c5723ac5 | 1979 | const unsigned char *addr) |
defb05b9 | 1980 | { |
a935c052 | 1981 | int i, err; |
defb05b9 GR |
1982 | |
1983 | for (i = 0; i < 3; i++) { | |
a935c052 VD |
1984 | err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i, |
1985 | (addr[i * 2] << 8) | addr[i * 2 + 1]); | |
1986 | if (err) | |
1987 | return err; | |
defb05b9 GR |
1988 | } |
1989 | ||
1990 | return 0; | |
1991 | } | |
1992 | ||
fad09c73 | 1993 | static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip, |
158bc065 | 1994 | unsigned char *addr) |
defb05b9 | 1995 | { |
a935c052 VD |
1996 | u16 val; |
1997 | int i, err; | |
defb05b9 GR |
1998 | |
1999 | for (i = 0; i < 3; i++) { | |
a935c052 VD |
2000 | err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val); |
2001 | if (err) | |
2002 | return err; | |
2003 | ||
2004 | addr[i * 2] = val >> 8; | |
2005 | addr[i * 2 + 1] = val & 0xff; | |
defb05b9 GR |
2006 | } |
2007 | ||
2008 | return 0; | |
2009 | } | |
2010 | ||
fad09c73 | 2011 | static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip, |
fd231c82 | 2012 | struct mv88e6xxx_atu_entry *entry) |
defb05b9 | 2013 | { |
6630e236 VD |
2014 | int ret; |
2015 | ||
fad09c73 | 2016 | ret = _mv88e6xxx_atu_wait(chip); |
defb05b9 GR |
2017 | if (ret < 0) |
2018 | return ret; | |
2019 | ||
fad09c73 | 2020 | ret = _mv88e6xxx_atu_mac_write(chip, entry->mac); |
defb05b9 GR |
2021 | if (ret < 0) |
2022 | return ret; | |
2023 | ||
fad09c73 | 2024 | ret = _mv88e6xxx_atu_data_write(chip, entry); |
fd231c82 | 2025 | if (ret < 0) |
87820510 VD |
2026 | return ret; |
2027 | ||
fad09c73 | 2028 | return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB); |
fd231c82 | 2029 | } |
87820510 | 2030 | |
88472939 VD |
2031 | static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, |
2032 | struct mv88e6xxx_atu_entry *entry); | |
2033 | ||
2034 | static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid, | |
2035 | const u8 *addr, struct mv88e6xxx_atu_entry *entry) | |
2036 | { | |
2037 | struct mv88e6xxx_atu_entry next; | |
2038 | int err; | |
2039 | ||
2040 | eth_broadcast_addr(next.mac); | |
2041 | ||
2042 | err = _mv88e6xxx_atu_mac_write(chip, next.mac); | |
2043 | if (err) | |
2044 | return err; | |
2045 | ||
2046 | do { | |
2047 | err = _mv88e6xxx_atu_getnext(chip, fid, &next); | |
2048 | if (err) | |
2049 | return err; | |
2050 | ||
2051 | if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED) | |
2052 | break; | |
2053 | ||
2054 | if (ether_addr_equal(next.mac, addr)) { | |
2055 | *entry = next; | |
2056 | return 0; | |
2057 | } | |
2058 | } while (!is_broadcast_ether_addr(next.mac)); | |
2059 | ||
2060 | memset(entry, 0, sizeof(*entry)); | |
2061 | entry->fid = fid; | |
2062 | ether_addr_copy(entry->mac, addr); | |
2063 | ||
2064 | return 0; | |
2065 | } | |
2066 | ||
83dabd1f VD |
2067 | static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, |
2068 | const unsigned char *addr, u16 vid, | |
2069 | u8 state) | |
fd231c82 | 2070 | { |
b4e47c0f | 2071 | struct mv88e6xxx_vtu_entry vlan; |
88472939 | 2072 | struct mv88e6xxx_atu_entry entry; |
3285f9e8 VD |
2073 | int err; |
2074 | ||
2db9ce1f VD |
2075 | /* Null VLAN ID corresponds to the port private database */ |
2076 | if (vid == 0) | |
b4e48c50 | 2077 | err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); |
2db9ce1f | 2078 | else |
fad09c73 | 2079 | err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); |
3285f9e8 VD |
2080 | if (err) |
2081 | return err; | |
fd231c82 | 2082 | |
88472939 VD |
2083 | err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry); |
2084 | if (err) | |
2085 | return err; | |
2086 | ||
2087 | /* Purge the ATU entry only if no port is using it anymore */ | |
2088 | if (state == GLOBAL_ATU_DATA_STATE_UNUSED) { | |
2089 | entry.portv_trunkid &= ~BIT(port); | |
2090 | if (!entry.portv_trunkid) | |
2091 | entry.state = GLOBAL_ATU_DATA_STATE_UNUSED; | |
2092 | } else { | |
2093 | entry.portv_trunkid |= BIT(port); | |
2094 | entry.state = state; | |
fd231c82 VD |
2095 | } |
2096 | ||
fad09c73 | 2097 | return _mv88e6xxx_atu_load(chip, &entry); |
87820510 VD |
2098 | } |
2099 | ||
f81ec90f VD |
2100 | static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, |
2101 | const struct switchdev_obj_port_fdb *fdb, | |
2102 | struct switchdev_trans *trans) | |
146a3206 VD |
2103 | { |
2104 | /* We don't need any dynamic resource from the kernel (yet), | |
2105 | * so skip the prepare phase. | |
2106 | */ | |
2107 | return 0; | |
2108 | } | |
2109 | ||
f81ec90f VD |
2110 | static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, |
2111 | const struct switchdev_obj_port_fdb *fdb, | |
2112 | struct switchdev_trans *trans) | |
87820510 | 2113 | { |
04bed143 | 2114 | struct mv88e6xxx_chip *chip = ds->priv; |
87820510 | 2115 | |
fad09c73 | 2116 | mutex_lock(&chip->reg_lock); |
83dabd1f VD |
2117 | if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, |
2118 | GLOBAL_ATU_DATA_STATE_UC_STATIC)) | |
2119 | netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n"); | |
fad09c73 | 2120 | mutex_unlock(&chip->reg_lock); |
87820510 VD |
2121 | } |
2122 | ||
f81ec90f VD |
2123 | static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, |
2124 | const struct switchdev_obj_port_fdb *fdb) | |
87820510 | 2125 | { |
04bed143 | 2126 | struct mv88e6xxx_chip *chip = ds->priv; |
83dabd1f | 2127 | int err; |
87820510 | 2128 | |
fad09c73 | 2129 | mutex_lock(&chip->reg_lock); |
83dabd1f VD |
2130 | err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, |
2131 | GLOBAL_ATU_DATA_STATE_UNUSED); | |
fad09c73 | 2132 | mutex_unlock(&chip->reg_lock); |
87820510 | 2133 | |
83dabd1f | 2134 | return err; |
87820510 VD |
2135 | } |
2136 | ||
fad09c73 | 2137 | static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, |
1d194046 | 2138 | struct mv88e6xxx_atu_entry *entry) |
6630e236 | 2139 | { |
1d194046 | 2140 | struct mv88e6xxx_atu_entry next = { 0 }; |
a935c052 VD |
2141 | u16 val; |
2142 | int err; | |
1d194046 VD |
2143 | |
2144 | next.fid = fid; | |
defb05b9 | 2145 | |
a935c052 VD |
2146 | err = _mv88e6xxx_atu_wait(chip); |
2147 | if (err) | |
2148 | return err; | |
6630e236 | 2149 | |
a935c052 VD |
2150 | err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB); |
2151 | if (err) | |
2152 | return err; | |
6630e236 | 2153 | |
a935c052 VD |
2154 | err = _mv88e6xxx_atu_mac_read(chip, next.mac); |
2155 | if (err) | |
2156 | return err; | |
6630e236 | 2157 | |
a935c052 VD |
2158 | err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val); |
2159 | if (err) | |
2160 | return err; | |
6630e236 | 2161 | |
a935c052 | 2162 | next.state = val & GLOBAL_ATU_DATA_STATE_MASK; |
1d194046 VD |
2163 | if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) { |
2164 | unsigned int mask, shift; | |
2165 | ||
a935c052 | 2166 | if (val & GLOBAL_ATU_DATA_TRUNK) { |
1d194046 VD |
2167 | next.trunk = true; |
2168 | mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; | |
2169 | shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; | |
2170 | } else { | |
2171 | next.trunk = false; | |
2172 | mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; | |
2173 | shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; | |
2174 | } | |
2175 | ||
a935c052 | 2176 | next.portv_trunkid = (val & mask) >> shift; |
1d194046 | 2177 | } |
cdf09697 | 2178 | |
1d194046 | 2179 | *entry = next; |
cdf09697 DM |
2180 | return 0; |
2181 | } | |
2182 | ||
83dabd1f VD |
2183 | static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, |
2184 | u16 fid, u16 vid, int port, | |
2185 | struct switchdev_obj *obj, | |
2186 | int (*cb)(struct switchdev_obj *obj)) | |
74b6ba0d VD |
2187 | { |
2188 | struct mv88e6xxx_atu_entry addr = { | |
2189 | .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, | |
2190 | }; | |
2191 | int err; | |
2192 | ||
fad09c73 | 2193 | err = _mv88e6xxx_atu_mac_write(chip, addr.mac); |
74b6ba0d VD |
2194 | if (err) |
2195 | return err; | |
2196 | ||
2197 | do { | |
fad09c73 | 2198 | err = _mv88e6xxx_atu_getnext(chip, fid, &addr); |
74b6ba0d | 2199 | if (err) |
83dabd1f | 2200 | return err; |
74b6ba0d VD |
2201 | |
2202 | if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED) | |
2203 | break; | |
2204 | ||
83dabd1f VD |
2205 | if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0) |
2206 | continue; | |
2207 | ||
2208 | if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) { | |
2209 | struct switchdev_obj_port_fdb *fdb; | |
74b6ba0d | 2210 | |
83dabd1f VD |
2211 | if (!is_unicast_ether_addr(addr.mac)) |
2212 | continue; | |
2213 | ||
2214 | fdb = SWITCHDEV_OBJ_PORT_FDB(obj); | |
74b6ba0d VD |
2215 | fdb->vid = vid; |
2216 | ether_addr_copy(fdb->addr, addr.mac); | |
83dabd1f VD |
2217 | if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC) |
2218 | fdb->ndm_state = NUD_NOARP; | |
2219 | else | |
2220 | fdb->ndm_state = NUD_REACHABLE; | |
7df8fbdd VD |
2221 | } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) { |
2222 | struct switchdev_obj_port_mdb *mdb; | |
2223 | ||
2224 | if (!is_multicast_ether_addr(addr.mac)) | |
2225 | continue; | |
2226 | ||
2227 | mdb = SWITCHDEV_OBJ_PORT_MDB(obj); | |
2228 | mdb->vid = vid; | |
2229 | ether_addr_copy(mdb->addr, addr.mac); | |
83dabd1f VD |
2230 | } else { |
2231 | return -EOPNOTSUPP; | |
74b6ba0d | 2232 | } |
83dabd1f VD |
2233 | |
2234 | err = cb(obj); | |
2235 | if (err) | |
2236 | return err; | |
74b6ba0d VD |
2237 | } while (!is_broadcast_ether_addr(addr.mac)); |
2238 | ||
2239 | return err; | |
2240 | } | |
2241 | ||
83dabd1f VD |
2242 | static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, |
2243 | struct switchdev_obj *obj, | |
2244 | int (*cb)(struct switchdev_obj *obj)) | |
f33475bd | 2245 | { |
b4e47c0f | 2246 | struct mv88e6xxx_vtu_entry vlan = { |
f33475bd VD |
2247 | .vid = GLOBAL_VTU_VID_MASK, /* all ones */ |
2248 | }; | |
2db9ce1f | 2249 | u16 fid; |
f33475bd VD |
2250 | int err; |
2251 | ||
2db9ce1f | 2252 | /* Dump port's default Filtering Information Database (VLAN ID 0) */ |
b4e48c50 | 2253 | err = mv88e6xxx_port_get_fid(chip, port, &fid); |
2db9ce1f | 2254 | if (err) |
83dabd1f | 2255 | return err; |
2db9ce1f | 2256 | |
83dabd1f | 2257 | err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb); |
2db9ce1f | 2258 | if (err) |
83dabd1f | 2259 | return err; |
2db9ce1f | 2260 | |
74b6ba0d | 2261 | /* Dump VLANs' Filtering Information Databases */ |
fad09c73 | 2262 | err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid); |
f33475bd | 2263 | if (err) |
83dabd1f | 2264 | return err; |
f33475bd VD |
2265 | |
2266 | do { | |
fad09c73 | 2267 | err = _mv88e6xxx_vtu_getnext(chip, &vlan); |
f33475bd | 2268 | if (err) |
83dabd1f | 2269 | return err; |
f33475bd VD |
2270 | |
2271 | if (!vlan.valid) | |
2272 | break; | |
2273 | ||
83dabd1f VD |
2274 | err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, |
2275 | obj, cb); | |
f33475bd | 2276 | if (err) |
83dabd1f | 2277 | return err; |
f33475bd VD |
2278 | } while (vlan.vid < GLOBAL_VTU_VID_MASK); |
2279 | ||
83dabd1f VD |
2280 | return err; |
2281 | } | |
2282 | ||
2283 | static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, | |
2284 | struct switchdev_obj_port_fdb *fdb, | |
2285 | int (*cb)(struct switchdev_obj *obj)) | |
2286 | { | |
04bed143 | 2287 | struct mv88e6xxx_chip *chip = ds->priv; |
83dabd1f VD |
2288 | int err; |
2289 | ||
2290 | mutex_lock(&chip->reg_lock); | |
2291 | err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb); | |
fad09c73 | 2292 | mutex_unlock(&chip->reg_lock); |
f33475bd VD |
2293 | |
2294 | return err; | |
2295 | } | |
2296 | ||
f81ec90f VD |
2297 | static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, |
2298 | struct net_device *bridge) | |
e79a8bcb | 2299 | { |
04bed143 | 2300 | struct mv88e6xxx_chip *chip = ds->priv; |
1d9619d5 | 2301 | int i, err = 0; |
466dfa07 | 2302 | |
fad09c73 | 2303 | mutex_lock(&chip->reg_lock); |
466dfa07 | 2304 | |
b7666efe | 2305 | /* Assign the bridge and remap each port's VLANTable */ |
fad09c73 | 2306 | chip->ports[port].bridge_dev = bridge; |
b7666efe | 2307 | |
370b4ffb | 2308 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
fad09c73 VD |
2309 | if (chip->ports[i].bridge_dev == bridge) { |
2310 | err = _mv88e6xxx_port_based_vlan_map(chip, i); | |
b7666efe VD |
2311 | if (err) |
2312 | break; | |
2313 | } | |
2314 | } | |
2315 | ||
fad09c73 | 2316 | mutex_unlock(&chip->reg_lock); |
a6692754 | 2317 | |
466dfa07 | 2318 | return err; |
e79a8bcb VD |
2319 | } |
2320 | ||
f81ec90f | 2321 | static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port) |
66d9cd0f | 2322 | { |
04bed143 | 2323 | struct mv88e6xxx_chip *chip = ds->priv; |
fad09c73 | 2324 | struct net_device *bridge = chip->ports[port].bridge_dev; |
16bfa702 | 2325 | int i; |
466dfa07 | 2326 | |
fad09c73 | 2327 | mutex_lock(&chip->reg_lock); |
466dfa07 | 2328 | |
b7666efe | 2329 | /* Unassign the bridge and remap each port's VLANTable */ |
fad09c73 | 2330 | chip->ports[port].bridge_dev = NULL; |
b7666efe | 2331 | |
370b4ffb | 2332 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) |
fad09c73 VD |
2333 | if (i == port || chip->ports[i].bridge_dev == bridge) |
2334 | if (_mv88e6xxx_port_based_vlan_map(chip, i)) | |
c8b09808 AL |
2335 | netdev_warn(ds->ports[i].netdev, |
2336 | "failed to remap\n"); | |
b7666efe | 2337 | |
fad09c73 | 2338 | mutex_unlock(&chip->reg_lock); |
66d9cd0f VD |
2339 | } |
2340 | ||
fad09c73 | 2341 | static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) |
552238b5 | 2342 | { |
fad09c73 | 2343 | bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE); |
552238b5 | 2344 | u16 is_reset = (ppu_active ? 0x8800 : 0xc800); |
fad09c73 | 2345 | struct gpio_desc *gpiod = chip->reset; |
552238b5 | 2346 | unsigned long timeout; |
0e7b9925 | 2347 | u16 reg; |
a935c052 | 2348 | int err; |
552238b5 VD |
2349 | int i; |
2350 | ||
2351 | /* Set all ports to the disabled state. */ | |
370b4ffb | 2352 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { |
e28def33 VD |
2353 | err = mv88e6xxx_port_set_state(chip, i, |
2354 | PORT_CONTROL_STATE_DISABLED); | |
0e7b9925 AL |
2355 | if (err) |
2356 | return err; | |
552238b5 VD |
2357 | } |
2358 | ||
2359 | /* Wait for transmit queues to drain. */ | |
2360 | usleep_range(2000, 4000); | |
2361 | ||
2362 | /* If there is a gpio connected to the reset pin, toggle it */ | |
2363 | if (gpiod) { | |
2364 | gpiod_set_value_cansleep(gpiod, 1); | |
2365 | usleep_range(10000, 20000); | |
2366 | gpiod_set_value_cansleep(gpiod, 0); | |
2367 | usleep_range(10000, 20000); | |
2368 | } | |
2369 | ||
2370 | /* Reset the switch. Keep the PPU active if requested. The PPU | |
2371 | * needs to be active to support indirect phy register access | |
2372 | * through global registers 0x18 and 0x19. | |
2373 | */ | |
2374 | if (ppu_active) | |
a935c052 | 2375 | err = mv88e6xxx_g1_write(chip, 0x04, 0xc000); |
552238b5 | 2376 | else |
a935c052 | 2377 | err = mv88e6xxx_g1_write(chip, 0x04, 0xc400); |
0e7b9925 AL |
2378 | if (err) |
2379 | return err; | |
552238b5 VD |
2380 | |
2381 | /* Wait up to one second for reset to complete. */ | |
2382 | timeout = jiffies + 1 * HZ; | |
2383 | while (time_before(jiffies, timeout)) { | |
a935c052 VD |
2384 | err = mv88e6xxx_g1_read(chip, 0x00, ®); |
2385 | if (err) | |
2386 | return err; | |
552238b5 | 2387 | |
a935c052 | 2388 | if ((reg & is_reset) == is_reset) |
552238b5 VD |
2389 | break; |
2390 | usleep_range(1000, 2000); | |
2391 | } | |
2392 | if (time_after(jiffies, timeout)) | |
0e7b9925 | 2393 | err = -ETIMEDOUT; |
552238b5 | 2394 | else |
0e7b9925 | 2395 | err = 0; |
552238b5 | 2396 | |
0e7b9925 | 2397 | return err; |
552238b5 VD |
2398 | } |
2399 | ||
09cb7dfd | 2400 | static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip) |
13a7ebb3 | 2401 | { |
09cb7dfd VD |
2402 | u16 val; |
2403 | int err; | |
13a7ebb3 | 2404 | |
09cb7dfd VD |
2405 | /* Clear Power Down bit */ |
2406 | err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val); | |
2407 | if (err) | |
2408 | return err; | |
13a7ebb3 | 2409 | |
09cb7dfd VD |
2410 | if (val & BMCR_PDOWN) { |
2411 | val &= ~BMCR_PDOWN; | |
2412 | err = mv88e6xxx_serdes_write(chip, MII_BMCR, val); | |
13a7ebb3 PU |
2413 | } |
2414 | ||
09cb7dfd | 2415 | return err; |
13a7ebb3 PU |
2416 | } |
2417 | ||
fad09c73 | 2418 | static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) |
d827e88a | 2419 | { |
fad09c73 | 2420 | struct dsa_switch *ds = chip->ds; |
0e7b9925 | 2421 | int err; |
54d792f2 | 2422 | u16 reg; |
d827e88a | 2423 | |
d78343d2 VD |
2424 | /* MAC Forcing register: don't force link, speed, duplex or flow control |
2425 | * state to any particular values on physical ports, but force the CPU | |
2426 | * port and all DSA ports to their maximum bandwidth and full duplex. | |
2427 | */ | |
2428 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) | |
2429 | err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, | |
2430 | SPEED_MAX, DUPLEX_FULL, | |
2431 | PHY_INTERFACE_MODE_NA); | |
2432 | else | |
2433 | err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, | |
2434 | SPEED_UNFORCED, DUPLEX_UNFORCED, | |
2435 | PHY_INTERFACE_MODE_NA); | |
2436 | if (err) | |
2437 | return err; | |
54d792f2 AL |
2438 | |
2439 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, | |
2440 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN | |
2441 | * tunneling, determine priority by looking at 802.1p and IP | |
2442 | * priority fields (IP prio has precedence), and set STP state | |
2443 | * to Forwarding. | |
2444 | * | |
2445 | * If this is the CPU link, use DSA or EDSA tagging depending | |
2446 | * on which tagging mode was configured. | |
2447 | * | |
2448 | * If this is a link to another switch, use DSA tagging mode. | |
2449 | * | |
2450 | * If this is the upstream port for this switch, enable | |
2451 | * forwarding of unknown unicasts and multicasts. | |
2452 | */ | |
2453 | reg = 0; | |
fad09c73 VD |
2454 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
2455 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || | |
2456 | mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) || | |
2457 | mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip)) | |
54d792f2 AL |
2458 | reg = PORT_CONTROL_IGMP_MLD_SNOOP | |
2459 | PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | | |
2460 | PORT_CONTROL_STATE_FORWARDING; | |
2461 | if (dsa_is_cpu_port(ds, port)) { | |
2bbb33be | 2462 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) |
5377b802 | 2463 | reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA | |
c047a1f9 | 2464 | PORT_CONTROL_FORWARD_UNKNOWN_MC; |
2bbb33be AL |
2465 | else |
2466 | reg |= PORT_CONTROL_DSA_TAG; | |
f027e0cc JL |
2467 | reg |= PORT_CONTROL_EGRESS_ADD_TAG | |
2468 | PORT_CONTROL_FORWARD_UNKNOWN; | |
54d792f2 | 2469 | } |
6083ce71 | 2470 | if (dsa_is_dsa_port(ds, port)) { |
fad09c73 VD |
2471 | if (mv88e6xxx_6095_family(chip) || |
2472 | mv88e6xxx_6185_family(chip)) | |
6083ce71 | 2473 | reg |= PORT_CONTROL_DSA_TAG; |
fad09c73 VD |
2474 | if (mv88e6xxx_6352_family(chip) || |
2475 | mv88e6xxx_6351_family(chip) || | |
2476 | mv88e6xxx_6165_family(chip) || | |
2477 | mv88e6xxx_6097_family(chip) || | |
2478 | mv88e6xxx_6320_family(chip)) { | |
54d792f2 | 2479 | reg |= PORT_CONTROL_FRAME_MODE_DSA; |
6083ce71 AL |
2480 | } |
2481 | ||
54d792f2 AL |
2482 | if (port == dsa_upstream_port(ds)) |
2483 | reg |= PORT_CONTROL_FORWARD_UNKNOWN | | |
2484 | PORT_CONTROL_FORWARD_UNKNOWN_MC; | |
2485 | } | |
2486 | if (reg) { | |
0e7b9925 AL |
2487 | err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg); |
2488 | if (err) | |
2489 | return err; | |
54d792f2 AL |
2490 | } |
2491 | ||
13a7ebb3 PU |
2492 | /* If this port is connected to a SerDes, make sure the SerDes is not |
2493 | * powered down. | |
2494 | */ | |
09cb7dfd | 2495 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) { |
0e7b9925 AL |
2496 | err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®); |
2497 | if (err) | |
2498 | return err; | |
2499 | reg &= PORT_STATUS_CMODE_MASK; | |
2500 | if ((reg == PORT_STATUS_CMODE_100BASE_X) || | |
2501 | (reg == PORT_STATUS_CMODE_1000BASE_X) || | |
2502 | (reg == PORT_STATUS_CMODE_SGMII)) { | |
2503 | err = mv88e6xxx_serdes_power_on(chip); | |
2504 | if (err < 0) | |
2505 | return err; | |
13a7ebb3 PU |
2506 | } |
2507 | } | |
2508 | ||
8efdda4a | 2509 | /* Port Control 2: don't force a good FCS, set the maximum frame size to |
46fbe5e5 | 2510 | * 10240 bytes, disable 802.1q tags checking, don't discard tagged or |
8efdda4a VD |
2511 | * untagged frames on this port, do a destination address lookup on all |
2512 | * received packets as usual, disable ARP mirroring and don't send a | |
2513 | * copy of all transmitted/received frames on this port to the CPU. | |
54d792f2 AL |
2514 | */ |
2515 | reg = 0; | |
fad09c73 VD |
2516 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
2517 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || | |
2518 | mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) || | |
2519 | mv88e6xxx_6185_family(chip)) | |
54d792f2 AL |
2520 | reg = PORT_CONTROL_2_MAP_DA; |
2521 | ||
fad09c73 VD |
2522 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
2523 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip)) | |
54d792f2 AL |
2524 | reg |= PORT_CONTROL_2_JUMBO_10240; |
2525 | ||
fad09c73 | 2526 | if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) { |
54d792f2 AL |
2527 | /* Set the upstream port this port should use */ |
2528 | reg |= dsa_upstream_port(ds); | |
2529 | /* enable forwarding of unknown multicast addresses to | |
2530 | * the upstream port | |
2531 | */ | |
2532 | if (port == dsa_upstream_port(ds)) | |
2533 | reg |= PORT_CONTROL_2_FORWARD_UNKNOWN; | |
2534 | } | |
2535 | ||
46fbe5e5 | 2536 | reg |= PORT_CONTROL_2_8021Q_DISABLED; |
8efdda4a | 2537 | |
54d792f2 | 2538 | if (reg) { |
0e7b9925 AL |
2539 | err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg); |
2540 | if (err) | |
2541 | return err; | |
54d792f2 AL |
2542 | } |
2543 | ||
2544 | /* Port Association Vector: when learning source addresses | |
2545 | * of packets, add the address to the address database using | |
2546 | * a port bitmap that has only the bit for this port set and | |
2547 | * the other bits clear. | |
2548 | */ | |
4c7ea3c0 | 2549 | reg = 1 << port; |
996ecb82 VD |
2550 | /* Disable learning for CPU port */ |
2551 | if (dsa_is_cpu_port(ds, port)) | |
65fa4027 | 2552 | reg = 0; |
4c7ea3c0 | 2553 | |
0e7b9925 AL |
2554 | err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg); |
2555 | if (err) | |
2556 | return err; | |
54d792f2 AL |
2557 | |
2558 | /* Egress rate control 2: disable egress rate control. */ | |
0e7b9925 AL |
2559 | err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000); |
2560 | if (err) | |
2561 | return err; | |
54d792f2 | 2562 | |
fad09c73 VD |
2563 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
2564 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || | |
2565 | mv88e6xxx_6320_family(chip)) { | |
54d792f2 AL |
2566 | /* Do not limit the period of time that this port can |
2567 | * be paused for by the remote end or the period of | |
2568 | * time that this port can pause the remote end. | |
2569 | */ | |
0e7b9925 AL |
2570 | err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000); |
2571 | if (err) | |
2572 | return err; | |
54d792f2 AL |
2573 | |
2574 | /* Port ATU control: disable limiting the number of | |
2575 | * address database entries that this port is allowed | |
2576 | * to use. | |
2577 | */ | |
0e7b9925 AL |
2578 | err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL, |
2579 | 0x0000); | |
54d792f2 AL |
2580 | /* Priority Override: disable DA, SA and VTU priority |
2581 | * override. | |
2582 | */ | |
0e7b9925 AL |
2583 | err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE, |
2584 | 0x0000); | |
2585 | if (err) | |
2586 | return err; | |
54d792f2 AL |
2587 | |
2588 | /* Port Ethertype: use the Ethertype DSA Ethertype | |
2589 | * value. | |
2590 | */ | |
2bbb33be | 2591 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) { |
0e7b9925 AL |
2592 | err = mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE, |
2593 | ETH_P_EDSA); | |
2594 | if (err) | |
2595 | return err; | |
2bbb33be AL |
2596 | } |
2597 | ||
54d792f2 AL |
2598 | /* Tag Remap: use an identity 802.1p prio -> switch |
2599 | * prio mapping. | |
2600 | */ | |
0e7b9925 AL |
2601 | err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123, |
2602 | 0x3210); | |
2603 | if (err) | |
2604 | return err; | |
54d792f2 AL |
2605 | |
2606 | /* Tag Remap 2: use an identity 802.1p prio -> switch | |
2607 | * prio mapping. | |
2608 | */ | |
0e7b9925 AL |
2609 | err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567, |
2610 | 0x7654); | |
2611 | if (err) | |
2612 | return err; | |
54d792f2 AL |
2613 | } |
2614 | ||
1bc261fa | 2615 | /* Rate Control: disable ingress rate limiting. */ |
fad09c73 VD |
2616 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
2617 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || | |
fad09c73 | 2618 | mv88e6xxx_6320_family(chip)) { |
0e7b9925 AL |
2619 | err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, |
2620 | 0x0001); | |
2621 | if (err) | |
2622 | return err; | |
1bc261fa | 2623 | } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) { |
0e7b9925 AL |
2624 | err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, |
2625 | 0x0000); | |
2626 | if (err) | |
2627 | return err; | |
54d792f2 AL |
2628 | } |
2629 | ||
366f0a0f GR |
2630 | /* Port Control 1: disable trunking, disable sending |
2631 | * learning messages to this port. | |
d827e88a | 2632 | */ |
0e7b9925 AL |
2633 | err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000); |
2634 | if (err) | |
2635 | return err; | |
d827e88a | 2636 | |
207afda1 | 2637 | /* Port based VLAN map: give each port the same default address |
b7666efe VD |
2638 | * database, and allow bidirectional communication between the |
2639 | * CPU and DSA port(s), and the other ports. | |
d827e88a | 2640 | */ |
b4e48c50 | 2641 | err = mv88e6xxx_port_set_fid(chip, port, 0); |
0e7b9925 AL |
2642 | if (err) |
2643 | return err; | |
2db9ce1f | 2644 | |
0e7b9925 AL |
2645 | err = _mv88e6xxx_port_based_vlan_map(chip, port); |
2646 | if (err) | |
2647 | return err; | |
d827e88a GR |
2648 | |
2649 | /* Default VLAN ID and priority: don't set a default VLAN | |
2650 | * ID, and set the default packet priority to zero. | |
2651 | */ | |
0e7b9925 | 2652 | return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000); |
dbde9e66 AL |
2653 | } |
2654 | ||
aa0938c6 | 2655 | static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) |
3b4caa1b VD |
2656 | { |
2657 | int err; | |
2658 | ||
a935c052 | 2659 | err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]); |
3b4caa1b VD |
2660 | if (err) |
2661 | return err; | |
2662 | ||
a935c052 | 2663 | err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); |
3b4caa1b VD |
2664 | if (err) |
2665 | return err; | |
2666 | ||
a935c052 VD |
2667 | err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); |
2668 | if (err) | |
2669 | return err; | |
2670 | ||
2671 | return 0; | |
3b4caa1b VD |
2672 | } |
2673 | ||
acddbd21 VD |
2674 | static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip, |
2675 | unsigned int msecs) | |
2676 | { | |
2677 | const unsigned int coeff = chip->info->age_time_coeff; | |
2678 | const unsigned int min = 0x01 * coeff; | |
2679 | const unsigned int max = 0xff * coeff; | |
2680 | u8 age_time; | |
2681 | u16 val; | |
2682 | int err; | |
2683 | ||
2684 | if (msecs < min || msecs > max) | |
2685 | return -ERANGE; | |
2686 | ||
2687 | /* Round to nearest multiple of coeff */ | |
2688 | age_time = (msecs + coeff / 2) / coeff; | |
2689 | ||
a935c052 | 2690 | err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val); |
acddbd21 VD |
2691 | if (err) |
2692 | return err; | |
2693 | ||
2694 | /* AgeTime is 11:4 bits */ | |
2695 | val &= ~0xff0; | |
2696 | val |= age_time << 4; | |
2697 | ||
a935c052 | 2698 | return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val); |
acddbd21 VD |
2699 | } |
2700 | ||
2cfcd964 VD |
2701 | static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, |
2702 | unsigned int ageing_time) | |
2703 | { | |
04bed143 | 2704 | struct mv88e6xxx_chip *chip = ds->priv; |
2cfcd964 VD |
2705 | int err; |
2706 | ||
2707 | mutex_lock(&chip->reg_lock); | |
2708 | err = mv88e6xxx_g1_set_age_time(chip, ageing_time); | |
2709 | mutex_unlock(&chip->reg_lock); | |
2710 | ||
2711 | return err; | |
2712 | } | |
2713 | ||
9729934c | 2714 | static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) |
acdaffcc | 2715 | { |
fad09c73 | 2716 | struct dsa_switch *ds = chip->ds; |
b0745e87 | 2717 | u32 upstream_port = dsa_upstream_port(ds); |
119477bd | 2718 | u16 reg; |
552238b5 | 2719 | int err; |
54d792f2 | 2720 | |
119477bd VD |
2721 | /* Enable the PHY Polling Unit if present, don't discard any packets, |
2722 | * and mask all interrupt sources. | |
2723 | */ | |
dc30c35b AL |
2724 | err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®); |
2725 | if (err < 0) | |
2726 | return err; | |
2727 | ||
2728 | reg &= ~GLOBAL_CONTROL_PPU_ENABLE; | |
fad09c73 VD |
2729 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) || |
2730 | mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE)) | |
119477bd VD |
2731 | reg |= GLOBAL_CONTROL_PPU_ENABLE; |
2732 | ||
a935c052 | 2733 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg); |
119477bd VD |
2734 | if (err) |
2735 | return err; | |
2736 | ||
b0745e87 VD |
2737 | /* Configure the upstream port, and configure it as the port to which |
2738 | * ingress and egress and ARP monitor frames are to be sent. | |
2739 | */ | |
2740 | reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT | | |
2741 | upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT | | |
2742 | upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT; | |
a935c052 | 2743 | err = mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg); |
b0745e87 VD |
2744 | if (err) |
2745 | return err; | |
2746 | ||
50484ff4 | 2747 | /* Disable remote management, and set the switch's DSA device number. */ |
a935c052 VD |
2748 | err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2, |
2749 | GLOBAL_CONTROL_2_MULTIPLE_CASCADE | | |
2750 | (ds->index & 0x1f)); | |
50484ff4 VD |
2751 | if (err) |
2752 | return err; | |
2753 | ||
acddbd21 VD |
2754 | /* Clear all the VTU and STU entries */ |
2755 | err = _mv88e6xxx_vtu_stu_flush(chip); | |
2756 | if (err < 0) | |
2757 | return err; | |
2758 | ||
54d792f2 AL |
2759 | /* Set the default address aging time to 5 minutes, and |
2760 | * enable address learn messages to be sent to all message | |
2761 | * ports. | |
2762 | */ | |
a935c052 VD |
2763 | err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, |
2764 | GLOBAL_ATU_CONTROL_LEARN2ALL); | |
48ace4ef | 2765 | if (err) |
08a01261 | 2766 | return err; |
54d792f2 | 2767 | |
acddbd21 VD |
2768 | err = mv88e6xxx_g1_set_age_time(chip, 300000); |
2769 | if (err) | |
9729934c VD |
2770 | return err; |
2771 | ||
2772 | /* Clear all ATU entries */ | |
2773 | err = _mv88e6xxx_atu_flush(chip, 0, true); | |
2774 | if (err) | |
2775 | return err; | |
2776 | ||
54d792f2 | 2777 | /* Configure the IP ToS mapping registers. */ |
a935c052 | 2778 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000); |
48ace4ef | 2779 | if (err) |
08a01261 | 2780 | return err; |
a935c052 | 2781 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000); |
48ace4ef | 2782 | if (err) |
08a01261 | 2783 | return err; |
a935c052 | 2784 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555); |
48ace4ef | 2785 | if (err) |
08a01261 | 2786 | return err; |
a935c052 | 2787 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555); |
48ace4ef | 2788 | if (err) |
08a01261 | 2789 | return err; |
a935c052 | 2790 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa); |
48ace4ef | 2791 | if (err) |
08a01261 | 2792 | return err; |
a935c052 | 2793 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa); |
48ace4ef | 2794 | if (err) |
08a01261 | 2795 | return err; |
a935c052 | 2796 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff); |
48ace4ef | 2797 | if (err) |
08a01261 | 2798 | return err; |
a935c052 | 2799 | err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff); |
48ace4ef | 2800 | if (err) |
08a01261 | 2801 | return err; |
54d792f2 AL |
2802 | |
2803 | /* Configure the IEEE 802.1p priority mapping register. */ | |
a935c052 | 2804 | err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41); |
48ace4ef | 2805 | if (err) |
08a01261 | 2806 | return err; |
54d792f2 | 2807 | |
de227387 AL |
2808 | /* Initialize the statistics unit */ |
2809 | err = mv88e6xxx_stats_set_histogram(chip); | |
2810 | if (err) | |
2811 | return err; | |
2812 | ||
9729934c | 2813 | /* Clear the statistics counters for all ports */ |
a935c052 VD |
2814 | err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP, |
2815 | GLOBAL_STATS_OP_FLUSH_ALL); | |
9729934c VD |
2816 | if (err) |
2817 | return err; | |
2818 | ||
2819 | /* Wait for the flush to complete. */ | |
2820 | err = _mv88e6xxx_stats_wait(chip); | |
2821 | if (err) | |
2822 | return err; | |
2823 | ||
2824 | return 0; | |
2825 | } | |
2826 | ||
f81ec90f | 2827 | static int mv88e6xxx_setup(struct dsa_switch *ds) |
08a01261 | 2828 | { |
04bed143 | 2829 | struct mv88e6xxx_chip *chip = ds->priv; |
08a01261 | 2830 | int err; |
a1a6a4d1 VD |
2831 | int i; |
2832 | ||
fad09c73 VD |
2833 | chip->ds = ds; |
2834 | ds->slave_mii_bus = chip->mdio_bus; | |
08a01261 | 2835 | |
fad09c73 | 2836 | mutex_lock(&chip->reg_lock); |
08a01261 | 2837 | |
9729934c | 2838 | /* Setup Switch Port Registers */ |
370b4ffb | 2839 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { |
9729934c VD |
2840 | err = mv88e6xxx_setup_port(chip, i); |
2841 | if (err) | |
2842 | goto unlock; | |
2843 | } | |
2844 | ||
2845 | /* Setup Switch Global 1 Registers */ | |
2846 | err = mv88e6xxx_g1_setup(chip); | |
a1a6a4d1 VD |
2847 | if (err) |
2848 | goto unlock; | |
2849 | ||
9729934c VD |
2850 | /* Setup Switch Global 2 Registers */ |
2851 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) { | |
2852 | err = mv88e6xxx_g2_setup(chip); | |
a1a6a4d1 VD |
2853 | if (err) |
2854 | goto unlock; | |
2855 | } | |
08a01261 | 2856 | |
6b17e864 | 2857 | unlock: |
fad09c73 | 2858 | mutex_unlock(&chip->reg_lock); |
db687a56 | 2859 | |
48ace4ef | 2860 | return err; |
54d792f2 AL |
2861 | } |
2862 | ||
3b4caa1b VD |
2863 | static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr) |
2864 | { | |
04bed143 | 2865 | struct mv88e6xxx_chip *chip = ds->priv; |
3b4caa1b VD |
2866 | int err; |
2867 | ||
b073d4e2 VD |
2868 | if (!chip->info->ops->set_switch_mac) |
2869 | return -EOPNOTSUPP; | |
3b4caa1b | 2870 | |
b073d4e2 VD |
2871 | mutex_lock(&chip->reg_lock); |
2872 | err = chip->info->ops->set_switch_mac(chip, addr); | |
3b4caa1b VD |
2873 | mutex_unlock(&chip->reg_lock); |
2874 | ||
2875 | return err; | |
2876 | } | |
2877 | ||
e57e5e77 | 2878 | static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) |
fd3a0ee4 | 2879 | { |
fad09c73 | 2880 | struct mv88e6xxx_chip *chip = bus->priv; |
e57e5e77 VD |
2881 | u16 val; |
2882 | int err; | |
fd3a0ee4 | 2883 | |
370b4ffb | 2884 | if (phy >= mv88e6xxx_num_ports(chip)) |
158bc065 | 2885 | return 0xffff; |
fd3a0ee4 | 2886 | |
fad09c73 | 2887 | mutex_lock(&chip->reg_lock); |
e57e5e77 | 2888 | err = mv88e6xxx_phy_read(chip, phy, reg, &val); |
fad09c73 | 2889 | mutex_unlock(&chip->reg_lock); |
e57e5e77 VD |
2890 | |
2891 | return err ? err : val; | |
fd3a0ee4 AL |
2892 | } |
2893 | ||
e57e5e77 | 2894 | static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) |
fd3a0ee4 | 2895 | { |
fad09c73 | 2896 | struct mv88e6xxx_chip *chip = bus->priv; |
e57e5e77 | 2897 | int err; |
fd3a0ee4 | 2898 | |
370b4ffb | 2899 | if (phy >= mv88e6xxx_num_ports(chip)) |
158bc065 | 2900 | return 0xffff; |
fd3a0ee4 | 2901 | |
fad09c73 | 2902 | mutex_lock(&chip->reg_lock); |
e57e5e77 | 2903 | err = mv88e6xxx_phy_write(chip, phy, reg, val); |
fad09c73 | 2904 | mutex_unlock(&chip->reg_lock); |
e57e5e77 VD |
2905 | |
2906 | return err; | |
fd3a0ee4 AL |
2907 | } |
2908 | ||
fad09c73 | 2909 | static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, |
b516d453 AL |
2910 | struct device_node *np) |
2911 | { | |
2912 | static int index; | |
2913 | struct mii_bus *bus; | |
2914 | int err; | |
2915 | ||
b516d453 | 2916 | if (np) |
fad09c73 | 2917 | chip->mdio_np = of_get_child_by_name(np, "mdio"); |
b516d453 | 2918 | |
fad09c73 | 2919 | bus = devm_mdiobus_alloc(chip->dev); |
b516d453 AL |
2920 | if (!bus) |
2921 | return -ENOMEM; | |
2922 | ||
fad09c73 | 2923 | bus->priv = (void *)chip; |
b516d453 AL |
2924 | if (np) { |
2925 | bus->name = np->full_name; | |
2926 | snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name); | |
2927 | } else { | |
2928 | bus->name = "mv88e6xxx SMI"; | |
2929 | snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); | |
2930 | } | |
2931 | ||
2932 | bus->read = mv88e6xxx_mdio_read; | |
2933 | bus->write = mv88e6xxx_mdio_write; | |
fad09c73 | 2934 | bus->parent = chip->dev; |
b516d453 | 2935 | |
fad09c73 VD |
2936 | if (chip->mdio_np) |
2937 | err = of_mdiobus_register(bus, chip->mdio_np); | |
b516d453 AL |
2938 | else |
2939 | err = mdiobus_register(bus); | |
2940 | if (err) { | |
fad09c73 | 2941 | dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); |
b516d453 AL |
2942 | goto out; |
2943 | } | |
fad09c73 | 2944 | chip->mdio_bus = bus; |
b516d453 AL |
2945 | |
2946 | return 0; | |
2947 | ||
2948 | out: | |
fad09c73 VD |
2949 | if (chip->mdio_np) |
2950 | of_node_put(chip->mdio_np); | |
b516d453 AL |
2951 | |
2952 | return err; | |
2953 | } | |
2954 | ||
fad09c73 | 2955 | static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip) |
b516d453 AL |
2956 | |
2957 | { | |
fad09c73 | 2958 | struct mii_bus *bus = chip->mdio_bus; |
b516d453 AL |
2959 | |
2960 | mdiobus_unregister(bus); | |
2961 | ||
fad09c73 VD |
2962 | if (chip->mdio_np) |
2963 | of_node_put(chip->mdio_np); | |
b516d453 AL |
2964 | } |
2965 | ||
c22995c5 GR |
2966 | #ifdef CONFIG_NET_DSA_HWMON |
2967 | ||
2968 | static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp) | |
2969 | { | |
04bed143 | 2970 | struct mv88e6xxx_chip *chip = ds->priv; |
9c93829c | 2971 | u16 val; |
c22995c5 | 2972 | int ret; |
c22995c5 GR |
2973 | |
2974 | *temp = 0; | |
2975 | ||
fad09c73 | 2976 | mutex_lock(&chip->reg_lock); |
c22995c5 | 2977 | |
9c93829c | 2978 | ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6); |
c22995c5 GR |
2979 | if (ret < 0) |
2980 | goto error; | |
2981 | ||
2982 | /* Enable temperature sensor */ | |
9c93829c | 2983 | ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val); |
c22995c5 GR |
2984 | if (ret < 0) |
2985 | goto error; | |
2986 | ||
9c93829c | 2987 | ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5)); |
c22995c5 GR |
2988 | if (ret < 0) |
2989 | goto error; | |
2990 | ||
2991 | /* Wait for temperature to stabilize */ | |
2992 | usleep_range(10000, 12000); | |
2993 | ||
9c93829c VD |
2994 | ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val); |
2995 | if (ret < 0) | |
c22995c5 | 2996 | goto error; |
c22995c5 GR |
2997 | |
2998 | /* Disable temperature sensor */ | |
9c93829c | 2999 | ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5)); |
c22995c5 GR |
3000 | if (ret < 0) |
3001 | goto error; | |
3002 | ||
3003 | *temp = ((val & 0x1f) - 5) * 5; | |
3004 | ||
3005 | error: | |
9c93829c | 3006 | mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0); |
fad09c73 | 3007 | mutex_unlock(&chip->reg_lock); |
c22995c5 GR |
3008 | return ret; |
3009 | } | |
3010 | ||
3011 | static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp) | |
3012 | { | |
04bed143 | 3013 | struct mv88e6xxx_chip *chip = ds->priv; |
fad09c73 | 3014 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
9c93829c | 3015 | u16 val; |
c22995c5 GR |
3016 | int ret; |
3017 | ||
3018 | *temp = 0; | |
3019 | ||
9c93829c VD |
3020 | mutex_lock(&chip->reg_lock); |
3021 | ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val); | |
3022 | mutex_unlock(&chip->reg_lock); | |
c22995c5 GR |
3023 | if (ret < 0) |
3024 | return ret; | |
3025 | ||
9c93829c | 3026 | *temp = (val & 0xff) - 25; |
c22995c5 GR |
3027 | |
3028 | return 0; | |
3029 | } | |
3030 | ||
f81ec90f | 3031 | static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) |
c22995c5 | 3032 | { |
04bed143 | 3033 | struct mv88e6xxx_chip *chip = ds->priv; |
158bc065 | 3034 | |
fad09c73 | 3035 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP)) |
6594f615 VD |
3036 | return -EOPNOTSUPP; |
3037 | ||
fad09c73 | 3038 | if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip)) |
c22995c5 GR |
3039 | return mv88e63xx_get_temp(ds, temp); |
3040 | ||
3041 | return mv88e61xx_get_temp(ds, temp); | |
3042 | } | |
3043 | ||
f81ec90f | 3044 | static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp) |
c22995c5 | 3045 | { |
04bed143 | 3046 | struct mv88e6xxx_chip *chip = ds->priv; |
fad09c73 | 3047 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
9c93829c | 3048 | u16 val; |
c22995c5 GR |
3049 | int ret; |
3050 | ||
fad09c73 | 3051 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) |
c22995c5 GR |
3052 | return -EOPNOTSUPP; |
3053 | ||
3054 | *temp = 0; | |
3055 | ||
9c93829c VD |
3056 | mutex_lock(&chip->reg_lock); |
3057 | ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); | |
3058 | mutex_unlock(&chip->reg_lock); | |
c22995c5 GR |
3059 | if (ret < 0) |
3060 | return ret; | |
3061 | ||
9c93829c | 3062 | *temp = (((val >> 8) & 0x1f) * 5) - 25; |
c22995c5 GR |
3063 | |
3064 | return 0; | |
3065 | } | |
3066 | ||
f81ec90f | 3067 | static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp) |
c22995c5 | 3068 | { |
04bed143 | 3069 | struct mv88e6xxx_chip *chip = ds->priv; |
fad09c73 | 3070 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
9c93829c VD |
3071 | u16 val; |
3072 | int err; | |
c22995c5 | 3073 | |
fad09c73 | 3074 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) |
c22995c5 GR |
3075 | return -EOPNOTSUPP; |
3076 | ||
9c93829c VD |
3077 | mutex_lock(&chip->reg_lock); |
3078 | err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); | |
3079 | if (err) | |
3080 | goto unlock; | |
c22995c5 | 3081 | temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); |
9c93829c VD |
3082 | err = mv88e6xxx_phy_page_write(chip, phy, 6, 26, |
3083 | (val & 0xe0ff) | (temp << 8)); | |
3084 | unlock: | |
3085 | mutex_unlock(&chip->reg_lock); | |
3086 | ||
3087 | return err; | |
c22995c5 GR |
3088 | } |
3089 | ||
f81ec90f | 3090 | static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm) |
c22995c5 | 3091 | { |
04bed143 | 3092 | struct mv88e6xxx_chip *chip = ds->priv; |
fad09c73 | 3093 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
9c93829c | 3094 | u16 val; |
c22995c5 GR |
3095 | int ret; |
3096 | ||
fad09c73 | 3097 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) |
c22995c5 GR |
3098 | return -EOPNOTSUPP; |
3099 | ||
3100 | *alarm = false; | |
3101 | ||
9c93829c VD |
3102 | mutex_lock(&chip->reg_lock); |
3103 | ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); | |
3104 | mutex_unlock(&chip->reg_lock); | |
c22995c5 GR |
3105 | if (ret < 0) |
3106 | return ret; | |
3107 | ||
9c93829c | 3108 | *alarm = !!(val & 0x40); |
c22995c5 GR |
3109 | |
3110 | return 0; | |
3111 | } | |
3112 | #endif /* CONFIG_NET_DSA_HWMON */ | |
3113 | ||
855b1932 VD |
3114 | static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) |
3115 | { | |
04bed143 | 3116 | struct mv88e6xxx_chip *chip = ds->priv; |
855b1932 VD |
3117 | |
3118 | return chip->eeprom_len; | |
3119 | } | |
3120 | ||
855b1932 VD |
3121 | static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, |
3122 | struct ethtool_eeprom *eeprom, u8 *data) | |
3123 | { | |
04bed143 | 3124 | struct mv88e6xxx_chip *chip = ds->priv; |
855b1932 VD |
3125 | int err; |
3126 | ||
ee4dc2e7 VD |
3127 | if (!chip->info->ops->get_eeprom) |
3128 | return -EOPNOTSUPP; | |
855b1932 | 3129 | |
ee4dc2e7 VD |
3130 | mutex_lock(&chip->reg_lock); |
3131 | err = chip->info->ops->get_eeprom(chip, eeprom, data); | |
855b1932 VD |
3132 | mutex_unlock(&chip->reg_lock); |
3133 | ||
3134 | if (err) | |
3135 | return err; | |
3136 | ||
3137 | eeprom->magic = 0xc3ec4951; | |
3138 | ||
3139 | return 0; | |
3140 | } | |
3141 | ||
855b1932 VD |
3142 | static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, |
3143 | struct ethtool_eeprom *eeprom, u8 *data) | |
3144 | { | |
04bed143 | 3145 | struct mv88e6xxx_chip *chip = ds->priv; |
855b1932 VD |
3146 | int err; |
3147 | ||
ee4dc2e7 VD |
3148 | if (!chip->info->ops->set_eeprom) |
3149 | return -EOPNOTSUPP; | |
3150 | ||
855b1932 VD |
3151 | if (eeprom->magic != 0xc3ec4951) |
3152 | return -EINVAL; | |
3153 | ||
3154 | mutex_lock(&chip->reg_lock); | |
ee4dc2e7 | 3155 | err = chip->info->ops->set_eeprom(chip, eeprom, data); |
855b1932 VD |
3156 | mutex_unlock(&chip->reg_lock); |
3157 | ||
3158 | return err; | |
3159 | } | |
3160 | ||
b3469dd8 | 3161 | static const struct mv88e6xxx_ops mv88e6085_ops = { |
4b325d8c | 3162 | /* MV88E6XXX_FAMILY_6097 */ |
b073d4e2 | 3163 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
b3469dd8 VD |
3164 | .phy_read = mv88e6xxx_phy_ppu_read, |
3165 | .phy_write = mv88e6xxx_phy_ppu_write, | |
08ef7f10 | 3166 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3167 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3168 | .port_set_speed = mv88e6185_port_set_speed, |
a605a0fe | 3169 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
b3469dd8 VD |
3170 | }; |
3171 | ||
3172 | static const struct mv88e6xxx_ops mv88e6095_ops = { | |
4b325d8c | 3173 | /* MV88E6XXX_FAMILY_6095 */ |
b073d4e2 | 3174 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
b3469dd8 VD |
3175 | .phy_read = mv88e6xxx_phy_ppu_read, |
3176 | .phy_write = mv88e6xxx_phy_ppu_write, | |
08ef7f10 | 3177 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3178 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3179 | .port_set_speed = mv88e6185_port_set_speed, |
a605a0fe | 3180 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
b3469dd8 VD |
3181 | }; |
3182 | ||
3183 | static const struct mv88e6xxx_ops mv88e6123_ops = { | |
4b325d8c | 3184 | /* MV88E6XXX_FAMILY_6165 */ |
b073d4e2 | 3185 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3186 | .phy_read = mv88e6xxx_read, |
3187 | .phy_write = mv88e6xxx_write, | |
08ef7f10 | 3188 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3189 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3190 | .port_set_speed = mv88e6185_port_set_speed, |
a605a0fe | 3191 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
b3469dd8 VD |
3192 | }; |
3193 | ||
3194 | static const struct mv88e6xxx_ops mv88e6131_ops = { | |
4b325d8c | 3195 | /* MV88E6XXX_FAMILY_6185 */ |
b073d4e2 | 3196 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
b3469dd8 VD |
3197 | .phy_read = mv88e6xxx_phy_ppu_read, |
3198 | .phy_write = mv88e6xxx_phy_ppu_write, | |
08ef7f10 | 3199 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3200 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3201 | .port_set_speed = mv88e6185_port_set_speed, |
a605a0fe | 3202 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
b3469dd8 VD |
3203 | }; |
3204 | ||
3205 | static const struct mv88e6xxx_ops mv88e6161_ops = { | |
4b325d8c | 3206 | /* MV88E6XXX_FAMILY_6165 */ |
b073d4e2 | 3207 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3208 | .phy_read = mv88e6xxx_read, |
3209 | .phy_write = mv88e6xxx_write, | |
08ef7f10 | 3210 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3211 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3212 | .port_set_speed = mv88e6185_port_set_speed, |
a605a0fe | 3213 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
b3469dd8 VD |
3214 | }; |
3215 | ||
3216 | static const struct mv88e6xxx_ops mv88e6165_ops = { | |
4b325d8c | 3217 | /* MV88E6XXX_FAMILY_6165 */ |
b073d4e2 | 3218 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3219 | .phy_read = mv88e6xxx_read, |
3220 | .phy_write = mv88e6xxx_write, | |
08ef7f10 | 3221 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3222 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3223 | .port_set_speed = mv88e6185_port_set_speed, |
a605a0fe | 3224 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
b3469dd8 VD |
3225 | }; |
3226 | ||
3227 | static const struct mv88e6xxx_ops mv88e6171_ops = { | |
4b325d8c | 3228 | /* MV88E6XXX_FAMILY_6351 */ |
b073d4e2 | 3229 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3230 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3231 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3232 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3233 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
94d66ae6 | 3234 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3235 | .port_set_speed = mv88e6185_port_set_speed, |
a605a0fe | 3236 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
b3469dd8 VD |
3237 | }; |
3238 | ||
3239 | static const struct mv88e6xxx_ops mv88e6172_ops = { | |
4b325d8c | 3240 | /* MV88E6XXX_FAMILY_6352 */ |
ee4dc2e7 VD |
3241 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3242 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3243 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3244 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3245 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3246 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3247 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 3248 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3249 | .port_set_speed = mv88e6352_port_set_speed, |
a605a0fe | 3250 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
b3469dd8 VD |
3251 | }; |
3252 | ||
3253 | static const struct mv88e6xxx_ops mv88e6175_ops = { | |
4b325d8c | 3254 | /* MV88E6XXX_FAMILY_6351 */ |
b073d4e2 | 3255 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3256 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3257 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3258 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3259 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
94d66ae6 | 3260 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3261 | .port_set_speed = mv88e6185_port_set_speed, |
a605a0fe | 3262 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
b3469dd8 VD |
3263 | }; |
3264 | ||
3265 | static const struct mv88e6xxx_ops mv88e6176_ops = { | |
4b325d8c | 3266 | /* MV88E6XXX_FAMILY_6352 */ |
ee4dc2e7 VD |
3267 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3268 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3269 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3270 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3271 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3272 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3273 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 3274 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3275 | .port_set_speed = mv88e6352_port_set_speed, |
a605a0fe | 3276 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
b3469dd8 VD |
3277 | }; |
3278 | ||
3279 | static const struct mv88e6xxx_ops mv88e6185_ops = { | |
4b325d8c | 3280 | /* MV88E6XXX_FAMILY_6185 */ |
b073d4e2 | 3281 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
b3469dd8 VD |
3282 | .phy_read = mv88e6xxx_phy_ppu_read, |
3283 | .phy_write = mv88e6xxx_phy_ppu_write, | |
08ef7f10 | 3284 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3285 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3286 | .port_set_speed = mv88e6185_port_set_speed, |
a605a0fe | 3287 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
b3469dd8 VD |
3288 | }; |
3289 | ||
1a3b39ec | 3290 | static const struct mv88e6xxx_ops mv88e6190_ops = { |
4b325d8c | 3291 | /* MV88E6XXX_FAMILY_6390 */ |
1a3b39ec AL |
3292 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3293 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3294 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3295 | .port_set_link = mv88e6xxx_port_set_link, | |
3296 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3297 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
3298 | .port_set_speed = mv88e6390_port_set_speed, | |
79523473 | 3299 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 3300 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
1a3b39ec AL |
3301 | }; |
3302 | ||
3303 | static const struct mv88e6xxx_ops mv88e6190x_ops = { | |
4b325d8c | 3304 | /* MV88E6XXX_FAMILY_6390 */ |
1a3b39ec AL |
3305 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3306 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3307 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3308 | .port_set_link = mv88e6xxx_port_set_link, | |
3309 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3310 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
3311 | .port_set_speed = mv88e6390x_port_set_speed, | |
79523473 | 3312 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 3313 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
1a3b39ec AL |
3314 | }; |
3315 | ||
3316 | static const struct mv88e6xxx_ops mv88e6191_ops = { | |
4b325d8c | 3317 | /* MV88E6XXX_FAMILY_6390 */ |
1a3b39ec AL |
3318 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3319 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3320 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3321 | .port_set_link = mv88e6xxx_port_set_link, | |
3322 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3323 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
3324 | .port_set_speed = mv88e6390_port_set_speed, | |
79523473 | 3325 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 3326 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
1a3b39ec AL |
3327 | }; |
3328 | ||
b3469dd8 | 3329 | static const struct mv88e6xxx_ops mv88e6240_ops = { |
4b325d8c | 3330 | /* MV88E6XXX_FAMILY_6352 */ |
ee4dc2e7 VD |
3331 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3332 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3333 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3334 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3335 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3336 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3337 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 3338 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3339 | .port_set_speed = mv88e6352_port_set_speed, |
a605a0fe | 3340 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
b3469dd8 VD |
3341 | }; |
3342 | ||
1a3b39ec | 3343 | static const struct mv88e6xxx_ops mv88e6290_ops = { |
4b325d8c | 3344 | /* MV88E6XXX_FAMILY_6390 */ |
1a3b39ec AL |
3345 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3346 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3347 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3348 | .port_set_link = mv88e6xxx_port_set_link, | |
3349 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3350 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
3351 | .port_set_speed = mv88e6390_port_set_speed, | |
79523473 | 3352 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 3353 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
1a3b39ec AL |
3354 | }; |
3355 | ||
b3469dd8 | 3356 | static const struct mv88e6xxx_ops mv88e6320_ops = { |
4b325d8c | 3357 | /* MV88E6XXX_FAMILY_6320 */ |
ee4dc2e7 VD |
3358 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3359 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3360 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3361 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3362 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3363 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3364 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3365 | .port_set_speed = mv88e6185_port_set_speed, |
a605a0fe | 3366 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
b3469dd8 VD |
3367 | }; |
3368 | ||
3369 | static const struct mv88e6xxx_ops mv88e6321_ops = { | |
4b325d8c | 3370 | /* MV88E6XXX_FAMILY_6321 */ |
ee4dc2e7 VD |
3371 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3372 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3373 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3374 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3375 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3376 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3377 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3378 | .port_set_speed = mv88e6185_port_set_speed, |
a605a0fe | 3379 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
b3469dd8 VD |
3380 | }; |
3381 | ||
3382 | static const struct mv88e6xxx_ops mv88e6350_ops = { | |
4b325d8c | 3383 | /* MV88E6XXX_FAMILY_6351 */ |
b073d4e2 | 3384 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3385 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3386 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3387 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3388 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
94d66ae6 | 3389 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3390 | .port_set_speed = mv88e6185_port_set_speed, |
a605a0fe | 3391 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
b3469dd8 VD |
3392 | }; |
3393 | ||
3394 | static const struct mv88e6xxx_ops mv88e6351_ops = { | |
4b325d8c | 3395 | /* MV88E6XXX_FAMILY_6351 */ |
b073d4e2 | 3396 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3397 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3398 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3399 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3400 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
94d66ae6 | 3401 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3402 | .port_set_speed = mv88e6185_port_set_speed, |
a605a0fe | 3403 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
b3469dd8 VD |
3404 | }; |
3405 | ||
3406 | static const struct mv88e6xxx_ops mv88e6352_ops = { | |
4b325d8c | 3407 | /* MV88E6XXX_FAMILY_6352 */ |
ee4dc2e7 VD |
3408 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3409 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3410 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3411 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3412 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3413 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3414 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 3415 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3416 | .port_set_speed = mv88e6352_port_set_speed, |
a605a0fe | 3417 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
b3469dd8 VD |
3418 | }; |
3419 | ||
1a3b39ec | 3420 | static const struct mv88e6xxx_ops mv88e6390_ops = { |
4b325d8c | 3421 | /* MV88E6XXX_FAMILY_6390 */ |
1a3b39ec AL |
3422 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3423 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3424 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3425 | .port_set_link = mv88e6xxx_port_set_link, | |
3426 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3427 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
3428 | .port_set_speed = mv88e6390_port_set_speed, | |
79523473 | 3429 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 3430 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
1a3b39ec AL |
3431 | }; |
3432 | ||
3433 | static const struct mv88e6xxx_ops mv88e6390x_ops = { | |
4b325d8c | 3434 | /* MV88E6XXX_FAMILY_6390 */ |
1a3b39ec AL |
3435 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3436 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3437 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3438 | .port_set_link = mv88e6xxx_port_set_link, | |
3439 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3440 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
3441 | .port_set_speed = mv88e6390x_port_set_speed, | |
79523473 | 3442 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 3443 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
1a3b39ec AL |
3444 | }; |
3445 | ||
3446 | static const struct mv88e6xxx_ops mv88e6391_ops = { | |
4b325d8c | 3447 | /* MV88E6XXX_FAMILY_6390 */ |
1a3b39ec AL |
3448 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3449 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3450 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3451 | .port_set_link = mv88e6xxx_port_set_link, | |
3452 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3453 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
3454 | .port_set_speed = mv88e6390_port_set_speed, | |
79523473 | 3455 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 3456 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
1a3b39ec AL |
3457 | }; |
3458 | ||
f81ec90f VD |
3459 | static const struct mv88e6xxx_info mv88e6xxx_table[] = { |
3460 | [MV88E6085] = { | |
3461 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6085, | |
3462 | .family = MV88E6XXX_FAMILY_6097, | |
3463 | .name = "Marvell 88E6085", | |
3464 | .num_databases = 4096, | |
3465 | .num_ports = 10, | |
9dddd478 | 3466 | .port_base_addr = 0x10, |
a935c052 | 3467 | .global1_addr = 0x1b, |
acddbd21 | 3468 | .age_time_coeff = 15000, |
dc30c35b | 3469 | .g1_irqs = 8, |
f81ec90f | 3470 | .flags = MV88E6XXX_FLAGS_FAMILY_6097, |
b3469dd8 | 3471 | .ops = &mv88e6085_ops, |
f81ec90f VD |
3472 | }, |
3473 | ||
3474 | [MV88E6095] = { | |
3475 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6095, | |
3476 | .family = MV88E6XXX_FAMILY_6095, | |
3477 | .name = "Marvell 88E6095/88E6095F", | |
3478 | .num_databases = 256, | |
3479 | .num_ports = 11, | |
9dddd478 | 3480 | .port_base_addr = 0x10, |
a935c052 | 3481 | .global1_addr = 0x1b, |
acddbd21 | 3482 | .age_time_coeff = 15000, |
dc30c35b | 3483 | .g1_irqs = 8, |
f81ec90f | 3484 | .flags = MV88E6XXX_FLAGS_FAMILY_6095, |
b3469dd8 | 3485 | .ops = &mv88e6095_ops, |
f81ec90f VD |
3486 | }, |
3487 | ||
3488 | [MV88E6123] = { | |
3489 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6123, | |
3490 | .family = MV88E6XXX_FAMILY_6165, | |
3491 | .name = "Marvell 88E6123", | |
3492 | .num_databases = 4096, | |
3493 | .num_ports = 3, | |
9dddd478 | 3494 | .port_base_addr = 0x10, |
a935c052 | 3495 | .global1_addr = 0x1b, |
acddbd21 | 3496 | .age_time_coeff = 15000, |
dc30c35b | 3497 | .g1_irqs = 9, |
f81ec90f | 3498 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
b3469dd8 | 3499 | .ops = &mv88e6123_ops, |
f81ec90f VD |
3500 | }, |
3501 | ||
3502 | [MV88E6131] = { | |
3503 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6131, | |
3504 | .family = MV88E6XXX_FAMILY_6185, | |
3505 | .name = "Marvell 88E6131", | |
3506 | .num_databases = 256, | |
3507 | .num_ports = 8, | |
9dddd478 | 3508 | .port_base_addr = 0x10, |
a935c052 | 3509 | .global1_addr = 0x1b, |
acddbd21 | 3510 | .age_time_coeff = 15000, |
dc30c35b | 3511 | .g1_irqs = 9, |
f81ec90f | 3512 | .flags = MV88E6XXX_FLAGS_FAMILY_6185, |
b3469dd8 | 3513 | .ops = &mv88e6131_ops, |
f81ec90f VD |
3514 | }, |
3515 | ||
3516 | [MV88E6161] = { | |
3517 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6161, | |
3518 | .family = MV88E6XXX_FAMILY_6165, | |
3519 | .name = "Marvell 88E6161", | |
3520 | .num_databases = 4096, | |
3521 | .num_ports = 6, | |
9dddd478 | 3522 | .port_base_addr = 0x10, |
a935c052 | 3523 | .global1_addr = 0x1b, |
acddbd21 | 3524 | .age_time_coeff = 15000, |
dc30c35b | 3525 | .g1_irqs = 9, |
f81ec90f | 3526 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
b3469dd8 | 3527 | .ops = &mv88e6161_ops, |
f81ec90f VD |
3528 | }, |
3529 | ||
3530 | [MV88E6165] = { | |
3531 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6165, | |
3532 | .family = MV88E6XXX_FAMILY_6165, | |
3533 | .name = "Marvell 88E6165", | |
3534 | .num_databases = 4096, | |
3535 | .num_ports = 6, | |
9dddd478 | 3536 | .port_base_addr = 0x10, |
a935c052 | 3537 | .global1_addr = 0x1b, |
acddbd21 | 3538 | .age_time_coeff = 15000, |
dc30c35b | 3539 | .g1_irqs = 9, |
f81ec90f | 3540 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
b3469dd8 | 3541 | .ops = &mv88e6165_ops, |
f81ec90f VD |
3542 | }, |
3543 | ||
3544 | [MV88E6171] = { | |
3545 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6171, | |
3546 | .family = MV88E6XXX_FAMILY_6351, | |
3547 | .name = "Marvell 88E6171", | |
3548 | .num_databases = 4096, | |
3549 | .num_ports = 7, | |
9dddd478 | 3550 | .port_base_addr = 0x10, |
a935c052 | 3551 | .global1_addr = 0x1b, |
acddbd21 | 3552 | .age_time_coeff = 15000, |
dc30c35b | 3553 | .g1_irqs = 9, |
f81ec90f | 3554 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
b3469dd8 | 3555 | .ops = &mv88e6171_ops, |
f81ec90f VD |
3556 | }, |
3557 | ||
3558 | [MV88E6172] = { | |
3559 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6172, | |
3560 | .family = MV88E6XXX_FAMILY_6352, | |
3561 | .name = "Marvell 88E6172", | |
3562 | .num_databases = 4096, | |
3563 | .num_ports = 7, | |
9dddd478 | 3564 | .port_base_addr = 0x10, |
a935c052 | 3565 | .global1_addr = 0x1b, |
acddbd21 | 3566 | .age_time_coeff = 15000, |
dc30c35b | 3567 | .g1_irqs = 9, |
f81ec90f | 3568 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
b3469dd8 | 3569 | .ops = &mv88e6172_ops, |
f81ec90f VD |
3570 | }, |
3571 | ||
3572 | [MV88E6175] = { | |
3573 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6175, | |
3574 | .family = MV88E6XXX_FAMILY_6351, | |
3575 | .name = "Marvell 88E6175", | |
3576 | .num_databases = 4096, | |
3577 | .num_ports = 7, | |
9dddd478 | 3578 | .port_base_addr = 0x10, |
a935c052 | 3579 | .global1_addr = 0x1b, |
acddbd21 | 3580 | .age_time_coeff = 15000, |
dc30c35b | 3581 | .g1_irqs = 9, |
f81ec90f | 3582 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
b3469dd8 | 3583 | .ops = &mv88e6175_ops, |
f81ec90f VD |
3584 | }, |
3585 | ||
3586 | [MV88E6176] = { | |
3587 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6176, | |
3588 | .family = MV88E6XXX_FAMILY_6352, | |
3589 | .name = "Marvell 88E6176", | |
3590 | .num_databases = 4096, | |
3591 | .num_ports = 7, | |
9dddd478 | 3592 | .port_base_addr = 0x10, |
a935c052 | 3593 | .global1_addr = 0x1b, |
acddbd21 | 3594 | .age_time_coeff = 15000, |
dc30c35b | 3595 | .g1_irqs = 9, |
f81ec90f | 3596 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
b3469dd8 | 3597 | .ops = &mv88e6176_ops, |
f81ec90f VD |
3598 | }, |
3599 | ||
3600 | [MV88E6185] = { | |
3601 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6185, | |
3602 | .family = MV88E6XXX_FAMILY_6185, | |
3603 | .name = "Marvell 88E6185", | |
3604 | .num_databases = 256, | |
3605 | .num_ports = 10, | |
9dddd478 | 3606 | .port_base_addr = 0x10, |
a935c052 | 3607 | .global1_addr = 0x1b, |
acddbd21 | 3608 | .age_time_coeff = 15000, |
dc30c35b | 3609 | .g1_irqs = 8, |
f81ec90f | 3610 | .flags = MV88E6XXX_FLAGS_FAMILY_6185, |
b3469dd8 | 3611 | .ops = &mv88e6185_ops, |
f81ec90f VD |
3612 | }, |
3613 | ||
1a3b39ec AL |
3614 | [MV88E6190] = { |
3615 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6190, | |
3616 | .family = MV88E6XXX_FAMILY_6390, | |
3617 | .name = "Marvell 88E6190", | |
3618 | .num_databases = 4096, | |
3619 | .num_ports = 11, /* 10 + Z80 */ | |
3620 | .port_base_addr = 0x0, | |
3621 | .global1_addr = 0x1b, | |
3622 | .age_time_coeff = 15000, | |
3623 | .g1_irqs = 9, | |
3624 | .flags = MV88E6XXX_FLAGS_FAMILY_6390, | |
3625 | .ops = &mv88e6190_ops, | |
3626 | }, | |
3627 | ||
3628 | [MV88E6190X] = { | |
3629 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X, | |
3630 | .family = MV88E6XXX_FAMILY_6390, | |
3631 | .name = "Marvell 88E6190X", | |
3632 | .num_databases = 4096, | |
3633 | .num_ports = 11, /* 10 + Z80 */ | |
3634 | .port_base_addr = 0x0, | |
3635 | .global1_addr = 0x1b, | |
3636 | .age_time_coeff = 15000, | |
3637 | .g1_irqs = 9, | |
3638 | .flags = MV88E6XXX_FLAGS_FAMILY_6390, | |
3639 | .ops = &mv88e6190x_ops, | |
3640 | }, | |
3641 | ||
3642 | [MV88E6191] = { | |
3643 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6191, | |
3644 | .family = MV88E6XXX_FAMILY_6390, | |
3645 | .name = "Marvell 88E6191", | |
3646 | .num_databases = 4096, | |
3647 | .num_ports = 11, /* 10 + Z80 */ | |
3648 | .port_base_addr = 0x0, | |
3649 | .global1_addr = 0x1b, | |
3650 | .age_time_coeff = 15000, | |
3651 | .flags = MV88E6XXX_FLAGS_FAMILY_6390, | |
3652 | .ops = &mv88e6391_ops, | |
3653 | }, | |
3654 | ||
f81ec90f VD |
3655 | [MV88E6240] = { |
3656 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6240, | |
3657 | .family = MV88E6XXX_FAMILY_6352, | |
3658 | .name = "Marvell 88E6240", | |
3659 | .num_databases = 4096, | |
3660 | .num_ports = 7, | |
9dddd478 | 3661 | .port_base_addr = 0x10, |
a935c052 | 3662 | .global1_addr = 0x1b, |
acddbd21 | 3663 | .age_time_coeff = 15000, |
dc30c35b | 3664 | .g1_irqs = 9, |
f81ec90f | 3665 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
b3469dd8 | 3666 | .ops = &mv88e6240_ops, |
f81ec90f VD |
3667 | }, |
3668 | ||
1a3b39ec AL |
3669 | [MV88E6290] = { |
3670 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6290, | |
3671 | .family = MV88E6XXX_FAMILY_6390, | |
3672 | .name = "Marvell 88E6290", | |
3673 | .num_databases = 4096, | |
3674 | .num_ports = 11, /* 10 + Z80 */ | |
3675 | .port_base_addr = 0x0, | |
3676 | .global1_addr = 0x1b, | |
3677 | .age_time_coeff = 15000, | |
3678 | .g1_irqs = 9, | |
3679 | .flags = MV88E6XXX_FLAGS_FAMILY_6390, | |
3680 | .ops = &mv88e6290_ops, | |
3681 | }, | |
3682 | ||
f81ec90f VD |
3683 | [MV88E6320] = { |
3684 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6320, | |
3685 | .family = MV88E6XXX_FAMILY_6320, | |
3686 | .name = "Marvell 88E6320", | |
3687 | .num_databases = 4096, | |
3688 | .num_ports = 7, | |
9dddd478 | 3689 | .port_base_addr = 0x10, |
a935c052 | 3690 | .global1_addr = 0x1b, |
acddbd21 | 3691 | .age_time_coeff = 15000, |
dc30c35b | 3692 | .g1_irqs = 8, |
f81ec90f | 3693 | .flags = MV88E6XXX_FLAGS_FAMILY_6320, |
b3469dd8 | 3694 | .ops = &mv88e6320_ops, |
f81ec90f VD |
3695 | }, |
3696 | ||
3697 | [MV88E6321] = { | |
3698 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6321, | |
3699 | .family = MV88E6XXX_FAMILY_6320, | |
3700 | .name = "Marvell 88E6321", | |
3701 | .num_databases = 4096, | |
3702 | .num_ports = 7, | |
9dddd478 | 3703 | .port_base_addr = 0x10, |
a935c052 | 3704 | .global1_addr = 0x1b, |
acddbd21 | 3705 | .age_time_coeff = 15000, |
dc30c35b | 3706 | .g1_irqs = 8, |
f81ec90f | 3707 | .flags = MV88E6XXX_FLAGS_FAMILY_6320, |
b3469dd8 | 3708 | .ops = &mv88e6321_ops, |
f81ec90f VD |
3709 | }, |
3710 | ||
3711 | [MV88E6350] = { | |
3712 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6350, | |
3713 | .family = MV88E6XXX_FAMILY_6351, | |
3714 | .name = "Marvell 88E6350", | |
3715 | .num_databases = 4096, | |
3716 | .num_ports = 7, | |
9dddd478 | 3717 | .port_base_addr = 0x10, |
a935c052 | 3718 | .global1_addr = 0x1b, |
acddbd21 | 3719 | .age_time_coeff = 15000, |
dc30c35b | 3720 | .g1_irqs = 9, |
f81ec90f | 3721 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
b3469dd8 | 3722 | .ops = &mv88e6350_ops, |
f81ec90f VD |
3723 | }, |
3724 | ||
3725 | [MV88E6351] = { | |
3726 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6351, | |
3727 | .family = MV88E6XXX_FAMILY_6351, | |
3728 | .name = "Marvell 88E6351", | |
3729 | .num_databases = 4096, | |
3730 | .num_ports = 7, | |
9dddd478 | 3731 | .port_base_addr = 0x10, |
a935c052 | 3732 | .global1_addr = 0x1b, |
acddbd21 | 3733 | .age_time_coeff = 15000, |
dc30c35b | 3734 | .g1_irqs = 9, |
f81ec90f | 3735 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
b3469dd8 | 3736 | .ops = &mv88e6351_ops, |
f81ec90f VD |
3737 | }, |
3738 | ||
3739 | [MV88E6352] = { | |
3740 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6352, | |
3741 | .family = MV88E6XXX_FAMILY_6352, | |
3742 | .name = "Marvell 88E6352", | |
3743 | .num_databases = 4096, | |
3744 | .num_ports = 7, | |
9dddd478 | 3745 | .port_base_addr = 0x10, |
a935c052 | 3746 | .global1_addr = 0x1b, |
acddbd21 | 3747 | .age_time_coeff = 15000, |
dc30c35b | 3748 | .g1_irqs = 9, |
f81ec90f | 3749 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
b3469dd8 | 3750 | .ops = &mv88e6352_ops, |
f81ec90f | 3751 | }, |
1a3b39ec AL |
3752 | [MV88E6390] = { |
3753 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6390, | |
3754 | .family = MV88E6XXX_FAMILY_6390, | |
3755 | .name = "Marvell 88E6390", | |
3756 | .num_databases = 4096, | |
3757 | .num_ports = 11, /* 10 + Z80 */ | |
3758 | .port_base_addr = 0x0, | |
3759 | .global1_addr = 0x1b, | |
3760 | .age_time_coeff = 15000, | |
3761 | .g1_irqs = 9, | |
3762 | .flags = MV88E6XXX_FLAGS_FAMILY_6390, | |
3763 | .ops = &mv88e6390_ops, | |
3764 | }, | |
3765 | [MV88E6390X] = { | |
3766 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X, | |
3767 | .family = MV88E6XXX_FAMILY_6390, | |
3768 | .name = "Marvell 88E6390X", | |
3769 | .num_databases = 4096, | |
3770 | .num_ports = 11, /* 10 + Z80 */ | |
3771 | .port_base_addr = 0x0, | |
3772 | .global1_addr = 0x1b, | |
3773 | .age_time_coeff = 15000, | |
3774 | .g1_irqs = 9, | |
3775 | .flags = MV88E6XXX_FLAGS_FAMILY_6390, | |
3776 | .ops = &mv88e6390x_ops, | |
3777 | }, | |
f81ec90f VD |
3778 | }; |
3779 | ||
5f7c0367 | 3780 | static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) |
b9b37713 | 3781 | { |
a439c061 | 3782 | int i; |
b9b37713 | 3783 | |
5f7c0367 VD |
3784 | for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) |
3785 | if (mv88e6xxx_table[i].prod_num == prod_num) | |
3786 | return &mv88e6xxx_table[i]; | |
b9b37713 | 3787 | |
b9b37713 VD |
3788 | return NULL; |
3789 | } | |
3790 | ||
fad09c73 | 3791 | static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) |
bc46a3d5 VD |
3792 | { |
3793 | const struct mv88e6xxx_info *info; | |
8f6345b2 VD |
3794 | unsigned int prod_num, rev; |
3795 | u16 id; | |
3796 | int err; | |
bc46a3d5 | 3797 | |
8f6345b2 VD |
3798 | mutex_lock(&chip->reg_lock); |
3799 | err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id); | |
3800 | mutex_unlock(&chip->reg_lock); | |
3801 | if (err) | |
3802 | return err; | |
bc46a3d5 VD |
3803 | |
3804 | prod_num = (id & 0xfff0) >> 4; | |
3805 | rev = id & 0x000f; | |
3806 | ||
3807 | info = mv88e6xxx_lookup_info(prod_num); | |
3808 | if (!info) | |
3809 | return -ENODEV; | |
3810 | ||
caac8545 | 3811 | /* Update the compatible info with the probed one */ |
fad09c73 | 3812 | chip->info = info; |
bc46a3d5 | 3813 | |
ca070c10 VD |
3814 | err = mv88e6xxx_g2_require(chip); |
3815 | if (err) | |
3816 | return err; | |
3817 | ||
fad09c73 VD |
3818 | dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", |
3819 | chip->info->prod_num, chip->info->name, rev); | |
bc46a3d5 VD |
3820 | |
3821 | return 0; | |
3822 | } | |
3823 | ||
fad09c73 | 3824 | static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) |
469d729f | 3825 | { |
fad09c73 | 3826 | struct mv88e6xxx_chip *chip; |
469d729f | 3827 | |
fad09c73 VD |
3828 | chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); |
3829 | if (!chip) | |
469d729f VD |
3830 | return NULL; |
3831 | ||
fad09c73 | 3832 | chip->dev = dev; |
469d729f | 3833 | |
fad09c73 | 3834 | mutex_init(&chip->reg_lock); |
469d729f | 3835 | |
fad09c73 | 3836 | return chip; |
469d729f VD |
3837 | } |
3838 | ||
e57e5e77 VD |
3839 | static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip) |
3840 | { | |
b3469dd8 | 3841 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) |
e57e5e77 | 3842 | mv88e6xxx_ppu_state_init(chip); |
e57e5e77 VD |
3843 | } |
3844 | ||
930188ce AL |
3845 | static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip) |
3846 | { | |
b3469dd8 | 3847 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) |
930188ce | 3848 | mv88e6xxx_ppu_state_destroy(chip); |
930188ce AL |
3849 | } |
3850 | ||
fad09c73 | 3851 | static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, |
4a70c4ab VD |
3852 | struct mii_bus *bus, int sw_addr) |
3853 | { | |
3854 | /* ADDR[0] pin is unavailable externally and considered zero */ | |
3855 | if (sw_addr & 0x1) | |
3856 | return -EINVAL; | |
3857 | ||
914b32f6 | 3858 | if (sw_addr == 0) |
fad09c73 | 3859 | chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; |
a0ffff24 | 3860 | else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP)) |
fad09c73 | 3861 | chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; |
914b32f6 VD |
3862 | else |
3863 | return -EINVAL; | |
3864 | ||
fad09c73 VD |
3865 | chip->bus = bus; |
3866 | chip->sw_addr = sw_addr; | |
4a70c4ab VD |
3867 | |
3868 | return 0; | |
3869 | } | |
3870 | ||
7b314362 AL |
3871 | static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds) |
3872 | { | |
04bed143 | 3873 | struct mv88e6xxx_chip *chip = ds->priv; |
2bbb33be AL |
3874 | |
3875 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) | |
3876 | return DSA_TAG_PROTO_EDSA; | |
3877 | ||
3878 | return DSA_TAG_PROTO_DSA; | |
7b314362 AL |
3879 | } |
3880 | ||
fcdce7d0 AL |
3881 | static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, |
3882 | struct device *host_dev, int sw_addr, | |
3883 | void **priv) | |
a77d43f1 | 3884 | { |
fad09c73 | 3885 | struct mv88e6xxx_chip *chip; |
a439c061 | 3886 | struct mii_bus *bus; |
b516d453 | 3887 | int err; |
a77d43f1 | 3888 | |
a439c061 | 3889 | bus = dsa_host_dev_to_mii_bus(host_dev); |
c156913b AL |
3890 | if (!bus) |
3891 | return NULL; | |
3892 | ||
fad09c73 VD |
3893 | chip = mv88e6xxx_alloc_chip(dsa_dev); |
3894 | if (!chip) | |
469d729f VD |
3895 | return NULL; |
3896 | ||
caac8545 | 3897 | /* Legacy SMI probing will only support chips similar to 88E6085 */ |
fad09c73 | 3898 | chip->info = &mv88e6xxx_table[MV88E6085]; |
caac8545 | 3899 | |
fad09c73 | 3900 | err = mv88e6xxx_smi_init(chip, bus, sw_addr); |
4a70c4ab VD |
3901 | if (err) |
3902 | goto free; | |
3903 | ||
fad09c73 | 3904 | err = mv88e6xxx_detect(chip); |
bc46a3d5 | 3905 | if (err) |
469d729f | 3906 | goto free; |
a439c061 | 3907 | |
dc30c35b AL |
3908 | mutex_lock(&chip->reg_lock); |
3909 | err = mv88e6xxx_switch_reset(chip); | |
3910 | mutex_unlock(&chip->reg_lock); | |
3911 | if (err) | |
3912 | goto free; | |
3913 | ||
e57e5e77 VD |
3914 | mv88e6xxx_phy_init(chip); |
3915 | ||
fad09c73 | 3916 | err = mv88e6xxx_mdio_register(chip, NULL); |
b516d453 | 3917 | if (err) |
469d729f | 3918 | goto free; |
b516d453 | 3919 | |
fad09c73 | 3920 | *priv = chip; |
a439c061 | 3921 | |
fad09c73 | 3922 | return chip->info->name; |
469d729f | 3923 | free: |
fad09c73 | 3924 | devm_kfree(dsa_dev, chip); |
469d729f VD |
3925 | |
3926 | return NULL; | |
a77d43f1 AL |
3927 | } |
3928 | ||
7df8fbdd VD |
3929 | static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, |
3930 | const struct switchdev_obj_port_mdb *mdb, | |
3931 | struct switchdev_trans *trans) | |
3932 | { | |
3933 | /* We don't need any dynamic resource from the kernel (yet), | |
3934 | * so skip the prepare phase. | |
3935 | */ | |
3936 | ||
3937 | return 0; | |
3938 | } | |
3939 | ||
3940 | static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, | |
3941 | const struct switchdev_obj_port_mdb *mdb, | |
3942 | struct switchdev_trans *trans) | |
3943 | { | |
04bed143 | 3944 | struct mv88e6xxx_chip *chip = ds->priv; |
7df8fbdd VD |
3945 | |
3946 | mutex_lock(&chip->reg_lock); | |
3947 | if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, | |
3948 | GLOBAL_ATU_DATA_STATE_MC_STATIC)) | |
3949 | netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n"); | |
3950 | mutex_unlock(&chip->reg_lock); | |
3951 | } | |
3952 | ||
3953 | static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, | |
3954 | const struct switchdev_obj_port_mdb *mdb) | |
3955 | { | |
04bed143 | 3956 | struct mv88e6xxx_chip *chip = ds->priv; |
7df8fbdd VD |
3957 | int err; |
3958 | ||
3959 | mutex_lock(&chip->reg_lock); | |
3960 | err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, | |
3961 | GLOBAL_ATU_DATA_STATE_UNUSED); | |
3962 | mutex_unlock(&chip->reg_lock); | |
3963 | ||
3964 | return err; | |
3965 | } | |
3966 | ||
3967 | static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port, | |
3968 | struct switchdev_obj_port_mdb *mdb, | |
3969 | int (*cb)(struct switchdev_obj *obj)) | |
3970 | { | |
04bed143 | 3971 | struct mv88e6xxx_chip *chip = ds->priv; |
7df8fbdd VD |
3972 | int err; |
3973 | ||
3974 | mutex_lock(&chip->reg_lock); | |
3975 | err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb); | |
3976 | mutex_unlock(&chip->reg_lock); | |
3977 | ||
3978 | return err; | |
3979 | } | |
3980 | ||
9d490b4e | 3981 | static struct dsa_switch_ops mv88e6xxx_switch_ops = { |
fcdce7d0 | 3982 | .probe = mv88e6xxx_drv_probe, |
7b314362 | 3983 | .get_tag_protocol = mv88e6xxx_get_tag_protocol, |
f81ec90f VD |
3984 | .setup = mv88e6xxx_setup, |
3985 | .set_addr = mv88e6xxx_set_addr, | |
f81ec90f VD |
3986 | .adjust_link = mv88e6xxx_adjust_link, |
3987 | .get_strings = mv88e6xxx_get_strings, | |
3988 | .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, | |
3989 | .get_sset_count = mv88e6xxx_get_sset_count, | |
3990 | .set_eee = mv88e6xxx_set_eee, | |
3991 | .get_eee = mv88e6xxx_get_eee, | |
3992 | #ifdef CONFIG_NET_DSA_HWMON | |
3993 | .get_temp = mv88e6xxx_get_temp, | |
3994 | .get_temp_limit = mv88e6xxx_get_temp_limit, | |
3995 | .set_temp_limit = mv88e6xxx_set_temp_limit, | |
3996 | .get_temp_alarm = mv88e6xxx_get_temp_alarm, | |
3997 | #endif | |
f8cd8753 | 3998 | .get_eeprom_len = mv88e6xxx_get_eeprom_len, |
f81ec90f VD |
3999 | .get_eeprom = mv88e6xxx_get_eeprom, |
4000 | .set_eeprom = mv88e6xxx_set_eeprom, | |
4001 | .get_regs_len = mv88e6xxx_get_regs_len, | |
4002 | .get_regs = mv88e6xxx_get_regs, | |
2cfcd964 | 4003 | .set_ageing_time = mv88e6xxx_set_ageing_time, |
f81ec90f VD |
4004 | .port_bridge_join = mv88e6xxx_port_bridge_join, |
4005 | .port_bridge_leave = mv88e6xxx_port_bridge_leave, | |
4006 | .port_stp_state_set = mv88e6xxx_port_stp_state_set, | |
749efcb8 | 4007 | .port_fast_age = mv88e6xxx_port_fast_age, |
f81ec90f VD |
4008 | .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, |
4009 | .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, | |
4010 | .port_vlan_add = mv88e6xxx_port_vlan_add, | |
4011 | .port_vlan_del = mv88e6xxx_port_vlan_del, | |
4012 | .port_vlan_dump = mv88e6xxx_port_vlan_dump, | |
4013 | .port_fdb_prepare = mv88e6xxx_port_fdb_prepare, | |
4014 | .port_fdb_add = mv88e6xxx_port_fdb_add, | |
4015 | .port_fdb_del = mv88e6xxx_port_fdb_del, | |
4016 | .port_fdb_dump = mv88e6xxx_port_fdb_dump, | |
7df8fbdd VD |
4017 | .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, |
4018 | .port_mdb_add = mv88e6xxx_port_mdb_add, | |
4019 | .port_mdb_del = mv88e6xxx_port_mdb_del, | |
4020 | .port_mdb_dump = mv88e6xxx_port_mdb_dump, | |
f81ec90f VD |
4021 | }; |
4022 | ||
fad09c73 | 4023 | static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip, |
b7e66a5f VD |
4024 | struct device_node *np) |
4025 | { | |
fad09c73 | 4026 | struct device *dev = chip->dev; |
b7e66a5f VD |
4027 | struct dsa_switch *ds; |
4028 | ||
4029 | ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); | |
4030 | if (!ds) | |
4031 | return -ENOMEM; | |
4032 | ||
4033 | ds->dev = dev; | |
fad09c73 | 4034 | ds->priv = chip; |
9d490b4e | 4035 | ds->ops = &mv88e6xxx_switch_ops; |
b7e66a5f VD |
4036 | |
4037 | dev_set_drvdata(dev, ds); | |
4038 | ||
4039 | return dsa_register_switch(ds, np); | |
4040 | } | |
4041 | ||
fad09c73 | 4042 | static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) |
b7e66a5f | 4043 | { |
fad09c73 | 4044 | dsa_unregister_switch(chip->ds); |
b7e66a5f VD |
4045 | } |
4046 | ||
57d32310 | 4047 | static int mv88e6xxx_probe(struct mdio_device *mdiodev) |
98e67308 | 4048 | { |
14c7b3c3 | 4049 | struct device *dev = &mdiodev->dev; |
f8cd8753 | 4050 | struct device_node *np = dev->of_node; |
caac8545 | 4051 | const struct mv88e6xxx_info *compat_info; |
fad09c73 | 4052 | struct mv88e6xxx_chip *chip; |
f8cd8753 | 4053 | u32 eeprom_len; |
52638f71 | 4054 | int err; |
14c7b3c3 | 4055 | |
caac8545 VD |
4056 | compat_info = of_device_get_match_data(dev); |
4057 | if (!compat_info) | |
4058 | return -EINVAL; | |
4059 | ||
fad09c73 VD |
4060 | chip = mv88e6xxx_alloc_chip(dev); |
4061 | if (!chip) | |
14c7b3c3 AL |
4062 | return -ENOMEM; |
4063 | ||
fad09c73 | 4064 | chip->info = compat_info; |
caac8545 | 4065 | |
fad09c73 | 4066 | err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); |
4a70c4ab VD |
4067 | if (err) |
4068 | return err; | |
14c7b3c3 | 4069 | |
b4308f04 AL |
4070 | chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); |
4071 | if (IS_ERR(chip->reset)) | |
4072 | return PTR_ERR(chip->reset); | |
4073 | ||
fad09c73 | 4074 | err = mv88e6xxx_detect(chip); |
bc46a3d5 VD |
4075 | if (err) |
4076 | return err; | |
14c7b3c3 | 4077 | |
e57e5e77 VD |
4078 | mv88e6xxx_phy_init(chip); |
4079 | ||
ee4dc2e7 | 4080 | if (chip->info->ops->get_eeprom && |
f8cd8753 | 4081 | !of_property_read_u32(np, "eeprom-length", &eeprom_len)) |
fad09c73 | 4082 | chip->eeprom_len = eeprom_len; |
f8cd8753 | 4083 | |
dc30c35b AL |
4084 | mutex_lock(&chip->reg_lock); |
4085 | err = mv88e6xxx_switch_reset(chip); | |
4086 | mutex_unlock(&chip->reg_lock); | |
4087 | if (err) | |
4088 | goto out; | |
4089 | ||
4090 | chip->irq = of_irq_get(np, 0); | |
4091 | if (chip->irq == -EPROBE_DEFER) { | |
4092 | err = chip->irq; | |
4093 | goto out; | |
4094 | } | |
4095 | ||
4096 | if (chip->irq > 0) { | |
4097 | /* Has to be performed before the MDIO bus is created, | |
4098 | * because the PHYs will link there interrupts to these | |
4099 | * interrupt controllers | |
4100 | */ | |
4101 | mutex_lock(&chip->reg_lock); | |
4102 | err = mv88e6xxx_g1_irq_setup(chip); | |
4103 | mutex_unlock(&chip->reg_lock); | |
4104 | ||
4105 | if (err) | |
4106 | goto out; | |
4107 | ||
4108 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) { | |
4109 | err = mv88e6xxx_g2_irq_setup(chip); | |
4110 | if (err) | |
4111 | goto out_g1_irq; | |
4112 | } | |
4113 | } | |
4114 | ||
fad09c73 | 4115 | err = mv88e6xxx_mdio_register(chip, np); |
b516d453 | 4116 | if (err) |
dc30c35b | 4117 | goto out_g2_irq; |
b516d453 | 4118 | |
fad09c73 | 4119 | err = mv88e6xxx_register_switch(chip, np); |
dc30c35b AL |
4120 | if (err) |
4121 | goto out_mdio; | |
83c0afae | 4122 | |
98e67308 | 4123 | return 0; |
dc30c35b AL |
4124 | |
4125 | out_mdio: | |
4126 | mv88e6xxx_mdio_unregister(chip); | |
4127 | out_g2_irq: | |
46712644 | 4128 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0) |
dc30c35b AL |
4129 | mv88e6xxx_g2_irq_free(chip); |
4130 | out_g1_irq: | |
61f7c3f8 AL |
4131 | if (chip->irq > 0) { |
4132 | mutex_lock(&chip->reg_lock); | |
46712644 | 4133 | mv88e6xxx_g1_irq_free(chip); |
61f7c3f8 AL |
4134 | mutex_unlock(&chip->reg_lock); |
4135 | } | |
dc30c35b AL |
4136 | out: |
4137 | return err; | |
98e67308 | 4138 | } |
14c7b3c3 AL |
4139 | |
4140 | static void mv88e6xxx_remove(struct mdio_device *mdiodev) | |
4141 | { | |
4142 | struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); | |
04bed143 | 4143 | struct mv88e6xxx_chip *chip = ds->priv; |
14c7b3c3 | 4144 | |
930188ce | 4145 | mv88e6xxx_phy_destroy(chip); |
fad09c73 VD |
4146 | mv88e6xxx_unregister_switch(chip); |
4147 | mv88e6xxx_mdio_unregister(chip); | |
dc30c35b | 4148 | |
46712644 AL |
4149 | if (chip->irq > 0) { |
4150 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) | |
4151 | mv88e6xxx_g2_irq_free(chip); | |
4152 | mv88e6xxx_g1_irq_free(chip); | |
4153 | } | |
14c7b3c3 AL |
4154 | } |
4155 | ||
4156 | static const struct of_device_id mv88e6xxx_of_match[] = { | |
caac8545 VD |
4157 | { |
4158 | .compatible = "marvell,mv88e6085", | |
4159 | .data = &mv88e6xxx_table[MV88E6085], | |
4160 | }, | |
1a3b39ec AL |
4161 | { |
4162 | .compatible = "marvell,mv88e6190", | |
4163 | .data = &mv88e6xxx_table[MV88E6190], | |
4164 | }, | |
14c7b3c3 AL |
4165 | { /* sentinel */ }, |
4166 | }; | |
4167 | ||
4168 | MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); | |
4169 | ||
4170 | static struct mdio_driver mv88e6xxx_driver = { | |
4171 | .probe = mv88e6xxx_probe, | |
4172 | .remove = mv88e6xxx_remove, | |
4173 | .mdiodrv.driver = { | |
4174 | .name = "mv88e6085", | |
4175 | .of_match_table = mv88e6xxx_of_match, | |
4176 | }, | |
4177 | }; | |
4178 | ||
4179 | static int __init mv88e6xxx_init(void) | |
4180 | { | |
9d490b4e | 4181 | register_switch_driver(&mv88e6xxx_switch_ops); |
14c7b3c3 AL |
4182 | return mdio_driver_register(&mv88e6xxx_driver); |
4183 | } | |
98e67308 BH |
4184 | module_init(mv88e6xxx_init); |
4185 | ||
4186 | static void __exit mv88e6xxx_cleanup(void) | |
4187 | { | |
14c7b3c3 | 4188 | mdio_driver_unregister(&mv88e6xxx_driver); |
9d490b4e | 4189 | unregister_switch_driver(&mv88e6xxx_switch_ops); |
98e67308 BH |
4190 | } |
4191 | module_exit(mv88e6xxx_cleanup); | |
3d825ede BH |
4192 | |
4193 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); | |
4194 | MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); | |
4195 | MODULE_LICENSE("GPL"); |