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net: dsa: mv88e6xxx: setup message ports
[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
1f36faf2 35#include <net/switchdev.h>
ec561276 36
91da11f8 37#include "mv88e6xxx.h"
a935c052 38#include "global1.h"
ec561276 39#include "global2.h"
18abed21 40#include "port.h"
91da11f8 41
fad09c73 42static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 43{
fad09c73
VD		 44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 46 dump_stack();
47 }
48}
49
914b32f6
VD		 50/* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
52 *
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
56 *
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 60 */
914b32f6 61
fad09c73 62static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 63 int addr, int reg, u16 *val)
64{
fad09c73 65 if (!chip->smi_ops)
914b32f6
VD		 66 return -EOPNOTSUPP;
67
fad09c73 68 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 69}
70
fad09c73 71static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 72 int addr, int reg, u16 val)
73{
fad09c73 74 if (!chip->smi_ops)
914b32f6
VD		 75 return -EOPNOTSUPP;
76
fad09c73 77 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 78}
79
fad09c73 80static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 81 int addr, int reg, u16 *val)
82{
83 int ret;
84
fad09c73 85 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 86 if (ret < 0)
87 return ret;
88
89 *val = ret & 0xffff;
90
91 return 0;
92}
93
fad09c73 94static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 95 int addr, int reg, u16 val)
96{
97 int ret;
98
fad09c73 99 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 100 if (ret < 0)
101 return ret;
102
103 return 0;
104}
105
c08026ab 106static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
109};
110
fad09c73 111static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 112{
113 int ret;
114 int i;
115
116 for (i = 0; i < 16; i++) {
fad09c73 117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 118 if (ret < 0)
119 return ret;
120
cca8b133 121 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 122 return 0;
123 }
124
125 return -ETIMEDOUT;
126}
127
fad09c73 128static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 129 int addr, int reg, u16 *val)
91da11f8
LB		 130{
131 int ret;
132
3675c8d7 133 /* Wait for the bus to become free. */
fad09c73 134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 135 if (ret < 0)
136 return ret;
137
3675c8d7 138 /* Transmit the read command. */
fad09c73 139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 141 if (ret < 0)
142 return ret;
143
3675c8d7 144 /* Wait for the read command to complete. */
fad09c73 145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 146 if (ret < 0)
147 return ret;
148
3675c8d7 149 /* Read the data. */
fad09c73 150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 151 if (ret < 0)
152 return ret;
153
914b32f6 154 *val = ret & 0xffff;
91da11f8 155
914b32f6 156 return 0;
8d6d09e7
GR		 157}
158
fad09c73 159static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 160 int addr, int reg, u16 val)
91da11f8
LB		 161{
162 int ret;
163
3675c8d7 164 /* Wait for the bus to become free. */
fad09c73 165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 166 if (ret < 0)
167 return ret;
168
3675c8d7 169 /* Transmit the data to write. */
fad09c73 170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 171 if (ret < 0)
172 return ret;
173
3675c8d7 174 /* Transmit the write command. */
fad09c73 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 177 if (ret < 0)
178 return ret;
179
3675c8d7 180 /* Wait for the write command to complete. */
fad09c73 181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 182 if (ret < 0)
183 return ret;
184
185 return 0;
186}
187
c08026ab 188static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
191};
192
ec561276 193int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 194{
195 int err;
196
fad09c73 197 assert_reg_lock(chip);
914b32f6 198
fad09c73 199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 200 if (err)
201 return err;
202
fad09c73 203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 204 addr, reg, *val);
205
206 return 0;
207}
208
ec561276 209int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 210{
914b32f6
VD		 211 int err;
212
fad09c73 213 assert_reg_lock(chip);
91da11f8 214
fad09c73 215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 216 if (err)
217 return err;
218
fad09c73 219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 220 addr, reg, val);
221
914b32f6
VD		 222 return 0;
223}
224
ee26a228
AL		 225static int mv88e6165_phy_read(struct mv88e6xxx_chip *chip,
226 struct mii_bus *bus,
227 int addr, int reg, u16 *val)
efb3e74d
AL		 228{
229 return mv88e6xxx_read(chip, addr, reg, val);
230}
231
ee26a228
AL		 232static int mv88e6165_phy_write(struct mv88e6xxx_chip *chip,
233 struct mii_bus *bus,
234 int addr, int reg, u16 val)
efb3e74d
AL		 235{
236 return mv88e6xxx_write(chip, addr, reg, val);
237}
238
a3c53be5
AL		 239static struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
240{
241 struct mv88e6xxx_mdio_bus *mdio_bus;
242
243 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
244 list);
245 if (!mdio_bus)
246 return NULL;
247
248 return mdio_bus->bus;
249}
250
e57e5e77
VD		 251static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
252 int reg, u16 *val)
253{
254 int addr = phy; /* PHY devices addresses start at 0x0 */
a3c53be5 255 struct mii_bus *bus;
e57e5e77 256
a3c53be5
AL		 257 bus = mv88e6xxx_default_mdio_bus(chip);
258 if (!bus)
e57e5e77
VD		 259 return -EOPNOTSUPP;
260
a3c53be5 261 if (!chip->info->ops->phy_read)
ee26a228
AL		 262 return -EOPNOTSUPP;
263
264 return chip->info->ops->phy_read(chip, bus, addr, reg, val);
e57e5e77
VD		 265}
266
267static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
268 int reg, u16 val)
269{
270 int addr = phy; /* PHY devices addresses start at 0x0 */
a3c53be5 271 struct mii_bus *bus;
e57e5e77 272
a3c53be5
AL		 273 bus = mv88e6xxx_default_mdio_bus(chip);
274 if (!bus)
e57e5e77
VD		 275 return -EOPNOTSUPP;
276
a3c53be5 277 if (!chip->info->ops->phy_write)
ee26a228
AL		 278 return -EOPNOTSUPP;
279
280 return chip->info->ops->phy_write(chip, bus, addr, reg, val);
e57e5e77
VD		 281}
282
09cb7dfd
VD		 283static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
284{
285 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
286 return -EOPNOTSUPP;
287
288 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
289}
290
291static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
292{
293 int err;
294
295 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
297 if (unlikely(err)) {
298 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
299 phy, err);
300 }
301}
302
303static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
304 u8 page, int reg, u16 *val)
305{
306 int err;
307
308 /* There is no paging for registers 22 */
309 if (reg == PHY_PAGE)
310 return -EINVAL;
311
312 err = mv88e6xxx_phy_page_get(chip, phy, page);
313 if (!err) {
314 err = mv88e6xxx_phy_read(chip, phy, reg, val);
315 mv88e6xxx_phy_page_put(chip, phy);
316 }
317
318 return err;
319}
320
321static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
322 u8 page, int reg, u16 val)
323{
324 int err;
325
326 /* There is no paging for registers 22 */
327 if (reg == PHY_PAGE)
328 return -EINVAL;
329
330 err = mv88e6xxx_phy_page_get(chip, phy, page);
331 if (!err) {
332 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
333 mv88e6xxx_phy_page_put(chip, phy);
334 }
335
336 return err;
337}
338
339static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
340{
341 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
342 reg, val);
343}
344
345static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
346{
347 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
348 reg, val);
349}
350
dc30c35b
AL		 351static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
352{
353 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
354 unsigned int n = d->hwirq;
355
356 chip->g1_irq.masked |= (1 << n);
357}
358
359static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
360{
361 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
362 unsigned int n = d->hwirq;
363
364 chip->g1_irq.masked &= ~(1 << n);
365}
366
367static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
368{
369 struct mv88e6xxx_chip *chip = dev_id;
370 unsigned int nhandled = 0;
371 unsigned int sub_irq;
372 unsigned int n;
373 u16 reg;
374 int err;
375
376 mutex_lock(&chip->reg_lock);
377 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
378 mutex_unlock(&chip->reg_lock);
379
380 if (err)
381 goto out;
382
383 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
384 if (reg & (1 << n)) {
385 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
386 handle_nested_irq(sub_irq);
387 ++nhandled;
388 }
389 }
390out:
391 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
392}
393
394static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
395{
396 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
397
398 mutex_lock(&chip->reg_lock);
399}
400
401static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
402{
403 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
404 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
405 u16 reg;
406 int err;
407
408 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
409 if (err)
410 goto out;
411
412 reg &= ~mask;
413 reg |= (~chip->g1_irq.masked & mask);
414
415 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
416 if (err)
417 goto out;
418
419out:
420 mutex_unlock(&chip->reg_lock);
421}
422
423static struct irq_chip mv88e6xxx_g1_irq_chip = {
424 .name = "mv88e6xxx-g1",
425 .irq_mask = mv88e6xxx_g1_irq_mask,
426 .irq_unmask = mv88e6xxx_g1_irq_unmask,
427 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
428 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
429};
430
431static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
432 unsigned int irq,
433 irq_hw_number_t hwirq)
434{
435 struct mv88e6xxx_chip *chip = d->host_data;
436
437 irq_set_chip_data(irq, d->host_data);
438 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
439 irq_set_noprobe(irq);
440
441 return 0;
442}
443
444static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
445 .map = mv88e6xxx_g1_irq_domain_map,
446 .xlate = irq_domain_xlate_twocell,
447};
448
449static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
450{
451 int irq, virq;
3460a577
AL		 452 u16 mask;
453
454 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
455 mask |= GENMASK(chip->g1_irq.nirqs, 0);
456 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
457
458 free_irq(chip->irq, chip);
dc30c35b 459
5edef2f2 460 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
a3db3d3a 461 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 462 irq_dispose_mapping(virq);
463 }
464
a3db3d3a 465 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 466}
467
468static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
469{
3dd0ef05
AL		 470 int err, irq, virq;
471 u16 reg, mask;
dc30c35b
AL		 472
473 chip->g1_irq.nirqs = chip->info->g1_irqs;
474 chip->g1_irq.domain = irq_domain_add_simple(
475 NULL, chip->g1_irq.nirqs, 0,
476 &mv88e6xxx_g1_irq_domain_ops, chip);
477 if (!chip->g1_irq.domain)
478 return -ENOMEM;
479
480 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
481 irq_create_mapping(chip->g1_irq.domain, irq);
482
483 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
484 chip->g1_irq.masked = ~0;
485
3dd0ef05 486 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
dc30c35b 487 if (err)
3dd0ef05 488 goto out_mapping;
dc30c35b 489
3dd0ef05 490 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 491
3dd0ef05 492 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
dc30c35b 493 if (err)
3dd0ef05 494 goto out_disable;
dc30c35b
AL		 495
496 /* Reading the interrupt status clears (most of) them */
497 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
498 if (err)
3dd0ef05 499 goto out_disable;
dc30c35b
AL		 500
501 err = request_threaded_irq(chip->irq, NULL,
502 mv88e6xxx_g1_irq_thread_fn,
503 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
504 dev_name(chip->dev), chip);
505 if (err)
3dd0ef05 506 goto out_disable;
dc30c35b
AL		 507
508 return 0;
509
3dd0ef05
AL		 510out_disable:
511 mask |= GENMASK(chip->g1_irq.nirqs, 0);
512 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
513
514out_mapping:
515 for (irq = 0; irq < 16; irq++) {
516 virq = irq_find_mapping(chip->g1_irq.domain, irq);
517 irq_dispose_mapping(virq);
518 }
519
520 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 521
522 return err;
523}
524
ec561276 525int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 526{
6441e669 527 int i;
2d79af6e 528
6441e669 529 for (i = 0; i < 16; i++) {
2d79af6e
VD		 530 u16 val;
531 int err;
532
533 err = mv88e6xxx_read(chip, addr, reg, &val);
534 if (err)
535 return err;
536
537 if (!(val & mask))
538 return 0;
539
540 usleep_range(1000, 2000);
541 }
542
30853553 543 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 544 return -ETIMEDOUT;
545}
546
f22ab641 547/* Indirect write to single pointer-data register with an Update bit */
ec561276 548int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 549{
550 u16 val;
0f02b4f7 551 int err;
f22ab641
VD		 552
553 /* Wait until the previous operation is completed */
0f02b4f7
AL		 554 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
555 if (err)
556 return err;
f22ab641
VD		 557
558 /* Set the Update bit to trigger a write operation */
559 val = BIT(15) | update;
560
561 return mv88e6xxx_write(chip, addr, reg, val);
562}
563
a935c052 564static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
914b32f6 565{
a199d8b6
VD		 566 if (!chip->info->ops->ppu_disable)
567 return 0;
2e5f0320 568
a199d8b6 569 return chip->info->ops->ppu_disable(chip);
2e5f0320
LB		 570}
571
fad09c73 572static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 573{
a199d8b6
VD		 574 if (!chip->info->ops->ppu_enable)
575 return 0;
2e5f0320 576
a199d8b6 577 return chip->info->ops->ppu_enable(chip);
2e5f0320
LB		 578}
579
580static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
581{
fad09c73 582 struct mv88e6xxx_chip *chip;
2e5f0320 583
fad09c73 584 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 585
fad09c73 586 mutex_lock(&chip->reg_lock);
762eb67b 587
fad09c73
VD		 588 if (mutex_trylock(&chip->ppu_mutex)) {
589 if (mv88e6xxx_ppu_enable(chip) == 0)
590 chip->ppu_disabled = 0;
591 mutex_unlock(&chip->ppu_mutex);
2e5f0320 592 }
762eb67b 593
fad09c73 594 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 595}
596
597static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
598{
fad09c73 599 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 600
fad09c73 601 schedule_work(&chip->ppu_work);
2e5f0320
LB		 602}
603
fad09c73 604static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 605{
2e5f0320
LB		 606 int ret;
607
fad09c73 608 mutex_lock(&chip->ppu_mutex);
2e5f0320 609
3675c8d7 610 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 611 * we can access the PHY registers. If it was already
612 * disabled, cancel the timer that is going to re-enable
613 * it.
614 */
fad09c73
VD		 615 if (!chip->ppu_disabled) {
616 ret = mv88e6xxx_ppu_disable(chip);
85686581 617 if (ret < 0) {
fad09c73 618 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 619 return ret;
620 }
fad09c73 621 chip->ppu_disabled = 1;
2e5f0320 622 } else {
fad09c73 623 del_timer(&chip->ppu_timer);
85686581 624 ret = 0;
2e5f0320
LB		 625 }
626
627 return ret;
628}
629
fad09c73 630static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 631{
3675c8d7 632 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 633 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
634 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 635}
636
fad09c73 637static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 638{
fad09c73
VD		 639 mutex_init(&chip->ppu_mutex);
640 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
68497a87
WY		 641 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
642 (unsigned long)chip);
2e5f0320
LB		 643}
644
930188ce
AL		 645static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
646{
647 del_timer_sync(&chip->ppu_timer);
648}
649
ee26a228
AL		 650static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip,
651 struct mii_bus *bus,
652 int addr, int reg, u16 *val)
2e5f0320 653{
e57e5e77 654 int err;
2e5f0320 655
e57e5e77
VD		 656 err = mv88e6xxx_ppu_access_get(chip);
657 if (!err) {
658 err = mv88e6xxx_read(chip, addr, reg, val);
fad09c73 659 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 660 }
661
e57e5e77 662 return err;
2e5f0320
LB		 663}
664
ee26a228
AL		 665static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip,
666 struct mii_bus *bus,
667 int addr, int reg, u16 val)
2e5f0320 668{
e57e5e77 669 int err;
2e5f0320 670
e57e5e77
VD		 671 err = mv88e6xxx_ppu_access_get(chip);
672 if (!err) {
673 err = mv88e6xxx_write(chip, addr, reg, val);
fad09c73 674 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 675 }
676
e57e5e77 677 return err;
2e5f0320 678}
2e5f0320 679
fad09c73 680static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 681{
fad09c73 682 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 683}
684
fad09c73 685static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 686{
fad09c73 687 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 688}
689
fad09c73 690static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
7c3d0d67 691{
fad09c73 692 return chip->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 693}
694
a75961d0
GC		 695static bool mv88e6xxx_6341_family(struct mv88e6xxx_chip *chip)
696{
697 return chip->info->family == MV88E6XXX_FAMILY_6341;
698}
699
fad09c73 700static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 701{
fad09c73 702 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 703}
704
fad09c73 705static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 706{
fad09c73 707 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 708}
709
d78343d2
VD		 710static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
711 int link, int speed, int duplex,
712 phy_interface_t mode)
713{
714 int err;
715
716 if (!chip->info->ops->port_set_link)
717 return 0;
718
719 /* Port's MAC control must not be changed unless the link is down */
720 err = chip->info->ops->port_set_link(chip, port, 0);
721 if (err)
722 return err;
723
724 if (chip->info->ops->port_set_speed) {
725 err = chip->info->ops->port_set_speed(chip, port, speed);
726 if (err && err != -EOPNOTSUPP)
727 goto restore_link;
728 }
729
730 if (chip->info->ops->port_set_duplex) {
731 err = chip->info->ops->port_set_duplex(chip, port, duplex);
732 if (err && err != -EOPNOTSUPP)
733 goto restore_link;
734 }
735
736 if (chip->info->ops->port_set_rgmii_delay) {
737 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
738 if (err && err != -EOPNOTSUPP)
739 goto restore_link;
740 }
741
f39908d3
AL		 742 if (chip->info->ops->port_set_cmode) {
743 err = chip->info->ops->port_set_cmode(chip, port, mode);
744 if (err && err != -EOPNOTSUPP)
745 goto restore_link;
746 }
747
d78343d2
VD		 748 err = 0;
749restore_link:
750 if (chip->info->ops->port_set_link(chip, port, link))
751 netdev_err(chip->ds->ports[port].netdev,
752 "failed to restore MAC's link\n");
753
754 return err;
755}
756
dea87024
AL		 757/* We expect the switch to perform auto negotiation if there is a real
758 * phy. However, in the case of a fixed link phy, we force the port
759 * settings from the fixed link settings.
760 */
f81ec90f
VD		 761static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
762 struct phy_device *phydev)
dea87024 763{
04bed143 764 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 765 int err;
dea87024
AL		 766
767 if (!phy_is_pseudo_fixed_link(phydev))
768 return;
769
fad09c73 770 mutex_lock(&chip->reg_lock);
d78343d2
VD		 771 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
772 phydev->duplex, phydev->interface);
fad09c73 773 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 774
775 if (err && err != -EOPNOTSUPP)
776 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
dea87024
AL		 777}
778
a605a0fe 779static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 780{
a605a0fe
AL		 781 if (!chip->info->ops->stats_snapshot)
782 return -EOPNOTSUPP;
91da11f8 783
a605a0fe 784 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 785}
786
e413e7e1 787static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 788 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
789 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
790 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
791 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
792 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
793 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
794 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
795 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
796 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
797 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
798 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
799 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
800 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
801 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
802 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
803 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
804 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
805 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
806 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
807 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
808 { "single", 4, 0x14, STATS_TYPE_BANK0, },
809 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
810 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
811 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
812 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
813 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
814 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
815 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
816 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
817 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
818 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
819 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
820 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
821 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
822 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
823 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
824 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
825 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
826 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
827 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
828 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
829 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
830 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
831 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
832 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
833 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
834 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
835 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
836 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
837 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
838 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
839 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
840 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
841 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
842 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
843 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
844 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
845 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
846 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 847};
848
fad09c73 849static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 850 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 851 int port, u16 bank1_select,
852 u16 histogram)
80c4627b 853{
80c4627b
AL		 854 u32 low;
855 u32 high = 0;
dfafe449 856 u16 reg = 0;
0e7b9925 857 int err;
80c4627b
AL		 858 u64 value;
859
f5e2ed02 860 switch (s->type) {
dfafe449 861 case STATS_TYPE_PORT:
0e7b9925
AL		 862 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
863 if (err)
80c4627b
AL		 864 return UINT64_MAX;
865
0e7b9925 866 low = reg;
80c4627b 867 if (s->sizeof_stat == 4) {
0e7b9925
AL		 868 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
869 if (err)
80c4627b 870 return UINT64_MAX;
0e7b9925 871 high = reg;
80c4627b 872 }
f5e2ed02 873 break;
dfafe449 874 case STATS_TYPE_BANK1:
e0d8b615 875 reg = bank1_select;
dfafe449
AL		 876 /* fall through */
877 case STATS_TYPE_BANK0:
e0d8b615 878 reg |= s->reg | histogram;
7f9ef3af 879 mv88e6xxx_g1_stats_read(chip, reg, &low);
80c4627b 880 if (s->sizeof_stat == 8)
7f9ef3af 881 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
80c4627b
AL		 882 }
883 value = (((u64)high) << 16) | low;
884 return value;
885}
886
dfafe449
AL		 887static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
888 uint8_t *data, int types)
91da11f8 889{
f5e2ed02
AL		 890 struct mv88e6xxx_hw_stat *stat;
891 int i, j;
91da11f8 892
f5e2ed02
AL		 893 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
894 stat = &mv88e6xxx_hw_stats[i];
dfafe449 895 if (stat->type & types) {
f5e2ed02
AL		 896 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
897 ETH_GSTRING_LEN);
898 j++;
899 }
91da11f8 900 }
e413e7e1
AL		 901}
902
dfafe449
AL		 903static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
904 uint8_t *data)
905{
906 mv88e6xxx_stats_get_strings(chip, data,
907 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
908}
909
910static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
911 uint8_t *data)
912{
913 mv88e6xxx_stats_get_strings(chip, data,
914 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
915}
916
917static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
918 uint8_t *data)
e413e7e1 919{
04bed143 920 struct mv88e6xxx_chip *chip = ds->priv;
dfafe449
AL		 921
922 if (chip->info->ops->stats_get_strings)
923 chip->info->ops->stats_get_strings(chip, data);
924}
925
926static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
927 int types)
928{
f5e2ed02
AL		 929 struct mv88e6xxx_hw_stat *stat;
930 int i, j;
931
932 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
933 stat = &mv88e6xxx_hw_stats[i];
dfafe449 934 if (stat->type & types)
f5e2ed02
AL		 935 j++;
936 }
937 return j;
e413e7e1
AL		 938}
939
dfafe449
AL		 940static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
941{
942 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
943 STATS_TYPE_PORT);
944}
945
946static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
947{
948 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
949 STATS_TYPE_BANK1);
950}
951
952static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
953{
954 struct mv88e6xxx_chip *chip = ds->priv;
955
956 if (chip->info->ops->stats_get_sset_count)
957 return chip->info->ops->stats_get_sset_count(chip);
958
959 return 0;
960}
961
052f947f 962static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
e0d8b615
AL		 963 uint64_t *data, int types,
964 u16 bank1_select, u16 histogram)
052f947f
AL		 965{
966 struct mv88e6xxx_hw_stat *stat;
967 int i, j;
968
969 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
970 stat = &mv88e6xxx_hw_stats[i];
971 if (stat->type & types) {
e0d8b615
AL		 972 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
973 bank1_select,
974 histogram);
052f947f
AL		 975 j++;
976 }
977 }
978}
979
980static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
981 uint64_t *data)
982{
983 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 984 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
985 0, GLOBAL_STATS_OP_HIST_RX_TX);
052f947f
AL		 986}
987
988static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
989 uint64_t *data)
990{
991 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 992 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
993 GLOBAL_STATS_OP_BANK_1_BIT_9,
994 GLOBAL_STATS_OP_HIST_RX_TX);
995}
996
997static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
998 uint64_t *data)
999{
1000 return mv88e6xxx_stats_get_stats(chip, port, data,
1001 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1002 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
052f947f
AL		 1003}
1004
1005static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1006 uint64_t *data)
1007{
1008 if (chip->info->ops->stats_get_stats)
1009 chip->info->ops->stats_get_stats(chip, port, data);
1010}
1011
f81ec90f
VD		 1012static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1013 uint64_t *data)
e413e7e1 1014{
04bed143 1015 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 1016 int ret;
f5e2ed02 1017
fad09c73 1018 mutex_lock(&chip->reg_lock);
f5e2ed02 1019
a605a0fe 1020 ret = mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 1021 if (ret < 0) {
fad09c73 1022 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 1023 return;
1024 }
052f947f
AL		 1025
1026 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 1027
fad09c73 1028 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 1029}
1030
de227387
AL		 1031static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
1032{
1033 if (chip->info->ops->stats_set_histogram)
1034 return chip->info->ops->stats_set_histogram(chip);
1035
1036 return 0;
1037}
1038
f81ec90f 1039static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 1040{
1041 return 32 * sizeof(u16);
1042}
1043
f81ec90f
VD		 1044static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1045 struct ethtool_regs *regs, void *_p)
a1ab91f3 1046{
04bed143 1047 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 1048 int err;
1049 u16 reg;
a1ab91f3
GR		 1050 u16 *p = _p;
1051 int i;
1052
1053 regs->version = 0;
1054
1055 memset(p, 0xff, 32 * sizeof(u16));
1056
fad09c73 1057 mutex_lock(&chip->reg_lock);
23062513 1058
a1ab91f3 1059 for (i = 0; i < 32; i++) {
a1ab91f3 1060
0e7b9925
AL		 1061 err = mv88e6xxx_port_read(chip, port, i, &reg);
1062 if (!err)
1063 p[i] = reg;
a1ab91f3 1064 }
23062513 1065
fad09c73 1066 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 1067}
1068
fad09c73 1069static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
facd95b2 1070{
a935c052 1071 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 1072}
1073
f81ec90f
VD		 1074static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1075 struct ethtool_eee *e)
11b3b45d 1076{
04bed143 1077 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1078 u16 reg;
1079 int err;
11b3b45d 1080
fad09c73 1081 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1082 return -EOPNOTSUPP;
1083
fad09c73 1084 mutex_lock(&chip->reg_lock);
2f40c698 1085
9c93829c
VD		 1086 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1087 if (err)
2f40c698 1088 goto out;
11b3b45d
GR		 1089
1090 e->eee_enabled = !!(reg & 0x0200);
1091 e->tx_lpi_enabled = !!(reg & 0x0100);
1092
0e7b9925 1093 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
9c93829c 1094 if (err)
2f40c698 1095 goto out;
11b3b45d 1096
cca8b133 1097 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1098out:
fad09c73 1099 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 1100
1101 return err;
11b3b45d
GR		 1102}
1103
f81ec90f
VD		 1104static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1105 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 1106{
04bed143 1107 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1108 u16 reg;
1109 int err;
11b3b45d 1110
fad09c73 1111 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1112 return -EOPNOTSUPP;
1113
fad09c73 1114 mutex_lock(&chip->reg_lock);
11b3b45d 1115
9c93829c
VD		 1116 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1117 if (err)
2f40c698
AL		 1118 goto out;
1119
9c93829c 1120 reg &= ~0x0300;
2f40c698
AL		 1121 if (e->eee_enabled)
1122 reg |= 0x0200;
1123 if (e->tx_lpi_enabled)
1124 reg |= 0x0100;
1125
9c93829c 1126 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 1127out:
fad09c73 1128 mutex_unlock(&chip->reg_lock);
2f40c698 1129
9c93829c 1130 return err;
11b3b45d
GR		 1131}
1132
fad09c73 1133static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
facd95b2 1134{
a935c052
VD		 1135 u16 val;
1136 int err;
facd95b2 1137
6dc10bbc 1138 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
a935c052
VD		 1139 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
1140 if (err)
1141 return err;
fad09c73 1142 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f 1143 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
a935c052
VD		 1144 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
1145 if (err)
1146 return err;
11ea809f 1147
a935c052
VD		 1148 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
1149 (val & 0xfff) | ((fid << 8) & 0xf000));
1150 if (err)
1151 return err;
11ea809f
VD		 1152
1153 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1154 cmd |= fid & 0xf;
b426e5f7
VD		 1155 }
1156
a935c052
VD		 1157 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
1158 if (err)
1159 return err;
facd95b2 1160
fad09c73 1161 return _mv88e6xxx_atu_wait(chip);
facd95b2
GR		 1162}
1163
fad09c73 1164static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
37705b73
VD		 1165 struct mv88e6xxx_atu_entry *entry)
1166{
1167 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1168
1169 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1170 unsigned int mask, shift;
1171
1172 if (entry->trunk) {
1173 data |= GLOBAL_ATU_DATA_TRUNK;
1174 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1175 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1176 } else {
1177 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1178 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1179 }
1180
1181 data |= (entry->portv_trunkid << shift) & mask;
1182 }
1183
a935c052 1184 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
37705b73
VD		 1185}
1186
fad09c73 1187static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
7fb5e755
VD		 1188 struct mv88e6xxx_atu_entry *entry,
1189 bool static_too)
facd95b2 1190{
7fb5e755
VD		 1191 int op;
1192 int err;
facd95b2 1193
fad09c73 1194 err = _mv88e6xxx_atu_wait(chip);
7fb5e755
VD		 1195 if (err)
1196 return err;
facd95b2 1197
fad09c73 1198 err = _mv88e6xxx_atu_data_write(chip, entry);
7fb5e755
VD		 1199 if (err)
1200 return err;
1201
1202 if (entry->fid) {
7fb5e755
VD		 1203 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1204 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1205 } else {
1206 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1207 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1208 }
1209
fad09c73 1210 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
7fb5e755
VD		 1211}
1212
fad09c73 1213static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
158bc065 1214 u16 fid, bool static_too)
7fb5e755
VD		 1215{
1216 struct mv88e6xxx_atu_entry entry = {
1217 .fid = fid,
1218 .state = 0, /* EntryState bits must be 0 */
1219 };
70cc99d1 1220
fad09c73 1221 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
7fb5e755
VD		 1222}
1223
fad09c73 1224static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1225 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1226{
1227 struct mv88e6xxx_atu_entry entry = {
1228 .trunk = false,
1229 .fid = fid,
1230 };
1231
1232 /* EntryState bits must be 0xF */
1233 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1234
1235 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1236 entry.portv_trunkid = (to_port & 0x0f) << 4;
1237 entry.portv_trunkid |= from_port & 0x0f;
1238
fad09c73 1239 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
9f4d55d2
VD		 1240}
1241
fad09c73 1242static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1243 int port, bool static_too)
9f4d55d2
VD		 1244{
1245 /* Destination port 0xF means remove the entries */
fad09c73 1246 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1247}
1248
fad09c73 1249static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1250{
fad09c73 1251 struct dsa_switch *ds = chip->ds;
fae8a25e 1252 struct net_device *bridge = ds->ports[port].bridge_dev;
b7666efe 1253 u16 output_ports = 0;
b7666efe
VD		 1254 int i;
1255
1256 /* allow CPU port or DSA link(s) to send frames to every port */
1257 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
5a7921f4 1258 output_ports = ~0;
b7666efe 1259 } else {
370b4ffb 1260 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b7666efe 1261 /* allow sending frames to every group member */
fae8a25e 1262 if (bridge && ds->ports[i].bridge_dev == bridge)
b7666efe
VD		 1263 output_ports |= BIT(i);
1264
1265 /* allow sending frames to CPU port and DSA link(s) */
1266 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1267 output_ports |= BIT(i);
1268 }
1269 }
1270
1271 /* prevent frames from going back out of the port they came in on */
1272 output_ports &= ~BIT(port);
facd95b2 1273
5a7921f4 1274 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 1275}
1276
f81ec90f
VD		 1277static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1278 u8 state)
facd95b2 1279{
04bed143 1280 struct mv88e6xxx_chip *chip = ds->priv;
facd95b2 1281 int stp_state;
553eb544 1282 int err;
facd95b2
GR		 1283
1284 switch (state) {
1285 case BR_STATE_DISABLED:
cca8b133 1286 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1287 break;
1288 case BR_STATE_BLOCKING:
1289 case BR_STATE_LISTENING:
cca8b133 1290 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1291 break;
1292 case BR_STATE_LEARNING:
cca8b133 1293 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1294 break;
1295 case BR_STATE_FORWARDING:
1296 default:
cca8b133 1297 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1298 break;
1299 }
1300
fad09c73 1301 mutex_lock(&chip->reg_lock);
e28def33 1302 err = mv88e6xxx_port_set_state(chip, port, stp_state);
fad09c73 1303 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1304
1305 if (err)
e28def33 1306 netdev_err(ds->ports[port].netdev, "failed to update state\n");
facd95b2
GR		 1307}
1308
a2ac29d2
VD		 1309static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1310{
1311 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1312}
1313
749efcb8
VD		 1314static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1315{
1316 struct mv88e6xxx_chip *chip = ds->priv;
1317 int err;
1318
1319 mutex_lock(&chip->reg_lock);
1320 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1321 mutex_unlock(&chip->reg_lock);
1322
1323 if (err)
1324 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1325}
1326
fad09c73 1327static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1328{
a935c052 1329 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
6b17e864
VD		 1330}
1331
fad09c73 1332static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864 1333{
a935c052 1334 int err;
6b17e864 1335
a935c052
VD		 1336 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1337 if (err)
1338 return err;
6b17e864 1339
fad09c73 1340 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1341}
1342
fad09c73 1343static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1344{
1345 int ret;
1346
fad09c73 1347 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1348 if (ret < 0)
1349 return ret;
1350
fad09c73 1351 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1352}
1353
fad09c73 1354static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1355 struct mv88e6xxx_vtu_entry *entry,
b8fee957
VD		 1356 unsigned int nibble_offset)
1357{
b8fee957 1358 u16 regs[3];
a935c052 1359 int i, err;
b8fee957
VD		 1360
1361 for (i = 0; i < 3; ++i) {
a935c052 1362 u16 *reg = &regs[i];
b8fee957 1363
a935c052
VD		 1364 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1365 if (err)
1366 return err;
b8fee957
VD		 1367 }
1368
370b4ffb 1369 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b8fee957
VD		 1370 unsigned int shift = (i % 4) * 4 + nibble_offset;
1371 u16 reg = regs[i / 4];
1372
1373 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1374 }
1375
1376 return 0;
1377}
1378
fad09c73 1379static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1380 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1381{
fad09c73 1382 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1383}
1384
fad09c73 1385static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1386 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1387{
fad09c73 1388 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1389}
1390
fad09c73 1391static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1392 struct mv88e6xxx_vtu_entry *entry,
7dad08d7
VD		 1393 unsigned int nibble_offset)
1394{
7dad08d7 1395 u16 regs[3] = { 0 };
a935c052 1396 int i, err;
7dad08d7 1397
370b4ffb 1398 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7dad08d7
VD		 1399 unsigned int shift = (i % 4) * 4 + nibble_offset;
1400 u8 data = entry->data[i];
1401
1402 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1403 }
1404
1405 for (i = 0; i < 3; ++i) {
a935c052
VD		 1406 u16 reg = regs[i];
1407
1408 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1409 if (err)
1410 return err;
7dad08d7
VD		 1411 }
1412
1413 return 0;
1414}
1415
fad09c73 1416static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1417 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1418{
fad09c73 1419 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1420}
1421
fad09c73 1422static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1423 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1424{
fad09c73 1425 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1426}
1427
fad09c73 1428static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1429{
a935c052
VD		 1430 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1431 vid & GLOBAL_VTU_VID_MASK);
36d04ba1
VD		 1432}
1433
fad09c73 1434static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b4e47c0f 1435 struct mv88e6xxx_vtu_entry *entry)
b8fee957 1436{
b4e47c0f 1437 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1438 u16 val;
1439 int err;
b8fee957 1440
a935c052
VD		 1441 err = _mv88e6xxx_vtu_wait(chip);
1442 if (err)
1443 return err;
b8fee957 1444
a935c052
VD		 1445 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1446 if (err)
1447 return err;
b8fee957 1448
a935c052
VD		 1449 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1450 if (err)
1451 return err;
b8fee957 1452
a935c052
VD		 1453 next.vid = val & GLOBAL_VTU_VID_MASK;
1454 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
b8fee957
VD		 1455
1456 if (next.valid) {
a935c052
VD		 1457 err = mv88e6xxx_vtu_data_read(chip, &next);
1458 if (err)
1459 return err;
b8fee957 1460
6dc10bbc 1461 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
a935c052
VD		 1462 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1463 if (err)
1464 return err;
b8fee957 1465
a935c052 1466 next.fid = val & GLOBAL_VTU_FID_MASK;
fad09c73 1467 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1468 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1469 * VTU DBNum[3:0] are located in VTU Operation 3:0
1470 */
a935c052
VD		 1471 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1472 if (err)
1473 return err;
11ea809f 1474
a935c052
VD		 1475 next.fid = (val & 0xf00) >> 4;
1476 next.fid |= val & 0xf;
2e7bd5ef 1477 }
b8fee957 1478
fad09c73 1479 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
a935c052
VD		 1480 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1481 if (err)
1482 return err;
b8fee957 1483
a935c052 1484 next.sid = val & GLOBAL_VTU_SID_MASK;
b8fee957
VD		 1485 }
1486 }
1487
1488 *entry = next;
1489 return 0;
1490}
1491
f81ec90f
VD		 1492static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1493 struct switchdev_obj_port_vlan *vlan,
1494 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1495{
04bed143 1496 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1497 struct mv88e6xxx_vtu_entry next;
ceff5eff
VD		 1498 u16 pvid;
1499 int err;
1500
fad09c73 1501 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1502 return -EOPNOTSUPP;
1503
fad09c73 1504 mutex_lock(&chip->reg_lock);
ceff5eff 1505
77064f37 1506 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
ceff5eff
VD		 1507 if (err)
1508 goto unlock;
1509
fad09c73 1510 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1511 if (err)
1512 goto unlock;
1513
1514 do {
fad09c73 1515 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1516 if (err)
1517 break;
1518
1519 if (!next.valid)
1520 break;
1521
1522 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1523 continue;
1524
1525 /* reinit and dump this VLAN obj */
57d32310
VD		 1526 vlan->vid_begin = next.vid;
1527 vlan->vid_end = next.vid;
ceff5eff
VD		 1528 vlan->flags = 0;
1529
1530 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1531 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1532
1533 if (next.vid == pvid)
1534 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1535
1536 err = cb(&vlan->obj);
1537 if (err)
1538 break;
1539 } while (next.vid < GLOBAL_VTU_VID_MASK);
1540
1541unlock:
fad09c73 1542 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1543
1544 return err;
1545}
1546
fad09c73 1547static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1548 struct mv88e6xxx_vtu_entry *entry)
7dad08d7 1549{
11ea809f 1550 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7 1551 u16 reg = 0;
a935c052 1552 int err;
7dad08d7 1553
a935c052
VD		 1554 err = _mv88e6xxx_vtu_wait(chip);
1555 if (err)
1556 return err;
7dad08d7
VD		 1557
1558 if (!entry->valid)
1559 goto loadpurge;
1560
1561 /* Write port member tags */
a935c052
VD		 1562 err = mv88e6xxx_vtu_data_write(chip, entry);
1563 if (err)
1564 return err;
7dad08d7 1565
fad09c73 1566 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1567 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1568 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1569 if (err)
1570 return err;
b426e5f7 1571 }
7dad08d7 1572
6dc10bbc 1573 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
7dad08d7 1574 reg = entry->fid & GLOBAL_VTU_FID_MASK;
a935c052
VD		 1575 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1576 if (err)
1577 return err;
fad09c73 1578 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1579 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1580 * VTU DBNum[3:0] are located in VTU Operation 3:0
1581 */
1582 op |= (entry->fid & 0xf0) << 8;
1583 op |= entry->fid & 0xf;
7dad08d7
VD		 1584 }
1585
1586 reg = GLOBAL_VTU_VID_VALID;
1587loadpurge:
1588 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
a935c052
VD		 1589 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1590 if (err)
1591 return err;
7dad08d7 1592
fad09c73 1593 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1594}
1595
fad09c73 1596static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
b4e47c0f 1597 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1598{
b4e47c0f 1599 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1600 u16 val;
1601 int err;
0d3b33e6 1602
a935c052
VD		 1603 err = _mv88e6xxx_vtu_wait(chip);
1604 if (err)
1605 return err;
0d3b33e6 1606
a935c052
VD		 1607 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1608 sid & GLOBAL_VTU_SID_MASK);
1609 if (err)
1610 return err;
0d3b33e6 1611
a935c052
VD		 1612 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1613 if (err)
1614 return err;
0d3b33e6 1615
a935c052
VD		 1616 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1617 if (err)
1618 return err;
0d3b33e6 1619
a935c052 1620 next.sid = val & GLOBAL_VTU_SID_MASK;
0d3b33e6 1621
a935c052
VD		 1622 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1623 if (err)
1624 return err;
0d3b33e6 1625
a935c052 1626 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
0d3b33e6
VD		 1627
1628 if (next.valid) {
a935c052
VD		 1629 err = mv88e6xxx_stu_data_read(chip, &next);
1630 if (err)
1631 return err;
0d3b33e6
VD		 1632 }
1633
1634 *entry = next;
1635 return 0;
1636}
1637
fad09c73 1638static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1639 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6
VD		 1640{
1641 u16 reg = 0;
a935c052 1642 int err;
0d3b33e6 1643
a935c052
VD		 1644 err = _mv88e6xxx_vtu_wait(chip);
1645 if (err)
1646 return err;
0d3b33e6
VD		 1647
1648 if (!entry->valid)
1649 goto loadpurge;
1650
1651 /* Write port states */
a935c052
VD		 1652 err = mv88e6xxx_stu_data_write(chip, entry);
1653 if (err)
1654 return err;
0d3b33e6
VD		 1655
1656 reg = GLOBAL_VTU_VID_VALID;
1657loadpurge:
a935c052
VD		 1658 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1659 if (err)
1660 return err;
0d3b33e6
VD		 1661
1662 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1663 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1664 if (err)
1665 return err;
0d3b33e6 1666
fad09c73 1667 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1668}
1669
fad09c73 1670static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1671{
1672 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
b4e47c0f 1673 struct mv88e6xxx_vtu_entry vlan;
2db9ce1f 1674 int i, err;
3285f9e8
VD		 1675
1676 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1677
2db9ce1f 1678 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1679 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1680 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1681 if (err)
1682 return err;
1683
1684 set_bit(*fid, fid_bitmap);
1685 }
1686
3285f9e8 1687 /* Set every FID bit used by the VLAN entries */
fad09c73 1688 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1689 if (err)
1690 return err;
1691
1692 do {
fad09c73 1693 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1694 if (err)
1695 return err;
1696
1697 if (!vlan.valid)
1698 break;
1699
1700 set_bit(vlan.fid, fid_bitmap);
1701 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1702
1703 /* The reset value 0x000 is used to indicate that multiple address
1704 * databases are not needed. Return the next positive available.
1705 */
1706 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1707 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1708 return -ENOSPC;
1709
1710 /* Clear the database */
fad09c73 1711 return _mv88e6xxx_atu_flush(chip, *fid, true);
3285f9e8
VD		 1712}
1713
fad09c73 1714static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1715 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1716{
fad09c73 1717 struct dsa_switch *ds = chip->ds;
b4e47c0f 1718 struct mv88e6xxx_vtu_entry vlan = {
0d3b33e6
VD		 1719 .valid = true,
1720 .vid = vid,
1721 };
3285f9e8
VD		 1722 int i, err;
1723
fad09c73 1724 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
3285f9e8
VD		 1725 if (err)
1726 return err;
0d3b33e6 1727
3d131f07 1728 /* exclude all ports except the CPU and DSA ports */
370b4ffb 1729 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
3d131f07
VD		 1730 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1731 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1732 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1733
fad09c73 1734 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
a75961d0
GC		 1735 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip) ||
1736 mv88e6xxx_6341_family(chip)) {
b4e47c0f 1737 struct mv88e6xxx_vtu_entry vstp;
0d3b33e6
VD		 1738
1739 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1740 * implemented, only one STU entry is needed to cover all VTU
1741 * entries. Thus, validate the SID 0.
1742 */
1743 vlan.sid = 0;
fad09c73 1744 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1745 if (err)
1746 return err;
1747
1748 if (vstp.sid != vlan.sid || !vstp.valid) {
1749 memset(&vstp, 0, sizeof(vstp));
1750 vstp.valid = true;
1751 vstp.sid = vlan.sid;
1752
fad09c73 1753 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1754 if (err)
1755 return err;
1756 }
0d3b33e6
VD		 1757 }
1758
1759 *entry = vlan;
1760 return 0;
1761}
1762
fad09c73 1763static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1764 struct mv88e6xxx_vtu_entry *entry, bool creat)
2fb5ef09
VD		 1765{
1766 int err;
1767
1768 if (!vid)
1769 return -EINVAL;
1770
fad09c73 1771 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1772 if (err)
1773 return err;
1774
fad09c73 1775 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1776 if (err)
1777 return err;
1778
1779 if (entry->vid != vid || !entry->valid) {
1780 if (!creat)
1781 return -EOPNOTSUPP;
1782 /* -ENOENT would've been more appropriate, but switchdev expects
1783 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1784 */
1785
fad09c73 1786 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1787 }
1788
1789 return err;
1790}
1791
da9c359e
VD		 1792static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1793 u16 vid_begin, u16 vid_end)
1794{
04bed143 1795 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1796 struct mv88e6xxx_vtu_entry vlan;
da9c359e
VD		 1797 int i, err;
1798
1799 if (!vid_begin)
1800 return -EOPNOTSUPP;
1801
fad09c73 1802 mutex_lock(&chip->reg_lock);
da9c359e 1803
fad09c73 1804 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1805 if (err)
1806 goto unlock;
1807
1808 do {
fad09c73 1809 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1810 if (err)
1811 goto unlock;
1812
1813 if (!vlan.valid)
1814 break;
1815
1816 if (vlan.vid > vid_end)
1817 break;
1818
370b4ffb 1819 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1820 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1821 continue;
1822
66e2809d
AL		 1823 if (!ds->ports[port].netdev)
1824 continue;
1825
da9c359e
VD		 1826 if (vlan.data[i] ==
1827 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1828 continue;
1829
fae8a25e
VD		 1830 if (ds->ports[i].bridge_dev ==
1831 ds->ports[port].bridge_dev)
da9c359e
VD		 1832 break; /* same bridge, check next VLAN */
1833
fae8a25e 1834 if (!ds->ports[i].bridge_dev)
66e2809d
AL		 1835 continue;
1836
c8b09808 1837 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1838 "hardware VLAN %d already used by %s\n",
1839 vlan.vid,
fae8a25e 1840 netdev_name(ds->ports[i].bridge_dev));
da9c359e
VD		 1841 err = -EOPNOTSUPP;
1842 goto unlock;
1843 }
1844 } while (vlan.vid < vid_end);
1845
1846unlock:
fad09c73 1847 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1848
1849 return err;
1850}
1851
f81ec90f
VD		 1852static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1853 bool vlan_filtering)
214cdb99 1854{
04bed143 1855 struct mv88e6xxx_chip *chip = ds->priv;
385a0995 1856 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
214cdb99 1857 PORT_CONTROL_2_8021Q_DISABLED;
0e7b9925 1858 int err;
214cdb99 1859
fad09c73 1860 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1861 return -EOPNOTSUPP;
1862
fad09c73 1863 mutex_lock(&chip->reg_lock);
385a0995 1864 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1865 mutex_unlock(&chip->reg_lock);
214cdb99 1866
0e7b9925 1867 return err;
214cdb99
VD		 1868}
1869
57d32310
VD		 1870static int
1871mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1872 const struct switchdev_obj_port_vlan *vlan,
1873 struct switchdev_trans *trans)
76e398a6 1874{
04bed143 1875 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1876 int err;
1877
fad09c73 1878 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1879 return -EOPNOTSUPP;
1880
da9c359e
VD		 1881 /* If the requested port doesn't belong to the same bridge as the VLAN
1882 * members, do not support it (yet) and fallback to software VLAN.
1883 */
1884 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1885 vlan->vid_end);
1886 if (err)
1887 return err;
1888
76e398a6
VD		 1889 /* We don't need any dynamic resource from the kernel (yet),
1890 * so skip the prepare phase.
1891 */
1892 return 0;
1893}
1894
fad09c73 1895static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1896 u16 vid, bool untagged)
0d3b33e6 1897{
b4e47c0f 1898 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1899 int err;
1900
fad09c73 1901 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1902 if (err)
76e398a6 1903 return err;
0d3b33e6 1904
0d3b33e6
VD		 1905 vlan.data[port] = untagged ?
1906 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1907 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1908
fad09c73 1909 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1910}
1911
f81ec90f
VD		 1912static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1913 const struct switchdev_obj_port_vlan *vlan,
1914 struct switchdev_trans *trans)
76e398a6 1915{
04bed143 1916 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1917 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1918 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1919 u16 vid;
76e398a6 1920
fad09c73 1921 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1922 return;
1923
fad09c73 1924 mutex_lock(&chip->reg_lock);
76e398a6 1925
4d5770b3 1926 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1927 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1928 netdev_err(ds->ports[port].netdev,
1929 "failed to add VLAN %d%c\n",
4d5770b3 1930 vid, untagged ? 'u' : 't');
76e398a6 1931
77064f37 1932 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
c8b09808 1933 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1934 vlan->vid_end);
0d3b33e6 1935
fad09c73 1936 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1937}
1938
fad09c73 1939static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1940 int port, u16 vid)
7dad08d7 1941{
fad09c73 1942 struct dsa_switch *ds = chip->ds;
b4e47c0f 1943 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1944 int i, err;
1945
fad09c73 1946 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1947 if (err)
76e398a6 1948 return err;
7dad08d7 1949
2fb5ef09
VD		 1950 /* Tell switchdev if this VLAN is handled in software */
1951 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1952 return -EOPNOTSUPP;
7dad08d7
VD		 1953
1954 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1955
1956 /* keep the VLAN unless all ports are excluded */
f02bdffc 1957 vlan.valid = false;
370b4ffb 1958 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
3d131f07 1959 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1960 continue;
1961
1962 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1963 vlan.valid = true;
7dad08d7
VD		 1964 break;
1965 }
1966 }
1967
fad09c73 1968 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1969 if (err)
1970 return err;
1971
fad09c73 1972 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1973}
1974
f81ec90f
VD		 1975static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1976 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1977{
04bed143 1978 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1979 u16 pvid, vid;
1980 int err = 0;
1981
fad09c73 1982 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1983 return -EOPNOTSUPP;
1984
fad09c73 1985 mutex_lock(&chip->reg_lock);
76e398a6 1986
77064f37 1987 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1988 if (err)
1989 goto unlock;
1990
76e398a6 1991 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1992 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1993 if (err)
1994 goto unlock;
1995
1996 if (vid == pvid) {
77064f37 1997 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1998 if (err)
1999 goto unlock;
2000 }
2001 }
2002
7dad08d7 2003unlock:
fad09c73 2004 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 2005
2006 return err;
2007}
2008
fad09c73 2009static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
c5723ac5 2010 const unsigned char *addr)
defb05b9 2011{
a935c052 2012 int i, err;
defb05b9
GR		 2013
2014 for (i = 0; i < 3; i++) {
a935c052
VD		 2015 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
2016 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2017 if (err)
2018 return err;
defb05b9
GR		 2019 }
2020
2021 return 0;
2022}
2023
fad09c73 2024static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
158bc065 2025 unsigned char *addr)
defb05b9 2026{
a935c052
VD		 2027 u16 val;
2028 int i, err;
defb05b9
GR		 2029
2030 for (i = 0; i < 3; i++) {
a935c052
VD		 2031 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
2032 if (err)
2033 return err;
2034
2035 addr[i * 2] = val >> 8;
2036 addr[i * 2 + 1] = val & 0xff;
defb05b9
GR		 2037 }
2038
2039 return 0;
2040}
2041
fad09c73 2042static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
fd231c82 2043 struct mv88e6xxx_atu_entry *entry)
defb05b9 2044{
6630e236
VD		 2045 int ret;
2046
fad09c73 2047 ret = _mv88e6xxx_atu_wait(chip);
defb05b9
GR		 2048 if (ret < 0)
2049 return ret;
2050
fad09c73 2051 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
defb05b9
GR		 2052 if (ret < 0)
2053 return ret;
2054
fad09c73 2055 ret = _mv88e6xxx_atu_data_write(chip, entry);
fd231c82 2056 if (ret < 0)
87820510
VD		 2057 return ret;
2058
fad09c73 2059 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2060}
87820510 2061
88472939
VD		 2062static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2063 struct mv88e6xxx_atu_entry *entry);
2064
2065static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2066 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2067{
2068 struct mv88e6xxx_atu_entry next;
2069 int err;
2070
59527581
AL		 2071 memcpy(next.mac, addr, ETH_ALEN);
2072 eth_addr_dec(next.mac);
88472939
VD		 2073
2074 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2075 if (err)
2076 return err;
2077
2078 do {
2079 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2080 if (err)
2081 return err;
2082
2083 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2084 break;
2085
2086 if (ether_addr_equal(next.mac, addr)) {
2087 *entry = next;
2088 return 0;
2089 }
59527581 2090 } while (ether_addr_greater(addr, next.mac));
88472939
VD		 2091
2092 memset(entry, 0, sizeof(*entry));
2093 entry->fid = fid;
2094 ether_addr_copy(entry->mac, addr);
2095
2096 return 0;
2097}
2098
83dabd1f
VD		 2099static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2100 const unsigned char *addr, u16 vid,
2101 u8 state)
fd231c82 2102{
b4e47c0f 2103 struct mv88e6xxx_vtu_entry vlan;
88472939 2104 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 2105 int err;
2106
2db9ce1f
VD		 2107 /* Null VLAN ID corresponds to the port private database */
2108 if (vid == 0)
b4e48c50 2109 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2db9ce1f 2110 else
fad09c73 2111 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 2112 if (err)
2113 return err;
fd231c82 2114
88472939
VD		 2115 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2116 if (err)
2117 return err;
2118
2119 /* Purge the ATU entry only if no port is using it anymore */
2120 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2121 entry.portv_trunkid &= ~BIT(port);
2122 if (!entry.portv_trunkid)
2123 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2124 } else {
2125 entry.portv_trunkid |= BIT(port);
2126 entry.state = state;
fd231c82
VD		 2127 }
2128
fad09c73 2129 return _mv88e6xxx_atu_load(chip, &entry);
87820510
VD		 2130}
2131
f81ec90f
VD		 2132static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2133 const struct switchdev_obj_port_fdb *fdb,
2134 struct switchdev_trans *trans)
146a3206
VD		 2135{
2136 /* We don't need any dynamic resource from the kernel (yet),
2137 * so skip the prepare phase.
2138 */
2139 return 0;
2140}
2141
f81ec90f
VD		 2142static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2143 const struct switchdev_obj_port_fdb *fdb,
2144 struct switchdev_trans *trans)
87820510 2145{
04bed143 2146 struct mv88e6xxx_chip *chip = ds->priv;
87820510 2147
fad09c73 2148 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2149 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2150 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2151 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
fad09c73 2152 mutex_unlock(&chip->reg_lock);
87820510
VD		 2153}
2154
f81ec90f
VD		 2155static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2156 const struct switchdev_obj_port_fdb *fdb)
87820510 2157{
04bed143 2158 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 2159 int err;
87820510 2160
fad09c73 2161 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2162 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2163 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 2164 mutex_unlock(&chip->reg_lock);
87820510 2165
83dabd1f 2166 return err;
87820510
VD		 2167}
2168
fad09c73 2169static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
1d194046 2170 struct mv88e6xxx_atu_entry *entry)
6630e236 2171{
1d194046 2172 struct mv88e6xxx_atu_entry next = { 0 };
a935c052
VD		 2173 u16 val;
2174 int err;
1d194046
VD		 2175
2176 next.fid = fid;
defb05b9 2177
a935c052
VD		 2178 err = _mv88e6xxx_atu_wait(chip);
2179 if (err)
2180 return err;
6630e236 2181
a935c052
VD		 2182 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2183 if (err)
2184 return err;
6630e236 2185
a935c052
VD		 2186 err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2187 if (err)
2188 return err;
6630e236 2189
a935c052
VD		 2190 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2191 if (err)
2192 return err;
6630e236 2193
a935c052 2194 next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
1d194046
VD		 2195 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2196 unsigned int mask, shift;
2197
a935c052 2198 if (val & GLOBAL_ATU_DATA_TRUNK) {
1d194046
VD		 2199 next.trunk = true;
2200 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2201 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2202 } else {
2203 next.trunk = false;
2204 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2205 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2206 }
2207
a935c052 2208 next.portv_trunkid = (val & mask) >> shift;
1d194046 2209 }
cdf09697 2210
1d194046 2211 *entry = next;
cdf09697
DM		 2212 return 0;
2213}
2214
83dabd1f
VD		 2215static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2216 u16 fid, u16 vid, int port,
2217 struct switchdev_obj *obj,
2218 int (*cb)(struct switchdev_obj *obj))
74b6ba0d
VD		 2219{
2220 struct mv88e6xxx_atu_entry addr = {
2221 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2222 };
2223 int err;
2224
fad09c73 2225 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
74b6ba0d
VD		 2226 if (err)
2227 return err;
2228
2229 do {
fad09c73 2230 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
74b6ba0d 2231 if (err)
83dabd1f 2232 return err;
74b6ba0d
VD		 2233
2234 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2235 break;
2236
83dabd1f
VD		 2237 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2238 continue;
2239
2240 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2241 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 2242
83dabd1f
VD		 2243 if (!is_unicast_ether_addr(addr.mac))
2244 continue;
2245
2246 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 2247 fdb->vid = vid;
2248 ether_addr_copy(fdb->addr, addr.mac);
83dabd1f
VD		 2249 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2250 fdb->ndm_state = NUD_NOARP;
2251 else
2252 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 2253 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2254 struct switchdev_obj_port_mdb *mdb;
2255
2256 if (!is_multicast_ether_addr(addr.mac))
2257 continue;
2258
2259 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2260 mdb->vid = vid;
2261 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 2262 } else {
2263 return -EOPNOTSUPP;
74b6ba0d 2264 }
83dabd1f
VD		 2265
2266 err = cb(obj);
2267 if (err)
2268 return err;
74b6ba0d
VD		 2269 } while (!is_broadcast_ether_addr(addr.mac));
2270
2271 return err;
2272}
2273
83dabd1f
VD		 2274static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2275 struct switchdev_obj *obj,
2276 int (*cb)(struct switchdev_obj *obj))
f33475bd 2277{
b4e47c0f 2278 struct mv88e6xxx_vtu_entry vlan = {
f33475bd
VD		 2279 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2280 };
2db9ce1f 2281 u16 fid;
f33475bd
VD		 2282 int err;
2283
2db9ce1f 2284 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 2285 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 2286 if (err)
83dabd1f 2287 return err;
2db9ce1f 2288
83dabd1f 2289 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 2290 if (err)
83dabd1f 2291 return err;
2db9ce1f 2292
74b6ba0d 2293 /* Dump VLANs' Filtering Information Databases */
fad09c73 2294 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd 2295 if (err)
83dabd1f 2296 return err;
f33475bd
VD		 2297
2298 do {
fad09c73 2299 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2300 if (err)
83dabd1f 2301 return err;
f33475bd
VD		 2302
2303 if (!vlan.valid)
2304 break;
2305
83dabd1f
VD		 2306 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2307 obj, cb);
f33475bd 2308 if (err)
83dabd1f 2309 return err;
f33475bd
VD		 2310 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2311
83dabd1f
VD		 2312 return err;
2313}
2314
2315static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2316 struct switchdev_obj_port_fdb *fdb,
2317 int (*cb)(struct switchdev_obj *obj))
2318{
04bed143 2319 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 2320 int err;
2321
2322 mutex_lock(&chip->reg_lock);
2323 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 2324 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2325
2326 return err;
2327}
2328
f81ec90f 2329static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
fae8a25e 2330 struct net_device *br)
e79a8bcb 2331{
04bed143 2332 struct mv88e6xxx_chip *chip = ds->priv;
1d9619d5 2333 int i, err = 0;
466dfa07 2334
fad09c73 2335 mutex_lock(&chip->reg_lock);
466dfa07 2336
fae8a25e 2337 /* Remap each port's VLANTable */
370b4ffb 2338 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
fae8a25e 2339 if (ds->ports[i].bridge_dev == br) {
fad09c73 2340 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2341 if (err)
2342 break;
2343 }
2344 }
2345
fad09c73 2346 mutex_unlock(&chip->reg_lock);
a6692754 2347
466dfa07 2348 return err;
e79a8bcb
VD		 2349}
2350
f123f2fb
VD		 2351static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2352 struct net_device *br)
66d9cd0f 2353{
04bed143 2354 struct mv88e6xxx_chip *chip = ds->priv;
16bfa702 2355 int i;
466dfa07 2356
fad09c73 2357 mutex_lock(&chip->reg_lock);
466dfa07 2358
fae8a25e 2359 /* Remap each port's VLANTable */
370b4ffb 2360 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
fae8a25e 2361 if (i == port || ds->ports[i].bridge_dev == br)
fad09c73 2362 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2363 netdev_warn(ds->ports[i].netdev,
2364 "failed to remap\n");
b7666efe 2365
fad09c73 2366 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2367}
2368
17e708ba
VD		 2369static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2370{
2371 if (chip->info->ops->reset)
2372 return chip->info->ops->reset(chip);
2373
2374 return 0;
2375}
2376
309eca6d
VD		 2377static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2378{
2379 struct gpio_desc *gpiod = chip->reset;
2380
2381 /* If there is a GPIO connected to the reset pin, toggle it */
2382 if (gpiod) {
2383 gpiod_set_value_cansleep(gpiod, 1);
2384 usleep_range(10000, 20000);
2385 gpiod_set_value_cansleep(gpiod, 0);
2386 usleep_range(10000, 20000);
2387 }
2388}
2389
4ac4b5a6 2390static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
552238b5 2391{
4ac4b5a6 2392 int i, err;
552238b5 2393
4ac4b5a6 2394 /* Set all ports to the Disabled state */
370b4ffb 2395 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
e28def33
VD		 2396 err = mv88e6xxx_port_set_state(chip, i,
2397 PORT_CONTROL_STATE_DISABLED);
0e7b9925
AL		 2398 if (err)
2399 return err;
552238b5
VD		 2400 }
2401
4ac4b5a6
VD		 2402 /* Wait for transmit queues to drain,
2403 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2404 */
552238b5
VD		 2405 usleep_range(2000, 4000);
2406
4ac4b5a6
VD		 2407 return 0;
2408}
2409
2410static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2411{
4ac4b5a6
VD		 2412 int err;
2413
2414 err = mv88e6xxx_disable_ports(chip);
2415 if (err)
2416 return err;
2417
309eca6d 2418 mv88e6xxx_hardware_reset(chip);
552238b5 2419
17e708ba 2420 return mv88e6xxx_software_reset(chip);
552238b5
VD		 2421}
2422
09cb7dfd 2423static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
13a7ebb3 2424{
09cb7dfd
VD		 2425 u16 val;
2426 int err;
13a7ebb3 2427
09cb7dfd
VD		 2428 /* Clear Power Down bit */
2429 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2430 if (err)
2431 return err;
13a7ebb3 2432
09cb7dfd
VD		 2433 if (val & BMCR_PDOWN) {
2434 val &= ~BMCR_PDOWN;
2435 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
13a7ebb3
PU		 2436 }
2437
09cb7dfd 2438 return err;
13a7ebb3
PU		 2439}
2440
56995cbc
AL		 2441static int mv88e6xxx_setup_port_dsa(struct mv88e6xxx_chip *chip, int port,
2442 int upstream_port)
2443{
2444 int err;
2445
2446 err = chip->info->ops->port_set_frame_mode(
2447 chip, port, MV88E6XXX_FRAME_MODE_DSA);
2448 if (err)
2449 return err;
2450
2451 return chip->info->ops->port_set_egress_unknowns(
2452 chip, port, port == upstream_port);
2453}
2454
2455static int mv88e6xxx_setup_port_cpu(struct mv88e6xxx_chip *chip, int port)
2456{
2457 int err;
2458
2459 switch (chip->info->tag_protocol) {
2460 case DSA_TAG_PROTO_EDSA:
2461 err = chip->info->ops->port_set_frame_mode(
2462 chip, port, MV88E6XXX_FRAME_MODE_ETHERTYPE);
2463 if (err)
2464 return err;
2465
2466 err = mv88e6xxx_port_set_egress_mode(
2467 chip, port, PORT_CONTROL_EGRESS_ADD_TAG);
2468 if (err)
2469 return err;
2470
2471 if (chip->info->ops->port_set_ether_type)
2472 err = chip->info->ops->port_set_ether_type(
2473 chip, port, ETH_P_EDSA);
2474 break;
2475
2476 case DSA_TAG_PROTO_DSA:
2477 err = chip->info->ops->port_set_frame_mode(
2478 chip, port, MV88E6XXX_FRAME_MODE_DSA);
2479 if (err)
2480 return err;
2481
2482 err = mv88e6xxx_port_set_egress_mode(
2483 chip, port, PORT_CONTROL_EGRESS_UNMODIFIED);
2484 break;
2485 default:
2486 err = -EINVAL;
2487 }
2488
2489 if (err)
2490 return err;
2491
2492 return chip->info->ops->port_set_egress_unknowns(chip, port, true);
2493}
2494
2495static int mv88e6xxx_setup_port_normal(struct mv88e6xxx_chip *chip, int port)
2496{
2497 int err;
2498
2499 err = chip->info->ops->port_set_frame_mode(
2500 chip, port, MV88E6XXX_FRAME_MODE_NORMAL);
2501 if (err)
2502 return err;
2503
2504 return chip->info->ops->port_set_egress_unknowns(chip, port, false);
2505}
2506
ea698f4f
VD		 2507static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2508{
2509 bool message = dsa_is_dsa_port(chip->ds, port);
2510
2511 return mv88e6xxx_port_set_message_port(chip, port, message);
2512}
2513
fad09c73 2514static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2515{
fad09c73 2516 struct dsa_switch *ds = chip->ds;
0e7b9925 2517 int err;
54d792f2 2518 u16 reg;
d827e88a 2519
d78343d2
VD		 2520 /* MAC Forcing register: don't force link, speed, duplex or flow control
2521 * state to any particular values on physical ports, but force the CPU
2522 * port and all DSA ports to their maximum bandwidth and full duplex.
2523 */
2524 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2525 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2526 SPEED_MAX, DUPLEX_FULL,
2527 PHY_INTERFACE_MODE_NA);
2528 else
2529 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2530 SPEED_UNFORCED, DUPLEX_UNFORCED,
2531 PHY_INTERFACE_MODE_NA);
2532 if (err)
2533 return err;
54d792f2
AL		 2534
2535 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2536 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2537 * tunneling, determine priority by looking at 802.1p and IP
2538 * priority fields (IP prio has precedence), and set STP state
2539 * to Forwarding.
2540 *
2541 * If this is the CPU link, use DSA or EDSA tagging depending
2542 * on which tagging mode was configured.
2543 *
2544 * If this is a link to another switch, use DSA tagging mode.
2545 *
2546 * If this is the upstream port for this switch, enable
2547 * forwarding of unknown unicasts and multicasts.
2548 */
56995cbc 2549 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
54d792f2
AL		 2550 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2551 PORT_CONTROL_STATE_FORWARDING;
56995cbc
AL		 2552 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2553 if (err)
2554 return err;
6083ce71 2555
56995cbc
AL		 2556 if (dsa_is_cpu_port(ds, port)) {
2557 err = mv88e6xxx_setup_port_cpu(chip, port);
2558 } else if (dsa_is_dsa_port(ds, port)) {
2559 err = mv88e6xxx_setup_port_dsa(chip, port,
2560 dsa_upstream_port(ds));
2561 } else {
2562 err = mv88e6xxx_setup_port_normal(chip, port);
54d792f2 2563 }
56995cbc
AL		 2564 if (err)
2565 return err;
54d792f2 2566
13a7ebb3
PU		 2567 /* If this port is connected to a SerDes, make sure the SerDes is not
2568 * powered down.
2569 */
09cb7dfd 2570 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
0e7b9925
AL		 2571 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2572 if (err)
2573 return err;
2574 reg &= PORT_STATUS_CMODE_MASK;
2575 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2576 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2577 (reg == PORT_STATUS_CMODE_SGMII)) {
2578 err = mv88e6xxx_serdes_power_on(chip);
2579 if (err < 0)
2580 return err;
13a7ebb3
PU		 2581 }
2582 }
2583
8efdda4a 2584 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2585 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2586 * untagged frames on this port, do a destination address lookup on all
2587 * received packets as usual, disable ARP mirroring and don't send a
2588 * copy of all transmitted/received frames on this port to the CPU.
54d792f2 2589 */
a23b2961
AL		 2590 err = mv88e6xxx_port_set_map_da(chip, port);
2591 if (err)
2592 return err;
8efdda4a 2593
a23b2961
AL		 2594 reg = 0;
2595 if (chip->info->ops->port_set_upstream_port) {
2596 err = chip->info->ops->port_set_upstream_port(
2597 chip, port, dsa_upstream_port(ds));
0e7b9925
AL		 2598 if (err)
2599 return err;
54d792f2
AL		 2600 }
2601
a23b2961
AL		 2602 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2603 PORT_CONTROL_2_8021Q_DISABLED);
2604 if (err)
2605 return err;
2606
5f436666
AL		 2607 if (chip->info->ops->port_jumbo_config) {
2608 err = chip->info->ops->port_jumbo_config(chip, port);
2609 if (err)
2610 return err;
2611 }
2612
54d792f2
AL		 2613 /* Port Association Vector: when learning source addresses
2614 * of packets, add the address to the address database using
2615 * a port bitmap that has only the bit for this port set and
2616 * the other bits clear.
2617 */
4c7ea3c0 2618 reg = 1 << port;
996ecb82
VD		 2619 /* Disable learning for CPU port */
2620 if (dsa_is_cpu_port(ds, port))
65fa4027 2621 reg = 0;
4c7ea3c0 2622
0e7b9925
AL		 2623 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2624 if (err)
2625 return err;
54d792f2
AL		 2626
2627 /* Egress rate control 2: disable egress rate control. */
0e7b9925
AL		 2628 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2629 if (err)
2630 return err;
54d792f2 2631
b35d322a
AL		 2632 if (chip->info->ops->port_pause_config) {
2633 err = chip->info->ops->port_pause_config(chip, port);
0e7b9925
AL		 2634 if (err)
2635 return err;
b35d322a 2636 }
54d792f2 2637
b35d322a
AL		 2638 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2639 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
a75961d0 2640 mv88e6xxx_6320_family(chip) || mv88e6xxx_6341_family(chip)) {
54d792f2
AL		 2641 /* Port ATU control: disable limiting the number of
2642 * address database entries that this port is allowed
2643 * to use.
2644 */
0e7b9925
AL		 2645 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2646 0x0000);
54d792f2
AL		 2647 /* Priority Override: disable DA, SA and VTU priority
2648 * override.
2649 */
0e7b9925
AL		 2650 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2651 0x0000);
2652 if (err)
2653 return err;
ef0a7318 2654 }
2bbb33be 2655
ef0a7318
AL		 2656 if (chip->info->ops->port_tag_remap) {
2657 err = chip->info->ops->port_tag_remap(chip, port);
0e7b9925
AL		 2658 if (err)
2659 return err;
54d792f2
AL		 2660 }
2661
ef70b111
AL		 2662 if (chip->info->ops->port_egress_rate_limiting) {
2663 err = chip->info->ops->port_egress_rate_limiting(chip, port);
0e7b9925
AL		 2664 if (err)
2665 return err;
54d792f2
AL		 2666 }
2667
ea698f4f 2668 err = mv88e6xxx_setup_message_port(chip, port);
0e7b9925
AL		 2669 if (err)
2670 return err;
d827e88a 2671
207afda1 2672 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2673 * database, and allow bidirectional communication between the
2674 * CPU and DSA port(s), and the other ports.
d827e88a 2675 */
b4e48c50 2676 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 2677 if (err)
2678 return err;
2db9ce1f 2679
0e7b9925
AL		 2680 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2681 if (err)
2682 return err;
d827e88a
GR		 2683
2684 /* Default VLAN ID and priority: don't set a default VLAN
2685 * ID, and set the default packet priority to zero.
2686 */
0e7b9925 2687 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
dbde9e66
AL		 2688}
2689
aa0938c6 2690static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3b4caa1b
VD		 2691{
2692 int err;
2693
a935c052 2694 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
3b4caa1b
VD		 2695 if (err)
2696 return err;
2697
a935c052 2698 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
3b4caa1b
VD		 2699 if (err)
2700 return err;
2701
a935c052
VD		 2702 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2703 if (err)
2704 return err;
2705
2706 return 0;
3b4caa1b
VD		 2707}
2708
2cfcd964
VD		 2709static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2710 unsigned int ageing_time)
2711{
04bed143 2712 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2713 int err;
2714
2715 mutex_lock(&chip->reg_lock);
720c6343 2716 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2cfcd964
VD		 2717 mutex_unlock(&chip->reg_lock);
2718
2719 return err;
2720}
2721
9729934c 2722static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2723{
fad09c73 2724 struct dsa_switch *ds = chip->ds;
b0745e87 2725 u32 upstream_port = dsa_upstream_port(ds);
552238b5 2726 int err;
54d792f2 2727
119477bd
VD		 2728 /* Enable the PHY Polling Unit if present, don't discard any packets,
2729 * and mask all interrupt sources.
2730 */
a199d8b6 2731 err = mv88e6xxx_ppu_enable(chip);
119477bd
VD		 2732 if (err)
2733 return err;
2734
33641994
AL		 2735 if (chip->info->ops->g1_set_cpu_port) {
2736 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port);
2737 if (err)
2738 return err;
2739 }
2740
2741 if (chip->info->ops->g1_set_egress_port) {
2742 err = chip->info->ops->g1_set_egress_port(chip, upstream_port);
2743 if (err)
2744 return err;
2745 }
b0745e87 2746
50484ff4 2747 /* Disable remote management, and set the switch's DSA device number. */
a935c052
VD		 2748 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2749 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2750 (ds->index & 0x1f));
50484ff4
VD		 2751 if (err)
2752 return err;
2753
acddbd21
VD		 2754 /* Clear all the VTU and STU entries */
2755 err = _mv88e6xxx_vtu_stu_flush(chip);
2756 if (err < 0)
2757 return err;
2758
54d792f2
AL		 2759 /* Set the default address aging time to 5 minutes, and
2760 * enable address learn messages to be sent to all message
2761 * ports.
2762 */
a935c052
VD		 2763 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2764 GLOBAL_ATU_CONTROL_LEARN2ALL);
48ace4ef 2765 if (err)
08a01261 2766 return err;
54d792f2 2767
9729934c
VD		 2768 /* Clear all ATU entries */
2769 err = _mv88e6xxx_atu_flush(chip, 0, true);
2770 if (err)
2771 return err;
2772
54d792f2 2773 /* Configure the IP ToS mapping registers. */
a935c052 2774 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2775 if (err)
08a01261 2776 return err;
a935c052 2777 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2778 if (err)
08a01261 2779 return err;
a935c052 2780 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2781 if (err)
08a01261 2782 return err;
a935c052 2783 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2784 if (err)
08a01261 2785 return err;
a935c052 2786 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2787 if (err)
08a01261 2788 return err;
a935c052 2789 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2790 if (err)
08a01261 2791 return err;
a935c052 2792 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2793 if (err)
08a01261 2794 return err;
a935c052 2795 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2796 if (err)
08a01261 2797 return err;
54d792f2
AL		 2798
2799 /* Configure the IEEE 802.1p priority mapping register. */
a935c052 2800 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2801 if (err)
08a01261 2802 return err;
54d792f2 2803
de227387
AL		 2804 /* Initialize the statistics unit */
2805 err = mv88e6xxx_stats_set_histogram(chip);
2806 if (err)
2807 return err;
2808
9729934c 2809 /* Clear the statistics counters for all ports */
a935c052
VD		 2810 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2811 GLOBAL_STATS_OP_FLUSH_ALL);
9729934c
VD		 2812 if (err)
2813 return err;
2814
2815 /* Wait for the flush to complete. */
7f9ef3af 2816 err = mv88e6xxx_g1_stats_wait(chip);
9729934c
VD		 2817 if (err)
2818 return err;
2819
2820 return 0;
2821}
2822
f81ec90f 2823static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2824{
04bed143 2825 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2826 int err;
a1a6a4d1
VD		 2827 int i;
2828
fad09c73 2829 chip->ds = ds;
a3c53be5 2830 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
08a01261 2831
fad09c73 2832 mutex_lock(&chip->reg_lock);
08a01261 2833
9729934c 2834 /* Setup Switch Port Registers */
370b4ffb 2835 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
9729934c
VD		 2836 err = mv88e6xxx_setup_port(chip, i);
2837 if (err)
2838 goto unlock;
2839 }
2840
2841 /* Setup Switch Global 1 Registers */
2842 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2843 if (err)
2844 goto unlock;
2845
9729934c
VD		 2846 /* Setup Switch Global 2 Registers */
2847 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2848 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2849 if (err)
2850 goto unlock;
2851 }
08a01261 2852
a2ac29d2
VD		 2853 err = mv88e6xxx_atu_setup(chip);
2854 if (err)
2855 goto unlock;
2856
6e55f698
AL		 2857 /* Some generations have the configuration of sending reserved
2858 * management frames to the CPU in global2, others in
2859 * global1. Hence it does not fit the two setup functions
2860 * above.
2861 */
2862 if (chip->info->ops->mgmt_rsvd2cpu) {
2863 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2864 if (err)
2865 goto unlock;
2866 }
2867
6b17e864 2868unlock:
fad09c73 2869 mutex_unlock(&chip->reg_lock);
db687a56 2870
48ace4ef 2871 return err;
54d792f2
AL		 2872}
2873
3b4caa1b
VD		 2874static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2875{
04bed143 2876 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2877 int err;
2878
b073d4e2
VD		 2879 if (!chip->info->ops->set_switch_mac)
2880 return -EOPNOTSUPP;
3b4caa1b 2881
b073d4e2
VD		 2882 mutex_lock(&chip->reg_lock);
2883 err = chip->info->ops->set_switch_mac(chip, addr);
3b4caa1b
VD		 2884 mutex_unlock(&chip->reg_lock);
2885
2886 return err;
2887}
2888
e57e5e77 2889static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2890{
0dd12d54
AL		 2891 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2892 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77
VD		 2893 u16 val;
2894 int err;
fd3a0ee4 2895
ee26a228
AL		 2896 if (!chip->info->ops->phy_read)
2897 return -EOPNOTSUPP;
2898
fad09c73 2899 mutex_lock(&chip->reg_lock);
ee26a228 2900 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
fad09c73 2901 mutex_unlock(&chip->reg_lock);
e57e5e77 2902
da9f3301
AL		 2903 if (reg == MII_PHYSID2) {
2904 /* Some internal PHYS don't have a model number. Use
2905 * the mv88e6390 family model number instead.
2906 */
2907 if (!(val & 0x3f0))
2908 val |= PORT_SWITCH_ID_PROD_NUM_6390;
2909 }
2910
e57e5e77 2911 return err ? err : val;
fd3a0ee4
AL		 2912}
2913
e57e5e77 2914static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2915{
0dd12d54
AL		 2916 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2917 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77 2918 int err;
fd3a0ee4 2919
ee26a228
AL		 2920 if (!chip->info->ops->phy_write)
2921 return -EOPNOTSUPP;
2922
fad09c73 2923 mutex_lock(&chip->reg_lock);
ee26a228 2924 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
fad09c73 2925 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2926
2927 return err;
fd3a0ee4
AL		 2928}
2929
fad09c73 2930static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
a3c53be5
AL		 2931 struct device_node *np,
2932 bool external)
b516d453
AL		 2933{
2934 static int index;
0dd12d54 2935 struct mv88e6xxx_mdio_bus *mdio_bus;
b516d453
AL		 2936 struct mii_bus *bus;
2937 int err;
2938
0dd12d54 2939 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
b516d453
AL		 2940 if (!bus)
2941 return -ENOMEM;
2942
0dd12d54 2943 mdio_bus = bus->priv;
a3c53be5 2944 mdio_bus->bus = bus;
0dd12d54 2945 mdio_bus->chip = chip;
a3c53be5
AL		 2946 INIT_LIST_HEAD(&mdio_bus->list);
2947 mdio_bus->external = external;
0dd12d54 2948
b516d453
AL		 2949 if (np) {
2950 bus->name = np->full_name;
2951 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2952 } else {
2953 bus->name = "mv88e6xxx SMI";
2954 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2955 }
2956
2957 bus->read = mv88e6xxx_mdio_read;
2958 bus->write = mv88e6xxx_mdio_write;
fad09c73 2959 bus->parent = chip->dev;
b516d453 2960
a3c53be5
AL		 2961 if (np)
2962 err = of_mdiobus_register(bus, np);
b516d453
AL		 2963 else
2964 err = mdiobus_register(bus);
2965 if (err) {
fad09c73 2966 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
a3c53be5 2967 return err;
b516d453 2968 }
a3c53be5
AL		 2969
2970 if (external)
2971 list_add_tail(&mdio_bus->list, &chip->mdios);
2972 else
2973 list_add(&mdio_bus->list, &chip->mdios);
b516d453
AL		 2974
2975 return 0;
a3c53be5 2976}
b516d453 2977
a3c53be5
AL		 2978static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2979 { .compatible = "marvell,mv88e6xxx-mdio-external",
2980 .data = (void *)true },
2981 { },
2982};
b516d453 2983
a3c53be5
AL		 2984static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2985 struct device_node *np)
2986{
2987 const struct of_device_id *match;
2988 struct device_node *child;
2989 int err;
2990
2991 /* Always register one mdio bus for the internal/default mdio
2992 * bus. This maybe represented in the device tree, but is
2993 * optional.
2994 */
2995 child = of_get_child_by_name(np, "mdio");
2996 err = mv88e6xxx_mdio_register(chip, child, false);
2997 if (err)
2998 return err;
2999
3000 /* Walk the device tree, and see if there are any other nodes
3001 * which say they are compatible with the external mdio
3002 * bus.
3003 */
3004 for_each_available_child_of_node(np, child) {
3005 match = of_match_node(mv88e6xxx_mdio_external_match, child);
3006 if (match) {
3007 err = mv88e6xxx_mdio_register(chip, child, true);
3008 if (err)
3009 return err;
3010 }
3011 }
3012
3013 return 0;
b516d453
AL		 3014}
3015
a3c53be5 3016static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 3017
3018{
a3c53be5
AL		 3019 struct mv88e6xxx_mdio_bus *mdio_bus;
3020 struct mii_bus *bus;
b516d453 3021
a3c53be5
AL		 3022 list_for_each_entry(mdio_bus, &chip->mdios, list) {
3023 bus = mdio_bus->bus;
b516d453 3024
a3c53be5
AL		 3025 mdiobus_unregister(bus);
3026 }
b516d453
AL		 3027}
3028
855b1932
VD		 3029static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3030{
04bed143 3031 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3032
3033 return chip->eeprom_len;
3034}
3035
855b1932
VD		 3036static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3037 struct ethtool_eeprom *eeprom, u8 *data)
3038{
04bed143 3039 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3040 int err;
3041
ee4dc2e7
VD		 3042 if (!chip->info->ops->get_eeprom)
3043 return -EOPNOTSUPP;
855b1932 3044
ee4dc2e7
VD		 3045 mutex_lock(&chip->reg_lock);
3046 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 3047 mutex_unlock(&chip->reg_lock);
3048
3049 if (err)
3050 return err;
3051
3052 eeprom->magic = 0xc3ec4951;
3053
3054 return 0;
3055}
3056
855b1932
VD		 3057static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3058 struct ethtool_eeprom *eeprom, u8 *data)
3059{
04bed143 3060 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3061 int err;
3062
ee4dc2e7
VD		 3063 if (!chip->info->ops->set_eeprom)
3064 return -EOPNOTSUPP;
3065
855b1932
VD		 3066 if (eeprom->magic != 0xc3ec4951)
3067 return -EINVAL;
3068
3069 mutex_lock(&chip->reg_lock);
ee4dc2e7 3070 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 3071 mutex_unlock(&chip->reg_lock);
3072
3073 return err;
3074}
3075
b3469dd8 3076static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 3077 /* MV88E6XXX_FAMILY_6097 */
b073d4e2 3078 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3079 .phy_read = mv88e6xxx_phy_ppu_read,
3080 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3081 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3082 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3083 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3084 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3085 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3086 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3087 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 3088 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3089 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3090 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3091 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3092 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3093 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3094 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3095 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3096 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3097 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3098 .ppu_enable = mv88e6185_g1_ppu_enable,
3099 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3100 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3101};
3102
3103static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 3104 /* MV88E6XXX_FAMILY_6095 */
b073d4e2 3105 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3106 .phy_read = mv88e6xxx_phy_ppu_read,
3107 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3108 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3109 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3110 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 3111 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
a23b2961
AL		 3112 .port_set_egress_unknowns = mv88e6095_port_set_egress_unknowns,
3113 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 3114 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3115 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3116 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3117 .stats_get_stats = mv88e6095_stats_get_stats,
6e55f698 3118 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3119 .ppu_enable = mv88e6185_g1_ppu_enable,
3120 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3121 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3122};
3123
7d381a02 3124static const struct mv88e6xxx_ops mv88e6097_ops = {
15da3cc8 3125 /* MV88E6XXX_FAMILY_6097 */
7d381a02
SE		 3126 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3127 .phy_read = mv88e6xxx_g2_smi_phy_read,
3128 .phy_write = mv88e6xxx_g2_smi_phy_write,
3129 .port_set_link = mv88e6xxx_port_set_link,
3130 .port_set_duplex = mv88e6xxx_port_set_duplex,
3131 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3132 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3133 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3134 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3135 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3136 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3137 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
b35d322a 3138 .port_pause_config = mv88e6097_port_pause_config,
7d381a02
SE		 3139 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3140 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3141 .stats_get_strings = mv88e6095_stats_get_strings,
3142 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3143 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3144 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
91eaa475 3145 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3146 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3147 .reset = mv88e6352_g1_reset,
7d381a02
SE		 3148};
3149
b3469dd8 3150static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 3151 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3152 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 3153 .phy_read = mv88e6165_phy_read,
3154 .phy_write = mv88e6165_phy_write,
08ef7f10 3155 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3156 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3157 .port_set_speed = mv88e6185_port_set_speed,
56995cbc
AL		 3158 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3159 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,
a605a0fe 3160 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3161 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3162 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3163 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3164 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3165 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3166 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3167 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3168 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3169};
3170
3171static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 3172 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3173 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3174 .phy_read = mv88e6xxx_phy_ppu_read,
3175 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3176 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3177 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3178 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3179 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3180 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a23b2961 3181 .port_set_egress_unknowns = mv88e6095_port_set_egress_unknowns,
56995cbc 3182 .port_set_ether_type = mv88e6351_port_set_ether_type,
a23b2961 3183 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
5f436666 3184 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3185 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3186 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3187 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3188 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3189 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3190 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3191 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3192 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3193 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3194 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3195 .ppu_enable = mv88e6185_g1_ppu_enable,
3196 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3197 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3198};
3199
3200static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 3201 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3202 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 3203 .phy_read = mv88e6165_phy_read,
3204 .phy_write = mv88e6165_phy_write,
08ef7f10 3205 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3206 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3207 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3208 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3209 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3210 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3211 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3212 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3213 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3214 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3215 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3216 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3217 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3218 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3219 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3220 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3221 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3222 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3223 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3224};
3225
3226static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 3227 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3228 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 3229 .phy_read = mv88e6165_phy_read,
3230 .phy_write = mv88e6165_phy_write,
08ef7f10 3231 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3232 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3233 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3234 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3235 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3236 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3237 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3238 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3239 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3240 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3241 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3242 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3243};
3244
3245static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 3246 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3247 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3248 .phy_read = mv88e6xxx_g2_smi_phy_read,
3249 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3250 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3251 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3252 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3253 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3254 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3255 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3256 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3257 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3258 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3259 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3260 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3261 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3262 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3263 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3264 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3265 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3266 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3267 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3268 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3269 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3270};
3271
3272static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 3273 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3274 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3275 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3276 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3277 .phy_read = mv88e6xxx_g2_smi_phy_read,
3278 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3279 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3280 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3281 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3282 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3283 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3284 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3285 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3286 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3287 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3288 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3289 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3290 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3291 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3292 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3293 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3294 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3295 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3296 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3297 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3298 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3299};
3300
3301static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 3302 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3303 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3304 .phy_read = mv88e6xxx_g2_smi_phy_read,
3305 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3306 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3307 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3308 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3309 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3310 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3311 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3312 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3313 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3314 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3315 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3316 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3317 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3318 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3319 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3320 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3321 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3322 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3323 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3324 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3325 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3326};
3327
3328static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 3329 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3330 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3331 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3332 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3333 .phy_read = mv88e6xxx_g2_smi_phy_read,
3334 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3335 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3336 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3337 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3338 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3339 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3340 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3341 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3342 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3343 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3344 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3345 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3346 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3347 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3348 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3349 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3350 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3351 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3352 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3353 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3354 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3355};
3356
3357static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 3358 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3359 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3360 .phy_read = mv88e6xxx_phy_ppu_read,
3361 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3362 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3363 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3364 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 3365 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
a23b2961 3366 .port_set_egress_unknowns = mv88e6095_port_set_egress_unknowns,
ef70b111 3367 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
a23b2961 3368 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 3369 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3370 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3371 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3372 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3373 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3374 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3375 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3376 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3377 .ppu_enable = mv88e6185_g1_ppu_enable,
3378 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3379 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3380};
3381
1a3b39ec 3382static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 3383 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3384 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3385 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3386 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3387 .phy_read = mv88e6xxx_g2_smi_phy_read,
3388 .phy_write = mv88e6xxx_g2_smi_phy_write,
3389 .port_set_link = mv88e6xxx_port_set_link,
3390 .port_set_duplex = mv88e6xxx_port_set_duplex,
3391 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3392 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3393 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3394 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3395 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3396 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3397 .port_pause_config = mv88e6390_port_pause_config,
79523473 3398 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3399 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3400 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3401 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3402 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3403 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3404 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3405 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3406 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3407 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3408};
3409
3410static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 3411 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3412 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3413 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3414 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3415 .phy_read = mv88e6xxx_g2_smi_phy_read,
3416 .phy_write = mv88e6xxx_g2_smi_phy_write,
3417 .port_set_link = mv88e6xxx_port_set_link,
3418 .port_set_duplex = mv88e6xxx_port_set_duplex,
3419 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3420 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3421 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3422 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3423 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3424 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3425 .port_pause_config = mv88e6390_port_pause_config,
79523473 3426 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3427 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3428 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3429 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3430 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3431 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3432 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3433 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3434 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3435 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3436};
3437
3438static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 3439 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3440 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3441 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3442 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3443 .phy_read = mv88e6xxx_g2_smi_phy_read,
3444 .phy_write = mv88e6xxx_g2_smi_phy_write,
3445 .port_set_link = mv88e6xxx_port_set_link,
3446 .port_set_duplex = mv88e6xxx_port_set_duplex,
3447 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3448 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3449 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3450 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3451 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3452 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3453 .port_pause_config = mv88e6390_port_pause_config,
79523473 3454 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3455 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3456 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3457 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3458 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3459 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3460 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3461 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3462 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3463 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3464};
3465
b3469dd8 3466static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 3467 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3468 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3469 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3470 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3471 .phy_read = mv88e6xxx_g2_smi_phy_read,
3472 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3473 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3474 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3475 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3476 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3477 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3478 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3479 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3480 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3481 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3482 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3483 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3484 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3485 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3486 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3487 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3488 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3489 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3490 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3491 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3492 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3493};
3494
1a3b39ec 3495static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 3496 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3497 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3498 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3499 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3500 .phy_read = mv88e6xxx_g2_smi_phy_read,
3501 .phy_write = mv88e6xxx_g2_smi_phy_write,
3502 .port_set_link = mv88e6xxx_port_set_link,
3503 .port_set_duplex = mv88e6xxx_port_set_duplex,
3504 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3505 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3506 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3507 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3508 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3509 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3510 .port_pause_config = mv88e6390_port_pause_config,
f39908d3 3511 .port_set_cmode = mv88e6390x_port_set_cmode,
79523473 3512 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3513 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3514 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3515 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3516 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3517 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3518 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3519 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3520 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3521 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3522};
3523
b3469dd8 3524static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 3525 /* MV88E6XXX_FAMILY_6320 */
ee4dc2e7
VD		 3526 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3527 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3528 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3529 .phy_read = mv88e6xxx_g2_smi_phy_read,
3530 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3531 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3532 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3533 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3534 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3535 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3536 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3537 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3538 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3539 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3540 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3541 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3542 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3543 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3544 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3545 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3546 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3547 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3548 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3549};
3550
3551static const struct mv88e6xxx_ops mv88e6321_ops = {
4b325d8c 3552 /* MV88E6XXX_FAMILY_6321 */
ee4dc2e7
VD		 3553 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3554 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3555 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3556 .phy_read = mv88e6xxx_g2_smi_phy_read,
3557 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3558 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3559 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3560 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3561 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3562 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3563 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3564 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3565 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3566 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3567 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3568 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3569 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3570 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3571 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3572 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3573 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
17e708ba 3574 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3575};
3576
3577static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 3578 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3579 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3580 .phy_read = mv88e6xxx_g2_smi_phy_read,
3581 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3582 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3583 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3584 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3585 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3586 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3587 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3588 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3589 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3590 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3591 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3592 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3593 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3594 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3595 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3596 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3597 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3598 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3599 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3600 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3601 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3602};
3603
3604static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 3605 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3606 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3607 .phy_read = mv88e6xxx_g2_smi_phy_read,
3608 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3609 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3610 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3611 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3612 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3613 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3614 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3615 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3616 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3617 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3618 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3619 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3620 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3621 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3622 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3623 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3624 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3625 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3626 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3627 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3628 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3629};
3630
3631static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 3632 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3633 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3634 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3635 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3636 .phy_read = mv88e6xxx_g2_smi_phy_read,
3637 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3638 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3639 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3640 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3641 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3642 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3643 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3644 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3645 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3646 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3647 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3648 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3649 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3650 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3651 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3652 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3653 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3654 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3655 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3656 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3657 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3658};
3659
1558727a
GC		 3660static const struct mv88e6xxx_ops mv88e6141_ops = {
3661 /* MV88E6XXX_FAMILY_6341 */
3662 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3663 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3664 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3665 .phy_read = mv88e6xxx_g2_smi_phy_read,
3666 .phy_write = mv88e6xxx_g2_smi_phy_write,
3667 .port_set_link = mv88e6xxx_port_set_link,
3668 .port_set_duplex = mv88e6xxx_port_set_duplex,
3669 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3670 .port_set_speed = mv88e6390_port_set_speed,
3671 .port_tag_remap = mv88e6095_port_tag_remap,
3672 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3673 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3674 .port_set_ether_type = mv88e6351_port_set_ether_type,
3675 .port_jumbo_config = mv88e6165_port_jumbo_config,
3676 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3677 .port_pause_config = mv88e6097_port_pause_config,
3678 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3679 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3680 .stats_get_strings = mv88e6320_stats_get_strings,
3681 .stats_get_stats = mv88e6390_stats_get_stats,
3682 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3683 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3684 .watchdog_ops = &mv88e6390_watchdog_ops,
1558727a
GC		 3685 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3686 .reset = mv88e6352_g1_reset,
3687};
3688
a75961d0
GC		 3689static const struct mv88e6xxx_ops mv88e6341_ops = {
3690 /* MV88E6XXX_FAMILY_6341 */
3691 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3692 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3693 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3694 .phy_read = mv88e6xxx_g2_smi_phy_read,
3695 .phy_write = mv88e6xxx_g2_smi_phy_write,
3696 .port_set_link = mv88e6xxx_port_set_link,
3697 .port_set_duplex = mv88e6xxx_port_set_duplex,
3698 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3699 .port_set_speed = mv88e6390_port_set_speed,
3700 .port_tag_remap = mv88e6095_port_tag_remap,
3701 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3702 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3703 .port_set_ether_type = mv88e6351_port_set_ether_type,
3704 .port_jumbo_config = mv88e6165_port_jumbo_config,
3705 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3706 .port_pause_config = mv88e6097_port_pause_config,
3707 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3708 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3709 .stats_get_strings = mv88e6320_stats_get_strings,
3710 .stats_get_stats = mv88e6390_stats_get_stats,
3711 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3712 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3713 .watchdog_ops = &mv88e6390_watchdog_ops,
a75961d0
GC		 3714 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3715 .reset = mv88e6352_g1_reset,
3716};
3717
1a3b39ec 3718static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 3719 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3720 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3721 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3722 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3723 .phy_read = mv88e6xxx_g2_smi_phy_read,
3724 .phy_write = mv88e6xxx_g2_smi_phy_write,
3725 .port_set_link = mv88e6xxx_port_set_link,
3726 .port_set_duplex = mv88e6xxx_port_set_duplex,
3727 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3728 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3729 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3730 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3731 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3732 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3733 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3734 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3735 .port_pause_config = mv88e6390_port_pause_config,
f39908d3 3736 .port_set_cmode = mv88e6390x_port_set_cmode,
79523473 3737 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3738 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3739 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3740 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3741 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3742 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3743 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3744 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3745 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3746 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3747};
3748
3749static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 3750 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3751 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3752 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3753 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3754 .phy_read = mv88e6xxx_g2_smi_phy_read,
3755 .phy_write = mv88e6xxx_g2_smi_phy_write,
3756 .port_set_link = mv88e6xxx_port_set_link,
3757 .port_set_duplex = mv88e6xxx_port_set_duplex,
3758 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3759 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3760 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3761 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3762 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3763 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3764 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3765 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3766 .port_pause_config = mv88e6390_port_pause_config,
79523473 3767 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3768 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3769 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3770 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3771 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3772 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3773 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3774 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3775 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3776 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3777};
3778
3779static const struct mv88e6xxx_ops mv88e6391_ops = {
4b325d8c 3780 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3781 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3782 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3783 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3784 .phy_read = mv88e6xxx_g2_smi_phy_read,
3785 .phy_write = mv88e6xxx_g2_smi_phy_write,
3786 .port_set_link = mv88e6xxx_port_set_link,
3787 .port_set_duplex = mv88e6xxx_port_set_duplex,
3788 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3789 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3790 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3791 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3792 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3793 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3794 .port_pause_config = mv88e6390_port_pause_config,
79523473 3795 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3796 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3797 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3798 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3799 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3800 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3801 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3802 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3803 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3804 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3805};
3806
56995cbc
AL		 3807static int mv88e6xxx_verify_madatory_ops(struct mv88e6xxx_chip *chip,
3808 const struct mv88e6xxx_ops *ops)
3809{
3810 if (!ops->port_set_frame_mode) {
3811 dev_err(chip->dev, "Missing port_set_frame_mode");
3812 return -EINVAL;
3813 }
3814
3815 if (!ops->port_set_egress_unknowns) {
3816 dev_err(chip->dev, "Missing port_set_egress_mode");
3817 return -EINVAL;
3818 }
3819
3820 return 0;
3821}
3822
f81ec90f
VD		 3823static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3824 [MV88E6085] = {
3825 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3826 .family = MV88E6XXX_FAMILY_6097,
3827 .name = "Marvell 88E6085",
3828 .num_databases = 4096,
3829 .num_ports = 10,
9dddd478 3830 .port_base_addr = 0x10,
a935c052 3831 .global1_addr = 0x1b,
acddbd21 3832 .age_time_coeff = 15000,
dc30c35b 3833 .g1_irqs = 8,
443d5a1b 3834 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3835 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
b3469dd8 3836 .ops = &mv88e6085_ops,
f81ec90f
VD		 3837 },
3838
3839 [MV88E6095] = {
3840 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3841 .family = MV88E6XXX_FAMILY_6095,
3842 .name = "Marvell 88E6095/88E6095F",
3843 .num_databases = 256,
3844 .num_ports = 11,
9dddd478 3845 .port_base_addr = 0x10,
a935c052 3846 .global1_addr = 0x1b,
acddbd21 3847 .age_time_coeff = 15000,
dc30c35b 3848 .g1_irqs = 8,
443d5a1b 3849 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3850 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
b3469dd8 3851 .ops = &mv88e6095_ops,
f81ec90f
VD		 3852 },
3853
7d381a02
SE		 3854 [MV88E6097] = {
3855 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
3856 .family = MV88E6XXX_FAMILY_6097,
3857 .name = "Marvell 88E6097/88E6097F",
3858 .num_databases = 4096,
3859 .num_ports = 11,
3860 .port_base_addr = 0x10,
3861 .global1_addr = 0x1b,
3862 .age_time_coeff = 15000,
c534178b 3863 .g1_irqs = 8,
2bfcfcd3 3864 .tag_protocol = DSA_TAG_PROTO_EDSA,
7d381a02
SE		 3865 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3866 .ops = &mv88e6097_ops,
3867 },
3868
f81ec90f
VD		 3869 [MV88E6123] = {
3870 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3871 .family = MV88E6XXX_FAMILY_6165,
3872 .name = "Marvell 88E6123",
3873 .num_databases = 4096,
3874 .num_ports = 3,
9dddd478 3875 .port_base_addr = 0x10,
a935c052 3876 .global1_addr = 0x1b,
acddbd21 3877 .age_time_coeff = 15000,
dc30c35b 3878 .g1_irqs = 9,
443d5a1b 3879 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3880 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3881 .ops = &mv88e6123_ops,
f81ec90f
VD		 3882 },
3883
3884 [MV88E6131] = {
3885 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3886 .family = MV88E6XXX_FAMILY_6185,
3887 .name = "Marvell 88E6131",
3888 .num_databases = 256,
3889 .num_ports = 8,
9dddd478 3890 .port_base_addr = 0x10,
a935c052 3891 .global1_addr = 0x1b,
acddbd21 3892 .age_time_coeff = 15000,
dc30c35b 3893 .g1_irqs = 9,
443d5a1b 3894 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3895 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3896 .ops = &mv88e6131_ops,
f81ec90f
VD		 3897 },
3898
3899 [MV88E6161] = {
3900 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3901 .family = MV88E6XXX_FAMILY_6165,
3902 .name = "Marvell 88E6161",
3903 .num_databases = 4096,
3904 .num_ports = 6,
9dddd478 3905 .port_base_addr = 0x10,
a935c052 3906 .global1_addr = 0x1b,
acddbd21 3907 .age_time_coeff = 15000,
dc30c35b 3908 .g1_irqs = 9,
443d5a1b 3909 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3910 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3911 .ops = &mv88e6161_ops,
f81ec90f
VD		 3912 },
3913
3914 [MV88E6165] = {
3915 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3916 .family = MV88E6XXX_FAMILY_6165,
3917 .name = "Marvell 88E6165",
3918 .num_databases = 4096,
3919 .num_ports = 6,
9dddd478 3920 .port_base_addr = 0x10,
a935c052 3921 .global1_addr = 0x1b,
acddbd21 3922 .age_time_coeff = 15000,
dc30c35b 3923 .g1_irqs = 9,
443d5a1b 3924 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3925 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3926 .ops = &mv88e6165_ops,
f81ec90f
VD		 3927 },
3928
3929 [MV88E6171] = {
3930 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3931 .family = MV88E6XXX_FAMILY_6351,
3932 .name = "Marvell 88E6171",
3933 .num_databases = 4096,
3934 .num_ports = 7,
9dddd478 3935 .port_base_addr = 0x10,
a935c052 3936 .global1_addr = 0x1b,
acddbd21 3937 .age_time_coeff = 15000,
dc30c35b 3938 .g1_irqs = 9,
443d5a1b 3939 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3940 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3941 .ops = &mv88e6171_ops,
f81ec90f
VD		 3942 },
3943
3944 [MV88E6172] = {
3945 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3946 .family = MV88E6XXX_FAMILY_6352,
3947 .name = "Marvell 88E6172",
3948 .num_databases = 4096,
3949 .num_ports = 7,
9dddd478 3950 .port_base_addr = 0x10,
a935c052 3951 .global1_addr = 0x1b,
acddbd21 3952 .age_time_coeff = 15000,
dc30c35b 3953 .g1_irqs = 9,
443d5a1b 3954 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3955 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3956 .ops = &mv88e6172_ops,
f81ec90f
VD		 3957 },
3958
3959 [MV88E6175] = {
3960 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3961 .family = MV88E6XXX_FAMILY_6351,
3962 .name = "Marvell 88E6175",
3963 .num_databases = 4096,
3964 .num_ports = 7,
9dddd478 3965 .port_base_addr = 0x10,
a935c052 3966 .global1_addr = 0x1b,
acddbd21 3967 .age_time_coeff = 15000,
dc30c35b 3968 .g1_irqs = 9,
443d5a1b 3969 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3970 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3971 .ops = &mv88e6175_ops,
f81ec90f
VD		 3972 },
3973
3974 [MV88E6176] = {
3975 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3976 .family = MV88E6XXX_FAMILY_6352,
3977 .name = "Marvell 88E6176",
3978 .num_databases = 4096,
3979 .num_ports = 7,
9dddd478 3980 .port_base_addr = 0x10,
a935c052 3981 .global1_addr = 0x1b,
acddbd21 3982 .age_time_coeff = 15000,
dc30c35b 3983 .g1_irqs = 9,
443d5a1b 3984 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3985 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3986 .ops = &mv88e6176_ops,
f81ec90f
VD		 3987 },
3988
3989 [MV88E6185] = {
3990 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3991 .family = MV88E6XXX_FAMILY_6185,
3992 .name = "Marvell 88E6185",
3993 .num_databases = 256,
3994 .num_ports = 10,
9dddd478 3995 .port_base_addr = 0x10,
a935c052 3996 .global1_addr = 0x1b,
acddbd21 3997 .age_time_coeff = 15000,
dc30c35b 3998 .g1_irqs = 8,
443d5a1b 3999 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4000 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 4001 .ops = &mv88e6185_ops,
f81ec90f
VD		 4002 },
4003
1a3b39ec
AL		 4004 [MV88E6190] = {
4005 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
4006 .family = MV88E6XXX_FAMILY_6390,
4007 .name = "Marvell 88E6190",
4008 .num_databases = 4096,
4009 .num_ports = 11, /* 10 + Z80 */
4010 .port_base_addr = 0x0,
4011 .global1_addr = 0x1b,
443d5a1b 4012 .tag_protocol = DSA_TAG_PROTO_DSA,
b91e055c 4013 .age_time_coeff = 3750,
1a3b39ec
AL		 4014 .g1_irqs = 9,
4015 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4016 .ops = &mv88e6190_ops,
4017 },
4018
4019 [MV88E6190X] = {
4020 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
4021 .family = MV88E6XXX_FAMILY_6390,
4022 .name = "Marvell 88E6190X",
4023 .num_databases = 4096,
4024 .num_ports = 11, /* 10 + Z80 */
4025 .port_base_addr = 0x0,
4026 .global1_addr = 0x1b,
b91e055c 4027 .age_time_coeff = 3750,
1a3b39ec 4028 .g1_irqs = 9,
443d5a1b 4029 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4030 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4031 .ops = &mv88e6190x_ops,
4032 },
4033
4034 [MV88E6191] = {
4035 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
4036 .family = MV88E6XXX_FAMILY_6390,
4037 .name = "Marvell 88E6191",
4038 .num_databases = 4096,
4039 .num_ports = 11, /* 10 + Z80 */
4040 .port_base_addr = 0x0,
4041 .global1_addr = 0x1b,
b91e055c 4042 .age_time_coeff = 3750,
443d5a1b
AL		 4043 .g1_irqs = 9,
4044 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4045 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4046 .ops = &mv88e6391_ops,
4047 },
4048
f81ec90f
VD		 4049 [MV88E6240] = {
4050 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
4051 .family = MV88E6XXX_FAMILY_6352,
4052 .name = "Marvell 88E6240",
4053 .num_databases = 4096,
4054 .num_ports = 7,
9dddd478 4055 .port_base_addr = 0x10,
a935c052 4056 .global1_addr = 0x1b,
acddbd21 4057 .age_time_coeff = 15000,
dc30c35b 4058 .g1_irqs = 9,
443d5a1b 4059 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4060 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 4061 .ops = &mv88e6240_ops,
f81ec90f
VD		 4062 },
4063
1a3b39ec
AL		 4064 [MV88E6290] = {
4065 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
4066 .family = MV88E6XXX_FAMILY_6390,
4067 .name = "Marvell 88E6290",
4068 .num_databases = 4096,
4069 .num_ports = 11, /* 10 + Z80 */
4070 .port_base_addr = 0x0,
4071 .global1_addr = 0x1b,
b91e055c 4072 .age_time_coeff = 3750,
1a3b39ec 4073 .g1_irqs = 9,
443d5a1b 4074 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4075 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4076 .ops = &mv88e6290_ops,
4077 },
4078
f81ec90f
VD		 4079 [MV88E6320] = {
4080 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
4081 .family = MV88E6XXX_FAMILY_6320,
4082 .name = "Marvell 88E6320",
4083 .num_databases = 4096,
4084 .num_ports = 7,
9dddd478 4085 .port_base_addr = 0x10,
a935c052 4086 .global1_addr = 0x1b,
acddbd21 4087 .age_time_coeff = 15000,
dc30c35b 4088 .g1_irqs = 8,
443d5a1b 4089 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4090 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 4091 .ops = &mv88e6320_ops,
f81ec90f
VD		 4092 },
4093
4094 [MV88E6321] = {
4095 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
4096 .family = MV88E6XXX_FAMILY_6320,
4097 .name = "Marvell 88E6321",
4098 .num_databases = 4096,
4099 .num_ports = 7,
9dddd478 4100 .port_base_addr = 0x10,
a935c052 4101 .global1_addr = 0x1b,
acddbd21 4102 .age_time_coeff = 15000,
dc30c35b 4103 .g1_irqs = 8,
443d5a1b 4104 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4105 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 4106 .ops = &mv88e6321_ops,
f81ec90f
VD		 4107 },
4108
1558727a
GC		 4109 [MV88E6141] = {
4110 .prod_num = PORT_SWITCH_ID_PROD_NUM_6141,
4111 .family = MV88E6XXX_FAMILY_6341,
4112 .name = "Marvell 88E6341",
4113 .num_databases = 4096,
4114 .num_ports = 6,
4115 .port_base_addr = 0x10,
4116 .global1_addr = 0x1b,
4117 .age_time_coeff = 3750,
4118 .tag_protocol = DSA_TAG_PROTO_EDSA,
4119 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
4120 .ops = &mv88e6141_ops,
4121 },
4122
a75961d0
GC		 4123 [MV88E6341] = {
4124 .prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
4125 .family = MV88E6XXX_FAMILY_6341,
4126 .name = "Marvell 88E6341",
4127 .num_databases = 4096,
4128 .num_ports = 6,
4129 .port_base_addr = 0x10,
4130 .global1_addr = 0x1b,
4131 .age_time_coeff = 3750,
4132 .tag_protocol = DSA_TAG_PROTO_EDSA,
4133 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
4134 .ops = &mv88e6341_ops,
4135 },
4136
f81ec90f
VD		 4137 [MV88E6350] = {
4138 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
4139 .family = MV88E6XXX_FAMILY_6351,
4140 .name = "Marvell 88E6350",
4141 .num_databases = 4096,
4142 .num_ports = 7,
9dddd478 4143 .port_base_addr = 0x10,
a935c052 4144 .global1_addr = 0x1b,
acddbd21 4145 .age_time_coeff = 15000,
dc30c35b 4146 .g1_irqs = 9,
443d5a1b 4147 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4148 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 4149 .ops = &mv88e6350_ops,
f81ec90f
VD		 4150 },
4151
4152 [MV88E6351] = {
4153 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
4154 .family = MV88E6XXX_FAMILY_6351,
4155 .name = "Marvell 88E6351",
4156 .num_databases = 4096,
4157 .num_ports = 7,
9dddd478 4158 .port_base_addr = 0x10,
a935c052 4159 .global1_addr = 0x1b,
acddbd21 4160 .age_time_coeff = 15000,
dc30c35b 4161 .g1_irqs = 9,
443d5a1b 4162 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4163 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 4164 .ops = &mv88e6351_ops,
f81ec90f
VD		 4165 },
4166
4167 [MV88E6352] = {
4168 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
4169 .family = MV88E6XXX_FAMILY_6352,
4170 .name = "Marvell 88E6352",
4171 .num_databases = 4096,
4172 .num_ports = 7,
9dddd478 4173 .port_base_addr = 0x10,
a935c052 4174 .global1_addr = 0x1b,
acddbd21 4175 .age_time_coeff = 15000,
dc30c35b 4176 .g1_irqs = 9,
443d5a1b 4177 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4178 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 4179 .ops = &mv88e6352_ops,
f81ec90f 4180 },
1a3b39ec
AL		 4181 [MV88E6390] = {
4182 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
4183 .family = MV88E6XXX_FAMILY_6390,
4184 .name = "Marvell 88E6390",
4185 .num_databases = 4096,
4186 .num_ports = 11, /* 10 + Z80 */
4187 .port_base_addr = 0x0,
4188 .global1_addr = 0x1b,
b91e055c 4189 .age_time_coeff = 3750,
1a3b39ec 4190 .g1_irqs = 9,
443d5a1b 4191 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4192 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4193 .ops = &mv88e6390_ops,
4194 },
4195 [MV88E6390X] = {
4196 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
4197 .family = MV88E6XXX_FAMILY_6390,
4198 .name = "Marvell 88E6390X",
4199 .num_databases = 4096,
4200 .num_ports = 11, /* 10 + Z80 */
4201 .port_base_addr = 0x0,
4202 .global1_addr = 0x1b,
b91e055c 4203 .age_time_coeff = 3750,
1a3b39ec 4204 .g1_irqs = 9,
443d5a1b 4205 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4206 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4207 .ops = &mv88e6390x_ops,
4208 },
f81ec90f
VD		 4209};
4210
5f7c0367 4211static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 4212{
a439c061 4213 int i;
b9b37713 4214
5f7c0367
VD		 4215 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4216 if (mv88e6xxx_table[i].prod_num == prod_num)
4217 return &mv88e6xxx_table[i];
b9b37713 4218
b9b37713
VD		 4219 return NULL;
4220}
4221
fad09c73 4222static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 4223{
4224 const struct mv88e6xxx_info *info;
8f6345b2
VD		 4225 unsigned int prod_num, rev;
4226 u16 id;
4227 int err;
bc46a3d5 4228
8f6345b2
VD		 4229 mutex_lock(&chip->reg_lock);
4230 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
4231 mutex_unlock(&chip->reg_lock);
4232 if (err)
4233 return err;
bc46a3d5
VD		 4234
4235 prod_num = (id & 0xfff0) >> 4;
4236 rev = id & 0x000f;
4237
4238 info = mv88e6xxx_lookup_info(prod_num);
4239 if (!info)
4240 return -ENODEV;
4241
caac8545 4242 /* Update the compatible info with the probed one */
fad09c73 4243 chip->info = info;
bc46a3d5 4244
ca070c10
VD		 4245 err = mv88e6xxx_g2_require(chip);
4246 if (err)
4247 return err;
4248
fad09c73
VD		 4249 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4250 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 4251
4252 return 0;
4253}
4254
fad09c73 4255static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 4256{
fad09c73 4257 struct mv88e6xxx_chip *chip;
469d729f 4258
fad09c73
VD		 4259 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4260 if (!chip)
469d729f
VD		 4261 return NULL;
4262
fad09c73 4263 chip->dev = dev;
469d729f 4264
fad09c73 4265 mutex_init(&chip->reg_lock);
a3c53be5 4266 INIT_LIST_HEAD(&chip->mdios);
469d729f 4267
fad09c73 4268 return chip;
469d729f
VD		 4269}
4270
e57e5e77
VD		 4271static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
4272{
a199d8b6 4273 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
e57e5e77 4274 mv88e6xxx_ppu_state_init(chip);
e57e5e77
VD		 4275}
4276
930188ce
AL		 4277static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
4278{
a199d8b6 4279 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
930188ce 4280 mv88e6xxx_ppu_state_destroy(chip);
930188ce
AL		 4281}
4282
fad09c73 4283static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 4284 struct mii_bus *bus, int sw_addr)
4285{
914b32f6 4286 if (sw_addr == 0)
fad09c73 4287 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 4288 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 4289 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 4290 else
4291 return -EINVAL;
4292
fad09c73
VD		 4293 chip->bus = bus;
4294 chip->sw_addr = sw_addr;
4a70c4ab
VD		 4295
4296 return 0;
4297}
4298
7b314362
AL		 4299static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
4300{
04bed143 4301 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be 4302
443d5a1b 4303 return chip->info->tag_protocol;
7b314362
AL		 4304}
4305
fcdce7d0
AL		 4306static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4307 struct device *host_dev, int sw_addr,
4308 void **priv)
a77d43f1 4309{
fad09c73 4310 struct mv88e6xxx_chip *chip;
a439c061 4311 struct mii_bus *bus;
b516d453 4312 int err;
a77d43f1 4313
a439c061 4314 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 4315 if (!bus)
4316 return NULL;
4317
fad09c73
VD		 4318 chip = mv88e6xxx_alloc_chip(dsa_dev);
4319 if (!chip)
469d729f
VD		 4320 return NULL;
4321
caac8545 4322 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 4323 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 4324
fad09c73 4325 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 4326 if (err)
4327 goto free;
4328
fad09c73 4329 err = mv88e6xxx_detect(chip);
bc46a3d5 4330 if (err)
469d729f 4331 goto free;
a439c061 4332
dc30c35b
AL		 4333 mutex_lock(&chip->reg_lock);
4334 err = mv88e6xxx_switch_reset(chip);
4335 mutex_unlock(&chip->reg_lock);
4336 if (err)
4337 goto free;
4338
e57e5e77
VD		 4339 mv88e6xxx_phy_init(chip);
4340
a3c53be5 4341 err = mv88e6xxx_mdios_register(chip, NULL);
b516d453 4342 if (err)
469d729f 4343 goto free;
b516d453 4344
fad09c73 4345 *priv = chip;
a439c061 4346
fad09c73 4347 return chip->info->name;
469d729f 4348free:
fad09c73 4349 devm_kfree(dsa_dev, chip);
469d729f
VD		 4350
4351 return NULL;
a77d43f1
AL		 4352}
4353
7df8fbdd
VD		 4354static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4355 const struct switchdev_obj_port_mdb *mdb,
4356 struct switchdev_trans *trans)
4357{
4358 /* We don't need any dynamic resource from the kernel (yet),
4359 * so skip the prepare phase.
4360 */
4361
4362 return 0;
4363}
4364
4365static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4366 const struct switchdev_obj_port_mdb *mdb,
4367 struct switchdev_trans *trans)
4368{
04bed143 4369 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4370
4371 mutex_lock(&chip->reg_lock);
4372 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4373 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4374 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4375 mutex_unlock(&chip->reg_lock);
4376}
4377
4378static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4379 const struct switchdev_obj_port_mdb *mdb)
4380{
04bed143 4381 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4382 int err;
4383
4384 mutex_lock(&chip->reg_lock);
4385 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4386 GLOBAL_ATU_DATA_STATE_UNUSED);
4387 mutex_unlock(&chip->reg_lock);
4388
4389 return err;
4390}
4391
4392static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4393 struct switchdev_obj_port_mdb *mdb,
4394 int (*cb)(struct switchdev_obj *obj))
4395{
04bed143 4396 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4397 int err;
4398
4399 mutex_lock(&chip->reg_lock);
4400 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4401 mutex_unlock(&chip->reg_lock);
4402
4403 return err;
4404}
4405
a82f67af 4406static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 4407 .probe = mv88e6xxx_drv_probe,
7b314362 4408 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 4409 .setup = mv88e6xxx_setup,
4410 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 4411 .adjust_link = mv88e6xxx_adjust_link,
4412 .get_strings = mv88e6xxx_get_strings,
4413 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4414 .get_sset_count = mv88e6xxx_get_sset_count,
4415 .set_eee = mv88e6xxx_set_eee,
4416 .get_eee = mv88e6xxx_get_eee,
f8cd8753 4417 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 4418 .get_eeprom = mv88e6xxx_get_eeprom,
4419 .set_eeprom = mv88e6xxx_set_eeprom,
4420 .get_regs_len = mv88e6xxx_get_regs_len,
4421 .get_regs = mv88e6xxx_get_regs,
2cfcd964 4422 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 4423 .port_bridge_join = mv88e6xxx_port_bridge_join,
4424 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4425 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 4426 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 4427 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4428 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4429 .port_vlan_add = mv88e6xxx_port_vlan_add,
4430 .port_vlan_del = mv88e6xxx_port_vlan_del,
4431 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4432 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4433 .port_fdb_add = mv88e6xxx_port_fdb_add,
4434 .port_fdb_del = mv88e6xxx_port_fdb_del,
4435 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 4436 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4437 .port_mdb_add = mv88e6xxx_port_mdb_add,
4438 .port_mdb_del = mv88e6xxx_port_mdb_del,
4439 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
f81ec90f
VD		 4440};
4441
ab3d408d
FF		 4442static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4443 .ops = &mv88e6xxx_switch_ops,
4444};
4445
55ed0ce0 4446static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4447{
fad09c73 4448 struct device *dev = chip->dev;
b7e66a5f
VD		 4449 struct dsa_switch *ds;
4450
a0c02161 4451 ds = dsa_switch_alloc(dev, DSA_MAX_PORTS);
b7e66a5f
VD		 4452 if (!ds)
4453 return -ENOMEM;
4454
fad09c73 4455 ds->priv = chip;
9d490b4e 4456 ds->ops = &mv88e6xxx_switch_ops;
b7e66a5f
VD		 4457
4458 dev_set_drvdata(dev, ds);
4459
55ed0ce0 4460 return dsa_register_switch(ds, dev);
b7e66a5f
VD		 4461}
4462
fad09c73 4463static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4464{
fad09c73 4465 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 4466}
4467
57d32310 4468static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 4469{
14c7b3c3 4470 struct device *dev = &mdiodev->dev;
f8cd8753 4471 struct device_node *np = dev->of_node;
caac8545 4472 const struct mv88e6xxx_info *compat_info;
fad09c73 4473 struct mv88e6xxx_chip *chip;
f8cd8753 4474 u32 eeprom_len;
52638f71 4475 int err;
14c7b3c3 4476
caac8545
VD		 4477 compat_info = of_device_get_match_data(dev);
4478 if (!compat_info)
4479 return -EINVAL;
4480
fad09c73
VD		 4481 chip = mv88e6xxx_alloc_chip(dev);
4482 if (!chip)
14c7b3c3
AL		 4483 return -ENOMEM;
4484
fad09c73 4485 chip->info = compat_info;
caac8545 4486
56995cbc
AL		 4487 err = mv88e6xxx_verify_madatory_ops(chip, chip->info->ops);
4488 if (err)
4489 return err;
4490
fad09c73 4491 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4492 if (err)
4493 return err;
14c7b3c3 4494
b4308f04
AL		 4495 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4496 if (IS_ERR(chip->reset))
4497 return PTR_ERR(chip->reset);
4498
fad09c73 4499 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4500 if (err)
4501 return err;
14c7b3c3 4502
e57e5e77
VD		 4503 mv88e6xxx_phy_init(chip);
4504
ee4dc2e7 4505 if (chip->info->ops->get_eeprom &&
f8cd8753 4506 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4507 chip->eeprom_len = eeprom_len;
f8cd8753 4508
dc30c35b
AL		 4509 mutex_lock(&chip->reg_lock);
4510 err = mv88e6xxx_switch_reset(chip);
4511 mutex_unlock(&chip->reg_lock);
4512 if (err)
4513 goto out;
4514
4515 chip->irq = of_irq_get(np, 0);
4516 if (chip->irq == -EPROBE_DEFER) {
4517 err = chip->irq;
4518 goto out;
4519 }
4520
4521 if (chip->irq > 0) {
4522 /* Has to be performed before the MDIO bus is created,
4523 * because the PHYs will link there interrupts to these
4524 * interrupt controllers
4525 */
4526 mutex_lock(&chip->reg_lock);
4527 err = mv88e6xxx_g1_irq_setup(chip);
4528 mutex_unlock(&chip->reg_lock);
4529
4530 if (err)
4531 goto out;
4532
4533 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4534 err = mv88e6xxx_g2_irq_setup(chip);
4535 if (err)
4536 goto out_g1_irq;
4537 }
4538 }
4539
a3c53be5 4540 err = mv88e6xxx_mdios_register(chip, np);
b516d453 4541 if (err)
dc30c35b 4542 goto out_g2_irq;
b516d453 4543
55ed0ce0 4544 err = mv88e6xxx_register_switch(chip);
dc30c35b
AL		 4545 if (err)
4546 goto out_mdio;
83c0afae 4547
98e67308 4548 return 0;
dc30c35b
AL		 4549
4550out_mdio:
a3c53be5 4551 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4552out_g2_irq:
46712644 4553 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
dc30c35b
AL		 4554 mv88e6xxx_g2_irq_free(chip);
4555out_g1_irq:
61f7c3f8
AL		 4556 if (chip->irq > 0) {
4557 mutex_lock(&chip->reg_lock);
46712644 4558 mv88e6xxx_g1_irq_free(chip);
61f7c3f8
AL		 4559 mutex_unlock(&chip->reg_lock);
4560 }
dc30c35b
AL		 4561out:
4562 return err;
98e67308 4563}
14c7b3c3
AL		 4564
4565static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4566{
4567 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 4568 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 4569
930188ce 4570 mv88e6xxx_phy_destroy(chip);
fad09c73 4571 mv88e6xxx_unregister_switch(chip);
a3c53be5 4572 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4573
46712644
AL		 4574 if (chip->irq > 0) {
4575 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4576 mv88e6xxx_g2_irq_free(chip);
4577 mv88e6xxx_g1_irq_free(chip);
4578 }
14c7b3c3
AL		 4579}
4580
4581static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4582 {
4583 .compatible = "marvell,mv88e6085",
4584 .data = &mv88e6xxx_table[MV88E6085],
4585 },
1a3b39ec
AL		 4586 {
4587 .compatible = "marvell,mv88e6190",
4588 .data = &mv88e6xxx_table[MV88E6190],
4589 },
14c7b3c3
AL		 4590 { /* sentinel */ },
4591};
4592
4593MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4594
4595static struct mdio_driver mv88e6xxx_driver = {
4596 .probe = mv88e6xxx_probe,
4597 .remove = mv88e6xxx_remove,
4598 .mdiodrv.driver = {
4599 .name = "mv88e6085",
4600 .of_match_table = mv88e6xxx_of_match,
4601 },
4602};
4603
4604static int __init mv88e6xxx_init(void)
4605{
ab3d408d 4606 register_switch_driver(&mv88e6xxx_switch_drv);
14c7b3c3
AL		 4607 return mdio_driver_register(&mv88e6xxx_driver);
4608}
98e67308
BH		 4609module_init(mv88e6xxx_init);
4610
4611static void __exit mv88e6xxx_cleanup(void)
4612{
14c7b3c3 4613 mdio_driver_unregister(&mv88e6xxx_driver);
ab3d408d 4614 unregister_switch_driver(&mv88e6xxx_switch_drv);
98e67308
BH		 4615}
4616module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4617
4618MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4619MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4620MODULE_LICENSE("GPL");
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