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Commit | Line | Data |
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91da11f8 LB |
1 | /* |
2 | * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support | |
3 | * Copyright (c) 2008 Marvell Semiconductor | |
4 | * | |
b8fee957 VD |
5 | * Copyright (c) 2015 CMC Electronics, Inc. |
6 | * Added support for VLAN Table Unit operations | |
7 | * | |
91da11f8 LB |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
19b2f97e | 14 | #include <linux/delay.h> |
defb05b9 | 15 | #include <linux/etherdevice.h> |
dea87024 | 16 | #include <linux/ethtool.h> |
facd95b2 | 17 | #include <linux/if_bridge.h> |
19b2f97e | 18 | #include <linux/jiffies.h> |
91da11f8 | 19 | #include <linux/list.h> |
2bbba277 | 20 | #include <linux/module.h> |
91da11f8 LB |
21 | #include <linux/netdevice.h> |
22 | #include <linux/phy.h> | |
c8f0b869 | 23 | #include <net/dsa.h> |
1f36faf2 | 24 | #include <net/switchdev.h> |
91da11f8 LB |
25 | #include "mv88e6xxx.h" |
26 | ||
3996a4ff VD |
27 | static void assert_smi_lock(struct dsa_switch *ds) |
28 | { | |
29 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
30 | ||
31 | if (unlikely(!mutex_is_locked(&ps->smi_mutex))) { | |
32 | dev_err(ds->master_dev, "SMI lock not held!\n"); | |
33 | dump_stack(); | |
34 | } | |
35 | } | |
36 | ||
3675c8d7 | 37 | /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will |
91da11f8 LB |
38 | * use all 32 SMI bus addresses on its SMI bus, and all switch registers |
39 | * will be directly accessible on some {device address,register address} | |
40 | * pair. If the ADDR[4:0] pins are not strapped to zero, the switch | |
41 | * will only respond to SMI transactions to that specific address, and | |
42 | * an indirect addressing mechanism needs to be used to access its | |
43 | * registers. | |
44 | */ | |
45 | static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr) | |
46 | { | |
47 | int ret; | |
48 | int i; | |
49 | ||
50 | for (i = 0; i < 16; i++) { | |
6e899e6c | 51 | ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD); |
91da11f8 LB |
52 | if (ret < 0) |
53 | return ret; | |
54 | ||
cca8b133 | 55 | if ((ret & SMI_CMD_BUSY) == 0) |
91da11f8 LB |
56 | return 0; |
57 | } | |
58 | ||
59 | return -ETIMEDOUT; | |
60 | } | |
61 | ||
b9b37713 VD |
62 | static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, |
63 | int reg) | |
91da11f8 LB |
64 | { |
65 | int ret; | |
66 | ||
67 | if (sw_addr == 0) | |
6e899e6c | 68 | return mdiobus_read_nested(bus, addr, reg); |
91da11f8 | 69 | |
3675c8d7 | 70 | /* Wait for the bus to become free. */ |
91da11f8 LB |
71 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
72 | if (ret < 0) | |
73 | return ret; | |
74 | ||
3675c8d7 | 75 | /* Transmit the read command. */ |
6e899e6c NA |
76 | ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD, |
77 | SMI_CMD_OP_22_READ | (addr << 5) | reg); | |
91da11f8 LB |
78 | if (ret < 0) |
79 | return ret; | |
80 | ||
3675c8d7 | 81 | /* Wait for the read command to complete. */ |
91da11f8 LB |
82 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
83 | if (ret < 0) | |
84 | return ret; | |
85 | ||
3675c8d7 | 86 | /* Read the data. */ |
6e899e6c | 87 | ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA); |
91da11f8 LB |
88 | if (ret < 0) |
89 | return ret; | |
90 | ||
91 | return ret & 0xffff; | |
92 | } | |
93 | ||
8d6d09e7 | 94 | static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg) |
91da11f8 | 95 | { |
b184e497 | 96 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); |
91da11f8 LB |
97 | int ret; |
98 | ||
3996a4ff VD |
99 | assert_smi_lock(ds); |
100 | ||
b184e497 GR |
101 | if (bus == NULL) |
102 | return -EINVAL; | |
103 | ||
b184e497 | 104 | ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg); |
bb92ea5e VD |
105 | if (ret < 0) |
106 | return ret; | |
107 | ||
108 | dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", | |
109 | addr, reg, ret); | |
110 | ||
91da11f8 LB |
111 | return ret; |
112 | } | |
113 | ||
8d6d09e7 GR |
114 | int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg) |
115 | { | |
116 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
117 | int ret; | |
118 | ||
119 | mutex_lock(&ps->smi_mutex); | |
120 | ret = _mv88e6xxx_reg_read(ds, addr, reg); | |
121 | mutex_unlock(&ps->smi_mutex); | |
122 | ||
123 | return ret; | |
124 | } | |
125 | ||
b9b37713 VD |
126 | static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr, |
127 | int reg, u16 val) | |
91da11f8 LB |
128 | { |
129 | int ret; | |
130 | ||
131 | if (sw_addr == 0) | |
6e899e6c | 132 | return mdiobus_write_nested(bus, addr, reg, val); |
91da11f8 | 133 | |
3675c8d7 | 134 | /* Wait for the bus to become free. */ |
91da11f8 LB |
135 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
136 | if (ret < 0) | |
137 | return ret; | |
138 | ||
3675c8d7 | 139 | /* Transmit the data to write. */ |
6e899e6c | 140 | ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val); |
91da11f8 LB |
141 | if (ret < 0) |
142 | return ret; | |
143 | ||
3675c8d7 | 144 | /* Transmit the write command. */ |
6e899e6c NA |
145 | ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD, |
146 | SMI_CMD_OP_22_WRITE | (addr << 5) | reg); | |
91da11f8 LB |
147 | if (ret < 0) |
148 | return ret; | |
149 | ||
3675c8d7 | 150 | /* Wait for the write command to complete. */ |
91da11f8 LB |
151 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
152 | if (ret < 0) | |
153 | return ret; | |
154 | ||
155 | return 0; | |
156 | } | |
157 | ||
8d6d09e7 GR |
158 | static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, |
159 | u16 val) | |
91da11f8 | 160 | { |
b184e497 | 161 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); |
91da11f8 | 162 | |
3996a4ff VD |
163 | assert_smi_lock(ds); |
164 | ||
b184e497 GR |
165 | if (bus == NULL) |
166 | return -EINVAL; | |
167 | ||
bb92ea5e VD |
168 | dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
169 | addr, reg, val); | |
170 | ||
8d6d09e7 GR |
171 | return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val); |
172 | } | |
173 | ||
174 | int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) | |
175 | { | |
176 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
177 | int ret; | |
178 | ||
91da11f8 | 179 | mutex_lock(&ps->smi_mutex); |
8d6d09e7 | 180 | ret = _mv88e6xxx_reg_write(ds, addr, reg, val); |
91da11f8 LB |
181 | mutex_unlock(&ps->smi_mutex); |
182 | ||
183 | return ret; | |
184 | } | |
185 | ||
2e5f0320 LB |
186 | int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr) |
187 | { | |
cca8b133 AL |
188 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]); |
189 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); | |
190 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); | |
2e5f0320 LB |
191 | |
192 | return 0; | |
193 | } | |
194 | ||
91da11f8 LB |
195 | int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr) |
196 | { | |
197 | int i; | |
198 | int ret; | |
199 | ||
200 | for (i = 0; i < 6; i++) { | |
201 | int j; | |
202 | ||
3675c8d7 | 203 | /* Write the MAC address byte. */ |
cca8b133 AL |
204 | REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC, |
205 | GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]); | |
91da11f8 | 206 | |
3675c8d7 | 207 | /* Wait for the write to complete. */ |
91da11f8 | 208 | for (j = 0; j < 16; j++) { |
cca8b133 AL |
209 | ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC); |
210 | if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0) | |
91da11f8 LB |
211 | break; |
212 | } | |
213 | if (j == 16) | |
214 | return -ETIMEDOUT; | |
215 | } | |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
fd3a0ee4 | 220 | static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum) |
91da11f8 LB |
221 | { |
222 | if (addr >= 0) | |
3898c148 | 223 | return _mv88e6xxx_reg_read(ds, addr, regnum); |
91da11f8 LB |
224 | return 0xffff; |
225 | } | |
226 | ||
fd3a0ee4 AL |
227 | static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, |
228 | u16 val) | |
91da11f8 LB |
229 | { |
230 | if (addr >= 0) | |
3898c148 | 231 | return _mv88e6xxx_reg_write(ds, addr, regnum, val); |
91da11f8 LB |
232 | return 0; |
233 | } | |
234 | ||
2e5f0320 LB |
235 | #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU |
236 | static int mv88e6xxx_ppu_disable(struct dsa_switch *ds) | |
237 | { | |
238 | int ret; | |
19b2f97e | 239 | unsigned long timeout; |
2e5f0320 | 240 | |
cca8b133 AL |
241 | ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); |
242 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, | |
243 | ret & ~GLOBAL_CONTROL_PPU_ENABLE); | |
2e5f0320 | 244 | |
19b2f97e BG |
245 | timeout = jiffies + 1 * HZ; |
246 | while (time_before(jiffies, timeout)) { | |
cca8b133 | 247 | ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); |
19b2f97e | 248 | usleep_range(1000, 2000); |
cca8b133 AL |
249 | if ((ret & GLOBAL_STATUS_PPU_MASK) != |
250 | GLOBAL_STATUS_PPU_POLLING) | |
85686581 | 251 | return 0; |
2e5f0320 LB |
252 | } |
253 | ||
254 | return -ETIMEDOUT; | |
255 | } | |
256 | ||
257 | static int mv88e6xxx_ppu_enable(struct dsa_switch *ds) | |
258 | { | |
259 | int ret; | |
19b2f97e | 260 | unsigned long timeout; |
2e5f0320 | 261 | |
cca8b133 AL |
262 | ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); |
263 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE); | |
2e5f0320 | 264 | |
19b2f97e BG |
265 | timeout = jiffies + 1 * HZ; |
266 | while (time_before(jiffies, timeout)) { | |
cca8b133 | 267 | ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); |
19b2f97e | 268 | usleep_range(1000, 2000); |
cca8b133 AL |
269 | if ((ret & GLOBAL_STATUS_PPU_MASK) == |
270 | GLOBAL_STATUS_PPU_POLLING) | |
85686581 | 271 | return 0; |
2e5f0320 LB |
272 | } |
273 | ||
274 | return -ETIMEDOUT; | |
275 | } | |
276 | ||
277 | static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) | |
278 | { | |
279 | struct mv88e6xxx_priv_state *ps; | |
280 | ||
281 | ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work); | |
282 | if (mutex_trylock(&ps->ppu_mutex)) { | |
85686581 | 283 | struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1; |
2e5f0320 | 284 | |
85686581 BG |
285 | if (mv88e6xxx_ppu_enable(ds) == 0) |
286 | ps->ppu_disabled = 0; | |
287 | mutex_unlock(&ps->ppu_mutex); | |
2e5f0320 LB |
288 | } |
289 | } | |
290 | ||
291 | static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) | |
292 | { | |
293 | struct mv88e6xxx_priv_state *ps = (void *)_ps; | |
294 | ||
295 | schedule_work(&ps->ppu_work); | |
296 | } | |
297 | ||
298 | static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds) | |
299 | { | |
a22adce5 | 300 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 LB |
301 | int ret; |
302 | ||
303 | mutex_lock(&ps->ppu_mutex); | |
304 | ||
3675c8d7 | 305 | /* If the PHY polling unit is enabled, disable it so that |
2e5f0320 LB |
306 | * we can access the PHY registers. If it was already |
307 | * disabled, cancel the timer that is going to re-enable | |
308 | * it. | |
309 | */ | |
310 | if (!ps->ppu_disabled) { | |
85686581 BG |
311 | ret = mv88e6xxx_ppu_disable(ds); |
312 | if (ret < 0) { | |
313 | mutex_unlock(&ps->ppu_mutex); | |
314 | return ret; | |
315 | } | |
316 | ps->ppu_disabled = 1; | |
2e5f0320 | 317 | } else { |
85686581 BG |
318 | del_timer(&ps->ppu_timer); |
319 | ret = 0; | |
2e5f0320 LB |
320 | } |
321 | ||
322 | return ret; | |
323 | } | |
324 | ||
325 | static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds) | |
326 | { | |
a22adce5 | 327 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 | 328 | |
3675c8d7 | 329 | /* Schedule a timer to re-enable the PHY polling unit. */ |
2e5f0320 LB |
330 | mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10)); |
331 | mutex_unlock(&ps->ppu_mutex); | |
332 | } | |
333 | ||
334 | void mv88e6xxx_ppu_state_init(struct dsa_switch *ds) | |
335 | { | |
a22adce5 | 336 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 LB |
337 | |
338 | mutex_init(&ps->ppu_mutex); | |
339 | INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work); | |
340 | init_timer(&ps->ppu_timer); | |
341 | ps->ppu_timer.data = (unsigned long)ps; | |
342 | ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer; | |
343 | } | |
344 | ||
345 | int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum) | |
346 | { | |
347 | int ret; | |
348 | ||
349 | ret = mv88e6xxx_ppu_access_get(ds); | |
350 | if (ret >= 0) { | |
85686581 BG |
351 | ret = mv88e6xxx_reg_read(ds, addr, regnum); |
352 | mv88e6xxx_ppu_access_put(ds); | |
2e5f0320 LB |
353 | } |
354 | ||
355 | return ret; | |
356 | } | |
357 | ||
358 | int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr, | |
359 | int regnum, u16 val) | |
360 | { | |
361 | int ret; | |
362 | ||
363 | ret = mv88e6xxx_ppu_access_get(ds); | |
364 | if (ret >= 0) { | |
85686581 BG |
365 | ret = mv88e6xxx_reg_write(ds, addr, regnum, val); |
366 | mv88e6xxx_ppu_access_put(ds); | |
2e5f0320 LB |
367 | } |
368 | ||
369 | return ret; | |
370 | } | |
371 | #endif | |
372 | ||
54d792f2 AL |
373 | static bool mv88e6xxx_6065_family(struct dsa_switch *ds) |
374 | { | |
375 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
376 | ||
377 | switch (ps->id) { | |
378 | case PORT_SWITCH_ID_6031: | |
379 | case PORT_SWITCH_ID_6061: | |
380 | case PORT_SWITCH_ID_6035: | |
381 | case PORT_SWITCH_ID_6065: | |
382 | return true; | |
383 | } | |
384 | return false; | |
385 | } | |
386 | ||
387 | static bool mv88e6xxx_6095_family(struct dsa_switch *ds) | |
388 | { | |
389 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
390 | ||
391 | switch (ps->id) { | |
392 | case PORT_SWITCH_ID_6092: | |
393 | case PORT_SWITCH_ID_6095: | |
394 | return true; | |
395 | } | |
396 | return false; | |
397 | } | |
398 | ||
399 | static bool mv88e6xxx_6097_family(struct dsa_switch *ds) | |
400 | { | |
401 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
402 | ||
403 | switch (ps->id) { | |
404 | case PORT_SWITCH_ID_6046: | |
405 | case PORT_SWITCH_ID_6085: | |
406 | case PORT_SWITCH_ID_6096: | |
407 | case PORT_SWITCH_ID_6097: | |
408 | return true; | |
409 | } | |
410 | return false; | |
411 | } | |
412 | ||
413 | static bool mv88e6xxx_6165_family(struct dsa_switch *ds) | |
414 | { | |
415 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
416 | ||
417 | switch (ps->id) { | |
418 | case PORT_SWITCH_ID_6123: | |
419 | case PORT_SWITCH_ID_6161: | |
420 | case PORT_SWITCH_ID_6165: | |
421 | return true; | |
422 | } | |
423 | return false; | |
424 | } | |
425 | ||
426 | static bool mv88e6xxx_6185_family(struct dsa_switch *ds) | |
427 | { | |
428 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
429 | ||
430 | switch (ps->id) { | |
431 | case PORT_SWITCH_ID_6121: | |
432 | case PORT_SWITCH_ID_6122: | |
433 | case PORT_SWITCH_ID_6152: | |
434 | case PORT_SWITCH_ID_6155: | |
435 | case PORT_SWITCH_ID_6182: | |
436 | case PORT_SWITCH_ID_6185: | |
437 | case PORT_SWITCH_ID_6108: | |
438 | case PORT_SWITCH_ID_6131: | |
439 | return true; | |
440 | } | |
441 | return false; | |
442 | } | |
443 | ||
c22995c5 | 444 | static bool mv88e6xxx_6320_family(struct dsa_switch *ds) |
7c3d0d67 AK |
445 | { |
446 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
447 | ||
448 | switch (ps->id) { | |
449 | case PORT_SWITCH_ID_6320: | |
450 | case PORT_SWITCH_ID_6321: | |
451 | return true; | |
452 | } | |
453 | return false; | |
454 | } | |
455 | ||
54d792f2 AL |
456 | static bool mv88e6xxx_6351_family(struct dsa_switch *ds) |
457 | { | |
458 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
459 | ||
460 | switch (ps->id) { | |
461 | case PORT_SWITCH_ID_6171: | |
462 | case PORT_SWITCH_ID_6175: | |
463 | case PORT_SWITCH_ID_6350: | |
464 | case PORT_SWITCH_ID_6351: | |
465 | return true; | |
466 | } | |
467 | return false; | |
468 | } | |
469 | ||
f3a8b6b6 AL |
470 | static bool mv88e6xxx_6352_family(struct dsa_switch *ds) |
471 | { | |
472 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
473 | ||
474 | switch (ps->id) { | |
f3a8b6b6 AL |
475 | case PORT_SWITCH_ID_6172: |
476 | case PORT_SWITCH_ID_6176: | |
54d792f2 AL |
477 | case PORT_SWITCH_ID_6240: |
478 | case PORT_SWITCH_ID_6352: | |
f3a8b6b6 AL |
479 | return true; |
480 | } | |
481 | return false; | |
482 | } | |
483 | ||
dea87024 AL |
484 | /* We expect the switch to perform auto negotiation if there is a real |
485 | * phy. However, in the case of a fixed link phy, we force the port | |
486 | * settings from the fixed link settings. | |
487 | */ | |
488 | void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, | |
489 | struct phy_device *phydev) | |
490 | { | |
491 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
49052871 AL |
492 | u32 reg; |
493 | int ret; | |
dea87024 AL |
494 | |
495 | if (!phy_is_pseudo_fixed_link(phydev)) | |
496 | return; | |
497 | ||
498 | mutex_lock(&ps->smi_mutex); | |
499 | ||
500 | ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL); | |
501 | if (ret < 0) | |
502 | goto out; | |
503 | ||
504 | reg = ret & ~(PORT_PCS_CTRL_LINK_UP | | |
505 | PORT_PCS_CTRL_FORCE_LINK | | |
506 | PORT_PCS_CTRL_DUPLEX_FULL | | |
507 | PORT_PCS_CTRL_FORCE_DUPLEX | | |
508 | PORT_PCS_CTRL_UNFORCED); | |
509 | ||
510 | reg |= PORT_PCS_CTRL_FORCE_LINK; | |
511 | if (phydev->link) | |
512 | reg |= PORT_PCS_CTRL_LINK_UP; | |
513 | ||
514 | if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100) | |
515 | goto out; | |
516 | ||
517 | switch (phydev->speed) { | |
518 | case SPEED_1000: | |
519 | reg |= PORT_PCS_CTRL_1000; | |
520 | break; | |
521 | case SPEED_100: | |
522 | reg |= PORT_PCS_CTRL_100; | |
523 | break; | |
524 | case SPEED_10: | |
525 | reg |= PORT_PCS_CTRL_10; | |
526 | break; | |
527 | default: | |
528 | pr_info("Unknown speed"); | |
529 | goto out; | |
530 | } | |
531 | ||
532 | reg |= PORT_PCS_CTRL_FORCE_DUPLEX; | |
533 | if (phydev->duplex == DUPLEX_FULL) | |
534 | reg |= PORT_PCS_CTRL_DUPLEX_FULL; | |
535 | ||
e7e72ac0 AL |
536 | if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) && |
537 | (port >= ps->num_ports - 2)) { | |
538 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) | |
539 | reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK; | |
540 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) | |
541 | reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK; | |
542 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) | |
543 | reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK | | |
544 | PORT_PCS_CTRL_RGMII_DELAY_TXCLK); | |
545 | } | |
dea87024 AL |
546 | _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg); |
547 | ||
548 | out: | |
549 | mutex_unlock(&ps->smi_mutex); | |
550 | } | |
551 | ||
31888234 | 552 | static int _mv88e6xxx_stats_wait(struct dsa_switch *ds) |
91da11f8 LB |
553 | { |
554 | int ret; | |
555 | int i; | |
556 | ||
557 | for (i = 0; i < 10; i++) { | |
31888234 | 558 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP); |
cca8b133 | 559 | if ((ret & GLOBAL_STATS_OP_BUSY) == 0) |
91da11f8 LB |
560 | return 0; |
561 | } | |
562 | ||
563 | return -ETIMEDOUT; | |
564 | } | |
565 | ||
31888234 | 566 | static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port) |
91da11f8 LB |
567 | { |
568 | int ret; | |
569 | ||
7c3d0d67 | 570 | if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds)) |
f3a8b6b6 AL |
571 | port = (port + 1) << 5; |
572 | ||
3675c8d7 | 573 | /* Snapshot the hardware statistics counters for this port. */ |
31888234 AL |
574 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP, |
575 | GLOBAL_STATS_OP_CAPTURE_PORT | | |
576 | GLOBAL_STATS_OP_HIST_RX_TX | port); | |
577 | if (ret < 0) | |
578 | return ret; | |
91da11f8 | 579 | |
3675c8d7 | 580 | /* Wait for the snapshotting to complete. */ |
31888234 | 581 | ret = _mv88e6xxx_stats_wait(ds); |
91da11f8 LB |
582 | if (ret < 0) |
583 | return ret; | |
584 | ||
585 | return 0; | |
586 | } | |
587 | ||
31888234 | 588 | static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val) |
91da11f8 LB |
589 | { |
590 | u32 _val; | |
591 | int ret; | |
592 | ||
593 | *val = 0; | |
594 | ||
31888234 AL |
595 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP, |
596 | GLOBAL_STATS_OP_READ_CAPTURED | | |
597 | GLOBAL_STATS_OP_HIST_RX_TX | stat); | |
91da11f8 LB |
598 | if (ret < 0) |
599 | return; | |
600 | ||
31888234 | 601 | ret = _mv88e6xxx_stats_wait(ds); |
91da11f8 LB |
602 | if (ret < 0) |
603 | return; | |
604 | ||
31888234 | 605 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32); |
91da11f8 LB |
606 | if (ret < 0) |
607 | return; | |
608 | ||
609 | _val = ret << 16; | |
610 | ||
31888234 | 611 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01); |
91da11f8 LB |
612 | if (ret < 0) |
613 | return; | |
614 | ||
615 | *val = _val | ret; | |
616 | } | |
617 | ||
e413e7e1 AL |
618 | static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { |
619 | { "in_good_octets", 8, 0x00, }, | |
620 | { "in_bad_octets", 4, 0x02, }, | |
621 | { "in_unicast", 4, 0x04, }, | |
622 | { "in_broadcasts", 4, 0x06, }, | |
623 | { "in_multicasts", 4, 0x07, }, | |
624 | { "in_pause", 4, 0x16, }, | |
625 | { "in_undersize", 4, 0x18, }, | |
626 | { "in_fragments", 4, 0x19, }, | |
627 | { "in_oversize", 4, 0x1a, }, | |
628 | { "in_jabber", 4, 0x1b, }, | |
629 | { "in_rx_error", 4, 0x1c, }, | |
630 | { "in_fcs_error", 4, 0x1d, }, | |
631 | { "out_octets", 8, 0x0e, }, | |
632 | { "out_unicast", 4, 0x10, }, | |
633 | { "out_broadcasts", 4, 0x13, }, | |
634 | { "out_multicasts", 4, 0x12, }, | |
635 | { "out_pause", 4, 0x15, }, | |
636 | { "excessive", 4, 0x11, }, | |
637 | { "collisions", 4, 0x1e, }, | |
638 | { "deferred", 4, 0x05, }, | |
639 | { "single", 4, 0x14, }, | |
640 | { "multiple", 4, 0x17, }, | |
641 | { "out_fcs_error", 4, 0x03, }, | |
642 | { "late", 4, 0x1f, }, | |
643 | { "hist_64bytes", 4, 0x08, }, | |
644 | { "hist_65_127bytes", 4, 0x09, }, | |
645 | { "hist_128_255bytes", 4, 0x0a, }, | |
646 | { "hist_256_511bytes", 4, 0x0b, }, | |
647 | { "hist_512_1023bytes", 4, 0x0c, }, | |
648 | { "hist_1024_max_bytes", 4, 0x0d, }, | |
649 | /* Not all devices have the following counters */ | |
650 | { "sw_in_discards", 4, 0x110, }, | |
651 | { "sw_in_filtered", 2, 0x112, }, | |
652 | { "sw_out_filtered", 2, 0x113, }, | |
653 | ||
654 | }; | |
655 | ||
656 | static bool have_sw_in_discards(struct dsa_switch *ds) | |
657 | { | |
658 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
659 | ||
660 | switch (ps->id) { | |
cca8b133 AL |
661 | case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161: |
662 | case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171: | |
663 | case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176: | |
664 | case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185: | |
665 | case PORT_SWITCH_ID_6352: | |
e413e7e1 AL |
666 | return true; |
667 | default: | |
668 | return false; | |
669 | } | |
670 | } | |
671 | ||
672 | static void _mv88e6xxx_get_strings(struct dsa_switch *ds, | |
673 | int nr_stats, | |
674 | struct mv88e6xxx_hw_stat *stats, | |
675 | int port, uint8_t *data) | |
91da11f8 LB |
676 | { |
677 | int i; | |
678 | ||
679 | for (i = 0; i < nr_stats; i++) { | |
680 | memcpy(data + i * ETH_GSTRING_LEN, | |
681 | stats[i].string, ETH_GSTRING_LEN); | |
682 | } | |
683 | } | |
684 | ||
80c4627b AL |
685 | static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds, |
686 | int stat, | |
687 | struct mv88e6xxx_hw_stat *stats, | |
688 | int port) | |
689 | { | |
690 | struct mv88e6xxx_hw_stat *s = stats + stat; | |
691 | u32 low; | |
692 | u32 high = 0; | |
693 | int ret; | |
694 | u64 value; | |
695 | ||
696 | if (s->reg >= 0x100) { | |
697 | ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), | |
698 | s->reg - 0x100); | |
699 | if (ret < 0) | |
700 | return UINT64_MAX; | |
701 | ||
702 | low = ret; | |
703 | if (s->sizeof_stat == 4) { | |
704 | ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), | |
705 | s->reg - 0x100 + 1); | |
706 | if (ret < 0) | |
707 | return UINT64_MAX; | |
708 | high = ret; | |
709 | } | |
710 | } else { | |
711 | _mv88e6xxx_stats_read(ds, s->reg, &low); | |
712 | if (s->sizeof_stat == 8) | |
713 | _mv88e6xxx_stats_read(ds, s->reg + 1, &high); | |
714 | } | |
715 | value = (((u64)high) << 16) | low; | |
716 | return value; | |
717 | } | |
718 | ||
e413e7e1 AL |
719 | static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, |
720 | int nr_stats, | |
721 | struct mv88e6xxx_hw_stat *stats, | |
722 | int port, uint64_t *data) | |
91da11f8 | 723 | { |
a22adce5 | 724 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
91da11f8 LB |
725 | int ret; |
726 | int i; | |
727 | ||
31888234 | 728 | mutex_lock(&ps->smi_mutex); |
91da11f8 | 729 | |
31888234 | 730 | ret = _mv88e6xxx_stats_snapshot(ds, port); |
91da11f8 | 731 | if (ret < 0) { |
31888234 | 732 | mutex_unlock(&ps->smi_mutex); |
91da11f8 LB |
733 | return; |
734 | } | |
735 | ||
3675c8d7 | 736 | /* Read each of the counters. */ |
80c4627b AL |
737 | for (i = 0; i < nr_stats; i++) |
738 | data[i] = _mv88e6xxx_get_ethtool_stat(ds, i, stats, port); | |
91da11f8 | 739 | |
31888234 | 740 | mutex_unlock(&ps->smi_mutex); |
91da11f8 | 741 | } |
98e67308 | 742 | |
e413e7e1 AL |
743 | /* All the statistics in the table */ |
744 | void | |
745 | mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
746 | { | |
747 | if (have_sw_in_discards(ds)) | |
748 | _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats), | |
749 | mv88e6xxx_hw_stats, port, data); | |
750 | else | |
751 | _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3, | |
752 | mv88e6xxx_hw_stats, port, data); | |
753 | } | |
754 | ||
755 | int mv88e6xxx_get_sset_count(struct dsa_switch *ds) | |
756 | { | |
757 | if (have_sw_in_discards(ds)) | |
758 | return ARRAY_SIZE(mv88e6xxx_hw_stats); | |
759 | return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3; | |
760 | } | |
761 | ||
762 | void | |
763 | mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, | |
764 | int port, uint64_t *data) | |
765 | { | |
766 | if (have_sw_in_discards(ds)) | |
767 | _mv88e6xxx_get_ethtool_stats( | |
768 | ds, ARRAY_SIZE(mv88e6xxx_hw_stats), | |
769 | mv88e6xxx_hw_stats, port, data); | |
770 | else | |
771 | _mv88e6xxx_get_ethtool_stats( | |
772 | ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3, | |
773 | mv88e6xxx_hw_stats, port, data); | |
774 | } | |
775 | ||
a1ab91f3 GR |
776 | int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) |
777 | { | |
778 | return 32 * sizeof(u16); | |
779 | } | |
780 | ||
781 | void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, | |
782 | struct ethtool_regs *regs, void *_p) | |
783 | { | |
784 | u16 *p = _p; | |
785 | int i; | |
786 | ||
787 | regs->version = 0; | |
788 | ||
789 | memset(p, 0xff, 32 * sizeof(u16)); | |
790 | ||
791 | for (i = 0; i < 32; i++) { | |
792 | int ret; | |
793 | ||
794 | ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i); | |
795 | if (ret >= 0) | |
796 | p[i] = ret; | |
797 | } | |
798 | } | |
799 | ||
3898c148 AL |
800 | static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, |
801 | u16 mask) | |
f3044683 AL |
802 | { |
803 | unsigned long timeout = jiffies + HZ / 10; | |
804 | ||
805 | while (time_before(jiffies, timeout)) { | |
806 | int ret; | |
807 | ||
3898c148 AL |
808 | ret = _mv88e6xxx_reg_read(ds, reg, offset); |
809 | if (ret < 0) | |
810 | return ret; | |
f3044683 AL |
811 | if (!(ret & mask)) |
812 | return 0; | |
813 | ||
814 | usleep_range(1000, 2000); | |
815 | } | |
816 | return -ETIMEDOUT; | |
817 | } | |
818 | ||
3898c148 AL |
819 | static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask) |
820 | { | |
821 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
822 | int ret; | |
823 | ||
824 | mutex_lock(&ps->smi_mutex); | |
825 | ret = _mv88e6xxx_wait(ds, reg, offset, mask); | |
826 | mutex_unlock(&ps->smi_mutex); | |
827 | ||
828 | return ret; | |
829 | } | |
830 | ||
831 | static int _mv88e6xxx_phy_wait(struct dsa_switch *ds) | |
f3044683 | 832 | { |
3898c148 AL |
833 | return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP, |
834 | GLOBAL2_SMI_OP_BUSY); | |
f3044683 AL |
835 | } |
836 | ||
837 | int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds) | |
838 | { | |
cca8b133 AL |
839 | return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP, |
840 | GLOBAL2_EEPROM_OP_LOAD); | |
f3044683 AL |
841 | } |
842 | ||
843 | int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds) | |
844 | { | |
cca8b133 AL |
845 | return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP, |
846 | GLOBAL2_EEPROM_OP_BUSY); | |
f3044683 AL |
847 | } |
848 | ||
facd95b2 GR |
849 | static int _mv88e6xxx_atu_wait(struct dsa_switch *ds) |
850 | { | |
cca8b133 AL |
851 | return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP, |
852 | GLOBAL_ATU_OP_BUSY); | |
facd95b2 GR |
853 | } |
854 | ||
fd3a0ee4 AL |
855 | static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, |
856 | int regnum) | |
f3044683 AL |
857 | { |
858 | int ret; | |
859 | ||
3898c148 AL |
860 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP, |
861 | GLOBAL2_SMI_OP_22_READ | (addr << 5) | | |
862 | regnum); | |
863 | if (ret < 0) | |
864 | return ret; | |
f3044683 | 865 | |
3898c148 | 866 | ret = _mv88e6xxx_phy_wait(ds); |
f3044683 AL |
867 | if (ret < 0) |
868 | return ret; | |
869 | ||
3898c148 | 870 | return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA); |
f3044683 AL |
871 | } |
872 | ||
fd3a0ee4 AL |
873 | static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, |
874 | int regnum, u16 val) | |
f3044683 | 875 | { |
3898c148 AL |
876 | int ret; |
877 | ||
878 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val); | |
879 | if (ret < 0) | |
880 | return ret; | |
f3044683 | 881 | |
3898c148 AL |
882 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP, |
883 | GLOBAL2_SMI_OP_22_WRITE | (addr << 5) | | |
884 | regnum); | |
885 | ||
886 | return _mv88e6xxx_phy_wait(ds); | |
f3044683 AL |
887 | } |
888 | ||
11b3b45d GR |
889 | int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) |
890 | { | |
2f40c698 | 891 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
11b3b45d GR |
892 | int reg; |
893 | ||
3898c148 | 894 | mutex_lock(&ps->smi_mutex); |
2f40c698 AL |
895 | |
896 | reg = _mv88e6xxx_phy_read_indirect(ds, port, 16); | |
11b3b45d | 897 | if (reg < 0) |
2f40c698 | 898 | goto out; |
11b3b45d GR |
899 | |
900 | e->eee_enabled = !!(reg & 0x0200); | |
901 | e->tx_lpi_enabled = !!(reg & 0x0100); | |
902 | ||
3898c148 | 903 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS); |
11b3b45d | 904 | if (reg < 0) |
2f40c698 | 905 | goto out; |
11b3b45d | 906 | |
cca8b133 | 907 | e->eee_active = !!(reg & PORT_STATUS_EEE); |
2f40c698 | 908 | reg = 0; |
11b3b45d | 909 | |
2f40c698 | 910 | out: |
3898c148 | 911 | mutex_unlock(&ps->smi_mutex); |
2f40c698 | 912 | return reg; |
11b3b45d GR |
913 | } |
914 | ||
915 | int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, | |
916 | struct phy_device *phydev, struct ethtool_eee *e) | |
917 | { | |
2f40c698 AL |
918 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
919 | int reg; | |
11b3b45d GR |
920 | int ret; |
921 | ||
3898c148 | 922 | mutex_lock(&ps->smi_mutex); |
11b3b45d | 923 | |
2f40c698 AL |
924 | ret = _mv88e6xxx_phy_read_indirect(ds, port, 16); |
925 | if (ret < 0) | |
926 | goto out; | |
927 | ||
928 | reg = ret & ~0x0300; | |
929 | if (e->eee_enabled) | |
930 | reg |= 0x0200; | |
931 | if (e->tx_lpi_enabled) | |
932 | reg |= 0x0100; | |
933 | ||
934 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg); | |
935 | out: | |
3898c148 | 936 | mutex_unlock(&ps->smi_mutex); |
2f40c698 AL |
937 | |
938 | return ret; | |
11b3b45d GR |
939 | } |
940 | ||
70cc99d1 | 941 | static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 cmd) |
facd95b2 GR |
942 | { |
943 | int ret; | |
944 | ||
cca8b133 | 945 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd); |
facd95b2 GR |
946 | if (ret < 0) |
947 | return ret; | |
948 | ||
949 | return _mv88e6xxx_atu_wait(ds); | |
950 | } | |
951 | ||
37705b73 VD |
952 | static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds, |
953 | struct mv88e6xxx_atu_entry *entry) | |
954 | { | |
955 | u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK; | |
956 | ||
957 | if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) { | |
958 | unsigned int mask, shift; | |
959 | ||
960 | if (entry->trunk) { | |
961 | data |= GLOBAL_ATU_DATA_TRUNK; | |
962 | mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; | |
963 | shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; | |
964 | } else { | |
965 | mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; | |
966 | shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; | |
967 | } | |
968 | ||
969 | data |= (entry->portv_trunkid << shift) & mask; | |
970 | } | |
971 | ||
972 | return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data); | |
973 | } | |
974 | ||
7fb5e755 VD |
975 | static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds, |
976 | struct mv88e6xxx_atu_entry *entry, | |
977 | bool static_too) | |
facd95b2 | 978 | { |
7fb5e755 VD |
979 | int op; |
980 | int err; | |
facd95b2 | 981 | |
7fb5e755 VD |
982 | err = _mv88e6xxx_atu_wait(ds); |
983 | if (err) | |
984 | return err; | |
facd95b2 | 985 | |
7fb5e755 VD |
986 | err = _mv88e6xxx_atu_data_write(ds, entry); |
987 | if (err) | |
988 | return err; | |
989 | ||
990 | if (entry->fid) { | |
991 | err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, | |
992 | entry->fid); | |
993 | if (err) | |
994 | return err; | |
995 | ||
996 | op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB : | |
997 | GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; | |
998 | } else { | |
999 | op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL : | |
1000 | GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC; | |
1001 | } | |
1002 | ||
1003 | return _mv88e6xxx_atu_cmd(ds, op); | |
1004 | } | |
1005 | ||
1006 | static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too) | |
1007 | { | |
1008 | struct mv88e6xxx_atu_entry entry = { | |
1009 | .fid = fid, | |
1010 | .state = 0, /* EntryState bits must be 0 */ | |
1011 | }; | |
70cc99d1 | 1012 | |
7fb5e755 VD |
1013 | return _mv88e6xxx_atu_flush_move(ds, &entry, static_too); |
1014 | } | |
1015 | ||
9f4d55d2 VD |
1016 | static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port, |
1017 | int to_port, bool static_too) | |
1018 | { | |
1019 | struct mv88e6xxx_atu_entry entry = { | |
1020 | .trunk = false, | |
1021 | .fid = fid, | |
1022 | }; | |
1023 | ||
1024 | /* EntryState bits must be 0xF */ | |
1025 | entry.state = GLOBAL_ATU_DATA_STATE_MASK; | |
1026 | ||
1027 | /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */ | |
1028 | entry.portv_trunkid = (to_port & 0x0f) << 4; | |
1029 | entry.portv_trunkid |= from_port & 0x0f; | |
1030 | ||
1031 | return _mv88e6xxx_atu_flush_move(ds, &entry, static_too); | |
1032 | } | |
1033 | ||
1034 | static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port, | |
1035 | bool static_too) | |
1036 | { | |
1037 | /* Destination port 0xF means remove the entries */ | |
1038 | return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too); | |
1039 | } | |
1040 | ||
facd95b2 GR |
1041 | static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state) |
1042 | { | |
1043 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
c3ffe6d2 | 1044 | int reg, ret = 0; |
facd95b2 GR |
1045 | u8 oldstate; |
1046 | ||
1047 | mutex_lock(&ps->smi_mutex); | |
1048 | ||
cca8b133 | 1049 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL); |
538cc282 GR |
1050 | if (reg < 0) { |
1051 | ret = reg; | |
facd95b2 | 1052 | goto abort; |
538cc282 | 1053 | } |
facd95b2 | 1054 | |
cca8b133 | 1055 | oldstate = reg & PORT_CONTROL_STATE_MASK; |
facd95b2 GR |
1056 | if (oldstate != state) { |
1057 | /* Flush forwarding database if we're moving a port | |
1058 | * from Learning or Forwarding state to Disabled or | |
1059 | * Blocking or Listening state. | |
1060 | */ | |
cca8b133 AL |
1061 | if (oldstate >= PORT_CONTROL_STATE_LEARNING && |
1062 | state <= PORT_CONTROL_STATE_BLOCKING) { | |
2b8157b1 | 1063 | ret = _mv88e6xxx_atu_remove(ds, 0, port, false); |
facd95b2 GR |
1064 | if (ret) |
1065 | goto abort; | |
1066 | } | |
cca8b133 AL |
1067 | reg = (reg & ~PORT_CONTROL_STATE_MASK) | state; |
1068 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL, | |
1069 | reg); | |
facd95b2 GR |
1070 | } |
1071 | ||
1072 | abort: | |
1073 | mutex_unlock(&ps->smi_mutex); | |
1074 | return ret; | |
1075 | } | |
1076 | ||
ede8098d VD |
1077 | static int _mv88e6xxx_port_vlan_map_set(struct dsa_switch *ds, int port, |
1078 | u16 output_ports) | |
facd95b2 GR |
1079 | { |
1080 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
ede8098d VD |
1081 | const u16 mask = (1 << ps->num_ports) - 1; |
1082 | int reg; | |
facd95b2 | 1083 | |
ede8098d VD |
1084 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN); |
1085 | if (reg < 0) | |
1086 | return reg; | |
facd95b2 | 1087 | |
ede8098d VD |
1088 | reg &= ~mask; |
1089 | reg |= output_ports & mask; | |
facd95b2 | 1090 | |
ede8098d | 1091 | return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg); |
facd95b2 GR |
1092 | } |
1093 | ||
facd95b2 GR |
1094 | int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state) |
1095 | { | |
1096 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1097 | int stp_state; | |
1098 | ||
1099 | switch (state) { | |
1100 | case BR_STATE_DISABLED: | |
cca8b133 | 1101 | stp_state = PORT_CONTROL_STATE_DISABLED; |
facd95b2 GR |
1102 | break; |
1103 | case BR_STATE_BLOCKING: | |
1104 | case BR_STATE_LISTENING: | |
cca8b133 | 1105 | stp_state = PORT_CONTROL_STATE_BLOCKING; |
facd95b2 GR |
1106 | break; |
1107 | case BR_STATE_LEARNING: | |
cca8b133 | 1108 | stp_state = PORT_CONTROL_STATE_LEARNING; |
facd95b2 GR |
1109 | break; |
1110 | case BR_STATE_FORWARDING: | |
1111 | default: | |
cca8b133 | 1112 | stp_state = PORT_CONTROL_STATE_FORWARDING; |
facd95b2 GR |
1113 | break; |
1114 | } | |
1115 | ||
1116 | netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state); | |
1117 | ||
1118 | /* mv88e6xxx_port_stp_update may be called with softirqs disabled, | |
1119 | * so we can not update the port state directly but need to schedule it. | |
1120 | */ | |
1121 | ps->port_state[port] = stp_state; | |
1122 | set_bit(port, &ps->port_state_update_mask); | |
1123 | schedule_work(&ps->bridge_work); | |
1124 | ||
1125 | return 0; | |
1126 | } | |
1127 | ||
76e398a6 VD |
1128 | static int _mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid) |
1129 | { | |
1130 | int ret; | |
1131 | ||
1132 | ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN); | |
1133 | if (ret < 0) | |
1134 | return ret; | |
1135 | ||
1136 | *pvid = ret & PORT_DEFAULT_VLAN_MASK; | |
1137 | ||
1138 | return 0; | |
1139 | } | |
1140 | ||
b8fee957 VD |
1141 | int mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid) |
1142 | { | |
1143 | int ret; | |
1144 | ||
1145 | ret = mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN); | |
1146 | if (ret < 0) | |
1147 | return ret; | |
1148 | ||
1149 | *pvid = ret & PORT_DEFAULT_VLAN_MASK; | |
1150 | ||
1151 | return 0; | |
1152 | } | |
1153 | ||
76e398a6 | 1154 | static int _mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid) |
0d3b33e6 | 1155 | { |
76e398a6 | 1156 | return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN, |
0d3b33e6 VD |
1157 | pvid & PORT_DEFAULT_VLAN_MASK); |
1158 | } | |
1159 | ||
6b17e864 VD |
1160 | static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds) |
1161 | { | |
1162 | return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP, | |
1163 | GLOBAL_VTU_OP_BUSY); | |
1164 | } | |
1165 | ||
1166 | static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op) | |
1167 | { | |
1168 | int ret; | |
1169 | ||
1170 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op); | |
1171 | if (ret < 0) | |
1172 | return ret; | |
1173 | ||
1174 | return _mv88e6xxx_vtu_wait(ds); | |
1175 | } | |
1176 | ||
1177 | static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds) | |
1178 | { | |
1179 | int ret; | |
1180 | ||
1181 | ret = _mv88e6xxx_vtu_wait(ds); | |
1182 | if (ret < 0) | |
1183 | return ret; | |
1184 | ||
1185 | return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL); | |
1186 | } | |
1187 | ||
b8fee957 VD |
1188 | static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds, |
1189 | struct mv88e6xxx_vtu_stu_entry *entry, | |
1190 | unsigned int nibble_offset) | |
1191 | { | |
1192 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1193 | u16 regs[3]; | |
1194 | int i; | |
1195 | int ret; | |
1196 | ||
1197 | for (i = 0; i < 3; ++i) { | |
1198 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, | |
1199 | GLOBAL_VTU_DATA_0_3 + i); | |
1200 | if (ret < 0) | |
1201 | return ret; | |
1202 | ||
1203 | regs[i] = ret; | |
1204 | } | |
1205 | ||
1206 | for (i = 0; i < ps->num_ports; ++i) { | |
1207 | unsigned int shift = (i % 4) * 4 + nibble_offset; | |
1208 | u16 reg = regs[i / 4]; | |
1209 | ||
1210 | entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK; | |
1211 | } | |
1212 | ||
1213 | return 0; | |
1214 | } | |
1215 | ||
7dad08d7 VD |
1216 | static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds, |
1217 | struct mv88e6xxx_vtu_stu_entry *entry, | |
1218 | unsigned int nibble_offset) | |
1219 | { | |
1220 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1221 | u16 regs[3] = { 0 }; | |
1222 | int i; | |
1223 | int ret; | |
1224 | ||
1225 | for (i = 0; i < ps->num_ports; ++i) { | |
1226 | unsigned int shift = (i % 4) * 4 + nibble_offset; | |
1227 | u8 data = entry->data[i]; | |
1228 | ||
1229 | regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift; | |
1230 | } | |
1231 | ||
1232 | for (i = 0; i < 3; ++i) { | |
1233 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, | |
1234 | GLOBAL_VTU_DATA_0_3 + i, regs[i]); | |
1235 | if (ret < 0) | |
1236 | return ret; | |
1237 | } | |
1238 | ||
1239 | return 0; | |
1240 | } | |
1241 | ||
36d04ba1 VD |
1242 | static int _mv88e6xxx_vtu_vid_write(struct dsa_switch *ds, u16 vid) |
1243 | { | |
1244 | return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, | |
1245 | vid & GLOBAL_VTU_VID_MASK); | |
1246 | } | |
1247 | ||
1248 | static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds, | |
b8fee957 VD |
1249 | struct mv88e6xxx_vtu_stu_entry *entry) |
1250 | { | |
1251 | struct mv88e6xxx_vtu_stu_entry next = { 0 }; | |
1252 | int ret; | |
1253 | ||
1254 | ret = _mv88e6xxx_vtu_wait(ds); | |
1255 | if (ret < 0) | |
1256 | return ret; | |
1257 | ||
b8fee957 VD |
1258 | ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT); |
1259 | if (ret < 0) | |
1260 | return ret; | |
1261 | ||
1262 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID); | |
1263 | if (ret < 0) | |
1264 | return ret; | |
1265 | ||
1266 | next.vid = ret & GLOBAL_VTU_VID_MASK; | |
1267 | next.valid = !!(ret & GLOBAL_VTU_VID_VALID); | |
1268 | ||
1269 | if (next.valid) { | |
1270 | ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0); | |
1271 | if (ret < 0) | |
1272 | return ret; | |
1273 | ||
1274 | if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) || | |
1275 | mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) { | |
1276 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, | |
1277 | GLOBAL_VTU_FID); | |
1278 | if (ret < 0) | |
1279 | return ret; | |
1280 | ||
1281 | next.fid = ret & GLOBAL_VTU_FID_MASK; | |
1282 | ||
1283 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, | |
1284 | GLOBAL_VTU_SID); | |
1285 | if (ret < 0) | |
1286 | return ret; | |
1287 | ||
1288 | next.sid = ret & GLOBAL_VTU_SID_MASK; | |
1289 | } | |
1290 | } | |
1291 | ||
1292 | *entry = next; | |
1293 | return 0; | |
1294 | } | |
1295 | ||
7dad08d7 VD |
1296 | static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds, |
1297 | struct mv88e6xxx_vtu_stu_entry *entry) | |
1298 | { | |
1299 | u16 reg = 0; | |
1300 | int ret; | |
1301 | ||
1302 | ret = _mv88e6xxx_vtu_wait(ds); | |
1303 | if (ret < 0) | |
1304 | return ret; | |
1305 | ||
1306 | if (!entry->valid) | |
1307 | goto loadpurge; | |
1308 | ||
1309 | /* Write port member tags */ | |
1310 | ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0); | |
1311 | if (ret < 0) | |
1312 | return ret; | |
1313 | ||
1314 | if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) || | |
1315 | mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) { | |
1316 | reg = entry->sid & GLOBAL_VTU_SID_MASK; | |
1317 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg); | |
1318 | if (ret < 0) | |
1319 | return ret; | |
1320 | ||
1321 | reg = entry->fid & GLOBAL_VTU_FID_MASK; | |
1322 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg); | |
1323 | if (ret < 0) | |
1324 | return ret; | |
1325 | } | |
1326 | ||
1327 | reg = GLOBAL_VTU_VID_VALID; | |
1328 | loadpurge: | |
1329 | reg |= entry->vid & GLOBAL_VTU_VID_MASK; | |
1330 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg); | |
1331 | if (ret < 0) | |
1332 | return ret; | |
1333 | ||
1334 | return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_LOAD_PURGE); | |
1335 | } | |
1336 | ||
0d3b33e6 VD |
1337 | static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid, |
1338 | struct mv88e6xxx_vtu_stu_entry *entry) | |
1339 | { | |
1340 | struct mv88e6xxx_vtu_stu_entry next = { 0 }; | |
1341 | int ret; | |
1342 | ||
1343 | ret = _mv88e6xxx_vtu_wait(ds); | |
1344 | if (ret < 0) | |
1345 | return ret; | |
1346 | ||
1347 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, | |
1348 | sid & GLOBAL_VTU_SID_MASK); | |
1349 | if (ret < 0) | |
1350 | return ret; | |
1351 | ||
1352 | ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT); | |
1353 | if (ret < 0) | |
1354 | return ret; | |
1355 | ||
1356 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID); | |
1357 | if (ret < 0) | |
1358 | return ret; | |
1359 | ||
1360 | next.sid = ret & GLOBAL_VTU_SID_MASK; | |
1361 | ||
1362 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID); | |
1363 | if (ret < 0) | |
1364 | return ret; | |
1365 | ||
1366 | next.valid = !!(ret & GLOBAL_VTU_VID_VALID); | |
1367 | ||
1368 | if (next.valid) { | |
1369 | ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2); | |
1370 | if (ret < 0) | |
1371 | return ret; | |
1372 | } | |
1373 | ||
1374 | *entry = next; | |
1375 | return 0; | |
1376 | } | |
1377 | ||
1378 | static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds, | |
1379 | struct mv88e6xxx_vtu_stu_entry *entry) | |
1380 | { | |
1381 | u16 reg = 0; | |
1382 | int ret; | |
1383 | ||
1384 | ret = _mv88e6xxx_vtu_wait(ds); | |
1385 | if (ret < 0) | |
1386 | return ret; | |
1387 | ||
1388 | if (!entry->valid) | |
1389 | goto loadpurge; | |
1390 | ||
1391 | /* Write port states */ | |
1392 | ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2); | |
1393 | if (ret < 0) | |
1394 | return ret; | |
1395 | ||
1396 | reg = GLOBAL_VTU_VID_VALID; | |
1397 | loadpurge: | |
1398 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg); | |
1399 | if (ret < 0) | |
1400 | return ret; | |
1401 | ||
1402 | reg = entry->sid & GLOBAL_VTU_SID_MASK; | |
1403 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg); | |
1404 | if (ret < 0) | |
1405 | return ret; | |
1406 | ||
1407 | return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE); | |
1408 | } | |
1409 | ||
1410 | static int _mv88e6xxx_vlan_init(struct dsa_switch *ds, u16 vid, | |
1411 | struct mv88e6xxx_vtu_stu_entry *entry) | |
1412 | { | |
1413 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1414 | struct mv88e6xxx_vtu_stu_entry vlan = { | |
1415 | .valid = true, | |
1416 | .vid = vid, | |
f02bdffc | 1417 | .fid = vid, /* We use one FID per VLAN */ |
0d3b33e6 VD |
1418 | }; |
1419 | int i; | |
1420 | ||
1421 | /* exclude all ports except the CPU */ | |
1422 | for (i = 0; i < ps->num_ports; ++i) | |
1423 | vlan.data[i] = dsa_is_cpu_port(ds, i) ? | |
1424 | GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED : | |
1425 | GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; | |
1426 | ||
1427 | if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) || | |
1428 | mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) { | |
1429 | struct mv88e6xxx_vtu_stu_entry vstp; | |
1430 | int err; | |
1431 | ||
1432 | /* Adding a VTU entry requires a valid STU entry. As VSTP is not | |
1433 | * implemented, only one STU entry is needed to cover all VTU | |
1434 | * entries. Thus, validate the SID 0. | |
1435 | */ | |
1436 | vlan.sid = 0; | |
1437 | err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp); | |
1438 | if (err) | |
1439 | return err; | |
1440 | ||
1441 | if (vstp.sid != vlan.sid || !vstp.valid) { | |
1442 | memset(&vstp, 0, sizeof(vstp)); | |
1443 | vstp.valid = true; | |
1444 | vstp.sid = vlan.sid; | |
1445 | ||
1446 | err = _mv88e6xxx_stu_loadpurge(ds, &vstp); | |
1447 | if (err) | |
1448 | return err; | |
1449 | } | |
1450 | ||
7c400018 VD |
1451 | /* Clear all MAC addresses from the new database */ |
1452 | err = _mv88e6xxx_atu_flush(ds, vlan.fid, true); | |
0d3b33e6 VD |
1453 | if (err) |
1454 | return err; | |
0d3b33e6 VD |
1455 | } |
1456 | ||
1457 | *entry = vlan; | |
1458 | return 0; | |
1459 | } | |
1460 | ||
76e398a6 VD |
1461 | int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, |
1462 | const struct switchdev_obj_port_vlan *vlan, | |
1463 | struct switchdev_trans *trans) | |
1464 | { | |
1465 | /* We don't need any dynamic resource from the kernel (yet), | |
1466 | * so skip the prepare phase. | |
1467 | */ | |
1468 | return 0; | |
1469 | } | |
1470 | ||
1471 | static int _mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid, | |
1472 | bool untagged) | |
0d3b33e6 | 1473 | { |
0d3b33e6 VD |
1474 | struct mv88e6xxx_vtu_stu_entry vlan; |
1475 | int err; | |
1476 | ||
36d04ba1 VD |
1477 | err = _mv88e6xxx_vtu_vid_write(ds, vid - 1); |
1478 | if (err) | |
76e398a6 | 1479 | return err; |
36d04ba1 VD |
1480 | |
1481 | err = _mv88e6xxx_vtu_getnext(ds, &vlan); | |
0d3b33e6 | 1482 | if (err) |
76e398a6 | 1483 | return err; |
0d3b33e6 VD |
1484 | |
1485 | if (vlan.vid != vid || !vlan.valid) { | |
1486 | err = _mv88e6xxx_vlan_init(ds, vid, &vlan); | |
1487 | if (err) | |
76e398a6 | 1488 | return err; |
0d3b33e6 VD |
1489 | } |
1490 | ||
1491 | vlan.data[port] = untagged ? | |
1492 | GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED : | |
1493 | GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED; | |
1494 | ||
76e398a6 VD |
1495 | return _mv88e6xxx_vtu_loadpurge(ds, &vlan); |
1496 | } | |
1497 | ||
1498 | int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, | |
1499 | const struct switchdev_obj_port_vlan *vlan, | |
1500 | struct switchdev_trans *trans) | |
1501 | { | |
1502 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1503 | bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; | |
1504 | bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; | |
1505 | u16 vid; | |
1506 | int err = 0; | |
1507 | ||
1508 | mutex_lock(&ps->smi_mutex); | |
1509 | ||
1510 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { | |
1511 | err = _mv88e6xxx_port_vlan_add(ds, port, vid, untagged); | |
1512 | if (err) | |
1513 | goto unlock; | |
1514 | } | |
1515 | ||
1516 | /* no PVID with ranges, otherwise it's a bug */ | |
1517 | if (pvid) | |
1518 | err = _mv88e6xxx_port_pvid_set(ds, port, vid); | |
0d3b33e6 VD |
1519 | unlock: |
1520 | mutex_unlock(&ps->smi_mutex); | |
1521 | ||
1522 | return err; | |
1523 | } | |
1524 | ||
76e398a6 | 1525 | static int _mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid) |
7dad08d7 VD |
1526 | { |
1527 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1528 | struct mv88e6xxx_vtu_stu_entry vlan; | |
7dad08d7 VD |
1529 | int i, err; |
1530 | ||
36d04ba1 VD |
1531 | err = _mv88e6xxx_vtu_vid_write(ds, vid - 1); |
1532 | if (err) | |
76e398a6 | 1533 | return err; |
36d04ba1 VD |
1534 | |
1535 | err = _mv88e6xxx_vtu_getnext(ds, &vlan); | |
7dad08d7 | 1536 | if (err) |
76e398a6 | 1537 | return err; |
7dad08d7 VD |
1538 | |
1539 | if (vlan.vid != vid || !vlan.valid || | |
76e398a6 VD |
1540 | vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) |
1541 | return -ENOENT; | |
7dad08d7 VD |
1542 | |
1543 | vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; | |
1544 | ||
1545 | /* keep the VLAN unless all ports are excluded */ | |
f02bdffc | 1546 | vlan.valid = false; |
7dad08d7 VD |
1547 | for (i = 0; i < ps->num_ports; ++i) { |
1548 | if (dsa_is_cpu_port(ds, i)) | |
1549 | continue; | |
1550 | ||
1551 | if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) { | |
f02bdffc | 1552 | vlan.valid = true; |
7dad08d7 VD |
1553 | break; |
1554 | } | |
1555 | } | |
1556 | ||
7dad08d7 | 1557 | err = _mv88e6xxx_vtu_loadpurge(ds, &vlan); |
76e398a6 VD |
1558 | if (err) |
1559 | return err; | |
1560 | ||
1561 | return _mv88e6xxx_atu_remove(ds, vlan.fid, port, false); | |
1562 | } | |
1563 | ||
1564 | int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, | |
1565 | const struct switchdev_obj_port_vlan *vlan) | |
1566 | { | |
1567 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1568 | u16 pvid, vid; | |
1569 | int err = 0; | |
1570 | ||
1571 | mutex_lock(&ps->smi_mutex); | |
1572 | ||
1573 | err = _mv88e6xxx_port_pvid_get(ds, port, &pvid); | |
7dad08d7 VD |
1574 | if (err) |
1575 | goto unlock; | |
1576 | ||
76e398a6 VD |
1577 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { |
1578 | err = _mv88e6xxx_port_vlan_del(ds, port, vid); | |
1579 | if (err) | |
1580 | goto unlock; | |
1581 | ||
1582 | if (vid == pvid) { | |
1583 | err = _mv88e6xxx_port_pvid_set(ds, port, 0); | |
1584 | if (err) | |
1585 | goto unlock; | |
1586 | } | |
1587 | } | |
1588 | ||
7dad08d7 VD |
1589 | unlock: |
1590 | mutex_unlock(&ps->smi_mutex); | |
1591 | ||
1592 | return err; | |
1593 | } | |
1594 | ||
b8fee957 VD |
1595 | int mv88e6xxx_vlan_getnext(struct dsa_switch *ds, u16 *vid, |
1596 | unsigned long *ports, unsigned long *untagged) | |
1597 | { | |
1598 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1599 | struct mv88e6xxx_vtu_stu_entry next; | |
1600 | int port; | |
1601 | int err; | |
1602 | ||
1603 | if (*vid == 4095) | |
1604 | return -ENOENT; | |
1605 | ||
1606 | mutex_lock(&ps->smi_mutex); | |
36d04ba1 VD |
1607 | err = _mv88e6xxx_vtu_vid_write(ds, *vid); |
1608 | if (err) | |
1609 | goto unlock; | |
1610 | ||
1611 | err = _mv88e6xxx_vtu_getnext(ds, &next); | |
1612 | unlock: | |
b8fee957 VD |
1613 | mutex_unlock(&ps->smi_mutex); |
1614 | ||
1615 | if (err) | |
1616 | return err; | |
1617 | ||
1618 | if (!next.valid) | |
1619 | return -ENOENT; | |
1620 | ||
1621 | *vid = next.vid; | |
1622 | ||
1623 | for (port = 0; port < ps->num_ports; ++port) { | |
1624 | clear_bit(port, ports); | |
1625 | clear_bit(port, untagged); | |
1626 | ||
1627 | if (dsa_is_cpu_port(ds, port)) | |
1628 | continue; | |
1629 | ||
1630 | if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED || | |
1631 | next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED) | |
1632 | set_bit(port, ports); | |
1633 | ||
1634 | if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED) | |
1635 | set_bit(port, untagged); | |
1636 | } | |
1637 | ||
1638 | return 0; | |
1639 | } | |
1640 | ||
c5723ac5 VD |
1641 | static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds, |
1642 | const unsigned char *addr) | |
defb05b9 GR |
1643 | { |
1644 | int i, ret; | |
1645 | ||
1646 | for (i = 0; i < 3; i++) { | |
cca8b133 AL |
1647 | ret = _mv88e6xxx_reg_write( |
1648 | ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i, | |
1649 | (addr[i * 2] << 8) | addr[i * 2 + 1]); | |
defb05b9 GR |
1650 | if (ret < 0) |
1651 | return ret; | |
1652 | } | |
1653 | ||
1654 | return 0; | |
1655 | } | |
1656 | ||
c5723ac5 | 1657 | static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr) |
defb05b9 GR |
1658 | { |
1659 | int i, ret; | |
1660 | ||
1661 | for (i = 0; i < 3; i++) { | |
cca8b133 AL |
1662 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, |
1663 | GLOBAL_ATU_MAC_01 + i); | |
defb05b9 GR |
1664 | if (ret < 0) |
1665 | return ret; | |
1666 | addr[i * 2] = ret >> 8; | |
1667 | addr[i * 2 + 1] = ret & 0xff; | |
1668 | } | |
1669 | ||
1670 | return 0; | |
1671 | } | |
1672 | ||
fd231c82 VD |
1673 | static int _mv88e6xxx_atu_load(struct dsa_switch *ds, |
1674 | struct mv88e6xxx_atu_entry *entry) | |
defb05b9 | 1675 | { |
6630e236 VD |
1676 | int ret; |
1677 | ||
defb05b9 GR |
1678 | ret = _mv88e6xxx_atu_wait(ds); |
1679 | if (ret < 0) | |
1680 | return ret; | |
1681 | ||
fd231c82 | 1682 | ret = _mv88e6xxx_atu_mac_write(ds, entry->mac); |
defb05b9 GR |
1683 | if (ret < 0) |
1684 | return ret; | |
1685 | ||
37705b73 | 1686 | ret = _mv88e6xxx_atu_data_write(ds, entry); |
fd231c82 | 1687 | if (ret < 0) |
87820510 VD |
1688 | return ret; |
1689 | ||
70cc99d1 VD |
1690 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, entry->fid); |
1691 | if (ret < 0) | |
1692 | return ret; | |
1693 | ||
1694 | return _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_LOAD_DB); | |
fd231c82 | 1695 | } |
87820510 | 1696 | |
fd231c82 VD |
1697 | static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port, |
1698 | const unsigned char *addr, u16 vid, | |
1699 | u8 state) | |
1700 | { | |
1701 | struct mv88e6xxx_atu_entry entry = { 0 }; | |
fd231c82 | 1702 | |
f02bdffc | 1703 | entry.fid = vid; /* We use one FID per VLAN */ |
fd231c82 VD |
1704 | entry.state = state; |
1705 | ether_addr_copy(entry.mac, addr); | |
1706 | if (state != GLOBAL_ATU_DATA_STATE_UNUSED) { | |
1707 | entry.trunk = false; | |
1708 | entry.portv_trunkid = BIT(port); | |
1709 | } | |
1710 | ||
1711 | return _mv88e6xxx_atu_load(ds, &entry); | |
87820510 VD |
1712 | } |
1713 | ||
146a3206 VD |
1714 | int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, |
1715 | const struct switchdev_obj_port_fdb *fdb, | |
1716 | struct switchdev_trans *trans) | |
1717 | { | |
f02bdffc VD |
1718 | /* We don't use per-port FDB */ |
1719 | if (fdb->vid == 0) | |
1720 | return -EOPNOTSUPP; | |
1721 | ||
146a3206 VD |
1722 | /* We don't need any dynamic resource from the kernel (yet), |
1723 | * so skip the prepare phase. | |
1724 | */ | |
1725 | return 0; | |
1726 | } | |
1727 | ||
cdf09697 | 1728 | int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, |
1f36faf2 VD |
1729 | const struct switchdev_obj_port_fdb *fdb, |
1730 | struct switchdev_trans *trans) | |
87820510 | 1731 | { |
1f36faf2 | 1732 | int state = is_multicast_ether_addr(fdb->addr) ? |
87820510 VD |
1733 | GLOBAL_ATU_DATA_STATE_MC_STATIC : |
1734 | GLOBAL_ATU_DATA_STATE_UC_STATIC; | |
cdf09697 | 1735 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
87820510 VD |
1736 | int ret; |
1737 | ||
1738 | mutex_lock(&ps->smi_mutex); | |
1f36faf2 | 1739 | ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, state); |
87820510 VD |
1740 | mutex_unlock(&ps->smi_mutex); |
1741 | ||
1742 | return ret; | |
1743 | } | |
1744 | ||
cdf09697 | 1745 | int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, |
8057b3e7 | 1746 | const struct switchdev_obj_port_fdb *fdb) |
87820510 VD |
1747 | { |
1748 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
87820510 VD |
1749 | int ret; |
1750 | ||
1751 | mutex_lock(&ps->smi_mutex); | |
8057b3e7 | 1752 | ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, |
cdf09697 | 1753 | GLOBAL_ATU_DATA_STATE_UNUSED); |
87820510 VD |
1754 | mutex_unlock(&ps->smi_mutex); |
1755 | ||
1756 | return ret; | |
1757 | } | |
1758 | ||
1d194046 | 1759 | static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid, |
1d194046 | 1760 | struct mv88e6xxx_atu_entry *entry) |
6630e236 | 1761 | { |
1d194046 VD |
1762 | struct mv88e6xxx_atu_entry next = { 0 }; |
1763 | int ret; | |
1764 | ||
1765 | next.fid = fid; | |
defb05b9 | 1766 | |
cdf09697 DM |
1767 | ret = _mv88e6xxx_atu_wait(ds); |
1768 | if (ret < 0) | |
1769 | return ret; | |
6630e236 | 1770 | |
70cc99d1 VD |
1771 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid); |
1772 | if (ret < 0) | |
1773 | return ret; | |
1774 | ||
1775 | ret = _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_GET_NEXT_DB); | |
1d194046 VD |
1776 | if (ret < 0) |
1777 | return ret; | |
6630e236 | 1778 | |
1d194046 VD |
1779 | ret = _mv88e6xxx_atu_mac_read(ds, next.mac); |
1780 | if (ret < 0) | |
1781 | return ret; | |
6630e236 | 1782 | |
1d194046 | 1783 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA); |
cdf09697 DM |
1784 | if (ret < 0) |
1785 | return ret; | |
6630e236 | 1786 | |
1d194046 VD |
1787 | next.state = ret & GLOBAL_ATU_DATA_STATE_MASK; |
1788 | if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) { | |
1789 | unsigned int mask, shift; | |
1790 | ||
1791 | if (ret & GLOBAL_ATU_DATA_TRUNK) { | |
1792 | next.trunk = true; | |
1793 | mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; | |
1794 | shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; | |
1795 | } else { | |
1796 | next.trunk = false; | |
1797 | mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; | |
1798 | shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; | |
1799 | } | |
1800 | ||
1801 | next.portv_trunkid = (ret & mask) >> shift; | |
1802 | } | |
cdf09697 | 1803 | |
1d194046 | 1804 | *entry = next; |
cdf09697 DM |
1805 | return 0; |
1806 | } | |
1807 | ||
f33475bd VD |
1808 | int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, |
1809 | struct switchdev_obj_port_fdb *fdb, | |
1810 | int (*cb)(struct switchdev_obj *obj)) | |
1811 | { | |
1812 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1813 | struct mv88e6xxx_vtu_stu_entry vlan = { | |
1814 | .vid = GLOBAL_VTU_VID_MASK, /* all ones */ | |
1815 | }; | |
1816 | int err; | |
1817 | ||
1818 | mutex_lock(&ps->smi_mutex); | |
1819 | ||
1820 | err = _mv88e6xxx_vtu_vid_write(ds, vlan.vid); | |
1821 | if (err) | |
1822 | goto unlock; | |
1823 | ||
1824 | do { | |
1825 | struct mv88e6xxx_atu_entry addr = { | |
1826 | .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, | |
1827 | }; | |
1828 | ||
1829 | err = _mv88e6xxx_vtu_getnext(ds, &vlan); | |
1830 | if (err) | |
1831 | goto unlock; | |
1832 | ||
1833 | if (!vlan.valid) | |
1834 | break; | |
1835 | ||
1836 | err = _mv88e6xxx_atu_mac_write(ds, addr.mac); | |
1837 | if (err) | |
1838 | goto unlock; | |
1839 | ||
1840 | do { | |
1841 | err = _mv88e6xxx_atu_getnext(ds, vlan.fid, &addr); | |
1842 | if (err) | |
1843 | goto unlock; | |
1844 | ||
1845 | if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED) | |
1846 | break; | |
1847 | ||
1848 | if (!addr.trunk && addr.portv_trunkid & BIT(port)) { | |
1849 | bool is_static = addr.state == | |
1850 | (is_multicast_ether_addr(addr.mac) ? | |
1851 | GLOBAL_ATU_DATA_STATE_MC_STATIC : | |
1852 | GLOBAL_ATU_DATA_STATE_UC_STATIC); | |
1853 | ||
1854 | fdb->vid = vlan.vid; | |
1855 | ether_addr_copy(fdb->addr, addr.mac); | |
1856 | fdb->ndm_state = is_static ? NUD_NOARP : | |
1857 | NUD_REACHABLE; | |
1858 | ||
1859 | err = cb(&fdb->obj); | |
1860 | if (err) | |
1861 | goto unlock; | |
1862 | } | |
1863 | } while (!is_broadcast_ether_addr(addr.mac)); | |
1864 | ||
1865 | } while (vlan.vid < GLOBAL_VTU_VID_MASK); | |
1866 | ||
1867 | unlock: | |
1868 | mutex_unlock(&ps->smi_mutex); | |
1869 | ||
1870 | return err; | |
1871 | } | |
1872 | ||
facd95b2 GR |
1873 | static void mv88e6xxx_bridge_work(struct work_struct *work) |
1874 | { | |
1875 | struct mv88e6xxx_priv_state *ps; | |
1876 | struct dsa_switch *ds; | |
1877 | int port; | |
1878 | ||
1879 | ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work); | |
1880 | ds = ((struct dsa_switch *)ps) - 1; | |
1881 | ||
1882 | while (ps->port_state_update_mask) { | |
1883 | port = __ffs(ps->port_state_update_mask); | |
1884 | clear_bit(port, &ps->port_state_update_mask); | |
1885 | mv88e6xxx_set_port_state(ds, port, ps->port_state[port]); | |
1886 | } | |
1887 | } | |
1888 | ||
dbde9e66 | 1889 | static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port) |
d827e88a GR |
1890 | { |
1891 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
f02bdffc | 1892 | int ret; |
54d792f2 | 1893 | u16 reg; |
d827e88a GR |
1894 | |
1895 | mutex_lock(&ps->smi_mutex); | |
1896 | ||
54d792f2 AL |
1897 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || |
1898 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1899 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) || | |
7c3d0d67 | 1900 | mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) { |
54d792f2 AL |
1901 | /* MAC Forcing register: don't force link, speed, |
1902 | * duplex or flow control state to any particular | |
1903 | * values on physical ports, but force the CPU port | |
1904 | * and all DSA ports to their maximum bandwidth and | |
1905 | * full duplex. | |
1906 | */ | |
1907 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL); | |
60045cbf | 1908 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { |
53adc9e8 | 1909 | reg &= ~PORT_PCS_CTRL_UNFORCED; |
54d792f2 AL |
1910 | reg |= PORT_PCS_CTRL_FORCE_LINK | |
1911 | PORT_PCS_CTRL_LINK_UP | | |
1912 | PORT_PCS_CTRL_DUPLEX_FULL | | |
1913 | PORT_PCS_CTRL_FORCE_DUPLEX; | |
1914 | if (mv88e6xxx_6065_family(ds)) | |
1915 | reg |= PORT_PCS_CTRL_100; | |
1916 | else | |
1917 | reg |= PORT_PCS_CTRL_1000; | |
1918 | } else { | |
1919 | reg |= PORT_PCS_CTRL_UNFORCED; | |
1920 | } | |
1921 | ||
1922 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1923 | PORT_PCS_CTRL, reg); | |
1924 | if (ret) | |
1925 | goto abort; | |
1926 | } | |
1927 | ||
1928 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, | |
1929 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN | |
1930 | * tunneling, determine priority by looking at 802.1p and IP | |
1931 | * priority fields (IP prio has precedence), and set STP state | |
1932 | * to Forwarding. | |
1933 | * | |
1934 | * If this is the CPU link, use DSA or EDSA tagging depending | |
1935 | * on which tagging mode was configured. | |
1936 | * | |
1937 | * If this is a link to another switch, use DSA tagging mode. | |
1938 | * | |
1939 | * If this is the upstream port for this switch, enable | |
1940 | * forwarding of unknown unicasts and multicasts. | |
1941 | */ | |
1942 | reg = 0; | |
1943 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1944 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1945 | mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) || | |
7c3d0d67 | 1946 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) |
54d792f2 AL |
1947 | reg = PORT_CONTROL_IGMP_MLD_SNOOP | |
1948 | PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | | |
1949 | PORT_CONTROL_STATE_FORWARDING; | |
1950 | if (dsa_is_cpu_port(ds, port)) { | |
1951 | if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) | |
1952 | reg |= PORT_CONTROL_DSA_TAG; | |
1953 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
7c3d0d67 AK |
1954 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || |
1955 | mv88e6xxx_6320_family(ds)) { | |
54d792f2 AL |
1956 | if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) |
1957 | reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA; | |
1958 | else | |
1959 | reg |= PORT_CONTROL_FRAME_MODE_DSA; | |
c047a1f9 AL |
1960 | reg |= PORT_CONTROL_FORWARD_UNKNOWN | |
1961 | PORT_CONTROL_FORWARD_UNKNOWN_MC; | |
54d792f2 AL |
1962 | } |
1963 | ||
1964 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1965 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1966 | mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) || | |
7c3d0d67 | 1967 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) { |
54d792f2 AL |
1968 | if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) |
1969 | reg |= PORT_CONTROL_EGRESS_ADD_TAG; | |
1970 | } | |
1971 | } | |
6083ce71 AL |
1972 | if (dsa_is_dsa_port(ds, port)) { |
1973 | if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) | |
1974 | reg |= PORT_CONTROL_DSA_TAG; | |
1975 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1976 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1977 | mv88e6xxx_6320_family(ds)) { | |
54d792f2 | 1978 | reg |= PORT_CONTROL_FRAME_MODE_DSA; |
6083ce71 AL |
1979 | } |
1980 | ||
54d792f2 AL |
1981 | if (port == dsa_upstream_port(ds)) |
1982 | reg |= PORT_CONTROL_FORWARD_UNKNOWN | | |
1983 | PORT_CONTROL_FORWARD_UNKNOWN_MC; | |
1984 | } | |
1985 | if (reg) { | |
1986 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1987 | PORT_CONTROL, reg); | |
1988 | if (ret) | |
1989 | goto abort; | |
1990 | } | |
1991 | ||
8efdda4a VD |
1992 | /* Port Control 2: don't force a good FCS, set the maximum frame size to |
1993 | * 10240 bytes, enable secure 802.1q tags, don't discard tagged or | |
1994 | * untagged frames on this port, do a destination address lookup on all | |
1995 | * received packets as usual, disable ARP mirroring and don't send a | |
1996 | * copy of all transmitted/received frames on this port to the CPU. | |
54d792f2 AL |
1997 | */ |
1998 | reg = 0; | |
1999 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
2000 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
7c3d0d67 | 2001 | mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds)) |
54d792f2 AL |
2002 | reg = PORT_CONTROL_2_MAP_DA; |
2003 | ||
2004 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
7c3d0d67 | 2005 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds)) |
54d792f2 AL |
2006 | reg |= PORT_CONTROL_2_JUMBO_10240; |
2007 | ||
2008 | if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) { | |
2009 | /* Set the upstream port this port should use */ | |
2010 | reg |= dsa_upstream_port(ds); | |
2011 | /* enable forwarding of unknown multicast addresses to | |
2012 | * the upstream port | |
2013 | */ | |
2014 | if (port == dsa_upstream_port(ds)) | |
2015 | reg |= PORT_CONTROL_2_FORWARD_UNKNOWN; | |
2016 | } | |
2017 | ||
5fe7f680 | 2018 | reg |= PORT_CONTROL_2_8021Q_SECURE; |
8efdda4a | 2019 | |
54d792f2 AL |
2020 | if (reg) { |
2021 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
2022 | PORT_CONTROL_2, reg); | |
2023 | if (ret) | |
2024 | goto abort; | |
2025 | } | |
2026 | ||
2027 | /* Port Association Vector: when learning source addresses | |
2028 | * of packets, add the address to the address database using | |
2029 | * a port bitmap that has only the bit for this port set and | |
2030 | * the other bits clear. | |
2031 | */ | |
4c7ea3c0 AL |
2032 | reg = 1 << port; |
2033 | /* Disable learning for DSA and CPU ports */ | |
2034 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) | |
2035 | reg = PORT_ASSOC_VECTOR_LOCKED_PORT; | |
2036 | ||
2037 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, reg); | |
54d792f2 AL |
2038 | if (ret) |
2039 | goto abort; | |
2040 | ||
2041 | /* Egress rate control 2: disable egress rate control. */ | |
2042 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2, | |
2043 | 0x0000); | |
2044 | if (ret) | |
2045 | goto abort; | |
2046 | ||
2047 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
7c3d0d67 AK |
2048 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || |
2049 | mv88e6xxx_6320_family(ds)) { | |
54d792f2 AL |
2050 | /* Do not limit the period of time that this port can |
2051 | * be paused for by the remote end or the period of | |
2052 | * time that this port can pause the remote end. | |
2053 | */ | |
2054 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
2055 | PORT_PAUSE_CTRL, 0x0000); | |
2056 | if (ret) | |
2057 | goto abort; | |
2058 | ||
2059 | /* Port ATU control: disable limiting the number of | |
2060 | * address database entries that this port is allowed | |
2061 | * to use. | |
2062 | */ | |
2063 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
2064 | PORT_ATU_CONTROL, 0x0000); | |
2065 | /* Priority Override: disable DA, SA and VTU priority | |
2066 | * override. | |
2067 | */ | |
2068 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
2069 | PORT_PRI_OVERRIDE, 0x0000); | |
2070 | if (ret) | |
2071 | goto abort; | |
2072 | ||
2073 | /* Port Ethertype: use the Ethertype DSA Ethertype | |
2074 | * value. | |
2075 | */ | |
2076 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
2077 | PORT_ETH_TYPE, ETH_P_EDSA); | |
2078 | if (ret) | |
2079 | goto abort; | |
2080 | /* Tag Remap: use an identity 802.1p prio -> switch | |
2081 | * prio mapping. | |
2082 | */ | |
2083 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
2084 | PORT_TAG_REGMAP_0123, 0x3210); | |
2085 | if (ret) | |
2086 | goto abort; | |
2087 | ||
2088 | /* Tag Remap 2: use an identity 802.1p prio -> switch | |
2089 | * prio mapping. | |
2090 | */ | |
2091 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
2092 | PORT_TAG_REGMAP_4567, 0x7654); | |
2093 | if (ret) | |
2094 | goto abort; | |
2095 | } | |
2096 | ||
2097 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
2098 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
7c3d0d67 AK |
2099 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) || |
2100 | mv88e6xxx_6320_family(ds)) { | |
54d792f2 AL |
2101 | /* Rate Control: disable ingress rate limiting. */ |
2102 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
2103 | PORT_RATE_CONTROL, 0x0001); | |
2104 | if (ret) | |
2105 | goto abort; | |
2106 | } | |
2107 | ||
366f0a0f GR |
2108 | /* Port Control 1: disable trunking, disable sending |
2109 | * learning messages to this port. | |
d827e88a | 2110 | */ |
614f03fc | 2111 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000); |
d827e88a GR |
2112 | if (ret) |
2113 | goto abort; | |
2114 | ||
f02bdffc | 2115 | /* Port based VLAN map: do not give each port its own address |
5fe7f680 | 2116 | * database, and allow every port to egress frames on all other ports. |
d827e88a | 2117 | */ |
5fe7f680 | 2118 | reg = BIT(ps->num_ports) - 1; /* all ports */ |
ede8098d | 2119 | ret = _mv88e6xxx_port_vlan_map_set(ds, port, reg & ~port); |
d827e88a GR |
2120 | if (ret) |
2121 | goto abort; | |
2122 | ||
2123 | /* Default VLAN ID and priority: don't set a default VLAN | |
2124 | * ID, and set the default packet priority to zero. | |
2125 | */ | |
47cf1e65 VD |
2126 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN, |
2127 | 0x0000); | |
d827e88a GR |
2128 | abort: |
2129 | mutex_unlock(&ps->smi_mutex); | |
2130 | return ret; | |
2131 | } | |
2132 | ||
dbde9e66 AL |
2133 | int mv88e6xxx_setup_ports(struct dsa_switch *ds) |
2134 | { | |
2135 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2136 | int ret; | |
2137 | int i; | |
2138 | ||
2139 | for (i = 0; i < ps->num_ports; i++) { | |
2140 | ret = mv88e6xxx_setup_port(ds, i); | |
2141 | if (ret < 0) | |
2142 | return ret; | |
2143 | } | |
2144 | return 0; | |
2145 | } | |
2146 | ||
acdaffcc GR |
2147 | int mv88e6xxx_setup_common(struct dsa_switch *ds) |
2148 | { | |
2149 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2150 | ||
2151 | mutex_init(&ps->smi_mutex); | |
acdaffcc | 2152 | |
cca8b133 | 2153 | ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0; |
a8f064c6 | 2154 | |
facd95b2 GR |
2155 | INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work); |
2156 | ||
acdaffcc GR |
2157 | return 0; |
2158 | } | |
2159 | ||
54d792f2 AL |
2160 | int mv88e6xxx_setup_global(struct dsa_switch *ds) |
2161 | { | |
2162 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
24751e29 | 2163 | int ret; |
54d792f2 AL |
2164 | int i; |
2165 | ||
2166 | /* Set the default address aging time to 5 minutes, and | |
2167 | * enable address learn messages to be sent to all message | |
2168 | * ports. | |
2169 | */ | |
2170 | REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL, | |
2171 | 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL); | |
2172 | ||
2173 | /* Configure the IP ToS mapping registers. */ | |
2174 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000); | |
2175 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000); | |
2176 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555); | |
2177 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555); | |
2178 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa); | |
2179 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa); | |
2180 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff); | |
2181 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff); | |
2182 | ||
2183 | /* Configure the IEEE 802.1p priority mapping register. */ | |
2184 | REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41); | |
2185 | ||
2186 | /* Send all frames with destination addresses matching | |
2187 | * 01:80:c2:00:00:0x to the CPU port. | |
2188 | */ | |
2189 | REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff); | |
2190 | ||
2191 | /* Ignore removed tag data on doubly tagged packets, disable | |
2192 | * flow control messages, force flow control priority to the | |
2193 | * highest, and send all special multicast frames to the CPU | |
2194 | * port at the highest priority. | |
2195 | */ | |
2196 | REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, | |
2197 | 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 | | |
2198 | GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI); | |
2199 | ||
2200 | /* Program the DSA routing table. */ | |
2201 | for (i = 0; i < 32; i++) { | |
2202 | int nexthop = 0x1f; | |
2203 | ||
2204 | if (ds->pd->rtable && | |
2205 | i != ds->index && i < ds->dst->pd->nr_chips) | |
2206 | nexthop = ds->pd->rtable[i] & 0x1f; | |
2207 | ||
2208 | REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, | |
2209 | GLOBAL2_DEVICE_MAPPING_UPDATE | | |
2210 | (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | | |
2211 | nexthop); | |
2212 | } | |
2213 | ||
2214 | /* Clear all trunk masks. */ | |
2215 | for (i = 0; i < 8; i++) | |
2216 | REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK, | |
2217 | 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) | | |
2218 | ((1 << ps->num_ports) - 1)); | |
2219 | ||
2220 | /* Clear all trunk mappings. */ | |
2221 | for (i = 0; i < 16; i++) | |
2222 | REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, | |
2223 | GLOBAL2_TRUNK_MAPPING_UPDATE | | |
2224 | (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT)); | |
2225 | ||
2226 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
7c3d0d67 AK |
2227 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || |
2228 | mv88e6xxx_6320_family(ds)) { | |
54d792f2 AL |
2229 | /* Send all frames with destination addresses matching |
2230 | * 01:80:c2:00:00:2x to the CPU port. | |
2231 | */ | |
2232 | REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff); | |
2233 | ||
2234 | /* Initialise cross-chip port VLAN table to reset | |
2235 | * defaults. | |
2236 | */ | |
2237 | REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000); | |
2238 | ||
2239 | /* Clear the priority override table. */ | |
2240 | for (i = 0; i < 16; i++) | |
2241 | REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, | |
2242 | 0x8000 | (i << 8)); | |
2243 | } | |
2244 | ||
2245 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
2246 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
7c3d0d67 AK |
2247 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) || |
2248 | mv88e6xxx_6320_family(ds)) { | |
54d792f2 AL |
2249 | /* Disable ingress rate limiting by resetting all |
2250 | * ingress rate limit registers to their initial | |
2251 | * state. | |
2252 | */ | |
2253 | for (i = 0; i < ps->num_ports; i++) | |
2254 | REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP, | |
2255 | 0x9000 | (i << 8)); | |
2256 | } | |
2257 | ||
db687a56 AL |
2258 | /* Clear the statistics counters for all ports */ |
2259 | REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL); | |
2260 | ||
2261 | /* Wait for the flush to complete. */ | |
24751e29 VD |
2262 | mutex_lock(&ps->smi_mutex); |
2263 | ret = _mv88e6xxx_stats_wait(ds); | |
6b17e864 VD |
2264 | if (ret < 0) |
2265 | goto unlock; | |
2266 | ||
c161d0a5 VD |
2267 | /* Clear all ATU entries */ |
2268 | ret = _mv88e6xxx_atu_flush(ds, 0, true); | |
2269 | if (ret < 0) | |
2270 | goto unlock; | |
2271 | ||
6b17e864 VD |
2272 | /* Clear all the VTU and STU entries */ |
2273 | ret = _mv88e6xxx_vtu_stu_flush(ds); | |
2274 | unlock: | |
24751e29 | 2275 | mutex_unlock(&ps->smi_mutex); |
db687a56 | 2276 | |
24751e29 | 2277 | return ret; |
54d792f2 AL |
2278 | } |
2279 | ||
143a8307 AL |
2280 | int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active) |
2281 | { | |
2282 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2283 | u16 is_reset = (ppu_active ? 0x8800 : 0xc800); | |
2284 | unsigned long timeout; | |
2285 | int ret; | |
2286 | int i; | |
2287 | ||
2288 | /* Set all ports to the disabled state. */ | |
2289 | for (i = 0; i < ps->num_ports; i++) { | |
cca8b133 AL |
2290 | ret = REG_READ(REG_PORT(i), PORT_CONTROL); |
2291 | REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc); | |
143a8307 AL |
2292 | } |
2293 | ||
2294 | /* Wait for transmit queues to drain. */ | |
2295 | usleep_range(2000, 4000); | |
2296 | ||
2297 | /* Reset the switch. Keep the PPU active if requested. The PPU | |
2298 | * needs to be active to support indirect phy register access | |
2299 | * through global registers 0x18 and 0x19. | |
2300 | */ | |
2301 | if (ppu_active) | |
2302 | REG_WRITE(REG_GLOBAL, 0x04, 0xc000); | |
2303 | else | |
2304 | REG_WRITE(REG_GLOBAL, 0x04, 0xc400); | |
2305 | ||
2306 | /* Wait up to one second for reset to complete. */ | |
2307 | timeout = jiffies + 1 * HZ; | |
2308 | while (time_before(jiffies, timeout)) { | |
2309 | ret = REG_READ(REG_GLOBAL, 0x00); | |
2310 | if ((ret & is_reset) == is_reset) | |
2311 | break; | |
2312 | usleep_range(1000, 2000); | |
2313 | } | |
2314 | if (time_after(jiffies, timeout)) | |
2315 | return -ETIMEDOUT; | |
2316 | ||
2317 | return 0; | |
2318 | } | |
2319 | ||
49143585 AL |
2320 | int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg) |
2321 | { | |
2322 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2323 | int ret; | |
2324 | ||
3898c148 | 2325 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2326 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page); |
49143585 AL |
2327 | if (ret < 0) |
2328 | goto error; | |
fd3a0ee4 | 2329 | ret = _mv88e6xxx_phy_read_indirect(ds, port, reg); |
49143585 | 2330 | error: |
fd3a0ee4 | 2331 | _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0); |
3898c148 | 2332 | mutex_unlock(&ps->smi_mutex); |
49143585 AL |
2333 | return ret; |
2334 | } | |
2335 | ||
2336 | int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page, | |
2337 | int reg, int val) | |
2338 | { | |
2339 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2340 | int ret; | |
2341 | ||
3898c148 | 2342 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2343 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page); |
49143585 AL |
2344 | if (ret < 0) |
2345 | goto error; | |
2346 | ||
fd3a0ee4 | 2347 | ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val); |
49143585 | 2348 | error: |
fd3a0ee4 | 2349 | _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0); |
3898c148 | 2350 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
2351 | return ret; |
2352 | } | |
2353 | ||
2354 | static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port) | |
2355 | { | |
2356 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2357 | ||
2358 | if (port >= 0 && port < ps->num_ports) | |
2359 | return port; | |
2360 | return -EINVAL; | |
2361 | } | |
2362 | ||
2363 | int | |
2364 | mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum) | |
2365 | { | |
2366 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2367 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
2368 | int ret; | |
2369 | ||
2370 | if (addr < 0) | |
2371 | return addr; | |
2372 | ||
3898c148 | 2373 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2374 | ret = _mv88e6xxx_phy_read(ds, addr, regnum); |
3898c148 | 2375 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
2376 | return ret; |
2377 | } | |
2378 | ||
2379 | int | |
2380 | mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) | |
2381 | { | |
2382 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2383 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
2384 | int ret; | |
2385 | ||
2386 | if (addr < 0) | |
2387 | return addr; | |
2388 | ||
3898c148 | 2389 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2390 | ret = _mv88e6xxx_phy_write(ds, addr, regnum, val); |
3898c148 | 2391 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
2392 | return ret; |
2393 | } | |
2394 | ||
2395 | int | |
2396 | mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum) | |
2397 | { | |
2398 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2399 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
2400 | int ret; | |
2401 | ||
2402 | if (addr < 0) | |
2403 | return addr; | |
2404 | ||
3898c148 | 2405 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2406 | ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum); |
3898c148 | 2407 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
2408 | return ret; |
2409 | } | |
2410 | ||
2411 | int | |
2412 | mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum, | |
2413 | u16 val) | |
2414 | { | |
2415 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2416 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
2417 | int ret; | |
2418 | ||
2419 | if (addr < 0) | |
2420 | return addr; | |
2421 | ||
3898c148 | 2422 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2423 | ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val); |
3898c148 | 2424 | mutex_unlock(&ps->smi_mutex); |
49143585 AL |
2425 | return ret; |
2426 | } | |
2427 | ||
c22995c5 GR |
2428 | #ifdef CONFIG_NET_DSA_HWMON |
2429 | ||
2430 | static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp) | |
2431 | { | |
2432 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2433 | int ret; | |
2434 | int val; | |
2435 | ||
2436 | *temp = 0; | |
2437 | ||
2438 | mutex_lock(&ps->smi_mutex); | |
2439 | ||
2440 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6); | |
2441 | if (ret < 0) | |
2442 | goto error; | |
2443 | ||
2444 | /* Enable temperature sensor */ | |
2445 | ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a); | |
2446 | if (ret < 0) | |
2447 | goto error; | |
2448 | ||
2449 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5)); | |
2450 | if (ret < 0) | |
2451 | goto error; | |
2452 | ||
2453 | /* Wait for temperature to stabilize */ | |
2454 | usleep_range(10000, 12000); | |
2455 | ||
2456 | val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a); | |
2457 | if (val < 0) { | |
2458 | ret = val; | |
2459 | goto error; | |
2460 | } | |
2461 | ||
2462 | /* Disable temperature sensor */ | |
2463 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5)); | |
2464 | if (ret < 0) | |
2465 | goto error; | |
2466 | ||
2467 | *temp = ((val & 0x1f) - 5) * 5; | |
2468 | ||
2469 | error: | |
2470 | _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0); | |
2471 | mutex_unlock(&ps->smi_mutex); | |
2472 | return ret; | |
2473 | } | |
2474 | ||
2475 | static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp) | |
2476 | { | |
2477 | int phy = mv88e6xxx_6320_family(ds) ? 3 : 0; | |
2478 | int ret; | |
2479 | ||
2480 | *temp = 0; | |
2481 | ||
2482 | ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27); | |
2483 | if (ret < 0) | |
2484 | return ret; | |
2485 | ||
2486 | *temp = (ret & 0xff) - 25; | |
2487 | ||
2488 | return 0; | |
2489 | } | |
2490 | ||
2491 | int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) | |
2492 | { | |
2493 | if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds)) | |
2494 | return mv88e63xx_get_temp(ds, temp); | |
2495 | ||
2496 | return mv88e61xx_get_temp(ds, temp); | |
2497 | } | |
2498 | ||
2499 | int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp) | |
2500 | { | |
2501 | int phy = mv88e6xxx_6320_family(ds) ? 3 : 0; | |
2502 | int ret; | |
2503 | ||
2504 | if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds)) | |
2505 | return -EOPNOTSUPP; | |
2506 | ||
2507 | *temp = 0; | |
2508 | ||
2509 | ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26); | |
2510 | if (ret < 0) | |
2511 | return ret; | |
2512 | ||
2513 | *temp = (((ret >> 8) & 0x1f) * 5) - 25; | |
2514 | ||
2515 | return 0; | |
2516 | } | |
2517 | ||
2518 | int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp) | |
2519 | { | |
2520 | int phy = mv88e6xxx_6320_family(ds) ? 3 : 0; | |
2521 | int ret; | |
2522 | ||
2523 | if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds)) | |
2524 | return -EOPNOTSUPP; | |
2525 | ||
2526 | ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26); | |
2527 | if (ret < 0) | |
2528 | return ret; | |
2529 | temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); | |
2530 | return mv88e6xxx_phy_page_write(ds, phy, 6, 26, | |
2531 | (ret & 0xe0ff) | (temp << 8)); | |
2532 | } | |
2533 | ||
2534 | int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm) | |
2535 | { | |
2536 | int phy = mv88e6xxx_6320_family(ds) ? 3 : 0; | |
2537 | int ret; | |
2538 | ||
2539 | if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds)) | |
2540 | return -EOPNOTSUPP; | |
2541 | ||
2542 | *alarm = false; | |
2543 | ||
2544 | ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26); | |
2545 | if (ret < 0) | |
2546 | return ret; | |
2547 | ||
2548 | *alarm = !!(ret & 0x40); | |
2549 | ||
2550 | return 0; | |
2551 | } | |
2552 | #endif /* CONFIG_NET_DSA_HWMON */ | |
2553 | ||
b9b37713 VD |
2554 | char *mv88e6xxx_lookup_name(struct device *host_dev, int sw_addr, |
2555 | const struct mv88e6xxx_switch_id *table, | |
2556 | unsigned int num) | |
2557 | { | |
2558 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev); | |
2559 | int i, ret; | |
2560 | ||
2561 | if (!bus) | |
2562 | return NULL; | |
2563 | ||
2564 | ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID); | |
2565 | if (ret < 0) | |
2566 | return NULL; | |
2567 | ||
2568 | /* Look up the exact switch ID */ | |
2569 | for (i = 0; i < num; ++i) | |
2570 | if (table[i].id == ret) | |
2571 | return table[i].name; | |
2572 | ||
2573 | /* Look up only the product number */ | |
2574 | for (i = 0; i < num; ++i) { | |
2575 | if (table[i].id == (ret & PORT_SWITCH_ID_PROD_NUM_MASK)) { | |
2576 | dev_warn(host_dev, "unknown revision %d, using base switch 0x%x\n", | |
2577 | ret & PORT_SWITCH_ID_REV_MASK, | |
2578 | ret & PORT_SWITCH_ID_PROD_NUM_MASK); | |
2579 | return table[i].name; | |
2580 | } | |
2581 | } | |
2582 | ||
2583 | return NULL; | |
2584 | } | |
2585 | ||
98e67308 BH |
2586 | static int __init mv88e6xxx_init(void) |
2587 | { | |
2588 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131) | |
2589 | register_switch_driver(&mv88e6131_switch_driver); | |
2590 | #endif | |
2591 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65) | |
2592 | register_switch_driver(&mv88e6123_61_65_switch_driver); | |
42f27253 | 2593 | #endif |
3ad50cca GR |
2594 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352) |
2595 | register_switch_driver(&mv88e6352_switch_driver); | |
2596 | #endif | |
42f27253 AL |
2597 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171) |
2598 | register_switch_driver(&mv88e6171_switch_driver); | |
98e67308 BH |
2599 | #endif |
2600 | return 0; | |
2601 | } | |
2602 | module_init(mv88e6xxx_init); | |
2603 | ||
2604 | static void __exit mv88e6xxx_cleanup(void) | |
2605 | { | |
42f27253 AL |
2606 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171) |
2607 | unregister_switch_driver(&mv88e6171_switch_driver); | |
2608 | #endif | |
4212b543 VD |
2609 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352) |
2610 | unregister_switch_driver(&mv88e6352_switch_driver); | |
2611 | #endif | |
98e67308 BH |
2612 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65) |
2613 | unregister_switch_driver(&mv88e6123_61_65_switch_driver); | |
2614 | #endif | |
2615 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131) | |
2616 | unregister_switch_driver(&mv88e6131_switch_driver); | |
2617 | #endif | |
2618 | } | |
2619 | module_exit(mv88e6xxx_cleanup); | |
3d825ede BH |
2620 | |
2621 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); | |
2622 | MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); | |
2623 | MODULE_LICENSE("GPL"); |