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[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / mv88e6xxx.c
CommitLineData
91da11f8
LB		 1/*
2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
4 *
b8fee957
VD		 5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
7 *
91da11f8
LB		 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
19b2f97e 14#include <linux/delay.h>
defb05b9 15#include <linux/etherdevice.h>
dea87024 16#include <linux/ethtool.h>
facd95b2 17#include <linux/if_bridge.h>
19b2f97e 18#include <linux/jiffies.h>
91da11f8 19#include <linux/list.h>
2bbba277 20#include <linux/module.h>
91da11f8 21#include <linux/netdevice.h>
c8c1b39a 22#include <linux/gpio/consumer.h>
91da11f8 23#include <linux/phy.h>
c8f0b869 24#include <net/dsa.h>
1f36faf2 25#include <net/switchdev.h>
91da11f8
LB		 26#include "mv88e6xxx.h"
27
3996a4ff
VD		 28static void assert_smi_lock(struct dsa_switch *ds)
29{
30 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
31
32 if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
33 dev_err(ds->master_dev, "SMI lock not held!\n");
34 dump_stack();
35 }
36}
37
3675c8d7 38/* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
91da11f8
LB		 39 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
40 * will be directly accessible on some {device address,register address}
41 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
42 * will only respond to SMI transactions to that specific address, and
43 * an indirect addressing mechanism needs to be used to access its
44 * registers.
45 */
46static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
47{
48 int ret;
49 int i;
50
51 for (i = 0; i < 16; i++) {
6e899e6c 52 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
91da11f8
LB		 53 if (ret < 0)
54 return ret;
55
cca8b133 56 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 57 return 0;
58 }
59
60 return -ETIMEDOUT;
61}
62
b9b37713
VD		 63static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
64 int reg)
91da11f8
LB		 65{
66 int ret;
67
68 if (sw_addr == 0)
6e899e6c 69 return mdiobus_read_nested(bus, addr, reg);
91da11f8 70
3675c8d7 71 /* Wait for the bus to become free. */
91da11f8
LB		 72 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
73 if (ret < 0)
74 return ret;
75
3675c8d7 76 /* Transmit the read command. */
6e899e6c
NA		 77 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
78 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 79 if (ret < 0)
80 return ret;
81
3675c8d7 82 /* Wait for the read command to complete. */
91da11f8
LB		 83 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
84 if (ret < 0)
85 return ret;
86
3675c8d7 87 /* Read the data. */
6e899e6c 88 ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
91da11f8
LB		 89 if (ret < 0)
90 return ret;
91
92 return ret & 0xffff;
93}
94
8d6d09e7 95static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
91da11f8 96{
b184e497 97 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
91da11f8
LB		 98 int ret;
99
3996a4ff
VD		 100 assert_smi_lock(ds);
101
b184e497
GR		 102 if (bus == NULL)
103 return -EINVAL;
104
b184e497 105 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
bb92ea5e
VD		 106 if (ret < 0)
107 return ret;
108
109 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
110 addr, reg, ret);
111
91da11f8
LB		 112 return ret;
113}
114
8d6d09e7
GR		 115int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
116{
117 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
118 int ret;
119
120 mutex_lock(&ps->smi_mutex);
121 ret = _mv88e6xxx_reg_read(ds, addr, reg);
122 mutex_unlock(&ps->smi_mutex);
123
124 return ret;
125}
126
b9b37713
VD		 127static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
128 int reg, u16 val)
91da11f8
LB		 129{
130 int ret;
131
132 if (sw_addr == 0)
6e899e6c 133 return mdiobus_write_nested(bus, addr, reg, val);
91da11f8 134
3675c8d7 135 /* Wait for the bus to become free. */
91da11f8
LB		 136 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
137 if (ret < 0)
138 return ret;
139
3675c8d7 140 /* Transmit the data to write. */
6e899e6c 141 ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
91da11f8
LB		 142 if (ret < 0)
143 return ret;
144
3675c8d7 145 /* Transmit the write command. */
6e899e6c
NA		 146 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
147 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 148 if (ret < 0)
149 return ret;
150
3675c8d7 151 /* Wait for the write command to complete. */
91da11f8
LB		 152 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
153 if (ret < 0)
154 return ret;
155
156 return 0;
157}
158
8d6d09e7
GR		 159static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
160 u16 val)
91da11f8 161{
b184e497 162 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
91da11f8 163
3996a4ff
VD		 164 assert_smi_lock(ds);
165
b184e497
GR		 166 if (bus == NULL)
167 return -EINVAL;
168
bb92ea5e
VD		 169 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
170 addr, reg, val);
171
8d6d09e7
GR		 172 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
173}
174
175int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
176{
177 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
178 int ret;
179
91da11f8 180 mutex_lock(&ps->smi_mutex);
8d6d09e7 181 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
91da11f8
LB		 182 mutex_unlock(&ps->smi_mutex);
183
184 return ret;
185}
186
2e5f0320
LB		 187int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
188{
cca8b133
AL		 189 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
190 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
191 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2e5f0320
LB		 192
193 return 0;
194}
195
91da11f8
LB		 196int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
197{
198 int i;
199 int ret;
200
201 for (i = 0; i < 6; i++) {
202 int j;
203
3675c8d7 204 /* Write the MAC address byte. */
cca8b133
AL		 205 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
206 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
91da11f8 207
3675c8d7 208 /* Wait for the write to complete. */
91da11f8 209 for (j = 0; j < 16; j++) {
cca8b133
AL		 210 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
211 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
91da11f8
LB		 212 break;
213 }
214 if (j == 16)
215 return -ETIMEDOUT;
216 }
217
218 return 0;
219}
220
fd3a0ee4 221static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
91da11f8
LB		 222{
223 if (addr >= 0)
3898c148 224 return _mv88e6xxx_reg_read(ds, addr, regnum);
91da11f8
LB		 225 return 0xffff;
226}
227
fd3a0ee4
AL		 228static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
229 u16 val)
91da11f8
LB		 230{
231 if (addr >= 0)
3898c148 232 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
91da11f8
LB		 233 return 0;
234}
235
2e5f0320
LB		 236#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
237static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
238{
239 int ret;
19b2f97e 240 unsigned long timeout;
2e5f0320 241
cca8b133
AL		 242 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
243 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
244 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
2e5f0320 245
19b2f97e
BG		 246 timeout = jiffies + 1 * HZ;
247 while (time_before(jiffies, timeout)) {
cca8b133 248 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
19b2f97e 249 usleep_range(1000, 2000);
cca8b133
AL		 250 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
251 GLOBAL_STATUS_PPU_POLLING)
85686581 252 return 0;
2e5f0320
LB		 253 }
254
255 return -ETIMEDOUT;
256}
257
258static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
259{
260 int ret;
19b2f97e 261 unsigned long timeout;
2e5f0320 262
cca8b133
AL		 263 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
264 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
2e5f0320 265
19b2f97e
BG		 266 timeout = jiffies + 1 * HZ;
267 while (time_before(jiffies, timeout)) {
cca8b133 268 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
19b2f97e 269 usleep_range(1000, 2000);
cca8b133
AL		 270 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
271 GLOBAL_STATUS_PPU_POLLING)
85686581 272 return 0;
2e5f0320
LB		 273 }
274
275 return -ETIMEDOUT;
276}
277
278static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
279{
280 struct mv88e6xxx_priv_state *ps;
281
282 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
283 if (mutex_trylock(&ps->ppu_mutex)) {
85686581 284 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
2e5f0320 285
85686581
BG		 286 if (mv88e6xxx_ppu_enable(ds) == 0)
287 ps->ppu_disabled = 0;
288 mutex_unlock(&ps->ppu_mutex);
2e5f0320
LB		 289 }
290}
291
292static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
293{
294 struct mv88e6xxx_priv_state *ps = (void *)_ps;
295
296 schedule_work(&ps->ppu_work);
297}
298
299static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
300{
a22adce5 301 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320
LB		 302 int ret;
303
304 mutex_lock(&ps->ppu_mutex);
305
3675c8d7 306 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 307 * we can access the PHY registers. If it was already
308 * disabled, cancel the timer that is going to re-enable
309 * it.
310 */
311 if (!ps->ppu_disabled) {
85686581
BG		 312 ret = mv88e6xxx_ppu_disable(ds);
313 if (ret < 0) {
314 mutex_unlock(&ps->ppu_mutex);
315 return ret;
316 }
317 ps->ppu_disabled = 1;
2e5f0320 318 } else {
85686581
BG		 319 del_timer(&ps->ppu_timer);
320 ret = 0;
2e5f0320
LB		 321 }
322
323 return ret;
324}
325
326static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
327{
a22adce5 328 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320 329
3675c8d7 330 /* Schedule a timer to re-enable the PHY polling unit. */
2e5f0320
LB		 331 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
332 mutex_unlock(&ps->ppu_mutex);
333}
334
335void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
336{
a22adce5 337 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320
LB		 338
339 mutex_init(&ps->ppu_mutex);
340 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
341 init_timer(&ps->ppu_timer);
342 ps->ppu_timer.data = (unsigned long)ps;
343 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
344}
345
346int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
347{
348 int ret;
349
350 ret = mv88e6xxx_ppu_access_get(ds);
351 if (ret >= 0) {
85686581
BG		 352 ret = mv88e6xxx_reg_read(ds, addr, regnum);
353 mv88e6xxx_ppu_access_put(ds);
2e5f0320
LB		 354 }
355
356 return ret;
357}
358
359int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
360 int regnum, u16 val)
361{
362 int ret;
363
364 ret = mv88e6xxx_ppu_access_get(ds);
365 if (ret >= 0) {
85686581
BG		 366 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
367 mv88e6xxx_ppu_access_put(ds);
2e5f0320
LB		 368 }
369
370 return ret;
371}
372#endif
373
54d792f2
AL		 374static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
375{
376 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
377
378 switch (ps->id) {
379 case PORT_SWITCH_ID_6031:
380 case PORT_SWITCH_ID_6061:
381 case PORT_SWITCH_ID_6035:
382 case PORT_SWITCH_ID_6065:
383 return true;
384 }
385 return false;
386}
387
388static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
389{
390 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
391
392 switch (ps->id) {
393 case PORT_SWITCH_ID_6092:
394 case PORT_SWITCH_ID_6095:
395 return true;
396 }
397 return false;
398}
399
400static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
401{
402 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
403
404 switch (ps->id) {
405 case PORT_SWITCH_ID_6046:
406 case PORT_SWITCH_ID_6085:
407 case PORT_SWITCH_ID_6096:
408 case PORT_SWITCH_ID_6097:
409 return true;
410 }
411 return false;
412}
413
414static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
415{
416 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
417
418 switch (ps->id) {
419 case PORT_SWITCH_ID_6123:
420 case PORT_SWITCH_ID_6161:
421 case PORT_SWITCH_ID_6165:
422 return true;
423 }
424 return false;
425}
426
427static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
428{
429 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
430
431 switch (ps->id) {
432 case PORT_SWITCH_ID_6121:
433 case PORT_SWITCH_ID_6122:
434 case PORT_SWITCH_ID_6152:
435 case PORT_SWITCH_ID_6155:
436 case PORT_SWITCH_ID_6182:
437 case PORT_SWITCH_ID_6185:
438 case PORT_SWITCH_ID_6108:
439 case PORT_SWITCH_ID_6131:
440 return true;
441 }
442 return false;
443}
444
c22995c5 445static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
7c3d0d67
AK		 446{
447 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
448
449 switch (ps->id) {
450 case PORT_SWITCH_ID_6320:
451 case PORT_SWITCH_ID_6321:
452 return true;
453 }
454 return false;
455}
456
54d792f2
AL		 457static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
458{
459 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
460
461 switch (ps->id) {
462 case PORT_SWITCH_ID_6171:
463 case PORT_SWITCH_ID_6175:
464 case PORT_SWITCH_ID_6350:
465 case PORT_SWITCH_ID_6351:
466 return true;
467 }
468 return false;
469}
470
f3a8b6b6
AL		 471static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
472{
473 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
474
475 switch (ps->id) {
f3a8b6b6
AL		 476 case PORT_SWITCH_ID_6172:
477 case PORT_SWITCH_ID_6176:
54d792f2
AL		 478 case PORT_SWITCH_ID_6240:
479 case PORT_SWITCH_ID_6352:
f3a8b6b6
AL		 480 return true;
481 }
482 return false;
483}
484
f74df0be
VD		 485static unsigned int mv88e6xxx_num_databases(struct dsa_switch *ds)
486{
487 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
488
489 /* The following devices have 4-bit identifiers for 16 databases */
490 if (ps->id == PORT_SWITCH_ID_6061)
491 return 16;
492
493 /* The following devices have 6-bit identifiers for 64 databases */
494 if (ps->id == PORT_SWITCH_ID_6065)
495 return 64;
496
497 /* The following devices have 8-bit identifiers for 256 databases */
498 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
499 return 256;
500
501 /* The following devices have 12-bit identifiers for 4096 databases */
502 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
503 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds))
504 return 4096;
505
506 return 0;
507}
508
b426e5f7
VD		 509static bool mv88e6xxx_has_fid_reg(struct dsa_switch *ds)
510{
511 /* Does the device have dedicated FID registers for ATU and VTU ops? */
512 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
513 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds))
514 return true;
515
516 return false;
517}
518
2e7bd5ef
VD		 519static bool mv88e6xxx_has_stu(struct dsa_switch *ds)
520{
521 /* Does the device have STU and dedicated SID registers for VTU ops? */
522 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
523 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds))
524 return true;
525
526 return false;
527}
528
dea87024
AL		 529/* We expect the switch to perform auto negotiation if there is a real
530 * phy. However, in the case of a fixed link phy, we force the port
531 * settings from the fixed link settings.
532 */
533void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
534 struct phy_device *phydev)
535{
536 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
49052871
AL		 537 u32 reg;
538 int ret;
dea87024
AL		 539
540 if (!phy_is_pseudo_fixed_link(phydev))
541 return;
542
543 mutex_lock(&ps->smi_mutex);
544
545 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
546 if (ret < 0)
547 goto out;
548
549 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
550 PORT_PCS_CTRL_FORCE_LINK |
551 PORT_PCS_CTRL_DUPLEX_FULL |
552 PORT_PCS_CTRL_FORCE_DUPLEX |
553 PORT_PCS_CTRL_UNFORCED);
554
555 reg |= PORT_PCS_CTRL_FORCE_LINK;
556 if (phydev->link)
557 reg |= PORT_PCS_CTRL_LINK_UP;
558
559 if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100)
560 goto out;
561
562 switch (phydev->speed) {
563 case SPEED_1000:
564 reg |= PORT_PCS_CTRL_1000;
565 break;
566 case SPEED_100:
567 reg |= PORT_PCS_CTRL_100;
568 break;
569 case SPEED_10:
570 reg |= PORT_PCS_CTRL_10;
571 break;
572 default:
573 pr_info("Unknown speed");
574 goto out;
575 }
576
577 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
578 if (phydev->duplex == DUPLEX_FULL)
579 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
580
e7e72ac0
AL		 581 if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
582 (port >= ps->num_ports - 2)) {
583 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
584 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
585 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
586 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
587 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
588 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
589 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
590 }
dea87024
AL		 591 _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
592
593out:
594 mutex_unlock(&ps->smi_mutex);
595}
596
31888234 597static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
91da11f8
LB		 598{
599 int ret;
600 int i;
601
602 for (i = 0; i < 10; i++) {
31888234 603 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
cca8b133 604 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 605 return 0;
606 }
607
608 return -ETIMEDOUT;
609}
610
31888234 611static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
91da11f8
LB		 612{
613 int ret;
614
7c3d0d67 615 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
f3a8b6b6
AL		 616 port = (port + 1) << 5;
617
3675c8d7 618 /* Snapshot the hardware statistics counters for this port. */
31888234
AL		 619 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
620 GLOBAL_STATS_OP_CAPTURE_PORT |
621 GLOBAL_STATS_OP_HIST_RX_TX | port);
622 if (ret < 0)
623 return ret;
91da11f8 624
3675c8d7 625 /* Wait for the snapshotting to complete. */
31888234 626 ret = _mv88e6xxx_stats_wait(ds);
91da11f8
LB		 627 if (ret < 0)
628 return ret;
629
630 return 0;
631}
632
31888234 633static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
91da11f8
LB		 634{
635 u32 _val;
636 int ret;
637
638 *val = 0;
639
31888234
AL		 640 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
641 GLOBAL_STATS_OP_READ_CAPTURED |
642 GLOBAL_STATS_OP_HIST_RX_TX | stat);
91da11f8
LB		 643 if (ret < 0)
644 return;
645
31888234 646 ret = _mv88e6xxx_stats_wait(ds);
91da11f8
LB		 647 if (ret < 0)
648 return;
649
31888234 650 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
91da11f8
LB		 651 if (ret < 0)
652 return;
653
654 _val = ret << 16;
655
31888234 656 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
91da11f8
LB		 657 if (ret < 0)
658 return;
659
660 *val = _val | ret;
661}
662
e413e7e1 663static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 664 { "in_good_octets", 8, 0x00, BANK0, },
665 { "in_bad_octets", 4, 0x02, BANK0, },
666 { "in_unicast", 4, 0x04, BANK0, },
667 { "in_broadcasts", 4, 0x06, BANK0, },
668 { "in_multicasts", 4, 0x07, BANK0, },
669 { "in_pause", 4, 0x16, BANK0, },
670 { "in_undersize", 4, 0x18, BANK0, },
671 { "in_fragments", 4, 0x19, BANK0, },
672 { "in_oversize", 4, 0x1a, BANK0, },
673 { "in_jabber", 4, 0x1b, BANK0, },
674 { "in_rx_error", 4, 0x1c, BANK0, },
675 { "in_fcs_error", 4, 0x1d, BANK0, },
676 { "out_octets", 8, 0x0e, BANK0, },
677 { "out_unicast", 4, 0x10, BANK0, },
678 { "out_broadcasts", 4, 0x13, BANK0, },
679 { "out_multicasts", 4, 0x12, BANK0, },
680 { "out_pause", 4, 0x15, BANK0, },
681 { "excessive", 4, 0x11, BANK0, },
682 { "collisions", 4, 0x1e, BANK0, },
683 { "deferred", 4, 0x05, BANK0, },
684 { "single", 4, 0x14, BANK0, },
685 { "multiple", 4, 0x17, BANK0, },
686 { "out_fcs_error", 4, 0x03, BANK0, },
687 { "late", 4, 0x1f, BANK0, },
688 { "hist_64bytes", 4, 0x08, BANK0, },
689 { "hist_65_127bytes", 4, 0x09, BANK0, },
690 { "hist_128_255bytes", 4, 0x0a, BANK0, },
691 { "hist_256_511bytes", 4, 0x0b, BANK0, },
692 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
693 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
694 { "sw_in_discards", 4, 0x10, PORT, },
695 { "sw_in_filtered", 2, 0x12, PORT, },
696 { "sw_out_filtered", 2, 0x13, PORT, },
697 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
698 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
699 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
700 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
701 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
702 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
703 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
704 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
705 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
706 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
707 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
708 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
709 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
710 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
711 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
712 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
713 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
714 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
715 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
716 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
717 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
718 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
719 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
720 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
721 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
722 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 723};
724
f5e2ed02
AL		 725static bool mv88e6xxx_has_stat(struct dsa_switch *ds,
726 struct mv88e6xxx_hw_stat *stat)
e413e7e1 727{
f5e2ed02
AL		 728 switch (stat->type) {
729 case BANK0:
e413e7e1 730 return true;
f5e2ed02
AL		 731 case BANK1:
732 return mv88e6xxx_6320_family(ds);
733 case PORT:
734 return mv88e6xxx_6095_family(ds) ||
735 mv88e6xxx_6185_family(ds) ||
736 mv88e6xxx_6097_family(ds) ||
737 mv88e6xxx_6165_family(ds) ||
738 mv88e6xxx_6351_family(ds) ||
739 mv88e6xxx_6352_family(ds);
91da11f8 740 }
f5e2ed02 741 return false;
91da11f8
LB		 742}
743
80c4627b 744static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
f5e2ed02 745 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 746 int port)
747{
80c4627b
AL		 748 u32 low;
749 u32 high = 0;
750 int ret;
751 u64 value;
752
f5e2ed02
AL		 753 switch (s->type) {
754 case PORT:
755 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), s->reg);
80c4627b
AL		 756 if (ret < 0)
757 return UINT64_MAX;
758
759 low = ret;
760 if (s->sizeof_stat == 4) {
761 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
f5e2ed02 762 s->reg + 1);
80c4627b
AL		 763 if (ret < 0)
764 return UINT64_MAX;
765 high = ret;
766 }
f5e2ed02
AL		 767 break;
768 case BANK0:
769 case BANK1:
80c4627b
AL		 770 _mv88e6xxx_stats_read(ds, s->reg, &low);
771 if (s->sizeof_stat == 8)
772 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
773 }
774 value = (((u64)high) << 16) | low;
775 return value;
776}
777
f5e2ed02 778void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
91da11f8 779{
f5e2ed02
AL		 780 struct mv88e6xxx_hw_stat *stat;
781 int i, j;
91da11f8 782
f5e2ed02
AL		 783 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
784 stat = &mv88e6xxx_hw_stats[i];
785 if (mv88e6xxx_has_stat(ds, stat)) {
786 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
787 ETH_GSTRING_LEN);
788 j++;
789 }
91da11f8 790 }
e413e7e1
AL		 791}
792
793int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
794{
f5e2ed02
AL		 795 struct mv88e6xxx_hw_stat *stat;
796 int i, j;
797
798 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
799 stat = &mv88e6xxx_hw_stats[i];
800 if (mv88e6xxx_has_stat(ds, stat))
801 j++;
802 }
803 return j;
e413e7e1
AL		 804}
805
806void
807mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
808 int port, uint64_t *data)
809{
f5e2ed02
AL		 810 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
811 struct mv88e6xxx_hw_stat *stat;
812 int ret;
813 int i, j;
814
815 mutex_lock(&ps->smi_mutex);
816
817 ret = _mv88e6xxx_stats_snapshot(ds, port);
818 if (ret < 0) {
819 mutex_unlock(&ps->smi_mutex);
820 return;
821 }
822 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
823 stat = &mv88e6xxx_hw_stats[i];
824 if (mv88e6xxx_has_stat(ds, stat)) {
825 data[j] = _mv88e6xxx_get_ethtool_stat(ds, stat, port);
826 j++;
827 }
828 }
829
830 mutex_unlock(&ps->smi_mutex);
e413e7e1
AL		 831}
832
a1ab91f3
GR		 833int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
834{
835 return 32 * sizeof(u16);
836}
837
838void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
839 struct ethtool_regs *regs, void *_p)
840{
841 u16 *p = _p;
842 int i;
843
844 regs->version = 0;
845
846 memset(p, 0xff, 32 * sizeof(u16));
847
848 for (i = 0; i < 32; i++) {
849 int ret;
850
851 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
852 if (ret >= 0)
853 p[i] = ret;
854 }
855}
856
3898c148
AL		 857static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
858 u16 mask)
f3044683
AL		 859{
860 unsigned long timeout = jiffies + HZ / 10;
861
862 while (time_before(jiffies, timeout)) {
863 int ret;
864
3898c148
AL		 865 ret = _mv88e6xxx_reg_read(ds, reg, offset);
866 if (ret < 0)
867 return ret;
f3044683
AL		 868 if (!(ret & mask))
869 return 0;
870
871 usleep_range(1000, 2000);
872 }
873 return -ETIMEDOUT;
874}
875
3898c148
AL		 876static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
877{
878 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
879 int ret;
880
881 mutex_lock(&ps->smi_mutex);
882 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
883 mutex_unlock(&ps->smi_mutex);
884
885 return ret;
886}
887
888static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
f3044683 889{
3898c148
AL		 890 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
891 GLOBAL2_SMI_OP_BUSY);
f3044683
AL		 892}
893
894int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
895{
cca8b133
AL		 896 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
897 GLOBAL2_EEPROM_OP_LOAD);
f3044683
AL		 898}
899
900int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
901{
cca8b133
AL		 902 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
903 GLOBAL2_EEPROM_OP_BUSY);
f3044683
AL		 904}
905
facd95b2
GR		 906static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
907{
cca8b133
AL		 908 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
909 GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 910}
911
fd3a0ee4
AL		 912static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
913 int regnum)
f3044683
AL		 914{
915 int ret;
916
3898c148
AL		 917 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
918 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
919 regnum);
920 if (ret < 0)
921 return ret;
f3044683 922
3898c148 923 ret = _mv88e6xxx_phy_wait(ds);
f3044683
AL		 924 if (ret < 0)
925 return ret;
926
3898c148 927 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
f3044683
AL		 928}
929
fd3a0ee4
AL		 930static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
931 int regnum, u16 val)
f3044683 932{
3898c148
AL		 933 int ret;
934
935 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
936 if (ret < 0)
937 return ret;
f3044683 938
3898c148
AL		 939 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
940 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
941 regnum);
942
943 return _mv88e6xxx_phy_wait(ds);
f3044683
AL		 944}
945
11b3b45d
GR		 946int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
947{
2f40c698 948 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
11b3b45d
GR		 949 int reg;
950
3898c148 951 mutex_lock(&ps->smi_mutex);
2f40c698
AL		 952
953 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
11b3b45d 954 if (reg < 0)
2f40c698 955 goto out;
11b3b45d
GR		 956
957 e->eee_enabled = !!(reg & 0x0200);
958 e->tx_lpi_enabled = !!(reg & 0x0100);
959
3898c148 960 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
11b3b45d 961 if (reg < 0)
2f40c698 962 goto out;
11b3b45d 963
cca8b133 964 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 965 reg = 0;
11b3b45d 966
2f40c698 967out:
3898c148 968 mutex_unlock(&ps->smi_mutex);
2f40c698 969 return reg;
11b3b45d
GR		 970}
971
972int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
973 struct phy_device *phydev, struct ethtool_eee *e)
974{
2f40c698
AL		 975 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
976 int reg;
11b3b45d
GR		 977 int ret;
978
3898c148 979 mutex_lock(&ps->smi_mutex);
11b3b45d 980
2f40c698
AL		 981 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
982 if (ret < 0)
983 goto out;
984
985 reg = ret & ~0x0300;
986 if (e->eee_enabled)
987 reg |= 0x0200;
988 if (e->tx_lpi_enabled)
989 reg |= 0x0100;
990
991 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
992out:
3898c148 993 mutex_unlock(&ps->smi_mutex);
2f40c698
AL		 994
995 return ret;
11b3b45d
GR		 996}
997
b426e5f7 998static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 fid, u16 cmd)
facd95b2
GR		 999{
1000 int ret;
1001
b426e5f7
VD		 1002 if (mv88e6xxx_has_fid_reg(ds)) {
1003 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
1004 if (ret < 0)
1005 return ret;
11ea809f
VD		 1006 } else if (mv88e6xxx_num_databases(ds) == 256) {
1007 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
1008 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_CONTROL);
1009 if (ret < 0)
1010 return ret;
1011
1012 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_CONTROL,
1013 (ret & 0xfff) |
1014 ((fid << 8) & 0xf000));
1015 if (ret < 0)
1016 return ret;
1017
1018 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1019 cmd |= fid & 0xf;
b426e5f7
VD		 1020 }
1021
cca8b133 1022 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
facd95b2
GR		 1023 if (ret < 0)
1024 return ret;
1025
1026 return _mv88e6xxx_atu_wait(ds);
1027}
1028
37705b73
VD		 1029static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds,
1030 struct mv88e6xxx_atu_entry *entry)
1031{
1032 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1033
1034 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1035 unsigned int mask, shift;
1036
1037 if (entry->trunk) {
1038 data |= GLOBAL_ATU_DATA_TRUNK;
1039 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1040 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1041 } else {
1042 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1043 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1044 }
1045
1046 data |= (entry->portv_trunkid << shift) & mask;
1047 }
1048
1049 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1050}
1051
7fb5e755
VD		 1052static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds,
1053 struct mv88e6xxx_atu_entry *entry,
1054 bool static_too)
facd95b2 1055{
7fb5e755
VD		 1056 int op;
1057 int err;
facd95b2 1058
7fb5e755
VD		 1059 err = _mv88e6xxx_atu_wait(ds);
1060 if (err)
1061 return err;
facd95b2 1062
7fb5e755
VD		 1063 err = _mv88e6xxx_atu_data_write(ds, entry);
1064 if (err)
1065 return err;
1066
1067 if (entry->fid) {
7fb5e755
VD		 1068 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1069 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1070 } else {
1071 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1072 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1073 }
1074
b426e5f7 1075 return _mv88e6xxx_atu_cmd(ds, entry->fid, op);
7fb5e755
VD		 1076}
1077
1078static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too)
1079{
1080 struct mv88e6xxx_atu_entry entry = {
1081 .fid = fid,
1082 .state = 0, /* EntryState bits must be 0 */
1083 };
70cc99d1 1084
7fb5e755
VD		 1085 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1086}
1087
9f4d55d2
VD		 1088static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port,
1089 int to_port, bool static_too)
1090{
1091 struct mv88e6xxx_atu_entry entry = {
1092 .trunk = false,
1093 .fid = fid,
1094 };
1095
1096 /* EntryState bits must be 0xF */
1097 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1098
1099 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1100 entry.portv_trunkid = (to_port & 0x0f) << 4;
1101 entry.portv_trunkid |= from_port & 0x0f;
1102
1103 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1104}
1105
1106static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port,
1107 bool static_too)
1108{
1109 /* Destination port 0xF means remove the entries */
1110 return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too);
1111}
1112
2d9deae4
VD		 1113static const char * const mv88e6xxx_port_state_names[] = {
1114 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1115 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1116 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1117 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1118};
1119
1120static int _mv88e6xxx_port_state(struct dsa_switch *ds, int port, u8 state)
facd95b2 1121{
c3ffe6d2 1122 int reg, ret = 0;
facd95b2
GR		 1123 u8 oldstate;
1124
cca8b133 1125 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
2d9deae4
VD		 1126 if (reg < 0)
1127 return reg;
facd95b2 1128
cca8b133 1129 oldstate = reg & PORT_CONTROL_STATE_MASK;
2d9deae4 1130
facd95b2
GR		 1131 if (oldstate != state) {
1132 /* Flush forwarding database if we're moving a port
1133 * from Learning or Forwarding state to Disabled or
1134 * Blocking or Listening state.
1135 */
2d9deae4
VD		 1136 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1137 oldstate == PORT_CONTROL_STATE_FORWARDING)
1138 && (state == PORT_CONTROL_STATE_DISABLED ||
1139 state == PORT_CONTROL_STATE_BLOCKING)) {
2b8157b1 1140 ret = _mv88e6xxx_atu_remove(ds, 0, port, false);
facd95b2 1141 if (ret)
2d9deae4 1142 return ret;
facd95b2 1143 }
2d9deae4 1144
cca8b133
AL		 1145 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1146 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1147 reg);
2d9deae4
VD		 1148 if (ret)
1149 return ret;
1150
1151 netdev_dbg(ds->ports[port], "PortState %s (was %s)\n",
1152 mv88e6xxx_port_state_names[state],
1153 mv88e6xxx_port_state_names[oldstate]);
facd95b2
GR		 1154 }
1155
facd95b2
GR		 1156 return ret;
1157}
1158
b7666efe 1159static int _mv88e6xxx_port_based_vlan_map(struct dsa_switch *ds, int port)
facd95b2
GR		 1160{
1161 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
b7666efe 1162 struct net_device *bridge = ps->ports[port].bridge_dev;
ede8098d 1163 const u16 mask = (1 << ps->num_ports) - 1;
b7666efe 1164 u16 output_ports = 0;
ede8098d 1165 int reg;
b7666efe
VD		 1166 int i;
1167
1168 /* allow CPU port or DSA link(s) to send frames to every port */
1169 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1170 output_ports = mask;
1171 } else {
1172 for (i = 0; i < ps->num_ports; ++i) {
1173 /* allow sending frames to every group member */
1174 if (bridge && ps->ports[i].bridge_dev == bridge)
1175 output_ports |= BIT(i);
1176
1177 /* allow sending frames to CPU port and DSA link(s) */
1178 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1179 output_ports |= BIT(i);
1180 }
1181 }
1182
1183 /* prevent frames from going back out of the port they came in on */
1184 output_ports &= ~BIT(port);
facd95b2 1185
ede8098d
VD		 1186 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1187 if (reg < 0)
1188 return reg;
facd95b2 1189
ede8098d
VD		 1190 reg &= ~mask;
1191 reg |= output_ports & mask;
facd95b2 1192
ede8098d 1193 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
facd95b2
GR		 1194}
1195
43c44a9f 1196void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
facd95b2
GR		 1197{
1198 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1199 int stp_state;
1200
1201 switch (state) {
1202 case BR_STATE_DISABLED:
cca8b133 1203 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1204 break;
1205 case BR_STATE_BLOCKING:
1206 case BR_STATE_LISTENING:
cca8b133 1207 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1208 break;
1209 case BR_STATE_LEARNING:
cca8b133 1210 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1211 break;
1212 case BR_STATE_FORWARDING:
1213 default:
cca8b133 1214 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1215 break;
1216 }
1217
43c44a9f 1218 /* mv88e6xxx_port_stp_state_set may be called with softirqs disabled,
facd95b2
GR		 1219 * so we can not update the port state directly but need to schedule it.
1220 */
d715fa64 1221 ps->ports[port].state = stp_state;
2d9deae4 1222 set_bit(port, ps->port_state_update_mask);
facd95b2 1223 schedule_work(&ps->bridge_work);
facd95b2
GR		 1224}
1225
5da96031
VD		 1226static int _mv88e6xxx_port_pvid(struct dsa_switch *ds, int port, u16 *new,
1227 u16 *old)
76e398a6 1228{
5da96031 1229 u16 pvid;
76e398a6
VD		 1230 int ret;
1231
1232 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1233 if (ret < 0)
1234 return ret;
1235
5da96031
VD		 1236 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1237
1238 if (new) {
1239 ret &= ~PORT_DEFAULT_VLAN_MASK;
1240 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1241
1242 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1243 PORT_DEFAULT_VLAN, ret);
1244 if (ret < 0)
1245 return ret;
1246
1247 netdev_dbg(ds->ports[port], "DefaultVID %d (was %d)\n", *new,
1248 pvid);
1249 }
1250
1251 if (old)
1252 *old = pvid;
76e398a6
VD		 1253
1254 return 0;
1255}
1256
5da96031
VD		 1257static int _mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1258{
1259 return _mv88e6xxx_port_pvid(ds, port, NULL, pvid);
1260}
1261
76e398a6 1262static int _mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid)
0d3b33e6 1263{
5da96031 1264 return _mv88e6xxx_port_pvid(ds, port, &pvid, NULL);
0d3b33e6
VD		 1265}
1266
6b17e864
VD		 1267static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1268{
1269 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1270 GLOBAL_VTU_OP_BUSY);
1271}
1272
1273static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1274{
1275 int ret;
1276
1277 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1278 if (ret < 0)
1279 return ret;
1280
1281 return _mv88e6xxx_vtu_wait(ds);
1282}
1283
1284static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1285{
1286 int ret;
1287
1288 ret = _mv88e6xxx_vtu_wait(ds);
1289 if (ret < 0)
1290 return ret;
1291
1292 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1293}
1294
b8fee957
VD		 1295static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds,
1296 struct mv88e6xxx_vtu_stu_entry *entry,
1297 unsigned int nibble_offset)
1298{
1299 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1300 u16 regs[3];
1301 int i;
1302 int ret;
1303
1304 for (i = 0; i < 3; ++i) {
1305 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1306 GLOBAL_VTU_DATA_0_3 + i);
1307 if (ret < 0)
1308 return ret;
1309
1310 regs[i] = ret;
1311 }
1312
1313 for (i = 0; i < ps->num_ports; ++i) {
1314 unsigned int shift = (i % 4) * 4 + nibble_offset;
1315 u16 reg = regs[i / 4];
1316
1317 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1318 }
1319
1320 return 0;
1321}
1322
7dad08d7
VD		 1323static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds,
1324 struct mv88e6xxx_vtu_stu_entry *entry,
1325 unsigned int nibble_offset)
1326{
1327 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1328 u16 regs[3] = { 0 };
1329 int i;
1330 int ret;
1331
1332 for (i = 0; i < ps->num_ports; ++i) {
1333 unsigned int shift = (i % 4) * 4 + nibble_offset;
1334 u8 data = entry->data[i];
1335
1336 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1337 }
1338
1339 for (i = 0; i < 3; ++i) {
1340 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
1341 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1342 if (ret < 0)
1343 return ret;
1344 }
1345
1346 return 0;
1347}
1348
36d04ba1
VD		 1349static int _mv88e6xxx_vtu_vid_write(struct dsa_switch *ds, u16 vid)
1350{
1351 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID,
1352 vid & GLOBAL_VTU_VID_MASK);
1353}
1354
1355static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds,
b8fee957
VD		 1356 struct mv88e6xxx_vtu_stu_entry *entry)
1357{
1358 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1359 int ret;
1360
1361 ret = _mv88e6xxx_vtu_wait(ds);
1362 if (ret < 0)
1363 return ret;
1364
b8fee957
VD		 1365 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT);
1366 if (ret < 0)
1367 return ret;
1368
1369 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1370 if (ret < 0)
1371 return ret;
1372
1373 next.vid = ret & GLOBAL_VTU_VID_MASK;
1374 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1375
1376 if (next.valid) {
1377 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0);
1378 if (ret < 0)
1379 return ret;
1380
b426e5f7 1381 if (mv88e6xxx_has_fid_reg(ds)) {
b8fee957
VD		 1382 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1383 GLOBAL_VTU_FID);
1384 if (ret < 0)
1385 return ret;
1386
1387 next.fid = ret & GLOBAL_VTU_FID_MASK;
11ea809f
VD		 1388 } else if (mv88e6xxx_num_databases(ds) == 256) {
1389 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1390 * VTU DBNum[3:0] are located in VTU Operation 3:0
1391 */
1392 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1393 GLOBAL_VTU_OP);
1394 if (ret < 0)
1395 return ret;
1396
1397 next.fid = (ret & 0xf00) >> 4;
1398 next.fid |= ret & 0xf;
2e7bd5ef 1399 }
b8fee957 1400
2e7bd5ef 1401 if (mv88e6xxx_has_stu(ds)) {
b8fee957
VD		 1402 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1403 GLOBAL_VTU_SID);
1404 if (ret < 0)
1405 return ret;
1406
1407 next.sid = ret & GLOBAL_VTU_SID_MASK;
1408 }
1409 }
1410
1411 *entry = next;
1412 return 0;
1413}
1414
ceff5eff
VD		 1415int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1416 struct switchdev_obj_port_vlan *vlan,
1417 int (*cb)(struct switchdev_obj *obj))
1418{
1419 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1420 struct mv88e6xxx_vtu_stu_entry next;
1421 u16 pvid;
1422 int err;
1423
1424 mutex_lock(&ps->smi_mutex);
1425
1426 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1427 if (err)
1428 goto unlock;
1429
1430 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1431 if (err)
1432 goto unlock;
1433
1434 do {
1435 err = _mv88e6xxx_vtu_getnext(ds, &next);
1436 if (err)
1437 break;
1438
1439 if (!next.valid)
1440 break;
1441
1442 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1443 continue;
1444
1445 /* reinit and dump this VLAN obj */
1446 vlan->vid_begin = vlan->vid_end = next.vid;
1447 vlan->flags = 0;
1448
1449 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1450 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1451
1452 if (next.vid == pvid)
1453 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1454
1455 err = cb(&vlan->obj);
1456 if (err)
1457 break;
1458 } while (next.vid < GLOBAL_VTU_VID_MASK);
1459
1460unlock:
1461 mutex_unlock(&ps->smi_mutex);
1462
1463 return err;
1464}
1465
7dad08d7
VD		 1466static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds,
1467 struct mv88e6xxx_vtu_stu_entry *entry)
1468{
11ea809f 1469 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7
VD		 1470 u16 reg = 0;
1471 int ret;
1472
1473 ret = _mv88e6xxx_vtu_wait(ds);
1474 if (ret < 0)
1475 return ret;
1476
1477 if (!entry->valid)
1478 goto loadpurge;
1479
1480 /* Write port member tags */
1481 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0);
1482 if (ret < 0)
1483 return ret;
1484
2e7bd5ef 1485 if (mv88e6xxx_has_stu(ds)) {
7dad08d7
VD		 1486 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1487 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1488 if (ret < 0)
1489 return ret;
b426e5f7 1490 }
7dad08d7 1491
b426e5f7 1492 if (mv88e6xxx_has_fid_reg(ds)) {
7dad08d7
VD		 1493 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1494 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1495 if (ret < 0)
1496 return ret;
11ea809f
VD		 1497 } else if (mv88e6xxx_num_databases(ds) == 256) {
1498 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1499 * VTU DBNum[3:0] are located in VTU Operation 3:0
1500 */
1501 op |= (entry->fid & 0xf0) << 8;
1502 op |= entry->fid & 0xf;
7dad08d7
VD		 1503 }
1504
1505 reg = GLOBAL_VTU_VID_VALID;
1506loadpurge:
1507 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1508 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1509 if (ret < 0)
1510 return ret;
1511
11ea809f 1512 return _mv88e6xxx_vtu_cmd(ds, op);
7dad08d7
VD		 1513}
1514
0d3b33e6
VD		 1515static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid,
1516 struct mv88e6xxx_vtu_stu_entry *entry)
1517{
1518 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1519 int ret;
1520
1521 ret = _mv88e6xxx_vtu_wait(ds);
1522 if (ret < 0)
1523 return ret;
1524
1525 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID,
1526 sid & GLOBAL_VTU_SID_MASK);
1527 if (ret < 0)
1528 return ret;
1529
1530 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT);
1531 if (ret < 0)
1532 return ret;
1533
1534 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID);
1535 if (ret < 0)
1536 return ret;
1537
1538 next.sid = ret & GLOBAL_VTU_SID_MASK;
1539
1540 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1541 if (ret < 0)
1542 return ret;
1543
1544 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1545
1546 if (next.valid) {
1547 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2);
1548 if (ret < 0)
1549 return ret;
1550 }
1551
1552 *entry = next;
1553 return 0;
1554}
1555
1556static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds,
1557 struct mv88e6xxx_vtu_stu_entry *entry)
1558{
1559 u16 reg = 0;
1560 int ret;
1561
1562 ret = _mv88e6xxx_vtu_wait(ds);
1563 if (ret < 0)
1564 return ret;
1565
1566 if (!entry->valid)
1567 goto loadpurge;
1568
1569 /* Write port states */
1570 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2);
1571 if (ret < 0)
1572 return ret;
1573
1574 reg = GLOBAL_VTU_VID_VALID;
1575loadpurge:
1576 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1577 if (ret < 0)
1578 return ret;
1579
1580 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1581 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1582 if (ret < 0)
1583 return ret;
1584
1585 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1586}
1587
2db9ce1f
VD		 1588static int _mv88e6xxx_port_fid(struct dsa_switch *ds, int port, u16 *new,
1589 u16 *old)
1590{
f74df0be 1591 u16 upper_mask;
2db9ce1f
VD		 1592 u16 fid;
1593 int ret;
1594
f74df0be
VD		 1595 if (mv88e6xxx_num_databases(ds) == 4096)
1596 upper_mask = 0xff;
11ea809f
VD		 1597 else if (mv88e6xxx_num_databases(ds) == 256)
1598 upper_mask = 0xf;
f74df0be
VD		 1599 else
1600 return -EOPNOTSUPP;
1601
2db9ce1f
VD		 1602 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1603 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1604 if (ret < 0)
1605 return ret;
1606
1607 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1608
1609 if (new) {
1610 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1611 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1612
1613 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN,
1614 ret);
1615 if (ret < 0)
1616 return ret;
1617 }
1618
1619 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1620 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL_1);
1621 if (ret < 0)
1622 return ret;
1623
f74df0be 1624 fid |= (ret & upper_mask) << 4;
2db9ce1f
VD		 1625
1626 if (new) {
f74df0be
VD		 1627 ret &= ~upper_mask;
1628 ret |= (*new >> 4) & upper_mask;
2db9ce1f
VD		 1629
1630 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1,
1631 ret);
1632 if (ret < 0)
1633 return ret;
1634
1635 netdev_dbg(ds->ports[port], "FID %d (was %d)\n", *new, fid);
1636 }
1637
1638 if (old)
1639 *old = fid;
1640
1641 return 0;
1642}
1643
1644static int _mv88e6xxx_port_fid_get(struct dsa_switch *ds, int port, u16 *fid)
1645{
1646 return _mv88e6xxx_port_fid(ds, port, NULL, fid);
1647}
1648
1649static int _mv88e6xxx_port_fid_set(struct dsa_switch *ds, int port, u16 fid)
1650{
1651 return _mv88e6xxx_port_fid(ds, port, &fid, NULL);
1652}
1653
3285f9e8
VD		 1654static int _mv88e6xxx_fid_new(struct dsa_switch *ds, u16 *fid)
1655{
2db9ce1f 1656 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3285f9e8
VD		 1657 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1658 struct mv88e6xxx_vtu_stu_entry vlan;
2db9ce1f 1659 int i, err;
3285f9e8
VD		 1660
1661 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1662
2db9ce1f
VD		 1663 /* Set every FID bit used by the (un)bridged ports */
1664 for (i = 0; i < ps->num_ports; ++i) {
1665 err = _mv88e6xxx_port_fid_get(ds, i, fid);
1666 if (err)
1667 return err;
1668
1669 set_bit(*fid, fid_bitmap);
1670 }
1671
3285f9e8
VD		 1672 /* Set every FID bit used by the VLAN entries */
1673 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1674 if (err)
1675 return err;
1676
1677 do {
1678 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1679 if (err)
1680 return err;
1681
1682 if (!vlan.valid)
1683 break;
1684
1685 set_bit(vlan.fid, fid_bitmap);
1686 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1687
1688 /* The reset value 0x000 is used to indicate that multiple address
1689 * databases are not needed. Return the next positive available.
1690 */
1691 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
f74df0be 1692 if (unlikely(*fid >= mv88e6xxx_num_databases(ds)))
3285f9e8
VD		 1693 return -ENOSPC;
1694
1695 /* Clear the database */
1696 return _mv88e6xxx_atu_flush(ds, *fid, true);
1697}
1698
2fb5ef09
VD		 1699static int _mv88e6xxx_vtu_new(struct dsa_switch *ds, u16 vid,
1700 struct mv88e6xxx_vtu_stu_entry *entry)
0d3b33e6
VD		 1701{
1702 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1703 struct mv88e6xxx_vtu_stu_entry vlan = {
1704 .valid = true,
1705 .vid = vid,
1706 };
3285f9e8
VD		 1707 int i, err;
1708
1709 err = _mv88e6xxx_fid_new(ds, &vlan.fid);
1710 if (err)
1711 return err;
0d3b33e6 1712
3d131f07 1713 /* exclude all ports except the CPU and DSA ports */
0d3b33e6 1714 for (i = 0; i < ps->num_ports; ++i)
3d131f07
VD		 1715 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1716 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1717 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6
VD		 1718
1719 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1720 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1721 struct mv88e6xxx_vtu_stu_entry vstp;
0d3b33e6
VD		 1722
1723 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1724 * implemented, only one STU entry is needed to cover all VTU
1725 * entries. Thus, validate the SID 0.
1726 */
1727 vlan.sid = 0;
1728 err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp);
1729 if (err)
1730 return err;
1731
1732 if (vstp.sid != vlan.sid || !vstp.valid) {
1733 memset(&vstp, 0, sizeof(vstp));
1734 vstp.valid = true;
1735 vstp.sid = vlan.sid;
1736
1737 err = _mv88e6xxx_stu_loadpurge(ds, &vstp);
1738 if (err)
1739 return err;
1740 }
0d3b33e6
VD		 1741 }
1742
1743 *entry = vlan;
1744 return 0;
1745}
1746
2fb5ef09
VD		 1747static int _mv88e6xxx_vtu_get(struct dsa_switch *ds, u16 vid,
1748 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1749{
1750 int err;
1751
1752 if (!vid)
1753 return -EINVAL;
1754
1755 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1756 if (err)
1757 return err;
1758
1759 err = _mv88e6xxx_vtu_getnext(ds, entry);
1760 if (err)
1761 return err;
1762
1763 if (entry->vid != vid || !entry->valid) {
1764 if (!creat)
1765 return -EOPNOTSUPP;
1766 /* -ENOENT would've been more appropriate, but switchdev expects
1767 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1768 */
1769
1770 err = _mv88e6xxx_vtu_new(ds, vid, entry);
1771 }
1772
1773 return err;
1774}
1775
da9c359e
VD		 1776static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1777 u16 vid_begin, u16 vid_end)
1778{
1779 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1780 struct mv88e6xxx_vtu_stu_entry vlan;
1781 int i, err;
1782
1783 if (!vid_begin)
1784 return -EOPNOTSUPP;
1785
1786 mutex_lock(&ps->smi_mutex);
1787
1788 err = _mv88e6xxx_vtu_vid_write(ds, vid_begin - 1);
1789 if (err)
1790 goto unlock;
1791
1792 do {
1793 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1794 if (err)
1795 goto unlock;
1796
1797 if (!vlan.valid)
1798 break;
1799
1800 if (vlan.vid > vid_end)
1801 break;
1802
1803 for (i = 0; i < ps->num_ports; ++i) {
1804 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1805 continue;
1806
1807 if (vlan.data[i] ==
1808 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1809 continue;
1810
1811 if (ps->ports[i].bridge_dev ==
1812 ps->ports[port].bridge_dev)
1813 break; /* same bridge, check next VLAN */
1814
1815 netdev_warn(ds->ports[port],
1816 "hardware VLAN %d already used by %s\n",
1817 vlan.vid,
1818 netdev_name(ps->ports[i].bridge_dev));
1819 err = -EOPNOTSUPP;
1820 goto unlock;
1821 }
1822 } while (vlan.vid < vid_end);
1823
1824unlock:
1825 mutex_unlock(&ps->smi_mutex);
1826
1827 return err;
1828}
1829
214cdb99
VD		 1830static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1831 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1832 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1833 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1834 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1835};
1836
1837int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1838 bool vlan_filtering)
1839{
1840 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1841 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1842 PORT_CONTROL_2_8021Q_DISABLED;
1843 int ret;
1844
1845 mutex_lock(&ps->smi_mutex);
1846
1847 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL_2);
1848 if (ret < 0)
1849 goto unlock;
1850
1851 old = ret & PORT_CONTROL_2_8021Q_MASK;
1852
5220ef1e
VD		 1853 if (new != old) {
1854 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1855 ret |= new & PORT_CONTROL_2_8021Q_MASK;
214cdb99 1856
5220ef1e
VD		 1857 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_2,
1858 ret);
1859 if (ret < 0)
1860 goto unlock;
1861
1862 netdev_dbg(ds->ports[port], "802.1Q Mode %s (was %s)\n",
1863 mv88e6xxx_port_8021q_mode_names[new],
1864 mv88e6xxx_port_8021q_mode_names[old]);
1865 }
214cdb99 1866
5220ef1e 1867 ret = 0;
214cdb99
VD		 1868unlock:
1869 mutex_unlock(&ps->smi_mutex);
1870
1871 return ret;
1872}
1873
76e398a6
VD		 1874int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1875 const struct switchdev_obj_port_vlan *vlan,
1876 struct switchdev_trans *trans)
1877{
da9c359e
VD		 1878 int err;
1879
da9c359e
VD		 1880 /* If the requested port doesn't belong to the same bridge as the VLAN
1881 * members, do not support it (yet) and fallback to software VLAN.
1882 */
1883 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1884 vlan->vid_end);
1885 if (err)
1886 return err;
1887
76e398a6
VD		 1888 /* We don't need any dynamic resource from the kernel (yet),
1889 * so skip the prepare phase.
1890 */
1891 return 0;
1892}
1893
1894static int _mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1895 bool untagged)
0d3b33e6 1896{
0d3b33e6
VD		 1897 struct mv88e6xxx_vtu_stu_entry vlan;
1898 int err;
1899
2fb5ef09 1900 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, true);
0d3b33e6 1901 if (err)
76e398a6 1902 return err;
0d3b33e6 1903
0d3b33e6
VD		 1904 vlan.data[port] = untagged ?
1905 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1906 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1907
76e398a6
VD		 1908 return _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1909}
1910
1911int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1912 const struct switchdev_obj_port_vlan *vlan,
1913 struct switchdev_trans *trans)
1914{
1915 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1916 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1917 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1918 u16 vid;
1919 int err = 0;
1920
1921 mutex_lock(&ps->smi_mutex);
1922
1923 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1924 err = _mv88e6xxx_port_vlan_add(ds, port, vid, untagged);
1925 if (err)
1926 goto unlock;
1927 }
1928
1929 /* no PVID with ranges, otherwise it's a bug */
1930 if (pvid)
db0e51af 1931 err = _mv88e6xxx_port_pvid_set(ds, port, vlan->vid_end);
0d3b33e6
VD		 1932unlock:
1933 mutex_unlock(&ps->smi_mutex);
1934
1935 return err;
1936}
1937
76e398a6 1938static int _mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid)
7dad08d7
VD		 1939{
1940 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1941 struct mv88e6xxx_vtu_stu_entry vlan;
7dad08d7
VD		 1942 int i, err;
1943
2fb5ef09 1944 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
7dad08d7 1945 if (err)
76e398a6 1946 return err;
7dad08d7 1947
2fb5ef09
VD		 1948 /* Tell switchdev if this VLAN is handled in software */
1949 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1950 return -EOPNOTSUPP;
7dad08d7
VD		 1951
1952 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1953
1954 /* keep the VLAN unless all ports are excluded */
f02bdffc 1955 vlan.valid = false;
7dad08d7 1956 for (i = 0; i < ps->num_ports; ++i) {
3d131f07 1957 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1958 continue;
1959
1960 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1961 vlan.valid = true;
7dad08d7
VD		 1962 break;
1963 }
1964 }
1965
7dad08d7 1966 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
76e398a6
VD		 1967 if (err)
1968 return err;
1969
1970 return _mv88e6xxx_atu_remove(ds, vlan.fid, port, false);
1971}
1972
1973int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1974 const struct switchdev_obj_port_vlan *vlan)
1975{
1976 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1977 u16 pvid, vid;
1978 int err = 0;
1979
1980 mutex_lock(&ps->smi_mutex);
1981
1982 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
7dad08d7
VD		 1983 if (err)
1984 goto unlock;
1985
76e398a6
VD		 1986 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1987 err = _mv88e6xxx_port_vlan_del(ds, port, vid);
1988 if (err)
1989 goto unlock;
1990
1991 if (vid == pvid) {
46fbe5e5 1992 err = _mv88e6xxx_port_pvid_set(ds, port, 0);
76e398a6
VD		 1993 if (err)
1994 goto unlock;
1995 }
1996 }
1997
7dad08d7
VD		 1998unlock:
1999 mutex_unlock(&ps->smi_mutex);
2000
2001 return err;
2002}
2003
c5723ac5
VD		 2004static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
2005 const unsigned char *addr)
defb05b9
GR		 2006{
2007 int i, ret;
2008
2009 for (i = 0; i < 3; i++) {
cca8b133
AL		 2010 ret = _mv88e6xxx_reg_write(
2011 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2012 (addr[i * 2] << 8) | addr[i * 2 + 1]);
defb05b9
GR		 2013 if (ret < 0)
2014 return ret;
2015 }
2016
2017 return 0;
2018}
2019
c5723ac5 2020static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
defb05b9
GR		 2021{
2022 int i, ret;
2023
2024 for (i = 0; i < 3; i++) {
cca8b133
AL		 2025 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
2026 GLOBAL_ATU_MAC_01 + i);
defb05b9
GR		 2027 if (ret < 0)
2028 return ret;
2029 addr[i * 2] = ret >> 8;
2030 addr[i * 2 + 1] = ret & 0xff;
2031 }
2032
2033 return 0;
2034}
2035
fd231c82
VD		 2036static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
2037 struct mv88e6xxx_atu_entry *entry)
defb05b9 2038{
6630e236
VD		 2039 int ret;
2040
defb05b9
GR		 2041 ret = _mv88e6xxx_atu_wait(ds);
2042 if (ret < 0)
2043 return ret;
2044
fd231c82 2045 ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
defb05b9
GR		 2046 if (ret < 0)
2047 return ret;
2048
37705b73 2049 ret = _mv88e6xxx_atu_data_write(ds, entry);
fd231c82 2050 if (ret < 0)
87820510
VD		 2051 return ret;
2052
b426e5f7 2053 return _mv88e6xxx_atu_cmd(ds, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2054}
87820510 2055
fd231c82
VD		 2056static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
2057 const unsigned char *addr, u16 vid,
2058 u8 state)
2059{
2060 struct mv88e6xxx_atu_entry entry = { 0 };
3285f9e8
VD		 2061 struct mv88e6xxx_vtu_stu_entry vlan;
2062 int err;
2063
2db9ce1f
VD		 2064 /* Null VLAN ID corresponds to the port private database */
2065 if (vid == 0)
2066 err = _mv88e6xxx_port_fid_get(ds, port, &vlan.fid);
2067 else
2068 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
3285f9e8
VD		 2069 if (err)
2070 return err;
fd231c82 2071
3285f9e8 2072 entry.fid = vlan.fid;
fd231c82
VD		 2073 entry.state = state;
2074 ether_addr_copy(entry.mac, addr);
2075 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2076 entry.trunk = false;
2077 entry.portv_trunkid = BIT(port);
2078 }
2079
2080 return _mv88e6xxx_atu_load(ds, &entry);
87820510
VD		 2081}
2082
146a3206
VD		 2083int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2084 const struct switchdev_obj_port_fdb *fdb,
2085 struct switchdev_trans *trans)
2086{
2087 /* We don't need any dynamic resource from the kernel (yet),
2088 * so skip the prepare phase.
2089 */
2090 return 0;
2091}
2092
8497aa61
VD		 2093void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2094 const struct switchdev_obj_port_fdb *fdb,
2095 struct switchdev_trans *trans)
87820510 2096{
1f36faf2 2097 int state = is_multicast_ether_addr(fdb->addr) ?
87820510
VD		 2098 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2099 GLOBAL_ATU_DATA_STATE_UC_STATIC;
cdf09697 2100 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 2101
2102 mutex_lock(&ps->smi_mutex);
8497aa61
VD		 2103 if (_mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, state))
2104 netdev_err(ds->ports[port], "failed to load MAC address\n");
87820510 2105 mutex_unlock(&ps->smi_mutex);
87820510
VD		 2106}
2107
cdf09697 2108int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
8057b3e7 2109 const struct switchdev_obj_port_fdb *fdb)
87820510
VD		 2110{
2111 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 2112 int ret;
2113
2114 mutex_lock(&ps->smi_mutex);
8057b3e7 2115 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid,
cdf09697 2116 GLOBAL_ATU_DATA_STATE_UNUSED);
87820510
VD		 2117 mutex_unlock(&ps->smi_mutex);
2118
2119 return ret;
2120}
2121
1d194046 2122static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
1d194046 2123 struct mv88e6xxx_atu_entry *entry)
6630e236 2124{
1d194046
VD		 2125 struct mv88e6xxx_atu_entry next = { 0 };
2126 int ret;
2127
2128 next.fid = fid;
defb05b9 2129
cdf09697
DM		 2130 ret = _mv88e6xxx_atu_wait(ds);
2131 if (ret < 0)
2132 return ret;
6630e236 2133
b426e5f7 2134 ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
1d194046
VD		 2135 if (ret < 0)
2136 return ret;
6630e236 2137
1d194046
VD		 2138 ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
2139 if (ret < 0)
2140 return ret;
6630e236 2141
1d194046 2142 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
cdf09697
DM		 2143 if (ret < 0)
2144 return ret;
6630e236 2145
1d194046
VD		 2146 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2147 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2148 unsigned int mask, shift;
2149
2150 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2151 next.trunk = true;
2152 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2153 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2154 } else {
2155 next.trunk = false;
2156 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2157 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2158 }
2159
2160 next.portv_trunkid = (ret & mask) >> shift;
2161 }
cdf09697 2162
1d194046 2163 *entry = next;
cdf09697
DM		 2164 return 0;
2165}
2166
74b6ba0d
VD		 2167static int _mv88e6xxx_port_fdb_dump_one(struct dsa_switch *ds, u16 fid, u16 vid,
2168 int port,
2169 struct switchdev_obj_port_fdb *fdb,
2170 int (*cb)(struct switchdev_obj *obj))
2171{
2172 struct mv88e6xxx_atu_entry addr = {
2173 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2174 };
2175 int err;
2176
2177 err = _mv88e6xxx_atu_mac_write(ds, addr.mac);
2178 if (err)
2179 return err;
2180
2181 do {
2182 err = _mv88e6xxx_atu_getnext(ds, fid, &addr);
2183 if (err)
2184 break;
2185
2186 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2187 break;
2188
2189 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2190 bool is_static = addr.state ==
2191 (is_multicast_ether_addr(addr.mac) ?
2192 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2193 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2194
2195 fdb->vid = vid;
2196 ether_addr_copy(fdb->addr, addr.mac);
2197 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2198
2199 err = cb(&fdb->obj);
2200 if (err)
2201 break;
2202 }
2203 } while (!is_broadcast_ether_addr(addr.mac));
2204
2205 return err;
2206}
2207
f33475bd
VD		 2208int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2209 struct switchdev_obj_port_fdb *fdb,
2210 int (*cb)(struct switchdev_obj *obj))
2211{
2212 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2213 struct mv88e6xxx_vtu_stu_entry vlan = {
2214 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2215 };
2db9ce1f 2216 u16 fid;
f33475bd
VD		 2217 int err;
2218
2219 mutex_lock(&ps->smi_mutex);
2220
2db9ce1f
VD		 2221 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2222 err = _mv88e6xxx_port_fid_get(ds, port, &fid);
2223 if (err)
2224 goto unlock;
2225
2226 err = _mv88e6xxx_port_fdb_dump_one(ds, fid, 0, port, fdb, cb);
2227 if (err)
2228 goto unlock;
2229
74b6ba0d 2230 /* Dump VLANs' Filtering Information Databases */
f33475bd
VD		 2231 err = _mv88e6xxx_vtu_vid_write(ds, vlan.vid);
2232 if (err)
2233 goto unlock;
2234
2235 do {
f33475bd
VD		 2236 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
2237 if (err)
74b6ba0d 2238 break;
f33475bd
VD		 2239
2240 if (!vlan.valid)
2241 break;
2242
74b6ba0d
VD		 2243 err = _mv88e6xxx_port_fdb_dump_one(ds, vlan.fid, vlan.vid, port,
2244 fdb, cb);
f33475bd 2245 if (err)
74b6ba0d 2246 break;
f33475bd
VD		 2247 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2248
2249unlock:
2250 mutex_unlock(&ps->smi_mutex);
2251
2252 return err;
2253}
2254
a6692754
VD		 2255int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2256 struct net_device *bridge)
e79a8bcb 2257{
a6692754 2258 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
466dfa07
VD		 2259 u16 fid;
2260 int i, err;
2261
2262 mutex_lock(&ps->smi_mutex);
2263
2264 /* Get or create the bridge FID and assign it to the port */
2265 for (i = 0; i < ps->num_ports; ++i)
2266 if (ps->ports[i].bridge_dev == bridge)
2267 break;
2268
2269 if (i < ps->num_ports)
2270 err = _mv88e6xxx_port_fid_get(ds, i, &fid);
2271 else
2272 err = _mv88e6xxx_fid_new(ds, &fid);
2273 if (err)
2274 goto unlock;
2275
2276 err = _mv88e6xxx_port_fid_set(ds, port, fid);
2277 if (err)
2278 goto unlock;
a6692754 2279
b7666efe 2280 /* Assign the bridge and remap each port's VLANTable */
a6692754 2281 ps->ports[port].bridge_dev = bridge;
b7666efe
VD		 2282
2283 for (i = 0; i < ps->num_ports; ++i) {
2284 if (ps->ports[i].bridge_dev == bridge) {
2285 err = _mv88e6xxx_port_based_vlan_map(ds, i);
2286 if (err)
2287 break;
2288 }
2289 }
2290
466dfa07
VD		 2291unlock:
2292 mutex_unlock(&ps->smi_mutex);
a6692754 2293
466dfa07 2294 return err;
e79a8bcb
VD		 2295}
2296
16bfa702 2297void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2298{
a6692754 2299 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
b7666efe 2300 struct net_device *bridge = ps->ports[port].bridge_dev;
466dfa07 2301 u16 fid;
16bfa702 2302 int i;
466dfa07
VD		 2303
2304 mutex_lock(&ps->smi_mutex);
2305
2306 /* Give the port a fresh Filtering Information Database */
16bfa702
VD		 2307 if (_mv88e6xxx_fid_new(ds, &fid) ||
2308 _mv88e6xxx_port_fid_set(ds, port, fid))
2309 netdev_warn(ds->ports[port], "failed to assign a new FID\n");
a6692754 2310
b7666efe 2311 /* Unassign the bridge and remap each port's VLANTable */
a6692754 2312 ps->ports[port].bridge_dev = NULL;
b7666efe 2313
16bfa702
VD		 2314 for (i = 0; i < ps->num_ports; ++i)
2315 if (i == port || ps->ports[i].bridge_dev == bridge)
2316 if (_mv88e6xxx_port_based_vlan_map(ds, i))
2317 netdev_warn(ds->ports[i], "failed to remap\n");
b7666efe 2318
466dfa07 2319 mutex_unlock(&ps->smi_mutex);
66d9cd0f
VD		 2320}
2321
facd95b2
GR		 2322static void mv88e6xxx_bridge_work(struct work_struct *work)
2323{
2324 struct mv88e6xxx_priv_state *ps;
2325 struct dsa_switch *ds;
2326 int port;
2327
2328 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
2329 ds = ((struct dsa_switch *)ps) - 1;
2330
2d9deae4
VD		 2331 mutex_lock(&ps->smi_mutex);
2332
2333 for (port = 0; port < ps->num_ports; ++port)
2334 if (test_and_clear_bit(port, ps->port_state_update_mask) &&
2335 _mv88e6xxx_port_state(ds, port, ps->ports[port].state))
2336 netdev_warn(ds->ports[port], "failed to update state to %s\n",
2337 mv88e6xxx_port_state_names[ps->ports[port].state]);
2338
2339 mutex_unlock(&ps->smi_mutex);
facd95b2
GR		 2340}
2341
75baacf0
PU		 2342static int _mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2343 int reg, int val)
2344{
2345 int ret;
2346
2347 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2348 if (ret < 0)
2349 goto restore_page_0;
2350
2351 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
2352restore_page_0:
2353 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2354
2355 return ret;
2356}
2357
2358static int _mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page,
2359 int reg)
2360{
2361 int ret;
2362
2363 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2364 if (ret < 0)
2365 goto restore_page_0;
2366
2367 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
2368restore_page_0:
2369 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2370
2371 return ret;
2372}
2373
13a7ebb3
PU		 2374static int mv88e6xxx_power_on_serdes(struct dsa_switch *ds)
2375{
2376 int ret;
2377
2378 ret = _mv88e6xxx_phy_page_read(ds, REG_FIBER_SERDES, PAGE_FIBER_SERDES,
2379 MII_BMCR);
2380 if (ret < 0)
2381 return ret;
2382
2383 if (ret & BMCR_PDOWN) {
2384 ret &= ~BMCR_PDOWN;
2385 ret = _mv88e6xxx_phy_page_write(ds, REG_FIBER_SERDES,
2386 PAGE_FIBER_SERDES, MII_BMCR,
2387 ret);
2388 }
2389
2390 return ret;
2391}
2392
dbde9e66 2393static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
d827e88a
GR		 2394{
2395 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
f02bdffc 2396 int ret;
54d792f2 2397 u16 reg;
d827e88a
GR		 2398
2399 mutex_lock(&ps->smi_mutex);
2400
54d792f2
AL		 2401 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2402 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2403 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
7c3d0d67 2404 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2405 /* MAC Forcing register: don't force link, speed,
2406 * duplex or flow control state to any particular
2407 * values on physical ports, but force the CPU port
2408 * and all DSA ports to their maximum bandwidth and
2409 * full duplex.
2410 */
2411 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
60045cbf 2412 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 2413 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 2414 reg |= PORT_PCS_CTRL_FORCE_LINK |
2415 PORT_PCS_CTRL_LINK_UP |
2416 PORT_PCS_CTRL_DUPLEX_FULL |
2417 PORT_PCS_CTRL_FORCE_DUPLEX;
2418 if (mv88e6xxx_6065_family(ds))
2419 reg |= PORT_PCS_CTRL_100;
2420 else
2421 reg |= PORT_PCS_CTRL_1000;
2422 } else {
2423 reg |= PORT_PCS_CTRL_UNFORCED;
2424 }
2425
2426 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2427 PORT_PCS_CTRL, reg);
2428 if (ret)
2429 goto abort;
2430 }
2431
2432 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2433 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2434 * tunneling, determine priority by looking at 802.1p and IP
2435 * priority fields (IP prio has precedence), and set STP state
2436 * to Forwarding.
2437 *
2438 * If this is the CPU link, use DSA or EDSA tagging depending
2439 * on which tagging mode was configured.
2440 *
2441 * If this is a link to another switch, use DSA tagging mode.
2442 *
2443 * If this is the upstream port for this switch, enable
2444 * forwarding of unknown unicasts and multicasts.
2445 */
2446 reg = 0;
2447 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2448 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2449 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
7c3d0d67 2450 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
54d792f2
AL		 2451 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2452 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2453 PORT_CONTROL_STATE_FORWARDING;
2454 if (dsa_is_cpu_port(ds, port)) {
2455 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2456 reg |= PORT_CONTROL_DSA_TAG;
2457 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 2458 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2459 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2460 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2461 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2462 else
2463 reg |= PORT_CONTROL_FRAME_MODE_DSA;
c047a1f9
AL		 2464 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2465 PORT_CONTROL_FORWARD_UNKNOWN_MC;
54d792f2
AL		 2466 }
2467
2468 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2469 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2470 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
7c3d0d67 2471 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2472 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2473 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2474 }
2475 }
6083ce71
AL		 2476 if (dsa_is_dsa_port(ds, port)) {
2477 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2478 reg |= PORT_CONTROL_DSA_TAG;
2479 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2480 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2481 mv88e6xxx_6320_family(ds)) {
54d792f2 2482 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2483 }
2484
54d792f2
AL		 2485 if (port == dsa_upstream_port(ds))
2486 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2487 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2488 }
2489 if (reg) {
2490 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2491 PORT_CONTROL, reg);
2492 if (ret)
2493 goto abort;
2494 }
2495
13a7ebb3
PU		 2496 /* If this port is connected to a SerDes, make sure the SerDes is not
2497 * powered down.
2498 */
2499 if (mv88e6xxx_6352_family(ds)) {
2500 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
2501 if (ret < 0)
2502 goto abort;
2503 ret &= PORT_STATUS_CMODE_MASK;
2504 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2505 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2506 (ret == PORT_STATUS_CMODE_SGMII)) {
2507 ret = mv88e6xxx_power_on_serdes(ds);
2508 if (ret < 0)
2509 goto abort;
2510 }
2511 }
2512
8efdda4a 2513 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2514 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2515 * untagged frames on this port, do a destination address lookup on all
2516 * received packets as usual, disable ARP mirroring and don't send a
2517 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2518 */
2519 reg = 0;
2520 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2521 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
f93dd042
VD		 2522 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds) ||
2523 mv88e6xxx_6185_family(ds))
54d792f2
AL		 2524 reg = PORT_CONTROL_2_MAP_DA;
2525
2526 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67 2527 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
54d792f2
AL		 2528 reg |= PORT_CONTROL_2_JUMBO_10240;
2529
2530 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
2531 /* Set the upstream port this port should use */
2532 reg |= dsa_upstream_port(ds);
2533 /* enable forwarding of unknown multicast addresses to
2534 * the upstream port
2535 */
2536 if (port == dsa_upstream_port(ds))
2537 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2538 }
2539
46fbe5e5 2540 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2541
54d792f2
AL		 2542 if (reg) {
2543 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2544 PORT_CONTROL_2, reg);
2545 if (ret)
2546 goto abort;
2547 }
2548
2549 /* Port Association Vector: when learning source addresses
2550 * of packets, add the address to the address database using
2551 * a port bitmap that has only the bit for this port set and
2552 * the other bits clear.
2553 */
4c7ea3c0
AL		 2554 reg = 1 << port;
2555 /* Disable learning for DSA and CPU ports */
2556 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2557 reg = PORT_ASSOC_VECTOR_LOCKED_PORT;
2558
2559 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
54d792f2
AL		 2560 if (ret)
2561 goto abort;
2562
2563 /* Egress rate control 2: disable egress rate control. */
2564 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
2565 0x0000);
2566 if (ret)
2567 goto abort;
2568
2569 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 2570 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2571 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2572 /* Do not limit the period of time that this port can
2573 * be paused for by the remote end or the period of
2574 * time that this port can pause the remote end.
2575 */
2576 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2577 PORT_PAUSE_CTRL, 0x0000);
2578 if (ret)
2579 goto abort;
2580
2581 /* Port ATU control: disable limiting the number of
2582 * address database entries that this port is allowed
2583 * to use.
2584 */
2585 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2586 PORT_ATU_CONTROL, 0x0000);
2587 /* Priority Override: disable DA, SA and VTU priority
2588 * override.
2589 */
2590 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2591 PORT_PRI_OVERRIDE, 0x0000);
2592 if (ret)
2593 goto abort;
2594
2595 /* Port Ethertype: use the Ethertype DSA Ethertype
2596 * value.
2597 */
2598 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2599 PORT_ETH_TYPE, ETH_P_EDSA);
2600 if (ret)
2601 goto abort;
2602 /* Tag Remap: use an identity 802.1p prio -> switch
2603 * prio mapping.
2604 */
2605 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2606 PORT_TAG_REGMAP_0123, 0x3210);
2607 if (ret)
2608 goto abort;
2609
2610 /* Tag Remap 2: use an identity 802.1p prio -> switch
2611 * prio mapping.
2612 */
2613 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2614 PORT_TAG_REGMAP_4567, 0x7654);
2615 if (ret)
2616 goto abort;
2617 }
2618
2619 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2620 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
7c3d0d67
AK		 2621 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2622 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2623 /* Rate Control: disable ingress rate limiting. */
2624 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2625 PORT_RATE_CONTROL, 0x0001);
2626 if (ret)
2627 goto abort;
2628 }
2629
366f0a0f
GR		 2630 /* Port Control 1: disable trunking, disable sending
2631 * learning messages to this port.
d827e88a 2632 */
614f03fc 2633 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
d827e88a
GR		 2634 if (ret)
2635 goto abort;
2636
2db9ce1f 2637 /* Port based VLAN map: give each port its own address
b7666efe
VD		 2638 * database, and allow bidirectional communication between the
2639 * CPU and DSA port(s), and the other ports.
d827e88a 2640 */
2db9ce1f
VD		 2641 ret = _mv88e6xxx_port_fid_set(ds, port, port + 1);
2642 if (ret)
2643 goto abort;
2644
b7666efe 2645 ret = _mv88e6xxx_port_based_vlan_map(ds, port);
d827e88a
GR		 2646 if (ret)
2647 goto abort;
2648
2649 /* Default VLAN ID and priority: don't set a default VLAN
2650 * ID, and set the default packet priority to zero.
2651 */
47cf1e65
VD		 2652 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
2653 0x0000);
d827e88a
GR		 2654abort:
2655 mutex_unlock(&ps->smi_mutex);
2656 return ret;
2657}
2658
dbde9e66
AL		 2659int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2660{
2661 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2662 int ret;
2663 int i;
2664
2665 for (i = 0; i < ps->num_ports; i++) {
2666 ret = mv88e6xxx_setup_port(ds, i);
2667 if (ret < 0)
2668 return ret;
2669 }
2670 return 0;
2671}
2672
acdaffcc
GR		 2673int mv88e6xxx_setup_common(struct dsa_switch *ds)
2674{
2675 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2676
2677 mutex_init(&ps->smi_mutex);
acdaffcc 2678
cca8b133 2679 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
a8f064c6 2680
facd95b2
GR		 2681 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2682
acdaffcc
GR		 2683 return 0;
2684}
2685
54d792f2
AL		 2686int mv88e6xxx_setup_global(struct dsa_switch *ds)
2687{
2688 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
24751e29 2689 int ret;
54d792f2
AL		 2690 int i;
2691
2692 /* Set the default address aging time to 5 minutes, and
2693 * enable address learn messages to be sent to all message
2694 * ports.
2695 */
2696 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
2697 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2698
2699 /* Configure the IP ToS mapping registers. */
2700 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2701 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2702 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2703 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2704 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2705 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2706 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2707 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2708
2709 /* Configure the IEEE 802.1p priority mapping register. */
2710 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2711
2712 /* Send all frames with destination addresses matching
2713 * 01:80:c2:00:00:0x to the CPU port.
2714 */
2715 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2716
2717 /* Ignore removed tag data on doubly tagged packets, disable
2718 * flow control messages, force flow control priority to the
2719 * highest, and send all special multicast frames to the CPU
2720 * port at the highest priority.
2721 */
2722 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2723 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2724 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2725
2726 /* Program the DSA routing table. */
2727 for (i = 0; i < 32; i++) {
2728 int nexthop = 0x1f;
2729
2730 if (ds->pd->rtable &&
2731 i != ds->index && i < ds->dst->pd->nr_chips)
2732 nexthop = ds->pd->rtable[i] & 0x1f;
2733
2734 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2735 GLOBAL2_DEVICE_MAPPING_UPDATE |
2736 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
2737 nexthop);
2738 }
2739
2740 /* Clear all trunk masks. */
2741 for (i = 0; i < 8; i++)
2742 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2743 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2744 ((1 << ps->num_ports) - 1));
2745
2746 /* Clear all trunk mappings. */
2747 for (i = 0; i < 16; i++)
2748 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
2749 GLOBAL2_TRUNK_MAPPING_UPDATE |
2750 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2751
2752 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 2753 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2754 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2755 /* Send all frames with destination addresses matching
2756 * 01:80:c2:00:00:2x to the CPU port.
2757 */
2758 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
2759
2760 /* Initialise cross-chip port VLAN table to reset
2761 * defaults.
2762 */
2763 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
2764
2765 /* Clear the priority override table. */
2766 for (i = 0; i < 16; i++)
2767 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
2768 0x8000 | (i << 8));
2769 }
2770
2771 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2772 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
7c3d0d67
AK		 2773 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2774 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2775 /* Disable ingress rate limiting by resetting all
2776 * ingress rate limit registers to their initial
2777 * state.
2778 */
2779 for (i = 0; i < ps->num_ports; i++)
2780 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2781 0x9000 | (i << 8));
2782 }
2783
db687a56
AL		 2784 /* Clear the statistics counters for all ports */
2785 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2786
2787 /* Wait for the flush to complete. */
24751e29
VD		 2788 mutex_lock(&ps->smi_mutex);
2789 ret = _mv88e6xxx_stats_wait(ds);
6b17e864
VD		 2790 if (ret < 0)
2791 goto unlock;
2792
c161d0a5
VD		 2793 /* Clear all ATU entries */
2794 ret = _mv88e6xxx_atu_flush(ds, 0, true);
2795 if (ret < 0)
2796 goto unlock;
2797
6b17e864
VD		 2798 /* Clear all the VTU and STU entries */
2799 ret = _mv88e6xxx_vtu_stu_flush(ds);
2800unlock:
24751e29 2801 mutex_unlock(&ps->smi_mutex);
db687a56 2802
24751e29 2803 return ret;
54d792f2
AL		 2804}
2805
143a8307
AL		 2806int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2807{
2808 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2809 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
c8c1b39a 2810 struct gpio_desc *gpiod = ds->pd->reset;
143a8307
AL		 2811 unsigned long timeout;
2812 int ret;
2813 int i;
2814
2815 /* Set all ports to the disabled state. */
2816 for (i = 0; i < ps->num_ports; i++) {
cca8b133
AL		 2817 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2818 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
143a8307
AL		 2819 }
2820
2821 /* Wait for transmit queues to drain. */
2822 usleep_range(2000, 4000);
2823
c8c1b39a
AL		 2824 /* If there is a gpio connected to the reset pin, toggle it */
2825 if (gpiod) {
2826 gpiod_set_value_cansleep(gpiod, 1);
2827 usleep_range(10000, 20000);
2828 gpiod_set_value_cansleep(gpiod, 0);
2829 usleep_range(10000, 20000);
2830 }
2831
143a8307
AL		 2832 /* Reset the switch. Keep the PPU active if requested. The PPU
2833 * needs to be active to support indirect phy register access
2834 * through global registers 0x18 and 0x19.
2835 */
2836 if (ppu_active)
2837 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2838 else
2839 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2840
2841 /* Wait up to one second for reset to complete. */
2842 timeout = jiffies + 1 * HZ;
2843 while (time_before(jiffies, timeout)) {
2844 ret = REG_READ(REG_GLOBAL, 0x00);
2845 if ((ret & is_reset) == is_reset)
2846 break;
2847 usleep_range(1000, 2000);
2848 }
2849 if (time_after(jiffies, timeout))
2850 return -ETIMEDOUT;
2851
2852 return 0;
2853}
2854
49143585
AL		 2855int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2856{
2857 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2858 int ret;
2859
3898c148 2860 mutex_lock(&ps->smi_mutex);
75baacf0 2861 ret = _mv88e6xxx_phy_page_read(ds, port, page, reg);
3898c148 2862 mutex_unlock(&ps->smi_mutex);
75baacf0 2863
49143585
AL		 2864 return ret;
2865}
2866
2867int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2868 int reg, int val)
2869{
2870 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2871 int ret;
2872
3898c148 2873 mutex_lock(&ps->smi_mutex);
75baacf0 2874 ret = _mv88e6xxx_phy_page_write(ds, port, page, reg, val);
3898c148 2875 mutex_unlock(&ps->smi_mutex);
75baacf0 2876
fd3a0ee4
AL		 2877 return ret;
2878}
2879
2880static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2881{
2882 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2883
2884 if (port >= 0 && port < ps->num_ports)
2885 return port;
2886 return -EINVAL;
2887}
2888
2889int
2890mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2891{
2892 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2893 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2894 int ret;
2895
2896 if (addr < 0)
2897 return addr;
2898
3898c148 2899 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2900 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
3898c148 2901 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2902 return ret;
2903}
2904
2905int
2906mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2907{
2908 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2909 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2910 int ret;
2911
2912 if (addr < 0)
2913 return addr;
2914
3898c148 2915 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2916 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
3898c148 2917 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2918 return ret;
2919}
2920
2921int
2922mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2923{
2924 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2925 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2926 int ret;
2927
2928 if (addr < 0)
2929 return addr;
2930
3898c148 2931 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2932 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
3898c148 2933 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2934 return ret;
2935}
2936
2937int
2938mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2939 u16 val)
2940{
2941 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2942 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2943 int ret;
2944
2945 if (addr < 0)
2946 return addr;
2947
3898c148 2948 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2949 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
3898c148 2950 mutex_unlock(&ps->smi_mutex);
49143585
AL		 2951 return ret;
2952}
2953
c22995c5
GR		 2954#ifdef CONFIG_NET_DSA_HWMON
2955
2956static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2957{
2958 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2959 int ret;
2960 int val;
2961
2962 *temp = 0;
2963
2964 mutex_lock(&ps->smi_mutex);
2965
2966 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2967 if (ret < 0)
2968 goto error;
2969
2970 /* Enable temperature sensor */
2971 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2972 if (ret < 0)
2973 goto error;
2974
2975 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2976 if (ret < 0)
2977 goto error;
2978
2979 /* Wait for temperature to stabilize */
2980 usleep_range(10000, 12000);
2981
2982 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2983 if (val < 0) {
2984 ret = val;
2985 goto error;
2986 }
2987
2988 /* Disable temperature sensor */
2989 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
2990 if (ret < 0)
2991 goto error;
2992
2993 *temp = ((val & 0x1f) - 5) * 5;
2994
2995error:
2996 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
2997 mutex_unlock(&ps->smi_mutex);
2998 return ret;
2999}
3000
3001static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3002{
3003 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3004 int ret;
3005
3006 *temp = 0;
3007
3008 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
3009 if (ret < 0)
3010 return ret;
3011
3012 *temp = (ret & 0xff) - 25;
3013
3014 return 0;
3015}
3016
3017int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3018{
3019 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
3020 return mv88e63xx_get_temp(ds, temp);
3021
3022 return mv88e61xx_get_temp(ds, temp);
3023}
3024
3025int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3026{
3027 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3028 int ret;
3029
3030 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
3031 return -EOPNOTSUPP;
3032
3033 *temp = 0;
3034
3035 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3036 if (ret < 0)
3037 return ret;
3038
3039 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3040
3041 return 0;
3042}
3043
3044int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3045{
3046 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3047 int ret;
3048
3049 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
3050 return -EOPNOTSUPP;
3051
3052 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3053 if (ret < 0)
3054 return ret;
3055 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3056 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
3057 (ret & 0xe0ff) | (temp << 8));
3058}
3059
3060int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3061{
3062 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3063 int ret;
3064
3065 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
3066 return -EOPNOTSUPP;
3067
3068 *alarm = false;
3069
3070 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3071 if (ret < 0)
3072 return ret;
3073
3074 *alarm = !!(ret & 0x40);
3075
3076 return 0;
3077}
3078#endif /* CONFIG_NET_DSA_HWMON */
3079
b9b37713
VD		 3080char *mv88e6xxx_lookup_name(struct device *host_dev, int sw_addr,
3081 const struct mv88e6xxx_switch_id *table,
3082 unsigned int num)
3083{
3084 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
3085 int i, ret;
3086
3087 if (!bus)
3088 return NULL;
3089
3090 ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
3091 if (ret < 0)
3092 return NULL;
3093
3094 /* Look up the exact switch ID */
3095 for (i = 0; i < num; ++i)
3096 if (table[i].id == ret)
3097 return table[i].name;
3098
3099 /* Look up only the product number */
3100 for (i = 0; i < num; ++i) {
3101 if (table[i].id == (ret & PORT_SWITCH_ID_PROD_NUM_MASK)) {
3102 dev_warn(host_dev, "unknown revision %d, using base switch 0x%x\n",
3103 ret & PORT_SWITCH_ID_REV_MASK,
3104 ret & PORT_SWITCH_ID_PROD_NUM_MASK);
3105 return table[i].name;
3106 }
3107 }
3108
3109 return NULL;
3110}
3111
98e67308
BH		 3112static int __init mv88e6xxx_init(void)
3113{
3114#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3115 register_switch_driver(&mv88e6131_switch_driver);
3116#endif
ca3dfa51
AL		 3117#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3118 register_switch_driver(&mv88e6123_switch_driver);
42f27253 3119#endif
3ad50cca
GR		 3120#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3121 register_switch_driver(&mv88e6352_switch_driver);
3122#endif
42f27253
AL		 3123#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3124 register_switch_driver(&mv88e6171_switch_driver);
98e67308
BH		 3125#endif
3126 return 0;
3127}
3128module_init(mv88e6xxx_init);
3129
3130static void __exit mv88e6xxx_cleanup(void)
3131{
42f27253
AL		 3132#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3133 unregister_switch_driver(&mv88e6171_switch_driver);
3134#endif
4212b543
VD		 3135#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3136 unregister_switch_driver(&mv88e6352_switch_driver);
3137#endif
ca3dfa51
AL		 3138#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3139 unregister_switch_driver(&mv88e6123_switch_driver);
98e67308
BH		 3140#endif
3141#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3142 unregister_switch_driver(&mv88e6131_switch_driver);
3143#endif
3144}
3145module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 3146
3147MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3148MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3149MODULE_LICENSE("GPL");
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