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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
ad68076e | 4 | Copyright(c) 1999 - 2008 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #include <linux/delay.h> | |
30 | ||
31 | #include "e1000.h" | |
32 | ||
33 | static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); | |
34 | static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); | |
35 | static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); | |
36 | static s32 e1000_wait_autoneg(struct e1000_hw *hw); | |
97ac8cae BA |
37 | static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); |
38 | static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, | |
39 | u16 *data, bool read); | |
a4f58f54 BA |
40 | static u32 e1000_get_phy_addr_for_hv_page(u32 page); |
41 | static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, | |
42 | u16 *data, bool read); | |
bc7f75fa AK |
43 | |
44 | /* Cable length tables */ | |
45 | static const u16 e1000_m88_cable_length_table[] = | |
46 | { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; | |
47 | ||
48 | static const u16 e1000_igp_2_cable_length_table[] = | |
49 | { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, | |
50 | 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, | |
51 | 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, | |
52 | 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, | |
53 | 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, | |
54 | 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, | |
55 | 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, | |
56 | 124}; | |
57 | #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ | |
c00acf46 | 58 | ARRAY_SIZE(e1000_igp_2_cable_length_table) |
bc7f75fa | 59 | |
a4f58f54 BA |
60 | #define BM_PHY_REG_PAGE(offset) \ |
61 | ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) | |
62 | #define BM_PHY_REG_NUM(offset) \ | |
63 | ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ | |
64 | (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ | |
65 | ~MAX_PHY_REG_ADDRESS))) | |
66 | ||
67 | #define HV_INTC_FC_PAGE_START 768 | |
68 | #define I82578_ADDR_REG 29 | |
69 | #define I82577_ADDR_REG 16 | |
70 | #define I82577_CFG_REG 22 | |
71 | #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) | |
72 | #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ | |
73 | #define I82577_CTRL_REG 23 | |
74 | #define I82577_CTRL_DOWNSHIFT_MASK (7 << 10) | |
75 | ||
76 | /* 82577 specific PHY registers */ | |
77 | #define I82577_PHY_CTRL_2 18 | |
78 | #define I82577_PHY_STATUS_2 26 | |
79 | #define I82577_PHY_DIAG_STATUS 31 | |
80 | ||
81 | /* I82577 PHY Status 2 */ | |
82 | #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 | |
83 | #define I82577_PHY_STATUS2_MDIX 0x0800 | |
84 | #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 | |
85 | #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 | |
86 | ||
87 | /* I82577 PHY Control 2 */ | |
88 | #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400 | |
89 | #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200 | |
90 | ||
91 | /* I82577 PHY Diagnostics Status */ | |
92 | #define I82577_DSTATUS_CABLE_LENGTH 0x03FC | |
93 | #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 | |
94 | ||
95 | /* BM PHY Copper Specific Control 1 */ | |
96 | #define BM_CS_CTRL1 16 | |
97 | ||
a4f58f54 BA |
98 | #define HV_MUX_DATA_CTRL PHY_REG(776, 16) |
99 | #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 | |
100 | #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 | |
101 | ||
bc7f75fa AK |
102 | /** |
103 | * e1000e_check_reset_block_generic - Check if PHY reset is blocked | |
104 | * @hw: pointer to the HW structure | |
105 | * | |
106 | * Read the PHY management control register and check whether a PHY reset | |
107 | * is blocked. If a reset is not blocked return 0, otherwise | |
108 | * return E1000_BLK_PHY_RESET (12). | |
109 | **/ | |
110 | s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) | |
111 | { | |
112 | u32 manc; | |
113 | ||
114 | manc = er32(MANC); | |
115 | ||
116 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? | |
117 | E1000_BLK_PHY_RESET : 0; | |
118 | } | |
119 | ||
120 | /** | |
121 | * e1000e_get_phy_id - Retrieve the PHY ID and revision | |
122 | * @hw: pointer to the HW structure | |
123 | * | |
124 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
125 | * revision in the hardware structure. | |
126 | **/ | |
127 | s32 e1000e_get_phy_id(struct e1000_hw *hw) | |
128 | { | |
129 | struct e1000_phy_info *phy = &hw->phy; | |
a4f58f54 | 130 | s32 ret_val = 0; |
bc7f75fa | 131 | u16 phy_id; |
a4f58f54 | 132 | u16 retry_count = 0; |
bc7f75fa | 133 | |
94d8186a | 134 | if (!(phy->ops.read_reg)) |
a4f58f54 | 135 | goto out; |
bc7f75fa | 136 | |
a4f58f54 BA |
137 | while (retry_count < 2) { |
138 | ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); | |
139 | if (ret_val) | |
140 | goto out; | |
bc7f75fa | 141 | |
a4f58f54 BA |
142 | phy->id = (u32)(phy_id << 16); |
143 | udelay(20); | |
144 | ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); | |
145 | if (ret_val) | |
146 | goto out; | |
bc7f75fa | 147 | |
a4f58f54 BA |
148 | phy->id |= (u32)(phy_id & PHY_REVISION_MASK); |
149 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
150 | ||
151 | if (phy->id != 0 && phy->id != PHY_REVISION_MASK) | |
152 | goto out; | |
153 | ||
154 | /* | |
155 | * If the PHY ID is still unknown, we may have an 82577i | |
156 | * without link. We will try again after setting Slow | |
157 | * MDIC mode. No harm in trying again in this case since | |
158 | * the PHY ID is unknown at this point anyway | |
159 | */ | |
94d8186a | 160 | ret_val = phy->ops.acquire(hw); |
5ccdcecb BA |
161 | if (ret_val) |
162 | goto out; | |
a4f58f54 BA |
163 | ret_val = e1000_set_mdio_slow_mode_hv(hw, true); |
164 | if (ret_val) | |
165 | goto out; | |
94d8186a | 166 | phy->ops.release(hw); |
a4f58f54 BA |
167 | |
168 | retry_count++; | |
169 | } | |
170 | out: | |
171 | /* Revert to MDIO fast mode, if applicable */ | |
5ccdcecb | 172 | if (retry_count) { |
94d8186a | 173 | ret_val = phy->ops.acquire(hw); |
5ccdcecb BA |
174 | if (ret_val) |
175 | return ret_val; | |
a4f58f54 | 176 | ret_val = e1000_set_mdio_slow_mode_hv(hw, false); |
94d8186a | 177 | phy->ops.release(hw); |
5ccdcecb | 178 | } |
a4f58f54 BA |
179 | |
180 | return ret_val; | |
bc7f75fa AK |
181 | } |
182 | ||
183 | /** | |
184 | * e1000e_phy_reset_dsp - Reset PHY DSP | |
185 | * @hw: pointer to the HW structure | |
186 | * | |
187 | * Reset the digital signal processor. | |
188 | **/ | |
189 | s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) | |
190 | { | |
191 | s32 ret_val; | |
192 | ||
193 | ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); | |
194 | if (ret_val) | |
195 | return ret_val; | |
196 | ||
197 | return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); | |
198 | } | |
199 | ||
200 | /** | |
2d9498f3 | 201 | * e1000e_read_phy_reg_mdic - Read MDI control register |
bc7f75fa AK |
202 | * @hw: pointer to the HW structure |
203 | * @offset: register offset to be read | |
204 | * @data: pointer to the read data | |
205 | * | |
489815ce | 206 | * Reads the MDI control register in the PHY at offset and stores the |
bc7f75fa AK |
207 | * information read to data. |
208 | **/ | |
2d9498f3 | 209 | s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) |
bc7f75fa AK |
210 | { |
211 | struct e1000_phy_info *phy = &hw->phy; | |
212 | u32 i, mdic = 0; | |
213 | ||
214 | if (offset > MAX_PHY_REG_ADDRESS) { | |
3bb99fe2 | 215 | e_dbg("PHY Address %d is out of range\n", offset); |
bc7f75fa AK |
216 | return -E1000_ERR_PARAM; |
217 | } | |
218 | ||
ad68076e BA |
219 | /* |
220 | * Set up Op-code, Phy Address, and register offset in the MDI | |
bc7f75fa AK |
221 | * Control register. The MAC will take care of interfacing with the |
222 | * PHY to retrieve the desired data. | |
223 | */ | |
224 | mdic = ((offset << E1000_MDIC_REG_SHIFT) | | |
225 | (phy->addr << E1000_MDIC_PHY_SHIFT) | | |
226 | (E1000_MDIC_OP_READ)); | |
227 | ||
228 | ew32(MDIC, mdic); | |
229 | ||
ad68076e BA |
230 | /* |
231 | * Poll the ready bit to see if the MDI read completed | |
232 | * Increasing the time out as testing showed failures with | |
233 | * the lower time out | |
234 | */ | |
2d9498f3 | 235 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { |
bc7f75fa AK |
236 | udelay(50); |
237 | mdic = er32(MDIC); | |
238 | if (mdic & E1000_MDIC_READY) | |
239 | break; | |
240 | } | |
241 | if (!(mdic & E1000_MDIC_READY)) { | |
3bb99fe2 | 242 | e_dbg("MDI Read did not complete\n"); |
bc7f75fa AK |
243 | return -E1000_ERR_PHY; |
244 | } | |
245 | if (mdic & E1000_MDIC_ERROR) { | |
3bb99fe2 | 246 | e_dbg("MDI Error\n"); |
bc7f75fa AK |
247 | return -E1000_ERR_PHY; |
248 | } | |
249 | *data = (u16) mdic; | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
254 | /** | |
2d9498f3 | 255 | * e1000e_write_phy_reg_mdic - Write MDI control register |
bc7f75fa AK |
256 | * @hw: pointer to the HW structure |
257 | * @offset: register offset to write to | |
258 | * @data: data to write to register at offset | |
259 | * | |
260 | * Writes data to MDI control register in the PHY at offset. | |
261 | **/ | |
2d9498f3 | 262 | s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) |
bc7f75fa AK |
263 | { |
264 | struct e1000_phy_info *phy = &hw->phy; | |
265 | u32 i, mdic = 0; | |
266 | ||
267 | if (offset > MAX_PHY_REG_ADDRESS) { | |
3bb99fe2 | 268 | e_dbg("PHY Address %d is out of range\n", offset); |
bc7f75fa AK |
269 | return -E1000_ERR_PARAM; |
270 | } | |
271 | ||
ad68076e BA |
272 | /* |
273 | * Set up Op-code, Phy Address, and register offset in the MDI | |
bc7f75fa AK |
274 | * Control register. The MAC will take care of interfacing with the |
275 | * PHY to retrieve the desired data. | |
276 | */ | |
277 | mdic = (((u32)data) | | |
278 | (offset << E1000_MDIC_REG_SHIFT) | | |
279 | (phy->addr << E1000_MDIC_PHY_SHIFT) | | |
280 | (E1000_MDIC_OP_WRITE)); | |
281 | ||
282 | ew32(MDIC, mdic); | |
283 | ||
2d9498f3 DG |
284 | /* |
285 | * Poll the ready bit to see if the MDI read completed | |
286 | * Increasing the time out as testing showed failures with | |
287 | * the lower time out | |
288 | */ | |
289 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { | |
290 | udelay(50); | |
bc7f75fa AK |
291 | mdic = er32(MDIC); |
292 | if (mdic & E1000_MDIC_READY) | |
293 | break; | |
294 | } | |
295 | if (!(mdic & E1000_MDIC_READY)) { | |
3bb99fe2 | 296 | e_dbg("MDI Write did not complete\n"); |
bc7f75fa AK |
297 | return -E1000_ERR_PHY; |
298 | } | |
2d9498f3 | 299 | if (mdic & E1000_MDIC_ERROR) { |
3bb99fe2 | 300 | e_dbg("MDI Error\n"); |
2d9498f3 DG |
301 | return -E1000_ERR_PHY; |
302 | } | |
bc7f75fa AK |
303 | |
304 | return 0; | |
305 | } | |
306 | ||
307 | /** | |
308 | * e1000e_read_phy_reg_m88 - Read m88 PHY register | |
309 | * @hw: pointer to the HW structure | |
310 | * @offset: register offset to be read | |
311 | * @data: pointer to the read data | |
312 | * | |
313 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
314 | * and storing the retrieved information in data. Release any acquired | |
315 | * semaphores before exiting. | |
316 | **/ | |
317 | s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) | |
318 | { | |
319 | s32 ret_val; | |
320 | ||
94d8186a | 321 | ret_val = hw->phy.ops.acquire(hw); |
bc7f75fa AK |
322 | if (ret_val) |
323 | return ret_val; | |
324 | ||
2d9498f3 DG |
325 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
326 | data); | |
bc7f75fa | 327 | |
94d8186a | 328 | hw->phy.ops.release(hw); |
bc7f75fa AK |
329 | |
330 | return ret_val; | |
331 | } | |
332 | ||
333 | /** | |
334 | * e1000e_write_phy_reg_m88 - Write m88 PHY register | |
335 | * @hw: pointer to the HW structure | |
336 | * @offset: register offset to write to | |
337 | * @data: data to write at register offset | |
338 | * | |
339 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
340 | * at the offset. Release any acquired semaphores before exiting. | |
341 | **/ | |
342 | s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) | |
343 | { | |
344 | s32 ret_val; | |
345 | ||
94d8186a | 346 | ret_val = hw->phy.ops.acquire(hw); |
bc7f75fa AK |
347 | if (ret_val) |
348 | return ret_val; | |
349 | ||
2d9498f3 DG |
350 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
351 | data); | |
bc7f75fa | 352 | |
94d8186a | 353 | hw->phy.ops.release(hw); |
bc7f75fa AK |
354 | |
355 | return ret_val; | |
356 | } | |
357 | ||
358 | /** | |
5ccdcecb | 359 | * __e1000e_read_phy_reg_igp - Read igp PHY register |
bc7f75fa AK |
360 | * @hw: pointer to the HW structure |
361 | * @offset: register offset to be read | |
362 | * @data: pointer to the read data | |
5ccdcecb | 363 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
364 | * |
365 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
5ccdcecb | 366 | * and stores the retrieved information in data. Release any acquired |
bc7f75fa AK |
367 | * semaphores before exiting. |
368 | **/ | |
5ccdcecb BA |
369 | static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, |
370 | bool locked) | |
bc7f75fa | 371 | { |
5ccdcecb | 372 | s32 ret_val = 0; |
bc7f75fa | 373 | |
5ccdcecb | 374 | if (!locked) { |
94d8186a | 375 | if (!(hw->phy.ops.acquire)) |
5ccdcecb BA |
376 | goto out; |
377 | ||
94d8186a | 378 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
379 | if (ret_val) |
380 | goto out; | |
381 | } | |
bc7f75fa AK |
382 | |
383 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2d9498f3 DG |
384 | ret_val = e1000e_write_phy_reg_mdic(hw, |
385 | IGP01E1000_PHY_PAGE_SELECT, | |
386 | (u16)offset); | |
5ccdcecb BA |
387 | if (ret_val) |
388 | goto release; | |
bc7f75fa AK |
389 | } |
390 | ||
2d9498f3 | 391 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
5ccdcecb | 392 | data); |
bc7f75fa | 393 | |
5ccdcecb BA |
394 | release: |
395 | if (!locked) | |
94d8186a | 396 | hw->phy.ops.release(hw); |
5ccdcecb | 397 | out: |
bc7f75fa AK |
398 | return ret_val; |
399 | } | |
400 | ||
5ccdcecb BA |
401 | /** |
402 | * e1000e_read_phy_reg_igp - Read igp PHY register | |
403 | * @hw: pointer to the HW structure | |
404 | * @offset: register offset to be read | |
405 | * @data: pointer to the read data | |
406 | * | |
407 | * Acquires semaphore then reads the PHY register at offset and stores the | |
408 | * retrieved information in data. | |
409 | * Release the acquired semaphore before exiting. | |
410 | **/ | |
411 | s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) | |
412 | { | |
413 | return __e1000e_read_phy_reg_igp(hw, offset, data, false); | |
414 | } | |
415 | ||
416 | /** | |
417 | * e1000e_read_phy_reg_igp_locked - Read igp PHY register | |
418 | * @hw: pointer to the HW structure | |
419 | * @offset: register offset to be read | |
420 | * @data: pointer to the read data | |
421 | * | |
422 | * Reads the PHY register at offset and stores the retrieved information | |
423 | * in data. Assumes semaphore already acquired. | |
424 | **/ | |
425 | s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) | |
426 | { | |
427 | return __e1000e_read_phy_reg_igp(hw, offset, data, true); | |
428 | } | |
429 | ||
bc7f75fa AK |
430 | /** |
431 | * e1000e_write_phy_reg_igp - Write igp PHY register | |
432 | * @hw: pointer to the HW structure | |
433 | * @offset: register offset to write to | |
434 | * @data: data to write at register offset | |
5ccdcecb | 435 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
436 | * |
437 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
438 | * at the offset. Release any acquired semaphores before exiting. | |
439 | **/ | |
5ccdcecb BA |
440 | static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, |
441 | bool locked) | |
bc7f75fa | 442 | { |
5ccdcecb | 443 | s32 ret_val = 0; |
bc7f75fa | 444 | |
5ccdcecb | 445 | if (!locked) { |
94d8186a | 446 | if (!(hw->phy.ops.acquire)) |
5ccdcecb BA |
447 | goto out; |
448 | ||
94d8186a | 449 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
450 | if (ret_val) |
451 | goto out; | |
452 | } | |
bc7f75fa AK |
453 | |
454 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2d9498f3 DG |
455 | ret_val = e1000e_write_phy_reg_mdic(hw, |
456 | IGP01E1000_PHY_PAGE_SELECT, | |
457 | (u16)offset); | |
5ccdcecb BA |
458 | if (ret_val) |
459 | goto release; | |
bc7f75fa AK |
460 | } |
461 | ||
2d9498f3 DG |
462 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
463 | data); | |
bc7f75fa | 464 | |
5ccdcecb BA |
465 | release: |
466 | if (!locked) | |
94d8186a | 467 | hw->phy.ops.release(hw); |
bc7f75fa | 468 | |
5ccdcecb | 469 | out: |
bc7f75fa AK |
470 | return ret_val; |
471 | } | |
472 | ||
473 | /** | |
5ccdcecb BA |
474 | * e1000e_write_phy_reg_igp - Write igp PHY register |
475 | * @hw: pointer to the HW structure | |
476 | * @offset: register offset to write to | |
477 | * @data: data to write at register offset | |
478 | * | |
479 | * Acquires semaphore then writes the data to PHY register | |
480 | * at the offset. Release any acquired semaphores before exiting. | |
481 | **/ | |
482 | s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) | |
483 | { | |
484 | return __e1000e_write_phy_reg_igp(hw, offset, data, false); | |
485 | } | |
486 | ||
487 | /** | |
488 | * e1000e_write_phy_reg_igp_locked - Write igp PHY register | |
489 | * @hw: pointer to the HW structure | |
490 | * @offset: register offset to write to | |
491 | * @data: data to write at register offset | |
492 | * | |
493 | * Writes the data to PHY register at the offset. | |
494 | * Assumes semaphore already acquired. | |
495 | **/ | |
496 | s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) | |
497 | { | |
498 | return __e1000e_write_phy_reg_igp(hw, offset, data, true); | |
499 | } | |
500 | ||
501 | /** | |
502 | * __e1000_read_kmrn_reg - Read kumeran register | |
bc7f75fa AK |
503 | * @hw: pointer to the HW structure |
504 | * @offset: register offset to be read | |
505 | * @data: pointer to the read data | |
5ccdcecb | 506 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
507 | * |
508 | * Acquires semaphore, if necessary. Then reads the PHY register at offset | |
509 | * using the kumeran interface. The information retrieved is stored in data. | |
510 | * Release any acquired semaphores before exiting. | |
511 | **/ | |
5ccdcecb BA |
512 | static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, |
513 | bool locked) | |
bc7f75fa AK |
514 | { |
515 | u32 kmrnctrlsta; | |
5ccdcecb | 516 | s32 ret_val = 0; |
bc7f75fa | 517 | |
5ccdcecb | 518 | if (!locked) { |
94d8186a | 519 | if (!(hw->phy.ops.acquire)) |
5ccdcecb BA |
520 | goto out; |
521 | ||
94d8186a | 522 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
523 | if (ret_val) |
524 | goto out; | |
525 | } | |
bc7f75fa AK |
526 | |
527 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
528 | E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; | |
529 | ew32(KMRNCTRLSTA, kmrnctrlsta); | |
530 | ||
531 | udelay(2); | |
532 | ||
533 | kmrnctrlsta = er32(KMRNCTRLSTA); | |
534 | *data = (u16)kmrnctrlsta; | |
535 | ||
5ccdcecb | 536 | if (!locked) |
94d8186a | 537 | hw->phy.ops.release(hw); |
bc7f75fa | 538 | |
5ccdcecb | 539 | out: |
bc7f75fa AK |
540 | return ret_val; |
541 | } | |
542 | ||
543 | /** | |
5ccdcecb BA |
544 | * e1000e_read_kmrn_reg - Read kumeran register |
545 | * @hw: pointer to the HW structure | |
546 | * @offset: register offset to be read | |
547 | * @data: pointer to the read data | |
548 | * | |
549 | * Acquires semaphore then reads the PHY register at offset using the | |
550 | * kumeran interface. The information retrieved is stored in data. | |
551 | * Release the acquired semaphore before exiting. | |
552 | **/ | |
553 | s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) | |
554 | { | |
555 | return __e1000_read_kmrn_reg(hw, offset, data, false); | |
556 | } | |
557 | ||
558 | /** | |
1d5846b9 | 559 | * e1000e_read_kmrn_reg_locked - Read kumeran register |
5ccdcecb BA |
560 | * @hw: pointer to the HW structure |
561 | * @offset: register offset to be read | |
562 | * @data: pointer to the read data | |
563 | * | |
564 | * Reads the PHY register at offset using the kumeran interface. The | |
565 | * information retrieved is stored in data. | |
566 | * Assumes semaphore already acquired. | |
567 | **/ | |
1d5846b9 | 568 | s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
5ccdcecb BA |
569 | { |
570 | return __e1000_read_kmrn_reg(hw, offset, data, true); | |
571 | } | |
572 | ||
573 | /** | |
574 | * __e1000_write_kmrn_reg - Write kumeran register | |
bc7f75fa AK |
575 | * @hw: pointer to the HW structure |
576 | * @offset: register offset to write to | |
577 | * @data: data to write at register offset | |
5ccdcecb | 578 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
579 | * |
580 | * Acquires semaphore, if necessary. Then write the data to PHY register | |
581 | * at the offset using the kumeran interface. Release any acquired semaphores | |
582 | * before exiting. | |
583 | **/ | |
5ccdcecb BA |
584 | static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, |
585 | bool locked) | |
bc7f75fa AK |
586 | { |
587 | u32 kmrnctrlsta; | |
5ccdcecb | 588 | s32 ret_val = 0; |
bc7f75fa | 589 | |
5ccdcecb | 590 | if (!locked) { |
94d8186a | 591 | if (!(hw->phy.ops.acquire)) |
5ccdcecb BA |
592 | goto out; |
593 | ||
94d8186a | 594 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
595 | if (ret_val) |
596 | goto out; | |
597 | } | |
bc7f75fa AK |
598 | |
599 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
600 | E1000_KMRNCTRLSTA_OFFSET) | data; | |
601 | ew32(KMRNCTRLSTA, kmrnctrlsta); | |
602 | ||
603 | udelay(2); | |
bc7f75fa | 604 | |
5ccdcecb | 605 | if (!locked) |
94d8186a | 606 | hw->phy.ops.release(hw); |
5ccdcecb BA |
607 | |
608 | out: | |
bc7f75fa AK |
609 | return ret_val; |
610 | } | |
611 | ||
5ccdcecb BA |
612 | /** |
613 | * e1000e_write_kmrn_reg - Write kumeran register | |
614 | * @hw: pointer to the HW structure | |
615 | * @offset: register offset to write to | |
616 | * @data: data to write at register offset | |
617 | * | |
618 | * Acquires semaphore then writes the data to the PHY register at the offset | |
619 | * using the kumeran interface. Release the acquired semaphore before exiting. | |
620 | **/ | |
621 | s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) | |
622 | { | |
623 | return __e1000_write_kmrn_reg(hw, offset, data, false); | |
624 | } | |
625 | ||
626 | /** | |
1d5846b9 | 627 | * e1000e_write_kmrn_reg_locked - Write kumeran register |
5ccdcecb BA |
628 | * @hw: pointer to the HW structure |
629 | * @offset: register offset to write to | |
630 | * @data: data to write at register offset | |
631 | * | |
632 | * Write the data to PHY register at the offset using the kumeran interface. | |
633 | * Assumes semaphore already acquired. | |
634 | **/ | |
1d5846b9 | 635 | s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) |
5ccdcecb BA |
636 | { |
637 | return __e1000_write_kmrn_reg(hw, offset, data, true); | |
638 | } | |
639 | ||
a4f58f54 BA |
640 | /** |
641 | * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link | |
642 | * @hw: pointer to the HW structure | |
643 | * | |
644 | * Sets up Carrier-sense on Transmit and downshift values. | |
645 | **/ | |
646 | s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) | |
647 | { | |
648 | struct e1000_phy_info *phy = &hw->phy; | |
649 | s32 ret_val; | |
650 | u16 phy_data; | |
651 | ||
652 | /* Enable CRS on TX. This must be set for half-duplex operation. */ | |
94d8186a | 653 | ret_val = phy->ops.read_reg(hw, I82577_CFG_REG, &phy_data); |
a4f58f54 BA |
654 | if (ret_val) |
655 | goto out; | |
656 | ||
657 | phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; | |
658 | ||
659 | /* Enable downshift */ | |
660 | phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; | |
661 | ||
94d8186a | 662 | ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data); |
a4f58f54 BA |
663 | if (ret_val) |
664 | goto out; | |
665 | ||
666 | /* Set number of link attempts before downshift */ | |
94d8186a | 667 | ret_val = phy->ops.read_reg(hw, I82577_CTRL_REG, &phy_data); |
a4f58f54 BA |
668 | if (ret_val) |
669 | goto out; | |
670 | phy_data &= ~I82577_CTRL_DOWNSHIFT_MASK; | |
94d8186a | 671 | ret_val = phy->ops.write_reg(hw, I82577_CTRL_REG, phy_data); |
a4f58f54 BA |
672 | |
673 | out: | |
674 | return ret_val; | |
675 | } | |
676 | ||
bc7f75fa AK |
677 | /** |
678 | * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link | |
679 | * @hw: pointer to the HW structure | |
680 | * | |
681 | * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock | |
682 | * and downshift values are set also. | |
683 | **/ | |
684 | s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) | |
685 | { | |
686 | struct e1000_phy_info *phy = &hw->phy; | |
687 | s32 ret_val; | |
688 | u16 phy_data; | |
689 | ||
ad68076e | 690 | /* Enable CRS on Tx. This must be set for half-duplex operation. */ |
bc7f75fa AK |
691 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
692 | if (ret_val) | |
693 | return ret_val; | |
694 | ||
a4f58f54 BA |
695 | /* For BM PHY this bit is downshift enable */ |
696 | if (phy->type != e1000_phy_bm) | |
2d9498f3 | 697 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
bc7f75fa | 698 | |
ad68076e BA |
699 | /* |
700 | * Options: | |
bc7f75fa AK |
701 | * MDI/MDI-X = 0 (default) |
702 | * 0 - Auto for all speeds | |
703 | * 1 - MDI mode | |
704 | * 2 - MDI-X mode | |
705 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
706 | */ | |
707 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
708 | ||
709 | switch (phy->mdix) { | |
710 | case 1: | |
711 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | |
712 | break; | |
713 | case 2: | |
714 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | |
715 | break; | |
716 | case 3: | |
717 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | |
718 | break; | |
719 | case 0: | |
720 | default: | |
721 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | |
722 | break; | |
723 | } | |
724 | ||
ad68076e BA |
725 | /* |
726 | * Options: | |
bc7f75fa AK |
727 | * disable_polarity_correction = 0 (default) |
728 | * Automatic Correction for Reversed Cable Polarity | |
729 | * 0 - Disabled | |
730 | * 1 - Enabled | |
731 | */ | |
732 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; | |
733 | if (phy->disable_polarity_correction == 1) | |
734 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; | |
735 | ||
97ac8cae BA |
736 | /* Enable downshift on BM (disabled by default) */ |
737 | if (phy->type == e1000_phy_bm) | |
738 | phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; | |
739 | ||
bc7f75fa AK |
740 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
741 | if (ret_val) | |
742 | return ret_val; | |
743 | ||
4662e82b BA |
744 | if ((phy->type == e1000_phy_m88) && |
745 | (phy->revision < E1000_REVISION_4) && | |
746 | (phy->id != BME1000_E_PHY_ID_R2)) { | |
ad68076e BA |
747 | /* |
748 | * Force TX_CLK in the Extended PHY Specific Control Register | |
bc7f75fa AK |
749 | * to 25MHz clock. |
750 | */ | |
751 | ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | |
752 | if (ret_val) | |
753 | return ret_val; | |
754 | ||
755 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
756 | ||
757 | if ((phy->revision == 2) && | |
758 | (phy->id == M88E1111_I_PHY_ID)) { | |
759 | /* 82573L PHY - set the downshift counter to 5x. */ | |
760 | phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; | |
761 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; | |
762 | } else { | |
763 | /* Configure Master and Slave downshift values */ | |
764 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | | |
765 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); | |
766 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | | |
767 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); | |
768 | } | |
769 | ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
770 | if (ret_val) | |
771 | return ret_val; | |
772 | } | |
773 | ||
4662e82b BA |
774 | if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { |
775 | /* Set PHY page 0, register 29 to 0x0003 */ | |
776 | ret_val = e1e_wphy(hw, 29, 0x0003); | |
777 | if (ret_val) | |
778 | return ret_val; | |
779 | ||
780 | /* Set PHY page 0, register 30 to 0x0000 */ | |
781 | ret_val = e1e_wphy(hw, 30, 0x0000); | |
782 | if (ret_val) | |
783 | return ret_val; | |
784 | } | |
785 | ||
bc7f75fa AK |
786 | /* Commit the changes. */ |
787 | ret_val = e1000e_commit_phy(hw); | |
a4f58f54 | 788 | if (ret_val) { |
3bb99fe2 | 789 | e_dbg("Error committing the PHY changes\n"); |
a4f58f54 BA |
790 | return ret_val; |
791 | } | |
bc7f75fa | 792 | |
a4f58f54 | 793 | if (phy->type == e1000_phy_82578) { |
94d8186a | 794 | ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
a4f58f54 BA |
795 | &phy_data); |
796 | if (ret_val) | |
797 | return ret_val; | |
798 | ||
799 | /* 82578 PHY - set the downshift count to 1x. */ | |
800 | phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; | |
801 | phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; | |
94d8186a | 802 | ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
a4f58f54 BA |
803 | phy_data); |
804 | if (ret_val) | |
805 | return ret_val; | |
806 | } | |
807 | ||
808 | return 0; | |
bc7f75fa AK |
809 | } |
810 | ||
811 | /** | |
812 | * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link | |
813 | * @hw: pointer to the HW structure | |
814 | * | |
815 | * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for | |
816 | * igp PHY's. | |
817 | **/ | |
818 | s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw) | |
819 | { | |
820 | struct e1000_phy_info *phy = &hw->phy; | |
821 | s32 ret_val; | |
822 | u16 data; | |
823 | ||
824 | ret_val = e1000_phy_hw_reset(hw); | |
825 | if (ret_val) { | |
3bb99fe2 | 826 | e_dbg("Error resetting the PHY.\n"); |
bc7f75fa AK |
827 | return ret_val; |
828 | } | |
829 | ||
2d9498f3 DG |
830 | /* |
831 | * Wait 100ms for MAC to configure PHY from NVM settings, to avoid | |
832 | * timeout issues when LFS is enabled. | |
833 | */ | |
834 | msleep(100); | |
bc7f75fa AK |
835 | |
836 | /* disable lplu d0 during driver init */ | |
837 | ret_val = e1000_set_d0_lplu_state(hw, 0); | |
838 | if (ret_val) { | |
3bb99fe2 | 839 | e_dbg("Error Disabling LPLU D0\n"); |
bc7f75fa AK |
840 | return ret_val; |
841 | } | |
842 | /* Configure mdi-mdix settings */ | |
843 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); | |
844 | if (ret_val) | |
845 | return ret_val; | |
846 | ||
847 | data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
848 | ||
849 | switch (phy->mdix) { | |
850 | case 1: | |
851 | data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
852 | break; | |
853 | case 2: | |
854 | data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
855 | break; | |
856 | case 0: | |
857 | default: | |
858 | data |= IGP01E1000_PSCR_AUTO_MDIX; | |
859 | break; | |
860 | } | |
861 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); | |
862 | if (ret_val) | |
863 | return ret_val; | |
864 | ||
865 | /* set auto-master slave resolution settings */ | |
866 | if (hw->mac.autoneg) { | |
ad68076e BA |
867 | /* |
868 | * when autonegotiation advertisement is only 1000Mbps then we | |
bc7f75fa | 869 | * should disable SmartSpeed and enable Auto MasterSlave |
ad68076e BA |
870 | * resolution as hardware default. |
871 | */ | |
bc7f75fa AK |
872 | if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { |
873 | /* Disable SmartSpeed */ | |
874 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 875 | &data); |
bc7f75fa AK |
876 | if (ret_val) |
877 | return ret_val; | |
878 | ||
879 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
880 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 881 | data); |
bc7f75fa AK |
882 | if (ret_val) |
883 | return ret_val; | |
884 | ||
885 | /* Set auto Master/Slave resolution process */ | |
886 | ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); | |
887 | if (ret_val) | |
888 | return ret_val; | |
889 | ||
890 | data &= ~CR_1000T_MS_ENABLE; | |
891 | ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); | |
892 | if (ret_val) | |
893 | return ret_val; | |
894 | } | |
895 | ||
896 | ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); | |
897 | if (ret_val) | |
898 | return ret_val; | |
899 | ||
900 | /* load defaults for future use */ | |
901 | phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? | |
902 | ((data & CR_1000T_MS_VALUE) ? | |
903 | e1000_ms_force_master : | |
904 | e1000_ms_force_slave) : | |
905 | e1000_ms_auto; | |
906 | ||
907 | switch (phy->ms_type) { | |
908 | case e1000_ms_force_master: | |
909 | data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); | |
910 | break; | |
911 | case e1000_ms_force_slave: | |
912 | data |= CR_1000T_MS_ENABLE; | |
913 | data &= ~(CR_1000T_MS_VALUE); | |
914 | break; | |
915 | case e1000_ms_auto: | |
916 | data &= ~CR_1000T_MS_ENABLE; | |
917 | default: | |
918 | break; | |
919 | } | |
920 | ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); | |
921 | } | |
922 | ||
923 | return ret_val; | |
924 | } | |
925 | ||
926 | /** | |
927 | * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation | |
928 | * @hw: pointer to the HW structure | |
929 | * | |
930 | * Reads the MII auto-neg advertisement register and/or the 1000T control | |
931 | * register and if the PHY is already setup for auto-negotiation, then | |
932 | * return successful. Otherwise, setup advertisement and flow control to | |
933 | * the appropriate values for the wanted auto-negotiation. | |
934 | **/ | |
935 | static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) | |
936 | { | |
937 | struct e1000_phy_info *phy = &hw->phy; | |
938 | s32 ret_val; | |
939 | u16 mii_autoneg_adv_reg; | |
940 | u16 mii_1000t_ctrl_reg = 0; | |
941 | ||
942 | phy->autoneg_advertised &= phy->autoneg_mask; | |
943 | ||
944 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ | |
945 | ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); | |
946 | if (ret_val) | |
947 | return ret_val; | |
948 | ||
949 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { | |
950 | /* Read the MII 1000Base-T Control Register (Address 9). */ | |
951 | ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); | |
952 | if (ret_val) | |
953 | return ret_val; | |
954 | } | |
955 | ||
ad68076e BA |
956 | /* |
957 | * Need to parse both autoneg_advertised and fc and set up | |
bc7f75fa AK |
958 | * the appropriate PHY registers. First we will parse for |
959 | * autoneg_advertised software override. Since we can advertise | |
960 | * a plethora of combinations, we need to check each bit | |
961 | * individually. | |
962 | */ | |
963 | ||
ad68076e BA |
964 | /* |
965 | * First we clear all the 10/100 mb speed bits in the Auto-Neg | |
bc7f75fa AK |
966 | * Advertisement Register (Address 4) and the 1000 mb speed bits in |
967 | * the 1000Base-T Control Register (Address 9). | |
968 | */ | |
969 | mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | | |
970 | NWAY_AR_100TX_HD_CAPS | | |
971 | NWAY_AR_10T_FD_CAPS | | |
972 | NWAY_AR_10T_HD_CAPS); | |
973 | mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); | |
974 | ||
3bb99fe2 | 975 | e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); |
bc7f75fa AK |
976 | |
977 | /* Do we want to advertise 10 Mb Half Duplex? */ | |
978 | if (phy->autoneg_advertised & ADVERTISE_10_HALF) { | |
3bb99fe2 | 979 | e_dbg("Advertise 10mb Half duplex\n"); |
bc7f75fa AK |
980 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; |
981 | } | |
982 | ||
983 | /* Do we want to advertise 10 Mb Full Duplex? */ | |
984 | if (phy->autoneg_advertised & ADVERTISE_10_FULL) { | |
3bb99fe2 | 985 | e_dbg("Advertise 10mb Full duplex\n"); |
bc7f75fa AK |
986 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; |
987 | } | |
988 | ||
989 | /* Do we want to advertise 100 Mb Half Duplex? */ | |
990 | if (phy->autoneg_advertised & ADVERTISE_100_HALF) { | |
3bb99fe2 | 991 | e_dbg("Advertise 100mb Half duplex\n"); |
bc7f75fa AK |
992 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
993 | } | |
994 | ||
995 | /* Do we want to advertise 100 Mb Full Duplex? */ | |
996 | if (phy->autoneg_advertised & ADVERTISE_100_FULL) { | |
3bb99fe2 | 997 | e_dbg("Advertise 100mb Full duplex\n"); |
bc7f75fa AK |
998 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; |
999 | } | |
1000 | ||
1001 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ | |
1002 | if (phy->autoneg_advertised & ADVERTISE_1000_HALF) | |
3bb99fe2 | 1003 | e_dbg("Advertise 1000mb Half duplex request denied!\n"); |
bc7f75fa AK |
1004 | |
1005 | /* Do we want to advertise 1000 Mb Full Duplex? */ | |
1006 | if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { | |
3bb99fe2 | 1007 | e_dbg("Advertise 1000mb Full duplex\n"); |
bc7f75fa AK |
1008 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
1009 | } | |
1010 | ||
ad68076e BA |
1011 | /* |
1012 | * Check for a software override of the flow control settings, and | |
bc7f75fa AK |
1013 | * setup the PHY advertisement registers accordingly. If |
1014 | * auto-negotiation is enabled, then software will have to set the | |
1015 | * "PAUSE" bits to the correct value in the Auto-Negotiation | |
1016 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- | |
1017 | * negotiation. | |
1018 | * | |
1019 | * The possible values of the "fc" parameter are: | |
1020 | * 0: Flow control is completely disabled | |
1021 | * 1: Rx flow control is enabled (we can receive pause frames | |
1022 | * but not send pause frames). | |
1023 | * 2: Tx flow control is enabled (we can send pause frames | |
1024 | * but we do not support receiving pause frames). | |
ad68076e | 1025 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
bc7f75fa AK |
1026 | * other: No software override. The flow control configuration |
1027 | * in the EEPROM is used. | |
1028 | */ | |
5c48ef3e | 1029 | switch (hw->fc.current_mode) { |
bc7f75fa | 1030 | case e1000_fc_none: |
ad68076e BA |
1031 | /* |
1032 | * Flow control (Rx & Tx) is completely disabled by a | |
bc7f75fa AK |
1033 | * software over-ride. |
1034 | */ | |
1035 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1036 | break; | |
1037 | case e1000_fc_rx_pause: | |
ad68076e BA |
1038 | /* |
1039 | * Rx Flow control is enabled, and Tx Flow control is | |
bc7f75fa | 1040 | * disabled, by a software over-ride. |
ad68076e BA |
1041 | * |
1042 | * Since there really isn't a way to advertise that we are | |
1043 | * capable of Rx Pause ONLY, we will advertise that we | |
1044 | * support both symmetric and asymmetric Rx PAUSE. Later | |
bc7f75fa AK |
1045 | * (in e1000e_config_fc_after_link_up) we will disable the |
1046 | * hw's ability to send PAUSE frames. | |
1047 | */ | |
1048 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1049 | break; | |
1050 | case e1000_fc_tx_pause: | |
ad68076e BA |
1051 | /* |
1052 | * Tx Flow control is enabled, and Rx Flow control is | |
bc7f75fa AK |
1053 | * disabled, by a software over-ride. |
1054 | */ | |
1055 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; | |
1056 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; | |
1057 | break; | |
1058 | case e1000_fc_full: | |
ad68076e BA |
1059 | /* |
1060 | * Flow control (both Rx and Tx) is enabled by a software | |
bc7f75fa AK |
1061 | * over-ride. |
1062 | */ | |
1063 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1064 | break; | |
1065 | default: | |
3bb99fe2 | 1066 | e_dbg("Flow control param set incorrectly\n"); |
bc7f75fa AK |
1067 | ret_val = -E1000_ERR_CONFIG; |
1068 | return ret_val; | |
1069 | } | |
1070 | ||
1071 | ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); | |
1072 | if (ret_val) | |
1073 | return ret_val; | |
1074 | ||
3bb99fe2 | 1075 | e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
bc7f75fa AK |
1076 | |
1077 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { | |
1078 | ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); | |
1079 | } | |
1080 | ||
1081 | return ret_val; | |
1082 | } | |
1083 | ||
1084 | /** | |
1085 | * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link | |
1086 | * @hw: pointer to the HW structure | |
1087 | * | |
1088 | * Performs initial bounds checking on autoneg advertisement parameter, then | |
1089 | * configure to advertise the full capability. Setup the PHY to autoneg | |
1090 | * and restart the negotiation process between the link partner. If | |
ad68076e | 1091 | * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. |
bc7f75fa AK |
1092 | **/ |
1093 | static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) | |
1094 | { | |
1095 | struct e1000_phy_info *phy = &hw->phy; | |
1096 | s32 ret_val; | |
1097 | u16 phy_ctrl; | |
1098 | ||
ad68076e BA |
1099 | /* |
1100 | * Perform some bounds checking on the autoneg advertisement | |
bc7f75fa AK |
1101 | * parameter. |
1102 | */ | |
1103 | phy->autoneg_advertised &= phy->autoneg_mask; | |
1104 | ||
ad68076e BA |
1105 | /* |
1106 | * If autoneg_advertised is zero, we assume it was not defaulted | |
bc7f75fa AK |
1107 | * by the calling code so we set to advertise full capability. |
1108 | */ | |
1109 | if (phy->autoneg_advertised == 0) | |
1110 | phy->autoneg_advertised = phy->autoneg_mask; | |
1111 | ||
3bb99fe2 | 1112 | e_dbg("Reconfiguring auto-neg advertisement params\n"); |
bc7f75fa AK |
1113 | ret_val = e1000_phy_setup_autoneg(hw); |
1114 | if (ret_val) { | |
3bb99fe2 | 1115 | e_dbg("Error Setting up Auto-Negotiation\n"); |
bc7f75fa AK |
1116 | return ret_val; |
1117 | } | |
3bb99fe2 | 1118 | e_dbg("Restarting Auto-Neg\n"); |
bc7f75fa | 1119 | |
ad68076e BA |
1120 | /* |
1121 | * Restart auto-negotiation by setting the Auto Neg Enable bit and | |
bc7f75fa AK |
1122 | * the Auto Neg Restart bit in the PHY control register. |
1123 | */ | |
1124 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); | |
1125 | if (ret_val) | |
1126 | return ret_val; | |
1127 | ||
1128 | phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); | |
1129 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); | |
1130 | if (ret_val) | |
1131 | return ret_val; | |
1132 | ||
ad68076e BA |
1133 | /* |
1134 | * Does the user want to wait for Auto-Neg to complete here, or | |
bc7f75fa AK |
1135 | * check at a later time (for example, callback routine). |
1136 | */ | |
318a94d6 | 1137 | if (phy->autoneg_wait_to_complete) { |
bc7f75fa AK |
1138 | ret_val = e1000_wait_autoneg(hw); |
1139 | if (ret_val) { | |
3bb99fe2 | 1140 | e_dbg("Error while waiting for " |
bc7f75fa AK |
1141 | "autoneg to complete\n"); |
1142 | return ret_val; | |
1143 | } | |
1144 | } | |
1145 | ||
1146 | hw->mac.get_link_status = 1; | |
1147 | ||
1148 | return ret_val; | |
1149 | } | |
1150 | ||
1151 | /** | |
1152 | * e1000e_setup_copper_link - Configure copper link settings | |
1153 | * @hw: pointer to the HW structure | |
1154 | * | |
1155 | * Calls the appropriate function to configure the link for auto-neg or forced | |
1156 | * speed and duplex. Then we check for link, once link is established calls | |
1157 | * to configure collision distance and flow control are called. If link is | |
1158 | * not established, we return -E1000_ERR_PHY (-2). | |
1159 | **/ | |
1160 | s32 e1000e_setup_copper_link(struct e1000_hw *hw) | |
1161 | { | |
1162 | s32 ret_val; | |
1163 | bool link; | |
1164 | ||
1165 | if (hw->mac.autoneg) { | |
ad68076e BA |
1166 | /* |
1167 | * Setup autoneg and flow control advertisement and perform | |
1168 | * autonegotiation. | |
1169 | */ | |
bc7f75fa AK |
1170 | ret_val = e1000_copper_link_autoneg(hw); |
1171 | if (ret_val) | |
1172 | return ret_val; | |
1173 | } else { | |
ad68076e BA |
1174 | /* |
1175 | * PHY will be set to 10H, 10F, 100H or 100F | |
1176 | * depending on user settings. | |
1177 | */ | |
3bb99fe2 | 1178 | e_dbg("Forcing Speed and Duplex\n"); |
bc7f75fa AK |
1179 | ret_val = e1000_phy_force_speed_duplex(hw); |
1180 | if (ret_val) { | |
3bb99fe2 | 1181 | e_dbg("Error Forcing Speed and Duplex\n"); |
bc7f75fa AK |
1182 | return ret_val; |
1183 | } | |
1184 | } | |
1185 | ||
ad68076e BA |
1186 | /* |
1187 | * Check link status. Wait up to 100 microseconds for link to become | |
bc7f75fa AK |
1188 | * valid. |
1189 | */ | |
1190 | ret_val = e1000e_phy_has_link_generic(hw, | |
1191 | COPPER_LINK_UP_LIMIT, | |
1192 | 10, | |
1193 | &link); | |
1194 | if (ret_val) | |
1195 | return ret_val; | |
1196 | ||
1197 | if (link) { | |
3bb99fe2 | 1198 | e_dbg("Valid link established!!!\n"); |
bc7f75fa AK |
1199 | e1000e_config_collision_dist(hw); |
1200 | ret_val = e1000e_config_fc_after_link_up(hw); | |
1201 | } else { | |
3bb99fe2 | 1202 | e_dbg("Unable to establish link!!!\n"); |
bc7f75fa AK |
1203 | } |
1204 | ||
1205 | return ret_val; | |
1206 | } | |
1207 | ||
1208 | /** | |
1209 | * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY | |
1210 | * @hw: pointer to the HW structure | |
1211 | * | |
1212 | * Calls the PHY setup function to force speed and duplex. Clears the | |
1213 | * auto-crossover to force MDI manually. Waits for link and returns | |
1214 | * successful if link up is successful, else -E1000_ERR_PHY (-2). | |
1215 | **/ | |
1216 | s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw) | |
1217 | { | |
1218 | struct e1000_phy_info *phy = &hw->phy; | |
1219 | s32 ret_val; | |
1220 | u16 phy_data; | |
1221 | bool link; | |
1222 | ||
1223 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); | |
1224 | if (ret_val) | |
1225 | return ret_val; | |
1226 | ||
1227 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
1228 | ||
1229 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); | |
1230 | if (ret_val) | |
1231 | return ret_val; | |
1232 | ||
ad68076e BA |
1233 | /* |
1234 | * Clear Auto-Crossover to force MDI manually. IGP requires MDI | |
bc7f75fa AK |
1235 | * forced whenever speed and duplex are forced. |
1236 | */ | |
1237 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); | |
1238 | if (ret_val) | |
1239 | return ret_val; | |
1240 | ||
1241 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
1242 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
1243 | ||
1244 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); | |
1245 | if (ret_val) | |
1246 | return ret_val; | |
1247 | ||
3bb99fe2 | 1248 | e_dbg("IGP PSCR: %X\n", phy_data); |
bc7f75fa AK |
1249 | |
1250 | udelay(1); | |
1251 | ||
318a94d6 | 1252 | if (phy->autoneg_wait_to_complete) { |
3bb99fe2 | 1253 | e_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); |
bc7f75fa AK |
1254 | |
1255 | ret_val = e1000e_phy_has_link_generic(hw, | |
1256 | PHY_FORCE_LIMIT, | |
1257 | 100000, | |
1258 | &link); | |
1259 | if (ret_val) | |
1260 | return ret_val; | |
1261 | ||
1262 | if (!link) | |
3bb99fe2 | 1263 | e_dbg("Link taking longer than expected.\n"); |
bc7f75fa AK |
1264 | |
1265 | /* Try once more */ | |
1266 | ret_val = e1000e_phy_has_link_generic(hw, | |
1267 | PHY_FORCE_LIMIT, | |
1268 | 100000, | |
1269 | &link); | |
1270 | if (ret_val) | |
1271 | return ret_val; | |
1272 | } | |
1273 | ||
1274 | return ret_val; | |
1275 | } | |
1276 | ||
1277 | /** | |
1278 | * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY | |
1279 | * @hw: pointer to the HW structure | |
1280 | * | |
1281 | * Calls the PHY setup function to force speed and duplex. Clears the | |
1282 | * auto-crossover to force MDI manually. Resets the PHY to commit the | |
1283 | * changes. If time expires while waiting for link up, we reset the DSP. | |
ad68076e | 1284 | * After reset, TX_CLK and CRS on Tx must be set. Return successful upon |
bc7f75fa AK |
1285 | * successful completion, else return corresponding error code. |
1286 | **/ | |
1287 | s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw) | |
1288 | { | |
1289 | struct e1000_phy_info *phy = &hw->phy; | |
1290 | s32 ret_val; | |
1291 | u16 phy_data; | |
1292 | bool link; | |
1293 | ||
ad68076e BA |
1294 | /* |
1295 | * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI | |
bc7f75fa AK |
1296 | * forced whenever speed and duplex are forced. |
1297 | */ | |
1298 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1299 | if (ret_val) | |
1300 | return ret_val; | |
1301 | ||
1302 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
1303 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
1304 | if (ret_val) | |
1305 | return ret_val; | |
1306 | ||
3bb99fe2 | 1307 | e_dbg("M88E1000 PSCR: %X\n", phy_data); |
bc7f75fa AK |
1308 | |
1309 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); | |
1310 | if (ret_val) | |
1311 | return ret_val; | |
1312 | ||
1313 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
1314 | ||
bc7f75fa AK |
1315 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); |
1316 | if (ret_val) | |
1317 | return ret_val; | |
1318 | ||
5aa49c82 BA |
1319 | /* Reset the phy to commit changes. */ |
1320 | ret_val = e1000e_commit_phy(hw); | |
1321 | if (ret_val) | |
1322 | return ret_val; | |
bc7f75fa | 1323 | |
318a94d6 | 1324 | if (phy->autoneg_wait_to_complete) { |
3bb99fe2 | 1325 | e_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); |
bc7f75fa AK |
1326 | |
1327 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
1328 | 100000, &link); | |
1329 | if (ret_val) | |
1330 | return ret_val; | |
1331 | ||
1332 | if (!link) { | |
ad68076e BA |
1333 | /* |
1334 | * We didn't get link. | |
bc7f75fa AK |
1335 | * Reset the DSP and cross our fingers. |
1336 | */ | |
ad68076e BA |
1337 | ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, |
1338 | 0x001d); | |
bc7f75fa AK |
1339 | if (ret_val) |
1340 | return ret_val; | |
1341 | ret_val = e1000e_phy_reset_dsp(hw); | |
1342 | if (ret_val) | |
1343 | return ret_val; | |
1344 | } | |
1345 | ||
1346 | /* Try once more */ | |
1347 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
1348 | 100000, &link); | |
1349 | if (ret_val) | |
1350 | return ret_val; | |
1351 | } | |
1352 | ||
1353 | ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | |
1354 | if (ret_val) | |
1355 | return ret_val; | |
1356 | ||
ad68076e BA |
1357 | /* |
1358 | * Resetting the phy means we need to re-force TX_CLK in the | |
bc7f75fa AK |
1359 | * Extended PHY Specific Control Register to 25MHz clock from |
1360 | * the reset value of 2.5MHz. | |
1361 | */ | |
1362 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
1363 | ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
1364 | if (ret_val) | |
1365 | return ret_val; | |
1366 | ||
ad68076e BA |
1367 | /* |
1368 | * In addition, we must re-enable CRS on Tx for both half and full | |
bc7f75fa AK |
1369 | * duplex. |
1370 | */ | |
1371 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1372 | if (ret_val) | |
1373 | return ret_val; | |
1374 | ||
1375 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | |
1376 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
1377 | ||
1378 | return ret_val; | |
1379 | } | |
1380 | ||
1381 | /** | |
1382 | * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex | |
1383 | * @hw: pointer to the HW structure | |
1384 | * @phy_ctrl: pointer to current value of PHY_CONTROL | |
1385 | * | |
1386 | * Forces speed and duplex on the PHY by doing the following: disable flow | |
1387 | * control, force speed/duplex on the MAC, disable auto speed detection, | |
1388 | * disable auto-negotiation, configure duplex, configure speed, configure | |
1389 | * the collision distance, write configuration to CTRL register. The | |
1390 | * caller must write to the PHY_CONTROL register for these settings to | |
1391 | * take affect. | |
1392 | **/ | |
1393 | void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) | |
1394 | { | |
1395 | struct e1000_mac_info *mac = &hw->mac; | |
1396 | u32 ctrl; | |
1397 | ||
1398 | /* Turn off flow control when forcing speed/duplex */ | |
5c48ef3e | 1399 | hw->fc.current_mode = e1000_fc_none; |
bc7f75fa AK |
1400 | |
1401 | /* Force speed/duplex on the mac */ | |
1402 | ctrl = er32(CTRL); | |
1403 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1404 | ctrl &= ~E1000_CTRL_SPD_SEL; | |
1405 | ||
1406 | /* Disable Auto Speed Detection */ | |
1407 | ctrl &= ~E1000_CTRL_ASDE; | |
1408 | ||
1409 | /* Disable autoneg on the phy */ | |
1410 | *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; | |
1411 | ||
1412 | /* Forcing Full or Half Duplex? */ | |
1413 | if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { | |
1414 | ctrl &= ~E1000_CTRL_FD; | |
1415 | *phy_ctrl &= ~MII_CR_FULL_DUPLEX; | |
3bb99fe2 | 1416 | e_dbg("Half Duplex\n"); |
bc7f75fa AK |
1417 | } else { |
1418 | ctrl |= E1000_CTRL_FD; | |
1419 | *phy_ctrl |= MII_CR_FULL_DUPLEX; | |
3bb99fe2 | 1420 | e_dbg("Full Duplex\n"); |
bc7f75fa AK |
1421 | } |
1422 | ||
1423 | /* Forcing 10mb or 100mb? */ | |
1424 | if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { | |
1425 | ctrl |= E1000_CTRL_SPD_100; | |
1426 | *phy_ctrl |= MII_CR_SPEED_100; | |
1427 | *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); | |
3bb99fe2 | 1428 | e_dbg("Forcing 100mb\n"); |
bc7f75fa AK |
1429 | } else { |
1430 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); | |
1431 | *phy_ctrl |= MII_CR_SPEED_10; | |
1432 | *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); | |
3bb99fe2 | 1433 | e_dbg("Forcing 10mb\n"); |
bc7f75fa AK |
1434 | } |
1435 | ||
1436 | e1000e_config_collision_dist(hw); | |
1437 | ||
1438 | ew32(CTRL, ctrl); | |
1439 | } | |
1440 | ||
1441 | /** | |
1442 | * e1000e_set_d3_lplu_state - Sets low power link up state for D3 | |
1443 | * @hw: pointer to the HW structure | |
1444 | * @active: boolean used to enable/disable lplu | |
1445 | * | |
1446 | * Success returns 0, Failure returns 1 | |
1447 | * | |
1448 | * The low power link up (lplu) state is set to the power management level D3 | |
1449 | * and SmartSpeed is disabled when active is true, else clear lplu for D3 | |
1450 | * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU | |
1451 | * is used during Dx states where the power conservation is most important. | |
1452 | * During driver activity, SmartSpeed should be enabled so performance is | |
1453 | * maintained. | |
1454 | **/ | |
1455 | s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) | |
1456 | { | |
1457 | struct e1000_phy_info *phy = &hw->phy; | |
1458 | s32 ret_val; | |
1459 | u16 data; | |
1460 | ||
1461 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); | |
1462 | if (ret_val) | |
1463 | return ret_val; | |
1464 | ||
1465 | if (!active) { | |
1466 | data &= ~IGP02E1000_PM_D3_LPLU; | |
2d9498f3 | 1467 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
bc7f75fa AK |
1468 | if (ret_val) |
1469 | return ret_val; | |
ad68076e BA |
1470 | /* |
1471 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
1472 | * during Dx states where the power conservation is most |
1473 | * important. During driver activity we should enable | |
ad68076e BA |
1474 | * SmartSpeed, so performance is maintained. |
1475 | */ | |
bc7f75fa AK |
1476 | if (phy->smart_speed == e1000_smart_speed_on) { |
1477 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1478 | &data); |
bc7f75fa AK |
1479 | if (ret_val) |
1480 | return ret_val; | |
1481 | ||
1482 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
1483 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1484 | data); |
bc7f75fa AK |
1485 | if (ret_val) |
1486 | return ret_val; | |
1487 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
1488 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1489 | &data); |
bc7f75fa AK |
1490 | if (ret_val) |
1491 | return ret_val; | |
1492 | ||
1493 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
1494 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1495 | data); |
bc7f75fa AK |
1496 | if (ret_val) |
1497 | return ret_val; | |
1498 | } | |
1499 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || | |
1500 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || | |
1501 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { | |
1502 | data |= IGP02E1000_PM_D3_LPLU; | |
1503 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
1504 | if (ret_val) | |
1505 | return ret_val; | |
1506 | ||
1507 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
1508 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
1509 | if (ret_val) | |
1510 | return ret_val; | |
1511 | ||
1512 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
1513 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
1514 | } | |
1515 | ||
1516 | return ret_val; | |
1517 | } | |
1518 | ||
1519 | /** | |
489815ce | 1520 | * e1000e_check_downshift - Checks whether a downshift in speed occurred |
bc7f75fa AK |
1521 | * @hw: pointer to the HW structure |
1522 | * | |
1523 | * Success returns 0, Failure returns 1 | |
1524 | * | |
1525 | * A downshift is detected by querying the PHY link health. | |
1526 | **/ | |
1527 | s32 e1000e_check_downshift(struct e1000_hw *hw) | |
1528 | { | |
1529 | struct e1000_phy_info *phy = &hw->phy; | |
1530 | s32 ret_val; | |
1531 | u16 phy_data, offset, mask; | |
1532 | ||
1533 | switch (phy->type) { | |
1534 | case e1000_phy_m88: | |
1535 | case e1000_phy_gg82563: | |
a4f58f54 BA |
1536 | case e1000_phy_82578: |
1537 | case e1000_phy_82577: | |
bc7f75fa AK |
1538 | offset = M88E1000_PHY_SPEC_STATUS; |
1539 | mask = M88E1000_PSSR_DOWNSHIFT; | |
1540 | break; | |
1541 | case e1000_phy_igp_2: | |
1542 | case e1000_phy_igp_3: | |
1543 | offset = IGP01E1000_PHY_LINK_HEALTH; | |
1544 | mask = IGP01E1000_PLHR_SS_DOWNGRADE; | |
1545 | break; | |
1546 | default: | |
1547 | /* speed downshift not supported */ | |
1548 | phy->speed_downgraded = 0; | |
1549 | return 0; | |
1550 | } | |
1551 | ||
1552 | ret_val = e1e_rphy(hw, offset, &phy_data); | |
1553 | ||
1554 | if (!ret_val) | |
1555 | phy->speed_downgraded = (phy_data & mask); | |
1556 | ||
1557 | return ret_val; | |
1558 | } | |
1559 | ||
1560 | /** | |
1561 | * e1000_check_polarity_m88 - Checks the polarity. | |
1562 | * @hw: pointer to the HW structure | |
1563 | * | |
1564 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1565 | * | |
1566 | * Polarity is determined based on the PHY specific status register. | |
1567 | **/ | |
1568 | static s32 e1000_check_polarity_m88(struct e1000_hw *hw) | |
1569 | { | |
1570 | struct e1000_phy_info *phy = &hw->phy; | |
1571 | s32 ret_val; | |
1572 | u16 data; | |
1573 | ||
1574 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data); | |
1575 | ||
1576 | if (!ret_val) | |
1577 | phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) | |
1578 | ? e1000_rev_polarity_reversed | |
1579 | : e1000_rev_polarity_normal; | |
1580 | ||
1581 | return ret_val; | |
1582 | } | |
1583 | ||
1584 | /** | |
1585 | * e1000_check_polarity_igp - Checks the polarity. | |
1586 | * @hw: pointer to the HW structure | |
1587 | * | |
1588 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1589 | * | |
1590 | * Polarity is determined based on the PHY port status register, and the | |
1591 | * current speed (since there is no polarity at 100Mbps). | |
1592 | **/ | |
1593 | static s32 e1000_check_polarity_igp(struct e1000_hw *hw) | |
1594 | { | |
1595 | struct e1000_phy_info *phy = &hw->phy; | |
1596 | s32 ret_val; | |
1597 | u16 data, offset, mask; | |
1598 | ||
ad68076e BA |
1599 | /* |
1600 | * Polarity is determined based on the speed of | |
1601 | * our connection. | |
1602 | */ | |
bc7f75fa AK |
1603 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
1604 | if (ret_val) | |
1605 | return ret_val; | |
1606 | ||
1607 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == | |
1608 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
1609 | offset = IGP01E1000_PHY_PCS_INIT_REG; | |
1610 | mask = IGP01E1000_PHY_POLARITY_MASK; | |
1611 | } else { | |
ad68076e BA |
1612 | /* |
1613 | * This really only applies to 10Mbps since | |
bc7f75fa AK |
1614 | * there is no polarity for 100Mbps (always 0). |
1615 | */ | |
1616 | offset = IGP01E1000_PHY_PORT_STATUS; | |
1617 | mask = IGP01E1000_PSSR_POLARITY_REVERSED; | |
1618 | } | |
1619 | ||
1620 | ret_val = e1e_rphy(hw, offset, &data); | |
1621 | ||
1622 | if (!ret_val) | |
1623 | phy->cable_polarity = (data & mask) | |
1624 | ? e1000_rev_polarity_reversed | |
1625 | : e1000_rev_polarity_normal; | |
1626 | ||
1627 | return ret_val; | |
1628 | } | |
1629 | ||
1630 | /** | |
ad68076e | 1631 | * e1000_wait_autoneg - Wait for auto-neg completion |
bc7f75fa AK |
1632 | * @hw: pointer to the HW structure |
1633 | * | |
1634 | * Waits for auto-negotiation to complete or for the auto-negotiation time | |
1635 | * limit to expire, which ever happens first. | |
1636 | **/ | |
1637 | static s32 e1000_wait_autoneg(struct e1000_hw *hw) | |
1638 | { | |
1639 | s32 ret_val = 0; | |
1640 | u16 i, phy_status; | |
1641 | ||
1642 | /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ | |
1643 | for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { | |
1644 | ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); | |
1645 | if (ret_val) | |
1646 | break; | |
1647 | ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); | |
1648 | if (ret_val) | |
1649 | break; | |
1650 | if (phy_status & MII_SR_AUTONEG_COMPLETE) | |
1651 | break; | |
1652 | msleep(100); | |
1653 | } | |
1654 | ||
ad68076e BA |
1655 | /* |
1656 | * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation | |
bc7f75fa AK |
1657 | * has completed. |
1658 | */ | |
1659 | return ret_val; | |
1660 | } | |
1661 | ||
1662 | /** | |
1663 | * e1000e_phy_has_link_generic - Polls PHY for link | |
1664 | * @hw: pointer to the HW structure | |
1665 | * @iterations: number of times to poll for link | |
1666 | * @usec_interval: delay between polling attempts | |
1667 | * @success: pointer to whether polling was successful or not | |
1668 | * | |
1669 | * Polls the PHY status register for link, 'iterations' number of times. | |
1670 | **/ | |
1671 | s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, | |
1672 | u32 usec_interval, bool *success) | |
1673 | { | |
1674 | s32 ret_val = 0; | |
1675 | u16 i, phy_status; | |
1676 | ||
1677 | for (i = 0; i < iterations; i++) { | |
ad68076e BA |
1678 | /* |
1679 | * Some PHYs require the PHY_STATUS register to be read | |
bc7f75fa AK |
1680 | * twice due to the link bit being sticky. No harm doing |
1681 | * it across the board. | |
1682 | */ | |
1683 | ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); | |
1684 | if (ret_val) | |
906e8d97 BA |
1685 | /* |
1686 | * If the first read fails, another entity may have | |
1687 | * ownership of the resources, wait and try again to | |
1688 | * see if they have relinquished the resources yet. | |
1689 | */ | |
1690 | udelay(usec_interval); | |
bc7f75fa AK |
1691 | ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); |
1692 | if (ret_val) | |
1693 | break; | |
1694 | if (phy_status & MII_SR_LINK_STATUS) | |
1695 | break; | |
1696 | if (usec_interval >= 1000) | |
1697 | mdelay(usec_interval/1000); | |
1698 | else | |
1699 | udelay(usec_interval); | |
1700 | } | |
1701 | ||
1702 | *success = (i < iterations); | |
1703 | ||
1704 | return ret_val; | |
1705 | } | |
1706 | ||
1707 | /** | |
1708 | * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY | |
1709 | * @hw: pointer to the HW structure | |
1710 | * | |
1711 | * Reads the PHY specific status register to retrieve the cable length | |
1712 | * information. The cable length is determined by averaging the minimum and | |
1713 | * maximum values to get the "average" cable length. The m88 PHY has four | |
1714 | * possible cable length values, which are: | |
1715 | * Register Value Cable Length | |
1716 | * 0 < 50 meters | |
1717 | * 1 50 - 80 meters | |
1718 | * 2 80 - 110 meters | |
1719 | * 3 110 - 140 meters | |
1720 | * 4 > 140 meters | |
1721 | **/ | |
1722 | s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) | |
1723 | { | |
1724 | struct e1000_phy_info *phy = &hw->phy; | |
1725 | s32 ret_val; | |
1726 | u16 phy_data, index; | |
1727 | ||
1728 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); | |
1729 | if (ret_val) | |
1730 | return ret_val; | |
1731 | ||
1732 | index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | |
1733 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; | |
1734 | phy->min_cable_length = e1000_m88_cable_length_table[index]; | |
1735 | phy->max_cable_length = e1000_m88_cable_length_table[index+1]; | |
1736 | ||
1737 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
1738 | ||
1739 | return ret_val; | |
1740 | } | |
1741 | ||
1742 | /** | |
1743 | * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY | |
1744 | * @hw: pointer to the HW structure | |
1745 | * | |
1746 | * The automatic gain control (agc) normalizes the amplitude of the | |
1747 | * received signal, adjusting for the attenuation produced by the | |
489815ce AK |
1748 | * cable. By reading the AGC registers, which represent the |
1749 | * combination of course and fine gain value, the value can be put | |
bc7f75fa AK |
1750 | * into a lookup table to obtain the approximate cable length |
1751 | * for each channel. | |
1752 | **/ | |
1753 | s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw) | |
1754 | { | |
1755 | struct e1000_phy_info *phy = &hw->phy; | |
1756 | s32 ret_val; | |
1757 | u16 phy_data, i, agc_value = 0; | |
1758 | u16 cur_agc_index, max_agc_index = 0; | |
1759 | u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; | |
1760 | u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = | |
1761 | {IGP02E1000_PHY_AGC_A, | |
1762 | IGP02E1000_PHY_AGC_B, | |
1763 | IGP02E1000_PHY_AGC_C, | |
1764 | IGP02E1000_PHY_AGC_D}; | |
1765 | ||
1766 | /* Read the AGC registers for all channels */ | |
1767 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { | |
1768 | ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); | |
1769 | if (ret_val) | |
1770 | return ret_val; | |
1771 | ||
ad68076e BA |
1772 | /* |
1773 | * Getting bits 15:9, which represent the combination of | |
bc7f75fa AK |
1774 | * course and fine gain values. The result is a number |
1775 | * that can be put into the lookup table to obtain the | |
ad68076e BA |
1776 | * approximate cable length. |
1777 | */ | |
bc7f75fa AK |
1778 | cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & |
1779 | IGP02E1000_AGC_LENGTH_MASK; | |
1780 | ||
1781 | /* Array index bound check. */ | |
1782 | if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || | |
1783 | (cur_agc_index == 0)) | |
1784 | return -E1000_ERR_PHY; | |
1785 | ||
1786 | /* Remove min & max AGC values from calculation. */ | |
1787 | if (e1000_igp_2_cable_length_table[min_agc_index] > | |
1788 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
1789 | min_agc_index = cur_agc_index; | |
1790 | if (e1000_igp_2_cable_length_table[max_agc_index] < | |
1791 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
1792 | max_agc_index = cur_agc_index; | |
1793 | ||
1794 | agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; | |
1795 | } | |
1796 | ||
1797 | agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + | |
1798 | e1000_igp_2_cable_length_table[max_agc_index]); | |
1799 | agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); | |
1800 | ||
1801 | /* Calculate cable length with the error range of +/- 10 meters. */ | |
1802 | phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? | |
1803 | (agc_value - IGP02E1000_AGC_RANGE) : 0; | |
1804 | phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; | |
1805 | ||
1806 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
1807 | ||
1808 | return ret_val; | |
1809 | } | |
1810 | ||
1811 | /** | |
1812 | * e1000e_get_phy_info_m88 - Retrieve PHY information | |
1813 | * @hw: pointer to the HW structure | |
1814 | * | |
1815 | * Valid for only copper links. Read the PHY status register (sticky read) | |
1816 | * to verify that link is up. Read the PHY special control register to | |
1817 | * determine the polarity and 10base-T extended distance. Read the PHY | |
1818 | * special status register to determine MDI/MDIx and current speed. If | |
1819 | * speed is 1000, then determine cable length, local and remote receiver. | |
1820 | **/ | |
1821 | s32 e1000e_get_phy_info_m88(struct e1000_hw *hw) | |
1822 | { | |
1823 | struct e1000_phy_info *phy = &hw->phy; | |
1824 | s32 ret_val; | |
1825 | u16 phy_data; | |
1826 | bool link; | |
1827 | ||
318a94d6 | 1828 | if (hw->phy.media_type != e1000_media_type_copper) { |
3bb99fe2 | 1829 | e_dbg("Phy info is only valid for copper media\n"); |
bc7f75fa AK |
1830 | return -E1000_ERR_CONFIG; |
1831 | } | |
1832 | ||
1833 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
1834 | if (ret_val) | |
1835 | return ret_val; | |
1836 | ||
1837 | if (!link) { | |
3bb99fe2 | 1838 | e_dbg("Phy info is only valid if link is up\n"); |
bc7f75fa AK |
1839 | return -E1000_ERR_CONFIG; |
1840 | } | |
1841 | ||
1842 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1843 | if (ret_val) | |
1844 | return ret_val; | |
1845 | ||
1846 | phy->polarity_correction = (phy_data & | |
1847 | M88E1000_PSCR_POLARITY_REVERSAL); | |
1848 | ||
1849 | ret_val = e1000_check_polarity_m88(hw); | |
1850 | if (ret_val) | |
1851 | return ret_val; | |
1852 | ||
1853 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); | |
1854 | if (ret_val) | |
1855 | return ret_val; | |
1856 | ||
1857 | phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX); | |
1858 | ||
1859 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { | |
1860 | ret_val = e1000_get_cable_length(hw); | |
1861 | if (ret_val) | |
1862 | return ret_val; | |
1863 | ||
1864 | ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data); | |
1865 | if (ret_val) | |
1866 | return ret_val; | |
1867 | ||
1868 | phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) | |
1869 | ? e1000_1000t_rx_status_ok | |
1870 | : e1000_1000t_rx_status_not_ok; | |
1871 | ||
1872 | phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) | |
1873 | ? e1000_1000t_rx_status_ok | |
1874 | : e1000_1000t_rx_status_not_ok; | |
1875 | } else { | |
1876 | /* Set values to "undefined" */ | |
1877 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
1878 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
1879 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
1880 | } | |
1881 | ||
1882 | return ret_val; | |
1883 | } | |
1884 | ||
1885 | /** | |
1886 | * e1000e_get_phy_info_igp - Retrieve igp PHY information | |
1887 | * @hw: pointer to the HW structure | |
1888 | * | |
1889 | * Read PHY status to determine if link is up. If link is up, then | |
1890 | * set/determine 10base-T extended distance and polarity correction. Read | |
1891 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, | |
1892 | * determine on the cable length, local and remote receiver. | |
1893 | **/ | |
1894 | s32 e1000e_get_phy_info_igp(struct e1000_hw *hw) | |
1895 | { | |
1896 | struct e1000_phy_info *phy = &hw->phy; | |
1897 | s32 ret_val; | |
1898 | u16 data; | |
1899 | bool link; | |
1900 | ||
1901 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
1902 | if (ret_val) | |
1903 | return ret_val; | |
1904 | ||
1905 | if (!link) { | |
3bb99fe2 | 1906 | e_dbg("Phy info is only valid if link is up\n"); |
bc7f75fa AK |
1907 | return -E1000_ERR_CONFIG; |
1908 | } | |
1909 | ||
1910 | phy->polarity_correction = 1; | |
1911 | ||
1912 | ret_val = e1000_check_polarity_igp(hw); | |
1913 | if (ret_val) | |
1914 | return ret_val; | |
1915 | ||
1916 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); | |
1917 | if (ret_val) | |
1918 | return ret_val; | |
1919 | ||
1920 | phy->is_mdix = (data & IGP01E1000_PSSR_MDIX); | |
1921 | ||
1922 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == | |
1923 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
1924 | ret_val = e1000_get_cable_length(hw); | |
1925 | if (ret_val) | |
1926 | return ret_val; | |
1927 | ||
1928 | ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); | |
1929 | if (ret_val) | |
1930 | return ret_val; | |
1931 | ||
1932 | phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) | |
1933 | ? e1000_1000t_rx_status_ok | |
1934 | : e1000_1000t_rx_status_not_ok; | |
1935 | ||
1936 | phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) | |
1937 | ? e1000_1000t_rx_status_ok | |
1938 | : e1000_1000t_rx_status_not_ok; | |
1939 | } else { | |
1940 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
1941 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
1942 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
1943 | } | |
1944 | ||
1945 | return ret_val; | |
1946 | } | |
1947 | ||
1948 | /** | |
1949 | * e1000e_phy_sw_reset - PHY software reset | |
1950 | * @hw: pointer to the HW structure | |
1951 | * | |
1952 | * Does a software reset of the PHY by reading the PHY control register and | |
1953 | * setting/write the control register reset bit to the PHY. | |
1954 | **/ | |
1955 | s32 e1000e_phy_sw_reset(struct e1000_hw *hw) | |
1956 | { | |
1957 | s32 ret_val; | |
1958 | u16 phy_ctrl; | |
1959 | ||
1960 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); | |
1961 | if (ret_val) | |
1962 | return ret_val; | |
1963 | ||
1964 | phy_ctrl |= MII_CR_RESET; | |
1965 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); | |
1966 | if (ret_val) | |
1967 | return ret_val; | |
1968 | ||
1969 | udelay(1); | |
1970 | ||
1971 | return ret_val; | |
1972 | } | |
1973 | ||
1974 | /** | |
1975 | * e1000e_phy_hw_reset_generic - PHY hardware reset | |
1976 | * @hw: pointer to the HW structure | |
1977 | * | |
1978 | * Verify the reset block is not blocking us from resetting. Acquire | |
1979 | * semaphore (if necessary) and read/set/write the device control reset | |
1980 | * bit in the PHY. Wait the appropriate delay time for the device to | |
489815ce | 1981 | * reset and release the semaphore (if necessary). |
bc7f75fa AK |
1982 | **/ |
1983 | s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) | |
1984 | { | |
1985 | struct e1000_phy_info *phy = &hw->phy; | |
1986 | s32 ret_val; | |
1987 | u32 ctrl; | |
1988 | ||
1989 | ret_val = e1000_check_reset_block(hw); | |
1990 | if (ret_val) | |
1991 | return 0; | |
1992 | ||
94d8186a | 1993 | ret_val = phy->ops.acquire(hw); |
bc7f75fa AK |
1994 | if (ret_val) |
1995 | return ret_val; | |
1996 | ||
1997 | ctrl = er32(CTRL); | |
1998 | ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); | |
1999 | e1e_flush(); | |
2000 | ||
2001 | udelay(phy->reset_delay_us); | |
2002 | ||
2003 | ew32(CTRL, ctrl); | |
2004 | e1e_flush(); | |
2005 | ||
2006 | udelay(150); | |
2007 | ||
94d8186a | 2008 | phy->ops.release(hw); |
bc7f75fa AK |
2009 | |
2010 | return e1000_get_phy_cfg_done(hw); | |
2011 | } | |
2012 | ||
2013 | /** | |
2014 | * e1000e_get_cfg_done - Generic configuration done | |
2015 | * @hw: pointer to the HW structure | |
2016 | * | |
2017 | * Generic function to wait 10 milli-seconds for configuration to complete | |
2018 | * and return success. | |
2019 | **/ | |
2020 | s32 e1000e_get_cfg_done(struct e1000_hw *hw) | |
2021 | { | |
2022 | mdelay(10); | |
2023 | return 0; | |
2024 | } | |
2025 | ||
f4187b56 BA |
2026 | /** |
2027 | * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY | |
2028 | * @hw: pointer to the HW structure | |
2029 | * | |
2030 | * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. | |
2031 | **/ | |
2032 | s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw) | |
2033 | { | |
3bb99fe2 | 2034 | e_dbg("Running IGP 3 PHY init script\n"); |
f4187b56 BA |
2035 | |
2036 | /* PHY init IGP 3 */ | |
2037 | /* Enable rise/fall, 10-mode work in class-A */ | |
2038 | e1e_wphy(hw, 0x2F5B, 0x9018); | |
2039 | /* Remove all caps from Replica path filter */ | |
2040 | e1e_wphy(hw, 0x2F52, 0x0000); | |
2041 | /* Bias trimming for ADC, AFE and Driver (Default) */ | |
2042 | e1e_wphy(hw, 0x2FB1, 0x8B24); | |
2043 | /* Increase Hybrid poly bias */ | |
2044 | e1e_wphy(hw, 0x2FB2, 0xF8F0); | |
2045 | /* Add 4% to Tx amplitude in Gig mode */ | |
2046 | e1e_wphy(hw, 0x2010, 0x10B0); | |
2047 | /* Disable trimming (TTT) */ | |
2048 | e1e_wphy(hw, 0x2011, 0x0000); | |
2049 | /* Poly DC correction to 94.6% + 2% for all channels */ | |
2050 | e1e_wphy(hw, 0x20DD, 0x249A); | |
2051 | /* ABS DC correction to 95.9% */ | |
2052 | e1e_wphy(hw, 0x20DE, 0x00D3); | |
2053 | /* BG temp curve trim */ | |
2054 | e1e_wphy(hw, 0x28B4, 0x04CE); | |
2055 | /* Increasing ADC OPAMP stage 1 currents to max */ | |
2056 | e1e_wphy(hw, 0x2F70, 0x29E4); | |
2057 | /* Force 1000 ( required for enabling PHY regs configuration) */ | |
2058 | e1e_wphy(hw, 0x0000, 0x0140); | |
2059 | /* Set upd_freq to 6 */ | |
2060 | e1e_wphy(hw, 0x1F30, 0x1606); | |
2061 | /* Disable NPDFE */ | |
2062 | e1e_wphy(hw, 0x1F31, 0xB814); | |
2063 | /* Disable adaptive fixed FFE (Default) */ | |
2064 | e1e_wphy(hw, 0x1F35, 0x002A); | |
2065 | /* Enable FFE hysteresis */ | |
2066 | e1e_wphy(hw, 0x1F3E, 0x0067); | |
2067 | /* Fixed FFE for short cable lengths */ | |
2068 | e1e_wphy(hw, 0x1F54, 0x0065); | |
2069 | /* Fixed FFE for medium cable lengths */ | |
2070 | e1e_wphy(hw, 0x1F55, 0x002A); | |
2071 | /* Fixed FFE for long cable lengths */ | |
2072 | e1e_wphy(hw, 0x1F56, 0x002A); | |
2073 | /* Enable Adaptive Clip Threshold */ | |
2074 | e1e_wphy(hw, 0x1F72, 0x3FB0); | |
2075 | /* AHT reset limit to 1 */ | |
2076 | e1e_wphy(hw, 0x1F76, 0xC0FF); | |
2077 | /* Set AHT master delay to 127 msec */ | |
2078 | e1e_wphy(hw, 0x1F77, 0x1DEC); | |
2079 | /* Set scan bits for AHT */ | |
2080 | e1e_wphy(hw, 0x1F78, 0xF9EF); | |
2081 | /* Set AHT Preset bits */ | |
2082 | e1e_wphy(hw, 0x1F79, 0x0210); | |
2083 | /* Change integ_factor of channel A to 3 */ | |
2084 | e1e_wphy(hw, 0x1895, 0x0003); | |
2085 | /* Change prop_factor of channels BCD to 8 */ | |
2086 | e1e_wphy(hw, 0x1796, 0x0008); | |
2087 | /* Change cg_icount + enable integbp for channels BCD */ | |
2088 | e1e_wphy(hw, 0x1798, 0xD008); | |
2089 | /* | |
2090 | * Change cg_icount + enable integbp + change prop_factor_master | |
2091 | * to 8 for channel A | |
2092 | */ | |
2093 | e1e_wphy(hw, 0x1898, 0xD918); | |
2094 | /* Disable AHT in Slave mode on channel A */ | |
2095 | e1e_wphy(hw, 0x187A, 0x0800); | |
2096 | /* | |
2097 | * Enable LPLU and disable AN to 1000 in non-D0a states, | |
2098 | * Enable SPD+B2B | |
2099 | */ | |
2100 | e1e_wphy(hw, 0x0019, 0x008D); | |
2101 | /* Enable restart AN on an1000_dis change */ | |
2102 | e1e_wphy(hw, 0x001B, 0x2080); | |
2103 | /* Enable wh_fifo read clock in 10/100 modes */ | |
2104 | e1e_wphy(hw, 0x0014, 0x0045); | |
2105 | /* Restart AN, Speed selection is 1000 */ | |
2106 | e1e_wphy(hw, 0x0000, 0x1340); | |
2107 | ||
2108 | return 0; | |
2109 | } | |
2110 | ||
bc7f75fa AK |
2111 | /* Internal function pointers */ |
2112 | ||
2113 | /** | |
2114 | * e1000_get_phy_cfg_done - Generic PHY configuration done | |
2115 | * @hw: pointer to the HW structure | |
2116 | * | |
2117 | * Return success if silicon family did not implement a family specific | |
2118 | * get_cfg_done function. | |
2119 | **/ | |
2120 | static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) | |
2121 | { | |
2122 | if (hw->phy.ops.get_cfg_done) | |
2123 | return hw->phy.ops.get_cfg_done(hw); | |
2124 | ||
2125 | return 0; | |
2126 | } | |
2127 | ||
2128 | /** | |
2129 | * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex | |
2130 | * @hw: pointer to the HW structure | |
2131 | * | |
2132 | * When the silicon family has not implemented a forced speed/duplex | |
2133 | * function for the PHY, simply return 0. | |
2134 | **/ | |
2135 | static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) | |
2136 | { | |
2137 | if (hw->phy.ops.force_speed_duplex) | |
2138 | return hw->phy.ops.force_speed_duplex(hw); | |
2139 | ||
2140 | return 0; | |
2141 | } | |
2142 | ||
2143 | /** | |
2144 | * e1000e_get_phy_type_from_id - Get PHY type from id | |
2145 | * @phy_id: phy_id read from the phy | |
2146 | * | |
2147 | * Returns the phy type from the id. | |
2148 | **/ | |
2149 | enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id) | |
2150 | { | |
2151 | enum e1000_phy_type phy_type = e1000_phy_unknown; | |
2152 | ||
2153 | switch (phy_id) { | |
2154 | case M88E1000_I_PHY_ID: | |
2155 | case M88E1000_E_PHY_ID: | |
2156 | case M88E1111_I_PHY_ID: | |
2157 | case M88E1011_I_PHY_ID: | |
2158 | phy_type = e1000_phy_m88; | |
2159 | break; | |
2160 | case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ | |
2161 | phy_type = e1000_phy_igp_2; | |
2162 | break; | |
2163 | case GG82563_E_PHY_ID: | |
2164 | phy_type = e1000_phy_gg82563; | |
2165 | break; | |
2166 | case IGP03E1000_E_PHY_ID: | |
2167 | phy_type = e1000_phy_igp_3; | |
2168 | break; | |
2169 | case IFE_E_PHY_ID: | |
2170 | case IFE_PLUS_E_PHY_ID: | |
2171 | case IFE_C_E_PHY_ID: | |
2172 | phy_type = e1000_phy_ife; | |
2173 | break; | |
97ac8cae BA |
2174 | case BME1000_E_PHY_ID: |
2175 | case BME1000_E_PHY_ID_R2: | |
2176 | phy_type = e1000_phy_bm; | |
2177 | break; | |
a4f58f54 BA |
2178 | case I82578_E_PHY_ID: |
2179 | phy_type = e1000_phy_82578; | |
2180 | break; | |
2181 | case I82577_E_PHY_ID: | |
2182 | phy_type = e1000_phy_82577; | |
2183 | break; | |
bc7f75fa AK |
2184 | default: |
2185 | phy_type = e1000_phy_unknown; | |
2186 | break; | |
2187 | } | |
2188 | return phy_type; | |
2189 | } | |
2190 | ||
97ac8cae BA |
2191 | /** |
2192 | * e1000e_determine_phy_address - Determines PHY address. | |
2193 | * @hw: pointer to the HW structure | |
2194 | * | |
2195 | * This uses a trial and error method to loop through possible PHY | |
2196 | * addresses. It tests each by reading the PHY ID registers and | |
2197 | * checking for a match. | |
2198 | **/ | |
2199 | s32 e1000e_determine_phy_address(struct e1000_hw *hw) | |
2200 | { | |
2201 | s32 ret_val = -E1000_ERR_PHY_TYPE; | |
2202 | u32 phy_addr= 0; | |
2203 | u32 i = 0; | |
2204 | enum e1000_phy_type phy_type = e1000_phy_unknown; | |
2205 | ||
2206 | do { | |
2207 | for (phy_addr = 0; phy_addr < 4; phy_addr++) { | |
2208 | hw->phy.addr = phy_addr; | |
2209 | e1000e_get_phy_id(hw); | |
2210 | phy_type = e1000e_get_phy_type_from_id(hw->phy.id); | |
2211 | ||
2212 | /* | |
2213 | * If phy_type is valid, break - we found our | |
2214 | * PHY address | |
2215 | */ | |
2216 | if (phy_type != e1000_phy_unknown) { | |
2217 | ret_val = 0; | |
2218 | break; | |
2219 | } | |
2220 | } | |
2221 | i++; | |
2222 | } while ((ret_val != 0) && (i < 100)); | |
2223 | ||
2224 | return ret_val; | |
2225 | } | |
2226 | ||
2227 | /** | |
2228 | * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address | |
2229 | * @page: page to access | |
2230 | * | |
2231 | * Returns the phy address for the page requested. | |
2232 | **/ | |
2233 | static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) | |
2234 | { | |
2235 | u32 phy_addr = 2; | |
2236 | ||
2237 | if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) | |
2238 | phy_addr = 1; | |
2239 | ||
2240 | return phy_addr; | |
2241 | } | |
2242 | ||
2243 | /** | |
2244 | * e1000e_write_phy_reg_bm - Write BM PHY register | |
2245 | * @hw: pointer to the HW structure | |
2246 | * @offset: register offset to write to | |
2247 | * @data: data to write at register offset | |
2248 | * | |
2249 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
2250 | * at the offset. Release any acquired semaphores before exiting. | |
2251 | **/ | |
2252 | s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) | |
2253 | { | |
2254 | s32 ret_val; | |
2255 | u32 page_select = 0; | |
2256 | u32 page = offset >> IGP_PAGE_SHIFT; | |
2257 | u32 page_shift = 0; | |
2258 | ||
94d8186a | 2259 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2260 | if (ret_val) |
2261 | return ret_val; | |
2262 | ||
97ac8cae BA |
2263 | /* Page 800 works differently than the rest so it has its own func */ |
2264 | if (page == BM_WUC_PAGE) { | |
2265 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, | |
2266 | false); | |
2267 | goto out; | |
2268 | } | |
2269 | ||
97ac8cae BA |
2270 | hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
2271 | ||
2272 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2273 | /* | |
2274 | * Page select is register 31 for phy address 1 and 22 for | |
2275 | * phy address 2 and 3. Page select is shifted only for | |
2276 | * phy address 1. | |
2277 | */ | |
2278 | if (hw->phy.addr == 1) { | |
2279 | page_shift = IGP_PAGE_SHIFT; | |
2280 | page_select = IGP01E1000_PHY_PAGE_SELECT; | |
2281 | } else { | |
2282 | page_shift = 0; | |
2283 | page_select = BM_PHY_PAGE_SELECT; | |
2284 | } | |
2285 | ||
2286 | /* Page is shifted left, PHY expects (page x 32) */ | |
2287 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, | |
2288 | (page << page_shift)); | |
5ccdcecb | 2289 | if (ret_val) |
97ac8cae | 2290 | goto out; |
97ac8cae BA |
2291 | } |
2292 | ||
2293 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2294 | data); | |
2295 | ||
97ac8cae | 2296 | out: |
94d8186a | 2297 | hw->phy.ops.release(hw); |
97ac8cae BA |
2298 | return ret_val; |
2299 | } | |
2300 | ||
2301 | /** | |
2302 | * e1000e_read_phy_reg_bm - Read BM PHY register | |
2303 | * @hw: pointer to the HW structure | |
2304 | * @offset: register offset to be read | |
2305 | * @data: pointer to the read data | |
2306 | * | |
2307 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
2308 | * and storing the retrieved information in data. Release any acquired | |
2309 | * semaphores before exiting. | |
2310 | **/ | |
2311 | s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) | |
2312 | { | |
2313 | s32 ret_val; | |
2314 | u32 page_select = 0; | |
2315 | u32 page = offset >> IGP_PAGE_SHIFT; | |
2316 | u32 page_shift = 0; | |
2317 | ||
94d8186a | 2318 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2319 | if (ret_val) |
2320 | return ret_val; | |
2321 | ||
97ac8cae BA |
2322 | /* Page 800 works differently than the rest so it has its own func */ |
2323 | if (page == BM_WUC_PAGE) { | |
2324 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, | |
2325 | true); | |
2326 | goto out; | |
2327 | } | |
2328 | ||
97ac8cae BA |
2329 | hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
2330 | ||
2331 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2332 | /* | |
2333 | * Page select is register 31 for phy address 1 and 22 for | |
2334 | * phy address 2 and 3. Page select is shifted only for | |
2335 | * phy address 1. | |
2336 | */ | |
2337 | if (hw->phy.addr == 1) { | |
2338 | page_shift = IGP_PAGE_SHIFT; | |
2339 | page_select = IGP01E1000_PHY_PAGE_SELECT; | |
2340 | } else { | |
2341 | page_shift = 0; | |
2342 | page_select = BM_PHY_PAGE_SELECT; | |
2343 | } | |
2344 | ||
2345 | /* Page is shifted left, PHY expects (page x 32) */ | |
2346 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, | |
2347 | (page << page_shift)); | |
5ccdcecb | 2348 | if (ret_val) |
97ac8cae | 2349 | goto out; |
97ac8cae BA |
2350 | } |
2351 | ||
2352 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2353 | data); | |
97ac8cae | 2354 | out: |
94d8186a | 2355 | hw->phy.ops.release(hw); |
97ac8cae BA |
2356 | return ret_val; |
2357 | } | |
2358 | ||
4662e82b BA |
2359 | /** |
2360 | * e1000e_read_phy_reg_bm2 - Read BM PHY register | |
2361 | * @hw: pointer to the HW structure | |
2362 | * @offset: register offset to be read | |
2363 | * @data: pointer to the read data | |
2364 | * | |
2365 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
2366 | * and storing the retrieved information in data. Release any acquired | |
2367 | * semaphores before exiting. | |
2368 | **/ | |
2369 | s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) | |
2370 | { | |
2371 | s32 ret_val; | |
2372 | u16 page = (u16)(offset >> IGP_PAGE_SHIFT); | |
2373 | ||
94d8186a | 2374 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2375 | if (ret_val) |
2376 | return ret_val; | |
2377 | ||
4662e82b BA |
2378 | /* Page 800 works differently than the rest so it has its own func */ |
2379 | if (page == BM_WUC_PAGE) { | |
2380 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, | |
2381 | true); | |
5ccdcecb | 2382 | goto out; |
4662e82b BA |
2383 | } |
2384 | ||
4662e82b BA |
2385 | hw->phy.addr = 1; |
2386 | ||
2387 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2388 | ||
2389 | /* Page is shifted left, PHY expects (page x 32) */ | |
2390 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, | |
2391 | page); | |
2392 | ||
5ccdcecb BA |
2393 | if (ret_val) |
2394 | goto out; | |
4662e82b BA |
2395 | } |
2396 | ||
2397 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2398 | data); | |
5ccdcecb | 2399 | out: |
94d8186a | 2400 | hw->phy.ops.release(hw); |
4662e82b BA |
2401 | return ret_val; |
2402 | } | |
2403 | ||
2404 | /** | |
2405 | * e1000e_write_phy_reg_bm2 - Write BM PHY register | |
2406 | * @hw: pointer to the HW structure | |
2407 | * @offset: register offset to write to | |
2408 | * @data: data to write at register offset | |
2409 | * | |
2410 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
2411 | * at the offset. Release any acquired semaphores before exiting. | |
2412 | **/ | |
2413 | s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) | |
2414 | { | |
2415 | s32 ret_val; | |
2416 | u16 page = (u16)(offset >> IGP_PAGE_SHIFT); | |
2417 | ||
94d8186a | 2418 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2419 | if (ret_val) |
2420 | return ret_val; | |
2421 | ||
4662e82b BA |
2422 | /* Page 800 works differently than the rest so it has its own func */ |
2423 | if (page == BM_WUC_PAGE) { | |
2424 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, | |
2425 | false); | |
5ccdcecb | 2426 | goto out; |
4662e82b BA |
2427 | } |
2428 | ||
4662e82b BA |
2429 | hw->phy.addr = 1; |
2430 | ||
2431 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2432 | /* Page is shifted left, PHY expects (page x 32) */ | |
2433 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, | |
2434 | page); | |
2435 | ||
5ccdcecb BA |
2436 | if (ret_val) |
2437 | goto out; | |
4662e82b BA |
2438 | } |
2439 | ||
2440 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2441 | data); | |
2442 | ||
5ccdcecb | 2443 | out: |
94d8186a | 2444 | hw->phy.ops.release(hw); |
4662e82b BA |
2445 | return ret_val; |
2446 | } | |
2447 | ||
97ac8cae BA |
2448 | /** |
2449 | * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register | |
2450 | * @hw: pointer to the HW structure | |
2451 | * @offset: register offset to be read or written | |
2452 | * @data: pointer to the data to read or write | |
2453 | * @read: determines if operation is read or write | |
2454 | * | |
2455 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
2456 | * and storing the retrieved information in data. Release any acquired | |
2457 | * semaphores before exiting. Note that procedure to read the wakeup | |
2458 | * registers are different. It works as such: | |
2459 | * 1) Set page 769, register 17, bit 2 = 1 | |
2460 | * 2) Set page to 800 for host (801 if we were manageability) | |
2461 | * 3) Write the address using the address opcode (0x11) | |
2462 | * 4) Read or write the data using the data opcode (0x12) | |
2463 | * 5) Restore 769_17.2 to its original value | |
5ccdcecb BA |
2464 | * |
2465 | * Assumes semaphore already acquired. | |
97ac8cae BA |
2466 | **/ |
2467 | static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, | |
2468 | u16 *data, bool read) | |
2469 | { | |
2470 | s32 ret_val; | |
a4f58f54 | 2471 | u16 reg = BM_PHY_REG_NUM(offset); |
97ac8cae | 2472 | u16 phy_reg = 0; |
97ac8cae | 2473 | |
a4f58f54 BA |
2474 | /* Gig must be disabled for MDIO accesses to page 800 */ |
2475 | if ((hw->mac.type == e1000_pchlan) && | |
2476 | (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) | |
3bb99fe2 | 2477 | e_dbg("Attempting to access page 800 while gig enabled\n"); |
a4f58f54 | 2478 | |
97ac8cae BA |
2479 | /* All operations in this function are phy address 1 */ |
2480 | hw->phy.addr = 1; | |
2481 | ||
2482 | /* Set page 769 */ | |
2483 | e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, | |
2484 | (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); | |
2485 | ||
2486 | ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); | |
2487 | if (ret_val) | |
2488 | goto out; | |
2489 | ||
2490 | /* First clear bit 4 to avoid a power state change */ | |
2491 | phy_reg &= ~(BM_WUC_HOST_WU_BIT); | |
2492 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); | |
2493 | if (ret_val) | |
2494 | goto out; | |
2495 | ||
2496 | /* Write bit 2 = 1, and clear bit 4 to 769_17 */ | |
2497 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, | |
2498 | phy_reg | BM_WUC_ENABLE_BIT); | |
2499 | if (ret_val) | |
2500 | goto out; | |
2501 | ||
2502 | /* Select page 800 */ | |
2503 | ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, | |
2504 | (BM_WUC_PAGE << IGP_PAGE_SHIFT)); | |
2505 | ||
2506 | /* Write the page 800 offset value using opcode 0x11 */ | |
2507 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); | |
2508 | if (ret_val) | |
2509 | goto out; | |
2510 | ||
2511 | if (read) { | |
2512 | /* Read the page 800 value using opcode 0x12 */ | |
2513 | ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, | |
2514 | data); | |
2515 | } else { | |
2516 | /* Read the page 800 value using opcode 0x12 */ | |
2517 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, | |
2518 | *data); | |
2519 | } | |
2520 | ||
2521 | if (ret_val) | |
2522 | goto out; | |
2523 | ||
2524 | /* | |
2525 | * Restore 769_17.2 to its original value | |
2526 | * Set page 769 | |
2527 | */ | |
2528 | e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, | |
2529 | (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); | |
2530 | ||
2531 | /* Clear 769_17.2 */ | |
2532 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); | |
2533 | ||
2534 | out: | |
97ac8cae BA |
2535 | return ret_val; |
2536 | } | |
2537 | ||
bc7f75fa AK |
2538 | /** |
2539 | * e1000e_commit_phy - Soft PHY reset | |
2540 | * @hw: pointer to the HW structure | |
2541 | * | |
2542 | * Performs a soft PHY reset on those that apply. This is a function pointer | |
2543 | * entry point called by drivers. | |
2544 | **/ | |
2545 | s32 e1000e_commit_phy(struct e1000_hw *hw) | |
2546 | { | |
94d8186a BA |
2547 | if (hw->phy.ops.commit) |
2548 | return hw->phy.ops.commit(hw); | |
bc7f75fa AK |
2549 | |
2550 | return 0; | |
2551 | } | |
2552 | ||
2553 | /** | |
2554 | * e1000_set_d0_lplu_state - Sets low power link up state for D0 | |
2555 | * @hw: pointer to the HW structure | |
2556 | * @active: boolean used to enable/disable lplu | |
2557 | * | |
2558 | * Success returns 0, Failure returns 1 | |
2559 | * | |
2560 | * The low power link up (lplu) state is set to the power management level D0 | |
2561 | * and SmartSpeed is disabled when active is true, else clear lplu for D0 | |
2562 | * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU | |
2563 | * is used during Dx states where the power conservation is most important. | |
2564 | * During driver activity, SmartSpeed should be enabled so performance is | |
2565 | * maintained. This is a function pointer entry point called by drivers. | |
2566 | **/ | |
2567 | static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) | |
2568 | { | |
2569 | if (hw->phy.ops.set_d0_lplu_state) | |
2570 | return hw->phy.ops.set_d0_lplu_state(hw, active); | |
2571 | ||
2572 | return 0; | |
2573 | } | |
a4f58f54 | 2574 | |
5ccdcecb BA |
2575 | /** |
2576 | * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode | |
2577 | * @hw: pointer to the HW structure | |
2578 | * @slow: true for slow mode, false for normal mode | |
2579 | * | |
2580 | * Assumes semaphore already acquired. | |
2581 | **/ | |
a4f58f54 BA |
2582 | s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow) |
2583 | { | |
2584 | s32 ret_val = 0; | |
2585 | u16 data = 0; | |
2586 | ||
a4f58f54 BA |
2587 | /* Set MDIO mode - page 769, register 16: 0x2580==slow, 0x2180==fast */ |
2588 | hw->phy.addr = 1; | |
2589 | ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, | |
2590 | (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); | |
5ccdcecb BA |
2591 | if (ret_val) |
2592 | goto out; | |
2593 | ||
a4f58f54 BA |
2594 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_CS_CTRL1, |
2595 | (0x2180 | (slow << 10))); | |
5ccdcecb BA |
2596 | if (ret_val) |
2597 | goto out; | |
a4f58f54 BA |
2598 | |
2599 | /* dummy read when reverting to fast mode - throw away result */ | |
2600 | if (!slow) | |
5ccdcecb | 2601 | ret_val = e1000e_read_phy_reg_mdic(hw, BM_CS_CTRL1, &data); |
a4f58f54 | 2602 | |
5ccdcecb | 2603 | out: |
a4f58f54 BA |
2604 | return ret_val; |
2605 | } | |
2606 | ||
2607 | /** | |
5ccdcecb | 2608 | * __e1000_read_phy_reg_hv - Read HV PHY register |
a4f58f54 BA |
2609 | * @hw: pointer to the HW structure |
2610 | * @offset: register offset to be read | |
2611 | * @data: pointer to the read data | |
5ccdcecb | 2612 | * @locked: semaphore has already been acquired or not |
a4f58f54 BA |
2613 | * |
2614 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
5ccdcecb | 2615 | * and stores the retrieved information in data. Release any acquired |
a4f58f54 BA |
2616 | * semaphore before exiting. |
2617 | **/ | |
5ccdcecb BA |
2618 | static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, |
2619 | bool locked) | |
a4f58f54 BA |
2620 | { |
2621 | s32 ret_val; | |
2622 | u16 page = BM_PHY_REG_PAGE(offset); | |
2623 | u16 reg = BM_PHY_REG_NUM(offset); | |
2624 | bool in_slow_mode = false; | |
2625 | ||
5ccdcecb | 2626 | if (!locked) { |
94d8186a | 2627 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2628 | if (ret_val) |
2629 | return ret_val; | |
2630 | } | |
2631 | ||
a4f58f54 BA |
2632 | /* Workaround failure in MDIO access while cable is disconnected */ |
2633 | if ((hw->phy.type == e1000_phy_82577) && | |
2634 | !(er32(STATUS) & E1000_STATUS_LU)) { | |
2635 | ret_val = e1000_set_mdio_slow_mode_hv(hw, true); | |
2636 | if (ret_val) | |
2637 | goto out; | |
2638 | ||
2639 | in_slow_mode = true; | |
2640 | } | |
2641 | ||
2642 | /* Page 800 works differently than the rest so it has its own func */ | |
2643 | if (page == BM_WUC_PAGE) { | |
2644 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, | |
2645 | data, true); | |
2646 | goto out; | |
2647 | } | |
2648 | ||
2649 | if (page > 0 && page < HV_INTC_FC_PAGE_START) { | |
2650 | ret_val = e1000_access_phy_debug_regs_hv(hw, offset, | |
2651 | data, true); | |
2652 | goto out; | |
2653 | } | |
2654 | ||
a4f58f54 BA |
2655 | hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
2656 | ||
2657 | if (page == HV_INTC_FC_PAGE_START) | |
2658 | page = 0; | |
2659 | ||
2660 | if (reg > MAX_PHY_MULTI_PAGE_REG) { | |
2661 | if ((hw->phy.type != e1000_phy_82578) || | |
2662 | ((reg != I82578_ADDR_REG) && | |
2663 | (reg != I82578_ADDR_REG + 1))) { | |
2664 | u32 phy_addr = hw->phy.addr; | |
2665 | ||
2666 | hw->phy.addr = 1; | |
2667 | ||
2668 | /* Page is shifted left, PHY expects (page x 32) */ | |
2669 | ret_val = e1000e_write_phy_reg_mdic(hw, | |
2670 | IGP01E1000_PHY_PAGE_SELECT, | |
2671 | (page << IGP_PAGE_SHIFT)); | |
a4f58f54 BA |
2672 | hw->phy.addr = phy_addr; |
2673 | } | |
2674 | } | |
2675 | ||
2676 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, | |
2677 | data); | |
a4f58f54 BA |
2678 | out: |
2679 | /* Revert to MDIO fast mode, if applicable */ | |
2680 | if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) | |
2681 | ret_val = e1000_set_mdio_slow_mode_hv(hw, false); | |
2682 | ||
5ccdcecb | 2683 | if (!locked) |
94d8186a | 2684 | hw->phy.ops.release(hw); |
5ccdcecb | 2685 | |
a4f58f54 BA |
2686 | return ret_val; |
2687 | } | |
2688 | ||
2689 | /** | |
5ccdcecb BA |
2690 | * e1000_read_phy_reg_hv - Read HV PHY register |
2691 | * @hw: pointer to the HW structure | |
2692 | * @offset: register offset to be read | |
2693 | * @data: pointer to the read data | |
2694 | * | |
2695 | * Acquires semaphore then reads the PHY register at offset and stores | |
2696 | * the retrieved information in data. Release the acquired semaphore | |
2697 | * before exiting. | |
2698 | **/ | |
2699 | s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) | |
2700 | { | |
2701 | return __e1000_read_phy_reg_hv(hw, offset, data, false); | |
2702 | } | |
2703 | ||
2704 | /** | |
2705 | * e1000_read_phy_reg_hv_locked - Read HV PHY register | |
2706 | * @hw: pointer to the HW structure | |
2707 | * @offset: register offset to be read | |
2708 | * @data: pointer to the read data | |
2709 | * | |
2710 | * Reads the PHY register at offset and stores the retrieved information | |
2711 | * in data. Assumes semaphore already acquired. | |
2712 | **/ | |
2713 | s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) | |
2714 | { | |
2715 | return __e1000_read_phy_reg_hv(hw, offset, data, true); | |
2716 | } | |
2717 | ||
2718 | /** | |
2719 | * __e1000_write_phy_reg_hv - Write HV PHY register | |
a4f58f54 BA |
2720 | * @hw: pointer to the HW structure |
2721 | * @offset: register offset to write to | |
2722 | * @data: data to write at register offset | |
5ccdcecb | 2723 | * @locked: semaphore has already been acquired or not |
a4f58f54 BA |
2724 | * |
2725 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
2726 | * at the offset. Release any acquired semaphores before exiting. | |
2727 | **/ | |
5ccdcecb BA |
2728 | static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, |
2729 | bool locked) | |
a4f58f54 BA |
2730 | { |
2731 | s32 ret_val; | |
2732 | u16 page = BM_PHY_REG_PAGE(offset); | |
2733 | u16 reg = BM_PHY_REG_NUM(offset); | |
2734 | bool in_slow_mode = false; | |
2735 | ||
5ccdcecb | 2736 | if (!locked) { |
94d8186a | 2737 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2738 | if (ret_val) |
2739 | return ret_val; | |
2740 | } | |
2741 | ||
a4f58f54 BA |
2742 | /* Workaround failure in MDIO access while cable is disconnected */ |
2743 | if ((hw->phy.type == e1000_phy_82577) && | |
2744 | !(er32(STATUS) & E1000_STATUS_LU)) { | |
2745 | ret_val = e1000_set_mdio_slow_mode_hv(hw, true); | |
2746 | if (ret_val) | |
2747 | goto out; | |
2748 | ||
2749 | in_slow_mode = true; | |
2750 | } | |
2751 | ||
2752 | /* Page 800 works differently than the rest so it has its own func */ | |
2753 | if (page == BM_WUC_PAGE) { | |
2754 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, | |
2755 | &data, false); | |
2756 | goto out; | |
2757 | } | |
2758 | ||
2759 | if (page > 0 && page < HV_INTC_FC_PAGE_START) { | |
2760 | ret_val = e1000_access_phy_debug_regs_hv(hw, offset, | |
2761 | &data, false); | |
2762 | goto out; | |
2763 | } | |
2764 | ||
a4f58f54 BA |
2765 | hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
2766 | ||
2767 | if (page == HV_INTC_FC_PAGE_START) | |
2768 | page = 0; | |
2769 | ||
2770 | /* | |
2771 | * Workaround MDIO accesses being disabled after entering IEEE Power | |
2772 | * Down (whenever bit 11 of the PHY Control register is set) | |
2773 | */ | |
2774 | if ((hw->phy.type == e1000_phy_82578) && | |
2775 | (hw->phy.revision >= 1) && | |
2776 | (hw->phy.addr == 2) && | |
2777 | ((MAX_PHY_REG_ADDRESS & reg) == 0) && | |
2778 | (data & (1 << 11))) { | |
2779 | u16 data2 = 0x7EFF; | |
a4f58f54 BA |
2780 | ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, |
2781 | &data2, false); | |
2782 | if (ret_val) | |
2783 | goto out; | |
a4f58f54 BA |
2784 | } |
2785 | ||
2786 | if (reg > MAX_PHY_MULTI_PAGE_REG) { | |
2787 | if ((hw->phy.type != e1000_phy_82578) || | |
2788 | ((reg != I82578_ADDR_REG) && | |
2789 | (reg != I82578_ADDR_REG + 1))) { | |
2790 | u32 phy_addr = hw->phy.addr; | |
2791 | ||
2792 | hw->phy.addr = 1; | |
2793 | ||
2794 | /* Page is shifted left, PHY expects (page x 32) */ | |
2795 | ret_val = e1000e_write_phy_reg_mdic(hw, | |
2796 | IGP01E1000_PHY_PAGE_SELECT, | |
2797 | (page << IGP_PAGE_SHIFT)); | |
a4f58f54 BA |
2798 | hw->phy.addr = phy_addr; |
2799 | } | |
2800 | } | |
2801 | ||
2802 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, | |
2803 | data); | |
a4f58f54 BA |
2804 | |
2805 | out: | |
2806 | /* Revert to MDIO fast mode, if applicable */ | |
2807 | if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) | |
2808 | ret_val = e1000_set_mdio_slow_mode_hv(hw, false); | |
2809 | ||
5ccdcecb | 2810 | if (!locked) |
94d8186a | 2811 | hw->phy.ops.release(hw); |
5ccdcecb | 2812 | |
a4f58f54 BA |
2813 | return ret_val; |
2814 | } | |
2815 | ||
5ccdcecb BA |
2816 | /** |
2817 | * e1000_write_phy_reg_hv - Write HV PHY register | |
2818 | * @hw: pointer to the HW structure | |
2819 | * @offset: register offset to write to | |
2820 | * @data: data to write at register offset | |
2821 | * | |
2822 | * Acquires semaphore then writes the data to PHY register at the offset. | |
2823 | * Release the acquired semaphores before exiting. | |
2824 | **/ | |
2825 | s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) | |
2826 | { | |
2827 | return __e1000_write_phy_reg_hv(hw, offset, data, false); | |
2828 | } | |
2829 | ||
2830 | /** | |
2831 | * e1000_write_phy_reg_hv_locked - Write HV PHY register | |
2832 | * @hw: pointer to the HW structure | |
2833 | * @offset: register offset to write to | |
2834 | * @data: data to write at register offset | |
2835 | * | |
2836 | * Writes the data to PHY register at the offset. Assumes semaphore | |
2837 | * already acquired. | |
2838 | **/ | |
2839 | s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) | |
2840 | { | |
2841 | return __e1000_write_phy_reg_hv(hw, offset, data, true); | |
2842 | } | |
2843 | ||
a4f58f54 BA |
2844 | /** |
2845 | * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page | |
2846 | * @page: page to be accessed | |
2847 | **/ | |
2848 | static u32 e1000_get_phy_addr_for_hv_page(u32 page) | |
2849 | { | |
2850 | u32 phy_addr = 2; | |
2851 | ||
2852 | if (page >= HV_INTC_FC_PAGE_START) | |
2853 | phy_addr = 1; | |
2854 | ||
2855 | return phy_addr; | |
2856 | } | |
2857 | ||
2858 | /** | |
2859 | * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers | |
2860 | * @hw: pointer to the HW structure | |
2861 | * @offset: register offset to be read or written | |
2862 | * @data: pointer to the data to be read or written | |
2863 | * @read: determines if operation is read or written | |
2864 | * | |
5ccdcecb BA |
2865 | * Reads the PHY register at offset and stores the retreived information |
2866 | * in data. Assumes semaphore already acquired. Note that the procedure | |
2867 | * to read these regs uses the address port and data port to read/write. | |
a4f58f54 BA |
2868 | **/ |
2869 | static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, | |
2870 | u16 *data, bool read) | |
2871 | { | |
2872 | s32 ret_val; | |
2873 | u32 addr_reg = 0; | |
2874 | u32 data_reg = 0; | |
a4f58f54 BA |
2875 | |
2876 | /* This takes care of the difference with desktop vs mobile phy */ | |
2877 | addr_reg = (hw->phy.type == e1000_phy_82578) ? | |
2878 | I82578_ADDR_REG : I82577_ADDR_REG; | |
2879 | data_reg = addr_reg + 1; | |
2880 | ||
a4f58f54 BA |
2881 | /* All operations in this function are phy address 2 */ |
2882 | hw->phy.addr = 2; | |
2883 | ||
2884 | /* masking with 0x3F to remove the page from offset */ | |
2885 | ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); | |
2886 | if (ret_val) { | |
3bb99fe2 | 2887 | e_dbg("Could not write PHY the HV address register\n"); |
a4f58f54 BA |
2888 | goto out; |
2889 | } | |
2890 | ||
2891 | /* Read or write the data value next */ | |
2892 | if (read) | |
2893 | ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data); | |
2894 | else | |
2895 | ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); | |
2896 | ||
2897 | if (ret_val) { | |
3bb99fe2 | 2898 | e_dbg("Could not read data value from HV data register\n"); |
a4f58f54 BA |
2899 | goto out; |
2900 | } | |
2901 | ||
2902 | out: | |
a4f58f54 BA |
2903 | return ret_val; |
2904 | } | |
2905 | ||
2906 | /** | |
2907 | * e1000_link_stall_workaround_hv - Si workaround | |
2908 | * @hw: pointer to the HW structure | |
2909 | * | |
2910 | * This function works around a Si bug where the link partner can get | |
2911 | * a link up indication before the PHY does. If small packets are sent | |
2912 | * by the link partner they can be placed in the packet buffer without | |
2913 | * being properly accounted for by the PHY and will stall preventing | |
2914 | * further packets from being received. The workaround is to clear the | |
2915 | * packet buffer after the PHY detects link up. | |
2916 | **/ | |
2917 | s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) | |
2918 | { | |
2919 | s32 ret_val = 0; | |
2920 | u16 data; | |
2921 | ||
2922 | if (hw->phy.type != e1000_phy_82578) | |
2923 | goto out; | |
2924 | ||
e65fa87c | 2925 | /* Do not apply workaround if in PHY loopback bit 14 set */ |
94d8186a | 2926 | hw->phy.ops.read_reg(hw, PHY_CONTROL, &data); |
e65fa87c BA |
2927 | if (data & PHY_CONTROL_LB) |
2928 | goto out; | |
2929 | ||
a4f58f54 | 2930 | /* check if link is up and at 1Gbps */ |
94d8186a | 2931 | ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data); |
a4f58f54 BA |
2932 | if (ret_val) |
2933 | goto out; | |
2934 | ||
2935 | data &= BM_CS_STATUS_LINK_UP | | |
2936 | BM_CS_STATUS_RESOLVED | | |
2937 | BM_CS_STATUS_SPEED_MASK; | |
2938 | ||
2939 | if (data != (BM_CS_STATUS_LINK_UP | | |
2940 | BM_CS_STATUS_RESOLVED | | |
2941 | BM_CS_STATUS_SPEED_1000)) | |
2942 | goto out; | |
2943 | ||
2944 | mdelay(200); | |
2945 | ||
2946 | /* flush the packets in the fifo buffer */ | |
94d8186a | 2947 | ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, |
a4f58f54 BA |
2948 | HV_MUX_DATA_CTRL_GEN_TO_MAC | |
2949 | HV_MUX_DATA_CTRL_FORCE_SPEED); | |
2950 | if (ret_val) | |
2951 | goto out; | |
2952 | ||
94d8186a | 2953 | ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, |
a4f58f54 BA |
2954 | HV_MUX_DATA_CTRL_GEN_TO_MAC); |
2955 | ||
2956 | out: | |
2957 | return ret_val; | |
2958 | } | |
2959 | ||
2960 | /** | |
2961 | * e1000_check_polarity_82577 - Checks the polarity. | |
2962 | * @hw: pointer to the HW structure | |
2963 | * | |
2964 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
2965 | * | |
2966 | * Polarity is determined based on the PHY specific status register. | |
2967 | **/ | |
2968 | s32 e1000_check_polarity_82577(struct e1000_hw *hw) | |
2969 | { | |
2970 | struct e1000_phy_info *phy = &hw->phy; | |
2971 | s32 ret_val; | |
2972 | u16 data; | |
2973 | ||
94d8186a | 2974 | ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); |
a4f58f54 BA |
2975 | |
2976 | if (!ret_val) | |
2977 | phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) | |
2978 | ? e1000_rev_polarity_reversed | |
2979 | : e1000_rev_polarity_normal; | |
2980 | ||
2981 | return ret_val; | |
2982 | } | |
2983 | ||
2984 | /** | |
2985 | * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY | |
2986 | * @hw: pointer to the HW structure | |
2987 | * | |
2988 | * Calls the PHY setup function to force speed and duplex. Clears the | |
2989 | * auto-crossover to force MDI manually. Waits for link and returns | |
2990 | * successful if link up is successful, else -E1000_ERR_PHY (-2). | |
2991 | **/ | |
2992 | s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) | |
2993 | { | |
2994 | struct e1000_phy_info *phy = &hw->phy; | |
2995 | s32 ret_val; | |
2996 | u16 phy_data; | |
2997 | bool link; | |
2998 | ||
94d8186a | 2999 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); |
a4f58f54 BA |
3000 | if (ret_val) |
3001 | goto out; | |
3002 | ||
3003 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
3004 | ||
94d8186a | 3005 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); |
a4f58f54 BA |
3006 | if (ret_val) |
3007 | goto out; | |
3008 | ||
3009 | /* | |
3010 | * Clear Auto-Crossover to force MDI manually. 82577 requires MDI | |
3011 | * forced whenever speed and duplex are forced. | |
3012 | */ | |
94d8186a | 3013 | ret_val = phy->ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data); |
a4f58f54 BA |
3014 | if (ret_val) |
3015 | goto out; | |
3016 | ||
3017 | phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX; | |
3018 | phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX; | |
3019 | ||
94d8186a | 3020 | ret_val = phy->ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data); |
a4f58f54 BA |
3021 | if (ret_val) |
3022 | goto out; | |
3023 | ||
3bb99fe2 | 3024 | e_dbg("I82577_PHY_CTRL_2: %X\n", phy_data); |
a4f58f54 BA |
3025 | |
3026 | udelay(1); | |
3027 | ||
3028 | if (phy->autoneg_wait_to_complete) { | |
3bb99fe2 | 3029 | e_dbg("Waiting for forced speed/duplex link on 82577 phy\n"); |
a4f58f54 BA |
3030 | |
3031 | ret_val = e1000e_phy_has_link_generic(hw, | |
3032 | PHY_FORCE_LIMIT, | |
3033 | 100000, | |
3034 | &link); | |
3035 | if (ret_val) | |
3036 | goto out; | |
3037 | ||
3038 | if (!link) | |
3bb99fe2 | 3039 | e_dbg("Link taking longer than expected.\n"); |
a4f58f54 BA |
3040 | |
3041 | /* Try once more */ | |
3042 | ret_val = e1000e_phy_has_link_generic(hw, | |
3043 | PHY_FORCE_LIMIT, | |
3044 | 100000, | |
3045 | &link); | |
3046 | if (ret_val) | |
3047 | goto out; | |
3048 | } | |
3049 | ||
3050 | out: | |
3051 | return ret_val; | |
3052 | } | |
3053 | ||
3054 | /** | |
3055 | * e1000_get_phy_info_82577 - Retrieve I82577 PHY information | |
3056 | * @hw: pointer to the HW structure | |
3057 | * | |
3058 | * Read PHY status to determine if link is up. If link is up, then | |
3059 | * set/determine 10base-T extended distance and polarity correction. Read | |
3060 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, | |
3061 | * determine on the cable length, local and remote receiver. | |
3062 | **/ | |
3063 | s32 e1000_get_phy_info_82577(struct e1000_hw *hw) | |
3064 | { | |
3065 | struct e1000_phy_info *phy = &hw->phy; | |
3066 | s32 ret_val; | |
3067 | u16 data; | |
3068 | bool link; | |
3069 | ||
3070 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
3071 | if (ret_val) | |
3072 | goto out; | |
3073 | ||
3074 | if (!link) { | |
3bb99fe2 | 3075 | e_dbg("Phy info is only valid if link is up\n"); |
a4f58f54 BA |
3076 | ret_val = -E1000_ERR_CONFIG; |
3077 | goto out; | |
3078 | } | |
3079 | ||
3080 | phy->polarity_correction = true; | |
3081 | ||
3082 | ret_val = e1000_check_polarity_82577(hw); | |
3083 | if (ret_val) | |
3084 | goto out; | |
3085 | ||
94d8186a | 3086 | ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); |
a4f58f54 BA |
3087 | if (ret_val) |
3088 | goto out; | |
3089 | ||
3090 | phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false; | |
3091 | ||
3092 | if ((data & I82577_PHY_STATUS2_SPEED_MASK) == | |
3093 | I82577_PHY_STATUS2_SPEED_1000MBPS) { | |
3094 | ret_val = hw->phy.ops.get_cable_length(hw); | |
3095 | if (ret_val) | |
3096 | goto out; | |
3097 | ||
94d8186a | 3098 | ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); |
a4f58f54 BA |
3099 | if (ret_val) |
3100 | goto out; | |
3101 | ||
3102 | phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) | |
3103 | ? e1000_1000t_rx_status_ok | |
3104 | : e1000_1000t_rx_status_not_ok; | |
3105 | ||
3106 | phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) | |
3107 | ? e1000_1000t_rx_status_ok | |
3108 | : e1000_1000t_rx_status_not_ok; | |
3109 | } else { | |
3110 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
3111 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
3112 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
3113 | } | |
3114 | ||
3115 | out: | |
3116 | return ret_val; | |
3117 | } | |
3118 | ||
3119 | /** | |
3120 | * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY | |
3121 | * @hw: pointer to the HW structure | |
3122 | * | |
3123 | * Reads the diagnostic status register and verifies result is valid before | |
3124 | * placing it in the phy_cable_length field. | |
3125 | **/ | |
3126 | s32 e1000_get_cable_length_82577(struct e1000_hw *hw) | |
3127 | { | |
3128 | struct e1000_phy_info *phy = &hw->phy; | |
3129 | s32 ret_val; | |
3130 | u16 phy_data, length; | |
3131 | ||
94d8186a | 3132 | ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); |
a4f58f54 BA |
3133 | if (ret_val) |
3134 | goto out; | |
3135 | ||
3136 | length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> | |
3137 | I82577_DSTATUS_CABLE_LENGTH_SHIFT; | |
3138 | ||
3139 | if (length == E1000_CABLE_LENGTH_UNDEFINED) | |
98086a95 | 3140 | ret_val = -E1000_ERR_PHY; |
a4f58f54 BA |
3141 | |
3142 | phy->cable_length = length; | |
3143 | ||
3144 | out: | |
3145 | return ret_val; | |
3146 | } |