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Commit | Line | Data |
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c0c050c5 MC |
1 | /* Broadcom NetXtreme-C/E network driver. |
2 | * | |
11f15ed3 | 3 | * Copyright (c) 2014-2016 Broadcom Corporation |
c6cc32a2 | 4 | * Copyright (c) 2016-2019 Broadcom Limited |
c0c050c5 MC |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | ||
13 | #include <linux/stringify.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/timer.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/ioport.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/vmalloc.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/etherdevice.h> | |
24 | #include <linux/skbuff.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/bitops.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/irq.h> | |
29 | #include <linux/delay.h> | |
30 | #include <asm/byteorder.h> | |
31 | #include <asm/page.h> | |
32 | #include <linux/time.h> | |
33 | #include <linux/mii.h> | |
0ca12be9 | 34 | #include <linux/mdio.h> |
c0c050c5 MC |
35 | #include <linux/if.h> |
36 | #include <linux/if_vlan.h> | |
32e8239c | 37 | #include <linux/if_bridge.h> |
5ac67d8b | 38 | #include <linux/rtc.h> |
c6d30e83 | 39 | #include <linux/bpf.h> |
c0c050c5 MC |
40 | #include <net/ip.h> |
41 | #include <net/tcp.h> | |
42 | #include <net/udp.h> | |
43 | #include <net/checksum.h> | |
44 | #include <net/ip6_checksum.h> | |
ad51b8e9 | 45 | #include <net/udp_tunnel.h> |
c0c050c5 MC |
46 | #include <linux/workqueue.h> |
47 | #include <linux/prefetch.h> | |
48 | #include <linux/cache.h> | |
49 | #include <linux/log2.h> | |
50 | #include <linux/aer.h> | |
51 | #include <linux/bitmap.h> | |
52 | #include <linux/cpu_rmap.h> | |
56f0fd80 | 53 | #include <linux/cpumask.h> |
2ae7408f | 54 | #include <net/pkt_cls.h> |
cde49a42 VV |
55 | #include <linux/hwmon.h> |
56 | #include <linux/hwmon-sysfs.h> | |
322b87ca | 57 | #include <net/page_pool.h> |
c0c050c5 MC |
58 | |
59 | #include "bnxt_hsi.h" | |
60 | #include "bnxt.h" | |
a588e458 | 61 | #include "bnxt_ulp.h" |
c0c050c5 MC |
62 | #include "bnxt_sriov.h" |
63 | #include "bnxt_ethtool.h" | |
7df4ae9f | 64 | #include "bnxt_dcb.h" |
c6d30e83 | 65 | #include "bnxt_xdp.h" |
4ab0c6a8 | 66 | #include "bnxt_vfr.h" |
2ae7408f | 67 | #include "bnxt_tc.h" |
3c467bf3 | 68 | #include "bnxt_devlink.h" |
cabfb09d | 69 | #include "bnxt_debugfs.h" |
c0c050c5 MC |
70 | |
71 | #define BNXT_TX_TIMEOUT (5 * HZ) | |
72 | ||
c0c050c5 MC |
73 | MODULE_LICENSE("GPL"); |
74 | MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); | |
c0c050c5 MC |
75 | |
76 | #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) | |
77 | #define BNXT_RX_DMA_OFFSET NET_SKB_PAD | |
78 | #define BNXT_RX_COPY_THRESH 256 | |
79 | ||
4419dbe6 | 80 | #define BNXT_TX_PUSH_THRESH 164 |
c0c050c5 MC |
81 | |
82 | enum board_idx { | |
fbc9a523 | 83 | BCM57301, |
c0c050c5 MC |
84 | BCM57302, |
85 | BCM57304, | |
1f681688 | 86 | BCM57417_NPAR, |
fa853dda | 87 | BCM58700, |
b24eb6ae MC |
88 | BCM57311, |
89 | BCM57312, | |
fbc9a523 | 90 | BCM57402, |
c0c050c5 MC |
91 | BCM57404, |
92 | BCM57406, | |
1f681688 MC |
93 | BCM57402_NPAR, |
94 | BCM57407, | |
b24eb6ae MC |
95 | BCM57412, |
96 | BCM57414, | |
97 | BCM57416, | |
98 | BCM57417, | |
1f681688 | 99 | BCM57412_NPAR, |
5049e33b | 100 | BCM57314, |
1f681688 MC |
101 | BCM57417_SFP, |
102 | BCM57416_SFP, | |
103 | BCM57404_NPAR, | |
104 | BCM57406_NPAR, | |
105 | BCM57407_SFP, | |
adbc8305 | 106 | BCM57407_NPAR, |
1f681688 MC |
107 | BCM57414_NPAR, |
108 | BCM57416_NPAR, | |
32b40798 DK |
109 | BCM57452, |
110 | BCM57454, | |
92abef36 | 111 | BCM5745x_NPAR, |
1ab968d2 | 112 | BCM57508, |
c6cc32a2 | 113 | BCM57504, |
51fec80d | 114 | BCM57502, |
49c98421 MC |
115 | BCM57508_NPAR, |
116 | BCM57504_NPAR, | |
117 | BCM57502_NPAR, | |
4a58139b | 118 | BCM58802, |
8ed693b7 | 119 | BCM58804, |
4a58139b | 120 | BCM58808, |
adbc8305 MC |
121 | NETXTREME_E_VF, |
122 | NETXTREME_C_VF, | |
618784e3 | 123 | NETXTREME_S_VF, |
b16b6891 | 124 | NETXTREME_E_P5_VF, |
c0c050c5 MC |
125 | }; |
126 | ||
127 | /* indexed by enum above */ | |
128 | static const struct { | |
129 | char *name; | |
130 | } board_info[] = { | |
27573a7d SB |
131 | [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" }, |
132 | [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" }, | |
133 | [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, | |
134 | [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" }, | |
135 | [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" }, | |
136 | [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" }, | |
137 | [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" }, | |
138 | [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" }, | |
139 | [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" }, | |
140 | [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" }, | |
141 | [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" }, | |
142 | [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" }, | |
143 | [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" }, | |
144 | [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" }, | |
145 | [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" }, | |
146 | [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" }, | |
147 | [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" }, | |
148 | [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, | |
149 | [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" }, | |
150 | [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" }, | |
151 | [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" }, | |
152 | [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" }, | |
153 | [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" }, | |
154 | [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" }, | |
155 | [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" }, | |
156 | [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" }, | |
157 | [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" }, | |
158 | [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, | |
92abef36 | 159 | [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" }, |
1ab968d2 | 160 | [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, |
c6cc32a2 | 161 | [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, |
51fec80d | 162 | [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" }, |
49c98421 MC |
163 | [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" }, |
164 | [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" }, | |
165 | [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" }, | |
27573a7d | 166 | [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" }, |
8ed693b7 | 167 | [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, |
27573a7d SB |
168 | [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, |
169 | [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" }, | |
170 | [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" }, | |
618784e3 | 171 | [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" }, |
b16b6891 | 172 | [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" }, |
c0c050c5 MC |
173 | }; |
174 | ||
175 | static const struct pci_device_id bnxt_pci_tbl[] = { | |
92abef36 VV |
176 | { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR }, |
177 | { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR }, | |
4a58139b | 178 | { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 }, |
adbc8305 | 179 | { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR }, |
fbc9a523 | 180 | { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, |
c0c050c5 MC |
181 | { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, |
182 | { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, | |
1f681688 | 183 | { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR }, |
fa853dda | 184 | { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 }, |
b24eb6ae MC |
185 | { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 }, |
186 | { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 }, | |
fbc9a523 | 187 | { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, |
c0c050c5 MC |
188 | { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, |
189 | { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, | |
1f681688 MC |
190 | { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR }, |
191 | { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 }, | |
b24eb6ae MC |
192 | { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 }, |
193 | { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 }, | |
194 | { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 }, | |
195 | { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 }, | |
1f681688 | 196 | { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR }, |
5049e33b | 197 | { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 }, |
1f681688 MC |
198 | { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP }, |
199 | { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP }, | |
200 | { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR }, | |
201 | { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR }, | |
202 | { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP }, | |
adbc8305 MC |
203 | { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR }, |
204 | { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR }, | |
1f681688 | 205 | { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR }, |
adbc8305 | 206 | { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR }, |
1f681688 | 207 | { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR }, |
adbc8305 | 208 | { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR }, |
4a58139b | 209 | { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 }, |
32b40798 | 210 | { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 }, |
1ab968d2 | 211 | { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 }, |
c6cc32a2 | 212 | { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 }, |
51fec80d | 213 | { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 }, |
49c98421 MC |
214 | { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57508_NPAR }, |
215 | { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR }, | |
216 | { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57502_NPAR }, | |
217 | { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57508_NPAR }, | |
218 | { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR }, | |
219 | { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57502_NPAR }, | |
4a58139b | 220 | { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 }, |
8ed693b7 | 221 | { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 }, |
c0c050c5 | 222 | #ifdef CONFIG_BNXT_SRIOV |
c7ef35eb DK |
223 | { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF }, |
224 | { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF }, | |
adbc8305 MC |
225 | { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF }, |
226 | { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF }, | |
227 | { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF }, | |
228 | { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF }, | |
229 | { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF }, | |
230 | { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF }, | |
51fec80d | 231 | { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF }, |
b16b6891 | 232 | { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF }, |
618784e3 | 233 | { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF }, |
c0c050c5 MC |
234 | #endif |
235 | { 0 } | |
236 | }; | |
237 | ||
238 | MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); | |
239 | ||
240 | static const u16 bnxt_vf_req_snif[] = { | |
241 | HWRM_FUNC_CFG, | |
91cdda40 | 242 | HWRM_FUNC_VF_CFG, |
c0c050c5 MC |
243 | HWRM_PORT_PHY_QCFG, |
244 | HWRM_CFA_L2_FILTER_ALLOC, | |
245 | }; | |
246 | ||
25be8623 | 247 | static const u16 bnxt_async_events_arr[] = { |
87c374de | 248 | ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, |
b1613e78 | 249 | ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE, |
87c374de MC |
250 | ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD, |
251 | ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED, | |
252 | ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE, | |
253 | ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, | |
b1613e78 | 254 | ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE, |
2151fe08 | 255 | ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY, |
7e914027 | 256 | ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY, |
25be8623 MC |
257 | }; |
258 | ||
c213eae8 MC |
259 | static struct workqueue_struct *bnxt_pf_wq; |
260 | ||
c0c050c5 MC |
261 | static bool bnxt_vf_pciid(enum board_idx idx) |
262 | { | |
618784e3 | 263 | return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF || |
b16b6891 | 264 | idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF); |
c0c050c5 MC |
265 | } |
266 | ||
267 | #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) | |
268 | #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) | |
269 | #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) | |
270 | ||
c0c050c5 MC |
271 | #define BNXT_CP_DB_IRQ_DIS(db) \ |
272 | writel(DB_CP_IRQ_DIS_FLAGS, db) | |
273 | ||
697197e5 MC |
274 | #define BNXT_DB_CQ(db, idx) \ |
275 | writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell) | |
276 | ||
277 | #define BNXT_DB_NQ_P5(db, idx) \ | |
278 | writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell) | |
279 | ||
280 | #define BNXT_DB_CQ_ARM(db, idx) \ | |
281 | writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell) | |
282 | ||
283 | #define BNXT_DB_NQ_ARM_P5(db, idx) \ | |
284 | writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell) | |
285 | ||
286 | static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) | |
287 | { | |
288 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
289 | BNXT_DB_NQ_P5(db, idx); | |
290 | else | |
291 | BNXT_DB_CQ(db, idx); | |
292 | } | |
293 | ||
294 | static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) | |
295 | { | |
296 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
297 | BNXT_DB_NQ_ARM_P5(db, idx); | |
298 | else | |
299 | BNXT_DB_CQ_ARM(db, idx); | |
300 | } | |
301 | ||
302 | static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) | |
303 | { | |
304 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
305 | writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx), | |
306 | db->doorbell); | |
307 | else | |
308 | BNXT_DB_CQ(db, idx); | |
309 | } | |
310 | ||
38413406 | 311 | const u16 bnxt_lhint_arr[] = { |
c0c050c5 MC |
312 | TX_BD_FLAGS_LHINT_512_AND_SMALLER, |
313 | TX_BD_FLAGS_LHINT_512_TO_1023, | |
314 | TX_BD_FLAGS_LHINT_1024_TO_2047, | |
315 | TX_BD_FLAGS_LHINT_1024_TO_2047, | |
316 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
317 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
318 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
319 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
320 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
321 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
322 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
323 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
324 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
325 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
326 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
327 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
328 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
329 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
330 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
331 | }; | |
332 | ||
ee5c7fb3 SP |
333 | static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb) |
334 | { | |
335 | struct metadata_dst *md_dst = skb_metadata_dst(skb); | |
336 | ||
337 | if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX) | |
338 | return 0; | |
339 | ||
340 | return md_dst->u.port_info.port_id; | |
341 | } | |
342 | ||
c0c050c5 MC |
343 | static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) |
344 | { | |
345 | struct bnxt *bp = netdev_priv(dev); | |
346 | struct tx_bd *txbd; | |
347 | struct tx_bd_ext *txbd1; | |
348 | struct netdev_queue *txq; | |
349 | int i; | |
350 | dma_addr_t mapping; | |
351 | unsigned int length, pad = 0; | |
352 | u32 len, free_size, vlan_tag_flags, cfa_action, flags; | |
353 | u16 prod, last_frag; | |
354 | struct pci_dev *pdev = bp->pdev; | |
c0c050c5 MC |
355 | struct bnxt_tx_ring_info *txr; |
356 | struct bnxt_sw_tx_bd *tx_buf; | |
357 | ||
358 | i = skb_get_queue_mapping(skb); | |
359 | if (unlikely(i >= bp->tx_nr_rings)) { | |
360 | dev_kfree_skb_any(skb); | |
361 | return NETDEV_TX_OK; | |
362 | } | |
363 | ||
c0c050c5 | 364 | txq = netdev_get_tx_queue(dev, i); |
a960dec9 | 365 | txr = &bp->tx_ring[bp->tx_ring_map[i]]; |
c0c050c5 MC |
366 | prod = txr->tx_prod; |
367 | ||
368 | free_size = bnxt_tx_avail(bp, txr); | |
369 | if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { | |
370 | netif_tx_stop_queue(txq); | |
371 | return NETDEV_TX_BUSY; | |
372 | } | |
373 | ||
374 | length = skb->len; | |
375 | len = skb_headlen(skb); | |
376 | last_frag = skb_shinfo(skb)->nr_frags; | |
377 | ||
378 | txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; | |
379 | ||
380 | txbd->tx_bd_opaque = prod; | |
381 | ||
382 | tx_buf = &txr->tx_buf_ring[prod]; | |
383 | tx_buf->skb = skb; | |
384 | tx_buf->nr_frags = last_frag; | |
385 | ||
386 | vlan_tag_flags = 0; | |
ee5c7fb3 | 387 | cfa_action = bnxt_xmit_get_cfa_action(skb); |
c0c050c5 MC |
388 | if (skb_vlan_tag_present(skb)) { |
389 | vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | | |
390 | skb_vlan_tag_get(skb); | |
391 | /* Currently supports 8021Q, 8021AD vlan offloads | |
392 | * QINQ1, QINQ2, QINQ3 vlan headers are deprecated | |
393 | */ | |
394 | if (skb->vlan_proto == htons(ETH_P_8021Q)) | |
395 | vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; | |
396 | } | |
397 | ||
398 | if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) { | |
4419dbe6 MC |
399 | struct tx_push_buffer *tx_push_buf = txr->tx_push; |
400 | struct tx_push_bd *tx_push = &tx_push_buf->push_bd; | |
401 | struct tx_bd_ext *tx_push1 = &tx_push->txbd2; | |
697197e5 | 402 | void __iomem *db = txr->tx_db.doorbell; |
4419dbe6 MC |
403 | void *pdata = tx_push_buf->data; |
404 | u64 *end; | |
405 | int j, push_len; | |
c0c050c5 MC |
406 | |
407 | /* Set COAL_NOW to be ready quickly for the next push */ | |
408 | tx_push->tx_bd_len_flags_type = | |
409 | cpu_to_le32((length << TX_BD_LEN_SHIFT) | | |
410 | TX_BD_TYPE_LONG_TX_BD | | |
411 | TX_BD_FLAGS_LHINT_512_AND_SMALLER | | |
412 | TX_BD_FLAGS_COAL_NOW | | |
413 | TX_BD_FLAGS_PACKET_END | | |
414 | (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); | |
415 | ||
416 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
417 | tx_push1->tx_bd_hsize_lflags = | |
418 | cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); | |
419 | else | |
420 | tx_push1->tx_bd_hsize_lflags = 0; | |
421 | ||
422 | tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); | |
ee5c7fb3 SP |
423 | tx_push1->tx_bd_cfa_action = |
424 | cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); | |
c0c050c5 | 425 | |
fbb0fa8b MC |
426 | end = pdata + length; |
427 | end = PTR_ALIGN(end, 8) - 1; | |
4419dbe6 MC |
428 | *end = 0; |
429 | ||
c0c050c5 MC |
430 | skb_copy_from_linear_data(skb, pdata, len); |
431 | pdata += len; | |
432 | for (j = 0; j < last_frag; j++) { | |
433 | skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; | |
434 | void *fptr; | |
435 | ||
436 | fptr = skb_frag_address_safe(frag); | |
437 | if (!fptr) | |
438 | goto normal_tx; | |
439 | ||
440 | memcpy(pdata, fptr, skb_frag_size(frag)); | |
441 | pdata += skb_frag_size(frag); | |
442 | } | |
443 | ||
4419dbe6 MC |
444 | txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type; |
445 | txbd->tx_bd_haddr = txr->data_mapping; | |
c0c050c5 MC |
446 | prod = NEXT_TX(prod); |
447 | txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; | |
448 | memcpy(txbd, tx_push1, sizeof(*txbd)); | |
449 | prod = NEXT_TX(prod); | |
4419dbe6 | 450 | tx_push->doorbell = |
c0c050c5 MC |
451 | cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); |
452 | txr->tx_prod = prod; | |
453 | ||
b9a8460a | 454 | tx_buf->is_push = 1; |
c0c050c5 | 455 | netdev_tx_sent_queue(txq, skb->len); |
b9a8460a | 456 | wmb(); /* Sync is_push and byte queue before pushing data */ |
c0c050c5 | 457 | |
4419dbe6 MC |
458 | push_len = (length + sizeof(*tx_push) + 7) / 8; |
459 | if (push_len > 16) { | |
697197e5 MC |
460 | __iowrite64_copy(db, tx_push_buf, 16); |
461 | __iowrite32_copy(db + 4, tx_push_buf + 1, | |
9d13744b | 462 | (push_len - 16) << 1); |
4419dbe6 | 463 | } else { |
697197e5 | 464 | __iowrite64_copy(db, tx_push_buf, push_len); |
4419dbe6 | 465 | } |
c0c050c5 | 466 | |
c0c050c5 MC |
467 | goto tx_done; |
468 | } | |
469 | ||
470 | normal_tx: | |
471 | if (length < BNXT_MIN_PKT_SIZE) { | |
472 | pad = BNXT_MIN_PKT_SIZE - length; | |
473 | if (skb_pad(skb, pad)) { | |
474 | /* SKB already freed. */ | |
475 | tx_buf->skb = NULL; | |
476 | return NETDEV_TX_OK; | |
477 | } | |
478 | length = BNXT_MIN_PKT_SIZE; | |
479 | } | |
480 | ||
481 | mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); | |
482 | ||
483 | if (unlikely(dma_mapping_error(&pdev->dev, mapping))) { | |
484 | dev_kfree_skb_any(skb); | |
485 | tx_buf->skb = NULL; | |
486 | return NETDEV_TX_OK; | |
487 | } | |
488 | ||
489 | dma_unmap_addr_set(tx_buf, mapping, mapping); | |
490 | flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | | |
491 | ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); | |
492 | ||
493 | txbd->tx_bd_haddr = cpu_to_le64(mapping); | |
494 | ||
495 | prod = NEXT_TX(prod); | |
496 | txbd1 = (struct tx_bd_ext *) | |
497 | &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; | |
498 | ||
499 | txbd1->tx_bd_hsize_lflags = 0; | |
500 | if (skb_is_gso(skb)) { | |
501 | u32 hdr_len; | |
502 | ||
503 | if (skb->encapsulation) | |
504 | hdr_len = skb_inner_network_offset(skb) + | |
505 | skb_inner_network_header_len(skb) + | |
506 | inner_tcp_hdrlen(skb); | |
507 | else | |
508 | hdr_len = skb_transport_offset(skb) + | |
509 | tcp_hdrlen(skb); | |
510 | ||
511 | txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO | | |
512 | TX_BD_FLAGS_T_IPID | | |
513 | (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); | |
514 | length = skb_shinfo(skb)->gso_size; | |
515 | txbd1->tx_bd_mss = cpu_to_le32(length); | |
516 | length += hdr_len; | |
517 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
518 | txbd1->tx_bd_hsize_lflags = | |
519 | cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); | |
520 | txbd1->tx_bd_mss = 0; | |
521 | } | |
522 | ||
523 | length >>= 9; | |
2b3c6885 MC |
524 | if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) { |
525 | dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n", | |
526 | skb->len); | |
527 | i = 0; | |
528 | goto tx_dma_error; | |
529 | } | |
c0c050c5 MC |
530 | flags |= bnxt_lhint_arr[length]; |
531 | txbd->tx_bd_len_flags_type = cpu_to_le32(flags); | |
532 | ||
533 | txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); | |
ee5c7fb3 SP |
534 | txbd1->tx_bd_cfa_action = |
535 | cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); | |
c0c050c5 MC |
536 | for (i = 0; i < last_frag; i++) { |
537 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
538 | ||
539 | prod = NEXT_TX(prod); | |
540 | txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; | |
541 | ||
542 | len = skb_frag_size(frag); | |
543 | mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, | |
544 | DMA_TO_DEVICE); | |
545 | ||
546 | if (unlikely(dma_mapping_error(&pdev->dev, mapping))) | |
547 | goto tx_dma_error; | |
548 | ||
549 | tx_buf = &txr->tx_buf_ring[prod]; | |
550 | dma_unmap_addr_set(tx_buf, mapping, mapping); | |
551 | ||
552 | txbd->tx_bd_haddr = cpu_to_le64(mapping); | |
553 | ||
554 | flags = len << TX_BD_LEN_SHIFT; | |
555 | txbd->tx_bd_len_flags_type = cpu_to_le32(flags); | |
556 | } | |
557 | ||
558 | flags &= ~TX_BD_LEN; | |
559 | txbd->tx_bd_len_flags_type = | |
560 | cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | | |
561 | TX_BD_FLAGS_PACKET_END); | |
562 | ||
563 | netdev_tx_sent_queue(txq, skb->len); | |
564 | ||
565 | /* Sync BD data before updating doorbell */ | |
566 | wmb(); | |
567 | ||
568 | prod = NEXT_TX(prod); | |
569 | txr->tx_prod = prod; | |
570 | ||
6b16f9ee | 571 | if (!netdev_xmit_more() || netif_xmit_stopped(txq)) |
697197e5 | 572 | bnxt_db_write(bp, &txr->tx_db, prod); |
c0c050c5 MC |
573 | |
574 | tx_done: | |
575 | ||
c0c050c5 | 576 | if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { |
6b16f9ee | 577 | if (netdev_xmit_more() && !tx_buf->is_push) |
697197e5 | 578 | bnxt_db_write(bp, &txr->tx_db, prod); |
4d172f21 | 579 | |
c0c050c5 MC |
580 | netif_tx_stop_queue(txq); |
581 | ||
582 | /* netif_tx_stop_queue() must be done before checking | |
583 | * tx index in bnxt_tx_avail() below, because in | |
584 | * bnxt_tx_int(), we update tx index before checking for | |
585 | * netif_tx_queue_stopped(). | |
586 | */ | |
587 | smp_mb(); | |
588 | if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) | |
589 | netif_tx_wake_queue(txq); | |
590 | } | |
591 | return NETDEV_TX_OK; | |
592 | ||
593 | tx_dma_error: | |
594 | last_frag = i; | |
595 | ||
596 | /* start back at beginning and unmap skb */ | |
597 | prod = txr->tx_prod; | |
598 | tx_buf = &txr->tx_buf_ring[prod]; | |
599 | tx_buf->skb = NULL; | |
600 | dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), | |
601 | skb_headlen(skb), PCI_DMA_TODEVICE); | |
602 | prod = NEXT_TX(prod); | |
603 | ||
604 | /* unmap remaining mapped pages */ | |
605 | for (i = 0; i < last_frag; i++) { | |
606 | prod = NEXT_TX(prod); | |
607 | tx_buf = &txr->tx_buf_ring[prod]; | |
608 | dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), | |
609 | skb_frag_size(&skb_shinfo(skb)->frags[i]), | |
610 | PCI_DMA_TODEVICE); | |
611 | } | |
612 | ||
613 | dev_kfree_skb_any(skb); | |
614 | return NETDEV_TX_OK; | |
615 | } | |
616 | ||
617 | static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) | |
618 | { | |
b6ab4b01 | 619 | struct bnxt_tx_ring_info *txr = bnapi->tx_ring; |
a960dec9 | 620 | struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index); |
c0c050c5 MC |
621 | u16 cons = txr->tx_cons; |
622 | struct pci_dev *pdev = bp->pdev; | |
623 | int i; | |
624 | unsigned int tx_bytes = 0; | |
625 | ||
626 | for (i = 0; i < nr_pkts; i++) { | |
627 | struct bnxt_sw_tx_bd *tx_buf; | |
628 | struct sk_buff *skb; | |
629 | int j, last; | |
630 | ||
631 | tx_buf = &txr->tx_buf_ring[cons]; | |
632 | cons = NEXT_TX(cons); | |
633 | skb = tx_buf->skb; | |
634 | tx_buf->skb = NULL; | |
635 | ||
636 | if (tx_buf->is_push) { | |
637 | tx_buf->is_push = 0; | |
638 | goto next_tx_int; | |
639 | } | |
640 | ||
641 | dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), | |
642 | skb_headlen(skb), PCI_DMA_TODEVICE); | |
643 | last = tx_buf->nr_frags; | |
644 | ||
645 | for (j = 0; j < last; j++) { | |
646 | cons = NEXT_TX(cons); | |
647 | tx_buf = &txr->tx_buf_ring[cons]; | |
648 | dma_unmap_page( | |
649 | &pdev->dev, | |
650 | dma_unmap_addr(tx_buf, mapping), | |
651 | skb_frag_size(&skb_shinfo(skb)->frags[j]), | |
652 | PCI_DMA_TODEVICE); | |
653 | } | |
654 | ||
655 | next_tx_int: | |
656 | cons = NEXT_TX(cons); | |
657 | ||
658 | tx_bytes += skb->len; | |
659 | dev_kfree_skb_any(skb); | |
660 | } | |
661 | ||
662 | netdev_tx_completed_queue(txq, nr_pkts, tx_bytes); | |
663 | txr->tx_cons = cons; | |
664 | ||
665 | /* Need to make the tx_cons update visible to bnxt_start_xmit() | |
666 | * before checking for netif_tx_queue_stopped(). Without the | |
667 | * memory barrier, there is a small possibility that bnxt_start_xmit() | |
668 | * will miss it and cause the queue to be stopped forever. | |
669 | */ | |
670 | smp_mb(); | |
671 | ||
672 | if (unlikely(netif_tx_queue_stopped(txq)) && | |
673 | (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) { | |
674 | __netif_tx_lock(txq, smp_processor_id()); | |
675 | if (netif_tx_queue_stopped(txq) && | |
676 | bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh && | |
677 | txr->dev_state != BNXT_DEV_STATE_CLOSING) | |
678 | netif_tx_wake_queue(txq); | |
679 | __netif_tx_unlock(txq); | |
680 | } | |
681 | } | |
682 | ||
c61fb99c | 683 | static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping, |
322b87ca | 684 | struct bnxt_rx_ring_info *rxr, |
c61fb99c MC |
685 | gfp_t gfp) |
686 | { | |
687 | struct device *dev = &bp->pdev->dev; | |
688 | struct page *page; | |
689 | ||
322b87ca | 690 | page = page_pool_dev_alloc_pages(rxr->page_pool); |
c61fb99c MC |
691 | if (!page) |
692 | return NULL; | |
693 | ||
c519fe9a SN |
694 | *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir, |
695 | DMA_ATTR_WEAK_ORDERING); | |
c61fb99c | 696 | if (dma_mapping_error(dev, *mapping)) { |
322b87ca | 697 | page_pool_recycle_direct(rxr->page_pool, page); |
c61fb99c MC |
698 | return NULL; |
699 | } | |
700 | *mapping += bp->rx_dma_offset; | |
701 | return page; | |
702 | } | |
703 | ||
c0c050c5 MC |
704 | static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping, |
705 | gfp_t gfp) | |
706 | { | |
707 | u8 *data; | |
708 | struct pci_dev *pdev = bp->pdev; | |
709 | ||
710 | data = kmalloc(bp->rx_buf_size, gfp); | |
711 | if (!data) | |
712 | return NULL; | |
713 | ||
c519fe9a SN |
714 | *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset, |
715 | bp->rx_buf_use_size, bp->rx_dir, | |
716 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
717 | |
718 | if (dma_mapping_error(&pdev->dev, *mapping)) { | |
719 | kfree(data); | |
720 | data = NULL; | |
721 | } | |
722 | return data; | |
723 | } | |
724 | ||
38413406 MC |
725 | int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, |
726 | u16 prod, gfp_t gfp) | |
c0c050c5 MC |
727 | { |
728 | struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
729 | struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; | |
c0c050c5 MC |
730 | dma_addr_t mapping; |
731 | ||
c61fb99c | 732 | if (BNXT_RX_PAGE_MODE(bp)) { |
322b87ca AG |
733 | struct page *page = |
734 | __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp); | |
c0c050c5 | 735 | |
c61fb99c MC |
736 | if (!page) |
737 | return -ENOMEM; | |
738 | ||
739 | rx_buf->data = page; | |
740 | rx_buf->data_ptr = page_address(page) + bp->rx_offset; | |
741 | } else { | |
742 | u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp); | |
743 | ||
744 | if (!data) | |
745 | return -ENOMEM; | |
746 | ||
747 | rx_buf->data = data; | |
748 | rx_buf->data_ptr = data + bp->rx_offset; | |
749 | } | |
11cd119d | 750 | rx_buf->mapping = mapping; |
c0c050c5 MC |
751 | |
752 | rxbd->rx_bd_haddr = cpu_to_le64(mapping); | |
c0c050c5 MC |
753 | return 0; |
754 | } | |
755 | ||
c6d30e83 | 756 | void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data) |
c0c050c5 MC |
757 | { |
758 | u16 prod = rxr->rx_prod; | |
759 | struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; | |
760 | struct rx_bd *cons_bd, *prod_bd; | |
761 | ||
762 | prod_rx_buf = &rxr->rx_buf_ring[prod]; | |
763 | cons_rx_buf = &rxr->rx_buf_ring[cons]; | |
764 | ||
765 | prod_rx_buf->data = data; | |
6bb19474 | 766 | prod_rx_buf->data_ptr = cons_rx_buf->data_ptr; |
c0c050c5 | 767 | |
11cd119d | 768 | prod_rx_buf->mapping = cons_rx_buf->mapping; |
c0c050c5 MC |
769 | |
770 | prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
771 | cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; | |
772 | ||
773 | prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; | |
774 | } | |
775 | ||
776 | static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) | |
777 | { | |
778 | u16 next, max = rxr->rx_agg_bmap_size; | |
779 | ||
780 | next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); | |
781 | if (next >= max) | |
782 | next = find_first_zero_bit(rxr->rx_agg_bmap, max); | |
783 | return next; | |
784 | } | |
785 | ||
786 | static inline int bnxt_alloc_rx_page(struct bnxt *bp, | |
787 | struct bnxt_rx_ring_info *rxr, | |
788 | u16 prod, gfp_t gfp) | |
789 | { | |
790 | struct rx_bd *rxbd = | |
791 | &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
792 | struct bnxt_sw_rx_agg_bd *rx_agg_buf; | |
793 | struct pci_dev *pdev = bp->pdev; | |
794 | struct page *page; | |
795 | dma_addr_t mapping; | |
796 | u16 sw_prod = rxr->rx_sw_agg_prod; | |
89d0a06c | 797 | unsigned int offset = 0; |
c0c050c5 | 798 | |
89d0a06c MC |
799 | if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) { |
800 | page = rxr->rx_page; | |
801 | if (!page) { | |
802 | page = alloc_page(gfp); | |
803 | if (!page) | |
804 | return -ENOMEM; | |
805 | rxr->rx_page = page; | |
806 | rxr->rx_page_offset = 0; | |
807 | } | |
808 | offset = rxr->rx_page_offset; | |
809 | rxr->rx_page_offset += BNXT_RX_PAGE_SIZE; | |
810 | if (rxr->rx_page_offset == PAGE_SIZE) | |
811 | rxr->rx_page = NULL; | |
812 | else | |
813 | get_page(page); | |
814 | } else { | |
815 | page = alloc_page(gfp); | |
816 | if (!page) | |
817 | return -ENOMEM; | |
818 | } | |
c0c050c5 | 819 | |
c519fe9a SN |
820 | mapping = dma_map_page_attrs(&pdev->dev, page, offset, |
821 | BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE, | |
822 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
823 | if (dma_mapping_error(&pdev->dev, mapping)) { |
824 | __free_page(page); | |
825 | return -EIO; | |
826 | } | |
827 | ||
828 | if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) | |
829 | sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); | |
830 | ||
831 | __set_bit(sw_prod, rxr->rx_agg_bmap); | |
832 | rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; | |
833 | rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); | |
834 | ||
835 | rx_agg_buf->page = page; | |
89d0a06c | 836 | rx_agg_buf->offset = offset; |
c0c050c5 MC |
837 | rx_agg_buf->mapping = mapping; |
838 | rxbd->rx_bd_haddr = cpu_to_le64(mapping); | |
839 | rxbd->rx_bd_opaque = sw_prod; | |
840 | return 0; | |
841 | } | |
842 | ||
4a228a3a MC |
843 | static struct rx_agg_cmp *bnxt_get_agg(struct bnxt *bp, |
844 | struct bnxt_cp_ring_info *cpr, | |
845 | u16 cp_cons, u16 curr) | |
846 | { | |
847 | struct rx_agg_cmp *agg; | |
848 | ||
849 | cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr)); | |
850 | agg = (struct rx_agg_cmp *) | |
851 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
852 | return agg; | |
853 | } | |
854 | ||
bfcd8d79 MC |
855 | static struct rx_agg_cmp *bnxt_get_tpa_agg_p5(struct bnxt *bp, |
856 | struct bnxt_rx_ring_info *rxr, | |
857 | u16 agg_id, u16 curr) | |
858 | { | |
859 | struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id]; | |
860 | ||
861 | return &tpa_info->agg_arr[curr]; | |
862 | } | |
863 | ||
4a228a3a MC |
864 | static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx, |
865 | u16 start, u32 agg_bufs, bool tpa) | |
c0c050c5 | 866 | { |
e44758b7 | 867 | struct bnxt_napi *bnapi = cpr->bnapi; |
c0c050c5 | 868 | struct bnxt *bp = bnapi->bp; |
b6ab4b01 | 869 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
c0c050c5 MC |
870 | u16 prod = rxr->rx_agg_prod; |
871 | u16 sw_prod = rxr->rx_sw_agg_prod; | |
bfcd8d79 | 872 | bool p5_tpa = false; |
c0c050c5 MC |
873 | u32 i; |
874 | ||
bfcd8d79 MC |
875 | if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) |
876 | p5_tpa = true; | |
877 | ||
c0c050c5 MC |
878 | for (i = 0; i < agg_bufs; i++) { |
879 | u16 cons; | |
880 | struct rx_agg_cmp *agg; | |
881 | struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; | |
882 | struct rx_bd *prod_bd; | |
883 | struct page *page; | |
884 | ||
bfcd8d79 MC |
885 | if (p5_tpa) |
886 | agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i); | |
887 | else | |
888 | agg = bnxt_get_agg(bp, cpr, idx, start + i); | |
c0c050c5 MC |
889 | cons = agg->rx_agg_cmp_opaque; |
890 | __clear_bit(cons, rxr->rx_agg_bmap); | |
891 | ||
892 | if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) | |
893 | sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); | |
894 | ||
895 | __set_bit(sw_prod, rxr->rx_agg_bmap); | |
896 | prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; | |
897 | cons_rx_buf = &rxr->rx_agg_ring[cons]; | |
898 | ||
899 | /* It is possible for sw_prod to be equal to cons, so | |
900 | * set cons_rx_buf->page to NULL first. | |
901 | */ | |
902 | page = cons_rx_buf->page; | |
903 | cons_rx_buf->page = NULL; | |
904 | prod_rx_buf->page = page; | |
89d0a06c | 905 | prod_rx_buf->offset = cons_rx_buf->offset; |
c0c050c5 MC |
906 | |
907 | prod_rx_buf->mapping = cons_rx_buf->mapping; | |
908 | ||
909 | prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
910 | ||
911 | prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); | |
912 | prod_bd->rx_bd_opaque = sw_prod; | |
913 | ||
914 | prod = NEXT_RX_AGG(prod); | |
915 | sw_prod = NEXT_RX_AGG(sw_prod); | |
c0c050c5 MC |
916 | } |
917 | rxr->rx_agg_prod = prod; | |
918 | rxr->rx_sw_agg_prod = sw_prod; | |
919 | } | |
920 | ||
c61fb99c MC |
921 | static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp, |
922 | struct bnxt_rx_ring_info *rxr, | |
923 | u16 cons, void *data, u8 *data_ptr, | |
924 | dma_addr_t dma_addr, | |
925 | unsigned int offset_and_len) | |
926 | { | |
927 | unsigned int payload = offset_and_len >> 16; | |
928 | unsigned int len = offset_and_len & 0xffff; | |
d7840976 | 929 | skb_frag_t *frag; |
c61fb99c MC |
930 | struct page *page = data; |
931 | u16 prod = rxr->rx_prod; | |
932 | struct sk_buff *skb; | |
933 | int off, err; | |
934 | ||
935 | err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); | |
936 | if (unlikely(err)) { | |
937 | bnxt_reuse_rx_data(rxr, cons, data); | |
938 | return NULL; | |
939 | } | |
940 | dma_addr -= bp->rx_dma_offset; | |
c519fe9a SN |
941 | dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir, |
942 | DMA_ATTR_WEAK_ORDERING); | |
3071c517 | 943 | page_pool_release_page(rxr->page_pool, page); |
c61fb99c MC |
944 | |
945 | if (unlikely(!payload)) | |
c43f1255 | 946 | payload = eth_get_headlen(bp->dev, data_ptr, len); |
c61fb99c MC |
947 | |
948 | skb = napi_alloc_skb(&rxr->bnapi->napi, payload); | |
949 | if (!skb) { | |
950 | __free_page(page); | |
951 | return NULL; | |
952 | } | |
953 | ||
954 | off = (void *)data_ptr - page_address(page); | |
955 | skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE); | |
956 | memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN, | |
957 | payload + NET_IP_ALIGN); | |
958 | ||
959 | frag = &skb_shinfo(skb)->frags[0]; | |
960 | skb_frag_size_sub(frag, payload); | |
b54c9d5b | 961 | skb_frag_off_add(frag, payload); |
c61fb99c MC |
962 | skb->data_len -= payload; |
963 | skb->tail += payload; | |
964 | ||
965 | return skb; | |
966 | } | |
967 | ||
c0c050c5 MC |
968 | static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, |
969 | struct bnxt_rx_ring_info *rxr, u16 cons, | |
6bb19474 MC |
970 | void *data, u8 *data_ptr, |
971 | dma_addr_t dma_addr, | |
972 | unsigned int offset_and_len) | |
c0c050c5 | 973 | { |
6bb19474 | 974 | u16 prod = rxr->rx_prod; |
c0c050c5 | 975 | struct sk_buff *skb; |
6bb19474 | 976 | int err; |
c0c050c5 MC |
977 | |
978 | err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); | |
979 | if (unlikely(err)) { | |
980 | bnxt_reuse_rx_data(rxr, cons, data); | |
981 | return NULL; | |
982 | } | |
983 | ||
984 | skb = build_skb(data, 0); | |
c519fe9a SN |
985 | dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, |
986 | bp->rx_dir, DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
987 | if (!skb) { |
988 | kfree(data); | |
989 | return NULL; | |
990 | } | |
991 | ||
b3dba77c | 992 | skb_reserve(skb, bp->rx_offset); |
6bb19474 | 993 | skb_put(skb, offset_and_len & 0xffff); |
c0c050c5 MC |
994 | return skb; |
995 | } | |
996 | ||
e44758b7 MC |
997 | static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, |
998 | struct bnxt_cp_ring_info *cpr, | |
4a228a3a MC |
999 | struct sk_buff *skb, u16 idx, |
1000 | u32 agg_bufs, bool tpa) | |
c0c050c5 | 1001 | { |
e44758b7 | 1002 | struct bnxt_napi *bnapi = cpr->bnapi; |
c0c050c5 | 1003 | struct pci_dev *pdev = bp->pdev; |
b6ab4b01 | 1004 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
c0c050c5 | 1005 | u16 prod = rxr->rx_agg_prod; |
bfcd8d79 | 1006 | bool p5_tpa = false; |
c0c050c5 MC |
1007 | u32 i; |
1008 | ||
bfcd8d79 MC |
1009 | if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) |
1010 | p5_tpa = true; | |
1011 | ||
c0c050c5 MC |
1012 | for (i = 0; i < agg_bufs; i++) { |
1013 | u16 cons, frag_len; | |
1014 | struct rx_agg_cmp *agg; | |
1015 | struct bnxt_sw_rx_agg_bd *cons_rx_buf; | |
1016 | struct page *page; | |
1017 | dma_addr_t mapping; | |
1018 | ||
bfcd8d79 MC |
1019 | if (p5_tpa) |
1020 | agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i); | |
1021 | else | |
1022 | agg = bnxt_get_agg(bp, cpr, idx, i); | |
c0c050c5 MC |
1023 | cons = agg->rx_agg_cmp_opaque; |
1024 | frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & | |
1025 | RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; | |
1026 | ||
1027 | cons_rx_buf = &rxr->rx_agg_ring[cons]; | |
89d0a06c MC |
1028 | skb_fill_page_desc(skb, i, cons_rx_buf->page, |
1029 | cons_rx_buf->offset, frag_len); | |
c0c050c5 MC |
1030 | __clear_bit(cons, rxr->rx_agg_bmap); |
1031 | ||
1032 | /* It is possible for bnxt_alloc_rx_page() to allocate | |
1033 | * a sw_prod index that equals the cons index, so we | |
1034 | * need to clear the cons entry now. | |
1035 | */ | |
11cd119d | 1036 | mapping = cons_rx_buf->mapping; |
c0c050c5 MC |
1037 | page = cons_rx_buf->page; |
1038 | cons_rx_buf->page = NULL; | |
1039 | ||
1040 | if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { | |
1041 | struct skb_shared_info *shinfo; | |
1042 | unsigned int nr_frags; | |
1043 | ||
1044 | shinfo = skb_shinfo(skb); | |
1045 | nr_frags = --shinfo->nr_frags; | |
1046 | __skb_frag_set_page(&shinfo->frags[nr_frags], NULL); | |
1047 | ||
1048 | dev_kfree_skb(skb); | |
1049 | ||
1050 | cons_rx_buf->page = page; | |
1051 | ||
1052 | /* Update prod since possibly some pages have been | |
1053 | * allocated already. | |
1054 | */ | |
1055 | rxr->rx_agg_prod = prod; | |
4a228a3a | 1056 | bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa); |
c0c050c5 MC |
1057 | return NULL; |
1058 | } | |
1059 | ||
c519fe9a SN |
1060 | dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE, |
1061 | PCI_DMA_FROMDEVICE, | |
1062 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
1063 | |
1064 | skb->data_len += frag_len; | |
1065 | skb->len += frag_len; | |
1066 | skb->truesize += PAGE_SIZE; | |
1067 | ||
1068 | prod = NEXT_RX_AGG(prod); | |
c0c050c5 MC |
1069 | } |
1070 | rxr->rx_agg_prod = prod; | |
1071 | return skb; | |
1072 | } | |
1073 | ||
1074 | static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, | |
1075 | u8 agg_bufs, u32 *raw_cons) | |
1076 | { | |
1077 | u16 last; | |
1078 | struct rx_agg_cmp *agg; | |
1079 | ||
1080 | *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); | |
1081 | last = RING_CMP(*raw_cons); | |
1082 | agg = (struct rx_agg_cmp *) | |
1083 | &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; | |
1084 | return RX_AGG_CMP_VALID(agg, *raw_cons); | |
1085 | } | |
1086 | ||
1087 | static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, | |
1088 | unsigned int len, | |
1089 | dma_addr_t mapping) | |
1090 | { | |
1091 | struct bnxt *bp = bnapi->bp; | |
1092 | struct pci_dev *pdev = bp->pdev; | |
1093 | struct sk_buff *skb; | |
1094 | ||
1095 | skb = napi_alloc_skb(&bnapi->napi, len); | |
1096 | if (!skb) | |
1097 | return NULL; | |
1098 | ||
745fc05c MC |
1099 | dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh, |
1100 | bp->rx_dir); | |
c0c050c5 | 1101 | |
6bb19474 MC |
1102 | memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN, |
1103 | len + NET_IP_ALIGN); | |
c0c050c5 | 1104 | |
745fc05c MC |
1105 | dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh, |
1106 | bp->rx_dir); | |
c0c050c5 MC |
1107 | |
1108 | skb_put(skb, len); | |
1109 | return skb; | |
1110 | } | |
1111 | ||
e44758b7 | 1112 | static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, |
fa7e2812 MC |
1113 | u32 *raw_cons, void *cmp) |
1114 | { | |
fa7e2812 MC |
1115 | struct rx_cmp *rxcmp = cmp; |
1116 | u32 tmp_raw_cons = *raw_cons; | |
1117 | u8 cmp_type, agg_bufs = 0; | |
1118 | ||
1119 | cmp_type = RX_CMP_TYPE(rxcmp); | |
1120 | ||
1121 | if (cmp_type == CMP_TYPE_RX_L2_CMP) { | |
1122 | agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & | |
1123 | RX_CMP_AGG_BUFS) >> | |
1124 | RX_CMP_AGG_BUFS_SHIFT; | |
1125 | } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { | |
1126 | struct rx_tpa_end_cmp *tpa_end = cmp; | |
1127 | ||
bfcd8d79 MC |
1128 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
1129 | return 0; | |
1130 | ||
4a228a3a | 1131 | agg_bufs = TPA_END_AGG_BUFS(tpa_end); |
fa7e2812 MC |
1132 | } |
1133 | ||
1134 | if (agg_bufs) { | |
1135 | if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) | |
1136 | return -EBUSY; | |
1137 | } | |
1138 | *raw_cons = tmp_raw_cons; | |
1139 | return 0; | |
1140 | } | |
1141 | ||
230d1f0d MC |
1142 | static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay) |
1143 | { | |
1144 | if (BNXT_PF(bp)) | |
1145 | queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay); | |
1146 | else | |
1147 | schedule_delayed_work(&bp->fw_reset_task, delay); | |
1148 | } | |
1149 | ||
c213eae8 MC |
1150 | static void bnxt_queue_sp_work(struct bnxt *bp) |
1151 | { | |
1152 | if (BNXT_PF(bp)) | |
1153 | queue_work(bnxt_pf_wq, &bp->sp_task); | |
1154 | else | |
1155 | schedule_work(&bp->sp_task); | |
1156 | } | |
1157 | ||
1158 | static void bnxt_cancel_sp_work(struct bnxt *bp) | |
1159 | { | |
1160 | if (BNXT_PF(bp)) | |
1161 | flush_workqueue(bnxt_pf_wq); | |
1162 | else | |
1163 | cancel_work_sync(&bp->sp_task); | |
1164 | } | |
1165 | ||
fa7e2812 MC |
1166 | static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) |
1167 | { | |
1168 | if (!rxr->bnapi->in_reset) { | |
1169 | rxr->bnapi->in_reset = true; | |
1170 | set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); | |
c213eae8 | 1171 | bnxt_queue_sp_work(bp); |
fa7e2812 MC |
1172 | } |
1173 | rxr->rx_next_cons = 0xffff; | |
1174 | } | |
1175 | ||
ec4d8e7c MC |
1176 | static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) |
1177 | { | |
1178 | struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; | |
1179 | u16 idx = agg_id & MAX_TPA_P5_MASK; | |
1180 | ||
1181 | if (test_bit(idx, map->agg_idx_bmap)) | |
1182 | idx = find_first_zero_bit(map->agg_idx_bmap, | |
1183 | BNXT_AGG_IDX_BMAP_SIZE); | |
1184 | __set_bit(idx, map->agg_idx_bmap); | |
1185 | map->agg_id_tbl[agg_id] = idx; | |
1186 | return idx; | |
1187 | } | |
1188 | ||
1189 | static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) | |
1190 | { | |
1191 | struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; | |
1192 | ||
1193 | __clear_bit(idx, map->agg_idx_bmap); | |
1194 | } | |
1195 | ||
1196 | static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) | |
1197 | { | |
1198 | struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; | |
1199 | ||
1200 | return map->agg_id_tbl[agg_id]; | |
1201 | } | |
1202 | ||
c0c050c5 MC |
1203 | static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, |
1204 | struct rx_tpa_start_cmp *tpa_start, | |
1205 | struct rx_tpa_start_cmp_ext *tpa_start1) | |
1206 | { | |
c0c050c5 | 1207 | struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; |
bfcd8d79 MC |
1208 | struct bnxt_tpa_info *tpa_info; |
1209 | u16 cons, prod, agg_id; | |
c0c050c5 MC |
1210 | struct rx_bd *prod_bd; |
1211 | dma_addr_t mapping; | |
1212 | ||
ec4d8e7c | 1213 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
bfcd8d79 | 1214 | agg_id = TPA_START_AGG_ID_P5(tpa_start); |
ec4d8e7c MC |
1215 | agg_id = bnxt_alloc_agg_idx(rxr, agg_id); |
1216 | } else { | |
bfcd8d79 | 1217 | agg_id = TPA_START_AGG_ID(tpa_start); |
ec4d8e7c | 1218 | } |
c0c050c5 MC |
1219 | cons = tpa_start->rx_tpa_start_cmp_opaque; |
1220 | prod = rxr->rx_prod; | |
1221 | cons_rx_buf = &rxr->rx_buf_ring[cons]; | |
1222 | prod_rx_buf = &rxr->rx_buf_ring[prod]; | |
1223 | tpa_info = &rxr->rx_tpa[agg_id]; | |
1224 | ||
bfcd8d79 MC |
1225 | if (unlikely(cons != rxr->rx_next_cons || |
1226 | TPA_START_ERROR(tpa_start))) { | |
1227 | netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n", | |
1228 | cons, rxr->rx_next_cons, | |
1229 | TPA_START_ERROR_CODE(tpa_start1)); | |
fa7e2812 MC |
1230 | bnxt_sched_reset(bp, rxr); |
1231 | return; | |
1232 | } | |
ee5c7fb3 SP |
1233 | /* Store cfa_code in tpa_info to use in tpa_end |
1234 | * completion processing. | |
1235 | */ | |
1236 | tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1); | |
c0c050c5 | 1237 | prod_rx_buf->data = tpa_info->data; |
6bb19474 | 1238 | prod_rx_buf->data_ptr = tpa_info->data_ptr; |
c0c050c5 MC |
1239 | |
1240 | mapping = tpa_info->mapping; | |
11cd119d | 1241 | prod_rx_buf->mapping = mapping; |
c0c050c5 MC |
1242 | |
1243 | prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
1244 | ||
1245 | prod_bd->rx_bd_haddr = cpu_to_le64(mapping); | |
1246 | ||
1247 | tpa_info->data = cons_rx_buf->data; | |
6bb19474 | 1248 | tpa_info->data_ptr = cons_rx_buf->data_ptr; |
c0c050c5 | 1249 | cons_rx_buf->data = NULL; |
11cd119d | 1250 | tpa_info->mapping = cons_rx_buf->mapping; |
c0c050c5 MC |
1251 | |
1252 | tpa_info->len = | |
1253 | le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> | |
1254 | RX_TPA_START_CMP_LEN_SHIFT; | |
1255 | if (likely(TPA_START_HASH_VALID(tpa_start))) { | |
1256 | u32 hash_type = TPA_START_HASH_TYPE(tpa_start); | |
1257 | ||
1258 | tpa_info->hash_type = PKT_HASH_TYPE_L4; | |
1259 | tpa_info->gso_type = SKB_GSO_TCPV4; | |
1260 | /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ | |
50f011b6 | 1261 | if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1)) |
c0c050c5 MC |
1262 | tpa_info->gso_type = SKB_GSO_TCPV6; |
1263 | tpa_info->rss_hash = | |
1264 | le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); | |
1265 | } else { | |
1266 | tpa_info->hash_type = PKT_HASH_TYPE_NONE; | |
1267 | tpa_info->gso_type = 0; | |
1268 | if (netif_msg_rx_err(bp)) | |
1269 | netdev_warn(bp->dev, "TPA packet without valid hash\n"); | |
1270 | } | |
1271 | tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); | |
1272 | tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); | |
94758f8d | 1273 | tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info); |
bfcd8d79 | 1274 | tpa_info->agg_count = 0; |
c0c050c5 MC |
1275 | |
1276 | rxr->rx_prod = NEXT_RX(prod); | |
1277 | cons = NEXT_RX(cons); | |
376a5b86 | 1278 | rxr->rx_next_cons = NEXT_RX(cons); |
c0c050c5 MC |
1279 | cons_rx_buf = &rxr->rx_buf_ring[cons]; |
1280 | ||
1281 | bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); | |
1282 | rxr->rx_prod = NEXT_RX(rxr->rx_prod); | |
1283 | cons_rx_buf->data = NULL; | |
1284 | } | |
1285 | ||
4a228a3a | 1286 | static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs) |
c0c050c5 MC |
1287 | { |
1288 | if (agg_bufs) | |
4a228a3a | 1289 | bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true); |
c0c050c5 MC |
1290 | } |
1291 | ||
bee5a188 MC |
1292 | #ifdef CONFIG_INET |
1293 | static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto) | |
1294 | { | |
1295 | struct udphdr *uh = NULL; | |
1296 | ||
1297 | if (ip_proto == htons(ETH_P_IP)) { | |
1298 | struct iphdr *iph = (struct iphdr *)skb->data; | |
1299 | ||
1300 | if (iph->protocol == IPPROTO_UDP) | |
1301 | uh = (struct udphdr *)(iph + 1); | |
1302 | } else { | |
1303 | struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; | |
1304 | ||
1305 | if (iph->nexthdr == IPPROTO_UDP) | |
1306 | uh = (struct udphdr *)(iph + 1); | |
1307 | } | |
1308 | if (uh) { | |
1309 | if (uh->check) | |
1310 | skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM; | |
1311 | else | |
1312 | skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; | |
1313 | } | |
1314 | } | |
1315 | #endif | |
1316 | ||
94758f8d MC |
1317 | static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info, |
1318 | int payload_off, int tcp_ts, | |
1319 | struct sk_buff *skb) | |
1320 | { | |
1321 | #ifdef CONFIG_INET | |
1322 | struct tcphdr *th; | |
1323 | int len, nw_off; | |
1324 | u16 outer_ip_off, inner_ip_off, inner_mac_off; | |
1325 | u32 hdr_info = tpa_info->hdr_info; | |
1326 | bool loopback = false; | |
1327 | ||
1328 | inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); | |
1329 | inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); | |
1330 | outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); | |
1331 | ||
1332 | /* If the packet is an internal loopback packet, the offsets will | |
1333 | * have an extra 4 bytes. | |
1334 | */ | |
1335 | if (inner_mac_off == 4) { | |
1336 | loopback = true; | |
1337 | } else if (inner_mac_off > 4) { | |
1338 | __be16 proto = *((__be16 *)(skb->data + inner_ip_off - | |
1339 | ETH_HLEN - 2)); | |
1340 | ||
1341 | /* We only support inner iPv4/ipv6. If we don't see the | |
1342 | * correct protocol ID, it must be a loopback packet where | |
1343 | * the offsets are off by 4. | |
1344 | */ | |
09a7636a | 1345 | if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6)) |
94758f8d MC |
1346 | loopback = true; |
1347 | } | |
1348 | if (loopback) { | |
1349 | /* internal loopback packet, subtract all offsets by 4 */ | |
1350 | inner_ip_off -= 4; | |
1351 | inner_mac_off -= 4; | |
1352 | outer_ip_off -= 4; | |
1353 | } | |
1354 | ||
1355 | nw_off = inner_ip_off - ETH_HLEN; | |
1356 | skb_set_network_header(skb, nw_off); | |
1357 | if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) { | |
1358 | struct ipv6hdr *iph = ipv6_hdr(skb); | |
1359 | ||
1360 | skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); | |
1361 | len = skb->len - skb_transport_offset(skb); | |
1362 | th = tcp_hdr(skb); | |
1363 | th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); | |
1364 | } else { | |
1365 | struct iphdr *iph = ip_hdr(skb); | |
1366 | ||
1367 | skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); | |
1368 | len = skb->len - skb_transport_offset(skb); | |
1369 | th = tcp_hdr(skb); | |
1370 | th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); | |
1371 | } | |
1372 | ||
1373 | if (inner_mac_off) { /* tunnel */ | |
94758f8d MC |
1374 | __be16 proto = *((__be16 *)(skb->data + outer_ip_off - |
1375 | ETH_HLEN - 2)); | |
1376 | ||
bee5a188 | 1377 | bnxt_gro_tunnel(skb, proto); |
94758f8d MC |
1378 | } |
1379 | #endif | |
1380 | return skb; | |
1381 | } | |
1382 | ||
67912c36 MC |
1383 | static struct sk_buff *bnxt_gro_func_5750x(struct bnxt_tpa_info *tpa_info, |
1384 | int payload_off, int tcp_ts, | |
1385 | struct sk_buff *skb) | |
1386 | { | |
1387 | #ifdef CONFIG_INET | |
1388 | u16 outer_ip_off, inner_ip_off, inner_mac_off; | |
1389 | u32 hdr_info = tpa_info->hdr_info; | |
1390 | int iphdr_len, nw_off; | |
1391 | ||
1392 | inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); | |
1393 | inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); | |
1394 | outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); | |
1395 | ||
1396 | nw_off = inner_ip_off - ETH_HLEN; | |
1397 | skb_set_network_header(skb, nw_off); | |
1398 | iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ? | |
1399 | sizeof(struct ipv6hdr) : sizeof(struct iphdr); | |
1400 | skb_set_transport_header(skb, nw_off + iphdr_len); | |
1401 | ||
1402 | if (inner_mac_off) { /* tunnel */ | |
1403 | __be16 proto = *((__be16 *)(skb->data + outer_ip_off - | |
1404 | ETH_HLEN - 2)); | |
1405 | ||
1406 | bnxt_gro_tunnel(skb, proto); | |
1407 | } | |
1408 | #endif | |
1409 | return skb; | |
1410 | } | |
1411 | ||
c0c050c5 MC |
1412 | #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) |
1413 | #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) | |
1414 | ||
309369c9 MC |
1415 | static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info, |
1416 | int payload_off, int tcp_ts, | |
c0c050c5 MC |
1417 | struct sk_buff *skb) |
1418 | { | |
d1611c3a | 1419 | #ifdef CONFIG_INET |
c0c050c5 | 1420 | struct tcphdr *th; |
719ca811 | 1421 | int len, nw_off, tcp_opt_len = 0; |
27e24189 | 1422 | |
309369c9 | 1423 | if (tcp_ts) |
c0c050c5 MC |
1424 | tcp_opt_len = 12; |
1425 | ||
c0c050c5 MC |
1426 | if (tpa_info->gso_type == SKB_GSO_TCPV4) { |
1427 | struct iphdr *iph; | |
1428 | ||
1429 | nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - | |
1430 | ETH_HLEN; | |
1431 | skb_set_network_header(skb, nw_off); | |
1432 | iph = ip_hdr(skb); | |
1433 | skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); | |
1434 | len = skb->len - skb_transport_offset(skb); | |
1435 | th = tcp_hdr(skb); | |
1436 | th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); | |
1437 | } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { | |
1438 | struct ipv6hdr *iph; | |
1439 | ||
1440 | nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - | |
1441 | ETH_HLEN; | |
1442 | skb_set_network_header(skb, nw_off); | |
1443 | iph = ipv6_hdr(skb); | |
1444 | skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); | |
1445 | len = skb->len - skb_transport_offset(skb); | |
1446 | th = tcp_hdr(skb); | |
1447 | th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); | |
1448 | } else { | |
1449 | dev_kfree_skb_any(skb); | |
1450 | return NULL; | |
1451 | } | |
c0c050c5 | 1452 | |
bee5a188 MC |
1453 | if (nw_off) /* tunnel */ |
1454 | bnxt_gro_tunnel(skb, skb->protocol); | |
c0c050c5 MC |
1455 | #endif |
1456 | return skb; | |
1457 | } | |
1458 | ||
309369c9 MC |
1459 | static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp, |
1460 | struct bnxt_tpa_info *tpa_info, | |
1461 | struct rx_tpa_end_cmp *tpa_end, | |
1462 | struct rx_tpa_end_cmp_ext *tpa_end1, | |
1463 | struct sk_buff *skb) | |
1464 | { | |
1465 | #ifdef CONFIG_INET | |
1466 | int payload_off; | |
1467 | u16 segs; | |
1468 | ||
1469 | segs = TPA_END_TPA_SEGS(tpa_end); | |
1470 | if (segs == 1) | |
1471 | return skb; | |
1472 | ||
1473 | NAPI_GRO_CB(skb)->count = segs; | |
1474 | skb_shinfo(skb)->gso_size = | |
1475 | le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); | |
1476 | skb_shinfo(skb)->gso_type = tpa_info->gso_type; | |
bfcd8d79 MC |
1477 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
1478 | payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1); | |
1479 | else | |
1480 | payload_off = TPA_END_PAYLOAD_OFF(tpa_end); | |
309369c9 | 1481 | skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb); |
5910906c MC |
1482 | if (likely(skb)) |
1483 | tcp_gro_complete(skb); | |
309369c9 MC |
1484 | #endif |
1485 | return skb; | |
1486 | } | |
1487 | ||
ee5c7fb3 SP |
1488 | /* Given the cfa_code of a received packet determine which |
1489 | * netdev (vf-rep or PF) the packet is destined to. | |
1490 | */ | |
1491 | static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code) | |
1492 | { | |
1493 | struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code); | |
1494 | ||
1495 | /* if vf-rep dev is NULL, the must belongs to the PF */ | |
1496 | return dev ? dev : bp->dev; | |
1497 | } | |
1498 | ||
c0c050c5 | 1499 | static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, |
e44758b7 | 1500 | struct bnxt_cp_ring_info *cpr, |
c0c050c5 MC |
1501 | u32 *raw_cons, |
1502 | struct rx_tpa_end_cmp *tpa_end, | |
1503 | struct rx_tpa_end_cmp_ext *tpa_end1, | |
4e5dbbda | 1504 | u8 *event) |
c0c050c5 | 1505 | { |
e44758b7 | 1506 | struct bnxt_napi *bnapi = cpr->bnapi; |
b6ab4b01 | 1507 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
6bb19474 | 1508 | u8 *data_ptr, agg_bufs; |
c0c050c5 MC |
1509 | unsigned int len; |
1510 | struct bnxt_tpa_info *tpa_info; | |
1511 | dma_addr_t mapping; | |
1512 | struct sk_buff *skb; | |
bfcd8d79 | 1513 | u16 idx = 0, agg_id; |
6bb19474 | 1514 | void *data; |
bfcd8d79 | 1515 | bool gro; |
c0c050c5 | 1516 | |
fa7e2812 | 1517 | if (unlikely(bnapi->in_reset)) { |
e44758b7 | 1518 | int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end); |
fa7e2812 MC |
1519 | |
1520 | if (rc < 0) | |
1521 | return ERR_PTR(-EBUSY); | |
1522 | return NULL; | |
1523 | } | |
1524 | ||
bfcd8d79 MC |
1525 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
1526 | agg_id = TPA_END_AGG_ID_P5(tpa_end); | |
ec4d8e7c | 1527 | agg_id = bnxt_lookup_agg_idx(rxr, agg_id); |
bfcd8d79 MC |
1528 | agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1); |
1529 | tpa_info = &rxr->rx_tpa[agg_id]; | |
1530 | if (unlikely(agg_bufs != tpa_info->agg_count)) { | |
1531 | netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n", | |
1532 | agg_bufs, tpa_info->agg_count); | |
1533 | agg_bufs = tpa_info->agg_count; | |
1534 | } | |
1535 | tpa_info->agg_count = 0; | |
1536 | *event |= BNXT_AGG_EVENT; | |
ec4d8e7c | 1537 | bnxt_free_agg_idx(rxr, agg_id); |
bfcd8d79 MC |
1538 | idx = agg_id; |
1539 | gro = !!(bp->flags & BNXT_FLAG_GRO); | |
1540 | } else { | |
1541 | agg_id = TPA_END_AGG_ID(tpa_end); | |
1542 | agg_bufs = TPA_END_AGG_BUFS(tpa_end); | |
1543 | tpa_info = &rxr->rx_tpa[agg_id]; | |
1544 | idx = RING_CMP(*raw_cons); | |
1545 | if (agg_bufs) { | |
1546 | if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) | |
1547 | return ERR_PTR(-EBUSY); | |
1548 | ||
1549 | *event |= BNXT_AGG_EVENT; | |
1550 | idx = NEXT_CMP(idx); | |
1551 | } | |
1552 | gro = !!TPA_END_GRO(tpa_end); | |
1553 | } | |
c0c050c5 | 1554 | data = tpa_info->data; |
6bb19474 MC |
1555 | data_ptr = tpa_info->data_ptr; |
1556 | prefetch(data_ptr); | |
c0c050c5 MC |
1557 | len = tpa_info->len; |
1558 | mapping = tpa_info->mapping; | |
1559 | ||
69c149e2 | 1560 | if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) { |
4a228a3a | 1561 | bnxt_abort_tpa(cpr, idx, agg_bufs); |
69c149e2 MC |
1562 | if (agg_bufs > MAX_SKB_FRAGS) |
1563 | netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", | |
1564 | agg_bufs, (int)MAX_SKB_FRAGS); | |
c0c050c5 MC |
1565 | return NULL; |
1566 | } | |
1567 | ||
1568 | if (len <= bp->rx_copy_thresh) { | |
6bb19474 | 1569 | skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping); |
c0c050c5 | 1570 | if (!skb) { |
4a228a3a | 1571 | bnxt_abort_tpa(cpr, idx, agg_bufs); |
c0c050c5 MC |
1572 | return NULL; |
1573 | } | |
1574 | } else { | |
1575 | u8 *new_data; | |
1576 | dma_addr_t new_mapping; | |
1577 | ||
1578 | new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC); | |
1579 | if (!new_data) { | |
4a228a3a | 1580 | bnxt_abort_tpa(cpr, idx, agg_bufs); |
c0c050c5 MC |
1581 | return NULL; |
1582 | } | |
1583 | ||
1584 | tpa_info->data = new_data; | |
b3dba77c | 1585 | tpa_info->data_ptr = new_data + bp->rx_offset; |
c0c050c5 MC |
1586 | tpa_info->mapping = new_mapping; |
1587 | ||
1588 | skb = build_skb(data, 0); | |
c519fe9a SN |
1589 | dma_unmap_single_attrs(&bp->pdev->dev, mapping, |
1590 | bp->rx_buf_use_size, bp->rx_dir, | |
1591 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
1592 | |
1593 | if (!skb) { | |
1594 | kfree(data); | |
4a228a3a | 1595 | bnxt_abort_tpa(cpr, idx, agg_bufs); |
c0c050c5 MC |
1596 | return NULL; |
1597 | } | |
b3dba77c | 1598 | skb_reserve(skb, bp->rx_offset); |
c0c050c5 MC |
1599 | skb_put(skb, len); |
1600 | } | |
1601 | ||
1602 | if (agg_bufs) { | |
4a228a3a | 1603 | skb = bnxt_rx_pages(bp, cpr, skb, idx, agg_bufs, true); |
c0c050c5 MC |
1604 | if (!skb) { |
1605 | /* Page reuse already handled by bnxt_rx_pages(). */ | |
1606 | return NULL; | |
1607 | } | |
1608 | } | |
ee5c7fb3 SP |
1609 | |
1610 | skb->protocol = | |
1611 | eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code)); | |
c0c050c5 MC |
1612 | |
1613 | if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) | |
1614 | skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); | |
1615 | ||
8852ddb4 MC |
1616 | if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) && |
1617 | (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { | |
c0c050c5 MC |
1618 | u16 vlan_proto = tpa_info->metadata >> |
1619 | RX_CMP_FLAGS2_METADATA_TPID_SFT; | |
ed7bc602 | 1620 | u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK; |
c0c050c5 | 1621 | |
8852ddb4 | 1622 | __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); |
c0c050c5 MC |
1623 | } |
1624 | ||
1625 | skb_checksum_none_assert(skb); | |
1626 | if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { | |
1627 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1628 | skb->csum_level = | |
1629 | (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; | |
1630 | } | |
1631 | ||
bfcd8d79 | 1632 | if (gro) |
309369c9 | 1633 | skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb); |
c0c050c5 MC |
1634 | |
1635 | return skb; | |
1636 | } | |
1637 | ||
8fe88ce7 MC |
1638 | static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, |
1639 | struct rx_agg_cmp *rx_agg) | |
1640 | { | |
1641 | u16 agg_id = TPA_AGG_AGG_ID(rx_agg); | |
1642 | struct bnxt_tpa_info *tpa_info; | |
1643 | ||
ec4d8e7c | 1644 | agg_id = bnxt_lookup_agg_idx(rxr, agg_id); |
8fe88ce7 MC |
1645 | tpa_info = &rxr->rx_tpa[agg_id]; |
1646 | BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS); | |
1647 | tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg; | |
1648 | } | |
1649 | ||
ee5c7fb3 SP |
1650 | static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi, |
1651 | struct sk_buff *skb) | |
1652 | { | |
1653 | if (skb->dev != bp->dev) { | |
1654 | /* this packet belongs to a vf-rep */ | |
1655 | bnxt_vf_rep_rx(bp, skb); | |
1656 | return; | |
1657 | } | |
1658 | skb_record_rx_queue(skb, bnapi->index); | |
1659 | napi_gro_receive(&bnapi->napi, skb); | |
1660 | } | |
1661 | ||
c0c050c5 MC |
1662 | /* returns the following: |
1663 | * 1 - 1 packet successfully received | |
1664 | * 0 - successful TPA_START, packet not completed yet | |
1665 | * -EBUSY - completion ring does not have all the agg buffers yet | |
1666 | * -ENOMEM - packet aborted due to out of memory | |
1667 | * -EIO - packet aborted due to hw error indicated in BD | |
1668 | */ | |
e44758b7 MC |
1669 | static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, |
1670 | u32 *raw_cons, u8 *event) | |
c0c050c5 | 1671 | { |
e44758b7 | 1672 | struct bnxt_napi *bnapi = cpr->bnapi; |
b6ab4b01 | 1673 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
c0c050c5 MC |
1674 | struct net_device *dev = bp->dev; |
1675 | struct rx_cmp *rxcmp; | |
1676 | struct rx_cmp_ext *rxcmp1; | |
1677 | u32 tmp_raw_cons = *raw_cons; | |
ee5c7fb3 | 1678 | u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons); |
c0c050c5 MC |
1679 | struct bnxt_sw_rx_bd *rx_buf; |
1680 | unsigned int len; | |
6bb19474 | 1681 | u8 *data_ptr, agg_bufs, cmp_type; |
c0c050c5 MC |
1682 | dma_addr_t dma_addr; |
1683 | struct sk_buff *skb; | |
6bb19474 | 1684 | void *data; |
c0c050c5 | 1685 | int rc = 0; |
c61fb99c | 1686 | u32 misc; |
c0c050c5 MC |
1687 | |
1688 | rxcmp = (struct rx_cmp *) | |
1689 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
1690 | ||
8fe88ce7 MC |
1691 | cmp_type = RX_CMP_TYPE(rxcmp); |
1692 | ||
1693 | if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) { | |
1694 | bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp); | |
1695 | goto next_rx_no_prod_no_len; | |
1696 | } | |
1697 | ||
c0c050c5 MC |
1698 | tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); |
1699 | cp_cons = RING_CMP(tmp_raw_cons); | |
1700 | rxcmp1 = (struct rx_cmp_ext *) | |
1701 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
1702 | ||
1703 | if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) | |
1704 | return -EBUSY; | |
1705 | ||
c0c050c5 MC |
1706 | prod = rxr->rx_prod; |
1707 | ||
1708 | if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { | |
1709 | bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, | |
1710 | (struct rx_tpa_start_cmp_ext *)rxcmp1); | |
1711 | ||
4e5dbbda | 1712 | *event |= BNXT_RX_EVENT; |
e7e70fa6 | 1713 | goto next_rx_no_prod_no_len; |
c0c050c5 MC |
1714 | |
1715 | } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { | |
e44758b7 | 1716 | skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons, |
c0c050c5 | 1717 | (struct rx_tpa_end_cmp *)rxcmp, |
4e5dbbda | 1718 | (struct rx_tpa_end_cmp_ext *)rxcmp1, event); |
c0c050c5 | 1719 | |
1fac4b2f | 1720 | if (IS_ERR(skb)) |
c0c050c5 MC |
1721 | return -EBUSY; |
1722 | ||
1723 | rc = -ENOMEM; | |
1724 | if (likely(skb)) { | |
ee5c7fb3 | 1725 | bnxt_deliver_skb(bp, bnapi, skb); |
c0c050c5 MC |
1726 | rc = 1; |
1727 | } | |
4e5dbbda | 1728 | *event |= BNXT_RX_EVENT; |
e7e70fa6 | 1729 | goto next_rx_no_prod_no_len; |
c0c050c5 MC |
1730 | } |
1731 | ||
1732 | cons = rxcmp->rx_cmp_opaque; | |
fa7e2812 | 1733 | if (unlikely(cons != rxr->rx_next_cons)) { |
e44758b7 | 1734 | int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp); |
fa7e2812 | 1735 | |
a1b0e4e6 MC |
1736 | netdev_warn(bp->dev, "RX cons %x != expected cons %x\n", |
1737 | cons, rxr->rx_next_cons); | |
fa7e2812 MC |
1738 | bnxt_sched_reset(bp, rxr); |
1739 | return rc1; | |
1740 | } | |
a1b0e4e6 MC |
1741 | rx_buf = &rxr->rx_buf_ring[cons]; |
1742 | data = rx_buf->data; | |
1743 | data_ptr = rx_buf->data_ptr; | |
6bb19474 | 1744 | prefetch(data_ptr); |
c0c050c5 | 1745 | |
c61fb99c MC |
1746 | misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1); |
1747 | agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT; | |
c0c050c5 MC |
1748 | |
1749 | if (agg_bufs) { | |
1750 | if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) | |
1751 | return -EBUSY; | |
1752 | ||
1753 | cp_cons = NEXT_CMP(cp_cons); | |
4e5dbbda | 1754 | *event |= BNXT_AGG_EVENT; |
c0c050c5 | 1755 | } |
4e5dbbda | 1756 | *event |= BNXT_RX_EVENT; |
c0c050c5 MC |
1757 | |
1758 | rx_buf->data = NULL; | |
1759 | if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { | |
8e44e96c MC |
1760 | u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2); |
1761 | ||
c0c050c5 MC |
1762 | bnxt_reuse_rx_data(rxr, cons, data); |
1763 | if (agg_bufs) | |
4a228a3a MC |
1764 | bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs, |
1765 | false); | |
c0c050c5 MC |
1766 | |
1767 | rc = -EIO; | |
8e44e96c | 1768 | if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) { |
19b3751f MC |
1769 | bnapi->cp_ring.rx_buf_errors++; |
1770 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) { | |
1771 | netdev_warn(bp->dev, "RX buffer error %x\n", | |
1772 | rx_err); | |
1773 | bnxt_sched_reset(bp, rxr); | |
1774 | } | |
8e44e96c | 1775 | } |
0b397b17 | 1776 | goto next_rx_no_len; |
c0c050c5 MC |
1777 | } |
1778 | ||
1779 | len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; | |
11cd119d | 1780 | dma_addr = rx_buf->mapping; |
c0c050c5 | 1781 | |
c6d30e83 MC |
1782 | if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) { |
1783 | rc = 1; | |
1784 | goto next_rx; | |
1785 | } | |
1786 | ||
c0c050c5 | 1787 | if (len <= bp->rx_copy_thresh) { |
6bb19474 | 1788 | skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr); |
c0c050c5 MC |
1789 | bnxt_reuse_rx_data(rxr, cons, data); |
1790 | if (!skb) { | |
296d5b54 | 1791 | if (agg_bufs) |
4a228a3a MC |
1792 | bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, |
1793 | agg_bufs, false); | |
c0c050c5 MC |
1794 | rc = -ENOMEM; |
1795 | goto next_rx; | |
1796 | } | |
1797 | } else { | |
c61fb99c MC |
1798 | u32 payload; |
1799 | ||
c6d30e83 MC |
1800 | if (rx_buf->data_ptr == data_ptr) |
1801 | payload = misc & RX_CMP_PAYLOAD_OFFSET; | |
1802 | else | |
1803 | payload = 0; | |
6bb19474 | 1804 | skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr, |
c61fb99c | 1805 | payload | len); |
c0c050c5 MC |
1806 | if (!skb) { |
1807 | rc = -ENOMEM; | |
1808 | goto next_rx; | |
1809 | } | |
1810 | } | |
1811 | ||
1812 | if (agg_bufs) { | |
4a228a3a | 1813 | skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs, false); |
c0c050c5 MC |
1814 | if (!skb) { |
1815 | rc = -ENOMEM; | |
1816 | goto next_rx; | |
1817 | } | |
1818 | } | |
1819 | ||
1820 | if (RX_CMP_HASH_VALID(rxcmp)) { | |
1821 | u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); | |
1822 | enum pkt_hash_types type = PKT_HASH_TYPE_L4; | |
1823 | ||
1824 | /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ | |
1825 | if (hash_type != 1 && hash_type != 3) | |
1826 | type = PKT_HASH_TYPE_L3; | |
1827 | skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); | |
1828 | } | |
1829 | ||
ee5c7fb3 SP |
1830 | cfa_code = RX_CMP_CFA_CODE(rxcmp1); |
1831 | skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code)); | |
c0c050c5 | 1832 | |
8852ddb4 MC |
1833 | if ((rxcmp1->rx_cmp_flags2 & |
1834 | cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) && | |
1835 | (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { | |
c0c050c5 | 1836 | u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); |
ed7bc602 | 1837 | u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK; |
c0c050c5 MC |
1838 | u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT; |
1839 | ||
8852ddb4 | 1840 | __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); |
c0c050c5 MC |
1841 | } |
1842 | ||
1843 | skb_checksum_none_assert(skb); | |
1844 | if (RX_CMP_L4_CS_OK(rxcmp1)) { | |
1845 | if (dev->features & NETIF_F_RXCSUM) { | |
1846 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1847 | skb->csum_level = RX_CMP_ENCAP(rxcmp1); | |
1848 | } | |
1849 | } else { | |
665e350d SB |
1850 | if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { |
1851 | if (dev->features & NETIF_F_RXCSUM) | |
d1981929 | 1852 | bnapi->cp_ring.rx_l4_csum_errors++; |
665e350d | 1853 | } |
c0c050c5 MC |
1854 | } |
1855 | ||
ee5c7fb3 | 1856 | bnxt_deliver_skb(bp, bnapi, skb); |
c0c050c5 MC |
1857 | rc = 1; |
1858 | ||
1859 | next_rx: | |
6a8788f2 AG |
1860 | cpr->rx_packets += 1; |
1861 | cpr->rx_bytes += len; | |
e7e70fa6 | 1862 | |
0b397b17 MC |
1863 | next_rx_no_len: |
1864 | rxr->rx_prod = NEXT_RX(prod); | |
1865 | rxr->rx_next_cons = NEXT_RX(cons); | |
1866 | ||
e7e70fa6 | 1867 | next_rx_no_prod_no_len: |
c0c050c5 MC |
1868 | *raw_cons = tmp_raw_cons; |
1869 | ||
1870 | return rc; | |
1871 | } | |
1872 | ||
2270bc5d MC |
1873 | /* In netpoll mode, if we are using a combined completion ring, we need to |
1874 | * discard the rx packets and recycle the buffers. | |
1875 | */ | |
e44758b7 MC |
1876 | static int bnxt_force_rx_discard(struct bnxt *bp, |
1877 | struct bnxt_cp_ring_info *cpr, | |
2270bc5d MC |
1878 | u32 *raw_cons, u8 *event) |
1879 | { | |
2270bc5d MC |
1880 | u32 tmp_raw_cons = *raw_cons; |
1881 | struct rx_cmp_ext *rxcmp1; | |
1882 | struct rx_cmp *rxcmp; | |
1883 | u16 cp_cons; | |
1884 | u8 cmp_type; | |
1885 | ||
1886 | cp_cons = RING_CMP(tmp_raw_cons); | |
1887 | rxcmp = (struct rx_cmp *) | |
1888 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
1889 | ||
1890 | tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); | |
1891 | cp_cons = RING_CMP(tmp_raw_cons); | |
1892 | rxcmp1 = (struct rx_cmp_ext *) | |
1893 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
1894 | ||
1895 | if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) | |
1896 | return -EBUSY; | |
1897 | ||
1898 | cmp_type = RX_CMP_TYPE(rxcmp); | |
1899 | if (cmp_type == CMP_TYPE_RX_L2_CMP) { | |
1900 | rxcmp1->rx_cmp_cfa_code_errors_v2 |= | |
1901 | cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); | |
1902 | } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { | |
1903 | struct rx_tpa_end_cmp_ext *tpa_end1; | |
1904 | ||
1905 | tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1; | |
1906 | tpa_end1->rx_tpa_end_cmp_errors_v2 |= | |
1907 | cpu_to_le32(RX_TPA_END_CMP_ERRORS); | |
1908 | } | |
e44758b7 | 1909 | return bnxt_rx_pkt(bp, cpr, raw_cons, event); |
2270bc5d MC |
1910 | } |
1911 | ||
7e914027 MC |
1912 | u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx) |
1913 | { | |
1914 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
1915 | u32 reg = fw_health->regs[reg_idx]; | |
1916 | u32 reg_type, reg_off, val = 0; | |
1917 | ||
1918 | reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); | |
1919 | reg_off = BNXT_FW_HEALTH_REG_OFF(reg); | |
1920 | switch (reg_type) { | |
1921 | case BNXT_FW_HEALTH_REG_TYPE_CFG: | |
1922 | pci_read_config_dword(bp->pdev, reg_off, &val); | |
1923 | break; | |
1924 | case BNXT_FW_HEALTH_REG_TYPE_GRC: | |
1925 | reg_off = fw_health->mapped_regs[reg_idx]; | |
1926 | /* fall through */ | |
1927 | case BNXT_FW_HEALTH_REG_TYPE_BAR0: | |
1928 | val = readl(bp->bar0 + reg_off); | |
1929 | break; | |
1930 | case BNXT_FW_HEALTH_REG_TYPE_BAR1: | |
1931 | val = readl(bp->bar1 + reg_off); | |
1932 | break; | |
1933 | } | |
1934 | if (reg_idx == BNXT_FW_RESET_INPROG_REG) | |
1935 | val &= fw_health->fw_reset_inprog_reg_mask; | |
1936 | return val; | |
1937 | } | |
1938 | ||
4bb13abf | 1939 | #define BNXT_GET_EVENT_PORT(data) \ |
87c374de MC |
1940 | ((data) & \ |
1941 | ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK) | |
4bb13abf | 1942 | |
c0c050c5 MC |
1943 | static int bnxt_async_event_process(struct bnxt *bp, |
1944 | struct hwrm_async_event_cmpl *cmpl) | |
1945 | { | |
1946 | u16 event_id = le16_to_cpu(cmpl->event_id); | |
1947 | ||
1948 | /* TODO CHIMP_FW: Define event id's for link change, error etc */ | |
1949 | switch (event_id) { | |
87c374de | 1950 | case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: { |
8cbde117 MC |
1951 | u32 data1 = le32_to_cpu(cmpl->event_data1); |
1952 | struct bnxt_link_info *link_info = &bp->link_info; | |
1953 | ||
1954 | if (BNXT_VF(bp)) | |
1955 | goto async_event_process_exit; | |
a8168b6c MC |
1956 | |
1957 | /* print unsupported speed warning in forced speed mode only */ | |
1958 | if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) && | |
1959 | (data1 & 0x20000)) { | |
8cbde117 MC |
1960 | u16 fw_speed = link_info->force_link_speed; |
1961 | u32 speed = bnxt_fw_to_ethtool_speed(fw_speed); | |
1962 | ||
a8168b6c MC |
1963 | if (speed != SPEED_UNKNOWN) |
1964 | netdev_warn(bp->dev, "Link speed %d no longer supported\n", | |
1965 | speed); | |
8cbde117 | 1966 | } |
286ef9d6 | 1967 | set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event); |
8cbde117 | 1968 | } |
bc171e87 | 1969 | /* fall through */ |
b1613e78 MC |
1970 | case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE: |
1971 | case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE: | |
1972 | set_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, &bp->sp_event); | |
1973 | /* fall through */ | |
87c374de | 1974 | case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: |
c0c050c5 | 1975 | set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); |
19241368 | 1976 | break; |
87c374de | 1977 | case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: |
19241368 | 1978 | set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event); |
c0c050c5 | 1979 | break; |
87c374de | 1980 | case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: { |
4bb13abf MC |
1981 | u32 data1 = le32_to_cpu(cmpl->event_data1); |
1982 | u16 port_id = BNXT_GET_EVENT_PORT(data1); | |
1983 | ||
1984 | if (BNXT_VF(bp)) | |
1985 | break; | |
1986 | ||
1987 | if (bp->pf.port_id != port_id) | |
1988 | break; | |
1989 | ||
4bb13abf MC |
1990 | set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event); |
1991 | break; | |
1992 | } | |
87c374de | 1993 | case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: |
fc0f1929 MC |
1994 | if (BNXT_PF(bp)) |
1995 | goto async_event_process_exit; | |
1996 | set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event); | |
1997 | break; | |
acfb50e4 VV |
1998 | case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: { |
1999 | u32 data1 = le32_to_cpu(cmpl->event_data1); | |
2000 | ||
8280b38e VV |
2001 | if (!bp->fw_health) |
2002 | goto async_event_process_exit; | |
2003 | ||
2151fe08 MC |
2004 | bp->fw_reset_timestamp = jiffies; |
2005 | bp->fw_reset_min_dsecs = cmpl->timestamp_lo; | |
2006 | if (!bp->fw_reset_min_dsecs) | |
2007 | bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS; | |
2008 | bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi); | |
2009 | if (!bp->fw_reset_max_dsecs) | |
2010 | bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS; | |
acfb50e4 VV |
2011 | if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) { |
2012 | netdev_warn(bp->dev, "Firmware fatal reset event received\n"); | |
2013 | set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); | |
2014 | } else { | |
2015 | netdev_warn(bp->dev, "Firmware non-fatal reset event received, max wait time %d msec\n", | |
2016 | bp->fw_reset_max_dsecs * 100); | |
2017 | } | |
2151fe08 MC |
2018 | set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event); |
2019 | break; | |
acfb50e4 | 2020 | } |
7e914027 MC |
2021 | case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: { |
2022 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
2023 | u32 data1 = le32_to_cpu(cmpl->event_data1); | |
2024 | ||
2025 | if (!fw_health) | |
2026 | goto async_event_process_exit; | |
2027 | ||
2028 | fw_health->enabled = EVENT_DATA1_RECOVERY_ENABLED(data1); | |
2029 | fw_health->master = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1); | |
2030 | if (!fw_health->enabled) | |
2031 | break; | |
2032 | ||
2033 | if (netif_msg_drv(bp)) | |
2034 | netdev_info(bp->dev, "Error recovery info: error recovery[%d], master[%d], reset count[0x%x], health status: 0x%x\n", | |
2035 | fw_health->enabled, fw_health->master, | |
2036 | bnxt_fw_health_readl(bp, | |
2037 | BNXT_FW_RESET_CNT_REG), | |
2038 | bnxt_fw_health_readl(bp, | |
2039 | BNXT_FW_HEALTH_REG)); | |
2040 | fw_health->tmr_multiplier = | |
2041 | DIV_ROUND_UP(fw_health->polling_dsecs * HZ, | |
2042 | bp->current_interval * 10); | |
2043 | fw_health->tmr_counter = fw_health->tmr_multiplier; | |
2044 | fw_health->last_fw_heartbeat = | |
2045 | bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); | |
2046 | fw_health->last_fw_reset_cnt = | |
2047 | bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); | |
2048 | goto async_event_process_exit; | |
2049 | } | |
c0c050c5 | 2050 | default: |
19241368 | 2051 | goto async_event_process_exit; |
c0c050c5 | 2052 | } |
c213eae8 | 2053 | bnxt_queue_sp_work(bp); |
19241368 | 2054 | async_event_process_exit: |
a588e458 | 2055 | bnxt_ulp_async_events(bp, cmpl); |
c0c050c5 MC |
2056 | return 0; |
2057 | } | |
2058 | ||
2059 | static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) | |
2060 | { | |
2061 | u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; | |
2062 | struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; | |
2063 | struct hwrm_fwd_req_cmpl *fwd_req_cmpl = | |
2064 | (struct hwrm_fwd_req_cmpl *)txcmp; | |
2065 | ||
2066 | switch (cmpl_type) { | |
2067 | case CMPL_BASE_TYPE_HWRM_DONE: | |
2068 | seq_id = le16_to_cpu(h_cmpl->sequence_id); | |
2069 | if (seq_id == bp->hwrm_intr_seq_id) | |
fc718bb2 | 2070 | bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id; |
c0c050c5 MC |
2071 | else |
2072 | netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id); | |
2073 | break; | |
2074 | ||
2075 | case CMPL_BASE_TYPE_HWRM_FWD_REQ: | |
2076 | vf_id = le16_to_cpu(fwd_req_cmpl->source_id); | |
2077 | ||
2078 | if ((vf_id < bp->pf.first_vf_id) || | |
2079 | (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { | |
2080 | netdev_err(bp->dev, "Msg contains invalid VF id %x\n", | |
2081 | vf_id); | |
2082 | return -EINVAL; | |
2083 | } | |
2084 | ||
2085 | set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); | |
2086 | set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event); | |
c213eae8 | 2087 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
2088 | break; |
2089 | ||
2090 | case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: | |
2091 | bnxt_async_event_process(bp, | |
2092 | (struct hwrm_async_event_cmpl *)txcmp); | |
2093 | ||
2094 | default: | |
2095 | break; | |
2096 | } | |
2097 | ||
2098 | return 0; | |
2099 | } | |
2100 | ||
2101 | static irqreturn_t bnxt_msix(int irq, void *dev_instance) | |
2102 | { | |
2103 | struct bnxt_napi *bnapi = dev_instance; | |
2104 | struct bnxt *bp = bnapi->bp; | |
2105 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2106 | u32 cons = RING_CMP(cpr->cp_raw_cons); | |
2107 | ||
6a8788f2 | 2108 | cpr->event_ctr++; |
c0c050c5 MC |
2109 | prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); |
2110 | napi_schedule(&bnapi->napi); | |
2111 | return IRQ_HANDLED; | |
2112 | } | |
2113 | ||
2114 | static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) | |
2115 | { | |
2116 | u32 raw_cons = cpr->cp_raw_cons; | |
2117 | u16 cons = RING_CMP(raw_cons); | |
2118 | struct tx_cmp *txcmp; | |
2119 | ||
2120 | txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; | |
2121 | ||
2122 | return TX_CMP_VALID(txcmp, raw_cons); | |
2123 | } | |
2124 | ||
c0c050c5 MC |
2125 | static irqreturn_t bnxt_inta(int irq, void *dev_instance) |
2126 | { | |
2127 | struct bnxt_napi *bnapi = dev_instance; | |
2128 | struct bnxt *bp = bnapi->bp; | |
2129 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2130 | u32 cons = RING_CMP(cpr->cp_raw_cons); | |
2131 | u32 int_status; | |
2132 | ||
2133 | prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); | |
2134 | ||
2135 | if (!bnxt_has_work(bp, cpr)) { | |
11809490 | 2136 | int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); |
c0c050c5 MC |
2137 | /* return if erroneous interrupt */ |
2138 | if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) | |
2139 | return IRQ_NONE; | |
2140 | } | |
2141 | ||
2142 | /* disable ring IRQ */ | |
697197e5 | 2143 | BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell); |
c0c050c5 MC |
2144 | |
2145 | /* Return here if interrupt is shared and is disabled. */ | |
2146 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) | |
2147 | return IRQ_HANDLED; | |
2148 | ||
2149 | napi_schedule(&bnapi->napi); | |
2150 | return IRQ_HANDLED; | |
2151 | } | |
2152 | ||
3675b92f MC |
2153 | static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, |
2154 | int budget) | |
c0c050c5 | 2155 | { |
e44758b7 | 2156 | struct bnxt_napi *bnapi = cpr->bnapi; |
c0c050c5 MC |
2157 | u32 raw_cons = cpr->cp_raw_cons; |
2158 | u32 cons; | |
2159 | int tx_pkts = 0; | |
2160 | int rx_pkts = 0; | |
4e5dbbda | 2161 | u8 event = 0; |
c0c050c5 MC |
2162 | struct tx_cmp *txcmp; |
2163 | ||
0fcec985 | 2164 | cpr->has_more_work = 0; |
c0c050c5 MC |
2165 | while (1) { |
2166 | int rc; | |
2167 | ||
2168 | cons = RING_CMP(raw_cons); | |
2169 | txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; | |
2170 | ||
2171 | if (!TX_CMP_VALID(txcmp, raw_cons)) | |
2172 | break; | |
2173 | ||
67a95e20 MC |
2174 | /* The valid test of the entry must be done first before |
2175 | * reading any further. | |
2176 | */ | |
b67daab0 | 2177 | dma_rmb(); |
3675b92f | 2178 | cpr->had_work_done = 1; |
c0c050c5 MC |
2179 | if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { |
2180 | tx_pkts++; | |
2181 | /* return full budget so NAPI will complete. */ | |
73f21c65 | 2182 | if (unlikely(tx_pkts > bp->tx_wake_thresh)) { |
c0c050c5 | 2183 | rx_pkts = budget; |
73f21c65 | 2184 | raw_cons = NEXT_RAW_CMP(raw_cons); |
0fcec985 MC |
2185 | if (budget) |
2186 | cpr->has_more_work = 1; | |
73f21c65 MC |
2187 | break; |
2188 | } | |
c0c050c5 | 2189 | } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { |
2270bc5d | 2190 | if (likely(budget)) |
e44758b7 | 2191 | rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); |
2270bc5d | 2192 | else |
e44758b7 | 2193 | rc = bnxt_force_rx_discard(bp, cpr, &raw_cons, |
2270bc5d | 2194 | &event); |
c0c050c5 MC |
2195 | if (likely(rc >= 0)) |
2196 | rx_pkts += rc; | |
903649e7 MC |
2197 | /* Increment rx_pkts when rc is -ENOMEM to count towards |
2198 | * the NAPI budget. Otherwise, we may potentially loop | |
2199 | * here forever if we consistently cannot allocate | |
2200 | * buffers. | |
2201 | */ | |
2edbdb31 | 2202 | else if (rc == -ENOMEM && budget) |
903649e7 | 2203 | rx_pkts++; |
c0c050c5 MC |
2204 | else if (rc == -EBUSY) /* partial completion */ |
2205 | break; | |
c0c050c5 MC |
2206 | } else if (unlikely((TX_CMP_TYPE(txcmp) == |
2207 | CMPL_BASE_TYPE_HWRM_DONE) || | |
2208 | (TX_CMP_TYPE(txcmp) == | |
2209 | CMPL_BASE_TYPE_HWRM_FWD_REQ) || | |
2210 | (TX_CMP_TYPE(txcmp) == | |
2211 | CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { | |
2212 | bnxt_hwrm_handler(bp, txcmp); | |
2213 | } | |
2214 | raw_cons = NEXT_RAW_CMP(raw_cons); | |
2215 | ||
0fcec985 MC |
2216 | if (rx_pkts && rx_pkts == budget) { |
2217 | cpr->has_more_work = 1; | |
c0c050c5 | 2218 | break; |
0fcec985 | 2219 | } |
c0c050c5 MC |
2220 | } |
2221 | ||
f18c2b77 AG |
2222 | if (event & BNXT_REDIRECT_EVENT) |
2223 | xdp_do_flush_map(); | |
2224 | ||
38413406 MC |
2225 | if (event & BNXT_TX_EVENT) { |
2226 | struct bnxt_tx_ring_info *txr = bnapi->tx_ring; | |
38413406 MC |
2227 | u16 prod = txr->tx_prod; |
2228 | ||
2229 | /* Sync BD data before updating doorbell */ | |
2230 | wmb(); | |
2231 | ||
697197e5 | 2232 | bnxt_db_write_relaxed(bp, &txr->tx_db, prod); |
38413406 MC |
2233 | } |
2234 | ||
c0c050c5 | 2235 | cpr->cp_raw_cons = raw_cons; |
3675b92f MC |
2236 | bnapi->tx_pkts += tx_pkts; |
2237 | bnapi->events |= event; | |
2238 | return rx_pkts; | |
2239 | } | |
c0c050c5 | 2240 | |
3675b92f MC |
2241 | static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi) |
2242 | { | |
2243 | if (bnapi->tx_pkts) { | |
2244 | bnapi->tx_int(bp, bnapi, bnapi->tx_pkts); | |
2245 | bnapi->tx_pkts = 0; | |
2246 | } | |
c0c050c5 | 2247 | |
3675b92f | 2248 | if (bnapi->events & BNXT_RX_EVENT) { |
b6ab4b01 | 2249 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
c0c050c5 | 2250 | |
3675b92f | 2251 | if (bnapi->events & BNXT_AGG_EVENT) |
697197e5 | 2252 | bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); |
e8f267b0 | 2253 | bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); |
c0c050c5 | 2254 | } |
3675b92f MC |
2255 | bnapi->events = 0; |
2256 | } | |
2257 | ||
2258 | static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, | |
2259 | int budget) | |
2260 | { | |
2261 | struct bnxt_napi *bnapi = cpr->bnapi; | |
2262 | int rx_pkts; | |
2263 | ||
2264 | rx_pkts = __bnxt_poll_work(bp, cpr, budget); | |
2265 | ||
2266 | /* ACK completion ring before freeing tx ring and producing new | |
2267 | * buffers in rx/agg rings to prevent overflowing the completion | |
2268 | * ring. | |
2269 | */ | |
2270 | bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons); | |
2271 | ||
2272 | __bnxt_poll_work_done(bp, bnapi); | |
c0c050c5 MC |
2273 | return rx_pkts; |
2274 | } | |
2275 | ||
10bbdaf5 PS |
2276 | static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) |
2277 | { | |
2278 | struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); | |
2279 | struct bnxt *bp = bnapi->bp; | |
2280 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2281 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; | |
2282 | struct tx_cmp *txcmp; | |
2283 | struct rx_cmp_ext *rxcmp1; | |
2284 | u32 cp_cons, tmp_raw_cons; | |
2285 | u32 raw_cons = cpr->cp_raw_cons; | |
2286 | u32 rx_pkts = 0; | |
4e5dbbda | 2287 | u8 event = 0; |
10bbdaf5 PS |
2288 | |
2289 | while (1) { | |
2290 | int rc; | |
2291 | ||
2292 | cp_cons = RING_CMP(raw_cons); | |
2293 | txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
2294 | ||
2295 | if (!TX_CMP_VALID(txcmp, raw_cons)) | |
2296 | break; | |
2297 | ||
2298 | if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { | |
2299 | tmp_raw_cons = NEXT_RAW_CMP(raw_cons); | |
2300 | cp_cons = RING_CMP(tmp_raw_cons); | |
2301 | rxcmp1 = (struct rx_cmp_ext *) | |
2302 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
2303 | ||
2304 | if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) | |
2305 | break; | |
2306 | ||
2307 | /* force an error to recycle the buffer */ | |
2308 | rxcmp1->rx_cmp_cfa_code_errors_v2 |= | |
2309 | cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); | |
2310 | ||
e44758b7 | 2311 | rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); |
2edbdb31 | 2312 | if (likely(rc == -EIO) && budget) |
10bbdaf5 PS |
2313 | rx_pkts++; |
2314 | else if (rc == -EBUSY) /* partial completion */ | |
2315 | break; | |
2316 | } else if (unlikely(TX_CMP_TYPE(txcmp) == | |
2317 | CMPL_BASE_TYPE_HWRM_DONE)) { | |
2318 | bnxt_hwrm_handler(bp, txcmp); | |
2319 | } else { | |
2320 | netdev_err(bp->dev, | |
2321 | "Invalid completion received on special ring\n"); | |
2322 | } | |
2323 | raw_cons = NEXT_RAW_CMP(raw_cons); | |
2324 | ||
2325 | if (rx_pkts == budget) | |
2326 | break; | |
2327 | } | |
2328 | ||
2329 | cpr->cp_raw_cons = raw_cons; | |
697197e5 MC |
2330 | BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons); |
2331 | bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); | |
10bbdaf5 | 2332 | |
434c975a | 2333 | if (event & BNXT_AGG_EVENT) |
697197e5 | 2334 | bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); |
10bbdaf5 PS |
2335 | |
2336 | if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) { | |
6ad20165 | 2337 | napi_complete_done(napi, rx_pkts); |
697197e5 | 2338 | BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); |
10bbdaf5 PS |
2339 | } |
2340 | return rx_pkts; | |
2341 | } | |
2342 | ||
c0c050c5 MC |
2343 | static int bnxt_poll(struct napi_struct *napi, int budget) |
2344 | { | |
2345 | struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); | |
2346 | struct bnxt *bp = bnapi->bp; | |
2347 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2348 | int work_done = 0; | |
2349 | ||
c0c050c5 | 2350 | while (1) { |
e44758b7 | 2351 | work_done += bnxt_poll_work(bp, cpr, budget - work_done); |
c0c050c5 | 2352 | |
73f21c65 MC |
2353 | if (work_done >= budget) { |
2354 | if (!budget) | |
697197e5 | 2355 | BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); |
c0c050c5 | 2356 | break; |
73f21c65 | 2357 | } |
c0c050c5 MC |
2358 | |
2359 | if (!bnxt_has_work(bp, cpr)) { | |
e7b95691 | 2360 | if (napi_complete_done(napi, work_done)) |
697197e5 | 2361 | BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); |
c0c050c5 MC |
2362 | break; |
2363 | } | |
2364 | } | |
6a8788f2 | 2365 | if (bp->flags & BNXT_FLAG_DIM) { |
f06d0ca4 | 2366 | struct dim_sample dim_sample = {}; |
6a8788f2 | 2367 | |
8960b389 TG |
2368 | dim_update_sample(cpr->event_ctr, |
2369 | cpr->rx_packets, | |
2370 | cpr->rx_bytes, | |
2371 | &dim_sample); | |
6a8788f2 AG |
2372 | net_dim(&cpr->dim, dim_sample); |
2373 | } | |
c0c050c5 MC |
2374 | return work_done; |
2375 | } | |
2376 | ||
0fcec985 MC |
2377 | static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) |
2378 | { | |
2379 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2380 | int i, work_done = 0; | |
2381 | ||
2382 | for (i = 0; i < 2; i++) { | |
2383 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; | |
2384 | ||
2385 | if (cpr2) { | |
2386 | work_done += __bnxt_poll_work(bp, cpr2, | |
2387 | budget - work_done); | |
2388 | cpr->has_more_work |= cpr2->has_more_work; | |
2389 | } | |
2390 | } | |
2391 | return work_done; | |
2392 | } | |
2393 | ||
2394 | static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi, | |
2395 | u64 dbr_type, bool all) | |
2396 | { | |
2397 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2398 | int i; | |
2399 | ||
2400 | for (i = 0; i < 2; i++) { | |
2401 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; | |
2402 | struct bnxt_db_info *db; | |
2403 | ||
2404 | if (cpr2 && (all || cpr2->had_work_done)) { | |
2405 | db = &cpr2->cp_db; | |
2406 | writeq(db->db_key64 | dbr_type | | |
2407 | RING_CMP(cpr2->cp_raw_cons), db->doorbell); | |
2408 | cpr2->had_work_done = 0; | |
2409 | } | |
2410 | } | |
2411 | __bnxt_poll_work_done(bp, bnapi); | |
2412 | } | |
2413 | ||
2414 | static int bnxt_poll_p5(struct napi_struct *napi, int budget) | |
2415 | { | |
2416 | struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); | |
2417 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2418 | u32 raw_cons = cpr->cp_raw_cons; | |
2419 | struct bnxt *bp = bnapi->bp; | |
2420 | struct nqe_cn *nqcmp; | |
2421 | int work_done = 0; | |
2422 | u32 cons; | |
2423 | ||
2424 | if (cpr->has_more_work) { | |
2425 | cpr->has_more_work = 0; | |
2426 | work_done = __bnxt_poll_cqs(bp, bnapi, budget); | |
2427 | if (cpr->has_more_work) { | |
2428 | __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, false); | |
2429 | return work_done; | |
2430 | } | |
2431 | __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, true); | |
2432 | if (napi_complete_done(napi, work_done)) | |
2433 | BNXT_DB_NQ_ARM_P5(&cpr->cp_db, cpr->cp_raw_cons); | |
2434 | return work_done; | |
2435 | } | |
2436 | while (1) { | |
2437 | cons = RING_CMP(raw_cons); | |
2438 | nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)]; | |
2439 | ||
2440 | if (!NQ_CMP_VALID(nqcmp, raw_cons)) { | |
2441 | __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, | |
2442 | false); | |
2443 | cpr->cp_raw_cons = raw_cons; | |
2444 | if (napi_complete_done(napi, work_done)) | |
2445 | BNXT_DB_NQ_ARM_P5(&cpr->cp_db, | |
2446 | cpr->cp_raw_cons); | |
2447 | return work_done; | |
2448 | } | |
2449 | ||
2450 | /* The valid test of the entry must be done first before | |
2451 | * reading any further. | |
2452 | */ | |
2453 | dma_rmb(); | |
2454 | ||
2455 | if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) { | |
2456 | u32 idx = le32_to_cpu(nqcmp->cq_handle_low); | |
2457 | struct bnxt_cp_ring_info *cpr2; | |
2458 | ||
2459 | cpr2 = cpr->cp_ring_arr[idx]; | |
2460 | work_done += __bnxt_poll_work(bp, cpr2, | |
2461 | budget - work_done); | |
2462 | cpr->has_more_work = cpr2->has_more_work; | |
2463 | } else { | |
2464 | bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp); | |
2465 | } | |
2466 | raw_cons = NEXT_RAW_CMP(raw_cons); | |
2467 | if (cpr->has_more_work) | |
2468 | break; | |
2469 | } | |
2470 | __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, true); | |
2471 | cpr->cp_raw_cons = raw_cons; | |
2472 | return work_done; | |
2473 | } | |
2474 | ||
c0c050c5 MC |
2475 | static void bnxt_free_tx_skbs(struct bnxt *bp) |
2476 | { | |
2477 | int i, max_idx; | |
2478 | struct pci_dev *pdev = bp->pdev; | |
2479 | ||
b6ab4b01 | 2480 | if (!bp->tx_ring) |
c0c050c5 MC |
2481 | return; |
2482 | ||
2483 | max_idx = bp->tx_nr_pages * TX_DESC_CNT; | |
2484 | for (i = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 2485 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
c0c050c5 MC |
2486 | int j; |
2487 | ||
c0c050c5 MC |
2488 | for (j = 0; j < max_idx;) { |
2489 | struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; | |
f18c2b77 | 2490 | struct sk_buff *skb; |
c0c050c5 MC |
2491 | int k, last; |
2492 | ||
f18c2b77 AG |
2493 | if (i < bp->tx_nr_rings_xdp && |
2494 | tx_buf->action == XDP_REDIRECT) { | |
2495 | dma_unmap_single(&pdev->dev, | |
2496 | dma_unmap_addr(tx_buf, mapping), | |
2497 | dma_unmap_len(tx_buf, len), | |
2498 | PCI_DMA_TODEVICE); | |
2499 | xdp_return_frame(tx_buf->xdpf); | |
2500 | tx_buf->action = 0; | |
2501 | tx_buf->xdpf = NULL; | |
2502 | j++; | |
2503 | continue; | |
2504 | } | |
2505 | ||
2506 | skb = tx_buf->skb; | |
c0c050c5 MC |
2507 | if (!skb) { |
2508 | j++; | |
2509 | continue; | |
2510 | } | |
2511 | ||
2512 | tx_buf->skb = NULL; | |
2513 | ||
2514 | if (tx_buf->is_push) { | |
2515 | dev_kfree_skb(skb); | |
2516 | j += 2; | |
2517 | continue; | |
2518 | } | |
2519 | ||
2520 | dma_unmap_single(&pdev->dev, | |
2521 | dma_unmap_addr(tx_buf, mapping), | |
2522 | skb_headlen(skb), | |
2523 | PCI_DMA_TODEVICE); | |
2524 | ||
2525 | last = tx_buf->nr_frags; | |
2526 | j += 2; | |
d612a579 MC |
2527 | for (k = 0; k < last; k++, j++) { |
2528 | int ring_idx = j & bp->tx_ring_mask; | |
c0c050c5 MC |
2529 | skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; |
2530 | ||
d612a579 | 2531 | tx_buf = &txr->tx_buf_ring[ring_idx]; |
c0c050c5 MC |
2532 | dma_unmap_page( |
2533 | &pdev->dev, | |
2534 | dma_unmap_addr(tx_buf, mapping), | |
2535 | skb_frag_size(frag), PCI_DMA_TODEVICE); | |
2536 | } | |
2537 | dev_kfree_skb(skb); | |
2538 | } | |
2539 | netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); | |
2540 | } | |
2541 | } | |
2542 | ||
2543 | static void bnxt_free_rx_skbs(struct bnxt *bp) | |
2544 | { | |
2545 | int i, max_idx, max_agg_idx; | |
2546 | struct pci_dev *pdev = bp->pdev; | |
2547 | ||
b6ab4b01 | 2548 | if (!bp->rx_ring) |
c0c050c5 MC |
2549 | return; |
2550 | ||
2551 | max_idx = bp->rx_nr_pages * RX_DESC_CNT; | |
2552 | max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; | |
2553 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
b6ab4b01 | 2554 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
ec4d8e7c | 2555 | struct bnxt_tpa_idx_map *map; |
c0c050c5 MC |
2556 | int j; |
2557 | ||
c0c050c5 | 2558 | if (rxr->rx_tpa) { |
79632e9b | 2559 | for (j = 0; j < bp->max_tpa; j++) { |
c0c050c5 MC |
2560 | struct bnxt_tpa_info *tpa_info = |
2561 | &rxr->rx_tpa[j]; | |
2562 | u8 *data = tpa_info->data; | |
2563 | ||
2564 | if (!data) | |
2565 | continue; | |
2566 | ||
c519fe9a SN |
2567 | dma_unmap_single_attrs(&pdev->dev, |
2568 | tpa_info->mapping, | |
2569 | bp->rx_buf_use_size, | |
2570 | bp->rx_dir, | |
2571 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
2572 | |
2573 | tpa_info->data = NULL; | |
2574 | ||
2575 | kfree(data); | |
2576 | } | |
2577 | } | |
2578 | ||
2579 | for (j = 0; j < max_idx; j++) { | |
2580 | struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j]; | |
3ed3a83e | 2581 | dma_addr_t mapping = rx_buf->mapping; |
6bb19474 | 2582 | void *data = rx_buf->data; |
c0c050c5 MC |
2583 | |
2584 | if (!data) | |
2585 | continue; | |
2586 | ||
c0c050c5 MC |
2587 | rx_buf->data = NULL; |
2588 | ||
3ed3a83e MC |
2589 | if (BNXT_RX_PAGE_MODE(bp)) { |
2590 | mapping -= bp->rx_dma_offset; | |
c519fe9a SN |
2591 | dma_unmap_page_attrs(&pdev->dev, mapping, |
2592 | PAGE_SIZE, bp->rx_dir, | |
2593 | DMA_ATTR_WEAK_ORDERING); | |
322b87ca | 2594 | page_pool_recycle_direct(rxr->page_pool, data); |
3ed3a83e | 2595 | } else { |
c519fe9a SN |
2596 | dma_unmap_single_attrs(&pdev->dev, mapping, |
2597 | bp->rx_buf_use_size, | |
2598 | bp->rx_dir, | |
2599 | DMA_ATTR_WEAK_ORDERING); | |
c61fb99c | 2600 | kfree(data); |
3ed3a83e | 2601 | } |
c0c050c5 MC |
2602 | } |
2603 | ||
2604 | for (j = 0; j < max_agg_idx; j++) { | |
2605 | struct bnxt_sw_rx_agg_bd *rx_agg_buf = | |
2606 | &rxr->rx_agg_ring[j]; | |
2607 | struct page *page = rx_agg_buf->page; | |
2608 | ||
2609 | if (!page) | |
2610 | continue; | |
2611 | ||
c519fe9a SN |
2612 | dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping, |
2613 | BNXT_RX_PAGE_SIZE, | |
2614 | PCI_DMA_FROMDEVICE, | |
2615 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
2616 | |
2617 | rx_agg_buf->page = NULL; | |
2618 | __clear_bit(j, rxr->rx_agg_bmap); | |
2619 | ||
2620 | __free_page(page); | |
2621 | } | |
89d0a06c MC |
2622 | if (rxr->rx_page) { |
2623 | __free_page(rxr->rx_page); | |
2624 | rxr->rx_page = NULL; | |
2625 | } | |
ec4d8e7c MC |
2626 | map = rxr->rx_tpa_idx_map; |
2627 | if (map) | |
2628 | memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap)); | |
c0c050c5 MC |
2629 | } |
2630 | } | |
2631 | ||
2632 | static void bnxt_free_skbs(struct bnxt *bp) | |
2633 | { | |
2634 | bnxt_free_tx_skbs(bp); | |
2635 | bnxt_free_rx_skbs(bp); | |
2636 | } | |
2637 | ||
6fe19886 | 2638 | static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) |
c0c050c5 MC |
2639 | { |
2640 | struct pci_dev *pdev = bp->pdev; | |
2641 | int i; | |
2642 | ||
6fe19886 MC |
2643 | for (i = 0; i < rmem->nr_pages; i++) { |
2644 | if (!rmem->pg_arr[i]) | |
c0c050c5 MC |
2645 | continue; |
2646 | ||
6fe19886 MC |
2647 | dma_free_coherent(&pdev->dev, rmem->page_size, |
2648 | rmem->pg_arr[i], rmem->dma_arr[i]); | |
c0c050c5 | 2649 | |
6fe19886 | 2650 | rmem->pg_arr[i] = NULL; |
c0c050c5 | 2651 | } |
6fe19886 | 2652 | if (rmem->pg_tbl) { |
4f49b2b8 MC |
2653 | size_t pg_tbl_size = rmem->nr_pages * 8; |
2654 | ||
2655 | if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) | |
2656 | pg_tbl_size = rmem->page_size; | |
2657 | dma_free_coherent(&pdev->dev, pg_tbl_size, | |
6fe19886 MC |
2658 | rmem->pg_tbl, rmem->pg_tbl_map); |
2659 | rmem->pg_tbl = NULL; | |
c0c050c5 | 2660 | } |
6fe19886 MC |
2661 | if (rmem->vmem_size && *rmem->vmem) { |
2662 | vfree(*rmem->vmem); | |
2663 | *rmem->vmem = NULL; | |
c0c050c5 MC |
2664 | } |
2665 | } | |
2666 | ||
6fe19886 | 2667 | static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) |
c0c050c5 | 2668 | { |
c0c050c5 | 2669 | struct pci_dev *pdev = bp->pdev; |
66cca20a | 2670 | u64 valid_bit = 0; |
6fe19886 | 2671 | int i; |
c0c050c5 | 2672 | |
66cca20a MC |
2673 | if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG)) |
2674 | valid_bit = PTU_PTE_VALID; | |
4f49b2b8 MC |
2675 | if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) { |
2676 | size_t pg_tbl_size = rmem->nr_pages * 8; | |
2677 | ||
2678 | if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) | |
2679 | pg_tbl_size = rmem->page_size; | |
2680 | rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size, | |
6fe19886 | 2681 | &rmem->pg_tbl_map, |
c0c050c5 | 2682 | GFP_KERNEL); |
6fe19886 | 2683 | if (!rmem->pg_tbl) |
c0c050c5 MC |
2684 | return -ENOMEM; |
2685 | } | |
2686 | ||
6fe19886 | 2687 | for (i = 0; i < rmem->nr_pages; i++) { |
66cca20a MC |
2688 | u64 extra_bits = valid_bit; |
2689 | ||
6fe19886 MC |
2690 | rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev, |
2691 | rmem->page_size, | |
2692 | &rmem->dma_arr[i], | |
c0c050c5 | 2693 | GFP_KERNEL); |
6fe19886 | 2694 | if (!rmem->pg_arr[i]) |
c0c050c5 MC |
2695 | return -ENOMEM; |
2696 | ||
3be8136c MC |
2697 | if (rmem->init_val) |
2698 | memset(rmem->pg_arr[i], rmem->init_val, | |
2699 | rmem->page_size); | |
4f49b2b8 | 2700 | if (rmem->nr_pages > 1 || rmem->depth > 0) { |
66cca20a MC |
2701 | if (i == rmem->nr_pages - 2 && |
2702 | (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) | |
2703 | extra_bits |= PTU_PTE_NEXT_TO_LAST; | |
2704 | else if (i == rmem->nr_pages - 1 && | |
2705 | (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) | |
2706 | extra_bits |= PTU_PTE_LAST; | |
2707 | rmem->pg_tbl[i] = | |
2708 | cpu_to_le64(rmem->dma_arr[i] | extra_bits); | |
2709 | } | |
c0c050c5 MC |
2710 | } |
2711 | ||
6fe19886 MC |
2712 | if (rmem->vmem_size) { |
2713 | *rmem->vmem = vzalloc(rmem->vmem_size); | |
2714 | if (!(*rmem->vmem)) | |
c0c050c5 MC |
2715 | return -ENOMEM; |
2716 | } | |
2717 | return 0; | |
2718 | } | |
2719 | ||
4a228a3a MC |
2720 | static void bnxt_free_tpa_info(struct bnxt *bp) |
2721 | { | |
2722 | int i; | |
2723 | ||
2724 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
2725 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; | |
2726 | ||
ec4d8e7c MC |
2727 | kfree(rxr->rx_tpa_idx_map); |
2728 | rxr->rx_tpa_idx_map = NULL; | |
79632e9b MC |
2729 | if (rxr->rx_tpa) { |
2730 | kfree(rxr->rx_tpa[0].agg_arr); | |
2731 | rxr->rx_tpa[0].agg_arr = NULL; | |
2732 | } | |
4a228a3a MC |
2733 | kfree(rxr->rx_tpa); |
2734 | rxr->rx_tpa = NULL; | |
2735 | } | |
2736 | } | |
2737 | ||
2738 | static int bnxt_alloc_tpa_info(struct bnxt *bp) | |
2739 | { | |
79632e9b MC |
2740 | int i, j, total_aggs = 0; |
2741 | ||
2742 | bp->max_tpa = MAX_TPA; | |
2743 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
2744 | if (!bp->max_tpa_v2) | |
2745 | return 0; | |
2746 | bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5); | |
2747 | total_aggs = bp->max_tpa * MAX_SKB_FRAGS; | |
2748 | } | |
4a228a3a MC |
2749 | |
2750 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
2751 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; | |
79632e9b | 2752 | struct rx_agg_cmp *agg; |
4a228a3a | 2753 | |
79632e9b | 2754 | rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info), |
4a228a3a MC |
2755 | GFP_KERNEL); |
2756 | if (!rxr->rx_tpa) | |
2757 | return -ENOMEM; | |
79632e9b MC |
2758 | |
2759 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
2760 | continue; | |
2761 | agg = kcalloc(total_aggs, sizeof(*agg), GFP_KERNEL); | |
2762 | rxr->rx_tpa[0].agg_arr = agg; | |
2763 | if (!agg) | |
2764 | return -ENOMEM; | |
2765 | for (j = 1; j < bp->max_tpa; j++) | |
2766 | rxr->rx_tpa[j].agg_arr = agg + j * MAX_SKB_FRAGS; | |
ec4d8e7c MC |
2767 | rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map), |
2768 | GFP_KERNEL); | |
2769 | if (!rxr->rx_tpa_idx_map) | |
2770 | return -ENOMEM; | |
4a228a3a MC |
2771 | } |
2772 | return 0; | |
2773 | } | |
2774 | ||
c0c050c5 MC |
2775 | static void bnxt_free_rx_rings(struct bnxt *bp) |
2776 | { | |
2777 | int i; | |
2778 | ||
b6ab4b01 | 2779 | if (!bp->rx_ring) |
c0c050c5 MC |
2780 | return; |
2781 | ||
4a228a3a | 2782 | bnxt_free_tpa_info(bp); |
c0c050c5 | 2783 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 2784 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
c0c050c5 MC |
2785 | struct bnxt_ring_struct *ring; |
2786 | ||
c6d30e83 MC |
2787 | if (rxr->xdp_prog) |
2788 | bpf_prog_put(rxr->xdp_prog); | |
2789 | ||
96a8604f JDB |
2790 | if (xdp_rxq_info_is_reg(&rxr->xdp_rxq)) |
2791 | xdp_rxq_info_unreg(&rxr->xdp_rxq); | |
2792 | ||
12479f62 | 2793 | page_pool_destroy(rxr->page_pool); |
322b87ca AG |
2794 | rxr->page_pool = NULL; |
2795 | ||
c0c050c5 MC |
2796 | kfree(rxr->rx_agg_bmap); |
2797 | rxr->rx_agg_bmap = NULL; | |
2798 | ||
2799 | ring = &rxr->rx_ring_struct; | |
6fe19886 | 2800 | bnxt_free_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2801 | |
2802 | ring = &rxr->rx_agg_ring_struct; | |
6fe19886 | 2803 | bnxt_free_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2804 | } |
2805 | } | |
2806 | ||
322b87ca AG |
2807 | static int bnxt_alloc_rx_page_pool(struct bnxt *bp, |
2808 | struct bnxt_rx_ring_info *rxr) | |
2809 | { | |
2810 | struct page_pool_params pp = { 0 }; | |
2811 | ||
2812 | pp.pool_size = bp->rx_ring_size; | |
2813 | pp.nid = dev_to_node(&bp->pdev->dev); | |
2814 | pp.dev = &bp->pdev->dev; | |
2815 | pp.dma_dir = DMA_BIDIRECTIONAL; | |
2816 | ||
2817 | rxr->page_pool = page_pool_create(&pp); | |
2818 | if (IS_ERR(rxr->page_pool)) { | |
2819 | int err = PTR_ERR(rxr->page_pool); | |
2820 | ||
2821 | rxr->page_pool = NULL; | |
2822 | return err; | |
2823 | } | |
2824 | return 0; | |
2825 | } | |
2826 | ||
c0c050c5 MC |
2827 | static int bnxt_alloc_rx_rings(struct bnxt *bp) |
2828 | { | |
4a228a3a | 2829 | int i, rc = 0, agg_rings = 0; |
c0c050c5 | 2830 | |
b6ab4b01 MC |
2831 | if (!bp->rx_ring) |
2832 | return -ENOMEM; | |
2833 | ||
c0c050c5 MC |
2834 | if (bp->flags & BNXT_FLAG_AGG_RINGS) |
2835 | agg_rings = 1; | |
2836 | ||
c0c050c5 | 2837 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 2838 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
c0c050c5 MC |
2839 | struct bnxt_ring_struct *ring; |
2840 | ||
c0c050c5 MC |
2841 | ring = &rxr->rx_ring_struct; |
2842 | ||
322b87ca AG |
2843 | rc = bnxt_alloc_rx_page_pool(bp, rxr); |
2844 | if (rc) | |
2845 | return rc; | |
2846 | ||
96a8604f | 2847 | rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i); |
12479f62 | 2848 | if (rc < 0) |
96a8604f JDB |
2849 | return rc; |
2850 | ||
f18c2b77 | 2851 | rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq, |
322b87ca AG |
2852 | MEM_TYPE_PAGE_POOL, |
2853 | rxr->page_pool); | |
f18c2b77 AG |
2854 | if (rc) { |
2855 | xdp_rxq_info_unreg(&rxr->xdp_rxq); | |
2856 | return rc; | |
2857 | } | |
2858 | ||
6fe19886 | 2859 | rc = bnxt_alloc_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2860 | if (rc) |
2861 | return rc; | |
2862 | ||
2c61d211 | 2863 | ring->grp_idx = i; |
c0c050c5 MC |
2864 | if (agg_rings) { |
2865 | u16 mem_size; | |
2866 | ||
2867 | ring = &rxr->rx_agg_ring_struct; | |
6fe19886 | 2868 | rc = bnxt_alloc_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2869 | if (rc) |
2870 | return rc; | |
2871 | ||
9899bb59 | 2872 | ring->grp_idx = i; |
c0c050c5 MC |
2873 | rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; |
2874 | mem_size = rxr->rx_agg_bmap_size / 8; | |
2875 | rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); | |
2876 | if (!rxr->rx_agg_bmap) | |
2877 | return -ENOMEM; | |
c0c050c5 MC |
2878 | } |
2879 | } | |
4a228a3a MC |
2880 | if (bp->flags & BNXT_FLAG_TPA) |
2881 | rc = bnxt_alloc_tpa_info(bp); | |
2882 | return rc; | |
c0c050c5 MC |
2883 | } |
2884 | ||
2885 | static void bnxt_free_tx_rings(struct bnxt *bp) | |
2886 | { | |
2887 | int i; | |
2888 | struct pci_dev *pdev = bp->pdev; | |
2889 | ||
b6ab4b01 | 2890 | if (!bp->tx_ring) |
c0c050c5 MC |
2891 | return; |
2892 | ||
2893 | for (i = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 2894 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
c0c050c5 MC |
2895 | struct bnxt_ring_struct *ring; |
2896 | ||
c0c050c5 MC |
2897 | if (txr->tx_push) { |
2898 | dma_free_coherent(&pdev->dev, bp->tx_push_size, | |
2899 | txr->tx_push, txr->tx_push_mapping); | |
2900 | txr->tx_push = NULL; | |
2901 | } | |
2902 | ||
2903 | ring = &txr->tx_ring_struct; | |
2904 | ||
6fe19886 | 2905 | bnxt_free_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2906 | } |
2907 | } | |
2908 | ||
2909 | static int bnxt_alloc_tx_rings(struct bnxt *bp) | |
2910 | { | |
2911 | int i, j, rc; | |
2912 | struct pci_dev *pdev = bp->pdev; | |
2913 | ||
2914 | bp->tx_push_size = 0; | |
2915 | if (bp->tx_push_thresh) { | |
2916 | int push_size; | |
2917 | ||
2918 | push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + | |
2919 | bp->tx_push_thresh); | |
2920 | ||
4419dbe6 | 2921 | if (push_size > 256) { |
c0c050c5 MC |
2922 | push_size = 0; |
2923 | bp->tx_push_thresh = 0; | |
2924 | } | |
2925 | ||
2926 | bp->tx_push_size = push_size; | |
2927 | } | |
2928 | ||
2929 | for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 2930 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
c0c050c5 | 2931 | struct bnxt_ring_struct *ring; |
2e8ef77e | 2932 | u8 qidx; |
c0c050c5 | 2933 | |
c0c050c5 MC |
2934 | ring = &txr->tx_ring_struct; |
2935 | ||
6fe19886 | 2936 | rc = bnxt_alloc_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2937 | if (rc) |
2938 | return rc; | |
2939 | ||
9899bb59 | 2940 | ring->grp_idx = txr->bnapi->index; |
c0c050c5 | 2941 | if (bp->tx_push_size) { |
c0c050c5 MC |
2942 | dma_addr_t mapping; |
2943 | ||
2944 | /* One pre-allocated DMA buffer to backup | |
2945 | * TX push operation | |
2946 | */ | |
2947 | txr->tx_push = dma_alloc_coherent(&pdev->dev, | |
2948 | bp->tx_push_size, | |
2949 | &txr->tx_push_mapping, | |
2950 | GFP_KERNEL); | |
2951 | ||
2952 | if (!txr->tx_push) | |
2953 | return -ENOMEM; | |
2954 | ||
c0c050c5 MC |
2955 | mapping = txr->tx_push_mapping + |
2956 | sizeof(struct tx_push_bd); | |
4419dbe6 | 2957 | txr->data_mapping = cpu_to_le64(mapping); |
c0c050c5 | 2958 | } |
2e8ef77e MC |
2959 | qidx = bp->tc_to_qidx[j]; |
2960 | ring->queue_id = bp->q_info[qidx].queue_id; | |
5f449249 MC |
2961 | if (i < bp->tx_nr_rings_xdp) |
2962 | continue; | |
c0c050c5 MC |
2963 | if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) |
2964 | j++; | |
2965 | } | |
2966 | return 0; | |
2967 | } | |
2968 | ||
2969 | static void bnxt_free_cp_rings(struct bnxt *bp) | |
2970 | { | |
2971 | int i; | |
2972 | ||
2973 | if (!bp->bnapi) | |
2974 | return; | |
2975 | ||
2976 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
2977 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
2978 | struct bnxt_cp_ring_info *cpr; | |
2979 | struct bnxt_ring_struct *ring; | |
50e3ab78 | 2980 | int j; |
c0c050c5 MC |
2981 | |
2982 | if (!bnapi) | |
2983 | continue; | |
2984 | ||
2985 | cpr = &bnapi->cp_ring; | |
2986 | ring = &cpr->cp_ring_struct; | |
2987 | ||
6fe19886 | 2988 | bnxt_free_ring(bp, &ring->ring_mem); |
50e3ab78 MC |
2989 | |
2990 | for (j = 0; j < 2; j++) { | |
2991 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; | |
2992 | ||
2993 | if (cpr2) { | |
2994 | ring = &cpr2->cp_ring_struct; | |
2995 | bnxt_free_ring(bp, &ring->ring_mem); | |
2996 | kfree(cpr2); | |
2997 | cpr->cp_ring_arr[j] = NULL; | |
2998 | } | |
2999 | } | |
c0c050c5 MC |
3000 | } |
3001 | } | |
3002 | ||
50e3ab78 MC |
3003 | static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp) |
3004 | { | |
3005 | struct bnxt_ring_mem_info *rmem; | |
3006 | struct bnxt_ring_struct *ring; | |
3007 | struct bnxt_cp_ring_info *cpr; | |
3008 | int rc; | |
3009 | ||
3010 | cpr = kzalloc(sizeof(*cpr), GFP_KERNEL); | |
3011 | if (!cpr) | |
3012 | return NULL; | |
3013 | ||
3014 | ring = &cpr->cp_ring_struct; | |
3015 | rmem = &ring->ring_mem; | |
3016 | rmem->nr_pages = bp->cp_nr_pages; | |
3017 | rmem->page_size = HW_CMPD_RING_SIZE; | |
3018 | rmem->pg_arr = (void **)cpr->cp_desc_ring; | |
3019 | rmem->dma_arr = cpr->cp_desc_mapping; | |
3020 | rmem->flags = BNXT_RMEM_RING_PTE_FLAG; | |
3021 | rc = bnxt_alloc_ring(bp, rmem); | |
3022 | if (rc) { | |
3023 | bnxt_free_ring(bp, rmem); | |
3024 | kfree(cpr); | |
3025 | cpr = NULL; | |
3026 | } | |
3027 | return cpr; | |
3028 | } | |
3029 | ||
c0c050c5 MC |
3030 | static int bnxt_alloc_cp_rings(struct bnxt *bp) |
3031 | { | |
50e3ab78 | 3032 | bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS); |
e5811b8c | 3033 | int i, rc, ulp_base_vec, ulp_msix; |
c0c050c5 | 3034 | |
e5811b8c MC |
3035 | ulp_msix = bnxt_get_ulp_msix_num(bp); |
3036 | ulp_base_vec = bnxt_get_ulp_msix_base(bp); | |
c0c050c5 MC |
3037 | for (i = 0; i < bp->cp_nr_rings; i++) { |
3038 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
3039 | struct bnxt_cp_ring_info *cpr; | |
3040 | struct bnxt_ring_struct *ring; | |
3041 | ||
3042 | if (!bnapi) | |
3043 | continue; | |
3044 | ||
3045 | cpr = &bnapi->cp_ring; | |
50e3ab78 | 3046 | cpr->bnapi = bnapi; |
c0c050c5 MC |
3047 | ring = &cpr->cp_ring_struct; |
3048 | ||
6fe19886 | 3049 | rc = bnxt_alloc_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
3050 | if (rc) |
3051 | return rc; | |
e5811b8c MC |
3052 | |
3053 | if (ulp_msix && i >= ulp_base_vec) | |
3054 | ring->map_idx = i + ulp_msix; | |
3055 | else | |
3056 | ring->map_idx = i; | |
50e3ab78 MC |
3057 | |
3058 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
3059 | continue; | |
3060 | ||
3061 | if (i < bp->rx_nr_rings) { | |
3062 | struct bnxt_cp_ring_info *cpr2 = | |
3063 | bnxt_alloc_cp_sub_ring(bp); | |
3064 | ||
3065 | cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2; | |
3066 | if (!cpr2) | |
3067 | return -ENOMEM; | |
3068 | cpr2->bnapi = bnapi; | |
3069 | } | |
3070 | if ((sh && i < bp->tx_nr_rings) || | |
3071 | (!sh && i >= bp->rx_nr_rings)) { | |
3072 | struct bnxt_cp_ring_info *cpr2 = | |
3073 | bnxt_alloc_cp_sub_ring(bp); | |
3074 | ||
3075 | cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2; | |
3076 | if (!cpr2) | |
3077 | return -ENOMEM; | |
3078 | cpr2->bnapi = bnapi; | |
3079 | } | |
c0c050c5 MC |
3080 | } |
3081 | return 0; | |
3082 | } | |
3083 | ||
3084 | static void bnxt_init_ring_struct(struct bnxt *bp) | |
3085 | { | |
3086 | int i; | |
3087 | ||
3088 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3089 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
6fe19886 | 3090 | struct bnxt_ring_mem_info *rmem; |
c0c050c5 MC |
3091 | struct bnxt_cp_ring_info *cpr; |
3092 | struct bnxt_rx_ring_info *rxr; | |
3093 | struct bnxt_tx_ring_info *txr; | |
3094 | struct bnxt_ring_struct *ring; | |
3095 | ||
3096 | if (!bnapi) | |
3097 | continue; | |
3098 | ||
3099 | cpr = &bnapi->cp_ring; | |
3100 | ring = &cpr->cp_ring_struct; | |
6fe19886 MC |
3101 | rmem = &ring->ring_mem; |
3102 | rmem->nr_pages = bp->cp_nr_pages; | |
3103 | rmem->page_size = HW_CMPD_RING_SIZE; | |
3104 | rmem->pg_arr = (void **)cpr->cp_desc_ring; | |
3105 | rmem->dma_arr = cpr->cp_desc_mapping; | |
3106 | rmem->vmem_size = 0; | |
c0c050c5 | 3107 | |
b6ab4b01 | 3108 | rxr = bnapi->rx_ring; |
3b2b7d9d MC |
3109 | if (!rxr) |
3110 | goto skip_rx; | |
3111 | ||
c0c050c5 | 3112 | ring = &rxr->rx_ring_struct; |
6fe19886 MC |
3113 | rmem = &ring->ring_mem; |
3114 | rmem->nr_pages = bp->rx_nr_pages; | |
3115 | rmem->page_size = HW_RXBD_RING_SIZE; | |
3116 | rmem->pg_arr = (void **)rxr->rx_desc_ring; | |
3117 | rmem->dma_arr = rxr->rx_desc_mapping; | |
3118 | rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; | |
3119 | rmem->vmem = (void **)&rxr->rx_buf_ring; | |
c0c050c5 MC |
3120 | |
3121 | ring = &rxr->rx_agg_ring_struct; | |
6fe19886 MC |
3122 | rmem = &ring->ring_mem; |
3123 | rmem->nr_pages = bp->rx_agg_nr_pages; | |
3124 | rmem->page_size = HW_RXBD_RING_SIZE; | |
3125 | rmem->pg_arr = (void **)rxr->rx_agg_desc_ring; | |
3126 | rmem->dma_arr = rxr->rx_agg_desc_mapping; | |
3127 | rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; | |
3128 | rmem->vmem = (void **)&rxr->rx_agg_ring; | |
c0c050c5 | 3129 | |
3b2b7d9d | 3130 | skip_rx: |
b6ab4b01 | 3131 | txr = bnapi->tx_ring; |
3b2b7d9d MC |
3132 | if (!txr) |
3133 | continue; | |
3134 | ||
c0c050c5 | 3135 | ring = &txr->tx_ring_struct; |
6fe19886 MC |
3136 | rmem = &ring->ring_mem; |
3137 | rmem->nr_pages = bp->tx_nr_pages; | |
3138 | rmem->page_size = HW_RXBD_RING_SIZE; | |
3139 | rmem->pg_arr = (void **)txr->tx_desc_ring; | |
3140 | rmem->dma_arr = txr->tx_desc_mapping; | |
3141 | rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; | |
3142 | rmem->vmem = (void **)&txr->tx_buf_ring; | |
c0c050c5 MC |
3143 | } |
3144 | } | |
3145 | ||
3146 | static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) | |
3147 | { | |
3148 | int i; | |
3149 | u32 prod; | |
3150 | struct rx_bd **rx_buf_ring; | |
3151 | ||
6fe19886 MC |
3152 | rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr; |
3153 | for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) { | |
c0c050c5 MC |
3154 | int j; |
3155 | struct rx_bd *rxbd; | |
3156 | ||
3157 | rxbd = rx_buf_ring[i]; | |
3158 | if (!rxbd) | |
3159 | continue; | |
3160 | ||
3161 | for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { | |
3162 | rxbd->rx_bd_len_flags_type = cpu_to_le32(type); | |
3163 | rxbd->rx_bd_opaque = prod; | |
3164 | } | |
3165 | } | |
3166 | } | |
3167 | ||
3168 | static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) | |
3169 | { | |
3170 | struct net_device *dev = bp->dev; | |
c0c050c5 MC |
3171 | struct bnxt_rx_ring_info *rxr; |
3172 | struct bnxt_ring_struct *ring; | |
3173 | u32 prod, type; | |
3174 | int i; | |
3175 | ||
c0c050c5 MC |
3176 | type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | |
3177 | RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; | |
3178 | ||
3179 | if (NET_IP_ALIGN == 2) | |
3180 | type |= RX_BD_FLAGS_SOP; | |
3181 | ||
b6ab4b01 | 3182 | rxr = &bp->rx_ring[ring_nr]; |
c0c050c5 MC |
3183 | ring = &rxr->rx_ring_struct; |
3184 | bnxt_init_rxbd_pages(ring, type); | |
3185 | ||
c6d30e83 | 3186 | if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) { |
85192dbf AN |
3187 | bpf_prog_add(bp->xdp_prog, 1); |
3188 | rxr->xdp_prog = bp->xdp_prog; | |
c6d30e83 | 3189 | } |
c0c050c5 MC |
3190 | prod = rxr->rx_prod; |
3191 | for (i = 0; i < bp->rx_ring_size; i++) { | |
3192 | if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) { | |
3193 | netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", | |
3194 | ring_nr, i, bp->rx_ring_size); | |
3195 | break; | |
3196 | } | |
3197 | prod = NEXT_RX(prod); | |
3198 | } | |
3199 | rxr->rx_prod = prod; | |
3200 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
3201 | ||
edd0c2cc MC |
3202 | ring = &rxr->rx_agg_ring_struct; |
3203 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
3204 | ||
c0c050c5 MC |
3205 | if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) |
3206 | return 0; | |
3207 | ||
2839f28b | 3208 | type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) | |
c0c050c5 MC |
3209 | RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; |
3210 | ||
3211 | bnxt_init_rxbd_pages(ring, type); | |
3212 | ||
3213 | prod = rxr->rx_agg_prod; | |
3214 | for (i = 0; i < bp->rx_agg_ring_size; i++) { | |
3215 | if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) { | |
3216 | netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", | |
3217 | ring_nr, i, bp->rx_ring_size); | |
3218 | break; | |
3219 | } | |
3220 | prod = NEXT_RX_AGG(prod); | |
3221 | } | |
3222 | rxr->rx_agg_prod = prod; | |
c0c050c5 MC |
3223 | |
3224 | if (bp->flags & BNXT_FLAG_TPA) { | |
3225 | if (rxr->rx_tpa) { | |
3226 | u8 *data; | |
3227 | dma_addr_t mapping; | |
3228 | ||
79632e9b | 3229 | for (i = 0; i < bp->max_tpa; i++) { |
c0c050c5 MC |
3230 | data = __bnxt_alloc_rx_data(bp, &mapping, |
3231 | GFP_KERNEL); | |
3232 | if (!data) | |
3233 | return -ENOMEM; | |
3234 | ||
3235 | rxr->rx_tpa[i].data = data; | |
b3dba77c | 3236 | rxr->rx_tpa[i].data_ptr = data + bp->rx_offset; |
c0c050c5 MC |
3237 | rxr->rx_tpa[i].mapping = mapping; |
3238 | } | |
3239 | } else { | |
3240 | netdev_err(bp->dev, "No resource allocated for LRO/GRO\n"); | |
3241 | return -ENOMEM; | |
3242 | } | |
3243 | } | |
3244 | ||
3245 | return 0; | |
3246 | } | |
3247 | ||
2247925f SP |
3248 | static void bnxt_init_cp_rings(struct bnxt *bp) |
3249 | { | |
3e08b184 | 3250 | int i, j; |
2247925f SP |
3251 | |
3252 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3253 | struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; | |
3254 | struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; | |
3255 | ||
3256 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
6a8788f2 AG |
3257 | cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; |
3258 | cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; | |
3e08b184 MC |
3259 | for (j = 0; j < 2; j++) { |
3260 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; | |
3261 | ||
3262 | if (!cpr2) | |
3263 | continue; | |
3264 | ||
3265 | ring = &cpr2->cp_ring_struct; | |
3266 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
3267 | cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; | |
3268 | cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; | |
3269 | } | |
2247925f SP |
3270 | } |
3271 | } | |
3272 | ||
c0c050c5 MC |
3273 | static int bnxt_init_rx_rings(struct bnxt *bp) |
3274 | { | |
3275 | int i, rc = 0; | |
3276 | ||
c61fb99c | 3277 | if (BNXT_RX_PAGE_MODE(bp)) { |
c6d30e83 MC |
3278 | bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM; |
3279 | bp->rx_dma_offset = XDP_PACKET_HEADROOM; | |
c61fb99c MC |
3280 | } else { |
3281 | bp->rx_offset = BNXT_RX_OFFSET; | |
3282 | bp->rx_dma_offset = BNXT_RX_DMA_OFFSET; | |
3283 | } | |
b3dba77c | 3284 | |
c0c050c5 MC |
3285 | for (i = 0; i < bp->rx_nr_rings; i++) { |
3286 | rc = bnxt_init_one_rx_ring(bp, i); | |
3287 | if (rc) | |
3288 | break; | |
3289 | } | |
3290 | ||
3291 | return rc; | |
3292 | } | |
3293 | ||
3294 | static int bnxt_init_tx_rings(struct bnxt *bp) | |
3295 | { | |
3296 | u16 i; | |
3297 | ||
3298 | bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, | |
3299 | MAX_SKB_FRAGS + 1); | |
3300 | ||
3301 | for (i = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 3302 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
c0c050c5 MC |
3303 | struct bnxt_ring_struct *ring = &txr->tx_ring_struct; |
3304 | ||
3305 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
3306 | } | |
3307 | ||
3308 | return 0; | |
3309 | } | |
3310 | ||
3311 | static void bnxt_free_ring_grps(struct bnxt *bp) | |
3312 | { | |
3313 | kfree(bp->grp_info); | |
3314 | bp->grp_info = NULL; | |
3315 | } | |
3316 | ||
3317 | static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) | |
3318 | { | |
3319 | int i; | |
3320 | ||
3321 | if (irq_re_init) { | |
3322 | bp->grp_info = kcalloc(bp->cp_nr_rings, | |
3323 | sizeof(struct bnxt_ring_grp_info), | |
3324 | GFP_KERNEL); | |
3325 | if (!bp->grp_info) | |
3326 | return -ENOMEM; | |
3327 | } | |
3328 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3329 | if (irq_re_init) | |
3330 | bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; | |
3331 | bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; | |
3332 | bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; | |
3333 | bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; | |
3334 | bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; | |
3335 | } | |
3336 | return 0; | |
3337 | } | |
3338 | ||
3339 | static void bnxt_free_vnics(struct bnxt *bp) | |
3340 | { | |
3341 | kfree(bp->vnic_info); | |
3342 | bp->vnic_info = NULL; | |
3343 | bp->nr_vnics = 0; | |
3344 | } | |
3345 | ||
3346 | static int bnxt_alloc_vnics(struct bnxt *bp) | |
3347 | { | |
3348 | int num_vnics = 1; | |
3349 | ||
3350 | #ifdef CONFIG_RFS_ACCEL | |
9b3d15e6 | 3351 | if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) |
c0c050c5 MC |
3352 | num_vnics += bp->rx_nr_rings; |
3353 | #endif | |
3354 | ||
dc52c6c7 PS |
3355 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) |
3356 | num_vnics++; | |
3357 | ||
c0c050c5 MC |
3358 | bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), |
3359 | GFP_KERNEL); | |
3360 | if (!bp->vnic_info) | |
3361 | return -ENOMEM; | |
3362 | ||
3363 | bp->nr_vnics = num_vnics; | |
3364 | return 0; | |
3365 | } | |
3366 | ||
3367 | static void bnxt_init_vnics(struct bnxt *bp) | |
3368 | { | |
3369 | int i; | |
3370 | ||
3371 | for (i = 0; i < bp->nr_vnics; i++) { | |
3372 | struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; | |
44c6f72a | 3373 | int j; |
c0c050c5 MC |
3374 | |
3375 | vnic->fw_vnic_id = INVALID_HW_RING_ID; | |
44c6f72a MC |
3376 | for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) |
3377 | vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID; | |
3378 | ||
c0c050c5 MC |
3379 | vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; |
3380 | ||
3381 | if (bp->vnic_info[i].rss_hash_key) { | |
3382 | if (i == 0) | |
3383 | prandom_bytes(vnic->rss_hash_key, | |
3384 | HW_HASH_KEY_SIZE); | |
3385 | else | |
3386 | memcpy(vnic->rss_hash_key, | |
3387 | bp->vnic_info[0].rss_hash_key, | |
3388 | HW_HASH_KEY_SIZE); | |
3389 | } | |
3390 | } | |
3391 | } | |
3392 | ||
3393 | static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) | |
3394 | { | |
3395 | int pages; | |
3396 | ||
3397 | pages = ring_size / desc_per_pg; | |
3398 | ||
3399 | if (!pages) | |
3400 | return 1; | |
3401 | ||
3402 | pages++; | |
3403 | ||
3404 | while (pages & (pages - 1)) | |
3405 | pages++; | |
3406 | ||
3407 | return pages; | |
3408 | } | |
3409 | ||
c6d30e83 | 3410 | void bnxt_set_tpa_flags(struct bnxt *bp) |
c0c050c5 MC |
3411 | { |
3412 | bp->flags &= ~BNXT_FLAG_TPA; | |
341138c3 MC |
3413 | if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) |
3414 | return; | |
c0c050c5 MC |
3415 | if (bp->dev->features & NETIF_F_LRO) |
3416 | bp->flags |= BNXT_FLAG_LRO; | |
1054aee8 | 3417 | else if (bp->dev->features & NETIF_F_GRO_HW) |
c0c050c5 MC |
3418 | bp->flags |= BNXT_FLAG_GRO; |
3419 | } | |
3420 | ||
3421 | /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must | |
3422 | * be set on entry. | |
3423 | */ | |
3424 | void bnxt_set_ring_params(struct bnxt *bp) | |
3425 | { | |
3426 | u32 ring_size, rx_size, rx_space; | |
3427 | u32 agg_factor = 0, agg_ring_size = 0; | |
3428 | ||
3429 | /* 8 for CRC and VLAN */ | |
3430 | rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); | |
3431 | ||
3432 | rx_space = rx_size + NET_SKB_PAD + | |
3433 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
3434 | ||
3435 | bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; | |
3436 | ring_size = bp->rx_ring_size; | |
3437 | bp->rx_agg_ring_size = 0; | |
3438 | bp->rx_agg_nr_pages = 0; | |
3439 | ||
3440 | if (bp->flags & BNXT_FLAG_TPA) | |
2839f28b | 3441 | agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE); |
c0c050c5 MC |
3442 | |
3443 | bp->flags &= ~BNXT_FLAG_JUMBO; | |
bdbd1eb5 | 3444 | if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) { |
c0c050c5 MC |
3445 | u32 jumbo_factor; |
3446 | ||
3447 | bp->flags |= BNXT_FLAG_JUMBO; | |
3448 | jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; | |
3449 | if (jumbo_factor > agg_factor) | |
3450 | agg_factor = jumbo_factor; | |
3451 | } | |
3452 | agg_ring_size = ring_size * agg_factor; | |
3453 | ||
3454 | if (agg_ring_size) { | |
3455 | bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, | |
3456 | RX_DESC_CNT); | |
3457 | if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { | |
3458 | u32 tmp = agg_ring_size; | |
3459 | ||
3460 | bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; | |
3461 | agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; | |
3462 | netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", | |
3463 | tmp, agg_ring_size); | |
3464 | } | |
3465 | bp->rx_agg_ring_size = agg_ring_size; | |
3466 | bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; | |
3467 | rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); | |
3468 | rx_space = rx_size + NET_SKB_PAD + | |
3469 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
3470 | } | |
3471 | ||
3472 | bp->rx_buf_use_size = rx_size; | |
3473 | bp->rx_buf_size = rx_space; | |
3474 | ||
3475 | bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); | |
3476 | bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; | |
3477 | ||
3478 | ring_size = bp->tx_ring_size; | |
3479 | bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); | |
3480 | bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; | |
3481 | ||
3482 | ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size; | |
3483 | bp->cp_ring_size = ring_size; | |
3484 | ||
3485 | bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); | |
3486 | if (bp->cp_nr_pages > MAX_CP_PAGES) { | |
3487 | bp->cp_nr_pages = MAX_CP_PAGES; | |
3488 | bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; | |
3489 | netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", | |
3490 | ring_size, bp->cp_ring_size); | |
3491 | } | |
3492 | bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; | |
3493 | bp->cp_ring_mask = bp->cp_bit - 1; | |
3494 | } | |
3495 | ||
96a8604f JDB |
3496 | /* Changing allocation mode of RX rings. |
3497 | * TODO: Update when extending xdp_rxq_info to support allocation modes. | |
3498 | */ | |
c61fb99c | 3499 | int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode) |
6bb19474 | 3500 | { |
c61fb99c MC |
3501 | if (page_mode) { |
3502 | if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU) | |
3503 | return -EOPNOTSUPP; | |
7eb9bb3a MC |
3504 | bp->dev->max_mtu = |
3505 | min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU); | |
c61fb99c MC |
3506 | bp->flags &= ~BNXT_FLAG_AGG_RINGS; |
3507 | bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE; | |
c61fb99c MC |
3508 | bp->rx_dir = DMA_BIDIRECTIONAL; |
3509 | bp->rx_skb_func = bnxt_rx_page_skb; | |
1054aee8 MC |
3510 | /* Disable LRO or GRO_HW */ |
3511 | netdev_update_features(bp->dev); | |
c61fb99c | 3512 | } else { |
7eb9bb3a | 3513 | bp->dev->max_mtu = bp->max_mtu; |
c61fb99c MC |
3514 | bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE; |
3515 | bp->rx_dir = DMA_FROM_DEVICE; | |
3516 | bp->rx_skb_func = bnxt_rx_skb; | |
3517 | } | |
6bb19474 MC |
3518 | return 0; |
3519 | } | |
3520 | ||
c0c050c5 MC |
3521 | static void bnxt_free_vnic_attributes(struct bnxt *bp) |
3522 | { | |
3523 | int i; | |
3524 | struct bnxt_vnic_info *vnic; | |
3525 | struct pci_dev *pdev = bp->pdev; | |
3526 | ||
3527 | if (!bp->vnic_info) | |
3528 | return; | |
3529 | ||
3530 | for (i = 0; i < bp->nr_vnics; i++) { | |
3531 | vnic = &bp->vnic_info[i]; | |
3532 | ||
3533 | kfree(vnic->fw_grp_ids); | |
3534 | vnic->fw_grp_ids = NULL; | |
3535 | ||
3536 | kfree(vnic->uc_list); | |
3537 | vnic->uc_list = NULL; | |
3538 | ||
3539 | if (vnic->mc_list) { | |
3540 | dma_free_coherent(&pdev->dev, vnic->mc_list_size, | |
3541 | vnic->mc_list, vnic->mc_list_mapping); | |
3542 | vnic->mc_list = NULL; | |
3543 | } | |
3544 | ||
3545 | if (vnic->rss_table) { | |
3546 | dma_free_coherent(&pdev->dev, PAGE_SIZE, | |
3547 | vnic->rss_table, | |
3548 | vnic->rss_table_dma_addr); | |
3549 | vnic->rss_table = NULL; | |
3550 | } | |
3551 | ||
3552 | vnic->rss_hash_key = NULL; | |
3553 | vnic->flags = 0; | |
3554 | } | |
3555 | } | |
3556 | ||
3557 | static int bnxt_alloc_vnic_attributes(struct bnxt *bp) | |
3558 | { | |
3559 | int i, rc = 0, size; | |
3560 | struct bnxt_vnic_info *vnic; | |
3561 | struct pci_dev *pdev = bp->pdev; | |
3562 | int max_rings; | |
3563 | ||
3564 | for (i = 0; i < bp->nr_vnics; i++) { | |
3565 | vnic = &bp->vnic_info[i]; | |
3566 | ||
3567 | if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { | |
3568 | int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; | |
3569 | ||
3570 | if (mem_size > 0) { | |
3571 | vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); | |
3572 | if (!vnic->uc_list) { | |
3573 | rc = -ENOMEM; | |
3574 | goto out; | |
3575 | } | |
3576 | } | |
3577 | } | |
3578 | ||
3579 | if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { | |
3580 | vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; | |
3581 | vnic->mc_list = | |
3582 | dma_alloc_coherent(&pdev->dev, | |
3583 | vnic->mc_list_size, | |
3584 | &vnic->mc_list_mapping, | |
3585 | GFP_KERNEL); | |
3586 | if (!vnic->mc_list) { | |
3587 | rc = -ENOMEM; | |
3588 | goto out; | |
3589 | } | |
3590 | } | |
3591 | ||
44c6f72a MC |
3592 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
3593 | goto vnic_skip_grps; | |
3594 | ||
c0c050c5 MC |
3595 | if (vnic->flags & BNXT_VNIC_RSS_FLAG) |
3596 | max_rings = bp->rx_nr_rings; | |
3597 | else | |
3598 | max_rings = 1; | |
3599 | ||
3600 | vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); | |
3601 | if (!vnic->fw_grp_ids) { | |
3602 | rc = -ENOMEM; | |
3603 | goto out; | |
3604 | } | |
44c6f72a | 3605 | vnic_skip_grps: |
ae10ae74 MC |
3606 | if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) && |
3607 | !(vnic->flags & BNXT_VNIC_RSS_FLAG)) | |
3608 | continue; | |
3609 | ||
c0c050c5 MC |
3610 | /* Allocate rss table and hash key */ |
3611 | vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, | |
3612 | &vnic->rss_table_dma_addr, | |
3613 | GFP_KERNEL); | |
3614 | if (!vnic->rss_table) { | |
3615 | rc = -ENOMEM; | |
3616 | goto out; | |
3617 | } | |
3618 | ||
3619 | size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); | |
3620 | ||
3621 | vnic->rss_hash_key = ((void *)vnic->rss_table) + size; | |
3622 | vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; | |
3623 | } | |
3624 | return 0; | |
3625 | ||
3626 | out: | |
3627 | return rc; | |
3628 | } | |
3629 | ||
3630 | static void bnxt_free_hwrm_resources(struct bnxt *bp) | |
3631 | { | |
3632 | struct pci_dev *pdev = bp->pdev; | |
3633 | ||
a2bf74f4 VD |
3634 | if (bp->hwrm_cmd_resp_addr) { |
3635 | dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr, | |
3636 | bp->hwrm_cmd_resp_dma_addr); | |
3637 | bp->hwrm_cmd_resp_addr = NULL; | |
3638 | } | |
760b6d33 VD |
3639 | |
3640 | if (bp->hwrm_cmd_kong_resp_addr) { | |
3641 | dma_free_coherent(&pdev->dev, PAGE_SIZE, | |
3642 | bp->hwrm_cmd_kong_resp_addr, | |
3643 | bp->hwrm_cmd_kong_resp_dma_addr); | |
3644 | bp->hwrm_cmd_kong_resp_addr = NULL; | |
3645 | } | |
3646 | } | |
3647 | ||
3648 | static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp) | |
3649 | { | |
3650 | struct pci_dev *pdev = bp->pdev; | |
3651 | ||
ba642ab7 MC |
3652 | if (bp->hwrm_cmd_kong_resp_addr) |
3653 | return 0; | |
3654 | ||
760b6d33 VD |
3655 | bp->hwrm_cmd_kong_resp_addr = |
3656 | dma_alloc_coherent(&pdev->dev, PAGE_SIZE, | |
3657 | &bp->hwrm_cmd_kong_resp_dma_addr, | |
3658 | GFP_KERNEL); | |
3659 | if (!bp->hwrm_cmd_kong_resp_addr) | |
3660 | return -ENOMEM; | |
3661 | ||
3662 | return 0; | |
c0c050c5 MC |
3663 | } |
3664 | ||
3665 | static int bnxt_alloc_hwrm_resources(struct bnxt *bp) | |
3666 | { | |
3667 | struct pci_dev *pdev = bp->pdev; | |
3668 | ||
3669 | bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, | |
3670 | &bp->hwrm_cmd_resp_dma_addr, | |
3671 | GFP_KERNEL); | |
3672 | if (!bp->hwrm_cmd_resp_addr) | |
3673 | return -ENOMEM; | |
c0c050c5 MC |
3674 | |
3675 | return 0; | |
3676 | } | |
3677 | ||
e605db80 DK |
3678 | static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp) |
3679 | { | |
3680 | if (bp->hwrm_short_cmd_req_addr) { | |
3681 | struct pci_dev *pdev = bp->pdev; | |
3682 | ||
1dfddc41 | 3683 | dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, |
e605db80 DK |
3684 | bp->hwrm_short_cmd_req_addr, |
3685 | bp->hwrm_short_cmd_req_dma_addr); | |
3686 | bp->hwrm_short_cmd_req_addr = NULL; | |
3687 | } | |
3688 | } | |
3689 | ||
3690 | static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp) | |
3691 | { | |
3692 | struct pci_dev *pdev = bp->pdev; | |
3693 | ||
ba642ab7 MC |
3694 | if (bp->hwrm_short_cmd_req_addr) |
3695 | return 0; | |
3696 | ||
e605db80 | 3697 | bp->hwrm_short_cmd_req_addr = |
1dfddc41 | 3698 | dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, |
e605db80 DK |
3699 | &bp->hwrm_short_cmd_req_dma_addr, |
3700 | GFP_KERNEL); | |
3701 | if (!bp->hwrm_short_cmd_req_addr) | |
3702 | return -ENOMEM; | |
3703 | ||
3704 | return 0; | |
3705 | } | |
3706 | ||
fd3ab1c7 | 3707 | static void bnxt_free_port_stats(struct bnxt *bp) |
c0c050c5 | 3708 | { |
c0c050c5 MC |
3709 | struct pci_dev *pdev = bp->pdev; |
3710 | ||
00db3cba VV |
3711 | bp->flags &= ~BNXT_FLAG_PORT_STATS; |
3712 | bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT; | |
3713 | ||
3bdf56c4 MC |
3714 | if (bp->hw_rx_port_stats) { |
3715 | dma_free_coherent(&pdev->dev, bp->hw_port_stats_size, | |
3716 | bp->hw_rx_port_stats, | |
3717 | bp->hw_rx_port_stats_map); | |
3718 | bp->hw_rx_port_stats = NULL; | |
00db3cba VV |
3719 | } |
3720 | ||
36e53349 MC |
3721 | if (bp->hw_tx_port_stats_ext) { |
3722 | dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext), | |
3723 | bp->hw_tx_port_stats_ext, | |
3724 | bp->hw_tx_port_stats_ext_map); | |
3725 | bp->hw_tx_port_stats_ext = NULL; | |
3726 | } | |
3727 | ||
00db3cba VV |
3728 | if (bp->hw_rx_port_stats_ext) { |
3729 | dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), | |
3730 | bp->hw_rx_port_stats_ext, | |
3731 | bp->hw_rx_port_stats_ext_map); | |
3732 | bp->hw_rx_port_stats_ext = NULL; | |
3bdf56c4 | 3733 | } |
55e4398d VV |
3734 | |
3735 | if (bp->hw_pcie_stats) { | |
3736 | dma_free_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), | |
3737 | bp->hw_pcie_stats, bp->hw_pcie_stats_map); | |
3738 | bp->hw_pcie_stats = NULL; | |
3739 | } | |
fd3ab1c7 MC |
3740 | } |
3741 | ||
3742 | static void bnxt_free_ring_stats(struct bnxt *bp) | |
3743 | { | |
3744 | struct pci_dev *pdev = bp->pdev; | |
3745 | int size, i; | |
3bdf56c4 | 3746 | |
c0c050c5 MC |
3747 | if (!bp->bnapi) |
3748 | return; | |
3749 | ||
4e748506 | 3750 | size = bp->hw_ring_stats_size; |
c0c050c5 MC |
3751 | |
3752 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3753 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
3754 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
3755 | ||
3756 | if (cpr->hw_stats) { | |
3757 | dma_free_coherent(&pdev->dev, size, cpr->hw_stats, | |
3758 | cpr->hw_stats_map); | |
3759 | cpr->hw_stats = NULL; | |
3760 | } | |
3761 | } | |
3762 | } | |
3763 | ||
3764 | static int bnxt_alloc_stats(struct bnxt *bp) | |
3765 | { | |
3766 | u32 size, i; | |
3767 | struct pci_dev *pdev = bp->pdev; | |
3768 | ||
4e748506 | 3769 | size = bp->hw_ring_stats_size; |
c0c050c5 MC |
3770 | |
3771 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3772 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
3773 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
3774 | ||
3775 | cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size, | |
3776 | &cpr->hw_stats_map, | |
3777 | GFP_KERNEL); | |
3778 | if (!cpr->hw_stats) | |
3779 | return -ENOMEM; | |
3780 | ||
3781 | cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; | |
3782 | } | |
3bdf56c4 | 3783 | |
a220eabc VV |
3784 | if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700) |
3785 | return 0; | |
fd3ab1c7 | 3786 | |
a220eabc VV |
3787 | if (bp->hw_rx_port_stats) |
3788 | goto alloc_ext_stats; | |
3bdf56c4 | 3789 | |
a220eabc VV |
3790 | bp->hw_port_stats_size = sizeof(struct rx_port_stats) + |
3791 | sizeof(struct tx_port_stats) + 1024; | |
3bdf56c4 | 3792 | |
a220eabc VV |
3793 | bp->hw_rx_port_stats = |
3794 | dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size, | |
3795 | &bp->hw_rx_port_stats_map, | |
3796 | GFP_KERNEL); | |
3797 | if (!bp->hw_rx_port_stats) | |
3798 | return -ENOMEM; | |
3bdf56c4 | 3799 | |
a220eabc VV |
3800 | bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 512; |
3801 | bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map + | |
3802 | sizeof(struct rx_port_stats) + 512; | |
3803 | bp->flags |= BNXT_FLAG_PORT_STATS; | |
00db3cba | 3804 | |
fd3ab1c7 | 3805 | alloc_ext_stats: |
a220eabc VV |
3806 | /* Display extended statistics only if FW supports it */ |
3807 | if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900) | |
6154532f | 3808 | if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) |
00db3cba VV |
3809 | return 0; |
3810 | ||
a220eabc VV |
3811 | if (bp->hw_rx_port_stats_ext) |
3812 | goto alloc_tx_ext_stats; | |
fd3ab1c7 | 3813 | |
a220eabc VV |
3814 | bp->hw_rx_port_stats_ext = |
3815 | dma_alloc_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), | |
3816 | &bp->hw_rx_port_stats_ext_map, GFP_KERNEL); | |
3817 | if (!bp->hw_rx_port_stats_ext) | |
3818 | return 0; | |
00db3cba | 3819 | |
fd3ab1c7 | 3820 | alloc_tx_ext_stats: |
a220eabc | 3821 | if (bp->hw_tx_port_stats_ext) |
55e4398d | 3822 | goto alloc_pcie_stats; |
fd3ab1c7 | 3823 | |
6154532f VV |
3824 | if (bp->hwrm_spec_code >= 0x10902 || |
3825 | (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) { | |
a220eabc VV |
3826 | bp->hw_tx_port_stats_ext = |
3827 | dma_alloc_coherent(&pdev->dev, | |
3828 | sizeof(struct tx_port_stats_ext), | |
3829 | &bp->hw_tx_port_stats_ext_map, | |
3830 | GFP_KERNEL); | |
3bdf56c4 | 3831 | } |
a220eabc | 3832 | bp->flags |= BNXT_FLAG_PORT_STATS_EXT; |
55e4398d VV |
3833 | |
3834 | alloc_pcie_stats: | |
3835 | if (bp->hw_pcie_stats || | |
3836 | !(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) | |
3837 | return 0; | |
3838 | ||
3839 | bp->hw_pcie_stats = | |
3840 | dma_alloc_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), | |
3841 | &bp->hw_pcie_stats_map, GFP_KERNEL); | |
3842 | if (!bp->hw_pcie_stats) | |
3843 | return 0; | |
3844 | ||
3845 | bp->flags |= BNXT_FLAG_PCIE_STATS; | |
c0c050c5 MC |
3846 | return 0; |
3847 | } | |
3848 | ||
3849 | static void bnxt_clear_ring_indices(struct bnxt *bp) | |
3850 | { | |
3851 | int i; | |
3852 | ||
3853 | if (!bp->bnapi) | |
3854 | return; | |
3855 | ||
3856 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3857 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
3858 | struct bnxt_cp_ring_info *cpr; | |
3859 | struct bnxt_rx_ring_info *rxr; | |
3860 | struct bnxt_tx_ring_info *txr; | |
3861 | ||
3862 | if (!bnapi) | |
3863 | continue; | |
3864 | ||
3865 | cpr = &bnapi->cp_ring; | |
3866 | cpr->cp_raw_cons = 0; | |
3867 | ||
b6ab4b01 | 3868 | txr = bnapi->tx_ring; |
3b2b7d9d MC |
3869 | if (txr) { |
3870 | txr->tx_prod = 0; | |
3871 | txr->tx_cons = 0; | |
3872 | } | |
c0c050c5 | 3873 | |
b6ab4b01 | 3874 | rxr = bnapi->rx_ring; |
3b2b7d9d MC |
3875 | if (rxr) { |
3876 | rxr->rx_prod = 0; | |
3877 | rxr->rx_agg_prod = 0; | |
3878 | rxr->rx_sw_agg_prod = 0; | |
376a5b86 | 3879 | rxr->rx_next_cons = 0; |
3b2b7d9d | 3880 | } |
c0c050c5 MC |
3881 | } |
3882 | } | |
3883 | ||
3884 | static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) | |
3885 | { | |
3886 | #ifdef CONFIG_RFS_ACCEL | |
3887 | int i; | |
3888 | ||
3889 | /* Under rtnl_lock and all our NAPIs have been disabled. It's | |
3890 | * safe to delete the hash table. | |
3891 | */ | |
3892 | for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { | |
3893 | struct hlist_head *head; | |
3894 | struct hlist_node *tmp; | |
3895 | struct bnxt_ntuple_filter *fltr; | |
3896 | ||
3897 | head = &bp->ntp_fltr_hash_tbl[i]; | |
3898 | hlist_for_each_entry_safe(fltr, tmp, head, hash) { | |
3899 | hlist_del(&fltr->hash); | |
3900 | kfree(fltr); | |
3901 | } | |
3902 | } | |
3903 | if (irq_reinit) { | |
3904 | kfree(bp->ntp_fltr_bmap); | |
3905 | bp->ntp_fltr_bmap = NULL; | |
3906 | } | |
3907 | bp->ntp_fltr_count = 0; | |
3908 | #endif | |
3909 | } | |
3910 | ||
3911 | static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) | |
3912 | { | |
3913 | #ifdef CONFIG_RFS_ACCEL | |
3914 | int i, rc = 0; | |
3915 | ||
3916 | if (!(bp->flags & BNXT_FLAG_RFS)) | |
3917 | return 0; | |
3918 | ||
3919 | for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) | |
3920 | INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); | |
3921 | ||
3922 | bp->ntp_fltr_count = 0; | |
ac45bd93 DC |
3923 | bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR), |
3924 | sizeof(long), | |
c0c050c5 MC |
3925 | GFP_KERNEL); |
3926 | ||
3927 | if (!bp->ntp_fltr_bmap) | |
3928 | rc = -ENOMEM; | |
3929 | ||
3930 | return rc; | |
3931 | #else | |
3932 | return 0; | |
3933 | #endif | |
3934 | } | |
3935 | ||
3936 | static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) | |
3937 | { | |
3938 | bnxt_free_vnic_attributes(bp); | |
3939 | bnxt_free_tx_rings(bp); | |
3940 | bnxt_free_rx_rings(bp); | |
3941 | bnxt_free_cp_rings(bp); | |
3942 | bnxt_free_ntp_fltrs(bp, irq_re_init); | |
3943 | if (irq_re_init) { | |
fd3ab1c7 | 3944 | bnxt_free_ring_stats(bp); |
c0c050c5 MC |
3945 | bnxt_free_ring_grps(bp); |
3946 | bnxt_free_vnics(bp); | |
a960dec9 MC |
3947 | kfree(bp->tx_ring_map); |
3948 | bp->tx_ring_map = NULL; | |
b6ab4b01 MC |
3949 | kfree(bp->tx_ring); |
3950 | bp->tx_ring = NULL; | |
3951 | kfree(bp->rx_ring); | |
3952 | bp->rx_ring = NULL; | |
c0c050c5 MC |
3953 | kfree(bp->bnapi); |
3954 | bp->bnapi = NULL; | |
3955 | } else { | |
3956 | bnxt_clear_ring_indices(bp); | |
3957 | } | |
3958 | } | |
3959 | ||
3960 | static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) | |
3961 | { | |
01657bcd | 3962 | int i, j, rc, size, arr_size; |
c0c050c5 MC |
3963 | void *bnapi; |
3964 | ||
3965 | if (irq_re_init) { | |
3966 | /* Allocate bnapi mem pointer array and mem block for | |
3967 | * all queues | |
3968 | */ | |
3969 | arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * | |
3970 | bp->cp_nr_rings); | |
3971 | size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); | |
3972 | bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); | |
3973 | if (!bnapi) | |
3974 | return -ENOMEM; | |
3975 | ||
3976 | bp->bnapi = bnapi; | |
3977 | bnapi += arr_size; | |
3978 | for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { | |
3979 | bp->bnapi[i] = bnapi; | |
3980 | bp->bnapi[i]->index = i; | |
3981 | bp->bnapi[i]->bp = bp; | |
e38287b7 MC |
3982 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
3983 | struct bnxt_cp_ring_info *cpr = | |
3984 | &bp->bnapi[i]->cp_ring; | |
3985 | ||
3986 | cpr->cp_ring_struct.ring_mem.flags = | |
3987 | BNXT_RMEM_RING_PTE_FLAG; | |
3988 | } | |
c0c050c5 MC |
3989 | } |
3990 | ||
b6ab4b01 MC |
3991 | bp->rx_ring = kcalloc(bp->rx_nr_rings, |
3992 | sizeof(struct bnxt_rx_ring_info), | |
3993 | GFP_KERNEL); | |
3994 | if (!bp->rx_ring) | |
3995 | return -ENOMEM; | |
3996 | ||
3997 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
e38287b7 MC |
3998 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
3999 | ||
4000 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
4001 | rxr->rx_ring_struct.ring_mem.flags = | |
4002 | BNXT_RMEM_RING_PTE_FLAG; | |
4003 | rxr->rx_agg_ring_struct.ring_mem.flags = | |
4004 | BNXT_RMEM_RING_PTE_FLAG; | |
4005 | } | |
4006 | rxr->bnapi = bp->bnapi[i]; | |
b6ab4b01 MC |
4007 | bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; |
4008 | } | |
4009 | ||
4010 | bp->tx_ring = kcalloc(bp->tx_nr_rings, | |
4011 | sizeof(struct bnxt_tx_ring_info), | |
4012 | GFP_KERNEL); | |
4013 | if (!bp->tx_ring) | |
4014 | return -ENOMEM; | |
4015 | ||
a960dec9 MC |
4016 | bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16), |
4017 | GFP_KERNEL); | |
4018 | ||
4019 | if (!bp->tx_ring_map) | |
4020 | return -ENOMEM; | |
4021 | ||
01657bcd MC |
4022 | if (bp->flags & BNXT_FLAG_SHARED_RINGS) |
4023 | j = 0; | |
4024 | else | |
4025 | j = bp->rx_nr_rings; | |
4026 | ||
4027 | for (i = 0; i < bp->tx_nr_rings; i++, j++) { | |
e38287b7 MC |
4028 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
4029 | ||
4030 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
4031 | txr->tx_ring_struct.ring_mem.flags = | |
4032 | BNXT_RMEM_RING_PTE_FLAG; | |
4033 | txr->bnapi = bp->bnapi[j]; | |
4034 | bp->bnapi[j]->tx_ring = txr; | |
5f449249 | 4035 | bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i; |
38413406 | 4036 | if (i >= bp->tx_nr_rings_xdp) { |
e38287b7 | 4037 | txr->txq_index = i - bp->tx_nr_rings_xdp; |
38413406 MC |
4038 | bp->bnapi[j]->tx_int = bnxt_tx_int; |
4039 | } else { | |
fa3e93e8 | 4040 | bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP; |
38413406 MC |
4041 | bp->bnapi[j]->tx_int = bnxt_tx_int_xdp; |
4042 | } | |
b6ab4b01 MC |
4043 | } |
4044 | ||
c0c050c5 MC |
4045 | rc = bnxt_alloc_stats(bp); |
4046 | if (rc) | |
4047 | goto alloc_mem_err; | |
4048 | ||
4049 | rc = bnxt_alloc_ntp_fltrs(bp); | |
4050 | if (rc) | |
4051 | goto alloc_mem_err; | |
4052 | ||
4053 | rc = bnxt_alloc_vnics(bp); | |
4054 | if (rc) | |
4055 | goto alloc_mem_err; | |
4056 | } | |
4057 | ||
4058 | bnxt_init_ring_struct(bp); | |
4059 | ||
4060 | rc = bnxt_alloc_rx_rings(bp); | |
4061 | if (rc) | |
4062 | goto alloc_mem_err; | |
4063 | ||
4064 | rc = bnxt_alloc_tx_rings(bp); | |
4065 | if (rc) | |
4066 | goto alloc_mem_err; | |
4067 | ||
4068 | rc = bnxt_alloc_cp_rings(bp); | |
4069 | if (rc) | |
4070 | goto alloc_mem_err; | |
4071 | ||
4072 | bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | | |
4073 | BNXT_VNIC_UCAST_FLAG; | |
4074 | rc = bnxt_alloc_vnic_attributes(bp); | |
4075 | if (rc) | |
4076 | goto alloc_mem_err; | |
4077 | return 0; | |
4078 | ||
4079 | alloc_mem_err: | |
4080 | bnxt_free_mem(bp, true); | |
4081 | return rc; | |
4082 | } | |
4083 | ||
9d8bc097 MC |
4084 | static void bnxt_disable_int(struct bnxt *bp) |
4085 | { | |
4086 | int i; | |
4087 | ||
4088 | if (!bp->bnapi) | |
4089 | return; | |
4090 | ||
4091 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
4092 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
4093 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
daf1f1e7 | 4094 | struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; |
9d8bc097 | 4095 | |
daf1f1e7 | 4096 | if (ring->fw_ring_id != INVALID_HW_RING_ID) |
697197e5 | 4097 | bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); |
9d8bc097 MC |
4098 | } |
4099 | } | |
4100 | ||
e5811b8c MC |
4101 | static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n) |
4102 | { | |
4103 | struct bnxt_napi *bnapi = bp->bnapi[n]; | |
4104 | struct bnxt_cp_ring_info *cpr; | |
4105 | ||
4106 | cpr = &bnapi->cp_ring; | |
4107 | return cpr->cp_ring_struct.map_idx; | |
4108 | } | |
4109 | ||
9d8bc097 MC |
4110 | static void bnxt_disable_int_sync(struct bnxt *bp) |
4111 | { | |
4112 | int i; | |
4113 | ||
4114 | atomic_inc(&bp->intr_sem); | |
4115 | ||
4116 | bnxt_disable_int(bp); | |
e5811b8c MC |
4117 | for (i = 0; i < bp->cp_nr_rings; i++) { |
4118 | int map_idx = bnxt_cp_num_to_irq_num(bp, i); | |
4119 | ||
4120 | synchronize_irq(bp->irq_tbl[map_idx].vector); | |
4121 | } | |
9d8bc097 MC |
4122 | } |
4123 | ||
4124 | static void bnxt_enable_int(struct bnxt *bp) | |
4125 | { | |
4126 | int i; | |
4127 | ||
4128 | atomic_set(&bp->intr_sem, 0); | |
4129 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
4130 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
4131 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
4132 | ||
697197e5 | 4133 | bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons); |
9d8bc097 MC |
4134 | } |
4135 | } | |
4136 | ||
c0c050c5 MC |
4137 | void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type, |
4138 | u16 cmpl_ring, u16 target_id) | |
4139 | { | |
a8643e16 | 4140 | struct input *req = request; |
c0c050c5 | 4141 | |
a8643e16 MC |
4142 | req->req_type = cpu_to_le16(req_type); |
4143 | req->cmpl_ring = cpu_to_le16(cmpl_ring); | |
4144 | req->target_id = cpu_to_le16(target_id); | |
760b6d33 VD |
4145 | if (bnxt_kong_hwrm_message(bp, req)) |
4146 | req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); | |
4147 | else | |
4148 | req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr); | |
c0c050c5 MC |
4149 | } |
4150 | ||
d4f1420d MC |
4151 | static int bnxt_hwrm_to_stderr(u32 hwrm_err) |
4152 | { | |
4153 | switch (hwrm_err) { | |
4154 | case HWRM_ERR_CODE_SUCCESS: | |
4155 | return 0; | |
4156 | case HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED: | |
4157 | return -EACCES; | |
4158 | case HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR: | |
4159 | return -ENOSPC; | |
4160 | case HWRM_ERR_CODE_INVALID_PARAMS: | |
4161 | case HWRM_ERR_CODE_INVALID_FLAGS: | |
4162 | case HWRM_ERR_CODE_INVALID_ENABLES: | |
4163 | case HWRM_ERR_CODE_UNSUPPORTED_TLV: | |
4164 | case HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR: | |
4165 | return -EINVAL; | |
4166 | case HWRM_ERR_CODE_NO_BUFFER: | |
4167 | return -ENOMEM; | |
4168 | case HWRM_ERR_CODE_HOT_RESET_PROGRESS: | |
4169 | return -EAGAIN; | |
4170 | case HWRM_ERR_CODE_CMD_NOT_SUPPORTED: | |
4171 | return -EOPNOTSUPP; | |
4172 | default: | |
4173 | return -EIO; | |
4174 | } | |
4175 | } | |
4176 | ||
fbfbc485 MC |
4177 | static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len, |
4178 | int timeout, bool silent) | |
c0c050c5 | 4179 | { |
a11fa2be | 4180 | int i, intr_process, rc, tmo_count; |
a8643e16 | 4181 | struct input *req = msg; |
c0c050c5 | 4182 | u32 *data = msg; |
845adfe4 MC |
4183 | __le32 *resp_len; |
4184 | u8 *valid; | |
c0c050c5 MC |
4185 | u16 cp_ring_id, len = 0; |
4186 | struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr; | |
e605db80 | 4187 | u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN; |
ebd5818c | 4188 | struct hwrm_short_input short_input = {0}; |
2e9ee398 | 4189 | u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER; |
89455017 | 4190 | u8 *resp_addr = (u8 *)bp->hwrm_cmd_resp_addr; |
2e9ee398 | 4191 | u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM; |
760b6d33 | 4192 | u16 dst = BNXT_HWRM_CHNL_CHIMP; |
c0c050c5 | 4193 | |
b4fff207 MC |
4194 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) |
4195 | return -EBUSY; | |
4196 | ||
1dfddc41 MC |
4197 | if (msg_len > BNXT_HWRM_MAX_REQ_LEN) { |
4198 | if (msg_len > bp->hwrm_max_ext_req_len || | |
4199 | !bp->hwrm_short_cmd_req_addr) | |
4200 | return -EINVAL; | |
4201 | } | |
4202 | ||
760b6d33 VD |
4203 | if (bnxt_hwrm_kong_chnl(bp, req)) { |
4204 | dst = BNXT_HWRM_CHNL_KONG; | |
4205 | bar_offset = BNXT_GRCPF_REG_KONG_COMM; | |
4206 | doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER; | |
4207 | resp = bp->hwrm_cmd_kong_resp_addr; | |
4208 | resp_addr = (u8 *)bp->hwrm_cmd_kong_resp_addr; | |
4209 | } | |
4210 | ||
4211 | memset(resp, 0, PAGE_SIZE); | |
4212 | cp_ring_id = le16_to_cpu(req->cmpl_ring); | |
4213 | intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1; | |
4214 | ||
4215 | req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst)); | |
4216 | /* currently supports only one outstanding message */ | |
4217 | if (intr_process) | |
4218 | bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id); | |
4219 | ||
1dfddc41 MC |
4220 | if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || |
4221 | msg_len > BNXT_HWRM_MAX_REQ_LEN) { | |
e605db80 | 4222 | void *short_cmd_req = bp->hwrm_short_cmd_req_addr; |
1dfddc41 MC |
4223 | u16 max_msg_len; |
4224 | ||
4225 | /* Set boundary for maximum extended request length for short | |
4226 | * cmd format. If passed up from device use the max supported | |
4227 | * internal req length. | |
4228 | */ | |
4229 | max_msg_len = bp->hwrm_max_ext_req_len; | |
e605db80 DK |
4230 | |
4231 | memcpy(short_cmd_req, req, msg_len); | |
1dfddc41 MC |
4232 | if (msg_len < max_msg_len) |
4233 | memset(short_cmd_req + msg_len, 0, | |
4234 | max_msg_len - msg_len); | |
e605db80 DK |
4235 | |
4236 | short_input.req_type = req->req_type; | |
4237 | short_input.signature = | |
4238 | cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD); | |
4239 | short_input.size = cpu_to_le16(msg_len); | |
4240 | short_input.req_addr = | |
4241 | cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr); | |
4242 | ||
4243 | data = (u32 *)&short_input; | |
4244 | msg_len = sizeof(short_input); | |
4245 | ||
4246 | /* Sync memory write before updating doorbell */ | |
4247 | wmb(); | |
4248 | ||
4249 | max_req_len = BNXT_HWRM_SHORT_REQ_LEN; | |
4250 | } | |
4251 | ||
c0c050c5 | 4252 | /* Write request msg to hwrm channel */ |
2e9ee398 | 4253 | __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4); |
c0c050c5 | 4254 | |
e605db80 | 4255 | for (i = msg_len; i < max_req_len; i += 4) |
2e9ee398 | 4256 | writel(0, bp->bar0 + bar_offset + i); |
d79979a1 | 4257 | |
c0c050c5 | 4258 | /* Ring channel doorbell */ |
2e9ee398 | 4259 | writel(1, bp->bar0 + doorbell_offset); |
c0c050c5 | 4260 | |
5bedb529 MC |
4261 | if (!pci_is_enabled(bp->pdev)) |
4262 | return 0; | |
4263 | ||
ff4fe81d MC |
4264 | if (!timeout) |
4265 | timeout = DFLT_HWRM_CMD_TIMEOUT; | |
9751e8e7 AG |
4266 | /* convert timeout to usec */ |
4267 | timeout *= 1000; | |
ff4fe81d | 4268 | |
c0c050c5 | 4269 | i = 0; |
9751e8e7 AG |
4270 | /* Short timeout for the first few iterations: |
4271 | * number of loops = number of loops for short timeout + | |
4272 | * number of loops for standard timeout. | |
4273 | */ | |
4274 | tmo_count = HWRM_SHORT_TIMEOUT_COUNTER; | |
4275 | timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER; | |
4276 | tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT); | |
89455017 VD |
4277 | resp_len = (__le32 *)(resp_addr + HWRM_RESP_LEN_OFFSET); |
4278 | ||
c0c050c5 | 4279 | if (intr_process) { |
fc718bb2 VD |
4280 | u16 seq_id = bp->hwrm_intr_seq_id; |
4281 | ||
c0c050c5 | 4282 | /* Wait until hwrm response cmpl interrupt is processed */ |
fc718bb2 | 4283 | while (bp->hwrm_intr_seq_id != (u16)~seq_id && |
a11fa2be | 4284 | i++ < tmo_count) { |
642aebde PC |
4285 | /* Abort the wait for completion if the FW health |
4286 | * check has failed. | |
4287 | */ | |
4288 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) | |
4289 | return -EBUSY; | |
9751e8e7 AG |
4290 | /* on first few passes, just barely sleep */ |
4291 | if (i < HWRM_SHORT_TIMEOUT_COUNTER) | |
4292 | usleep_range(HWRM_SHORT_MIN_TIMEOUT, | |
4293 | HWRM_SHORT_MAX_TIMEOUT); | |
4294 | else | |
4295 | usleep_range(HWRM_MIN_TIMEOUT, | |
4296 | HWRM_MAX_TIMEOUT); | |
c0c050c5 MC |
4297 | } |
4298 | ||
fc718bb2 | 4299 | if (bp->hwrm_intr_seq_id != (u16)~seq_id) { |
5bedb529 MC |
4300 | if (!silent) |
4301 | netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n", | |
4302 | le16_to_cpu(req->req_type)); | |
a935cb7e | 4303 | return -EBUSY; |
c0c050c5 | 4304 | } |
845adfe4 MC |
4305 | len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> |
4306 | HWRM_RESP_LEN_SFT; | |
89455017 | 4307 | valid = resp_addr + len - 1; |
c0c050c5 | 4308 | } else { |
cc559c1a MC |
4309 | int j; |
4310 | ||
c0c050c5 | 4311 | /* Check if response len is updated */ |
a11fa2be | 4312 | for (i = 0; i < tmo_count; i++) { |
642aebde PC |
4313 | /* Abort the wait for completion if the FW health |
4314 | * check has failed. | |
4315 | */ | |
4316 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) | |
4317 | return -EBUSY; | |
c0c050c5 MC |
4318 | len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> |
4319 | HWRM_RESP_LEN_SFT; | |
4320 | if (len) | |
4321 | break; | |
9751e8e7 | 4322 | /* on first few passes, just barely sleep */ |
67681d02 | 4323 | if (i < HWRM_SHORT_TIMEOUT_COUNTER) |
9751e8e7 AG |
4324 | usleep_range(HWRM_SHORT_MIN_TIMEOUT, |
4325 | HWRM_SHORT_MAX_TIMEOUT); | |
4326 | else | |
4327 | usleep_range(HWRM_MIN_TIMEOUT, | |
4328 | HWRM_MAX_TIMEOUT); | |
c0c050c5 MC |
4329 | } |
4330 | ||
a11fa2be | 4331 | if (i >= tmo_count) { |
5bedb529 MC |
4332 | if (!silent) |
4333 | netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n", | |
4334 | HWRM_TOTAL_TIMEOUT(i), | |
4335 | le16_to_cpu(req->req_type), | |
4336 | le16_to_cpu(req->seq_id), len); | |
a935cb7e | 4337 | return -EBUSY; |
c0c050c5 MC |
4338 | } |
4339 | ||
845adfe4 | 4340 | /* Last byte of resp contains valid bit */ |
89455017 | 4341 | valid = resp_addr + len - 1; |
cc559c1a | 4342 | for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) { |
845adfe4 MC |
4343 | /* make sure we read from updated DMA memory */ |
4344 | dma_rmb(); | |
4345 | if (*valid) | |
c0c050c5 | 4346 | break; |
0000b81a | 4347 | usleep_range(1, 5); |
c0c050c5 MC |
4348 | } |
4349 | ||
cc559c1a | 4350 | if (j >= HWRM_VALID_BIT_DELAY_USEC) { |
5bedb529 MC |
4351 | if (!silent) |
4352 | netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n", | |
4353 | HWRM_TOTAL_TIMEOUT(i), | |
4354 | le16_to_cpu(req->req_type), | |
4355 | le16_to_cpu(req->seq_id), len, | |
4356 | *valid); | |
a935cb7e | 4357 | return -EBUSY; |
c0c050c5 MC |
4358 | } |
4359 | } | |
4360 | ||
845adfe4 MC |
4361 | /* Zero valid bit for compatibility. Valid bit in an older spec |
4362 | * may become a new field in a newer spec. We must make sure that | |
4363 | * a new field not implemented by old spec will read zero. | |
4364 | */ | |
4365 | *valid = 0; | |
c0c050c5 | 4366 | rc = le16_to_cpu(resp->error_code); |
fbfbc485 | 4367 | if (rc && !silent) |
c0c050c5 MC |
4368 | netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n", |
4369 | le16_to_cpu(resp->req_type), | |
4370 | le16_to_cpu(resp->seq_id), rc); | |
d4f1420d | 4371 | return bnxt_hwrm_to_stderr(rc); |
fbfbc485 MC |
4372 | } |
4373 | ||
4374 | int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) | |
4375 | { | |
4376 | return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false); | |
c0c050c5 MC |
4377 | } |
4378 | ||
cc72f3b1 MC |
4379 | int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, |
4380 | int timeout) | |
4381 | { | |
4382 | return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); | |
4383 | } | |
4384 | ||
c0c050c5 MC |
4385 | int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) |
4386 | { | |
4387 | int rc; | |
4388 | ||
4389 | mutex_lock(&bp->hwrm_cmd_lock); | |
4390 | rc = _hwrm_send_message(bp, msg, msg_len, timeout); | |
4391 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4392 | return rc; | |
4393 | } | |
4394 | ||
90e20921 MC |
4395 | int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, |
4396 | int timeout) | |
4397 | { | |
4398 | int rc; | |
4399 | ||
4400 | mutex_lock(&bp->hwrm_cmd_lock); | |
4401 | rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); | |
4402 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4403 | return rc; | |
4404 | } | |
4405 | ||
2e882468 VV |
4406 | int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, int bmap_size, |
4407 | bool async_only) | |
c0c050c5 | 4408 | { |
2e882468 | 4409 | struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr; |
c0c050c5 | 4410 | struct hwrm_func_drv_rgtr_input req = {0}; |
25be8623 MC |
4411 | DECLARE_BITMAP(async_events_bmap, 256); |
4412 | u32 *events = (u32 *)async_events_bmap; | |
acfb50e4 | 4413 | u32 flags; |
2e882468 | 4414 | int rc, i; |
a1653b13 MC |
4415 | |
4416 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); | |
4417 | ||
4418 | req.enables = | |
4419 | cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | | |
2e882468 VV |
4420 | FUNC_DRV_RGTR_REQ_ENABLES_VER | |
4421 | FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); | |
a1653b13 | 4422 | |
11f15ed3 | 4423 | req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX); |
8280b38e VV |
4424 | flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE; |
4425 | if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) | |
4426 | flags |= FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT; | |
acfb50e4 | 4427 | if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) |
e633a329 VV |
4428 | flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT | |
4429 | FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT; | |
acfb50e4 | 4430 | req.flags = cpu_to_le32(flags); |
d4f52de0 MC |
4431 | req.ver_maj_8b = DRV_VER_MAJ; |
4432 | req.ver_min_8b = DRV_VER_MIN; | |
4433 | req.ver_upd_8b = DRV_VER_UPD; | |
4434 | req.ver_maj = cpu_to_le16(DRV_VER_MAJ); | |
4435 | req.ver_min = cpu_to_le16(DRV_VER_MIN); | |
4436 | req.ver_upd = cpu_to_le16(DRV_VER_UPD); | |
c0c050c5 MC |
4437 | |
4438 | if (BNXT_PF(bp)) { | |
9b0436c3 | 4439 | u32 data[8]; |
a1653b13 | 4440 | int i; |
c0c050c5 | 4441 | |
9b0436c3 MC |
4442 | memset(data, 0, sizeof(data)); |
4443 | for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) { | |
4444 | u16 cmd = bnxt_vf_req_snif[i]; | |
4445 | unsigned int bit, idx; | |
4446 | ||
4447 | idx = cmd / 32; | |
4448 | bit = cmd % 32; | |
4449 | data[idx] |= 1 << bit; | |
4450 | } | |
c0c050c5 | 4451 | |
de68f5de MC |
4452 | for (i = 0; i < 8; i++) |
4453 | req.vf_req_fwd[i] = cpu_to_le32(data[i]); | |
4454 | ||
c0c050c5 MC |
4455 | req.enables |= |
4456 | cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); | |
4457 | } | |
4458 | ||
abd43a13 VD |
4459 | if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE) |
4460 | req.flags |= cpu_to_le32( | |
4461 | FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE); | |
4462 | ||
2e882468 VV |
4463 | memset(async_events_bmap, 0, sizeof(async_events_bmap)); |
4464 | for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) { | |
4465 | u16 event_id = bnxt_async_events_arr[i]; | |
4466 | ||
4467 | if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY && | |
4468 | !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) | |
4469 | continue; | |
4470 | __set_bit(bnxt_async_events_arr[i], async_events_bmap); | |
4471 | } | |
4472 | if (bmap && bmap_size) { | |
4473 | for (i = 0; i < bmap_size; i++) { | |
4474 | if (test_bit(i, bmap)) | |
4475 | __set_bit(i, async_events_bmap); | |
4476 | } | |
4477 | } | |
4478 | for (i = 0; i < 8; i++) | |
4479 | req.async_event_fwd[i] |= cpu_to_le32(events[i]); | |
4480 | ||
4481 | if (async_only) | |
4482 | req.enables = | |
4483 | cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); | |
4484 | ||
25e1acd6 MC |
4485 | mutex_lock(&bp->hwrm_cmd_lock); |
4486 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
bdb38602 VV |
4487 | if (!rc) { |
4488 | set_bit(BNXT_STATE_DRV_REGISTERED, &bp->state); | |
4489 | if (resp->flags & | |
4490 | cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED)) | |
4491 | bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE; | |
4492 | } | |
25e1acd6 MC |
4493 | mutex_unlock(&bp->hwrm_cmd_lock); |
4494 | return rc; | |
c0c050c5 MC |
4495 | } |
4496 | ||
be58a0da JH |
4497 | static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) |
4498 | { | |
4499 | struct hwrm_func_drv_unrgtr_input req = {0}; | |
4500 | ||
bdb38602 VV |
4501 | if (!test_and_clear_bit(BNXT_STATE_DRV_REGISTERED, &bp->state)) |
4502 | return 0; | |
4503 | ||
be58a0da JH |
4504 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1); |
4505 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4506 | } | |
4507 | ||
c0c050c5 MC |
4508 | static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) |
4509 | { | |
4510 | u32 rc = 0; | |
4511 | struct hwrm_tunnel_dst_port_free_input req = {0}; | |
4512 | ||
4513 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1); | |
4514 | req.tunnel_type = tunnel_type; | |
4515 | ||
4516 | switch (tunnel_type) { | |
4517 | case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: | |
4518 | req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id; | |
4519 | break; | |
4520 | case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: | |
4521 | req.tunnel_dst_port_id = bp->nge_fw_dst_port_id; | |
4522 | break; | |
4523 | default: | |
4524 | break; | |
4525 | } | |
4526 | ||
4527 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4528 | if (rc) | |
4529 | netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", | |
4530 | rc); | |
4531 | return rc; | |
4532 | } | |
4533 | ||
4534 | static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, | |
4535 | u8 tunnel_type) | |
4536 | { | |
4537 | u32 rc = 0; | |
4538 | struct hwrm_tunnel_dst_port_alloc_input req = {0}; | |
4539 | struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
4540 | ||
4541 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1); | |
4542 | ||
4543 | req.tunnel_type = tunnel_type; | |
4544 | req.tunnel_dst_port_val = port; | |
4545 | ||
4546 | mutex_lock(&bp->hwrm_cmd_lock); | |
4547 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4548 | if (rc) { | |
4549 | netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", | |
4550 | rc); | |
4551 | goto err_out; | |
4552 | } | |
4553 | ||
57aac71b CJ |
4554 | switch (tunnel_type) { |
4555 | case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN: | |
c0c050c5 | 4556 | bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id; |
57aac71b CJ |
4557 | break; |
4558 | case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE: | |
c0c050c5 | 4559 | bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id; |
57aac71b CJ |
4560 | break; |
4561 | default: | |
4562 | break; | |
4563 | } | |
4564 | ||
c0c050c5 MC |
4565 | err_out: |
4566 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4567 | return rc; | |
4568 | } | |
4569 | ||
4570 | static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) | |
4571 | { | |
4572 | struct hwrm_cfa_l2_set_rx_mask_input req = {0}; | |
4573 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; | |
4574 | ||
4575 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1); | |
c193554e | 4576 | req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); |
c0c050c5 MC |
4577 | |
4578 | req.num_mc_entries = cpu_to_le32(vnic->mc_list_count); | |
4579 | req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); | |
4580 | req.mask = cpu_to_le32(vnic->rx_mask); | |
4581 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4582 | } | |
4583 | ||
4584 | #ifdef CONFIG_RFS_ACCEL | |
4585 | static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, | |
4586 | struct bnxt_ntuple_filter *fltr) | |
4587 | { | |
4588 | struct hwrm_cfa_ntuple_filter_free_input req = {0}; | |
4589 | ||
4590 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1); | |
4591 | req.ntuple_filter_id = fltr->filter_id; | |
4592 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4593 | } | |
4594 | ||
4595 | #define BNXT_NTP_FLTR_FLAGS \ | |
4596 | (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ | |
4597 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ | |
4598 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ | |
4599 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ | |
4600 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ | |
4601 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ | |
4602 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ | |
4603 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ | |
4604 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ | |
4605 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ | |
4606 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ | |
4607 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ | |
4608 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ | |
c193554e | 4609 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) |
c0c050c5 | 4610 | |
61aad724 MC |
4611 | #define BNXT_NTP_TUNNEL_FLTR_FLAG \ |
4612 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE | |
4613 | ||
c0c050c5 MC |
4614 | static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, |
4615 | struct bnxt_ntuple_filter *fltr) | |
4616 | { | |
c0c050c5 | 4617 | struct hwrm_cfa_ntuple_filter_alloc_input req = {0}; |
5c209fc8 | 4618 | struct hwrm_cfa_ntuple_filter_alloc_output *resp; |
c0c050c5 | 4619 | struct flow_keys *keys = &fltr->fkeys; |
ac33906c | 4620 | struct bnxt_vnic_info *vnic; |
41136ab3 | 4621 | u32 flags = 0; |
5c209fc8 | 4622 | int rc = 0; |
c0c050c5 MC |
4623 | |
4624 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1); | |
a54c4d74 | 4625 | req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx]; |
c0c050c5 | 4626 | |
41136ab3 MC |
4627 | if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) { |
4628 | flags = CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX; | |
4629 | req.dst_id = cpu_to_le16(fltr->rxq); | |
ac33906c MC |
4630 | } else { |
4631 | vnic = &bp->vnic_info[fltr->rxq + 1]; | |
41136ab3 | 4632 | req.dst_id = cpu_to_le16(vnic->fw_vnic_id); |
ac33906c | 4633 | } |
41136ab3 MC |
4634 | req.flags = cpu_to_le32(flags); |
4635 | req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS); | |
c0c050c5 MC |
4636 | |
4637 | req.ethertype = htons(ETH_P_IP); | |
4638 | memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN); | |
c193554e | 4639 | req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; |
c0c050c5 MC |
4640 | req.ip_protocol = keys->basic.ip_proto; |
4641 | ||
dda0e746 MC |
4642 | if (keys->basic.n_proto == htons(ETH_P_IPV6)) { |
4643 | int i; | |
4644 | ||
4645 | req.ethertype = htons(ETH_P_IPV6); | |
4646 | req.ip_addr_type = | |
4647 | CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6; | |
4648 | *(struct in6_addr *)&req.src_ipaddr[0] = | |
4649 | keys->addrs.v6addrs.src; | |
4650 | *(struct in6_addr *)&req.dst_ipaddr[0] = | |
4651 | keys->addrs.v6addrs.dst; | |
4652 | for (i = 0; i < 4; i++) { | |
4653 | req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff); | |
4654 | req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff); | |
4655 | } | |
4656 | } else { | |
4657 | req.src_ipaddr[0] = keys->addrs.v4addrs.src; | |
4658 | req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); | |
4659 | req.dst_ipaddr[0] = keys->addrs.v4addrs.dst; | |
4660 | req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); | |
4661 | } | |
61aad724 MC |
4662 | if (keys->control.flags & FLOW_DIS_ENCAPSULATION) { |
4663 | req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG); | |
4664 | req.tunnel_type = | |
4665 | CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL; | |
4666 | } | |
c0c050c5 MC |
4667 | |
4668 | req.src_port = keys->ports.src; | |
4669 | req.src_port_mask = cpu_to_be16(0xffff); | |
4670 | req.dst_port = keys->ports.dst; | |
4671 | req.dst_port_mask = cpu_to_be16(0xffff); | |
4672 | ||
c0c050c5 MC |
4673 | mutex_lock(&bp->hwrm_cmd_lock); |
4674 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5c209fc8 VD |
4675 | if (!rc) { |
4676 | resp = bnxt_get_hwrm_resp_addr(bp, &req); | |
c0c050c5 | 4677 | fltr->filter_id = resp->ntuple_filter_id; |
5c209fc8 | 4678 | } |
c0c050c5 MC |
4679 | mutex_unlock(&bp->hwrm_cmd_lock); |
4680 | return rc; | |
4681 | } | |
4682 | #endif | |
4683 | ||
4684 | static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, | |
4685 | u8 *mac_addr) | |
4686 | { | |
4687 | u32 rc = 0; | |
4688 | struct hwrm_cfa_l2_filter_alloc_input req = {0}; | |
4689 | struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
4690 | ||
4691 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1); | |
dc52c6c7 PS |
4692 | req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX); |
4693 | if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) | |
4694 | req.flags |= | |
4695 | cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); | |
c193554e | 4696 | req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); |
c0c050c5 MC |
4697 | req.enables = |
4698 | cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | | |
c193554e | 4699 | CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | |
c0c050c5 MC |
4700 | CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); |
4701 | memcpy(req.l2_addr, mac_addr, ETH_ALEN); | |
4702 | req.l2_addr_mask[0] = 0xff; | |
4703 | req.l2_addr_mask[1] = 0xff; | |
4704 | req.l2_addr_mask[2] = 0xff; | |
4705 | req.l2_addr_mask[3] = 0xff; | |
4706 | req.l2_addr_mask[4] = 0xff; | |
4707 | req.l2_addr_mask[5] = 0xff; | |
4708 | ||
4709 | mutex_lock(&bp->hwrm_cmd_lock); | |
4710 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4711 | if (!rc) | |
4712 | bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = | |
4713 | resp->l2_filter_id; | |
4714 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4715 | return rc; | |
4716 | } | |
4717 | ||
4718 | static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) | |
4719 | { | |
4720 | u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ | |
4721 | int rc = 0; | |
4722 | ||
4723 | /* Any associated ntuple filters will also be cleared by firmware. */ | |
4724 | mutex_lock(&bp->hwrm_cmd_lock); | |
4725 | for (i = 0; i < num_of_vnics; i++) { | |
4726 | struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; | |
4727 | ||
4728 | for (j = 0; j < vnic->uc_filter_count; j++) { | |
4729 | struct hwrm_cfa_l2_filter_free_input req = {0}; | |
4730 | ||
4731 | bnxt_hwrm_cmd_hdr_init(bp, &req, | |
4732 | HWRM_CFA_L2_FILTER_FREE, -1, -1); | |
4733 | ||
4734 | req.l2_filter_id = vnic->fw_l2_filter_id[j]; | |
4735 | ||
4736 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
4737 | HWRM_CMD_TIMEOUT); | |
4738 | } | |
4739 | vnic->uc_filter_count = 0; | |
4740 | } | |
4741 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4742 | ||
4743 | return rc; | |
4744 | } | |
4745 | ||
4746 | static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) | |
4747 | { | |
4748 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; | |
79632e9b | 4749 | u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX; |
c0c050c5 MC |
4750 | struct hwrm_vnic_tpa_cfg_input req = {0}; |
4751 | ||
3c4fe80b MC |
4752 | if (vnic->fw_vnic_id == INVALID_HW_RING_ID) |
4753 | return 0; | |
4754 | ||
c0c050c5 MC |
4755 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1); |
4756 | ||
4757 | if (tpa_flags) { | |
4758 | u16 mss = bp->dev->mtu - 40; | |
4759 | u32 nsegs, n, segs = 0, flags; | |
4760 | ||
4761 | flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | | |
4762 | VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | | |
4763 | VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | | |
4764 | VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | | |
4765 | VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; | |
4766 | if (tpa_flags & BNXT_FLAG_GRO) | |
4767 | flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; | |
4768 | ||
4769 | req.flags = cpu_to_le32(flags); | |
4770 | ||
4771 | req.enables = | |
4772 | cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | | |
c193554e MC |
4773 | VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | |
4774 | VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); | |
c0c050c5 MC |
4775 | |
4776 | /* Number of segs are log2 units, and first packet is not | |
4777 | * included as part of this units. | |
4778 | */ | |
2839f28b MC |
4779 | if (mss <= BNXT_RX_PAGE_SIZE) { |
4780 | n = BNXT_RX_PAGE_SIZE / mss; | |
c0c050c5 MC |
4781 | nsegs = (MAX_SKB_FRAGS - 1) * n; |
4782 | } else { | |
2839f28b MC |
4783 | n = mss / BNXT_RX_PAGE_SIZE; |
4784 | if (mss & (BNXT_RX_PAGE_SIZE - 1)) | |
c0c050c5 MC |
4785 | n++; |
4786 | nsegs = (MAX_SKB_FRAGS - n) / n; | |
4787 | } | |
4788 | ||
79632e9b MC |
4789 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
4790 | segs = MAX_TPA_SEGS_P5; | |
4791 | max_aggs = bp->max_tpa; | |
4792 | } else { | |
4793 | segs = ilog2(nsegs); | |
4794 | } | |
c0c050c5 | 4795 | req.max_agg_segs = cpu_to_le16(segs); |
79632e9b | 4796 | req.max_aggs = cpu_to_le16(max_aggs); |
c193554e MC |
4797 | |
4798 | req.min_agg_len = cpu_to_le32(512); | |
c0c050c5 MC |
4799 | } |
4800 | req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); | |
4801 | ||
4802 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4803 | } | |
4804 | ||
2c61d211 MC |
4805 | static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring) |
4806 | { | |
4807 | struct bnxt_ring_grp_info *grp_info; | |
4808 | ||
4809 | grp_info = &bp->grp_info[ring->grp_idx]; | |
4810 | return grp_info->cp_fw_ring_id; | |
4811 | } | |
4812 | ||
4813 | static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) | |
4814 | { | |
4815 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
4816 | struct bnxt_napi *bnapi = rxr->bnapi; | |
4817 | struct bnxt_cp_ring_info *cpr; | |
4818 | ||
4819 | cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL]; | |
4820 | return cpr->cp_ring_struct.fw_ring_id; | |
4821 | } else { | |
4822 | return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct); | |
4823 | } | |
4824 | } | |
4825 | ||
4826 | static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr) | |
4827 | { | |
4828 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
4829 | struct bnxt_napi *bnapi = txr->bnapi; | |
4830 | struct bnxt_cp_ring_info *cpr; | |
4831 | ||
4832 | cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL]; | |
4833 | return cpr->cp_ring_struct.fw_ring_id; | |
4834 | } else { | |
4835 | return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct); | |
4836 | } | |
4837 | } | |
4838 | ||
c0c050c5 MC |
4839 | static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) |
4840 | { | |
4841 | u32 i, j, max_rings; | |
4842 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; | |
4843 | struct hwrm_vnic_rss_cfg_input req = {0}; | |
4844 | ||
7b3af4f7 MC |
4845 | if ((bp->flags & BNXT_FLAG_CHIP_P5) || |
4846 | vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID) | |
c0c050c5 MC |
4847 | return 0; |
4848 | ||
4849 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); | |
4850 | if (set_rss) { | |
87da7f79 | 4851 | req.hash_type = cpu_to_le32(bp->rss_hash_cfg); |
50f011b6 | 4852 | req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; |
dc52c6c7 PS |
4853 | if (vnic->flags & BNXT_VNIC_RSS_FLAG) { |
4854 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) | |
4855 | max_rings = bp->rx_nr_rings - 1; | |
4856 | else | |
4857 | max_rings = bp->rx_nr_rings; | |
4858 | } else { | |
c0c050c5 | 4859 | max_rings = 1; |
dc52c6c7 | 4860 | } |
c0c050c5 MC |
4861 | |
4862 | /* Fill the RSS indirection table with ring group ids */ | |
4863 | for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) { | |
4864 | if (j == max_rings) | |
4865 | j = 0; | |
4866 | vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); | |
4867 | } | |
4868 | ||
4869 | req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); | |
4870 | req.hash_key_tbl_addr = | |
4871 | cpu_to_le64(vnic->rss_hash_key_dma_addr); | |
4872 | } | |
94ce9caa | 4873 | req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); |
c0c050c5 MC |
4874 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
4875 | } | |
4876 | ||
7b3af4f7 MC |
4877 | static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss) |
4878 | { | |
4879 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; | |
4880 | u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings; | |
4881 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; | |
4882 | struct hwrm_vnic_rss_cfg_input req = {0}; | |
4883 | ||
4884 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); | |
4885 | req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); | |
4886 | if (!set_rss) { | |
4887 | hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4888 | return 0; | |
4889 | } | |
4890 | req.hash_type = cpu_to_le32(bp->rss_hash_cfg); | |
4891 | req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; | |
4892 | req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); | |
4893 | req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr); | |
4894 | nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64); | |
4895 | for (i = 0, k = 0; i < nr_ctxs; i++) { | |
4896 | __le16 *ring_tbl = vnic->rss_table; | |
4897 | int rc; | |
4898 | ||
4899 | req.ring_table_pair_index = i; | |
4900 | req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]); | |
4901 | for (j = 0; j < 64; j++) { | |
4902 | u16 ring_id; | |
4903 | ||
4904 | ring_id = rxr->rx_ring_struct.fw_ring_id; | |
4905 | *ring_tbl++ = cpu_to_le16(ring_id); | |
4906 | ring_id = bnxt_cp_ring_for_rx(bp, rxr); | |
4907 | *ring_tbl++ = cpu_to_le16(ring_id); | |
4908 | rxr++; | |
4909 | k++; | |
4910 | if (k == max_rings) { | |
4911 | k = 0; | |
4912 | rxr = &bp->rx_ring[0]; | |
4913 | } | |
4914 | } | |
4915 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4916 | if (rc) | |
d4f1420d | 4917 | return rc; |
7b3af4f7 MC |
4918 | } |
4919 | return 0; | |
4920 | } | |
4921 | ||
c0c050c5 MC |
4922 | static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) |
4923 | { | |
4924 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; | |
4925 | struct hwrm_vnic_plcmodes_cfg_input req = {0}; | |
4926 | ||
4927 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1); | |
4928 | req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT | | |
4929 | VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | | |
4930 | VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); | |
4931 | req.enables = | |
4932 | cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID | | |
4933 | VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); | |
4934 | /* thresholds not implemented in firmware yet */ | |
4935 | req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); | |
4936 | req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh); | |
4937 | req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); | |
4938 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4939 | } | |
4940 | ||
94ce9caa PS |
4941 | static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id, |
4942 | u16 ctx_idx) | |
c0c050c5 MC |
4943 | { |
4944 | struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0}; | |
4945 | ||
4946 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1); | |
4947 | req.rss_cos_lb_ctx_id = | |
94ce9caa | 4948 | cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]); |
c0c050c5 MC |
4949 | |
4950 | hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
94ce9caa | 4951 | bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID; |
c0c050c5 MC |
4952 | } |
4953 | ||
4954 | static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) | |
4955 | { | |
94ce9caa | 4956 | int i, j; |
c0c050c5 MC |
4957 | |
4958 | for (i = 0; i < bp->nr_vnics; i++) { | |
4959 | struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; | |
4960 | ||
94ce9caa PS |
4961 | for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) { |
4962 | if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID) | |
4963 | bnxt_hwrm_vnic_ctx_free_one(bp, i, j); | |
4964 | } | |
c0c050c5 MC |
4965 | } |
4966 | bp->rsscos_nr_ctxs = 0; | |
4967 | } | |
4968 | ||
94ce9caa | 4969 | static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx) |
c0c050c5 MC |
4970 | { |
4971 | int rc; | |
4972 | struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; | |
4973 | struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = | |
4974 | bp->hwrm_cmd_resp_addr; | |
4975 | ||
4976 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1, | |
4977 | -1); | |
4978 | ||
4979 | mutex_lock(&bp->hwrm_cmd_lock); | |
4980 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4981 | if (!rc) | |
94ce9caa | 4982 | bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = |
c0c050c5 MC |
4983 | le16_to_cpu(resp->rss_cos_lb_ctx_id); |
4984 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4985 | ||
4986 | return rc; | |
4987 | } | |
4988 | ||
abe93ad2 MC |
4989 | static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp) |
4990 | { | |
4991 | if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP) | |
4992 | return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE; | |
4993 | return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE; | |
4994 | } | |
4995 | ||
a588e458 | 4996 | int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) |
c0c050c5 | 4997 | { |
b81a90d3 | 4998 | unsigned int ring = 0, grp_idx; |
c0c050c5 MC |
4999 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
5000 | struct hwrm_vnic_cfg_input req = {0}; | |
cf6645f8 | 5001 | u16 def_vlan = 0; |
c0c050c5 MC |
5002 | |
5003 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1); | |
dc52c6c7 | 5004 | |
7b3af4f7 MC |
5005 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5006 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; | |
5007 | ||
5008 | req.default_rx_ring_id = | |
5009 | cpu_to_le16(rxr->rx_ring_struct.fw_ring_id); | |
5010 | req.default_cmpl_ring_id = | |
5011 | cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr)); | |
5012 | req.enables = | |
5013 | cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID | | |
5014 | VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID); | |
5015 | goto vnic_mru; | |
5016 | } | |
dc52c6c7 | 5017 | req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP); |
c0c050c5 | 5018 | /* Only RSS support for now TBD: COS & LB */ |
dc52c6c7 PS |
5019 | if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) { |
5020 | req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); | |
5021 | req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | | |
5022 | VNIC_CFG_REQ_ENABLES_MRU); | |
ae10ae74 MC |
5023 | } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) { |
5024 | req.rss_rule = | |
5025 | cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]); | |
5026 | req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | | |
5027 | VNIC_CFG_REQ_ENABLES_MRU); | |
5028 | req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE); | |
dc52c6c7 PS |
5029 | } else { |
5030 | req.rss_rule = cpu_to_le16(0xffff); | |
5031 | } | |
94ce9caa | 5032 | |
dc52c6c7 PS |
5033 | if (BNXT_CHIP_TYPE_NITRO_A0(bp) && |
5034 | (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) { | |
94ce9caa PS |
5035 | req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]); |
5036 | req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE); | |
5037 | } else { | |
5038 | req.cos_rule = cpu_to_le16(0xffff); | |
5039 | } | |
5040 | ||
c0c050c5 | 5041 | if (vnic->flags & BNXT_VNIC_RSS_FLAG) |
b81a90d3 | 5042 | ring = 0; |
c0c050c5 | 5043 | else if (vnic->flags & BNXT_VNIC_RFS_FLAG) |
b81a90d3 | 5044 | ring = vnic_id - 1; |
76595193 PS |
5045 | else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp)) |
5046 | ring = bp->rx_nr_rings - 1; | |
c0c050c5 | 5047 | |
b81a90d3 | 5048 | grp_idx = bp->rx_ring[ring].bnapi->index; |
c0c050c5 | 5049 | req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); |
c0c050c5 | 5050 | req.lb_rule = cpu_to_le16(0xffff); |
7b3af4f7 | 5051 | vnic_mru: |
c0c050c5 MC |
5052 | req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + |
5053 | VLAN_HLEN); | |
5054 | ||
7b3af4f7 | 5055 | req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); |
cf6645f8 MC |
5056 | #ifdef CONFIG_BNXT_SRIOV |
5057 | if (BNXT_VF(bp)) | |
5058 | def_vlan = bp->vf.vlan; | |
5059 | #endif | |
5060 | if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan) | |
c0c050c5 | 5061 | req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); |
a588e458 | 5062 | if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) |
abe93ad2 | 5063 | req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp)); |
c0c050c5 MC |
5064 | |
5065 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5066 | } | |
5067 | ||
5068 | static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) | |
5069 | { | |
5070 | u32 rc = 0; | |
5071 | ||
5072 | if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { | |
5073 | struct hwrm_vnic_free_input req = {0}; | |
5074 | ||
5075 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1); | |
5076 | req.vnic_id = | |
5077 | cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); | |
5078 | ||
5079 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
c0c050c5 MC |
5080 | bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; |
5081 | } | |
5082 | return rc; | |
5083 | } | |
5084 | ||
5085 | static void bnxt_hwrm_vnic_free(struct bnxt *bp) | |
5086 | { | |
5087 | u16 i; | |
5088 | ||
5089 | for (i = 0; i < bp->nr_vnics; i++) | |
5090 | bnxt_hwrm_vnic_free_one(bp, i); | |
5091 | } | |
5092 | ||
b81a90d3 MC |
5093 | static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, |
5094 | unsigned int start_rx_ring_idx, | |
5095 | unsigned int nr_rings) | |
c0c050c5 | 5096 | { |
b81a90d3 MC |
5097 | int rc = 0; |
5098 | unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; | |
c0c050c5 MC |
5099 | struct hwrm_vnic_alloc_input req = {0}; |
5100 | struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
44c6f72a MC |
5101 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
5102 | ||
5103 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
5104 | goto vnic_no_ring_grps; | |
c0c050c5 MC |
5105 | |
5106 | /* map ring groups to this vnic */ | |
b81a90d3 MC |
5107 | for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { |
5108 | grp_idx = bp->rx_ring[i].bnapi->index; | |
5109 | if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { | |
c0c050c5 | 5110 | netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", |
b81a90d3 | 5111 | j, nr_rings); |
c0c050c5 MC |
5112 | break; |
5113 | } | |
44c6f72a | 5114 | vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id; |
c0c050c5 MC |
5115 | } |
5116 | ||
44c6f72a MC |
5117 | vnic_no_ring_grps: |
5118 | for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++) | |
5119 | vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID; | |
c0c050c5 MC |
5120 | if (vnic_id == 0) |
5121 | req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); | |
5122 | ||
5123 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1); | |
5124 | ||
5125 | mutex_lock(&bp->hwrm_cmd_lock); | |
5126 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5127 | if (!rc) | |
44c6f72a | 5128 | vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id); |
c0c050c5 MC |
5129 | mutex_unlock(&bp->hwrm_cmd_lock); |
5130 | return rc; | |
5131 | } | |
5132 | ||
8fdefd63 MC |
5133 | static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) |
5134 | { | |
5135 | struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
5136 | struct hwrm_vnic_qcaps_input req = {0}; | |
5137 | int rc; | |
5138 | ||
fbbdbc64 | 5139 | bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats); |
ba642ab7 | 5140 | bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP); |
8fdefd63 MC |
5141 | if (bp->hwrm_spec_code < 0x10600) |
5142 | return 0; | |
5143 | ||
5144 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1); | |
5145 | mutex_lock(&bp->hwrm_cmd_lock); | |
5146 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5147 | if (!rc) { | |
abe93ad2 MC |
5148 | u32 flags = le32_to_cpu(resp->flags); |
5149 | ||
41e8d798 MC |
5150 | if (!(bp->flags & BNXT_FLAG_CHIP_P5) && |
5151 | (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)) | |
8fdefd63 | 5152 | bp->flags |= BNXT_FLAG_NEW_RSS_CAP; |
abe93ad2 MC |
5153 | if (flags & |
5154 | VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP) | |
5155 | bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP; | |
79632e9b | 5156 | bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported); |
4e748506 MC |
5157 | if (bp->max_tpa_v2) |
5158 | bp->hw_ring_stats_size = | |
5159 | sizeof(struct ctx_hw_stats_ext); | |
8fdefd63 MC |
5160 | } |
5161 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5162 | return rc; | |
5163 | } | |
5164 | ||
c0c050c5 MC |
5165 | static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) |
5166 | { | |
5167 | u16 i; | |
5168 | u32 rc = 0; | |
5169 | ||
44c6f72a MC |
5170 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
5171 | return 0; | |
5172 | ||
c0c050c5 MC |
5173 | mutex_lock(&bp->hwrm_cmd_lock); |
5174 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
5175 | struct hwrm_ring_grp_alloc_input req = {0}; | |
5176 | struct hwrm_ring_grp_alloc_output *resp = | |
5177 | bp->hwrm_cmd_resp_addr; | |
b81a90d3 | 5178 | unsigned int grp_idx = bp->rx_ring[i].bnapi->index; |
c0c050c5 MC |
5179 | |
5180 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1); | |
5181 | ||
b81a90d3 MC |
5182 | req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); |
5183 | req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); | |
5184 | req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); | |
5185 | req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); | |
c0c050c5 MC |
5186 | |
5187 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
5188 | HWRM_CMD_TIMEOUT); | |
5189 | if (rc) | |
5190 | break; | |
5191 | ||
b81a90d3 MC |
5192 | bp->grp_info[grp_idx].fw_grp_id = |
5193 | le32_to_cpu(resp->ring_group_id); | |
c0c050c5 MC |
5194 | } |
5195 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5196 | return rc; | |
5197 | } | |
5198 | ||
5199 | static int bnxt_hwrm_ring_grp_free(struct bnxt *bp) | |
5200 | { | |
5201 | u16 i; | |
5202 | u32 rc = 0; | |
5203 | struct hwrm_ring_grp_free_input req = {0}; | |
5204 | ||
44c6f72a | 5205 | if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5)) |
c0c050c5 MC |
5206 | return 0; |
5207 | ||
5208 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1); | |
5209 | ||
5210 | mutex_lock(&bp->hwrm_cmd_lock); | |
5211 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
5212 | if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) | |
5213 | continue; | |
5214 | req.ring_group_id = | |
5215 | cpu_to_le32(bp->grp_info[i].fw_grp_id); | |
5216 | ||
5217 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
5218 | HWRM_CMD_TIMEOUT); | |
c0c050c5 MC |
5219 | bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; |
5220 | } | |
5221 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5222 | return rc; | |
5223 | } | |
5224 | ||
5225 | static int hwrm_ring_alloc_send_msg(struct bnxt *bp, | |
5226 | struct bnxt_ring_struct *ring, | |
9899bb59 | 5227 | u32 ring_type, u32 map_index) |
c0c050c5 MC |
5228 | { |
5229 | int rc = 0, err = 0; | |
5230 | struct hwrm_ring_alloc_input req = {0}; | |
5231 | struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
6fe19886 | 5232 | struct bnxt_ring_mem_info *rmem = &ring->ring_mem; |
9899bb59 | 5233 | struct bnxt_ring_grp_info *grp_info; |
c0c050c5 MC |
5234 | u16 ring_id; |
5235 | ||
5236 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1); | |
5237 | ||
5238 | req.enables = 0; | |
6fe19886 MC |
5239 | if (rmem->nr_pages > 1) { |
5240 | req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map); | |
c0c050c5 MC |
5241 | /* Page size is in log2 units */ |
5242 | req.page_size = BNXT_PAGE_SHIFT; | |
5243 | req.page_tbl_depth = 1; | |
5244 | } else { | |
6fe19886 | 5245 | req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]); |
c0c050c5 MC |
5246 | } |
5247 | req.fbo = 0; | |
5248 | /* Association of ring index with doorbell index and MSIX number */ | |
5249 | req.logical_id = cpu_to_le16(map_index); | |
5250 | ||
5251 | switch (ring_type) { | |
2c61d211 MC |
5252 | case HWRM_RING_ALLOC_TX: { |
5253 | struct bnxt_tx_ring_info *txr; | |
5254 | ||
5255 | txr = container_of(ring, struct bnxt_tx_ring_info, | |
5256 | tx_ring_struct); | |
c0c050c5 MC |
5257 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX; |
5258 | /* Association of transmit ring with completion ring */ | |
9899bb59 | 5259 | grp_info = &bp->grp_info[ring->grp_idx]; |
2c61d211 | 5260 | req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr)); |
c0c050c5 | 5261 | req.length = cpu_to_le32(bp->tx_ring_mask + 1); |
9899bb59 | 5262 | req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); |
c0c050c5 MC |
5263 | req.queue_id = cpu_to_le16(ring->queue_id); |
5264 | break; | |
2c61d211 | 5265 | } |
c0c050c5 MC |
5266 | case HWRM_RING_ALLOC_RX: |
5267 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; | |
5268 | req.length = cpu_to_le32(bp->rx_ring_mask + 1); | |
23aefdd7 MC |
5269 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5270 | u16 flags = 0; | |
5271 | ||
5272 | /* Association of rx ring with stats context */ | |
5273 | grp_info = &bp->grp_info[ring->grp_idx]; | |
5274 | req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size); | |
5275 | req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); | |
5276 | req.enables |= cpu_to_le32( | |
5277 | RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); | |
5278 | if (NET_IP_ALIGN == 2) | |
5279 | flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD; | |
5280 | req.flags = cpu_to_le16(flags); | |
5281 | } | |
c0c050c5 MC |
5282 | break; |
5283 | case HWRM_RING_ALLOC_AGG: | |
23aefdd7 MC |
5284 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5285 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG; | |
5286 | /* Association of agg ring with rx ring */ | |
5287 | grp_info = &bp->grp_info[ring->grp_idx]; | |
5288 | req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id); | |
5289 | req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE); | |
5290 | req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); | |
5291 | req.enables |= cpu_to_le32( | |
5292 | RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID | | |
5293 | RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); | |
5294 | } else { | |
5295 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; | |
5296 | } | |
c0c050c5 MC |
5297 | req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1); |
5298 | break; | |
5299 | case HWRM_RING_ALLOC_CMPL: | |
bac9a7e0 | 5300 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL; |
c0c050c5 | 5301 | req.length = cpu_to_le32(bp->cp_ring_mask + 1); |
23aefdd7 MC |
5302 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5303 | /* Association of cp ring with nq */ | |
5304 | grp_info = &bp->grp_info[map_index]; | |
5305 | req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id); | |
5306 | req.cq_handle = cpu_to_le64(ring->handle); | |
5307 | req.enables |= cpu_to_le32( | |
5308 | RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID); | |
5309 | } else if (bp->flags & BNXT_FLAG_USING_MSIX) { | |
5310 | req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; | |
5311 | } | |
5312 | break; | |
5313 | case HWRM_RING_ALLOC_NQ: | |
5314 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ; | |
5315 | req.length = cpu_to_le32(bp->cp_ring_mask + 1); | |
c0c050c5 MC |
5316 | if (bp->flags & BNXT_FLAG_USING_MSIX) |
5317 | req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; | |
5318 | break; | |
5319 | default: | |
5320 | netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", | |
5321 | ring_type); | |
5322 | return -1; | |
5323 | } | |
5324 | ||
5325 | mutex_lock(&bp->hwrm_cmd_lock); | |
5326 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5327 | err = le16_to_cpu(resp->error_code); | |
5328 | ring_id = le16_to_cpu(resp->ring_id); | |
5329 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5330 | ||
5331 | if (rc || err) { | |
2727c888 MC |
5332 | netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n", |
5333 | ring_type, rc, err); | |
5334 | return -EIO; | |
c0c050c5 MC |
5335 | } |
5336 | ring->fw_ring_id = ring_id; | |
5337 | return rc; | |
5338 | } | |
5339 | ||
486b5c22 MC |
5340 | static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx) |
5341 | { | |
5342 | int rc; | |
5343 | ||
5344 | if (BNXT_PF(bp)) { | |
5345 | struct hwrm_func_cfg_input req = {0}; | |
5346 | ||
5347 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); | |
5348 | req.fid = cpu_to_le16(0xffff); | |
5349 | req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR); | |
5350 | req.async_event_cr = cpu_to_le16(idx); | |
5351 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5352 | } else { | |
5353 | struct hwrm_func_vf_cfg_input req = {0}; | |
5354 | ||
5355 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1); | |
5356 | req.enables = | |
5357 | cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR); | |
5358 | req.async_event_cr = cpu_to_le16(idx); | |
5359 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5360 | } | |
5361 | return rc; | |
5362 | } | |
5363 | ||
697197e5 MC |
5364 | static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type, |
5365 | u32 map_idx, u32 xid) | |
5366 | { | |
5367 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
5368 | if (BNXT_PF(bp)) | |
5369 | db->doorbell = bp->bar1 + 0x10000; | |
5370 | else | |
5371 | db->doorbell = bp->bar1 + 0x4000; | |
5372 | switch (ring_type) { | |
5373 | case HWRM_RING_ALLOC_TX: | |
5374 | db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ; | |
5375 | break; | |
5376 | case HWRM_RING_ALLOC_RX: | |
5377 | case HWRM_RING_ALLOC_AGG: | |
5378 | db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ; | |
5379 | break; | |
5380 | case HWRM_RING_ALLOC_CMPL: | |
5381 | db->db_key64 = DBR_PATH_L2; | |
5382 | break; | |
5383 | case HWRM_RING_ALLOC_NQ: | |
5384 | db->db_key64 = DBR_PATH_L2; | |
5385 | break; | |
5386 | } | |
5387 | db->db_key64 |= (u64)xid << DBR_XID_SFT; | |
5388 | } else { | |
5389 | db->doorbell = bp->bar1 + map_idx * 0x80; | |
5390 | switch (ring_type) { | |
5391 | case HWRM_RING_ALLOC_TX: | |
5392 | db->db_key32 = DB_KEY_TX; | |
5393 | break; | |
5394 | case HWRM_RING_ALLOC_RX: | |
5395 | case HWRM_RING_ALLOC_AGG: | |
5396 | db->db_key32 = DB_KEY_RX; | |
5397 | break; | |
5398 | case HWRM_RING_ALLOC_CMPL: | |
5399 | db->db_key32 = DB_KEY_CP; | |
5400 | break; | |
5401 | } | |
5402 | } | |
5403 | } | |
5404 | ||
c0c050c5 MC |
5405 | static int bnxt_hwrm_ring_alloc(struct bnxt *bp) |
5406 | { | |
e8f267b0 | 5407 | bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS); |
c0c050c5 | 5408 | int i, rc = 0; |
697197e5 | 5409 | u32 type; |
c0c050c5 | 5410 | |
23aefdd7 MC |
5411 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
5412 | type = HWRM_RING_ALLOC_NQ; | |
5413 | else | |
5414 | type = HWRM_RING_ALLOC_CMPL; | |
edd0c2cc MC |
5415 | for (i = 0; i < bp->cp_nr_rings; i++) { |
5416 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
5417 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
5418 | struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; | |
9899bb59 | 5419 | u32 map_idx = ring->map_idx; |
5e66e35a | 5420 | unsigned int vector; |
c0c050c5 | 5421 | |
5e66e35a MC |
5422 | vector = bp->irq_tbl[map_idx].vector; |
5423 | disable_irq_nosync(vector); | |
697197e5 | 5424 | rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); |
5e66e35a MC |
5425 | if (rc) { |
5426 | enable_irq(vector); | |
edd0c2cc | 5427 | goto err_out; |
5e66e35a | 5428 | } |
697197e5 MC |
5429 | bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id); |
5430 | bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); | |
5e66e35a | 5431 | enable_irq(vector); |
edd0c2cc | 5432 | bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; |
486b5c22 MC |
5433 | |
5434 | if (!i) { | |
5435 | rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id); | |
5436 | if (rc) | |
5437 | netdev_warn(bp->dev, "Failed to set async event completion ring.\n"); | |
5438 | } | |
c0c050c5 MC |
5439 | } |
5440 | ||
697197e5 | 5441 | type = HWRM_RING_ALLOC_TX; |
edd0c2cc | 5442 | for (i = 0; i < bp->tx_nr_rings; i++) { |
b6ab4b01 | 5443 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
3e08b184 MC |
5444 | struct bnxt_ring_struct *ring; |
5445 | u32 map_idx; | |
c0c050c5 | 5446 | |
3e08b184 MC |
5447 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5448 | struct bnxt_napi *bnapi = txr->bnapi; | |
5449 | struct bnxt_cp_ring_info *cpr, *cpr2; | |
5450 | u32 type2 = HWRM_RING_ALLOC_CMPL; | |
5451 | ||
5452 | cpr = &bnapi->cp_ring; | |
5453 | cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL]; | |
5454 | ring = &cpr2->cp_ring_struct; | |
5455 | ring->handle = BNXT_TX_HDL; | |
5456 | map_idx = bnapi->index; | |
5457 | rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); | |
5458 | if (rc) | |
5459 | goto err_out; | |
5460 | bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, | |
5461 | ring->fw_ring_id); | |
5462 | bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); | |
5463 | } | |
5464 | ring = &txr->tx_ring_struct; | |
5465 | map_idx = i; | |
697197e5 | 5466 | rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); |
edd0c2cc MC |
5467 | if (rc) |
5468 | goto err_out; | |
697197e5 | 5469 | bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id); |
c0c050c5 MC |
5470 | } |
5471 | ||
697197e5 | 5472 | type = HWRM_RING_ALLOC_RX; |
edd0c2cc | 5473 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 5474 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
edd0c2cc | 5475 | struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; |
3e08b184 MC |
5476 | struct bnxt_napi *bnapi = rxr->bnapi; |
5477 | u32 map_idx = bnapi->index; | |
c0c050c5 | 5478 | |
697197e5 | 5479 | rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); |
edd0c2cc MC |
5480 | if (rc) |
5481 | goto err_out; | |
697197e5 | 5482 | bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id); |
e8f267b0 MC |
5483 | /* If we have agg rings, post agg buffers first. */ |
5484 | if (!agg_rings) | |
5485 | bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); | |
b81a90d3 | 5486 | bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; |
3e08b184 MC |
5487 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5488 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
5489 | u32 type2 = HWRM_RING_ALLOC_CMPL; | |
5490 | struct bnxt_cp_ring_info *cpr2; | |
5491 | ||
5492 | cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL]; | |
5493 | ring = &cpr2->cp_ring_struct; | |
5494 | ring->handle = BNXT_RX_HDL; | |
5495 | rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); | |
5496 | if (rc) | |
5497 | goto err_out; | |
5498 | bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, | |
5499 | ring->fw_ring_id); | |
5500 | bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); | |
5501 | } | |
c0c050c5 MC |
5502 | } |
5503 | ||
e8f267b0 | 5504 | if (agg_rings) { |
697197e5 | 5505 | type = HWRM_RING_ALLOC_AGG; |
c0c050c5 | 5506 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 5507 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
c0c050c5 MC |
5508 | struct bnxt_ring_struct *ring = |
5509 | &rxr->rx_agg_ring_struct; | |
9899bb59 | 5510 | u32 grp_idx = ring->grp_idx; |
b81a90d3 | 5511 | u32 map_idx = grp_idx + bp->rx_nr_rings; |
c0c050c5 | 5512 | |
697197e5 | 5513 | rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); |
c0c050c5 MC |
5514 | if (rc) |
5515 | goto err_out; | |
5516 | ||
697197e5 MC |
5517 | bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx, |
5518 | ring->fw_ring_id); | |
5519 | bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); | |
e8f267b0 | 5520 | bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); |
b81a90d3 | 5521 | bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; |
c0c050c5 MC |
5522 | } |
5523 | } | |
5524 | err_out: | |
5525 | return rc; | |
5526 | } | |
5527 | ||
5528 | static int hwrm_ring_free_send_msg(struct bnxt *bp, | |
5529 | struct bnxt_ring_struct *ring, | |
5530 | u32 ring_type, int cmpl_ring_id) | |
5531 | { | |
5532 | int rc; | |
5533 | struct hwrm_ring_free_input req = {0}; | |
5534 | struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr; | |
5535 | u16 error_code; | |
5536 | ||
b4fff207 MC |
5537 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) |
5538 | return 0; | |
5539 | ||
74608fc9 | 5540 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1); |
c0c050c5 MC |
5541 | req.ring_type = ring_type; |
5542 | req.ring_id = cpu_to_le16(ring->fw_ring_id); | |
5543 | ||
5544 | mutex_lock(&bp->hwrm_cmd_lock); | |
5545 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5546 | error_code = le16_to_cpu(resp->error_code); | |
5547 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5548 | ||
5549 | if (rc || error_code) { | |
2727c888 MC |
5550 | netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n", |
5551 | ring_type, rc, error_code); | |
5552 | return -EIO; | |
c0c050c5 MC |
5553 | } |
5554 | return 0; | |
5555 | } | |
5556 | ||
edd0c2cc | 5557 | static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) |
c0c050c5 | 5558 | { |
23aefdd7 | 5559 | u32 type; |
edd0c2cc | 5560 | int i; |
c0c050c5 MC |
5561 | |
5562 | if (!bp->bnapi) | |
edd0c2cc | 5563 | return; |
c0c050c5 | 5564 | |
edd0c2cc | 5565 | for (i = 0; i < bp->tx_nr_rings; i++) { |
b6ab4b01 | 5566 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
edd0c2cc | 5567 | struct bnxt_ring_struct *ring = &txr->tx_ring_struct; |
edd0c2cc MC |
5568 | |
5569 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
1f83391b MC |
5570 | u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr); |
5571 | ||
edd0c2cc MC |
5572 | hwrm_ring_free_send_msg(bp, ring, |
5573 | RING_FREE_REQ_RING_TYPE_TX, | |
5574 | close_path ? cmpl_ring_id : | |
5575 | INVALID_HW_RING_ID); | |
5576 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
c0c050c5 MC |
5577 | } |
5578 | } | |
5579 | ||
edd0c2cc | 5580 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 5581 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
edd0c2cc | 5582 | struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; |
b81a90d3 | 5583 | u32 grp_idx = rxr->bnapi->index; |
edd0c2cc MC |
5584 | |
5585 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
1f83391b MC |
5586 | u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); |
5587 | ||
edd0c2cc MC |
5588 | hwrm_ring_free_send_msg(bp, ring, |
5589 | RING_FREE_REQ_RING_TYPE_RX, | |
5590 | close_path ? cmpl_ring_id : | |
5591 | INVALID_HW_RING_ID); | |
5592 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
b81a90d3 MC |
5593 | bp->grp_info[grp_idx].rx_fw_ring_id = |
5594 | INVALID_HW_RING_ID; | |
c0c050c5 MC |
5595 | } |
5596 | } | |
5597 | ||
23aefdd7 MC |
5598 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
5599 | type = RING_FREE_REQ_RING_TYPE_RX_AGG; | |
5600 | else | |
5601 | type = RING_FREE_REQ_RING_TYPE_RX; | |
edd0c2cc | 5602 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 5603 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
edd0c2cc | 5604 | struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; |
b81a90d3 | 5605 | u32 grp_idx = rxr->bnapi->index; |
edd0c2cc MC |
5606 | |
5607 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
1f83391b MC |
5608 | u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); |
5609 | ||
23aefdd7 | 5610 | hwrm_ring_free_send_msg(bp, ring, type, |
edd0c2cc MC |
5611 | close_path ? cmpl_ring_id : |
5612 | INVALID_HW_RING_ID); | |
5613 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
b81a90d3 MC |
5614 | bp->grp_info[grp_idx].agg_fw_ring_id = |
5615 | INVALID_HW_RING_ID; | |
c0c050c5 MC |
5616 | } |
5617 | } | |
5618 | ||
9d8bc097 MC |
5619 | /* The completion rings are about to be freed. After that the |
5620 | * IRQ doorbell will not work anymore. So we need to disable | |
5621 | * IRQ here. | |
5622 | */ | |
5623 | bnxt_disable_int_sync(bp); | |
5624 | ||
23aefdd7 MC |
5625 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
5626 | type = RING_FREE_REQ_RING_TYPE_NQ; | |
5627 | else | |
5628 | type = RING_FREE_REQ_RING_TYPE_L2_CMPL; | |
edd0c2cc MC |
5629 | for (i = 0; i < bp->cp_nr_rings; i++) { |
5630 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
5631 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
3e08b184 MC |
5632 | struct bnxt_ring_struct *ring; |
5633 | int j; | |
edd0c2cc | 5634 | |
3e08b184 MC |
5635 | for (j = 0; j < 2; j++) { |
5636 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; | |
5637 | ||
5638 | if (cpr2) { | |
5639 | ring = &cpr2->cp_ring_struct; | |
5640 | if (ring->fw_ring_id == INVALID_HW_RING_ID) | |
5641 | continue; | |
5642 | hwrm_ring_free_send_msg(bp, ring, | |
5643 | RING_FREE_REQ_RING_TYPE_L2_CMPL, | |
5644 | INVALID_HW_RING_ID); | |
5645 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
5646 | } | |
5647 | } | |
5648 | ring = &cpr->cp_ring_struct; | |
edd0c2cc | 5649 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { |
23aefdd7 | 5650 | hwrm_ring_free_send_msg(bp, ring, type, |
edd0c2cc MC |
5651 | INVALID_HW_RING_ID); |
5652 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
5653 | bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; | |
c0c050c5 MC |
5654 | } |
5655 | } | |
c0c050c5 MC |
5656 | } |
5657 | ||
41e8d798 MC |
5658 | static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, |
5659 | bool shared); | |
5660 | ||
674f50a5 MC |
5661 | static int bnxt_hwrm_get_rings(struct bnxt *bp) |
5662 | { | |
5663 | struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
5664 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
5665 | struct hwrm_func_qcfg_input req = {0}; | |
5666 | int rc; | |
5667 | ||
5668 | if (bp->hwrm_spec_code < 0x10601) | |
5669 | return 0; | |
5670 | ||
5671 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); | |
5672 | req.fid = cpu_to_le16(0xffff); | |
5673 | mutex_lock(&bp->hwrm_cmd_lock); | |
5674 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5675 | if (rc) { | |
5676 | mutex_unlock(&bp->hwrm_cmd_lock); | |
d4f1420d | 5677 | return rc; |
674f50a5 MC |
5678 | } |
5679 | ||
5680 | hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings); | |
f1ca94de | 5681 | if (BNXT_NEW_RM(bp)) { |
674f50a5 MC |
5682 | u16 cp, stats; |
5683 | ||
5684 | hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings); | |
5685 | hw_resc->resv_hw_ring_grps = | |
5686 | le32_to_cpu(resp->alloc_hw_ring_grps); | |
5687 | hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics); | |
5688 | cp = le16_to_cpu(resp->alloc_cmpl_rings); | |
5689 | stats = le16_to_cpu(resp->alloc_stat_ctx); | |
75720e63 | 5690 | hw_resc->resv_irqs = cp; |
41e8d798 MC |
5691 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5692 | int rx = hw_resc->resv_rx_rings; | |
5693 | int tx = hw_resc->resv_tx_rings; | |
5694 | ||
5695 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
5696 | rx >>= 1; | |
5697 | if (cp < (rx + tx)) { | |
5698 | bnxt_trim_rings(bp, &rx, &tx, cp, false); | |
5699 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
5700 | rx <<= 1; | |
5701 | hw_resc->resv_rx_rings = rx; | |
5702 | hw_resc->resv_tx_rings = tx; | |
5703 | } | |
75720e63 | 5704 | hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix); |
41e8d798 MC |
5705 | hw_resc->resv_hw_ring_grps = rx; |
5706 | } | |
674f50a5 | 5707 | hw_resc->resv_cp_rings = cp; |
780baad4 | 5708 | hw_resc->resv_stat_ctxs = stats; |
674f50a5 MC |
5709 | } |
5710 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5711 | return 0; | |
5712 | } | |
5713 | ||
391be5c2 MC |
5714 | /* Caller must hold bp->hwrm_cmd_lock */ |
5715 | int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings) | |
5716 | { | |
5717 | struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
5718 | struct hwrm_func_qcfg_input req = {0}; | |
5719 | int rc; | |
5720 | ||
5721 | if (bp->hwrm_spec_code < 0x10601) | |
5722 | return 0; | |
5723 | ||
5724 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); | |
5725 | req.fid = cpu_to_le16(fid); | |
5726 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5727 | if (!rc) | |
5728 | *tx_rings = le16_to_cpu(resp->alloc_tx_rings); | |
5729 | ||
5730 | return rc; | |
5731 | } | |
5732 | ||
41e8d798 MC |
5733 | static bool bnxt_rfs_supported(struct bnxt *bp); |
5734 | ||
4ed50ef4 MC |
5735 | static void |
5736 | __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req, | |
5737 | int tx_rings, int rx_rings, int ring_grps, | |
780baad4 | 5738 | int cp_rings, int stats, int vnics) |
391be5c2 | 5739 | { |
674f50a5 | 5740 | u32 enables = 0; |
391be5c2 | 5741 | |
4ed50ef4 MC |
5742 | bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1); |
5743 | req->fid = cpu_to_le16(0xffff); | |
674f50a5 | 5744 | enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; |
4ed50ef4 | 5745 | req->num_tx_rings = cpu_to_le16(tx_rings); |
f1ca94de | 5746 | if (BNXT_NEW_RM(bp)) { |
674f50a5 | 5747 | enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0; |
3f93cd3f | 5748 | enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; |
41e8d798 MC |
5749 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5750 | enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0; | |
5751 | enables |= tx_rings + ring_grps ? | |
3f93cd3f | 5752 | FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; |
41e8d798 MC |
5753 | enables |= rx_rings ? |
5754 | FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; | |
5755 | } else { | |
5756 | enables |= cp_rings ? | |
3f93cd3f | 5757 | FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; |
41e8d798 MC |
5758 | enables |= ring_grps ? |
5759 | FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS | | |
5760 | FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; | |
5761 | } | |
dbe80d44 | 5762 | enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0; |
674f50a5 | 5763 | |
4ed50ef4 | 5764 | req->num_rx_rings = cpu_to_le16(rx_rings); |
41e8d798 MC |
5765 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5766 | req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); | |
5767 | req->num_msix = cpu_to_le16(cp_rings); | |
5768 | req->num_rsscos_ctxs = | |
5769 | cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); | |
5770 | } else { | |
5771 | req->num_cmpl_rings = cpu_to_le16(cp_rings); | |
5772 | req->num_hw_ring_grps = cpu_to_le16(ring_grps); | |
5773 | req->num_rsscos_ctxs = cpu_to_le16(1); | |
5774 | if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) && | |
5775 | bnxt_rfs_supported(bp)) | |
5776 | req->num_rsscos_ctxs = | |
5777 | cpu_to_le16(ring_grps + 1); | |
5778 | } | |
780baad4 | 5779 | req->num_stat_ctxs = cpu_to_le16(stats); |
4ed50ef4 | 5780 | req->num_vnics = cpu_to_le16(vnics); |
674f50a5 | 5781 | } |
4ed50ef4 MC |
5782 | req->enables = cpu_to_le32(enables); |
5783 | } | |
5784 | ||
5785 | static void | |
5786 | __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, | |
5787 | struct hwrm_func_vf_cfg_input *req, int tx_rings, | |
5788 | int rx_rings, int ring_grps, int cp_rings, | |
780baad4 | 5789 | int stats, int vnics) |
4ed50ef4 MC |
5790 | { |
5791 | u32 enables = 0; | |
5792 | ||
5793 | bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1); | |
5794 | enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; | |
41e8d798 MC |
5795 | enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS | |
5796 | FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; | |
3f93cd3f | 5797 | enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; |
41e8d798 MC |
5798 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5799 | enables |= tx_rings + ring_grps ? | |
3f93cd3f | 5800 | FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; |
41e8d798 MC |
5801 | } else { |
5802 | enables |= cp_rings ? | |
3f93cd3f | 5803 | FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; |
41e8d798 MC |
5804 | enables |= ring_grps ? |
5805 | FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0; | |
5806 | } | |
4ed50ef4 | 5807 | enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0; |
41e8d798 | 5808 | enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS; |
4ed50ef4 | 5809 | |
41e8d798 | 5810 | req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX); |
4ed50ef4 MC |
5811 | req->num_tx_rings = cpu_to_le16(tx_rings); |
5812 | req->num_rx_rings = cpu_to_le16(rx_rings); | |
41e8d798 MC |
5813 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5814 | req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); | |
5815 | req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); | |
5816 | } else { | |
5817 | req->num_cmpl_rings = cpu_to_le16(cp_rings); | |
5818 | req->num_hw_ring_grps = cpu_to_le16(ring_grps); | |
5819 | req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX); | |
5820 | } | |
780baad4 | 5821 | req->num_stat_ctxs = cpu_to_le16(stats); |
4ed50ef4 MC |
5822 | req->num_vnics = cpu_to_le16(vnics); |
5823 | ||
5824 | req->enables = cpu_to_le32(enables); | |
5825 | } | |
5826 | ||
5827 | static int | |
5828 | bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, | |
780baad4 | 5829 | int ring_grps, int cp_rings, int stats, int vnics) |
4ed50ef4 MC |
5830 | { |
5831 | struct hwrm_func_cfg_input req = {0}; | |
5832 | int rc; | |
5833 | ||
5834 | __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, | |
780baad4 | 5835 | cp_rings, stats, vnics); |
4ed50ef4 | 5836 | if (!req.enables) |
391be5c2 MC |
5837 | return 0; |
5838 | ||
674f50a5 MC |
5839 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
5840 | if (rc) | |
d4f1420d | 5841 | return rc; |
674f50a5 MC |
5842 | |
5843 | if (bp->hwrm_spec_code < 0x10601) | |
5844 | bp->hw_resc.resv_tx_rings = tx_rings; | |
5845 | ||
5846 | rc = bnxt_hwrm_get_rings(bp); | |
5847 | return rc; | |
5848 | } | |
5849 | ||
5850 | static int | |
5851 | bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, | |
780baad4 | 5852 | int ring_grps, int cp_rings, int stats, int vnics) |
674f50a5 MC |
5853 | { |
5854 | struct hwrm_func_vf_cfg_input req = {0}; | |
674f50a5 MC |
5855 | int rc; |
5856 | ||
f1ca94de | 5857 | if (!BNXT_NEW_RM(bp)) { |
674f50a5 | 5858 | bp->hw_resc.resv_tx_rings = tx_rings; |
391be5c2 | 5859 | return 0; |
674f50a5 | 5860 | } |
391be5c2 | 5861 | |
4ed50ef4 | 5862 | __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, |
780baad4 | 5863 | cp_rings, stats, vnics); |
391be5c2 | 5864 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
674f50a5 | 5865 | if (rc) |
d4f1420d | 5866 | return rc; |
674f50a5 MC |
5867 | |
5868 | rc = bnxt_hwrm_get_rings(bp); | |
5869 | return rc; | |
5870 | } | |
5871 | ||
5872 | static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp, | |
780baad4 | 5873 | int cp, int stat, int vnic) |
674f50a5 MC |
5874 | { |
5875 | if (BNXT_PF(bp)) | |
780baad4 VV |
5876 | return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat, |
5877 | vnic); | |
674f50a5 | 5878 | else |
780baad4 VV |
5879 | return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat, |
5880 | vnic); | |
674f50a5 MC |
5881 | } |
5882 | ||
b16b6891 | 5883 | int bnxt_nq_rings_in_use(struct bnxt *bp) |
08654eb2 MC |
5884 | { |
5885 | int cp = bp->cp_nr_rings; | |
5886 | int ulp_msix, ulp_base; | |
5887 | ||
5888 | ulp_msix = bnxt_get_ulp_msix_num(bp); | |
5889 | if (ulp_msix) { | |
5890 | ulp_base = bnxt_get_ulp_msix_base(bp); | |
5891 | cp += ulp_msix; | |
5892 | if ((ulp_base + ulp_msix) > cp) | |
5893 | cp = ulp_base + ulp_msix; | |
5894 | } | |
5895 | return cp; | |
5896 | } | |
5897 | ||
c0b8cda0 MC |
5898 | static int bnxt_cp_rings_in_use(struct bnxt *bp) |
5899 | { | |
5900 | int cp; | |
5901 | ||
5902 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
5903 | return bnxt_nq_rings_in_use(bp); | |
5904 | ||
5905 | cp = bp->tx_nr_rings + bp->rx_nr_rings; | |
5906 | return cp; | |
5907 | } | |
5908 | ||
780baad4 VV |
5909 | static int bnxt_get_func_stat_ctxs(struct bnxt *bp) |
5910 | { | |
d77b1ad8 MC |
5911 | int ulp_stat = bnxt_get_ulp_stat_ctxs(bp); |
5912 | int cp = bp->cp_nr_rings; | |
5913 | ||
5914 | if (!ulp_stat) | |
5915 | return cp; | |
5916 | ||
5917 | if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp)) | |
5918 | return bnxt_get_ulp_msix_base(bp) + ulp_stat; | |
5919 | ||
5920 | return cp + ulp_stat; | |
780baad4 VV |
5921 | } |
5922 | ||
4e41dc5d MC |
5923 | static bool bnxt_need_reserve_rings(struct bnxt *bp) |
5924 | { | |
5925 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
fbcfc8e4 | 5926 | int cp = bnxt_cp_rings_in_use(bp); |
c0b8cda0 | 5927 | int nq = bnxt_nq_rings_in_use(bp); |
780baad4 | 5928 | int rx = bp->rx_nr_rings, stat; |
4e41dc5d MC |
5929 | int vnic = 1, grp = rx; |
5930 | ||
5931 | if (bp->hwrm_spec_code < 0x10601) | |
5932 | return false; | |
5933 | ||
5934 | if (hw_resc->resv_tx_rings != bp->tx_nr_rings) | |
5935 | return true; | |
5936 | ||
41e8d798 | 5937 | if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) |
4e41dc5d MC |
5938 | vnic = rx + 1; |
5939 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
5940 | rx <<= 1; | |
780baad4 | 5941 | stat = bnxt_get_func_stat_ctxs(bp); |
f1ca94de | 5942 | if (BNXT_NEW_RM(bp) && |
4e41dc5d | 5943 | (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp || |
01989c6b | 5944 | hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat || |
41e8d798 MC |
5945 | (hw_resc->resv_hw_ring_grps != grp && |
5946 | !(bp->flags & BNXT_FLAG_CHIP_P5)))) | |
4e41dc5d | 5947 | return true; |
01989c6b MC |
5948 | if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) && |
5949 | hw_resc->resv_irqs != nq) | |
5950 | return true; | |
4e41dc5d MC |
5951 | return false; |
5952 | } | |
5953 | ||
674f50a5 MC |
5954 | static int __bnxt_reserve_rings(struct bnxt *bp) |
5955 | { | |
5956 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
c0b8cda0 | 5957 | int cp = bnxt_nq_rings_in_use(bp); |
674f50a5 MC |
5958 | int tx = bp->tx_nr_rings; |
5959 | int rx = bp->rx_nr_rings; | |
674f50a5 | 5960 | int grp, rx_rings, rc; |
780baad4 | 5961 | int vnic = 1, stat; |
674f50a5 | 5962 | bool sh = false; |
674f50a5 | 5963 | |
4e41dc5d | 5964 | if (!bnxt_need_reserve_rings(bp)) |
674f50a5 MC |
5965 | return 0; |
5966 | ||
5967 | if (bp->flags & BNXT_FLAG_SHARED_RINGS) | |
5968 | sh = true; | |
41e8d798 | 5969 | if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) |
674f50a5 MC |
5970 | vnic = rx + 1; |
5971 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
5972 | rx <<= 1; | |
674f50a5 | 5973 | grp = bp->rx_nr_rings; |
780baad4 | 5974 | stat = bnxt_get_func_stat_ctxs(bp); |
674f50a5 | 5975 | |
780baad4 | 5976 | rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic); |
391be5c2 MC |
5977 | if (rc) |
5978 | return rc; | |
5979 | ||
674f50a5 | 5980 | tx = hw_resc->resv_tx_rings; |
f1ca94de | 5981 | if (BNXT_NEW_RM(bp)) { |
674f50a5 | 5982 | rx = hw_resc->resv_rx_rings; |
c0b8cda0 | 5983 | cp = hw_resc->resv_irqs; |
674f50a5 MC |
5984 | grp = hw_resc->resv_hw_ring_grps; |
5985 | vnic = hw_resc->resv_vnics; | |
780baad4 | 5986 | stat = hw_resc->resv_stat_ctxs; |
674f50a5 MC |
5987 | } |
5988 | ||
5989 | rx_rings = rx; | |
5990 | if (bp->flags & BNXT_FLAG_AGG_RINGS) { | |
5991 | if (rx >= 2) { | |
5992 | rx_rings = rx >> 1; | |
5993 | } else { | |
5994 | if (netif_running(bp->dev)) | |
5995 | return -ENOMEM; | |
5996 | ||
5997 | bp->flags &= ~BNXT_FLAG_AGG_RINGS; | |
5998 | bp->flags |= BNXT_FLAG_NO_AGG_RINGS; | |
5999 | bp->dev->hw_features &= ~NETIF_F_LRO; | |
6000 | bp->dev->features &= ~NETIF_F_LRO; | |
6001 | bnxt_set_ring_params(bp); | |
6002 | } | |
6003 | } | |
6004 | rx_rings = min_t(int, rx_rings, grp); | |
780baad4 VV |
6005 | cp = min_t(int, cp, bp->cp_nr_rings); |
6006 | if (stat > bnxt_get_ulp_stat_ctxs(bp)) | |
6007 | stat -= bnxt_get_ulp_stat_ctxs(bp); | |
6008 | cp = min_t(int, cp, stat); | |
674f50a5 MC |
6009 | rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh); |
6010 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
6011 | rx = rx_rings << 1; | |
6012 | cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings; | |
6013 | bp->tx_nr_rings = tx; | |
6014 | bp->rx_nr_rings = rx_rings; | |
6015 | bp->cp_nr_rings = cp; | |
6016 | ||
780baad4 | 6017 | if (!tx || !rx || !cp || !grp || !vnic || !stat) |
674f50a5 MC |
6018 | return -ENOMEM; |
6019 | ||
391be5c2 MC |
6020 | return rc; |
6021 | } | |
6022 | ||
8f23d638 | 6023 | static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, |
780baad4 VV |
6024 | int ring_grps, int cp_rings, int stats, |
6025 | int vnics) | |
98fdbe73 | 6026 | { |
8f23d638 | 6027 | struct hwrm_func_vf_cfg_input req = {0}; |
6fc2ffdf | 6028 | u32 flags; |
98fdbe73 MC |
6029 | int rc; |
6030 | ||
f1ca94de | 6031 | if (!BNXT_NEW_RM(bp)) |
98fdbe73 MC |
6032 | return 0; |
6033 | ||
6fc2ffdf | 6034 | __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, |
780baad4 | 6035 | cp_rings, stats, vnics); |
8f23d638 MC |
6036 | flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST | |
6037 | FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST | | |
6038 | FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | | |
8f23d638 | 6039 | FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | |
41e8d798 MC |
6040 | FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST | |
6041 | FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST; | |
6042 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
6043 | flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; | |
8f23d638 MC |
6044 | |
6045 | req.flags = cpu_to_le32(flags); | |
8f23d638 | 6046 | rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
d4f1420d | 6047 | return rc; |
8f23d638 MC |
6048 | } |
6049 | ||
6050 | static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, | |
780baad4 VV |
6051 | int ring_grps, int cp_rings, int stats, |
6052 | int vnics) | |
8f23d638 MC |
6053 | { |
6054 | struct hwrm_func_cfg_input req = {0}; | |
6fc2ffdf | 6055 | u32 flags; |
8f23d638 | 6056 | int rc; |
98fdbe73 | 6057 | |
6fc2ffdf | 6058 | __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, |
780baad4 | 6059 | cp_rings, stats, vnics); |
8f23d638 | 6060 | flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST; |
41e8d798 | 6061 | if (BNXT_NEW_RM(bp)) { |
8f23d638 MC |
6062 | flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST | |
6063 | FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | | |
8f23d638 MC |
6064 | FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | |
6065 | FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST; | |
41e8d798 | 6066 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
0b815023 MC |
6067 | flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST | |
6068 | FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST; | |
41e8d798 MC |
6069 | else |
6070 | flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; | |
6071 | } | |
6fc2ffdf | 6072 | |
8f23d638 | 6073 | req.flags = cpu_to_le32(flags); |
98fdbe73 | 6074 | rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
d4f1420d | 6075 | return rc; |
98fdbe73 MC |
6076 | } |
6077 | ||
8f23d638 | 6078 | static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings, |
780baad4 VV |
6079 | int ring_grps, int cp_rings, int stats, |
6080 | int vnics) | |
8f23d638 MC |
6081 | { |
6082 | if (bp->hwrm_spec_code < 0x10801) | |
6083 | return 0; | |
6084 | ||
6085 | if (BNXT_PF(bp)) | |
6086 | return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings, | |
780baad4 VV |
6087 | ring_grps, cp_rings, stats, |
6088 | vnics); | |
8f23d638 MC |
6089 | |
6090 | return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps, | |
780baad4 | 6091 | cp_rings, stats, vnics); |
8f23d638 MC |
6092 | } |
6093 | ||
74706afa MC |
6094 | static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp) |
6095 | { | |
6096 | struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
6097 | struct bnxt_coal_cap *coal_cap = &bp->coal_cap; | |
6098 | struct hwrm_ring_aggint_qcaps_input req = {0}; | |
6099 | int rc; | |
6100 | ||
6101 | coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS; | |
6102 | coal_cap->num_cmpl_dma_aggr_max = 63; | |
6103 | coal_cap->num_cmpl_dma_aggr_during_int_max = 63; | |
6104 | coal_cap->cmpl_aggr_dma_tmr_max = 65535; | |
6105 | coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535; | |
6106 | coal_cap->int_lat_tmr_min_max = 65535; | |
6107 | coal_cap->int_lat_tmr_max_max = 65535; | |
6108 | coal_cap->num_cmpl_aggr_int_max = 65535; | |
6109 | coal_cap->timer_units = 80; | |
6110 | ||
6111 | if (bp->hwrm_spec_code < 0x10902) | |
6112 | return; | |
6113 | ||
6114 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1); | |
6115 | mutex_lock(&bp->hwrm_cmd_lock); | |
6116 | rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
6117 | if (!rc) { | |
6118 | coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params); | |
58590c8d | 6119 | coal_cap->nq_params = le32_to_cpu(resp->nq_params); |
74706afa MC |
6120 | coal_cap->num_cmpl_dma_aggr_max = |
6121 | le16_to_cpu(resp->num_cmpl_dma_aggr_max); | |
6122 | coal_cap->num_cmpl_dma_aggr_during_int_max = | |
6123 | le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max); | |
6124 | coal_cap->cmpl_aggr_dma_tmr_max = | |
6125 | le16_to_cpu(resp->cmpl_aggr_dma_tmr_max); | |
6126 | coal_cap->cmpl_aggr_dma_tmr_during_int_max = | |
6127 | le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max); | |
6128 | coal_cap->int_lat_tmr_min_max = | |
6129 | le16_to_cpu(resp->int_lat_tmr_min_max); | |
6130 | coal_cap->int_lat_tmr_max_max = | |
6131 | le16_to_cpu(resp->int_lat_tmr_max_max); | |
6132 | coal_cap->num_cmpl_aggr_int_max = | |
6133 | le16_to_cpu(resp->num_cmpl_aggr_int_max); | |
6134 | coal_cap->timer_units = le16_to_cpu(resp->timer_units); | |
6135 | } | |
6136 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6137 | } | |
6138 | ||
6139 | static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec) | |
6140 | { | |
6141 | struct bnxt_coal_cap *coal_cap = &bp->coal_cap; | |
6142 | ||
6143 | return usec * 1000 / coal_cap->timer_units; | |
6144 | } | |
6145 | ||
6146 | static void bnxt_hwrm_set_coal_params(struct bnxt *bp, | |
6147 | struct bnxt_coal *hw_coal, | |
bb053f52 MC |
6148 | struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req) |
6149 | { | |
74706afa MC |
6150 | struct bnxt_coal_cap *coal_cap = &bp->coal_cap; |
6151 | u32 cmpl_params = coal_cap->cmpl_params; | |
6152 | u16 val, tmr, max, flags = 0; | |
f8503969 MC |
6153 | |
6154 | max = hw_coal->bufs_per_record * 128; | |
6155 | if (hw_coal->budget) | |
6156 | max = hw_coal->bufs_per_record * hw_coal->budget; | |
74706afa | 6157 | max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max); |
f8503969 MC |
6158 | |
6159 | val = clamp_t(u16, hw_coal->coal_bufs, 1, max); | |
6160 | req->num_cmpl_aggr_int = cpu_to_le16(val); | |
b153cbc5 | 6161 | |
74706afa | 6162 | val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max); |
f8503969 MC |
6163 | req->num_cmpl_dma_aggr = cpu_to_le16(val); |
6164 | ||
74706afa MC |
6165 | val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, |
6166 | coal_cap->num_cmpl_dma_aggr_during_int_max); | |
f8503969 MC |
6167 | req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val); |
6168 | ||
74706afa MC |
6169 | tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks); |
6170 | tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max); | |
f8503969 MC |
6171 | req->int_lat_tmr_max = cpu_to_le16(tmr); |
6172 | ||
6173 | /* min timer set to 1/2 of interrupt timer */ | |
74706afa MC |
6174 | if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) { |
6175 | val = tmr / 2; | |
6176 | val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max); | |
6177 | req->int_lat_tmr_min = cpu_to_le16(val); | |
6178 | req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); | |
6179 | } | |
f8503969 MC |
6180 | |
6181 | /* buf timer set to 1/4 of interrupt timer */ | |
74706afa | 6182 | val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max); |
f8503969 MC |
6183 | req->cmpl_aggr_dma_tmr = cpu_to_le16(val); |
6184 | ||
74706afa MC |
6185 | if (cmpl_params & |
6186 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) { | |
6187 | tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq); | |
6188 | val = clamp_t(u16, tmr, 1, | |
6189 | coal_cap->cmpl_aggr_dma_tmr_during_int_max); | |
6adc4601 | 6190 | req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val); |
74706afa MC |
6191 | req->enables |= |
6192 | cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE); | |
6193 | } | |
f8503969 | 6194 | |
74706afa MC |
6195 | if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET) |
6196 | flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; | |
6197 | if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) && | |
6198 | hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh) | |
f8503969 | 6199 | flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; |
bb053f52 | 6200 | req->flags = cpu_to_le16(flags); |
74706afa | 6201 | req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES); |
bb053f52 MC |
6202 | } |
6203 | ||
58590c8d MC |
6204 | /* Caller holds bp->hwrm_cmd_lock */ |
6205 | static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi, | |
6206 | struct bnxt_coal *hw_coal) | |
6207 | { | |
6208 | struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0}; | |
6209 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
6210 | struct bnxt_coal_cap *coal_cap = &bp->coal_cap; | |
6211 | u32 nq_params = coal_cap->nq_params; | |
6212 | u16 tmr; | |
6213 | ||
6214 | if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN)) | |
6215 | return 0; | |
6216 | ||
6217 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, | |
6218 | -1, -1); | |
6219 | req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id); | |
6220 | req.flags = | |
6221 | cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ); | |
6222 | ||
6223 | tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2; | |
6224 | tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max); | |
6225 | req.int_lat_tmr_min = cpu_to_le16(tmr); | |
6226 | req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); | |
6227 | return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
6228 | } | |
6229 | ||
6a8788f2 AG |
6230 | int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi) |
6231 | { | |
6232 | struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}; | |
6233 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
6234 | struct bnxt_coal coal; | |
6a8788f2 AG |
6235 | |
6236 | /* Tick values in micro seconds. | |
6237 | * 1 coal_buf x bufs_per_record = 1 completion record. | |
6238 | */ | |
6239 | memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal)); | |
6240 | ||
6241 | coal.coal_ticks = cpr->rx_ring_coal.coal_ticks; | |
6242 | coal.coal_bufs = cpr->rx_ring_coal.coal_bufs; | |
6243 | ||
6244 | if (!bnapi->rx_ring) | |
6245 | return -ENODEV; | |
6246 | ||
6247 | bnxt_hwrm_cmd_hdr_init(bp, &req_rx, | |
6248 | HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); | |
6249 | ||
74706afa | 6250 | bnxt_hwrm_set_coal_params(bp, &coal, &req_rx); |
6a8788f2 | 6251 | |
2c61d211 | 6252 | req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring)); |
6a8788f2 AG |
6253 | |
6254 | return hwrm_send_message(bp, &req_rx, sizeof(req_rx), | |
6255 | HWRM_CMD_TIMEOUT); | |
6256 | } | |
6257 | ||
c0c050c5 MC |
6258 | int bnxt_hwrm_set_coal(struct bnxt *bp) |
6259 | { | |
6260 | int i, rc = 0; | |
dfc9c94a MC |
6261 | struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}, |
6262 | req_tx = {0}, *req; | |
c0c050c5 | 6263 | |
dfc9c94a MC |
6264 | bnxt_hwrm_cmd_hdr_init(bp, &req_rx, |
6265 | HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); | |
6266 | bnxt_hwrm_cmd_hdr_init(bp, &req_tx, | |
6267 | HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); | |
c0c050c5 | 6268 | |
74706afa MC |
6269 | bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx); |
6270 | bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx); | |
c0c050c5 MC |
6271 | |
6272 | mutex_lock(&bp->hwrm_cmd_lock); | |
6273 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
dfc9c94a | 6274 | struct bnxt_napi *bnapi = bp->bnapi[i]; |
58590c8d | 6275 | struct bnxt_coal *hw_coal; |
2c61d211 | 6276 | u16 ring_id; |
c0c050c5 | 6277 | |
dfc9c94a | 6278 | req = &req_rx; |
2c61d211 MC |
6279 | if (!bnapi->rx_ring) { |
6280 | ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); | |
dfc9c94a | 6281 | req = &req_tx; |
2c61d211 MC |
6282 | } else { |
6283 | ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring); | |
6284 | } | |
6285 | req->ring_id = cpu_to_le16(ring_id); | |
dfc9c94a MC |
6286 | |
6287 | rc = _hwrm_send_message(bp, req, sizeof(*req), | |
c0c050c5 MC |
6288 | HWRM_CMD_TIMEOUT); |
6289 | if (rc) | |
6290 | break; | |
58590c8d MC |
6291 | |
6292 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
6293 | continue; | |
6294 | ||
6295 | if (bnapi->rx_ring && bnapi->tx_ring) { | |
6296 | req = &req_tx; | |
6297 | ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); | |
6298 | req->ring_id = cpu_to_le16(ring_id); | |
6299 | rc = _hwrm_send_message(bp, req, sizeof(*req), | |
6300 | HWRM_CMD_TIMEOUT); | |
6301 | if (rc) | |
6302 | break; | |
6303 | } | |
6304 | if (bnapi->rx_ring) | |
6305 | hw_coal = &bp->rx_coal; | |
6306 | else | |
6307 | hw_coal = &bp->tx_coal; | |
6308 | __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal); | |
c0c050c5 MC |
6309 | } |
6310 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6311 | return rc; | |
6312 | } | |
6313 | ||
6314 | static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp) | |
6315 | { | |
6316 | int rc = 0, i; | |
6317 | struct hwrm_stat_ctx_free_input req = {0}; | |
6318 | ||
6319 | if (!bp->bnapi) | |
6320 | return 0; | |
6321 | ||
3e8060fa PS |
6322 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) |
6323 | return 0; | |
6324 | ||
c0c050c5 MC |
6325 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1); |
6326 | ||
6327 | mutex_lock(&bp->hwrm_cmd_lock); | |
6328 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
6329 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
6330 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
6331 | ||
6332 | if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { | |
6333 | req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); | |
6334 | ||
6335 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
6336 | HWRM_CMD_TIMEOUT); | |
c0c050c5 MC |
6337 | |
6338 | cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; | |
6339 | } | |
6340 | } | |
6341 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6342 | return rc; | |
6343 | } | |
6344 | ||
6345 | static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) | |
6346 | { | |
6347 | int rc = 0, i; | |
6348 | struct hwrm_stat_ctx_alloc_input req = {0}; | |
6349 | struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
6350 | ||
3e8060fa PS |
6351 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) |
6352 | return 0; | |
6353 | ||
c0c050c5 MC |
6354 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1); |
6355 | ||
4e748506 | 6356 | req.stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size); |
51f30785 | 6357 | req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000); |
c0c050c5 MC |
6358 | |
6359 | mutex_lock(&bp->hwrm_cmd_lock); | |
6360 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
6361 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
6362 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
6363 | ||
6364 | req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map); | |
6365 | ||
6366 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
6367 | HWRM_CMD_TIMEOUT); | |
6368 | if (rc) | |
6369 | break; | |
6370 | ||
6371 | cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); | |
6372 | ||
6373 | bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; | |
6374 | } | |
6375 | mutex_unlock(&bp->hwrm_cmd_lock); | |
89aa8445 | 6376 | return rc; |
c0c050c5 MC |
6377 | } |
6378 | ||
cf6645f8 MC |
6379 | static int bnxt_hwrm_func_qcfg(struct bnxt *bp) |
6380 | { | |
6381 | struct hwrm_func_qcfg_input req = {0}; | |
567b2abe | 6382 | struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; |
9315edca | 6383 | u16 flags; |
cf6645f8 MC |
6384 | int rc; |
6385 | ||
6386 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); | |
6387 | req.fid = cpu_to_le16(0xffff); | |
6388 | mutex_lock(&bp->hwrm_cmd_lock); | |
6389 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
6390 | if (rc) | |
6391 | goto func_qcfg_exit; | |
6392 | ||
6393 | #ifdef CONFIG_BNXT_SRIOV | |
6394 | if (BNXT_VF(bp)) { | |
cf6645f8 MC |
6395 | struct bnxt_vf_info *vf = &bp->vf; |
6396 | ||
6397 | vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK; | |
230d1f0d MC |
6398 | } else { |
6399 | bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs); | |
cf6645f8 MC |
6400 | } |
6401 | #endif | |
9315edca MC |
6402 | flags = le16_to_cpu(resp->flags); |
6403 | if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED | | |
6404 | FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) { | |
97381a18 | 6405 | bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT; |
9315edca | 6406 | if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED) |
97381a18 | 6407 | bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT; |
9315edca MC |
6408 | } |
6409 | if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)) | |
6410 | bp->flags |= BNXT_FLAG_MULTI_HOST; | |
bc39f885 | 6411 | |
567b2abe SB |
6412 | switch (resp->port_partition_type) { |
6413 | case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0: | |
6414 | case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5: | |
6415 | case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0: | |
6416 | bp->port_partition_type = resp->port_partition_type; | |
6417 | break; | |
6418 | } | |
32e8239c MC |
6419 | if (bp->hwrm_spec_code < 0x10707 || |
6420 | resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB) | |
6421 | bp->br_mode = BRIDGE_MODE_VEB; | |
6422 | else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA) | |
6423 | bp->br_mode = BRIDGE_MODE_VEPA; | |
6424 | else | |
6425 | bp->br_mode = BRIDGE_MODE_UNDEF; | |
cf6645f8 | 6426 | |
7eb9bb3a MC |
6427 | bp->max_mtu = le16_to_cpu(resp->max_mtu_configured); |
6428 | if (!bp->max_mtu) | |
6429 | bp->max_mtu = BNXT_MAX_MTU; | |
6430 | ||
cf6645f8 MC |
6431 | func_qcfg_exit: |
6432 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6433 | return rc; | |
6434 | } | |
6435 | ||
98f04cf0 MC |
6436 | static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp) |
6437 | { | |
6438 | struct hwrm_func_backing_store_qcaps_input req = {0}; | |
6439 | struct hwrm_func_backing_store_qcaps_output *resp = | |
6440 | bp->hwrm_cmd_resp_addr; | |
6441 | int rc; | |
6442 | ||
6443 | if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx) | |
6444 | return 0; | |
6445 | ||
6446 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1); | |
6447 | mutex_lock(&bp->hwrm_cmd_lock); | |
6448 | rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
6449 | if (!rc) { | |
6450 | struct bnxt_ctx_pg_info *ctx_pg; | |
6451 | struct bnxt_ctx_mem_info *ctx; | |
6452 | int i; | |
6453 | ||
6454 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); | |
6455 | if (!ctx) { | |
6456 | rc = -ENOMEM; | |
6457 | goto ctx_err; | |
6458 | } | |
6459 | ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL); | |
6460 | if (!ctx_pg) { | |
6461 | kfree(ctx); | |
6462 | rc = -ENOMEM; | |
6463 | goto ctx_err; | |
6464 | } | |
6465 | for (i = 0; i < bp->max_q + 1; i++, ctx_pg++) | |
6466 | ctx->tqm_mem[i] = ctx_pg; | |
6467 | ||
6468 | bp->ctx = ctx; | |
6469 | ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries); | |
6470 | ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries); | |
6471 | ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries); | |
6472 | ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size); | |
6473 | ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries); | |
6474 | ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries); | |
6475 | ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size); | |
6476 | ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries); | |
6477 | ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries); | |
6478 | ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size); | |
6479 | ctx->vnic_max_vnic_entries = | |
6480 | le16_to_cpu(resp->vnic_max_vnic_entries); | |
6481 | ctx->vnic_max_ring_table_entries = | |
6482 | le16_to_cpu(resp->vnic_max_ring_table_entries); | |
6483 | ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size); | |
6484 | ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries); | |
6485 | ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size); | |
6486 | ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size); | |
6487 | ctx->tqm_min_entries_per_ring = | |
6488 | le32_to_cpu(resp->tqm_min_entries_per_ring); | |
6489 | ctx->tqm_max_entries_per_ring = | |
6490 | le32_to_cpu(resp->tqm_max_entries_per_ring); | |
6491 | ctx->tqm_entries_multiple = resp->tqm_entries_multiple; | |
6492 | if (!ctx->tqm_entries_multiple) | |
6493 | ctx->tqm_entries_multiple = 1; | |
6494 | ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries); | |
6495 | ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size); | |
53579e37 DS |
6496 | ctx->mrav_num_entries_units = |
6497 | le16_to_cpu(resp->mrav_num_entries_units); | |
98f04cf0 MC |
6498 | ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size); |
6499 | ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries); | |
3be8136c | 6500 | ctx->ctx_kind_initializer = resp->ctx_kind_initializer; |
98f04cf0 MC |
6501 | } else { |
6502 | rc = 0; | |
6503 | } | |
6504 | ctx_err: | |
6505 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6506 | return rc; | |
6507 | } | |
6508 | ||
1b9394e5 MC |
6509 | static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr, |
6510 | __le64 *pg_dir) | |
6511 | { | |
6512 | u8 pg_size = 0; | |
6513 | ||
6514 | if (BNXT_PAGE_SHIFT == 13) | |
6515 | pg_size = 1 << 4; | |
6516 | else if (BNXT_PAGE_SIZE == 16) | |
6517 | pg_size = 2 << 4; | |
6518 | ||
6519 | *pg_attr = pg_size; | |
08fe9d18 MC |
6520 | if (rmem->depth >= 1) { |
6521 | if (rmem->depth == 2) | |
6522 | *pg_attr |= 2; | |
6523 | else | |
6524 | *pg_attr |= 1; | |
1b9394e5 MC |
6525 | *pg_dir = cpu_to_le64(rmem->pg_tbl_map); |
6526 | } else { | |
6527 | *pg_dir = cpu_to_le64(rmem->dma_arr[0]); | |
6528 | } | |
6529 | } | |
6530 | ||
6531 | #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \ | |
6532 | (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \ | |
6533 | FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \ | |
6534 | FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \ | |
6535 | FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \ | |
6536 | FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) | |
6537 | ||
6538 | static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables) | |
6539 | { | |
6540 | struct hwrm_func_backing_store_cfg_input req = {0}; | |
6541 | struct bnxt_ctx_mem_info *ctx = bp->ctx; | |
6542 | struct bnxt_ctx_pg_info *ctx_pg; | |
6543 | __le32 *num_entries; | |
6544 | __le64 *pg_dir; | |
53579e37 | 6545 | u32 flags = 0; |
1b9394e5 MC |
6546 | u8 *pg_attr; |
6547 | int i, rc; | |
6548 | u32 ena; | |
6549 | ||
6550 | if (!ctx) | |
6551 | return 0; | |
6552 | ||
6553 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1); | |
6554 | req.enables = cpu_to_le32(enables); | |
6555 | ||
6556 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) { | |
6557 | ctx_pg = &ctx->qp_mem; | |
6558 | req.qp_num_entries = cpu_to_le32(ctx_pg->entries); | |
6559 | req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries); | |
6560 | req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries); | |
6561 | req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size); | |
6562 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6563 | &req.qpc_pg_size_qpc_lvl, | |
6564 | &req.qpc_page_dir); | |
6565 | } | |
6566 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) { | |
6567 | ctx_pg = &ctx->srq_mem; | |
6568 | req.srq_num_entries = cpu_to_le32(ctx_pg->entries); | |
6569 | req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries); | |
6570 | req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size); | |
6571 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6572 | &req.srq_pg_size_srq_lvl, | |
6573 | &req.srq_page_dir); | |
6574 | } | |
6575 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) { | |
6576 | ctx_pg = &ctx->cq_mem; | |
6577 | req.cq_num_entries = cpu_to_le32(ctx_pg->entries); | |
6578 | req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries); | |
6579 | req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size); | |
6580 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl, | |
6581 | &req.cq_page_dir); | |
6582 | } | |
6583 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) { | |
6584 | ctx_pg = &ctx->vnic_mem; | |
6585 | req.vnic_num_vnic_entries = | |
6586 | cpu_to_le16(ctx->vnic_max_vnic_entries); | |
6587 | req.vnic_num_ring_table_entries = | |
6588 | cpu_to_le16(ctx->vnic_max_ring_table_entries); | |
6589 | req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size); | |
6590 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6591 | &req.vnic_pg_size_vnic_lvl, | |
6592 | &req.vnic_page_dir); | |
6593 | } | |
6594 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) { | |
6595 | ctx_pg = &ctx->stat_mem; | |
6596 | req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries); | |
6597 | req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size); | |
6598 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6599 | &req.stat_pg_size_stat_lvl, | |
6600 | &req.stat_page_dir); | |
6601 | } | |
cf6daed0 MC |
6602 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) { |
6603 | ctx_pg = &ctx->mrav_mem; | |
6604 | req.mrav_num_entries = cpu_to_le32(ctx_pg->entries); | |
53579e37 DS |
6605 | if (ctx->mrav_num_entries_units) |
6606 | flags |= | |
6607 | FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT; | |
cf6daed0 MC |
6608 | req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size); |
6609 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6610 | &req.mrav_pg_size_mrav_lvl, | |
6611 | &req.mrav_page_dir); | |
6612 | } | |
6613 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) { | |
6614 | ctx_pg = &ctx->tim_mem; | |
6615 | req.tim_num_entries = cpu_to_le32(ctx_pg->entries); | |
6616 | req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size); | |
6617 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6618 | &req.tim_pg_size_tim_lvl, | |
6619 | &req.tim_page_dir); | |
6620 | } | |
1b9394e5 MC |
6621 | for (i = 0, num_entries = &req.tqm_sp_num_entries, |
6622 | pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl, | |
6623 | pg_dir = &req.tqm_sp_page_dir, | |
6624 | ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP; | |
6625 | i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) { | |
6626 | if (!(enables & ena)) | |
6627 | continue; | |
6628 | ||
6629 | req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size); | |
6630 | ctx_pg = ctx->tqm_mem[i]; | |
6631 | *num_entries = cpu_to_le32(ctx_pg->entries); | |
6632 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir); | |
6633 | } | |
53579e37 | 6634 | req.flags = cpu_to_le32(flags); |
1b9394e5 | 6635 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
1b9394e5 MC |
6636 | return rc; |
6637 | } | |
6638 | ||
98f04cf0 | 6639 | static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, |
08fe9d18 | 6640 | struct bnxt_ctx_pg_info *ctx_pg) |
98f04cf0 MC |
6641 | { |
6642 | struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; | |
6643 | ||
98f04cf0 MC |
6644 | rmem->page_size = BNXT_PAGE_SIZE; |
6645 | rmem->pg_arr = ctx_pg->ctx_pg_arr; | |
6646 | rmem->dma_arr = ctx_pg->ctx_dma_arr; | |
1b9394e5 | 6647 | rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; |
08fe9d18 MC |
6648 | if (rmem->depth >= 1) |
6649 | rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG; | |
98f04cf0 MC |
6650 | return bnxt_alloc_ring(bp, rmem); |
6651 | } | |
6652 | ||
08fe9d18 MC |
6653 | static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp, |
6654 | struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size, | |
3be8136c | 6655 | u8 depth, bool use_init_val) |
08fe9d18 MC |
6656 | { |
6657 | struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; | |
6658 | int rc; | |
6659 | ||
6660 | if (!mem_size) | |
6661 | return 0; | |
6662 | ||
6663 | ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); | |
6664 | if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) { | |
6665 | ctx_pg->nr_pages = 0; | |
6666 | return -EINVAL; | |
6667 | } | |
6668 | if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) { | |
6669 | int nr_tbls, i; | |
6670 | ||
6671 | rmem->depth = 2; | |
6672 | ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg), | |
6673 | GFP_KERNEL); | |
6674 | if (!ctx_pg->ctx_pg_tbl) | |
6675 | return -ENOMEM; | |
6676 | nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES); | |
6677 | rmem->nr_pages = nr_tbls; | |
6678 | rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); | |
6679 | if (rc) | |
6680 | return rc; | |
6681 | for (i = 0; i < nr_tbls; i++) { | |
6682 | struct bnxt_ctx_pg_info *pg_tbl; | |
6683 | ||
6684 | pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL); | |
6685 | if (!pg_tbl) | |
6686 | return -ENOMEM; | |
6687 | ctx_pg->ctx_pg_tbl[i] = pg_tbl; | |
6688 | rmem = &pg_tbl->ring_mem; | |
6689 | rmem->pg_tbl = ctx_pg->ctx_pg_arr[i]; | |
6690 | rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i]; | |
6691 | rmem->depth = 1; | |
6692 | rmem->nr_pages = MAX_CTX_PAGES; | |
3be8136c MC |
6693 | if (use_init_val) |
6694 | rmem->init_val = bp->ctx->ctx_kind_initializer; | |
6ef982de MC |
6695 | if (i == (nr_tbls - 1)) { |
6696 | int rem = ctx_pg->nr_pages % MAX_CTX_PAGES; | |
6697 | ||
6698 | if (rem) | |
6699 | rmem->nr_pages = rem; | |
6700 | } | |
08fe9d18 MC |
6701 | rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl); |
6702 | if (rc) | |
6703 | break; | |
6704 | } | |
6705 | } else { | |
6706 | rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); | |
6707 | if (rmem->nr_pages > 1 || depth) | |
6708 | rmem->depth = 1; | |
3be8136c MC |
6709 | if (use_init_val) |
6710 | rmem->init_val = bp->ctx->ctx_kind_initializer; | |
08fe9d18 MC |
6711 | rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); |
6712 | } | |
6713 | return rc; | |
6714 | } | |
6715 | ||
6716 | static void bnxt_free_ctx_pg_tbls(struct bnxt *bp, | |
6717 | struct bnxt_ctx_pg_info *ctx_pg) | |
6718 | { | |
6719 | struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; | |
6720 | ||
6721 | if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES || | |
6722 | ctx_pg->ctx_pg_tbl) { | |
6723 | int i, nr_tbls = rmem->nr_pages; | |
6724 | ||
6725 | for (i = 0; i < nr_tbls; i++) { | |
6726 | struct bnxt_ctx_pg_info *pg_tbl; | |
6727 | struct bnxt_ring_mem_info *rmem2; | |
6728 | ||
6729 | pg_tbl = ctx_pg->ctx_pg_tbl[i]; | |
6730 | if (!pg_tbl) | |
6731 | continue; | |
6732 | rmem2 = &pg_tbl->ring_mem; | |
6733 | bnxt_free_ring(bp, rmem2); | |
6734 | ctx_pg->ctx_pg_arr[i] = NULL; | |
6735 | kfree(pg_tbl); | |
6736 | ctx_pg->ctx_pg_tbl[i] = NULL; | |
6737 | } | |
6738 | kfree(ctx_pg->ctx_pg_tbl); | |
6739 | ctx_pg->ctx_pg_tbl = NULL; | |
6740 | } | |
6741 | bnxt_free_ring(bp, rmem); | |
6742 | ctx_pg->nr_pages = 0; | |
6743 | } | |
6744 | ||
98f04cf0 MC |
6745 | static void bnxt_free_ctx_mem(struct bnxt *bp) |
6746 | { | |
6747 | struct bnxt_ctx_mem_info *ctx = bp->ctx; | |
6748 | int i; | |
6749 | ||
6750 | if (!ctx) | |
6751 | return; | |
6752 | ||
6753 | if (ctx->tqm_mem[0]) { | |
6754 | for (i = 0; i < bp->max_q + 1; i++) | |
08fe9d18 | 6755 | bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]); |
98f04cf0 MC |
6756 | kfree(ctx->tqm_mem[0]); |
6757 | ctx->tqm_mem[0] = NULL; | |
6758 | } | |
6759 | ||
cf6daed0 MC |
6760 | bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem); |
6761 | bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem); | |
08fe9d18 MC |
6762 | bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem); |
6763 | bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem); | |
6764 | bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem); | |
6765 | bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem); | |
6766 | bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem); | |
98f04cf0 MC |
6767 | ctx->flags &= ~BNXT_CTX_FLAG_INITED; |
6768 | } | |
6769 | ||
6770 | static int bnxt_alloc_ctx_mem(struct bnxt *bp) | |
6771 | { | |
6772 | struct bnxt_ctx_pg_info *ctx_pg; | |
6773 | struct bnxt_ctx_mem_info *ctx; | |
1b9394e5 | 6774 | u32 mem_size, ena, entries; |
53579e37 | 6775 | u32 num_mr, num_ah; |
cf6daed0 MC |
6776 | u32 extra_srqs = 0; |
6777 | u32 extra_qps = 0; | |
6778 | u8 pg_lvl = 1; | |
98f04cf0 MC |
6779 | int i, rc; |
6780 | ||
6781 | rc = bnxt_hwrm_func_backing_store_qcaps(bp); | |
6782 | if (rc) { | |
6783 | netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n", | |
6784 | rc); | |
6785 | return rc; | |
6786 | } | |
6787 | ctx = bp->ctx; | |
6788 | if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) | |
6789 | return 0; | |
6790 | ||
d629522e | 6791 | if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) { |
cf6daed0 MC |
6792 | pg_lvl = 2; |
6793 | extra_qps = 65536; | |
6794 | extra_srqs = 8192; | |
6795 | } | |
6796 | ||
98f04cf0 | 6797 | ctx_pg = &ctx->qp_mem; |
cf6daed0 MC |
6798 | ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries + |
6799 | extra_qps; | |
98f04cf0 | 6800 | mem_size = ctx->qp_entry_size * ctx_pg->entries; |
3be8136c | 6801 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); |
98f04cf0 MC |
6802 | if (rc) |
6803 | return rc; | |
6804 | ||
6805 | ctx_pg = &ctx->srq_mem; | |
cf6daed0 | 6806 | ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs; |
98f04cf0 | 6807 | mem_size = ctx->srq_entry_size * ctx_pg->entries; |
3be8136c | 6808 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); |
98f04cf0 MC |
6809 | if (rc) |
6810 | return rc; | |
6811 | ||
6812 | ctx_pg = &ctx->cq_mem; | |
cf6daed0 | 6813 | ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2; |
98f04cf0 | 6814 | mem_size = ctx->cq_entry_size * ctx_pg->entries; |
3be8136c | 6815 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); |
98f04cf0 MC |
6816 | if (rc) |
6817 | return rc; | |
6818 | ||
6819 | ctx_pg = &ctx->vnic_mem; | |
6820 | ctx_pg->entries = ctx->vnic_max_vnic_entries + | |
6821 | ctx->vnic_max_ring_table_entries; | |
6822 | mem_size = ctx->vnic_entry_size * ctx_pg->entries; | |
3be8136c | 6823 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true); |
98f04cf0 MC |
6824 | if (rc) |
6825 | return rc; | |
6826 | ||
6827 | ctx_pg = &ctx->stat_mem; | |
6828 | ctx_pg->entries = ctx->stat_max_entries; | |
6829 | mem_size = ctx->stat_entry_size * ctx_pg->entries; | |
3be8136c | 6830 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true); |
98f04cf0 MC |
6831 | if (rc) |
6832 | return rc; | |
6833 | ||
cf6daed0 MC |
6834 | ena = 0; |
6835 | if (!(bp->flags & BNXT_FLAG_ROCE_CAP)) | |
6836 | goto skip_rdma; | |
6837 | ||
6838 | ctx_pg = &ctx->mrav_mem; | |
53579e37 DS |
6839 | /* 128K extra is needed to accommodate static AH context |
6840 | * allocation by f/w. | |
6841 | */ | |
6842 | num_mr = 1024 * 256; | |
6843 | num_ah = 1024 * 128; | |
6844 | ctx_pg->entries = num_mr + num_ah; | |
cf6daed0 | 6845 | mem_size = ctx->mrav_entry_size * ctx_pg->entries; |
3be8136c | 6846 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, true); |
cf6daed0 MC |
6847 | if (rc) |
6848 | return rc; | |
6849 | ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV; | |
53579e37 DS |
6850 | if (ctx->mrav_num_entries_units) |
6851 | ctx_pg->entries = | |
6852 | ((num_mr / ctx->mrav_num_entries_units) << 16) | | |
6853 | (num_ah / ctx->mrav_num_entries_units); | |
cf6daed0 MC |
6854 | |
6855 | ctx_pg = &ctx->tim_mem; | |
6856 | ctx_pg->entries = ctx->qp_mem.entries; | |
6857 | mem_size = ctx->tim_entry_size * ctx_pg->entries; | |
3be8136c | 6858 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false); |
cf6daed0 MC |
6859 | if (rc) |
6860 | return rc; | |
6861 | ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM; | |
6862 | ||
6863 | skip_rdma: | |
6864 | entries = ctx->qp_max_l2_entries + extra_qps; | |
98f04cf0 MC |
6865 | entries = roundup(entries, ctx->tqm_entries_multiple); |
6866 | entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring, | |
6867 | ctx->tqm_max_entries_per_ring); | |
cf6daed0 | 6868 | for (i = 0; i < bp->max_q + 1; i++) { |
98f04cf0 MC |
6869 | ctx_pg = ctx->tqm_mem[i]; |
6870 | ctx_pg->entries = entries; | |
6871 | mem_size = ctx->tqm_entry_size * entries; | |
3be8136c | 6872 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false); |
98f04cf0 MC |
6873 | if (rc) |
6874 | return rc; | |
1b9394e5 | 6875 | ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i; |
98f04cf0 | 6876 | } |
1b9394e5 MC |
6877 | ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES; |
6878 | rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); | |
6879 | if (rc) | |
6880 | netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n", | |
6881 | rc); | |
6882 | else | |
6883 | ctx->flags |= BNXT_CTX_FLAG_INITED; | |
6884 | ||
98f04cf0 MC |
6885 | return 0; |
6886 | } | |
6887 | ||
db4723b3 | 6888 | int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all) |
be0dd9c4 MC |
6889 | { |
6890 | struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
6891 | struct hwrm_func_resource_qcaps_input req = {0}; | |
6892 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
6893 | int rc; | |
6894 | ||
6895 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1); | |
6896 | req.fid = cpu_to_le16(0xffff); | |
6897 | ||
6898 | mutex_lock(&bp->hwrm_cmd_lock); | |
351cbde9 JT |
6899 | rc = _hwrm_send_message_silent(bp, &req, sizeof(req), |
6900 | HWRM_CMD_TIMEOUT); | |
d4f1420d | 6901 | if (rc) |
be0dd9c4 | 6902 | goto hwrm_func_resc_qcaps_exit; |
be0dd9c4 | 6903 | |
db4723b3 MC |
6904 | hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs); |
6905 | if (!all) | |
6906 | goto hwrm_func_resc_qcaps_exit; | |
6907 | ||
be0dd9c4 MC |
6908 | hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx); |
6909 | hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); | |
6910 | hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings); | |
6911 | hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); | |
6912 | hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings); | |
6913 | hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); | |
6914 | hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings); | |
6915 | hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); | |
6916 | hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps); | |
6917 | hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps); | |
6918 | hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs); | |
6919 | hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); | |
6920 | hw_resc->min_vnics = le16_to_cpu(resp->min_vnics); | |
6921 | hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); | |
6922 | hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx); | |
6923 | hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); | |
6924 | ||
9c1fabdf MC |
6925 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
6926 | u16 max_msix = le16_to_cpu(resp->max_msix); | |
6927 | ||
f7588cd8 | 6928 | hw_resc->max_nqs = max_msix; |
9c1fabdf MC |
6929 | hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings; |
6930 | } | |
6931 | ||
4673d664 MC |
6932 | if (BNXT_PF(bp)) { |
6933 | struct bnxt_pf_info *pf = &bp->pf; | |
6934 | ||
6935 | pf->vf_resv_strategy = | |
6936 | le16_to_cpu(resp->vf_reservation_strategy); | |
bf82736d | 6937 | if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC) |
4673d664 MC |
6938 | pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL; |
6939 | } | |
be0dd9c4 MC |
6940 | hwrm_func_resc_qcaps_exit: |
6941 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6942 | return rc; | |
6943 | } | |
6944 | ||
6945 | static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) | |
c0c050c5 MC |
6946 | { |
6947 | int rc = 0; | |
6948 | struct hwrm_func_qcaps_input req = {0}; | |
6949 | struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
6a4f2947 MC |
6950 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; |
6951 | u32 flags; | |
c0c050c5 MC |
6952 | |
6953 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1); | |
6954 | req.fid = cpu_to_le16(0xffff); | |
6955 | ||
6956 | mutex_lock(&bp->hwrm_cmd_lock); | |
6957 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
6958 | if (rc) | |
6959 | goto hwrm_func_qcaps_exit; | |
6960 | ||
6a4f2947 MC |
6961 | flags = le32_to_cpu(resp->flags); |
6962 | if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED) | |
e4060d30 | 6963 | bp->flags |= BNXT_FLAG_ROCEV1_CAP; |
6a4f2947 | 6964 | if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED) |
e4060d30 | 6965 | bp->flags |= BNXT_FLAG_ROCEV2_CAP; |
55e4398d VV |
6966 | if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED) |
6967 | bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED; | |
0a3f4e4f VV |
6968 | if (flags & FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE) |
6969 | bp->fw_cap |= BNXT_FW_CAP_HOT_RESET; | |
6154532f VV |
6970 | if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED) |
6971 | bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED; | |
07f83d72 MC |
6972 | if (flags & FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE) |
6973 | bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY; | |
4037eb71 VV |
6974 | if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD) |
6975 | bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD; | |
e4060d30 | 6976 | |
7cc5a20e | 6977 | bp->tx_push_thresh = 0; |
6a4f2947 | 6978 | if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) |
7cc5a20e MC |
6979 | bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; |
6980 | ||
6a4f2947 MC |
6981 | hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); |
6982 | hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); | |
6983 | hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); | |
6984 | hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); | |
6985 | hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); | |
6986 | if (!hw_resc->max_hw_ring_grps) | |
6987 | hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings; | |
6988 | hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); | |
6989 | hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); | |
6990 | hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); | |
6991 | ||
c0c050c5 MC |
6992 | if (BNXT_PF(bp)) { |
6993 | struct bnxt_pf_info *pf = &bp->pf; | |
6994 | ||
6995 | pf->fw_fid = le16_to_cpu(resp->fid); | |
6996 | pf->port_id = le16_to_cpu(resp->port_id); | |
11f15ed3 | 6997 | memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN); |
c0c050c5 MC |
6998 | pf->first_vf_id = le16_to_cpu(resp->first_vf_id); |
6999 | pf->max_vfs = le16_to_cpu(resp->max_vfs); | |
7000 | pf->max_encap_records = le32_to_cpu(resp->max_encap_records); | |
7001 | pf->max_decap_records = le32_to_cpu(resp->max_decap_records); | |
7002 | pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); | |
7003 | pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); | |
7004 | pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); | |
7005 | pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); | |
ba642ab7 | 7006 | bp->flags &= ~BNXT_FLAG_WOL_CAP; |
6a4f2947 | 7007 | if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED) |
c1ef146a | 7008 | bp->flags |= BNXT_FLAG_WOL_CAP; |
c0c050c5 | 7009 | } else { |
379a80a1 | 7010 | #ifdef CONFIG_BNXT_SRIOV |
c0c050c5 MC |
7011 | struct bnxt_vf_info *vf = &bp->vf; |
7012 | ||
7013 | vf->fw_fid = le16_to_cpu(resp->fid); | |
7cc5a20e | 7014 | memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN); |
379a80a1 | 7015 | #endif |
c0c050c5 MC |
7016 | } |
7017 | ||
c0c050c5 MC |
7018 | hwrm_func_qcaps_exit: |
7019 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7020 | return rc; | |
7021 | } | |
7022 | ||
804fba4e MC |
7023 | static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp); |
7024 | ||
be0dd9c4 MC |
7025 | static int bnxt_hwrm_func_qcaps(struct bnxt *bp) |
7026 | { | |
7027 | int rc; | |
7028 | ||
7029 | rc = __bnxt_hwrm_func_qcaps(bp); | |
7030 | if (rc) | |
7031 | return rc; | |
804fba4e MC |
7032 | rc = bnxt_hwrm_queue_qportcfg(bp); |
7033 | if (rc) { | |
7034 | netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc); | |
7035 | return rc; | |
7036 | } | |
be0dd9c4 | 7037 | if (bp->hwrm_spec_code >= 0x10803) { |
98f04cf0 MC |
7038 | rc = bnxt_alloc_ctx_mem(bp); |
7039 | if (rc) | |
7040 | return rc; | |
db4723b3 | 7041 | rc = bnxt_hwrm_func_resc_qcaps(bp, true); |
be0dd9c4 | 7042 | if (!rc) |
97381a18 | 7043 | bp->fw_cap |= BNXT_FW_CAP_NEW_RM; |
be0dd9c4 MC |
7044 | } |
7045 | return 0; | |
7046 | } | |
7047 | ||
e969ae5b MC |
7048 | static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp) |
7049 | { | |
7050 | struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0}; | |
7051 | struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp; | |
7052 | int rc = 0; | |
7053 | u32 flags; | |
7054 | ||
7055 | if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW)) | |
7056 | return 0; | |
7057 | ||
7058 | resp = bp->hwrm_cmd_resp_addr; | |
7059 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1); | |
7060 | ||
7061 | mutex_lock(&bp->hwrm_cmd_lock); | |
7062 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7063 | if (rc) | |
7064 | goto hwrm_cfa_adv_qcaps_exit; | |
7065 | ||
7066 | flags = le32_to_cpu(resp->flags); | |
7067 | if (flags & | |
41136ab3 MC |
7068 | CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED) |
7069 | bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2; | |
e969ae5b MC |
7070 | |
7071 | hwrm_cfa_adv_qcaps_exit: | |
7072 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7073 | return rc; | |
7074 | } | |
7075 | ||
9ffbd677 MC |
7076 | static int bnxt_map_fw_health_regs(struct bnxt *bp) |
7077 | { | |
7078 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
7079 | u32 reg_base = 0xffffffff; | |
7080 | int i; | |
7081 | ||
7082 | /* Only pre-map the monitoring GRC registers using window 3 */ | |
7083 | for (i = 0; i < 4; i++) { | |
7084 | u32 reg = fw_health->regs[i]; | |
7085 | ||
7086 | if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC) | |
7087 | continue; | |
7088 | if (reg_base == 0xffffffff) | |
7089 | reg_base = reg & BNXT_GRC_BASE_MASK; | |
7090 | if ((reg & BNXT_GRC_BASE_MASK) != reg_base) | |
7091 | return -ERANGE; | |
7092 | fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_BASE + | |
7093 | (reg & BNXT_GRC_OFFSET_MASK); | |
7094 | } | |
7095 | if (reg_base == 0xffffffff) | |
7096 | return 0; | |
7097 | ||
7098 | writel(reg_base, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + | |
7099 | BNXT_FW_HEALTH_WIN_MAP_OFF); | |
7100 | return 0; | |
7101 | } | |
7102 | ||
07f83d72 MC |
7103 | static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp) |
7104 | { | |
7105 | struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
7106 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
7107 | struct hwrm_error_recovery_qcfg_input req = {0}; | |
7108 | int rc, i; | |
7109 | ||
7110 | if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) | |
7111 | return 0; | |
7112 | ||
7113 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_ERROR_RECOVERY_QCFG, -1, -1); | |
7114 | mutex_lock(&bp->hwrm_cmd_lock); | |
7115 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7116 | if (rc) | |
7117 | goto err_recovery_out; | |
07f83d72 MC |
7118 | fw_health->flags = le32_to_cpu(resp->flags); |
7119 | if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) && | |
7120 | !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) { | |
7121 | rc = -EINVAL; | |
7122 | goto err_recovery_out; | |
7123 | } | |
7124 | fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq); | |
7125 | fw_health->master_func_wait_dsecs = | |
7126 | le32_to_cpu(resp->master_func_wait_period); | |
7127 | fw_health->normal_func_wait_dsecs = | |
7128 | le32_to_cpu(resp->normal_func_wait_period); | |
7129 | fw_health->post_reset_wait_dsecs = | |
7130 | le32_to_cpu(resp->master_func_wait_period_after_reset); | |
7131 | fw_health->post_reset_max_wait_dsecs = | |
7132 | le32_to_cpu(resp->max_bailout_time_after_reset); | |
7133 | fw_health->regs[BNXT_FW_HEALTH_REG] = | |
7134 | le32_to_cpu(resp->fw_health_status_reg); | |
7135 | fw_health->regs[BNXT_FW_HEARTBEAT_REG] = | |
7136 | le32_to_cpu(resp->fw_heartbeat_reg); | |
7137 | fw_health->regs[BNXT_FW_RESET_CNT_REG] = | |
7138 | le32_to_cpu(resp->fw_reset_cnt_reg); | |
7139 | fw_health->regs[BNXT_FW_RESET_INPROG_REG] = | |
7140 | le32_to_cpu(resp->reset_inprogress_reg); | |
7141 | fw_health->fw_reset_inprog_reg_mask = | |
7142 | le32_to_cpu(resp->reset_inprogress_reg_mask); | |
7143 | fw_health->fw_reset_seq_cnt = resp->reg_array_cnt; | |
7144 | if (fw_health->fw_reset_seq_cnt >= 16) { | |
7145 | rc = -EINVAL; | |
7146 | goto err_recovery_out; | |
7147 | } | |
7148 | for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) { | |
7149 | fw_health->fw_reset_seq_regs[i] = | |
7150 | le32_to_cpu(resp->reset_reg[i]); | |
7151 | fw_health->fw_reset_seq_vals[i] = | |
7152 | le32_to_cpu(resp->reset_reg_val[i]); | |
7153 | fw_health->fw_reset_seq_delay_msec[i] = | |
7154 | resp->delay_after_reset[i]; | |
7155 | } | |
7156 | err_recovery_out: | |
7157 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9ffbd677 MC |
7158 | if (!rc) |
7159 | rc = bnxt_map_fw_health_regs(bp); | |
07f83d72 MC |
7160 | if (rc) |
7161 | bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; | |
7162 | return rc; | |
7163 | } | |
7164 | ||
c0c050c5 MC |
7165 | static int bnxt_hwrm_func_reset(struct bnxt *bp) |
7166 | { | |
7167 | struct hwrm_func_reset_input req = {0}; | |
7168 | ||
7169 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1); | |
7170 | req.enables = 0; | |
7171 | ||
7172 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT); | |
7173 | } | |
7174 | ||
7175 | static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) | |
7176 | { | |
7177 | int rc = 0; | |
7178 | struct hwrm_queue_qportcfg_input req = {0}; | |
7179 | struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
aabfc016 MC |
7180 | u8 i, j, *qptr; |
7181 | bool no_rdma; | |
c0c050c5 MC |
7182 | |
7183 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1); | |
7184 | ||
7185 | mutex_lock(&bp->hwrm_cmd_lock); | |
7186 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7187 | if (rc) | |
7188 | goto qportcfg_exit; | |
7189 | ||
7190 | if (!resp->max_configurable_queues) { | |
7191 | rc = -EINVAL; | |
7192 | goto qportcfg_exit; | |
7193 | } | |
7194 | bp->max_tc = resp->max_configurable_queues; | |
87c374de | 7195 | bp->max_lltc = resp->max_configurable_lossless_queues; |
c0c050c5 MC |
7196 | if (bp->max_tc > BNXT_MAX_QUEUE) |
7197 | bp->max_tc = BNXT_MAX_QUEUE; | |
7198 | ||
aabfc016 MC |
7199 | no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP); |
7200 | qptr = &resp->queue_id0; | |
7201 | for (i = 0, j = 0; i < bp->max_tc; i++) { | |
98f04cf0 MC |
7202 | bp->q_info[j].queue_id = *qptr; |
7203 | bp->q_ids[i] = *qptr++; | |
aabfc016 MC |
7204 | bp->q_info[j].queue_profile = *qptr++; |
7205 | bp->tc_to_qidx[j] = j; | |
7206 | if (!BNXT_CNPQ(bp->q_info[j].queue_profile) || | |
7207 | (no_rdma && BNXT_PF(bp))) | |
7208 | j++; | |
7209 | } | |
98f04cf0 | 7210 | bp->max_q = bp->max_tc; |
aabfc016 MC |
7211 | bp->max_tc = max_t(u8, j, 1); |
7212 | ||
441cabbb MC |
7213 | if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) |
7214 | bp->max_tc = 1; | |
7215 | ||
87c374de MC |
7216 | if (bp->max_lltc > bp->max_tc) |
7217 | bp->max_lltc = bp->max_tc; | |
7218 | ||
c0c050c5 MC |
7219 | qportcfg_exit: |
7220 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7221 | return rc; | |
7222 | } | |
7223 | ||
ba642ab7 | 7224 | static int __bnxt_hwrm_ver_get(struct bnxt *bp, bool silent) |
c0c050c5 | 7225 | { |
c0c050c5 | 7226 | struct hwrm_ver_get_input req = {0}; |
ba642ab7 | 7227 | int rc; |
c0c050c5 MC |
7228 | |
7229 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1); | |
7230 | req.hwrm_intf_maj = HWRM_VERSION_MAJOR; | |
7231 | req.hwrm_intf_min = HWRM_VERSION_MINOR; | |
7232 | req.hwrm_intf_upd = HWRM_VERSION_UPDATE; | |
ba642ab7 MC |
7233 | |
7234 | rc = bnxt_hwrm_do_send_msg(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT, | |
7235 | silent); | |
7236 | return rc; | |
7237 | } | |
7238 | ||
7239 | static int bnxt_hwrm_ver_get(struct bnxt *bp) | |
7240 | { | |
7241 | struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr; | |
7242 | u32 dev_caps_cfg; | |
7243 | int rc; | |
7244 | ||
7245 | bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN; | |
c0c050c5 | 7246 | mutex_lock(&bp->hwrm_cmd_lock); |
ba642ab7 | 7247 | rc = __bnxt_hwrm_ver_get(bp, false); |
c0c050c5 MC |
7248 | if (rc) |
7249 | goto hwrm_ver_get_exit; | |
7250 | ||
7251 | memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); | |
7252 | ||
894aa69a MC |
7253 | bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 | |
7254 | resp->hwrm_intf_min_8b << 8 | | |
7255 | resp->hwrm_intf_upd_8b; | |
7256 | if (resp->hwrm_intf_maj_8b < 1) { | |
c193554e | 7257 | netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", |
894aa69a MC |
7258 | resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, |
7259 | resp->hwrm_intf_upd_8b); | |
c193554e | 7260 | netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); |
c0c050c5 | 7261 | } |
431aa1eb | 7262 | snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d", |
894aa69a MC |
7263 | resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b, |
7264 | resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b); | |
c0c050c5 | 7265 | |
691aa620 VV |
7266 | if (strlen(resp->active_pkg_name)) { |
7267 | int fw_ver_len = strlen(bp->fw_ver_str); | |
7268 | ||
7269 | snprintf(bp->fw_ver_str + fw_ver_len, | |
7270 | FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s", | |
7271 | resp->active_pkg_name); | |
7272 | bp->fw_cap |= BNXT_FW_CAP_PKG_VER; | |
7273 | } | |
7274 | ||
ff4fe81d MC |
7275 | bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout); |
7276 | if (!bp->hwrm_cmd_timeout) | |
7277 | bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; | |
7278 | ||
1dfddc41 | 7279 | if (resp->hwrm_intf_maj_8b >= 1) { |
e6ef2699 | 7280 | bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len); |
1dfddc41 MC |
7281 | bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len); |
7282 | } | |
7283 | if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN) | |
7284 | bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN; | |
e6ef2699 | 7285 | |
659c805c | 7286 | bp->chip_num = le16_to_cpu(resp->chip_num); |
5313845f | 7287 | bp->chip_rev = resp->chip_rev; |
3e8060fa PS |
7288 | if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev && |
7289 | !resp->chip_metal) | |
7290 | bp->flags |= BNXT_FLAG_CHIP_NITRO_A0; | |
659c805c | 7291 | |
e605db80 DK |
7292 | dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg); |
7293 | if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && | |
7294 | (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) | |
97381a18 | 7295 | bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD; |
e605db80 | 7296 | |
760b6d33 VD |
7297 | if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) |
7298 | bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL; | |
7299 | ||
abd43a13 VD |
7300 | if (dev_caps_cfg & |
7301 | VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED) | |
7302 | bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE; | |
7303 | ||
2a516444 MC |
7304 | if (dev_caps_cfg & |
7305 | VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED) | |
7306 | bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF; | |
7307 | ||
e969ae5b MC |
7308 | if (dev_caps_cfg & |
7309 | VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) | |
7310 | bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW; | |
7311 | ||
c0c050c5 MC |
7312 | hwrm_ver_get_exit: |
7313 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7314 | return rc; | |
7315 | } | |
7316 | ||
5ac67d8b RS |
7317 | int bnxt_hwrm_fw_set_time(struct bnxt *bp) |
7318 | { | |
7319 | struct hwrm_fw_set_time_input req = {0}; | |
7dfaa7bc AB |
7320 | struct tm tm; |
7321 | time64_t now = ktime_get_real_seconds(); | |
5ac67d8b | 7322 | |
ca2c39e2 MC |
7323 | if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) || |
7324 | bp->hwrm_spec_code < 0x10400) | |
5ac67d8b RS |
7325 | return -EOPNOTSUPP; |
7326 | ||
7dfaa7bc | 7327 | time64_to_tm(now, 0, &tm); |
5ac67d8b RS |
7328 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1); |
7329 | req.year = cpu_to_le16(1900 + tm.tm_year); | |
7330 | req.month = 1 + tm.tm_mon; | |
7331 | req.day = tm.tm_mday; | |
7332 | req.hour = tm.tm_hour; | |
7333 | req.minute = tm.tm_min; | |
7334 | req.second = tm.tm_sec; | |
7335 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7336 | } | |
7337 | ||
3bdf56c4 MC |
7338 | static int bnxt_hwrm_port_qstats(struct bnxt *bp) |
7339 | { | |
7340 | int rc; | |
7341 | struct bnxt_pf_info *pf = &bp->pf; | |
7342 | struct hwrm_port_qstats_input req = {0}; | |
7343 | ||
7344 | if (!(bp->flags & BNXT_FLAG_PORT_STATS)) | |
7345 | return 0; | |
7346 | ||
7347 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1); | |
7348 | req.port_id = cpu_to_le16(pf->port_id); | |
7349 | req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map); | |
7350 | req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map); | |
7351 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7352 | return rc; | |
7353 | } | |
7354 | ||
00db3cba VV |
7355 | static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp) |
7356 | { | |
36e53349 | 7357 | struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr; |
e37fed79 | 7358 | struct hwrm_queue_pri2cos_qcfg_input req2 = {0}; |
00db3cba VV |
7359 | struct hwrm_port_qstats_ext_input req = {0}; |
7360 | struct bnxt_pf_info *pf = &bp->pf; | |
ad361adf | 7361 | u32 tx_stat_size; |
36e53349 | 7362 | int rc; |
00db3cba VV |
7363 | |
7364 | if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) | |
7365 | return 0; | |
7366 | ||
7367 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1); | |
7368 | req.port_id = cpu_to_le16(pf->port_id); | |
7369 | req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext)); | |
7370 | req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map); | |
ad361adf MC |
7371 | tx_stat_size = bp->hw_tx_port_stats_ext ? |
7372 | sizeof(*bp->hw_tx_port_stats_ext) : 0; | |
7373 | req.tx_stat_size = cpu_to_le16(tx_stat_size); | |
36e53349 MC |
7374 | req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map); |
7375 | mutex_lock(&bp->hwrm_cmd_lock); | |
7376 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7377 | if (!rc) { | |
7378 | bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8; | |
ad361adf MC |
7379 | bp->fw_tx_stats_ext_size = tx_stat_size ? |
7380 | le16_to_cpu(resp->tx_stat_size) / 8 : 0; | |
36e53349 MC |
7381 | } else { |
7382 | bp->fw_rx_stats_ext_size = 0; | |
7383 | bp->fw_tx_stats_ext_size = 0; | |
7384 | } | |
e37fed79 MC |
7385 | if (bp->fw_tx_stats_ext_size <= |
7386 | offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) { | |
7387 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7388 | bp->pri2cos_valid = 0; | |
7389 | return rc; | |
7390 | } | |
7391 | ||
7392 | bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1); | |
7393 | req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN); | |
7394 | ||
7395 | rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT); | |
7396 | if (!rc) { | |
7397 | struct hwrm_queue_pri2cos_qcfg_output *resp2; | |
7398 | u8 *pri2cos; | |
7399 | int i, j; | |
7400 | ||
7401 | resp2 = bp->hwrm_cmd_resp_addr; | |
7402 | pri2cos = &resp2->pri0_cos_queue_id; | |
7403 | for (i = 0; i < 8; i++) { | |
7404 | u8 queue_id = pri2cos[i]; | |
7405 | ||
7406 | for (j = 0; j < bp->max_q; j++) { | |
7407 | if (bp->q_ids[j] == queue_id) | |
7408 | bp->pri2cos[i] = j; | |
7409 | } | |
7410 | } | |
7411 | bp->pri2cos_valid = 1; | |
7412 | } | |
36e53349 MC |
7413 | mutex_unlock(&bp->hwrm_cmd_lock); |
7414 | return rc; | |
00db3cba VV |
7415 | } |
7416 | ||
55e4398d VV |
7417 | static int bnxt_hwrm_pcie_qstats(struct bnxt *bp) |
7418 | { | |
7419 | struct hwrm_pcie_qstats_input req = {0}; | |
7420 | ||
7421 | if (!(bp->flags & BNXT_FLAG_PCIE_STATS)) | |
7422 | return 0; | |
7423 | ||
7424 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1); | |
7425 | req.pcie_stat_size = cpu_to_le16(sizeof(struct pcie_ctx_hw_stats)); | |
7426 | req.pcie_stat_host_addr = cpu_to_le64(bp->hw_pcie_stats_map); | |
7427 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7428 | } | |
7429 | ||
c0c050c5 MC |
7430 | static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) |
7431 | { | |
7432 | if (bp->vxlan_port_cnt) { | |
7433 | bnxt_hwrm_tunnel_dst_port_free( | |
7434 | bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); | |
7435 | } | |
7436 | bp->vxlan_port_cnt = 0; | |
7437 | if (bp->nge_port_cnt) { | |
7438 | bnxt_hwrm_tunnel_dst_port_free( | |
7439 | bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); | |
7440 | } | |
7441 | bp->nge_port_cnt = 0; | |
7442 | } | |
7443 | ||
7444 | static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) | |
7445 | { | |
7446 | int rc, i; | |
7447 | u32 tpa_flags = 0; | |
7448 | ||
7449 | if (set_tpa) | |
7450 | tpa_flags = bp->flags & BNXT_FLAG_TPA; | |
b4fff207 MC |
7451 | else if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) |
7452 | return 0; | |
c0c050c5 MC |
7453 | for (i = 0; i < bp->nr_vnics; i++) { |
7454 | rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); | |
7455 | if (rc) { | |
7456 | netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", | |
23e12c89 | 7457 | i, rc); |
c0c050c5 MC |
7458 | return rc; |
7459 | } | |
7460 | } | |
7461 | return 0; | |
7462 | } | |
7463 | ||
7464 | static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) | |
7465 | { | |
7466 | int i; | |
7467 | ||
7468 | for (i = 0; i < bp->nr_vnics; i++) | |
7469 | bnxt_hwrm_vnic_set_rss(bp, i, false); | |
7470 | } | |
7471 | ||
a46ecb11 | 7472 | static void bnxt_clear_vnic(struct bnxt *bp) |
c0c050c5 | 7473 | { |
a46ecb11 MC |
7474 | if (!bp->vnic_info) |
7475 | return; | |
7476 | ||
7477 | bnxt_hwrm_clear_vnic_filter(bp); | |
7478 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) { | |
c0c050c5 MC |
7479 | /* clear all RSS setting before free vnic ctx */ |
7480 | bnxt_hwrm_clear_vnic_rss(bp); | |
7481 | bnxt_hwrm_vnic_ctx_free(bp); | |
c0c050c5 | 7482 | } |
a46ecb11 MC |
7483 | /* before free the vnic, undo the vnic tpa settings */ |
7484 | if (bp->flags & BNXT_FLAG_TPA) | |
7485 | bnxt_set_tpa(bp, false); | |
7486 | bnxt_hwrm_vnic_free(bp); | |
7487 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
7488 | bnxt_hwrm_vnic_ctx_free(bp); | |
7489 | } | |
7490 | ||
7491 | static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, | |
7492 | bool irq_re_init) | |
7493 | { | |
7494 | bnxt_clear_vnic(bp); | |
c0c050c5 MC |
7495 | bnxt_hwrm_ring_free(bp, close_path); |
7496 | bnxt_hwrm_ring_grp_free(bp); | |
7497 | if (irq_re_init) { | |
7498 | bnxt_hwrm_stat_ctx_free(bp); | |
7499 | bnxt_hwrm_free_tunnel_ports(bp); | |
7500 | } | |
7501 | } | |
7502 | ||
39d8ba2e MC |
7503 | static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode) |
7504 | { | |
7505 | struct hwrm_func_cfg_input req = {0}; | |
7506 | int rc; | |
7507 | ||
7508 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); | |
7509 | req.fid = cpu_to_le16(0xffff); | |
7510 | req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE); | |
7511 | if (br_mode == BRIDGE_MODE_VEB) | |
7512 | req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB; | |
7513 | else if (br_mode == BRIDGE_MODE_VEPA) | |
7514 | req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA; | |
7515 | else | |
7516 | return -EINVAL; | |
7517 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
39d8ba2e MC |
7518 | return rc; |
7519 | } | |
7520 | ||
c3480a60 MC |
7521 | static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size) |
7522 | { | |
7523 | struct hwrm_func_cfg_input req = {0}; | |
7524 | int rc; | |
7525 | ||
7526 | if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803) | |
7527 | return 0; | |
7528 | ||
7529 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); | |
7530 | req.fid = cpu_to_le16(0xffff); | |
7531 | req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE); | |
d4f52de0 | 7532 | req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64; |
c3480a60 | 7533 | if (size == 128) |
d4f52de0 | 7534 | req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128; |
c3480a60 MC |
7535 | |
7536 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
c3480a60 MC |
7537 | return rc; |
7538 | } | |
7539 | ||
7b3af4f7 | 7540 | static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) |
c0c050c5 | 7541 | { |
ae10ae74 | 7542 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
c0c050c5 MC |
7543 | int rc; |
7544 | ||
ae10ae74 MC |
7545 | if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) |
7546 | goto skip_rss_ctx; | |
7547 | ||
c0c050c5 | 7548 | /* allocate context for vnic */ |
94ce9caa | 7549 | rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0); |
c0c050c5 MC |
7550 | if (rc) { |
7551 | netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", | |
7552 | vnic_id, rc); | |
7553 | goto vnic_setup_err; | |
7554 | } | |
7555 | bp->rsscos_nr_ctxs++; | |
7556 | ||
94ce9caa PS |
7557 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { |
7558 | rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1); | |
7559 | if (rc) { | |
7560 | netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n", | |
7561 | vnic_id, rc); | |
7562 | goto vnic_setup_err; | |
7563 | } | |
7564 | bp->rsscos_nr_ctxs++; | |
7565 | } | |
7566 | ||
ae10ae74 | 7567 | skip_rss_ctx: |
c0c050c5 MC |
7568 | /* configure default vnic, ring grp */ |
7569 | rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); | |
7570 | if (rc) { | |
7571 | netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", | |
7572 | vnic_id, rc); | |
7573 | goto vnic_setup_err; | |
7574 | } | |
7575 | ||
7576 | /* Enable RSS hashing on vnic */ | |
7577 | rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); | |
7578 | if (rc) { | |
7579 | netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", | |
7580 | vnic_id, rc); | |
7581 | goto vnic_setup_err; | |
7582 | } | |
7583 | ||
7584 | if (bp->flags & BNXT_FLAG_AGG_RINGS) { | |
7585 | rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); | |
7586 | if (rc) { | |
7587 | netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", | |
7588 | vnic_id, rc); | |
7589 | } | |
7590 | } | |
7591 | ||
7592 | vnic_setup_err: | |
7593 | return rc; | |
7594 | } | |
7595 | ||
7b3af4f7 MC |
7596 | static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id) |
7597 | { | |
7598 | int rc, i, nr_ctxs; | |
7599 | ||
7600 | nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64); | |
7601 | for (i = 0; i < nr_ctxs; i++) { | |
7602 | rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i); | |
7603 | if (rc) { | |
7604 | netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n", | |
7605 | vnic_id, i, rc); | |
7606 | break; | |
7607 | } | |
7608 | bp->rsscos_nr_ctxs++; | |
7609 | } | |
7610 | if (i < nr_ctxs) | |
7611 | return -ENOMEM; | |
7612 | ||
7613 | rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true); | |
7614 | if (rc) { | |
7615 | netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n", | |
7616 | vnic_id, rc); | |
7617 | return rc; | |
7618 | } | |
7619 | rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); | |
7620 | if (rc) { | |
7621 | netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", | |
7622 | vnic_id, rc); | |
7623 | return rc; | |
7624 | } | |
7625 | if (bp->flags & BNXT_FLAG_AGG_RINGS) { | |
7626 | rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); | |
7627 | if (rc) { | |
7628 | netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", | |
7629 | vnic_id, rc); | |
7630 | } | |
7631 | } | |
7632 | return rc; | |
7633 | } | |
7634 | ||
7635 | static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) | |
7636 | { | |
7637 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
7638 | return __bnxt_setup_vnic_p5(bp, vnic_id); | |
7639 | else | |
7640 | return __bnxt_setup_vnic(bp, vnic_id); | |
7641 | } | |
7642 | ||
c0c050c5 MC |
7643 | static int bnxt_alloc_rfs_vnics(struct bnxt *bp) |
7644 | { | |
7645 | #ifdef CONFIG_RFS_ACCEL | |
7646 | int i, rc = 0; | |
7647 | ||
9b3d15e6 MC |
7648 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
7649 | return 0; | |
7650 | ||
c0c050c5 | 7651 | for (i = 0; i < bp->rx_nr_rings; i++) { |
ae10ae74 | 7652 | struct bnxt_vnic_info *vnic; |
c0c050c5 MC |
7653 | u16 vnic_id = i + 1; |
7654 | u16 ring_id = i; | |
7655 | ||
7656 | if (vnic_id >= bp->nr_vnics) | |
7657 | break; | |
7658 | ||
ae10ae74 MC |
7659 | vnic = &bp->vnic_info[vnic_id]; |
7660 | vnic->flags |= BNXT_VNIC_RFS_FLAG; | |
7661 | if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) | |
7662 | vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG; | |
b81a90d3 | 7663 | rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); |
c0c050c5 MC |
7664 | if (rc) { |
7665 | netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", | |
7666 | vnic_id, rc); | |
7667 | break; | |
7668 | } | |
7669 | rc = bnxt_setup_vnic(bp, vnic_id); | |
7670 | if (rc) | |
7671 | break; | |
7672 | } | |
7673 | return rc; | |
7674 | #else | |
7675 | return 0; | |
7676 | #endif | |
7677 | } | |
7678 | ||
17c71ac3 MC |
7679 | /* Allow PF and VF with default VLAN to be in promiscuous mode */ |
7680 | static bool bnxt_promisc_ok(struct bnxt *bp) | |
7681 | { | |
7682 | #ifdef CONFIG_BNXT_SRIOV | |
7683 | if (BNXT_VF(bp) && !bp->vf.vlan) | |
7684 | return false; | |
7685 | #endif | |
7686 | return true; | |
7687 | } | |
7688 | ||
dc52c6c7 PS |
7689 | static int bnxt_setup_nitroa0_vnic(struct bnxt *bp) |
7690 | { | |
7691 | unsigned int rc = 0; | |
7692 | ||
7693 | rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1); | |
7694 | if (rc) { | |
7695 | netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", | |
7696 | rc); | |
7697 | return rc; | |
7698 | } | |
7699 | ||
7700 | rc = bnxt_hwrm_vnic_cfg(bp, 1); | |
7701 | if (rc) { | |
7702 | netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", | |
7703 | rc); | |
7704 | return rc; | |
7705 | } | |
7706 | return rc; | |
7707 | } | |
7708 | ||
b664f008 | 7709 | static int bnxt_cfg_rx_mode(struct bnxt *); |
7d2837dd | 7710 | static bool bnxt_mc_list_updated(struct bnxt *, u32 *); |
b664f008 | 7711 | |
c0c050c5 MC |
7712 | static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) |
7713 | { | |
7d2837dd | 7714 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; |
c0c050c5 | 7715 | int rc = 0; |
76595193 | 7716 | unsigned int rx_nr_rings = bp->rx_nr_rings; |
c0c050c5 MC |
7717 | |
7718 | if (irq_re_init) { | |
7719 | rc = bnxt_hwrm_stat_ctx_alloc(bp); | |
7720 | if (rc) { | |
7721 | netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", | |
7722 | rc); | |
7723 | goto err_out; | |
7724 | } | |
7725 | } | |
7726 | ||
7727 | rc = bnxt_hwrm_ring_alloc(bp); | |
7728 | if (rc) { | |
7729 | netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); | |
7730 | goto err_out; | |
7731 | } | |
7732 | ||
7733 | rc = bnxt_hwrm_ring_grp_alloc(bp); | |
7734 | if (rc) { | |
7735 | netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); | |
7736 | goto err_out; | |
7737 | } | |
7738 | ||
76595193 PS |
7739 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) |
7740 | rx_nr_rings--; | |
7741 | ||
c0c050c5 | 7742 | /* default vnic 0 */ |
76595193 | 7743 | rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings); |
c0c050c5 MC |
7744 | if (rc) { |
7745 | netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); | |
7746 | goto err_out; | |
7747 | } | |
7748 | ||
7749 | rc = bnxt_setup_vnic(bp, 0); | |
7750 | if (rc) | |
7751 | goto err_out; | |
7752 | ||
7753 | if (bp->flags & BNXT_FLAG_RFS) { | |
7754 | rc = bnxt_alloc_rfs_vnics(bp); | |
7755 | if (rc) | |
7756 | goto err_out; | |
7757 | } | |
7758 | ||
7759 | if (bp->flags & BNXT_FLAG_TPA) { | |
7760 | rc = bnxt_set_tpa(bp, true); | |
7761 | if (rc) | |
7762 | goto err_out; | |
7763 | } | |
7764 | ||
7765 | if (BNXT_VF(bp)) | |
7766 | bnxt_update_vf_mac(bp); | |
7767 | ||
7768 | /* Filter for default vnic 0 */ | |
7769 | rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); | |
7770 | if (rc) { | |
7771 | netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); | |
7772 | goto err_out; | |
7773 | } | |
7d2837dd | 7774 | vnic->uc_filter_count = 1; |
c0c050c5 | 7775 | |
30e33848 MC |
7776 | vnic->rx_mask = 0; |
7777 | if (bp->dev->flags & IFF_BROADCAST) | |
7778 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; | |
c0c050c5 | 7779 | |
17c71ac3 | 7780 | if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) |
7d2837dd MC |
7781 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; |
7782 | ||
7783 | if (bp->dev->flags & IFF_ALLMULTI) { | |
7784 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; | |
7785 | vnic->mc_list_count = 0; | |
7786 | } else { | |
7787 | u32 mask = 0; | |
7788 | ||
7789 | bnxt_mc_list_updated(bp, &mask); | |
7790 | vnic->rx_mask |= mask; | |
7791 | } | |
c0c050c5 | 7792 | |
b664f008 MC |
7793 | rc = bnxt_cfg_rx_mode(bp); |
7794 | if (rc) | |
c0c050c5 | 7795 | goto err_out; |
c0c050c5 MC |
7796 | |
7797 | rc = bnxt_hwrm_set_coal(bp); | |
7798 | if (rc) | |
7799 | netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", | |
dc52c6c7 PS |
7800 | rc); |
7801 | ||
7802 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { | |
7803 | rc = bnxt_setup_nitroa0_vnic(bp); | |
7804 | if (rc) | |
7805 | netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n", | |
7806 | rc); | |
7807 | } | |
c0c050c5 | 7808 | |
cf6645f8 MC |
7809 | if (BNXT_VF(bp)) { |
7810 | bnxt_hwrm_func_qcfg(bp); | |
7811 | netdev_update_features(bp->dev); | |
7812 | } | |
7813 | ||
c0c050c5 MC |
7814 | return 0; |
7815 | ||
7816 | err_out: | |
7817 | bnxt_hwrm_resource_free(bp, 0, true); | |
7818 | ||
7819 | return rc; | |
7820 | } | |
7821 | ||
7822 | static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) | |
7823 | { | |
7824 | bnxt_hwrm_resource_free(bp, 1, irq_re_init); | |
7825 | return 0; | |
7826 | } | |
7827 | ||
7828 | static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) | |
7829 | { | |
2247925f | 7830 | bnxt_init_cp_rings(bp); |
c0c050c5 MC |
7831 | bnxt_init_rx_rings(bp); |
7832 | bnxt_init_tx_rings(bp); | |
7833 | bnxt_init_ring_grps(bp, irq_re_init); | |
7834 | bnxt_init_vnics(bp); | |
7835 | ||
7836 | return bnxt_init_chip(bp, irq_re_init); | |
7837 | } | |
7838 | ||
c0c050c5 MC |
7839 | static int bnxt_set_real_num_queues(struct bnxt *bp) |
7840 | { | |
7841 | int rc; | |
7842 | struct net_device *dev = bp->dev; | |
7843 | ||
5f449249 MC |
7844 | rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings - |
7845 | bp->tx_nr_rings_xdp); | |
c0c050c5 MC |
7846 | if (rc) |
7847 | return rc; | |
7848 | ||
7849 | rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); | |
7850 | if (rc) | |
7851 | return rc; | |
7852 | ||
7853 | #ifdef CONFIG_RFS_ACCEL | |
45019a18 | 7854 | if (bp->flags & BNXT_FLAG_RFS) |
c0c050c5 | 7855 | dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); |
c0c050c5 MC |
7856 | #endif |
7857 | ||
7858 | return rc; | |
7859 | } | |
7860 | ||
6e6c5a57 MC |
7861 | static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, |
7862 | bool shared) | |
7863 | { | |
7864 | int _rx = *rx, _tx = *tx; | |
7865 | ||
7866 | if (shared) { | |
7867 | *rx = min_t(int, _rx, max); | |
7868 | *tx = min_t(int, _tx, max); | |
7869 | } else { | |
7870 | if (max < 2) | |
7871 | return -ENOMEM; | |
7872 | ||
7873 | while (_rx + _tx > max) { | |
7874 | if (_rx > _tx && _rx > 1) | |
7875 | _rx--; | |
7876 | else if (_tx > 1) | |
7877 | _tx--; | |
7878 | } | |
7879 | *rx = _rx; | |
7880 | *tx = _tx; | |
7881 | } | |
7882 | return 0; | |
7883 | } | |
7884 | ||
7809592d MC |
7885 | static void bnxt_setup_msix(struct bnxt *bp) |
7886 | { | |
7887 | const int len = sizeof(bp->irq_tbl[0].name); | |
7888 | struct net_device *dev = bp->dev; | |
7889 | int tcs, i; | |
7890 | ||
7891 | tcs = netdev_get_num_tc(dev); | |
18e4960c | 7892 | if (tcs) { |
d1e7925e | 7893 | int i, off, count; |
7809592d | 7894 | |
d1e7925e MC |
7895 | for (i = 0; i < tcs; i++) { |
7896 | count = bp->tx_nr_rings_per_tc; | |
7897 | off = i * count; | |
7898 | netdev_set_tc_queue(dev, i, count, off); | |
7809592d MC |
7899 | } |
7900 | } | |
7901 | ||
7902 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
e5811b8c | 7903 | int map_idx = bnxt_cp_num_to_irq_num(bp, i); |
7809592d MC |
7904 | char *attr; |
7905 | ||
7906 | if (bp->flags & BNXT_FLAG_SHARED_RINGS) | |
7907 | attr = "TxRx"; | |
7908 | else if (i < bp->rx_nr_rings) | |
7909 | attr = "rx"; | |
7910 | else | |
7911 | attr = "tx"; | |
7912 | ||
e5811b8c MC |
7913 | snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name, |
7914 | attr, i); | |
7915 | bp->irq_tbl[map_idx].handler = bnxt_msix; | |
7809592d MC |
7916 | } |
7917 | } | |
7918 | ||
7919 | static void bnxt_setup_inta(struct bnxt *bp) | |
7920 | { | |
7921 | const int len = sizeof(bp->irq_tbl[0].name); | |
7922 | ||
7923 | if (netdev_get_num_tc(bp->dev)) | |
7924 | netdev_reset_tc(bp->dev); | |
7925 | ||
7926 | snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx", | |
7927 | 0); | |
7928 | bp->irq_tbl[0].handler = bnxt_inta; | |
7929 | } | |
7930 | ||
7931 | static int bnxt_setup_int_mode(struct bnxt *bp) | |
7932 | { | |
7933 | int rc; | |
7934 | ||
7935 | if (bp->flags & BNXT_FLAG_USING_MSIX) | |
7936 | bnxt_setup_msix(bp); | |
7937 | else | |
7938 | bnxt_setup_inta(bp); | |
7939 | ||
7940 | rc = bnxt_set_real_num_queues(bp); | |
7941 | return rc; | |
7942 | } | |
7943 | ||
b7429954 | 7944 | #ifdef CONFIG_RFS_ACCEL |
8079e8f1 MC |
7945 | static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp) |
7946 | { | |
6a4f2947 | 7947 | return bp->hw_resc.max_rsscos_ctxs; |
8079e8f1 MC |
7948 | } |
7949 | ||
7950 | static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp) | |
7951 | { | |
6a4f2947 | 7952 | return bp->hw_resc.max_vnics; |
8079e8f1 | 7953 | } |
b7429954 | 7954 | #endif |
8079e8f1 | 7955 | |
e4060d30 MC |
7956 | unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp) |
7957 | { | |
6a4f2947 | 7958 | return bp->hw_resc.max_stat_ctxs; |
e4060d30 MC |
7959 | } |
7960 | ||
7961 | unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp) | |
7962 | { | |
6a4f2947 | 7963 | return bp->hw_resc.max_cp_rings; |
e4060d30 MC |
7964 | } |
7965 | ||
e916b081 | 7966 | static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp) |
a588e458 | 7967 | { |
c0b8cda0 MC |
7968 | unsigned int cp = bp->hw_resc.max_cp_rings; |
7969 | ||
7970 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
7971 | cp -= bnxt_get_ulp_msix_num(bp); | |
7972 | ||
7973 | return cp; | |
a588e458 MC |
7974 | } |
7975 | ||
ad95c27b | 7976 | static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp) |
7809592d | 7977 | { |
6a4f2947 MC |
7978 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; |
7979 | ||
f7588cd8 MC |
7980 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
7981 | return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs); | |
7982 | ||
6a4f2947 | 7983 | return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings); |
7809592d MC |
7984 | } |
7985 | ||
30f52947 | 7986 | static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs) |
33c2657e | 7987 | { |
6a4f2947 | 7988 | bp->hw_resc.max_irqs = max_irqs; |
33c2657e MC |
7989 | } |
7990 | ||
e916b081 MC |
7991 | unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp) |
7992 | { | |
7993 | unsigned int cp; | |
7994 | ||
7995 | cp = bnxt_get_max_func_cp_rings_for_en(bp); | |
7996 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
7997 | return cp - bp->rx_nr_rings - bp->tx_nr_rings; | |
7998 | else | |
7999 | return cp - bp->cp_nr_rings; | |
8000 | } | |
8001 | ||
c027c6b4 VV |
8002 | unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp) |
8003 | { | |
d77b1ad8 | 8004 | return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp); |
c027c6b4 VV |
8005 | } |
8006 | ||
fbcfc8e4 MC |
8007 | int bnxt_get_avail_msix(struct bnxt *bp, int num) |
8008 | { | |
8009 | int max_cp = bnxt_get_max_func_cp_rings(bp); | |
8010 | int max_irq = bnxt_get_max_func_irqs(bp); | |
8011 | int total_req = bp->cp_nr_rings + num; | |
8012 | int max_idx, avail_msix; | |
8013 | ||
75720e63 MC |
8014 | max_idx = bp->total_irqs; |
8015 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
8016 | max_idx = min_t(int, bp->total_irqs, max_cp); | |
fbcfc8e4 | 8017 | avail_msix = max_idx - bp->cp_nr_rings; |
f1ca94de | 8018 | if (!BNXT_NEW_RM(bp) || avail_msix >= num) |
fbcfc8e4 MC |
8019 | return avail_msix; |
8020 | ||
8021 | if (max_irq < total_req) { | |
8022 | num = max_irq - bp->cp_nr_rings; | |
8023 | if (num <= 0) | |
8024 | return 0; | |
8025 | } | |
8026 | return num; | |
8027 | } | |
8028 | ||
08654eb2 MC |
8029 | static int bnxt_get_num_msix(struct bnxt *bp) |
8030 | { | |
f1ca94de | 8031 | if (!BNXT_NEW_RM(bp)) |
08654eb2 MC |
8032 | return bnxt_get_max_func_irqs(bp); |
8033 | ||
c0b8cda0 | 8034 | return bnxt_nq_rings_in_use(bp); |
08654eb2 MC |
8035 | } |
8036 | ||
7809592d | 8037 | static int bnxt_init_msix(struct bnxt *bp) |
c0c050c5 | 8038 | { |
fbcfc8e4 | 8039 | int i, total_vecs, max, rc = 0, min = 1, ulp_msix; |
7809592d | 8040 | struct msix_entry *msix_ent; |
c0c050c5 | 8041 | |
08654eb2 MC |
8042 | total_vecs = bnxt_get_num_msix(bp); |
8043 | max = bnxt_get_max_func_irqs(bp); | |
8044 | if (total_vecs > max) | |
8045 | total_vecs = max; | |
8046 | ||
2773dfb2 MC |
8047 | if (!total_vecs) |
8048 | return 0; | |
8049 | ||
c0c050c5 MC |
8050 | msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); |
8051 | if (!msix_ent) | |
8052 | return -ENOMEM; | |
8053 | ||
8054 | for (i = 0; i < total_vecs; i++) { | |
8055 | msix_ent[i].entry = i; | |
8056 | msix_ent[i].vector = 0; | |
8057 | } | |
8058 | ||
01657bcd MC |
8059 | if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) |
8060 | min = 2; | |
8061 | ||
8062 | total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); | |
fbcfc8e4 MC |
8063 | ulp_msix = bnxt_get_ulp_msix_num(bp); |
8064 | if (total_vecs < 0 || total_vecs < ulp_msix) { | |
c0c050c5 MC |
8065 | rc = -ENODEV; |
8066 | goto msix_setup_exit; | |
8067 | } | |
8068 | ||
8069 | bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); | |
8070 | if (bp->irq_tbl) { | |
7809592d MC |
8071 | for (i = 0; i < total_vecs; i++) |
8072 | bp->irq_tbl[i].vector = msix_ent[i].vector; | |
c0c050c5 | 8073 | |
7809592d | 8074 | bp->total_irqs = total_vecs; |
c0c050c5 | 8075 | /* Trim rings based upon num of vectors allocated */ |
6e6c5a57 | 8076 | rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, |
fbcfc8e4 | 8077 | total_vecs - ulp_msix, min == 1); |
6e6c5a57 MC |
8078 | if (rc) |
8079 | goto msix_setup_exit; | |
8080 | ||
7809592d MC |
8081 | bp->cp_nr_rings = (min == 1) ? |
8082 | max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : | |
8083 | bp->tx_nr_rings + bp->rx_nr_rings; | |
c0c050c5 | 8084 | |
c0c050c5 MC |
8085 | } else { |
8086 | rc = -ENOMEM; | |
8087 | goto msix_setup_exit; | |
8088 | } | |
8089 | bp->flags |= BNXT_FLAG_USING_MSIX; | |
8090 | kfree(msix_ent); | |
8091 | return 0; | |
8092 | ||
8093 | msix_setup_exit: | |
7809592d MC |
8094 | netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc); |
8095 | kfree(bp->irq_tbl); | |
8096 | bp->irq_tbl = NULL; | |
c0c050c5 MC |
8097 | pci_disable_msix(bp->pdev); |
8098 | kfree(msix_ent); | |
8099 | return rc; | |
8100 | } | |
8101 | ||
7809592d | 8102 | static int bnxt_init_inta(struct bnxt *bp) |
c0c050c5 | 8103 | { |
c0c050c5 | 8104 | bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL); |
7809592d MC |
8105 | if (!bp->irq_tbl) |
8106 | return -ENOMEM; | |
8107 | ||
8108 | bp->total_irqs = 1; | |
c0c050c5 MC |
8109 | bp->rx_nr_rings = 1; |
8110 | bp->tx_nr_rings = 1; | |
8111 | bp->cp_nr_rings = 1; | |
01657bcd | 8112 | bp->flags |= BNXT_FLAG_SHARED_RINGS; |
c0c050c5 | 8113 | bp->irq_tbl[0].vector = bp->pdev->irq; |
7809592d | 8114 | return 0; |
c0c050c5 MC |
8115 | } |
8116 | ||
7809592d | 8117 | static int bnxt_init_int_mode(struct bnxt *bp) |
c0c050c5 MC |
8118 | { |
8119 | int rc = 0; | |
8120 | ||
8121 | if (bp->flags & BNXT_FLAG_MSIX_CAP) | |
7809592d | 8122 | rc = bnxt_init_msix(bp); |
c0c050c5 | 8123 | |
1fa72e29 | 8124 | if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) { |
c0c050c5 | 8125 | /* fallback to INTA */ |
7809592d | 8126 | rc = bnxt_init_inta(bp); |
c0c050c5 MC |
8127 | } |
8128 | return rc; | |
8129 | } | |
8130 | ||
7809592d MC |
8131 | static void bnxt_clear_int_mode(struct bnxt *bp) |
8132 | { | |
8133 | if (bp->flags & BNXT_FLAG_USING_MSIX) | |
8134 | pci_disable_msix(bp->pdev); | |
8135 | ||
8136 | kfree(bp->irq_tbl); | |
8137 | bp->irq_tbl = NULL; | |
8138 | bp->flags &= ~BNXT_FLAG_USING_MSIX; | |
8139 | } | |
8140 | ||
1b3f0b75 | 8141 | int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init) |
674f50a5 | 8142 | { |
674f50a5 | 8143 | int tcs = netdev_get_num_tc(bp->dev); |
1b3f0b75 | 8144 | bool irq_cleared = false; |
674f50a5 MC |
8145 | int rc; |
8146 | ||
8147 | if (!bnxt_need_reserve_rings(bp)) | |
8148 | return 0; | |
8149 | ||
1b3f0b75 MC |
8150 | if (irq_re_init && BNXT_NEW_RM(bp) && |
8151 | bnxt_get_num_msix(bp) != bp->total_irqs) { | |
ec86f14e | 8152 | bnxt_ulp_irq_stop(bp); |
674f50a5 | 8153 | bnxt_clear_int_mode(bp); |
1b3f0b75 | 8154 | irq_cleared = true; |
36d65be9 MC |
8155 | } |
8156 | rc = __bnxt_reserve_rings(bp); | |
1b3f0b75 | 8157 | if (irq_cleared) { |
36d65be9 MC |
8158 | if (!rc) |
8159 | rc = bnxt_init_int_mode(bp); | |
ec86f14e | 8160 | bnxt_ulp_irq_restart(bp, rc); |
36d65be9 MC |
8161 | } |
8162 | if (rc) { | |
8163 | netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc); | |
8164 | return rc; | |
674f50a5 MC |
8165 | } |
8166 | if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) { | |
8167 | netdev_err(bp->dev, "tx ring reservation failure\n"); | |
8168 | netdev_reset_tc(bp->dev); | |
8169 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; | |
8170 | return -ENOMEM; | |
8171 | } | |
674f50a5 MC |
8172 | return 0; |
8173 | } | |
8174 | ||
c0c050c5 MC |
8175 | static void bnxt_free_irq(struct bnxt *bp) |
8176 | { | |
8177 | struct bnxt_irq *irq; | |
8178 | int i; | |
8179 | ||
8180 | #ifdef CONFIG_RFS_ACCEL | |
8181 | free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); | |
8182 | bp->dev->rx_cpu_rmap = NULL; | |
8183 | #endif | |
cb98526b | 8184 | if (!bp->irq_tbl || !bp->bnapi) |
c0c050c5 MC |
8185 | return; |
8186 | ||
8187 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
e5811b8c MC |
8188 | int map_idx = bnxt_cp_num_to_irq_num(bp, i); |
8189 | ||
8190 | irq = &bp->irq_tbl[map_idx]; | |
56f0fd80 VV |
8191 | if (irq->requested) { |
8192 | if (irq->have_cpumask) { | |
8193 | irq_set_affinity_hint(irq->vector, NULL); | |
8194 | free_cpumask_var(irq->cpu_mask); | |
8195 | irq->have_cpumask = 0; | |
8196 | } | |
c0c050c5 | 8197 | free_irq(irq->vector, bp->bnapi[i]); |
56f0fd80 VV |
8198 | } |
8199 | ||
c0c050c5 MC |
8200 | irq->requested = 0; |
8201 | } | |
c0c050c5 MC |
8202 | } |
8203 | ||
8204 | static int bnxt_request_irq(struct bnxt *bp) | |
8205 | { | |
b81a90d3 | 8206 | int i, j, rc = 0; |
c0c050c5 MC |
8207 | unsigned long flags = 0; |
8208 | #ifdef CONFIG_RFS_ACCEL | |
e5811b8c | 8209 | struct cpu_rmap *rmap; |
c0c050c5 MC |
8210 | #endif |
8211 | ||
e5811b8c MC |
8212 | rc = bnxt_setup_int_mode(bp); |
8213 | if (rc) { | |
8214 | netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", | |
8215 | rc); | |
8216 | return rc; | |
8217 | } | |
8218 | #ifdef CONFIG_RFS_ACCEL | |
8219 | rmap = bp->dev->rx_cpu_rmap; | |
8220 | #endif | |
c0c050c5 MC |
8221 | if (!(bp->flags & BNXT_FLAG_USING_MSIX)) |
8222 | flags = IRQF_SHARED; | |
8223 | ||
b81a90d3 | 8224 | for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { |
e5811b8c MC |
8225 | int map_idx = bnxt_cp_num_to_irq_num(bp, i); |
8226 | struct bnxt_irq *irq = &bp->irq_tbl[map_idx]; | |
8227 | ||
c0c050c5 | 8228 | #ifdef CONFIG_RFS_ACCEL |
b81a90d3 | 8229 | if (rmap && bp->bnapi[i]->rx_ring) { |
c0c050c5 MC |
8230 | rc = irq_cpu_rmap_add(rmap, irq->vector); |
8231 | if (rc) | |
8232 | netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", | |
b81a90d3 MC |
8233 | j); |
8234 | j++; | |
c0c050c5 MC |
8235 | } |
8236 | #endif | |
8237 | rc = request_irq(irq->vector, irq->handler, flags, irq->name, | |
8238 | bp->bnapi[i]); | |
8239 | if (rc) | |
8240 | break; | |
8241 | ||
8242 | irq->requested = 1; | |
56f0fd80 VV |
8243 | |
8244 | if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) { | |
8245 | int numa_node = dev_to_node(&bp->pdev->dev); | |
8246 | ||
8247 | irq->have_cpumask = 1; | |
8248 | cpumask_set_cpu(cpumask_local_spread(i, numa_node), | |
8249 | irq->cpu_mask); | |
8250 | rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask); | |
8251 | if (rc) { | |
8252 | netdev_warn(bp->dev, | |
8253 | "Set affinity failed, IRQ = %d\n", | |
8254 | irq->vector); | |
8255 | break; | |
8256 | } | |
8257 | } | |
c0c050c5 MC |
8258 | } |
8259 | return rc; | |
8260 | } | |
8261 | ||
8262 | static void bnxt_del_napi(struct bnxt *bp) | |
8263 | { | |
8264 | int i; | |
8265 | ||
8266 | if (!bp->bnapi) | |
8267 | return; | |
8268 | ||
8269 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
8270 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
8271 | ||
8272 | napi_hash_del(&bnapi->napi); | |
8273 | netif_napi_del(&bnapi->napi); | |
8274 | } | |
e5f6f564 ED |
8275 | /* We called napi_hash_del() before netif_napi_del(), we need |
8276 | * to respect an RCU grace period before freeing napi structures. | |
8277 | */ | |
8278 | synchronize_net(); | |
c0c050c5 MC |
8279 | } |
8280 | ||
8281 | static void bnxt_init_napi(struct bnxt *bp) | |
8282 | { | |
8283 | int i; | |
10bbdaf5 | 8284 | unsigned int cp_nr_rings = bp->cp_nr_rings; |
c0c050c5 MC |
8285 | struct bnxt_napi *bnapi; |
8286 | ||
8287 | if (bp->flags & BNXT_FLAG_USING_MSIX) { | |
0fcec985 MC |
8288 | int (*poll_fn)(struct napi_struct *, int) = bnxt_poll; |
8289 | ||
8290 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
8291 | poll_fn = bnxt_poll_p5; | |
8292 | else if (BNXT_CHIP_TYPE_NITRO_A0(bp)) | |
10bbdaf5 PS |
8293 | cp_nr_rings--; |
8294 | for (i = 0; i < cp_nr_rings; i++) { | |
c0c050c5 | 8295 | bnapi = bp->bnapi[i]; |
0fcec985 | 8296 | netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64); |
c0c050c5 | 8297 | } |
10bbdaf5 PS |
8298 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { |
8299 | bnapi = bp->bnapi[cp_nr_rings]; | |
8300 | netif_napi_add(bp->dev, &bnapi->napi, | |
8301 | bnxt_poll_nitroa0, 64); | |
10bbdaf5 | 8302 | } |
c0c050c5 MC |
8303 | } else { |
8304 | bnapi = bp->bnapi[0]; | |
8305 | netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64); | |
c0c050c5 MC |
8306 | } |
8307 | } | |
8308 | ||
8309 | static void bnxt_disable_napi(struct bnxt *bp) | |
8310 | { | |
8311 | int i; | |
8312 | ||
8313 | if (!bp->bnapi) | |
8314 | return; | |
8315 | ||
0bc0b97f AG |
8316 | for (i = 0; i < bp->cp_nr_rings; i++) { |
8317 | struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; | |
8318 | ||
8319 | if (bp->bnapi[i]->rx_ring) | |
8320 | cancel_work_sync(&cpr->dim.work); | |
8321 | ||
c0c050c5 | 8322 | napi_disable(&bp->bnapi[i]->napi); |
0bc0b97f | 8323 | } |
c0c050c5 MC |
8324 | } |
8325 | ||
8326 | static void bnxt_enable_napi(struct bnxt *bp) | |
8327 | { | |
8328 | int i; | |
8329 | ||
8330 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
6a8788f2 | 8331 | struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; |
fa7e2812 | 8332 | bp->bnapi[i]->in_reset = false; |
6a8788f2 AG |
8333 | |
8334 | if (bp->bnapi[i]->rx_ring) { | |
8335 | INIT_WORK(&cpr->dim.work, bnxt_dim_work); | |
c002bd52 | 8336 | cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; |
6a8788f2 | 8337 | } |
c0c050c5 MC |
8338 | napi_enable(&bp->bnapi[i]->napi); |
8339 | } | |
8340 | } | |
8341 | ||
7df4ae9f | 8342 | void bnxt_tx_disable(struct bnxt *bp) |
c0c050c5 MC |
8343 | { |
8344 | int i; | |
c0c050c5 | 8345 | struct bnxt_tx_ring_info *txr; |
c0c050c5 | 8346 | |
b6ab4b01 | 8347 | if (bp->tx_ring) { |
c0c050c5 | 8348 | for (i = 0; i < bp->tx_nr_rings; i++) { |
b6ab4b01 | 8349 | txr = &bp->tx_ring[i]; |
c0c050c5 | 8350 | txr->dev_state = BNXT_DEV_STATE_CLOSING; |
c0c050c5 MC |
8351 | } |
8352 | } | |
8353 | /* Stop all TX queues */ | |
8354 | netif_tx_disable(bp->dev); | |
8355 | netif_carrier_off(bp->dev); | |
8356 | } | |
8357 | ||
7df4ae9f | 8358 | void bnxt_tx_enable(struct bnxt *bp) |
c0c050c5 MC |
8359 | { |
8360 | int i; | |
c0c050c5 | 8361 | struct bnxt_tx_ring_info *txr; |
c0c050c5 MC |
8362 | |
8363 | for (i = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 8364 | txr = &bp->tx_ring[i]; |
c0c050c5 MC |
8365 | txr->dev_state = 0; |
8366 | } | |
8367 | netif_tx_wake_all_queues(bp->dev); | |
8368 | if (bp->link_info.link_up) | |
8369 | netif_carrier_on(bp->dev); | |
8370 | } | |
8371 | ||
8372 | static void bnxt_report_link(struct bnxt *bp) | |
8373 | { | |
8374 | if (bp->link_info.link_up) { | |
8375 | const char *duplex; | |
8376 | const char *flow_ctrl; | |
38a21b34 DK |
8377 | u32 speed; |
8378 | u16 fec; | |
c0c050c5 MC |
8379 | |
8380 | netif_carrier_on(bp->dev); | |
8381 | if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) | |
8382 | duplex = "full"; | |
8383 | else | |
8384 | duplex = "half"; | |
8385 | if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) | |
8386 | flow_ctrl = "ON - receive & transmit"; | |
8387 | else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) | |
8388 | flow_ctrl = "ON - transmit"; | |
8389 | else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) | |
8390 | flow_ctrl = "ON - receive"; | |
8391 | else | |
8392 | flow_ctrl = "none"; | |
8393 | speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); | |
38a21b34 | 8394 | netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n", |
c0c050c5 | 8395 | speed, duplex, flow_ctrl); |
170ce013 MC |
8396 | if (bp->flags & BNXT_FLAG_EEE_CAP) |
8397 | netdev_info(bp->dev, "EEE is %s\n", | |
8398 | bp->eee.eee_active ? "active" : | |
8399 | "not active"); | |
e70c752f MC |
8400 | fec = bp->link_info.fec_cfg; |
8401 | if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED)) | |
8402 | netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n", | |
8403 | (fec & BNXT_FEC_AUTONEG) ? "on" : "off", | |
8404 | (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" : | |
8405 | (fec & BNXT_FEC_ENC_RS) ? "RS" : "None"); | |
c0c050c5 MC |
8406 | } else { |
8407 | netif_carrier_off(bp->dev); | |
8408 | netdev_err(bp->dev, "NIC Link is Down\n"); | |
8409 | } | |
8410 | } | |
8411 | ||
170ce013 MC |
8412 | static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) |
8413 | { | |
8414 | int rc = 0; | |
8415 | struct hwrm_port_phy_qcaps_input req = {0}; | |
8416 | struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
93ed8117 | 8417 | struct bnxt_link_info *link_info = &bp->link_info; |
170ce013 | 8418 | |
ba642ab7 MC |
8419 | bp->flags &= ~BNXT_FLAG_EEE_CAP; |
8420 | if (bp->test_info) | |
8a60efd1 MC |
8421 | bp->test_info->flags &= ~(BNXT_TEST_FL_EXT_LPBK | |
8422 | BNXT_TEST_FL_AN_PHY_LPBK); | |
170ce013 MC |
8423 | if (bp->hwrm_spec_code < 0x10201) |
8424 | return 0; | |
8425 | ||
8426 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); | |
8427 | ||
8428 | mutex_lock(&bp->hwrm_cmd_lock); | |
8429 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8430 | if (rc) | |
8431 | goto hwrm_phy_qcaps_exit; | |
8432 | ||
acb20054 | 8433 | if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) { |
170ce013 MC |
8434 | struct ethtool_eee *eee = &bp->eee; |
8435 | u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode); | |
8436 | ||
8437 | bp->flags |= BNXT_FLAG_EEE_CAP; | |
8438 | eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); | |
8439 | bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) & | |
8440 | PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK; | |
8441 | bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) & | |
8442 | PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK; | |
8443 | } | |
55fd0cf3 MC |
8444 | if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) { |
8445 | if (bp->test_info) | |
8446 | bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK; | |
8447 | } | |
8a60efd1 MC |
8448 | if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED) { |
8449 | if (bp->test_info) | |
8450 | bp->test_info->flags |= BNXT_TEST_FL_AN_PHY_LPBK; | |
8451 | } | |
c7e457f4 MC |
8452 | if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED) { |
8453 | if (BNXT_PF(bp)) | |
8454 | bp->fw_cap |= BNXT_FW_CAP_SHARED_PORT_CFG; | |
8455 | } | |
520ad89a MC |
8456 | if (resp->supported_speeds_auto_mode) |
8457 | link_info->support_auto_speeds = | |
8458 | le16_to_cpu(resp->supported_speeds_auto_mode); | |
170ce013 | 8459 | |
d5430d31 MC |
8460 | bp->port_count = resp->port_cnt; |
8461 | ||
170ce013 MC |
8462 | hwrm_phy_qcaps_exit: |
8463 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8464 | return rc; | |
8465 | } | |
8466 | ||
c0c050c5 MC |
8467 | static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) |
8468 | { | |
8469 | int rc = 0; | |
8470 | struct bnxt_link_info *link_info = &bp->link_info; | |
8471 | struct hwrm_port_phy_qcfg_input req = {0}; | |
8472 | struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
8473 | u8 link_up = link_info->link_up; | |
286ef9d6 | 8474 | u16 diff; |
c0c050c5 MC |
8475 | |
8476 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1); | |
8477 | ||
8478 | mutex_lock(&bp->hwrm_cmd_lock); | |
8479 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8480 | if (rc) { | |
8481 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8482 | return rc; | |
8483 | } | |
8484 | ||
8485 | memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); | |
8486 | link_info->phy_link_status = resp->link; | |
acb20054 MC |
8487 | link_info->duplex = resp->duplex_cfg; |
8488 | if (bp->hwrm_spec_code >= 0x10800) | |
8489 | link_info->duplex = resp->duplex_state; | |
c0c050c5 MC |
8490 | link_info->pause = resp->pause; |
8491 | link_info->auto_mode = resp->auto_mode; | |
8492 | link_info->auto_pause_setting = resp->auto_pause; | |
3277360e | 8493 | link_info->lp_pause = resp->link_partner_adv_pause; |
c0c050c5 | 8494 | link_info->force_pause_setting = resp->force_pause; |
acb20054 | 8495 | link_info->duplex_setting = resp->duplex_cfg; |
c0c050c5 MC |
8496 | if (link_info->phy_link_status == BNXT_LINK_LINK) |
8497 | link_info->link_speed = le16_to_cpu(resp->link_speed); | |
8498 | else | |
8499 | link_info->link_speed = 0; | |
8500 | link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); | |
c0c050c5 MC |
8501 | link_info->support_speeds = le16_to_cpu(resp->support_speeds); |
8502 | link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); | |
3277360e MC |
8503 | link_info->lp_auto_link_speeds = |
8504 | le16_to_cpu(resp->link_partner_adv_speeds); | |
c0c050c5 MC |
8505 | link_info->preemphasis = le32_to_cpu(resp->preemphasis); |
8506 | link_info->phy_ver[0] = resp->phy_maj; | |
8507 | link_info->phy_ver[1] = resp->phy_min; | |
8508 | link_info->phy_ver[2] = resp->phy_bld; | |
8509 | link_info->media_type = resp->media_type; | |
03efbec0 | 8510 | link_info->phy_type = resp->phy_type; |
11f15ed3 | 8511 | link_info->transceiver = resp->xcvr_pkg_type; |
170ce013 MC |
8512 | link_info->phy_addr = resp->eee_config_phy_addr & |
8513 | PORT_PHY_QCFG_RESP_PHY_ADDR_MASK; | |
42ee18fe | 8514 | link_info->module_status = resp->module_status; |
170ce013 MC |
8515 | |
8516 | if (bp->flags & BNXT_FLAG_EEE_CAP) { | |
8517 | struct ethtool_eee *eee = &bp->eee; | |
8518 | u16 fw_speeds; | |
8519 | ||
8520 | eee->eee_active = 0; | |
8521 | if (resp->eee_config_phy_addr & | |
8522 | PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) { | |
8523 | eee->eee_active = 1; | |
8524 | fw_speeds = le16_to_cpu( | |
8525 | resp->link_partner_adv_eee_link_speed_mask); | |
8526 | eee->lp_advertised = | |
8527 | _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); | |
8528 | } | |
8529 | ||
8530 | /* Pull initial EEE config */ | |
8531 | if (!chng_link_state) { | |
8532 | if (resp->eee_config_phy_addr & | |
8533 | PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED) | |
8534 | eee->eee_enabled = 1; | |
c0c050c5 | 8535 | |
170ce013 MC |
8536 | fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask); |
8537 | eee->advertised = | |
8538 | _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); | |
8539 | ||
8540 | if (resp->eee_config_phy_addr & | |
8541 | PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) { | |
8542 | __le32 tmr; | |
8543 | ||
8544 | eee->tx_lpi_enabled = 1; | |
8545 | tmr = resp->xcvr_identifier_type_tx_lpi_timer; | |
8546 | eee->tx_lpi_timer = le32_to_cpu(tmr) & | |
8547 | PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK; | |
8548 | } | |
8549 | } | |
8550 | } | |
e70c752f MC |
8551 | |
8552 | link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED; | |
8553 | if (bp->hwrm_spec_code >= 0x10504) | |
8554 | link_info->fec_cfg = le16_to_cpu(resp->fec_cfg); | |
8555 | ||
c0c050c5 MC |
8556 | /* TODO: need to add more logic to report VF link */ |
8557 | if (chng_link_state) { | |
8558 | if (link_info->phy_link_status == BNXT_LINK_LINK) | |
8559 | link_info->link_up = 1; | |
8560 | else | |
8561 | link_info->link_up = 0; | |
8562 | if (link_up != link_info->link_up) | |
8563 | bnxt_report_link(bp); | |
8564 | } else { | |
8565 | /* alwasy link down if not require to update link state */ | |
8566 | link_info->link_up = 0; | |
8567 | } | |
8568 | mutex_unlock(&bp->hwrm_cmd_lock); | |
286ef9d6 | 8569 | |
c7e457f4 | 8570 | if (!BNXT_PHY_CFG_ABLE(bp)) |
dac04907 MC |
8571 | return 0; |
8572 | ||
286ef9d6 MC |
8573 | diff = link_info->support_auto_speeds ^ link_info->advertising; |
8574 | if ((link_info->support_auto_speeds | diff) != | |
8575 | link_info->support_auto_speeds) { | |
8576 | /* An advertised speed is no longer supported, so we need to | |
0eaa24b9 MC |
8577 | * update the advertisement settings. Caller holds RTNL |
8578 | * so we can modify link settings. | |
286ef9d6 | 8579 | */ |
286ef9d6 | 8580 | link_info->advertising = link_info->support_auto_speeds; |
0eaa24b9 | 8581 | if (link_info->autoneg & BNXT_AUTONEG_SPEED) |
286ef9d6 | 8582 | bnxt_hwrm_set_link_setting(bp, true, false); |
286ef9d6 | 8583 | } |
c0c050c5 MC |
8584 | return 0; |
8585 | } | |
8586 | ||
10289bec MC |
8587 | static void bnxt_get_port_module_status(struct bnxt *bp) |
8588 | { | |
8589 | struct bnxt_link_info *link_info = &bp->link_info; | |
8590 | struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; | |
8591 | u8 module_status; | |
8592 | ||
8593 | if (bnxt_update_link(bp, true)) | |
8594 | return; | |
8595 | ||
8596 | module_status = link_info->module_status; | |
8597 | switch (module_status) { | |
8598 | case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX: | |
8599 | case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: | |
8600 | case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG: | |
8601 | netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n", | |
8602 | bp->pf.port_id); | |
8603 | if (bp->hwrm_spec_code >= 0x10201) { | |
8604 | netdev_warn(bp->dev, "Module part number %s\n", | |
8605 | resp->phy_vendor_partnumber); | |
8606 | } | |
8607 | if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX) | |
8608 | netdev_warn(bp->dev, "TX is disabled\n"); | |
8609 | if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN) | |
8610 | netdev_warn(bp->dev, "SFP+ module is shutdown\n"); | |
8611 | } | |
8612 | } | |
8613 | ||
c0c050c5 MC |
8614 | static void |
8615 | bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) | |
8616 | { | |
8617 | if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { | |
c9ee9516 MC |
8618 | if (bp->hwrm_spec_code >= 0x10201) |
8619 | req->auto_pause = | |
8620 | PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; | |
c0c050c5 MC |
8621 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) |
8622 | req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; | |
8623 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) | |
49b5c7a1 | 8624 | req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX; |
c0c050c5 MC |
8625 | req->enables |= |
8626 | cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); | |
8627 | } else { | |
8628 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) | |
8629 | req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; | |
8630 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) | |
8631 | req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; | |
8632 | req->enables |= | |
8633 | cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); | |
c9ee9516 MC |
8634 | if (bp->hwrm_spec_code >= 0x10201) { |
8635 | req->auto_pause = req->force_pause; | |
8636 | req->enables |= cpu_to_le32( | |
8637 | PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); | |
8638 | } | |
c0c050c5 MC |
8639 | } |
8640 | } | |
8641 | ||
8642 | static void bnxt_hwrm_set_link_common(struct bnxt *bp, | |
8643 | struct hwrm_port_phy_cfg_input *req) | |
8644 | { | |
8645 | u8 autoneg = bp->link_info.autoneg; | |
8646 | u16 fw_link_speed = bp->link_info.req_link_speed; | |
68515a18 | 8647 | u16 advertising = bp->link_info.advertising; |
c0c050c5 MC |
8648 | |
8649 | if (autoneg & BNXT_AUTONEG_SPEED) { | |
8650 | req->auto_mode |= | |
11f15ed3 | 8651 | PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK; |
c0c050c5 MC |
8652 | |
8653 | req->enables |= cpu_to_le32( | |
8654 | PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); | |
8655 | req->auto_link_speed_mask = cpu_to_le16(advertising); | |
8656 | ||
8657 | req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); | |
8658 | req->flags |= | |
8659 | cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); | |
8660 | } else { | |
8661 | req->force_link_speed = cpu_to_le16(fw_link_speed); | |
8662 | req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); | |
8663 | } | |
8664 | ||
c0c050c5 MC |
8665 | /* tell chimp that the setting takes effect immediately */ |
8666 | req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); | |
8667 | } | |
8668 | ||
8669 | int bnxt_hwrm_set_pause(struct bnxt *bp) | |
8670 | { | |
8671 | struct hwrm_port_phy_cfg_input req = {0}; | |
8672 | int rc; | |
8673 | ||
8674 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); | |
8675 | bnxt_hwrm_set_pause_common(bp, &req); | |
8676 | ||
8677 | if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || | |
8678 | bp->link_info.force_link_chng) | |
8679 | bnxt_hwrm_set_link_common(bp, &req); | |
8680 | ||
8681 | mutex_lock(&bp->hwrm_cmd_lock); | |
8682 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8683 | if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { | |
8684 | /* since changing of pause setting doesn't trigger any link | |
8685 | * change event, the driver needs to update the current pause | |
8686 | * result upon successfully return of the phy_cfg command | |
8687 | */ | |
8688 | bp->link_info.pause = | |
8689 | bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; | |
8690 | bp->link_info.auto_pause_setting = 0; | |
8691 | if (!bp->link_info.force_link_chng) | |
8692 | bnxt_report_link(bp); | |
8693 | } | |
8694 | bp->link_info.force_link_chng = false; | |
8695 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8696 | return rc; | |
8697 | } | |
8698 | ||
939f7f0c MC |
8699 | static void bnxt_hwrm_set_eee(struct bnxt *bp, |
8700 | struct hwrm_port_phy_cfg_input *req) | |
8701 | { | |
8702 | struct ethtool_eee *eee = &bp->eee; | |
8703 | ||
8704 | if (eee->eee_enabled) { | |
8705 | u16 eee_speeds; | |
8706 | u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE; | |
8707 | ||
8708 | if (eee->tx_lpi_enabled) | |
8709 | flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE; | |
8710 | else | |
8711 | flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE; | |
8712 | ||
8713 | req->flags |= cpu_to_le32(flags); | |
8714 | eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); | |
8715 | req->eee_link_speed_mask = cpu_to_le16(eee_speeds); | |
8716 | req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer); | |
8717 | } else { | |
8718 | req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE); | |
8719 | } | |
8720 | } | |
8721 | ||
8722 | int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee) | |
c0c050c5 MC |
8723 | { |
8724 | struct hwrm_port_phy_cfg_input req = {0}; | |
8725 | ||
8726 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); | |
8727 | if (set_pause) | |
8728 | bnxt_hwrm_set_pause_common(bp, &req); | |
8729 | ||
8730 | bnxt_hwrm_set_link_common(bp, &req); | |
939f7f0c MC |
8731 | |
8732 | if (set_eee) | |
8733 | bnxt_hwrm_set_eee(bp, &req); | |
c0c050c5 MC |
8734 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
8735 | } | |
8736 | ||
33f7d55f MC |
8737 | static int bnxt_hwrm_shutdown_link(struct bnxt *bp) |
8738 | { | |
8739 | struct hwrm_port_phy_cfg_input req = {0}; | |
8740 | ||
567b2abe | 8741 | if (!BNXT_SINGLE_PF(bp)) |
33f7d55f MC |
8742 | return 0; |
8743 | ||
8744 | if (pci_num_vf(bp->pdev)) | |
8745 | return 0; | |
8746 | ||
8747 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); | |
16d663a6 | 8748 | req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN); |
33f7d55f MC |
8749 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
8750 | } | |
8751 | ||
ec5d31e3 MC |
8752 | static int bnxt_fw_init_one(struct bnxt *bp); |
8753 | ||
25e1acd6 MC |
8754 | static int bnxt_hwrm_if_change(struct bnxt *bp, bool up) |
8755 | { | |
8756 | struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr; | |
8757 | struct hwrm_func_drv_if_change_input req = {0}; | |
ec5d31e3 MC |
8758 | bool resc_reinit = false, fw_reset = false; |
8759 | u32 flags = 0; | |
25e1acd6 MC |
8760 | int rc; |
8761 | ||
8762 | if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE)) | |
8763 | return 0; | |
8764 | ||
8765 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1); | |
8766 | if (up) | |
8767 | req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP); | |
8768 | mutex_lock(&bp->hwrm_cmd_lock); | |
8769 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
ec5d31e3 MC |
8770 | if (!rc) |
8771 | flags = le32_to_cpu(resp->flags); | |
25e1acd6 | 8772 | mutex_unlock(&bp->hwrm_cmd_lock); |
ec5d31e3 MC |
8773 | if (rc) |
8774 | return rc; | |
25e1acd6 | 8775 | |
ec5d31e3 MC |
8776 | if (!up) |
8777 | return 0; | |
25e1acd6 | 8778 | |
ec5d31e3 MC |
8779 | if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE) |
8780 | resc_reinit = true; | |
8781 | if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE) | |
8782 | fw_reset = true; | |
8783 | ||
3bc7d4a3 MC |
8784 | if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) { |
8785 | netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n"); | |
8786 | return -ENODEV; | |
8787 | } | |
ec5d31e3 MC |
8788 | if (resc_reinit || fw_reset) { |
8789 | if (fw_reset) { | |
f3a6d206 VV |
8790 | if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) |
8791 | bnxt_ulp_stop(bp); | |
325f85f3 MC |
8792 | bnxt_free_ctx_mem(bp); |
8793 | kfree(bp->ctx); | |
8794 | bp->ctx = NULL; | |
ec5d31e3 MC |
8795 | rc = bnxt_fw_init_one(bp); |
8796 | if (rc) { | |
8797 | set_bit(BNXT_STATE_ABORT_ERR, &bp->state); | |
8798 | return rc; | |
8799 | } | |
8800 | bnxt_clear_int_mode(bp); | |
8801 | rc = bnxt_init_int_mode(bp); | |
8802 | if (rc) { | |
8803 | netdev_err(bp->dev, "init int mode failed\n"); | |
8804 | return rc; | |
8805 | } | |
8806 | set_bit(BNXT_STATE_FW_RESET_DET, &bp->state); | |
8807 | } | |
8808 | if (BNXT_NEW_RM(bp)) { | |
8809 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
8810 | ||
8811 | rc = bnxt_hwrm_func_resc_qcaps(bp, true); | |
8812 | hw_resc->resv_cp_rings = 0; | |
8813 | hw_resc->resv_stat_ctxs = 0; | |
8814 | hw_resc->resv_irqs = 0; | |
8815 | hw_resc->resv_tx_rings = 0; | |
8816 | hw_resc->resv_rx_rings = 0; | |
8817 | hw_resc->resv_hw_ring_grps = 0; | |
8818 | hw_resc->resv_vnics = 0; | |
8819 | if (!fw_reset) { | |
8820 | bp->tx_nr_rings = 0; | |
8821 | bp->rx_nr_rings = 0; | |
8822 | } | |
8823 | } | |
25e1acd6 | 8824 | } |
ec5d31e3 | 8825 | return 0; |
25e1acd6 MC |
8826 | } |
8827 | ||
5ad2cbee MC |
8828 | static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) |
8829 | { | |
8830 | struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
8831 | struct hwrm_port_led_qcaps_input req = {0}; | |
8832 | struct bnxt_pf_info *pf = &bp->pf; | |
8833 | int rc; | |
8834 | ||
ba642ab7 | 8835 | bp->num_leds = 0; |
5ad2cbee MC |
8836 | if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601) |
8837 | return 0; | |
8838 | ||
8839 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1); | |
8840 | req.port_id = cpu_to_le16(pf->port_id); | |
8841 | mutex_lock(&bp->hwrm_cmd_lock); | |
8842 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8843 | if (rc) { | |
8844 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8845 | return rc; | |
8846 | } | |
8847 | if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) { | |
8848 | int i; | |
8849 | ||
8850 | bp->num_leds = resp->num_leds; | |
8851 | memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) * | |
8852 | bp->num_leds); | |
8853 | for (i = 0; i < bp->num_leds; i++) { | |
8854 | struct bnxt_led_info *led = &bp->leds[i]; | |
8855 | __le16 caps = led->led_state_caps; | |
8856 | ||
8857 | if (!led->led_group_id || | |
8858 | !BNXT_LED_ALT_BLINK_CAP(caps)) { | |
8859 | bp->num_leds = 0; | |
8860 | break; | |
8861 | } | |
8862 | } | |
8863 | } | |
8864 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8865 | return 0; | |
8866 | } | |
8867 | ||
5282db6c MC |
8868 | int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp) |
8869 | { | |
8870 | struct hwrm_wol_filter_alloc_input req = {0}; | |
8871 | struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
8872 | int rc; | |
8873 | ||
8874 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1); | |
8875 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
8876 | req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT; | |
8877 | req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS); | |
8878 | memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN); | |
8879 | mutex_lock(&bp->hwrm_cmd_lock); | |
8880 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8881 | if (!rc) | |
8882 | bp->wol_filter_id = resp->wol_filter_id; | |
8883 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8884 | return rc; | |
8885 | } | |
8886 | ||
8887 | int bnxt_hwrm_free_wol_fltr(struct bnxt *bp) | |
8888 | { | |
8889 | struct hwrm_wol_filter_free_input req = {0}; | |
8890 | int rc; | |
8891 | ||
8892 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1); | |
8893 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
8894 | req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID); | |
8895 | req.wol_filter_id = bp->wol_filter_id; | |
8896 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8897 | return rc; | |
8898 | } | |
8899 | ||
c1ef146a MC |
8900 | static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle) |
8901 | { | |
8902 | struct hwrm_wol_filter_qcfg_input req = {0}; | |
8903 | struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
8904 | u16 next_handle = 0; | |
8905 | int rc; | |
8906 | ||
8907 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1); | |
8908 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
8909 | req.handle = cpu_to_le16(handle); | |
8910 | mutex_lock(&bp->hwrm_cmd_lock); | |
8911 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8912 | if (!rc) { | |
8913 | next_handle = le16_to_cpu(resp->next_handle); | |
8914 | if (next_handle != 0) { | |
8915 | if (resp->wol_type == | |
8916 | WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) { | |
8917 | bp->wol = 1; | |
8918 | bp->wol_filter_id = resp->wol_filter_id; | |
8919 | } | |
8920 | } | |
8921 | } | |
8922 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8923 | return next_handle; | |
8924 | } | |
8925 | ||
8926 | static void bnxt_get_wol_settings(struct bnxt *bp) | |
8927 | { | |
8928 | u16 handle = 0; | |
8929 | ||
ba642ab7 | 8930 | bp->wol = 0; |
c1ef146a MC |
8931 | if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP)) |
8932 | return; | |
8933 | ||
8934 | do { | |
8935 | handle = bnxt_hwrm_get_wol_fltrs(bp, handle); | |
8936 | } while (handle && handle != 0xffff); | |
8937 | } | |
8938 | ||
cde49a42 VV |
8939 | #ifdef CONFIG_BNXT_HWMON |
8940 | static ssize_t bnxt_show_temp(struct device *dev, | |
8941 | struct device_attribute *devattr, char *buf) | |
8942 | { | |
8943 | struct hwrm_temp_monitor_query_input req = {0}; | |
8944 | struct hwrm_temp_monitor_query_output *resp; | |
8945 | struct bnxt *bp = dev_get_drvdata(dev); | |
8946 | u32 temp = 0; | |
8947 | ||
8948 | resp = bp->hwrm_cmd_resp_addr; | |
8949 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1); | |
8950 | mutex_lock(&bp->hwrm_cmd_lock); | |
8951 | if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT)) | |
8952 | temp = resp->temp * 1000; /* display millidegree */ | |
8953 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8954 | ||
8955 | return sprintf(buf, "%u\n", temp); | |
8956 | } | |
8957 | static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0); | |
8958 | ||
8959 | static struct attribute *bnxt_attrs[] = { | |
8960 | &sensor_dev_attr_temp1_input.dev_attr.attr, | |
8961 | NULL | |
8962 | }; | |
8963 | ATTRIBUTE_GROUPS(bnxt); | |
8964 | ||
8965 | static void bnxt_hwmon_close(struct bnxt *bp) | |
8966 | { | |
8967 | if (bp->hwmon_dev) { | |
8968 | hwmon_device_unregister(bp->hwmon_dev); | |
8969 | bp->hwmon_dev = NULL; | |
8970 | } | |
8971 | } | |
8972 | ||
8973 | static void bnxt_hwmon_open(struct bnxt *bp) | |
8974 | { | |
8975 | struct pci_dev *pdev = bp->pdev; | |
8976 | ||
ba642ab7 MC |
8977 | if (bp->hwmon_dev) |
8978 | return; | |
8979 | ||
cde49a42 VV |
8980 | bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, |
8981 | DRV_MODULE_NAME, bp, | |
8982 | bnxt_groups); | |
8983 | if (IS_ERR(bp->hwmon_dev)) { | |
8984 | bp->hwmon_dev = NULL; | |
8985 | dev_warn(&pdev->dev, "Cannot register hwmon device\n"); | |
8986 | } | |
8987 | } | |
8988 | #else | |
8989 | static void bnxt_hwmon_close(struct bnxt *bp) | |
8990 | { | |
8991 | } | |
8992 | ||
8993 | static void bnxt_hwmon_open(struct bnxt *bp) | |
8994 | { | |
8995 | } | |
8996 | #endif | |
8997 | ||
939f7f0c MC |
8998 | static bool bnxt_eee_config_ok(struct bnxt *bp) |
8999 | { | |
9000 | struct ethtool_eee *eee = &bp->eee; | |
9001 | struct bnxt_link_info *link_info = &bp->link_info; | |
9002 | ||
9003 | if (!(bp->flags & BNXT_FLAG_EEE_CAP)) | |
9004 | return true; | |
9005 | ||
9006 | if (eee->eee_enabled) { | |
9007 | u32 advertising = | |
9008 | _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); | |
9009 | ||
9010 | if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { | |
9011 | eee->eee_enabled = 0; | |
9012 | return false; | |
9013 | } | |
9014 | if (eee->advertised & ~advertising) { | |
9015 | eee->advertised = advertising & eee->supported; | |
9016 | return false; | |
9017 | } | |
9018 | } | |
9019 | return true; | |
9020 | } | |
9021 | ||
c0c050c5 MC |
9022 | static int bnxt_update_phy_setting(struct bnxt *bp) |
9023 | { | |
9024 | int rc; | |
9025 | bool update_link = false; | |
9026 | bool update_pause = false; | |
939f7f0c | 9027 | bool update_eee = false; |
c0c050c5 MC |
9028 | struct bnxt_link_info *link_info = &bp->link_info; |
9029 | ||
9030 | rc = bnxt_update_link(bp, true); | |
9031 | if (rc) { | |
9032 | netdev_err(bp->dev, "failed to update link (rc: %x)\n", | |
9033 | rc); | |
9034 | return rc; | |
9035 | } | |
33dac24a MC |
9036 | if (!BNXT_SINGLE_PF(bp)) |
9037 | return 0; | |
9038 | ||
c0c050c5 | 9039 | if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && |
c9ee9516 MC |
9040 | (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) != |
9041 | link_info->req_flow_ctrl) | |
c0c050c5 MC |
9042 | update_pause = true; |
9043 | if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && | |
9044 | link_info->force_pause_setting != link_info->req_flow_ctrl) | |
9045 | update_pause = true; | |
c0c050c5 MC |
9046 | if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { |
9047 | if (BNXT_AUTO_MODE(link_info->auto_mode)) | |
9048 | update_link = true; | |
9049 | if (link_info->req_link_speed != link_info->force_link_speed) | |
9050 | update_link = true; | |
de73018f MC |
9051 | if (link_info->req_duplex != link_info->duplex_setting) |
9052 | update_link = true; | |
c0c050c5 MC |
9053 | } else { |
9054 | if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) | |
9055 | update_link = true; | |
9056 | if (link_info->advertising != link_info->auto_link_speeds) | |
9057 | update_link = true; | |
c0c050c5 MC |
9058 | } |
9059 | ||
16d663a6 MC |
9060 | /* The last close may have shutdown the link, so need to call |
9061 | * PHY_CFG to bring it back up. | |
9062 | */ | |
83d8f5e9 | 9063 | if (!bp->link_info.link_up) |
16d663a6 MC |
9064 | update_link = true; |
9065 | ||
939f7f0c MC |
9066 | if (!bnxt_eee_config_ok(bp)) |
9067 | update_eee = true; | |
9068 | ||
c0c050c5 | 9069 | if (update_link) |
939f7f0c | 9070 | rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee); |
c0c050c5 MC |
9071 | else if (update_pause) |
9072 | rc = bnxt_hwrm_set_pause(bp); | |
9073 | if (rc) { | |
9074 | netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", | |
9075 | rc); | |
9076 | return rc; | |
9077 | } | |
9078 | ||
9079 | return rc; | |
9080 | } | |
9081 | ||
11809490 JH |
9082 | /* Common routine to pre-map certain register block to different GRC window. |
9083 | * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows | |
9084 | * in PF and 3 windows in VF that can be customized to map in different | |
9085 | * register blocks. | |
9086 | */ | |
9087 | static void bnxt_preset_reg_win(struct bnxt *bp) | |
9088 | { | |
9089 | if (BNXT_PF(bp)) { | |
9090 | /* CAG registers map to GRC window #4 */ | |
9091 | writel(BNXT_CAG_REG_BASE, | |
9092 | bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); | |
9093 | } | |
9094 | } | |
9095 | ||
47558acd MC |
9096 | static int bnxt_init_dflt_ring_mode(struct bnxt *bp); |
9097 | ||
c0c050c5 MC |
9098 | static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) |
9099 | { | |
9100 | int rc = 0; | |
9101 | ||
11809490 | 9102 | bnxt_preset_reg_win(bp); |
c0c050c5 MC |
9103 | netif_carrier_off(bp->dev); |
9104 | if (irq_re_init) { | |
47558acd MC |
9105 | /* Reserve rings now if none were reserved at driver probe. */ |
9106 | rc = bnxt_init_dflt_ring_mode(bp); | |
9107 | if (rc) { | |
9108 | netdev_err(bp->dev, "Failed to reserve default rings at open\n"); | |
9109 | return rc; | |
9110 | } | |
c0c050c5 | 9111 | } |
1b3f0b75 | 9112 | rc = bnxt_reserve_rings(bp, irq_re_init); |
41e8d798 MC |
9113 | if (rc) |
9114 | return rc; | |
c0c050c5 MC |
9115 | if ((bp->flags & BNXT_FLAG_RFS) && |
9116 | !(bp->flags & BNXT_FLAG_USING_MSIX)) { | |
9117 | /* disable RFS if falling back to INTA */ | |
9118 | bp->dev->hw_features &= ~NETIF_F_NTUPLE; | |
9119 | bp->flags &= ~BNXT_FLAG_RFS; | |
9120 | } | |
9121 | ||
9122 | rc = bnxt_alloc_mem(bp, irq_re_init); | |
9123 | if (rc) { | |
9124 | netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); | |
9125 | goto open_err_free_mem; | |
9126 | } | |
9127 | ||
9128 | if (irq_re_init) { | |
9129 | bnxt_init_napi(bp); | |
9130 | rc = bnxt_request_irq(bp); | |
9131 | if (rc) { | |
9132 | netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); | |
c58387ab | 9133 | goto open_err_irq; |
c0c050c5 MC |
9134 | } |
9135 | } | |
9136 | ||
9137 | bnxt_enable_napi(bp); | |
cabfb09d | 9138 | bnxt_debug_dev_init(bp); |
c0c050c5 MC |
9139 | |
9140 | rc = bnxt_init_nic(bp, irq_re_init); | |
9141 | if (rc) { | |
9142 | netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); | |
9143 | goto open_err; | |
9144 | } | |
9145 | ||
9146 | if (link_re_init) { | |
e2dc9b6e | 9147 | mutex_lock(&bp->link_lock); |
c0c050c5 | 9148 | rc = bnxt_update_phy_setting(bp); |
e2dc9b6e | 9149 | mutex_unlock(&bp->link_lock); |
a1ef4a79 | 9150 | if (rc) { |
ba41d46f | 9151 | netdev_warn(bp->dev, "failed to update phy settings\n"); |
a1ef4a79 MC |
9152 | if (BNXT_SINGLE_PF(bp)) { |
9153 | bp->link_info.phy_retry = true; | |
9154 | bp->link_info.phy_retry_expires = | |
9155 | jiffies + 5 * HZ; | |
9156 | } | |
9157 | } | |
c0c050c5 MC |
9158 | } |
9159 | ||
7cdd5fc3 | 9160 | if (irq_re_init) |
ad51b8e9 | 9161 | udp_tunnel_get_rx_info(bp->dev); |
c0c050c5 | 9162 | |
caefe526 | 9163 | set_bit(BNXT_STATE_OPEN, &bp->state); |
c0c050c5 MC |
9164 | bnxt_enable_int(bp); |
9165 | /* Enable TX queues */ | |
9166 | bnxt_tx_enable(bp); | |
9167 | mod_timer(&bp->timer, jiffies + bp->current_interval); | |
10289bec MC |
9168 | /* Poll link status and check for SFP+ module status */ |
9169 | bnxt_get_port_module_status(bp); | |
c0c050c5 | 9170 | |
ee5c7fb3 SP |
9171 | /* VF-reps may need to be re-opened after the PF is re-opened */ |
9172 | if (BNXT_PF(bp)) | |
9173 | bnxt_vf_reps_open(bp); | |
c0c050c5 MC |
9174 | return 0; |
9175 | ||
9176 | open_err: | |
cabfb09d | 9177 | bnxt_debug_dev_exit(bp); |
c0c050c5 | 9178 | bnxt_disable_napi(bp); |
c58387ab VG |
9179 | |
9180 | open_err_irq: | |
c0c050c5 MC |
9181 | bnxt_del_napi(bp); |
9182 | ||
9183 | open_err_free_mem: | |
9184 | bnxt_free_skbs(bp); | |
9185 | bnxt_free_irq(bp); | |
9186 | bnxt_free_mem(bp, true); | |
9187 | return rc; | |
9188 | } | |
9189 | ||
9190 | /* rtnl_lock held */ | |
9191 | int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) | |
9192 | { | |
9193 | int rc = 0; | |
9194 | ||
9195 | rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); | |
9196 | if (rc) { | |
9197 | netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); | |
9198 | dev_close(bp->dev); | |
9199 | } | |
9200 | return rc; | |
9201 | } | |
9202 | ||
f7dc1ea6 MC |
9203 | /* rtnl_lock held, open the NIC half way by allocating all resources, but |
9204 | * NAPI, IRQ, and TX are not enabled. This is mainly used for offline | |
9205 | * self tests. | |
9206 | */ | |
9207 | int bnxt_half_open_nic(struct bnxt *bp) | |
9208 | { | |
9209 | int rc = 0; | |
9210 | ||
9211 | rc = bnxt_alloc_mem(bp, false); | |
9212 | if (rc) { | |
9213 | netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); | |
9214 | goto half_open_err; | |
9215 | } | |
9216 | rc = bnxt_init_nic(bp, false); | |
9217 | if (rc) { | |
9218 | netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); | |
9219 | goto half_open_err; | |
9220 | } | |
9221 | return 0; | |
9222 | ||
9223 | half_open_err: | |
9224 | bnxt_free_skbs(bp); | |
9225 | bnxt_free_mem(bp, false); | |
9226 | dev_close(bp->dev); | |
9227 | return rc; | |
9228 | } | |
9229 | ||
9230 | /* rtnl_lock held, this call can only be made after a previous successful | |
9231 | * call to bnxt_half_open_nic(). | |
9232 | */ | |
9233 | void bnxt_half_close_nic(struct bnxt *bp) | |
9234 | { | |
9235 | bnxt_hwrm_resource_free(bp, false, false); | |
9236 | bnxt_free_skbs(bp); | |
9237 | bnxt_free_mem(bp, false); | |
9238 | } | |
9239 | ||
c16d4ee0 MC |
9240 | static void bnxt_reenable_sriov(struct bnxt *bp) |
9241 | { | |
9242 | if (BNXT_PF(bp)) { | |
9243 | struct bnxt_pf_info *pf = &bp->pf; | |
9244 | int n = pf->active_vfs; | |
9245 | ||
9246 | if (n) | |
9247 | bnxt_cfg_hw_sriov(bp, &n, true); | |
9248 | } | |
9249 | } | |
9250 | ||
c0c050c5 MC |
9251 | static int bnxt_open(struct net_device *dev) |
9252 | { | |
9253 | struct bnxt *bp = netdev_priv(dev); | |
25e1acd6 | 9254 | int rc; |
c0c050c5 | 9255 | |
ec5d31e3 MC |
9256 | if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) { |
9257 | netdev_err(bp->dev, "A previous firmware reset did not complete, aborting\n"); | |
9258 | return -ENODEV; | |
9259 | } | |
9260 | ||
9261 | rc = bnxt_hwrm_if_change(bp, true); | |
25e1acd6 | 9262 | if (rc) |
ec5d31e3 MC |
9263 | return rc; |
9264 | rc = __bnxt_open_nic(bp, true, true); | |
9265 | if (rc) { | |
25e1acd6 | 9266 | bnxt_hwrm_if_change(bp, false); |
ec5d31e3 | 9267 | } else { |
f3a6d206 | 9268 | if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) { |
12de2ead | 9269 | if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { |
f3a6d206 | 9270 | bnxt_ulp_start(bp, 0); |
12de2ead MC |
9271 | bnxt_reenable_sriov(bp); |
9272 | } | |
ec5d31e3 MC |
9273 | } |
9274 | bnxt_hwmon_open(bp); | |
9275 | } | |
cde49a42 | 9276 | |
25e1acd6 | 9277 | return rc; |
c0c050c5 MC |
9278 | } |
9279 | ||
f9b76ebd MC |
9280 | static bool bnxt_drv_busy(struct bnxt *bp) |
9281 | { | |
9282 | return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) || | |
9283 | test_bit(BNXT_STATE_READ_STATS, &bp->state)); | |
9284 | } | |
9285 | ||
b8875ca3 MC |
9286 | static void bnxt_get_ring_stats(struct bnxt *bp, |
9287 | struct rtnl_link_stats64 *stats); | |
9288 | ||
86e953db MC |
9289 | static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init, |
9290 | bool link_re_init) | |
c0c050c5 | 9291 | { |
ee5c7fb3 SP |
9292 | /* Close the VF-reps before closing PF */ |
9293 | if (BNXT_PF(bp)) | |
9294 | bnxt_vf_reps_close(bp); | |
86e953db | 9295 | |
c0c050c5 MC |
9296 | /* Change device state to avoid TX queue wake up's */ |
9297 | bnxt_tx_disable(bp); | |
9298 | ||
caefe526 | 9299 | clear_bit(BNXT_STATE_OPEN, &bp->state); |
4cebdcec | 9300 | smp_mb__after_atomic(); |
f9b76ebd | 9301 | while (bnxt_drv_busy(bp)) |
4cebdcec | 9302 | msleep(20); |
c0c050c5 | 9303 | |
9d8bc097 | 9304 | /* Flush rings and and disable interrupts */ |
c0c050c5 MC |
9305 | bnxt_shutdown_nic(bp, irq_re_init); |
9306 | ||
9307 | /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ | |
9308 | ||
cabfb09d | 9309 | bnxt_debug_dev_exit(bp); |
c0c050c5 | 9310 | bnxt_disable_napi(bp); |
c0c050c5 MC |
9311 | del_timer_sync(&bp->timer); |
9312 | bnxt_free_skbs(bp); | |
9313 | ||
b8875ca3 MC |
9314 | /* Save ring stats before shutdown */ |
9315 | if (bp->bnapi) | |
9316 | bnxt_get_ring_stats(bp, &bp->net_stats_prev); | |
c0c050c5 MC |
9317 | if (irq_re_init) { |
9318 | bnxt_free_irq(bp); | |
9319 | bnxt_del_napi(bp); | |
9320 | } | |
9321 | bnxt_free_mem(bp, irq_re_init); | |
86e953db MC |
9322 | } |
9323 | ||
9324 | int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) | |
9325 | { | |
9326 | int rc = 0; | |
9327 | ||
3bc7d4a3 MC |
9328 | if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { |
9329 | /* If we get here, it means firmware reset is in progress | |
9330 | * while we are trying to close. We can safely proceed with | |
9331 | * the close because we are holding rtnl_lock(). Some firmware | |
9332 | * messages may fail as we proceed to close. We set the | |
9333 | * ABORT_ERR flag here so that the FW reset thread will later | |
9334 | * abort when it gets the rtnl_lock() and sees the flag. | |
9335 | */ | |
9336 | netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n"); | |
9337 | set_bit(BNXT_STATE_ABORT_ERR, &bp->state); | |
9338 | } | |
9339 | ||
86e953db MC |
9340 | #ifdef CONFIG_BNXT_SRIOV |
9341 | if (bp->sriov_cfg) { | |
9342 | rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, | |
9343 | !bp->sriov_cfg, | |
9344 | BNXT_SRIOV_CFG_WAIT_TMO); | |
9345 | if (rc) | |
9346 | netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); | |
9347 | } | |
9348 | #endif | |
9349 | __bnxt_close_nic(bp, irq_re_init, link_re_init); | |
c0c050c5 MC |
9350 | return rc; |
9351 | } | |
9352 | ||
9353 | static int bnxt_close(struct net_device *dev) | |
9354 | { | |
9355 | struct bnxt *bp = netdev_priv(dev); | |
9356 | ||
cde49a42 | 9357 | bnxt_hwmon_close(bp); |
c0c050c5 | 9358 | bnxt_close_nic(bp, true, true); |
33f7d55f | 9359 | bnxt_hwrm_shutdown_link(bp); |
25e1acd6 | 9360 | bnxt_hwrm_if_change(bp, false); |
c0c050c5 MC |
9361 | return 0; |
9362 | } | |
9363 | ||
0ca12be9 VV |
9364 | static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg, |
9365 | u16 *val) | |
9366 | { | |
9367 | struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr; | |
9368 | struct hwrm_port_phy_mdio_read_input req = {0}; | |
9369 | int rc; | |
9370 | ||
9371 | if (bp->hwrm_spec_code < 0x10a00) | |
9372 | return -EOPNOTSUPP; | |
9373 | ||
9374 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1); | |
9375 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
9376 | req.phy_addr = phy_addr; | |
9377 | req.reg_addr = cpu_to_le16(reg & 0x1f); | |
2730214d | 9378 | if (mdio_phy_id_is_c45(phy_addr)) { |
0ca12be9 VV |
9379 | req.cl45_mdio = 1; |
9380 | req.phy_addr = mdio_phy_id_prtad(phy_addr); | |
9381 | req.dev_addr = mdio_phy_id_devad(phy_addr); | |
9382 | req.reg_addr = cpu_to_le16(reg); | |
9383 | } | |
9384 | ||
9385 | mutex_lock(&bp->hwrm_cmd_lock); | |
9386 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
9387 | if (!rc) | |
9388 | *val = le16_to_cpu(resp->reg_data); | |
9389 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9390 | return rc; | |
9391 | } | |
9392 | ||
9393 | static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg, | |
9394 | u16 val) | |
9395 | { | |
9396 | struct hwrm_port_phy_mdio_write_input req = {0}; | |
9397 | ||
9398 | if (bp->hwrm_spec_code < 0x10a00) | |
9399 | return -EOPNOTSUPP; | |
9400 | ||
9401 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1); | |
9402 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
9403 | req.phy_addr = phy_addr; | |
9404 | req.reg_addr = cpu_to_le16(reg & 0x1f); | |
2730214d | 9405 | if (mdio_phy_id_is_c45(phy_addr)) { |
0ca12be9 VV |
9406 | req.cl45_mdio = 1; |
9407 | req.phy_addr = mdio_phy_id_prtad(phy_addr); | |
9408 | req.dev_addr = mdio_phy_id_devad(phy_addr); | |
9409 | req.reg_addr = cpu_to_le16(reg); | |
9410 | } | |
9411 | req.reg_data = cpu_to_le16(val); | |
9412 | ||
9413 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
9414 | } | |
9415 | ||
c0c050c5 MC |
9416 | /* rtnl_lock held */ |
9417 | static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
9418 | { | |
0ca12be9 VV |
9419 | struct mii_ioctl_data *mdio = if_mii(ifr); |
9420 | struct bnxt *bp = netdev_priv(dev); | |
9421 | int rc; | |
9422 | ||
c0c050c5 MC |
9423 | switch (cmd) { |
9424 | case SIOCGMIIPHY: | |
0ca12be9 VV |
9425 | mdio->phy_id = bp->link_info.phy_addr; |
9426 | ||
c0c050c5 MC |
9427 | /* fallthru */ |
9428 | case SIOCGMIIREG: { | |
0ca12be9 VV |
9429 | u16 mii_regval = 0; |
9430 | ||
c0c050c5 MC |
9431 | if (!netif_running(dev)) |
9432 | return -EAGAIN; | |
9433 | ||
0ca12be9 VV |
9434 | rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num, |
9435 | &mii_regval); | |
9436 | mdio->val_out = mii_regval; | |
9437 | return rc; | |
c0c050c5 MC |
9438 | } |
9439 | ||
9440 | case SIOCSMIIREG: | |
9441 | if (!netif_running(dev)) | |
9442 | return -EAGAIN; | |
9443 | ||
0ca12be9 VV |
9444 | return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num, |
9445 | mdio->val_in); | |
c0c050c5 MC |
9446 | |
9447 | default: | |
9448 | /* do nothing */ | |
9449 | break; | |
9450 | } | |
9451 | return -EOPNOTSUPP; | |
9452 | } | |
9453 | ||
b8875ca3 MC |
9454 | static void bnxt_get_ring_stats(struct bnxt *bp, |
9455 | struct rtnl_link_stats64 *stats) | |
c0c050c5 | 9456 | { |
b8875ca3 | 9457 | int i; |
c0c050c5 | 9458 | |
c0c050c5 | 9459 | |
c0c050c5 MC |
9460 | for (i = 0; i < bp->cp_nr_rings; i++) { |
9461 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
9462 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
9463 | struct ctx_hw_stats *hw_stats = cpr->hw_stats; | |
9464 | ||
9465 | stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts); | |
9466 | stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts); | |
9467 | stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts); | |
9468 | ||
9469 | stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts); | |
9470 | stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts); | |
9471 | stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts); | |
9472 | ||
9473 | stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes); | |
9474 | stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes); | |
9475 | stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes); | |
9476 | ||
9477 | stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes); | |
9478 | stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes); | |
9479 | stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes); | |
9480 | ||
9481 | stats->rx_missed_errors += | |
9482 | le64_to_cpu(hw_stats->rx_discard_pkts); | |
9483 | ||
9484 | stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts); | |
9485 | ||
c0c050c5 MC |
9486 | stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts); |
9487 | } | |
b8875ca3 MC |
9488 | } |
9489 | ||
9490 | static void bnxt_add_prev_stats(struct bnxt *bp, | |
9491 | struct rtnl_link_stats64 *stats) | |
9492 | { | |
9493 | struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev; | |
9494 | ||
9495 | stats->rx_packets += prev_stats->rx_packets; | |
9496 | stats->tx_packets += prev_stats->tx_packets; | |
9497 | stats->rx_bytes += prev_stats->rx_bytes; | |
9498 | stats->tx_bytes += prev_stats->tx_bytes; | |
9499 | stats->rx_missed_errors += prev_stats->rx_missed_errors; | |
9500 | stats->multicast += prev_stats->multicast; | |
9501 | stats->tx_dropped += prev_stats->tx_dropped; | |
9502 | } | |
9503 | ||
9504 | static void | |
9505 | bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) | |
9506 | { | |
9507 | struct bnxt *bp = netdev_priv(dev); | |
9508 | ||
9509 | set_bit(BNXT_STATE_READ_STATS, &bp->state); | |
9510 | /* Make sure bnxt_close_nic() sees that we are reading stats before | |
9511 | * we check the BNXT_STATE_OPEN flag. | |
9512 | */ | |
9513 | smp_mb__after_atomic(); | |
9514 | if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { | |
9515 | clear_bit(BNXT_STATE_READ_STATS, &bp->state); | |
9516 | *stats = bp->net_stats_prev; | |
9517 | return; | |
9518 | } | |
9519 | ||
9520 | bnxt_get_ring_stats(bp, stats); | |
9521 | bnxt_add_prev_stats(bp, stats); | |
c0c050c5 | 9522 | |
9947f83f MC |
9523 | if (bp->flags & BNXT_FLAG_PORT_STATS) { |
9524 | struct rx_port_stats *rx = bp->hw_rx_port_stats; | |
9525 | struct tx_port_stats *tx = bp->hw_tx_port_stats; | |
9526 | ||
9527 | stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames); | |
9528 | stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames); | |
9529 | stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) + | |
9530 | le64_to_cpu(rx->rx_ovrsz_frames) + | |
9531 | le64_to_cpu(rx->rx_runt_frames); | |
9532 | stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) + | |
9533 | le64_to_cpu(rx->rx_jbr_frames); | |
9534 | stats->collisions = le64_to_cpu(tx->tx_total_collisions); | |
9535 | stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns); | |
9536 | stats->tx_errors = le64_to_cpu(tx->tx_err); | |
9537 | } | |
f9b76ebd | 9538 | clear_bit(BNXT_STATE_READ_STATS, &bp->state); |
c0c050c5 MC |
9539 | } |
9540 | ||
9541 | static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) | |
9542 | { | |
9543 | struct net_device *dev = bp->dev; | |
9544 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; | |
9545 | struct netdev_hw_addr *ha; | |
9546 | u8 *haddr; | |
9547 | int mc_count = 0; | |
9548 | bool update = false; | |
9549 | int off = 0; | |
9550 | ||
9551 | netdev_for_each_mc_addr(ha, dev) { | |
9552 | if (mc_count >= BNXT_MAX_MC_ADDRS) { | |
9553 | *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; | |
9554 | vnic->mc_list_count = 0; | |
9555 | return false; | |
9556 | } | |
9557 | haddr = ha->addr; | |
9558 | if (!ether_addr_equal(haddr, vnic->mc_list + off)) { | |
9559 | memcpy(vnic->mc_list + off, haddr, ETH_ALEN); | |
9560 | update = true; | |
9561 | } | |
9562 | off += ETH_ALEN; | |
9563 | mc_count++; | |
9564 | } | |
9565 | if (mc_count) | |
9566 | *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; | |
9567 | ||
9568 | if (mc_count != vnic->mc_list_count) { | |
9569 | vnic->mc_list_count = mc_count; | |
9570 | update = true; | |
9571 | } | |
9572 | return update; | |
9573 | } | |
9574 | ||
9575 | static bool bnxt_uc_list_updated(struct bnxt *bp) | |
9576 | { | |
9577 | struct net_device *dev = bp->dev; | |
9578 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; | |
9579 | struct netdev_hw_addr *ha; | |
9580 | int off = 0; | |
9581 | ||
9582 | if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) | |
9583 | return true; | |
9584 | ||
9585 | netdev_for_each_uc_addr(ha, dev) { | |
9586 | if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) | |
9587 | return true; | |
9588 | ||
9589 | off += ETH_ALEN; | |
9590 | } | |
9591 | return false; | |
9592 | } | |
9593 | ||
9594 | static void bnxt_set_rx_mode(struct net_device *dev) | |
9595 | { | |
9596 | struct bnxt *bp = netdev_priv(dev); | |
268d0895 | 9597 | struct bnxt_vnic_info *vnic; |
c0c050c5 MC |
9598 | bool mc_update = false; |
9599 | bool uc_update; | |
268d0895 | 9600 | u32 mask; |
c0c050c5 | 9601 | |
268d0895 | 9602 | if (!test_bit(BNXT_STATE_OPEN, &bp->state)) |
c0c050c5 MC |
9603 | return; |
9604 | ||
268d0895 MC |
9605 | vnic = &bp->vnic_info[0]; |
9606 | mask = vnic->rx_mask; | |
c0c050c5 MC |
9607 | mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | |
9608 | CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | | |
30e33848 MC |
9609 | CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST | |
9610 | CFA_L2_SET_RX_MASK_REQ_MASK_BCAST); | |
c0c050c5 | 9611 | |
17c71ac3 | 9612 | if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) |
c0c050c5 MC |
9613 | mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; |
9614 | ||
9615 | uc_update = bnxt_uc_list_updated(bp); | |
9616 | ||
30e33848 MC |
9617 | if (dev->flags & IFF_BROADCAST) |
9618 | mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; | |
c0c050c5 MC |
9619 | if (dev->flags & IFF_ALLMULTI) { |
9620 | mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; | |
9621 | vnic->mc_list_count = 0; | |
9622 | } else { | |
9623 | mc_update = bnxt_mc_list_updated(bp, &mask); | |
9624 | } | |
9625 | ||
9626 | if (mask != vnic->rx_mask || uc_update || mc_update) { | |
9627 | vnic->rx_mask = mask; | |
9628 | ||
9629 | set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); | |
c213eae8 | 9630 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
9631 | } |
9632 | } | |
9633 | ||
b664f008 | 9634 | static int bnxt_cfg_rx_mode(struct bnxt *bp) |
c0c050c5 MC |
9635 | { |
9636 | struct net_device *dev = bp->dev; | |
9637 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; | |
9638 | struct netdev_hw_addr *ha; | |
9639 | int i, off = 0, rc; | |
9640 | bool uc_update; | |
9641 | ||
9642 | netif_addr_lock_bh(dev); | |
9643 | uc_update = bnxt_uc_list_updated(bp); | |
9644 | netif_addr_unlock_bh(dev); | |
9645 | ||
9646 | if (!uc_update) | |
9647 | goto skip_uc; | |
9648 | ||
9649 | mutex_lock(&bp->hwrm_cmd_lock); | |
9650 | for (i = 1; i < vnic->uc_filter_count; i++) { | |
9651 | struct hwrm_cfa_l2_filter_free_input req = {0}; | |
9652 | ||
9653 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1, | |
9654 | -1); | |
9655 | ||
9656 | req.l2_filter_id = vnic->fw_l2_filter_id[i]; | |
9657 | ||
9658 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
9659 | HWRM_CMD_TIMEOUT); | |
9660 | } | |
9661 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9662 | ||
9663 | vnic->uc_filter_count = 1; | |
9664 | ||
9665 | netif_addr_lock_bh(dev); | |
9666 | if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { | |
9667 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; | |
9668 | } else { | |
9669 | netdev_for_each_uc_addr(ha, dev) { | |
9670 | memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); | |
9671 | off += ETH_ALEN; | |
9672 | vnic->uc_filter_count++; | |
9673 | } | |
9674 | } | |
9675 | netif_addr_unlock_bh(dev); | |
9676 | ||
9677 | for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { | |
9678 | rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); | |
9679 | if (rc) { | |
9680 | netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", | |
9681 | rc); | |
9682 | vnic->uc_filter_count = i; | |
b664f008 | 9683 | return rc; |
c0c050c5 MC |
9684 | } |
9685 | } | |
9686 | ||
9687 | skip_uc: | |
9688 | rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); | |
b4e30e8e MC |
9689 | if (rc && vnic->mc_list_count) { |
9690 | netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n", | |
9691 | rc); | |
9692 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; | |
9693 | vnic->mc_list_count = 0; | |
9694 | rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); | |
9695 | } | |
c0c050c5 | 9696 | if (rc) |
b4e30e8e | 9697 | netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n", |
c0c050c5 | 9698 | rc); |
b664f008 MC |
9699 | |
9700 | return rc; | |
c0c050c5 MC |
9701 | } |
9702 | ||
2773dfb2 MC |
9703 | static bool bnxt_can_reserve_rings(struct bnxt *bp) |
9704 | { | |
9705 | #ifdef CONFIG_BNXT_SRIOV | |
f1ca94de | 9706 | if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) { |
2773dfb2 MC |
9707 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; |
9708 | ||
9709 | /* No minimum rings were provisioned by the PF. Don't | |
9710 | * reserve rings by default when device is down. | |
9711 | */ | |
9712 | if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings) | |
9713 | return true; | |
9714 | ||
9715 | if (!netif_running(bp->dev)) | |
9716 | return false; | |
9717 | } | |
9718 | #endif | |
9719 | return true; | |
9720 | } | |
9721 | ||
8079e8f1 MC |
9722 | /* If the chip and firmware supports RFS */ |
9723 | static bool bnxt_rfs_supported(struct bnxt *bp) | |
9724 | { | |
e969ae5b | 9725 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
41136ab3 | 9726 | if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) |
e969ae5b | 9727 | return true; |
41e8d798 | 9728 | return false; |
e969ae5b | 9729 | } |
8079e8f1 MC |
9730 | if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) |
9731 | return true; | |
ae10ae74 MC |
9732 | if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) |
9733 | return true; | |
8079e8f1 MC |
9734 | return false; |
9735 | } | |
9736 | ||
9737 | /* If runtime conditions support RFS */ | |
2bcfa6f6 MC |
9738 | static bool bnxt_rfs_capable(struct bnxt *bp) |
9739 | { | |
9740 | #ifdef CONFIG_RFS_ACCEL | |
8079e8f1 | 9741 | int vnics, max_vnics, max_rss_ctxs; |
2bcfa6f6 | 9742 | |
41e8d798 | 9743 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
ac33906c | 9744 | return bnxt_rfs_supported(bp); |
2773dfb2 | 9745 | if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp)) |
2bcfa6f6 MC |
9746 | return false; |
9747 | ||
9748 | vnics = 1 + bp->rx_nr_rings; | |
8079e8f1 MC |
9749 | max_vnics = bnxt_get_max_func_vnics(bp); |
9750 | max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp); | |
ae10ae74 MC |
9751 | |
9752 | /* RSS contexts not a limiting factor */ | |
9753 | if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) | |
9754 | max_rss_ctxs = max_vnics; | |
8079e8f1 | 9755 | if (vnics > max_vnics || vnics > max_rss_ctxs) { |
6a1eef5b MC |
9756 | if (bp->rx_nr_rings > 1) |
9757 | netdev_warn(bp->dev, | |
9758 | "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n", | |
9759 | min(max_rss_ctxs - 1, max_vnics - 1)); | |
2bcfa6f6 | 9760 | return false; |
a2304909 | 9761 | } |
2bcfa6f6 | 9762 | |
f1ca94de | 9763 | if (!BNXT_NEW_RM(bp)) |
6a1eef5b MC |
9764 | return true; |
9765 | ||
9766 | if (vnics == bp->hw_resc.resv_vnics) | |
9767 | return true; | |
9768 | ||
780baad4 | 9769 | bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics); |
6a1eef5b MC |
9770 | if (vnics <= bp->hw_resc.resv_vnics) |
9771 | return true; | |
9772 | ||
9773 | netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n"); | |
780baad4 | 9774 | bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1); |
6a1eef5b | 9775 | return false; |
2bcfa6f6 MC |
9776 | #else |
9777 | return false; | |
9778 | #endif | |
9779 | } | |
9780 | ||
c0c050c5 MC |
9781 | static netdev_features_t bnxt_fix_features(struct net_device *dev, |
9782 | netdev_features_t features) | |
9783 | { | |
2bcfa6f6 MC |
9784 | struct bnxt *bp = netdev_priv(dev); |
9785 | ||
a2304909 | 9786 | if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp)) |
2bcfa6f6 | 9787 | features &= ~NETIF_F_NTUPLE; |
5a9f6b23 | 9788 | |
1054aee8 MC |
9789 | if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) |
9790 | features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); | |
9791 | ||
9792 | if (!(features & NETIF_F_GRO)) | |
9793 | features &= ~NETIF_F_GRO_HW; | |
9794 | ||
9795 | if (features & NETIF_F_GRO_HW) | |
9796 | features &= ~NETIF_F_LRO; | |
9797 | ||
5a9f6b23 MC |
9798 | /* Both CTAG and STAG VLAN accelaration on the RX side have to be |
9799 | * turned on or off together. | |
9800 | */ | |
9801 | if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) != | |
9802 | (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) { | |
9803 | if (dev->features & NETIF_F_HW_VLAN_CTAG_RX) | |
9804 | features &= ~(NETIF_F_HW_VLAN_CTAG_RX | | |
9805 | NETIF_F_HW_VLAN_STAG_RX); | |
9806 | else | |
9807 | features |= NETIF_F_HW_VLAN_CTAG_RX | | |
9808 | NETIF_F_HW_VLAN_STAG_RX; | |
9809 | } | |
cf6645f8 MC |
9810 | #ifdef CONFIG_BNXT_SRIOV |
9811 | if (BNXT_VF(bp)) { | |
9812 | if (bp->vf.vlan) { | |
9813 | features &= ~(NETIF_F_HW_VLAN_CTAG_RX | | |
9814 | NETIF_F_HW_VLAN_STAG_RX); | |
9815 | } | |
9816 | } | |
9817 | #endif | |
c0c050c5 MC |
9818 | return features; |
9819 | } | |
9820 | ||
9821 | static int bnxt_set_features(struct net_device *dev, netdev_features_t features) | |
9822 | { | |
9823 | struct bnxt *bp = netdev_priv(dev); | |
9824 | u32 flags = bp->flags; | |
9825 | u32 changes; | |
9826 | int rc = 0; | |
9827 | bool re_init = false; | |
9828 | bool update_tpa = false; | |
9829 | ||
9830 | flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; | |
1054aee8 | 9831 | if (features & NETIF_F_GRO_HW) |
c0c050c5 | 9832 | flags |= BNXT_FLAG_GRO; |
1054aee8 | 9833 | else if (features & NETIF_F_LRO) |
c0c050c5 MC |
9834 | flags |= BNXT_FLAG_LRO; |
9835 | ||
bdbd1eb5 MC |
9836 | if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) |
9837 | flags &= ~BNXT_FLAG_TPA; | |
9838 | ||
c0c050c5 MC |
9839 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
9840 | flags |= BNXT_FLAG_STRIP_VLAN; | |
9841 | ||
9842 | if (features & NETIF_F_NTUPLE) | |
9843 | flags |= BNXT_FLAG_RFS; | |
9844 | ||
9845 | changes = flags ^ bp->flags; | |
9846 | if (changes & BNXT_FLAG_TPA) { | |
9847 | update_tpa = true; | |
9848 | if ((bp->flags & BNXT_FLAG_TPA) == 0 || | |
f45b7b78 MC |
9849 | (flags & BNXT_FLAG_TPA) == 0 || |
9850 | (bp->flags & BNXT_FLAG_CHIP_P5)) | |
c0c050c5 MC |
9851 | re_init = true; |
9852 | } | |
9853 | ||
9854 | if (changes & ~BNXT_FLAG_TPA) | |
9855 | re_init = true; | |
9856 | ||
9857 | if (flags != bp->flags) { | |
9858 | u32 old_flags = bp->flags; | |
9859 | ||
2bcfa6f6 | 9860 | if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { |
f45b7b78 | 9861 | bp->flags = flags; |
c0c050c5 MC |
9862 | if (update_tpa) |
9863 | bnxt_set_ring_params(bp); | |
9864 | return rc; | |
9865 | } | |
9866 | ||
9867 | if (re_init) { | |
9868 | bnxt_close_nic(bp, false, false); | |
f45b7b78 | 9869 | bp->flags = flags; |
c0c050c5 MC |
9870 | if (update_tpa) |
9871 | bnxt_set_ring_params(bp); | |
9872 | ||
9873 | return bnxt_open_nic(bp, false, false); | |
9874 | } | |
9875 | if (update_tpa) { | |
f45b7b78 | 9876 | bp->flags = flags; |
c0c050c5 MC |
9877 | rc = bnxt_set_tpa(bp, |
9878 | (flags & BNXT_FLAG_TPA) ? | |
9879 | true : false); | |
9880 | if (rc) | |
9881 | bp->flags = old_flags; | |
9882 | } | |
9883 | } | |
9884 | return rc; | |
9885 | } | |
9886 | ||
ffd77621 MC |
9887 | static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type, |
9888 | u32 ring_id, u32 *prod, u32 *cons) | |
9889 | { | |
9890 | struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr; | |
9891 | struct hwrm_dbg_ring_info_get_input req = {0}; | |
9892 | int rc; | |
9893 | ||
9894 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1); | |
9895 | req.ring_type = ring_type; | |
9896 | req.fw_ring_id = cpu_to_le32(ring_id); | |
9897 | mutex_lock(&bp->hwrm_cmd_lock); | |
9898 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
9899 | if (!rc) { | |
9900 | *prod = le32_to_cpu(resp->producer_index); | |
9901 | *cons = le32_to_cpu(resp->consumer_index); | |
9902 | } | |
9903 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9904 | return rc; | |
9905 | } | |
9906 | ||
9f554590 MC |
9907 | static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) |
9908 | { | |
b6ab4b01 | 9909 | struct bnxt_tx_ring_info *txr = bnapi->tx_ring; |
9f554590 MC |
9910 | int i = bnapi->index; |
9911 | ||
3b2b7d9d MC |
9912 | if (!txr) |
9913 | return; | |
9914 | ||
9f554590 MC |
9915 | netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", |
9916 | i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, | |
9917 | txr->tx_cons); | |
9918 | } | |
9919 | ||
9920 | static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) | |
9921 | { | |
b6ab4b01 | 9922 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
9f554590 MC |
9923 | int i = bnapi->index; |
9924 | ||
3b2b7d9d MC |
9925 | if (!rxr) |
9926 | return; | |
9927 | ||
9f554590 MC |
9928 | netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", |
9929 | i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, | |
9930 | rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, | |
9931 | rxr->rx_sw_agg_prod); | |
9932 | } | |
9933 | ||
9934 | static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) | |
9935 | { | |
9936 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
9937 | int i = bnapi->index; | |
9938 | ||
9939 | netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", | |
9940 | i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); | |
9941 | } | |
9942 | ||
c0c050c5 MC |
9943 | static void bnxt_dbg_dump_states(struct bnxt *bp) |
9944 | { | |
9945 | int i; | |
9946 | struct bnxt_napi *bnapi; | |
c0c050c5 MC |
9947 | |
9948 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
9949 | bnapi = bp->bnapi[i]; | |
c0c050c5 | 9950 | if (netif_msg_drv(bp)) { |
9f554590 MC |
9951 | bnxt_dump_tx_sw_state(bnapi); |
9952 | bnxt_dump_rx_sw_state(bnapi); | |
9953 | bnxt_dump_cp_sw_state(bnapi); | |
c0c050c5 MC |
9954 | } |
9955 | } | |
9956 | } | |
9957 | ||
6988bd92 | 9958 | static void bnxt_reset_task(struct bnxt *bp, bool silent) |
c0c050c5 | 9959 | { |
6988bd92 MC |
9960 | if (!silent) |
9961 | bnxt_dbg_dump_states(bp); | |
028de140 | 9962 | if (netif_running(bp->dev)) { |
b386cd36 MC |
9963 | int rc; |
9964 | ||
aa46dfff VV |
9965 | if (silent) { |
9966 | bnxt_close_nic(bp, false, false); | |
9967 | bnxt_open_nic(bp, false, false); | |
9968 | } else { | |
b386cd36 | 9969 | bnxt_ulp_stop(bp); |
aa46dfff VV |
9970 | bnxt_close_nic(bp, true, false); |
9971 | rc = bnxt_open_nic(bp, true, false); | |
9972 | bnxt_ulp_start(bp, rc); | |
9973 | } | |
028de140 | 9974 | } |
c0c050c5 MC |
9975 | } |
9976 | ||
0290bd29 | 9977 | static void bnxt_tx_timeout(struct net_device *dev, unsigned int txqueue) |
c0c050c5 MC |
9978 | { |
9979 | struct bnxt *bp = netdev_priv(dev); | |
9980 | ||
9981 | netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); | |
9982 | set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); | |
c213eae8 | 9983 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
9984 | } |
9985 | ||
acfb50e4 VV |
9986 | static void bnxt_fw_health_check(struct bnxt *bp) |
9987 | { | |
9988 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
9989 | u32 val; | |
9990 | ||
0797c10d | 9991 | if (!fw_health->enabled || test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) |
acfb50e4 VV |
9992 | return; |
9993 | ||
9994 | if (fw_health->tmr_counter) { | |
9995 | fw_health->tmr_counter--; | |
9996 | return; | |
9997 | } | |
9998 | ||
9999 | val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); | |
10000 | if (val == fw_health->last_fw_heartbeat) | |
10001 | goto fw_reset; | |
10002 | ||
10003 | fw_health->last_fw_heartbeat = val; | |
10004 | ||
10005 | val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); | |
10006 | if (val != fw_health->last_fw_reset_cnt) | |
10007 | goto fw_reset; | |
10008 | ||
10009 | fw_health->tmr_counter = fw_health->tmr_multiplier; | |
10010 | return; | |
10011 | ||
10012 | fw_reset: | |
10013 | set_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event); | |
10014 | bnxt_queue_sp_work(bp); | |
10015 | } | |
10016 | ||
e99e88a9 | 10017 | static void bnxt_timer(struct timer_list *t) |
c0c050c5 | 10018 | { |
e99e88a9 | 10019 | struct bnxt *bp = from_timer(bp, t, timer); |
c0c050c5 MC |
10020 | struct net_device *dev = bp->dev; |
10021 | ||
10022 | if (!netif_running(dev)) | |
10023 | return; | |
10024 | ||
10025 | if (atomic_read(&bp->intr_sem) != 0) | |
10026 | goto bnxt_restart_timer; | |
10027 | ||
acfb50e4 VV |
10028 | if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) |
10029 | bnxt_fw_health_check(bp); | |
10030 | ||
adcc331e MC |
10031 | if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) && |
10032 | bp->stats_coal_ticks) { | |
3bdf56c4 | 10033 | set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event); |
c213eae8 | 10034 | bnxt_queue_sp_work(bp); |
3bdf56c4 | 10035 | } |
5a84acbe SP |
10036 | |
10037 | if (bnxt_tc_flower_enabled(bp)) { | |
10038 | set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event); | |
10039 | bnxt_queue_sp_work(bp); | |
10040 | } | |
a1ef4a79 | 10041 | |
87d67f59 PC |
10042 | #ifdef CONFIG_RFS_ACCEL |
10043 | if ((bp->flags & BNXT_FLAG_RFS) && bp->ntp_fltr_count) { | |
10044 | set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); | |
10045 | bnxt_queue_sp_work(bp); | |
10046 | } | |
10047 | #endif /*CONFIG_RFS_ACCEL*/ | |
10048 | ||
a1ef4a79 MC |
10049 | if (bp->link_info.phy_retry) { |
10050 | if (time_after(jiffies, bp->link_info.phy_retry_expires)) { | |
acda6180 | 10051 | bp->link_info.phy_retry = false; |
a1ef4a79 MC |
10052 | netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n"); |
10053 | } else { | |
10054 | set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event); | |
10055 | bnxt_queue_sp_work(bp); | |
10056 | } | |
10057 | } | |
ffd77621 | 10058 | |
5313845f MC |
10059 | if ((bp->flags & BNXT_FLAG_CHIP_P5) && !bp->chip_rev && |
10060 | netif_carrier_ok(dev)) { | |
ffd77621 MC |
10061 | set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event); |
10062 | bnxt_queue_sp_work(bp); | |
10063 | } | |
c0c050c5 MC |
10064 | bnxt_restart_timer: |
10065 | mod_timer(&bp->timer, jiffies + bp->current_interval); | |
10066 | } | |
10067 | ||
a551ee94 | 10068 | static void bnxt_rtnl_lock_sp(struct bnxt *bp) |
6988bd92 | 10069 | { |
a551ee94 MC |
10070 | /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK |
10071 | * set. If the device is being closed, bnxt_close() may be holding | |
6988bd92 MC |
10072 | * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we |
10073 | * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). | |
10074 | */ | |
10075 | clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); | |
10076 | rtnl_lock(); | |
a551ee94 MC |
10077 | } |
10078 | ||
10079 | static void bnxt_rtnl_unlock_sp(struct bnxt *bp) | |
10080 | { | |
6988bd92 MC |
10081 | set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); |
10082 | rtnl_unlock(); | |
10083 | } | |
10084 | ||
a551ee94 MC |
10085 | /* Only called from bnxt_sp_task() */ |
10086 | static void bnxt_reset(struct bnxt *bp, bool silent) | |
10087 | { | |
10088 | bnxt_rtnl_lock_sp(bp); | |
10089 | if (test_bit(BNXT_STATE_OPEN, &bp->state)) | |
10090 | bnxt_reset_task(bp, silent); | |
10091 | bnxt_rtnl_unlock_sp(bp); | |
10092 | } | |
10093 | ||
230d1f0d MC |
10094 | static void bnxt_fw_reset_close(struct bnxt *bp) |
10095 | { | |
f3a6d206 | 10096 | bnxt_ulp_stop(bp); |
d4073028 VV |
10097 | /* When firmware is fatal state, disable PCI device to prevent |
10098 | * any potential bad DMAs before freeing kernel memory. | |
10099 | */ | |
10100 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) | |
10101 | pci_disable_device(bp->pdev); | |
230d1f0d | 10102 | __bnxt_close_nic(bp, true, false); |
230d1f0d MC |
10103 | bnxt_clear_int_mode(bp); |
10104 | bnxt_hwrm_func_drv_unrgtr(bp); | |
d4073028 VV |
10105 | if (pci_is_enabled(bp->pdev)) |
10106 | pci_disable_device(bp->pdev); | |
230d1f0d MC |
10107 | bnxt_free_ctx_mem(bp); |
10108 | kfree(bp->ctx); | |
10109 | bp->ctx = NULL; | |
10110 | } | |
10111 | ||
acfb50e4 VV |
10112 | static bool is_bnxt_fw_ok(struct bnxt *bp) |
10113 | { | |
10114 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
10115 | bool no_heartbeat = false, has_reset = false; | |
10116 | u32 val; | |
10117 | ||
10118 | val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); | |
10119 | if (val == fw_health->last_fw_heartbeat) | |
10120 | no_heartbeat = true; | |
10121 | ||
10122 | val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); | |
10123 | if (val != fw_health->last_fw_reset_cnt) | |
10124 | has_reset = true; | |
10125 | ||
10126 | if (!no_heartbeat && has_reset) | |
10127 | return true; | |
10128 | ||
10129 | return false; | |
10130 | } | |
10131 | ||
d1db9e16 MC |
10132 | /* rtnl_lock is acquired before calling this function */ |
10133 | static void bnxt_force_fw_reset(struct bnxt *bp) | |
10134 | { | |
10135 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
10136 | u32 wait_dsecs; | |
10137 | ||
10138 | if (!test_bit(BNXT_STATE_OPEN, &bp->state) || | |
10139 | test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) | |
10140 | return; | |
10141 | ||
10142 | set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
10143 | bnxt_fw_reset_close(bp); | |
10144 | wait_dsecs = fw_health->master_func_wait_dsecs; | |
10145 | if (fw_health->master) { | |
10146 | if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) | |
10147 | wait_dsecs = 0; | |
10148 | bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; | |
10149 | } else { | |
10150 | bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10; | |
10151 | wait_dsecs = fw_health->normal_func_wait_dsecs; | |
10152 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
10153 | } | |
4037eb71 VV |
10154 | |
10155 | bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs; | |
d1db9e16 MC |
10156 | bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs; |
10157 | bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); | |
10158 | } | |
10159 | ||
10160 | void bnxt_fw_exception(struct bnxt *bp) | |
10161 | { | |
a2b31e27 | 10162 | netdev_warn(bp->dev, "Detected firmware fatal condition, initiating reset\n"); |
d1db9e16 MC |
10163 | set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); |
10164 | bnxt_rtnl_lock_sp(bp); | |
10165 | bnxt_force_fw_reset(bp); | |
10166 | bnxt_rtnl_unlock_sp(bp); | |
10167 | } | |
10168 | ||
e72cb7d6 MC |
10169 | /* Returns the number of registered VFs, or 1 if VF configuration is pending, or |
10170 | * < 0 on error. | |
10171 | */ | |
10172 | static int bnxt_get_registered_vfs(struct bnxt *bp) | |
230d1f0d | 10173 | { |
e72cb7d6 | 10174 | #ifdef CONFIG_BNXT_SRIOV |
230d1f0d MC |
10175 | int rc; |
10176 | ||
e72cb7d6 MC |
10177 | if (!BNXT_PF(bp)) |
10178 | return 0; | |
10179 | ||
10180 | rc = bnxt_hwrm_func_qcfg(bp); | |
10181 | if (rc) { | |
10182 | netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc); | |
10183 | return rc; | |
10184 | } | |
10185 | if (bp->pf.registered_vfs) | |
10186 | return bp->pf.registered_vfs; | |
10187 | if (bp->sriov_cfg) | |
10188 | return 1; | |
10189 | #endif | |
10190 | return 0; | |
10191 | } | |
10192 | ||
10193 | void bnxt_fw_reset(struct bnxt *bp) | |
10194 | { | |
230d1f0d MC |
10195 | bnxt_rtnl_lock_sp(bp); |
10196 | if (test_bit(BNXT_STATE_OPEN, &bp->state) && | |
10197 | !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { | |
4037eb71 | 10198 | int n = 0, tmo; |
e72cb7d6 | 10199 | |
230d1f0d | 10200 | set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); |
e72cb7d6 MC |
10201 | if (bp->pf.active_vfs && |
10202 | !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) | |
10203 | n = bnxt_get_registered_vfs(bp); | |
10204 | if (n < 0) { | |
10205 | netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n", | |
10206 | n); | |
10207 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
10208 | dev_close(bp->dev); | |
10209 | goto fw_reset_exit; | |
10210 | } else if (n > 0) { | |
10211 | u16 vf_tmo_dsecs = n * 10; | |
10212 | ||
10213 | if (bp->fw_reset_max_dsecs < vf_tmo_dsecs) | |
10214 | bp->fw_reset_max_dsecs = vf_tmo_dsecs; | |
10215 | bp->fw_reset_state = | |
10216 | BNXT_FW_RESET_STATE_POLL_VF; | |
10217 | bnxt_queue_fw_reset_work(bp, HZ / 10); | |
10218 | goto fw_reset_exit; | |
230d1f0d MC |
10219 | } |
10220 | bnxt_fw_reset_close(bp); | |
4037eb71 VV |
10221 | if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { |
10222 | bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; | |
10223 | tmo = HZ / 10; | |
10224 | } else { | |
10225 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
10226 | tmo = bp->fw_reset_min_dsecs * HZ / 10; | |
10227 | } | |
10228 | bnxt_queue_fw_reset_work(bp, tmo); | |
230d1f0d MC |
10229 | } |
10230 | fw_reset_exit: | |
10231 | bnxt_rtnl_unlock_sp(bp); | |
10232 | } | |
10233 | ||
ffd77621 MC |
10234 | static void bnxt_chk_missed_irq(struct bnxt *bp) |
10235 | { | |
10236 | int i; | |
10237 | ||
10238 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
10239 | return; | |
10240 | ||
10241 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
10242 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
10243 | struct bnxt_cp_ring_info *cpr; | |
10244 | u32 fw_ring_id; | |
10245 | int j; | |
10246 | ||
10247 | if (!bnapi) | |
10248 | continue; | |
10249 | ||
10250 | cpr = &bnapi->cp_ring; | |
10251 | for (j = 0; j < 2; j++) { | |
10252 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; | |
10253 | u32 val[2]; | |
10254 | ||
10255 | if (!cpr2 || cpr2->has_more_work || | |
10256 | !bnxt_has_work(bp, cpr2)) | |
10257 | continue; | |
10258 | ||
10259 | if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) { | |
10260 | cpr2->last_cp_raw_cons = cpr2->cp_raw_cons; | |
10261 | continue; | |
10262 | } | |
10263 | fw_ring_id = cpr2->cp_ring_struct.fw_ring_id; | |
10264 | bnxt_dbg_hwrm_ring_info_get(bp, | |
10265 | DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL, | |
10266 | fw_ring_id, &val[0], &val[1]); | |
83eb5c5c | 10267 | cpr->missed_irqs++; |
ffd77621 MC |
10268 | } |
10269 | } | |
10270 | } | |
10271 | ||
c0c050c5 MC |
10272 | static void bnxt_cfg_ntp_filters(struct bnxt *); |
10273 | ||
8119e49b MC |
10274 | static void bnxt_init_ethtool_link_settings(struct bnxt *bp) |
10275 | { | |
10276 | struct bnxt_link_info *link_info = &bp->link_info; | |
10277 | ||
10278 | if (BNXT_AUTO_MODE(link_info->auto_mode)) { | |
10279 | link_info->autoneg = BNXT_AUTONEG_SPEED; | |
10280 | if (bp->hwrm_spec_code >= 0x10201) { | |
10281 | if (link_info->auto_pause_setting & | |
10282 | PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE) | |
10283 | link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; | |
10284 | } else { | |
10285 | link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; | |
10286 | } | |
10287 | link_info->advertising = link_info->auto_link_speeds; | |
10288 | } else { | |
10289 | link_info->req_link_speed = link_info->force_link_speed; | |
10290 | link_info->req_duplex = link_info->duplex_setting; | |
10291 | } | |
10292 | if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) | |
10293 | link_info->req_flow_ctrl = | |
10294 | link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH; | |
10295 | else | |
10296 | link_info->req_flow_ctrl = link_info->force_pause_setting; | |
10297 | } | |
10298 | ||
c0c050c5 MC |
10299 | static void bnxt_sp_task(struct work_struct *work) |
10300 | { | |
10301 | struct bnxt *bp = container_of(work, struct bnxt, sp_task); | |
c0c050c5 | 10302 | |
4cebdcec MC |
10303 | set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); |
10304 | smp_mb__after_atomic(); | |
10305 | if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { | |
10306 | clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); | |
c0c050c5 | 10307 | return; |
4cebdcec | 10308 | } |
c0c050c5 MC |
10309 | |
10310 | if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) | |
10311 | bnxt_cfg_rx_mode(bp); | |
10312 | ||
10313 | if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) | |
10314 | bnxt_cfg_ntp_filters(bp); | |
c0c050c5 MC |
10315 | if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) |
10316 | bnxt_hwrm_exec_fwd_req(bp); | |
10317 | if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) { | |
10318 | bnxt_hwrm_tunnel_dst_port_alloc( | |
10319 | bp, bp->vxlan_port, | |
10320 | TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); | |
10321 | } | |
10322 | if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) { | |
10323 | bnxt_hwrm_tunnel_dst_port_free( | |
10324 | bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); | |
10325 | } | |
7cdd5fc3 AD |
10326 | if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) { |
10327 | bnxt_hwrm_tunnel_dst_port_alloc( | |
10328 | bp, bp->nge_port, | |
10329 | TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); | |
10330 | } | |
10331 | if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) { | |
10332 | bnxt_hwrm_tunnel_dst_port_free( | |
10333 | bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); | |
10334 | } | |
00db3cba | 10335 | if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) { |
3bdf56c4 | 10336 | bnxt_hwrm_port_qstats(bp); |
00db3cba | 10337 | bnxt_hwrm_port_qstats_ext(bp); |
55e4398d | 10338 | bnxt_hwrm_pcie_qstats(bp); |
00db3cba | 10339 | } |
3bdf56c4 | 10340 | |
0eaa24b9 | 10341 | if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { |
e2dc9b6e | 10342 | int rc; |
0eaa24b9 | 10343 | |
e2dc9b6e | 10344 | mutex_lock(&bp->link_lock); |
0eaa24b9 MC |
10345 | if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, |
10346 | &bp->sp_event)) | |
10347 | bnxt_hwrm_phy_qcaps(bp); | |
10348 | ||
b1613e78 MC |
10349 | if (test_and_clear_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, |
10350 | &bp->sp_event)) | |
10351 | bnxt_init_ethtool_link_settings(bp); | |
10352 | ||
e2dc9b6e MC |
10353 | rc = bnxt_update_link(bp, true); |
10354 | mutex_unlock(&bp->link_lock); | |
0eaa24b9 MC |
10355 | if (rc) |
10356 | netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", | |
10357 | rc); | |
10358 | } | |
a1ef4a79 MC |
10359 | if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) { |
10360 | int rc; | |
10361 | ||
10362 | mutex_lock(&bp->link_lock); | |
10363 | rc = bnxt_update_phy_setting(bp); | |
10364 | mutex_unlock(&bp->link_lock); | |
10365 | if (rc) { | |
10366 | netdev_warn(bp->dev, "update phy settings retry failed\n"); | |
10367 | } else { | |
10368 | bp->link_info.phy_retry = false; | |
10369 | netdev_info(bp->dev, "update phy settings retry succeeded\n"); | |
10370 | } | |
10371 | } | |
90c694bb | 10372 | if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) { |
e2dc9b6e MC |
10373 | mutex_lock(&bp->link_lock); |
10374 | bnxt_get_port_module_status(bp); | |
10375 | mutex_unlock(&bp->link_lock); | |
90c694bb | 10376 | } |
5a84acbe SP |
10377 | |
10378 | if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event)) | |
10379 | bnxt_tc_flow_stats_work(bp); | |
10380 | ||
ffd77621 MC |
10381 | if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event)) |
10382 | bnxt_chk_missed_irq(bp); | |
10383 | ||
e2dc9b6e MC |
10384 | /* These functions below will clear BNXT_STATE_IN_SP_TASK. They |
10385 | * must be the last functions to be called before exiting. | |
10386 | */ | |
6988bd92 MC |
10387 | if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) |
10388 | bnxt_reset(bp, false); | |
4cebdcec | 10389 | |
fc0f1929 MC |
10390 | if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event)) |
10391 | bnxt_reset(bp, true); | |
10392 | ||
657a33c8 VV |
10393 | if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event)) |
10394 | bnxt_devlink_health_report(bp, BNXT_FW_RESET_NOTIFY_SP_EVENT); | |
10395 | ||
acfb50e4 VV |
10396 | if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) { |
10397 | if (!is_bnxt_fw_ok(bp)) | |
10398 | bnxt_devlink_health_report(bp, | |
10399 | BNXT_FW_EXCEPTION_SP_EVENT); | |
10400 | } | |
10401 | ||
4cebdcec MC |
10402 | smp_mb__before_atomic(); |
10403 | clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); | |
c0c050c5 MC |
10404 | } |
10405 | ||
d1e7925e | 10406 | /* Under rtnl_lock */ |
98fdbe73 MC |
10407 | int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, |
10408 | int tx_xdp) | |
d1e7925e MC |
10409 | { |
10410 | int max_rx, max_tx, tx_sets = 1; | |
780baad4 | 10411 | int tx_rings_needed, stats; |
8f23d638 | 10412 | int rx_rings = rx; |
6fc2ffdf | 10413 | int cp, vnics, rc; |
d1e7925e | 10414 | |
d1e7925e MC |
10415 | if (tcs) |
10416 | tx_sets = tcs; | |
10417 | ||
10418 | rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh); | |
10419 | if (rc) | |
10420 | return rc; | |
10421 | ||
10422 | if (max_rx < rx) | |
10423 | return -ENOMEM; | |
10424 | ||
5f449249 | 10425 | tx_rings_needed = tx * tx_sets + tx_xdp; |
d1e7925e MC |
10426 | if (max_tx < tx_rings_needed) |
10427 | return -ENOMEM; | |
10428 | ||
6fc2ffdf | 10429 | vnics = 1; |
9b3d15e6 | 10430 | if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) |
6fc2ffdf EW |
10431 | vnics += rx_rings; |
10432 | ||
8f23d638 MC |
10433 | if (bp->flags & BNXT_FLAG_AGG_RINGS) |
10434 | rx_rings <<= 1; | |
10435 | cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx; | |
780baad4 VV |
10436 | stats = cp; |
10437 | if (BNXT_NEW_RM(bp)) { | |
11c3ec7b | 10438 | cp += bnxt_get_ulp_msix_num(bp); |
780baad4 VV |
10439 | stats += bnxt_get_ulp_stat_ctxs(bp); |
10440 | } | |
6fc2ffdf | 10441 | return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp, |
780baad4 | 10442 | stats, vnics); |
d1e7925e MC |
10443 | } |
10444 | ||
17086399 SP |
10445 | static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev) |
10446 | { | |
10447 | if (bp->bar2) { | |
10448 | pci_iounmap(pdev, bp->bar2); | |
10449 | bp->bar2 = NULL; | |
10450 | } | |
10451 | ||
10452 | if (bp->bar1) { | |
10453 | pci_iounmap(pdev, bp->bar1); | |
10454 | bp->bar1 = NULL; | |
10455 | } | |
10456 | ||
10457 | if (bp->bar0) { | |
10458 | pci_iounmap(pdev, bp->bar0); | |
10459 | bp->bar0 = NULL; | |
10460 | } | |
10461 | } | |
10462 | ||
10463 | static void bnxt_cleanup_pci(struct bnxt *bp) | |
10464 | { | |
10465 | bnxt_unmap_bars(bp, bp->pdev); | |
10466 | pci_release_regions(bp->pdev); | |
f6824308 VV |
10467 | if (pci_is_enabled(bp->pdev)) |
10468 | pci_disable_device(bp->pdev); | |
17086399 SP |
10469 | } |
10470 | ||
18775aa8 MC |
10471 | static void bnxt_init_dflt_coal(struct bnxt *bp) |
10472 | { | |
10473 | struct bnxt_coal *coal; | |
10474 | ||
10475 | /* Tick values in micro seconds. | |
10476 | * 1 coal_buf x bufs_per_record = 1 completion record. | |
10477 | */ | |
10478 | coal = &bp->rx_coal; | |
0c2ff8d7 | 10479 | coal->coal_ticks = 10; |
18775aa8 MC |
10480 | coal->coal_bufs = 30; |
10481 | coal->coal_ticks_irq = 1; | |
10482 | coal->coal_bufs_irq = 2; | |
05abe4dd | 10483 | coal->idle_thresh = 50; |
18775aa8 MC |
10484 | coal->bufs_per_record = 2; |
10485 | coal->budget = 64; /* NAPI budget */ | |
10486 | ||
10487 | coal = &bp->tx_coal; | |
10488 | coal->coal_ticks = 28; | |
10489 | coal->coal_bufs = 30; | |
10490 | coal->coal_ticks_irq = 2; | |
10491 | coal->coal_bufs_irq = 2; | |
10492 | coal->bufs_per_record = 1; | |
10493 | ||
10494 | bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS; | |
10495 | } | |
10496 | ||
8280b38e VV |
10497 | static void bnxt_alloc_fw_health(struct bnxt *bp) |
10498 | { | |
10499 | if (bp->fw_health) | |
10500 | return; | |
10501 | ||
10502 | if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) && | |
10503 | !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) | |
10504 | return; | |
10505 | ||
10506 | bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL); | |
10507 | if (!bp->fw_health) { | |
10508 | netdev_warn(bp->dev, "Failed to allocate fw_health\n"); | |
10509 | bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET; | |
10510 | bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; | |
10511 | } | |
10512 | } | |
10513 | ||
7c380918 MC |
10514 | static int bnxt_fw_init_one_p1(struct bnxt *bp) |
10515 | { | |
10516 | int rc; | |
10517 | ||
10518 | bp->fw_cap = 0; | |
10519 | rc = bnxt_hwrm_ver_get(bp); | |
10520 | if (rc) | |
10521 | return rc; | |
10522 | ||
10523 | if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) { | |
10524 | rc = bnxt_alloc_kong_hwrm_resources(bp); | |
10525 | if (rc) | |
10526 | bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL; | |
10527 | } | |
10528 | ||
10529 | if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || | |
10530 | bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) { | |
10531 | rc = bnxt_alloc_hwrm_short_cmd_req(bp); | |
10532 | if (rc) | |
10533 | return rc; | |
10534 | } | |
10535 | rc = bnxt_hwrm_func_reset(bp); | |
10536 | if (rc) | |
10537 | return -ENODEV; | |
10538 | ||
10539 | bnxt_hwrm_fw_set_time(bp); | |
10540 | return 0; | |
10541 | } | |
10542 | ||
10543 | static int bnxt_fw_init_one_p2(struct bnxt *bp) | |
10544 | { | |
10545 | int rc; | |
10546 | ||
10547 | /* Get the MAX capabilities for this function */ | |
10548 | rc = bnxt_hwrm_func_qcaps(bp); | |
10549 | if (rc) { | |
10550 | netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", | |
10551 | rc); | |
10552 | return -ENODEV; | |
10553 | } | |
10554 | ||
10555 | rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp); | |
10556 | if (rc) | |
10557 | netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n", | |
10558 | rc); | |
10559 | ||
8280b38e | 10560 | bnxt_alloc_fw_health(bp); |
07f83d72 MC |
10561 | rc = bnxt_hwrm_error_recovery_qcfg(bp); |
10562 | if (rc) | |
10563 | netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n", | |
10564 | rc); | |
10565 | ||
2e882468 | 10566 | rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false); |
7c380918 MC |
10567 | if (rc) |
10568 | return -ENODEV; | |
10569 | ||
10570 | bnxt_hwrm_func_qcfg(bp); | |
10571 | bnxt_hwrm_vnic_qcaps(bp); | |
10572 | bnxt_hwrm_port_led_qcaps(bp); | |
10573 | bnxt_ethtool_init(bp); | |
10574 | bnxt_dcb_init(bp); | |
10575 | return 0; | |
10576 | } | |
10577 | ||
ba642ab7 MC |
10578 | static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp) |
10579 | { | |
10580 | bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP; | |
10581 | bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 | | |
10582 | VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 | | |
10583 | VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | | |
10584 | VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; | |
c66c06c5 | 10585 | if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) { |
ba642ab7 MC |
10586 | bp->flags |= BNXT_FLAG_UDP_RSS_CAP; |
10587 | bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 | | |
10588 | VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; | |
10589 | } | |
10590 | } | |
10591 | ||
10592 | static void bnxt_set_dflt_rfs(struct bnxt *bp) | |
10593 | { | |
10594 | struct net_device *dev = bp->dev; | |
10595 | ||
10596 | dev->hw_features &= ~NETIF_F_NTUPLE; | |
10597 | dev->features &= ~NETIF_F_NTUPLE; | |
10598 | bp->flags &= ~BNXT_FLAG_RFS; | |
10599 | if (bnxt_rfs_supported(bp)) { | |
10600 | dev->hw_features |= NETIF_F_NTUPLE; | |
10601 | if (bnxt_rfs_capable(bp)) { | |
10602 | bp->flags |= BNXT_FLAG_RFS; | |
10603 | dev->features |= NETIF_F_NTUPLE; | |
10604 | } | |
10605 | } | |
10606 | } | |
10607 | ||
10608 | static void bnxt_fw_init_one_p3(struct bnxt *bp) | |
10609 | { | |
10610 | struct pci_dev *pdev = bp->pdev; | |
10611 | ||
10612 | bnxt_set_dflt_rss_hash_type(bp); | |
10613 | bnxt_set_dflt_rfs(bp); | |
10614 | ||
10615 | bnxt_get_wol_settings(bp); | |
10616 | if (bp->flags & BNXT_FLAG_WOL_CAP) | |
10617 | device_set_wakeup_enable(&pdev->dev, bp->wol); | |
10618 | else | |
10619 | device_set_wakeup_capable(&pdev->dev, false); | |
10620 | ||
10621 | bnxt_hwrm_set_cache_line_size(bp, cache_line_size()); | |
10622 | bnxt_hwrm_coal_params_qcaps(bp); | |
10623 | } | |
10624 | ||
ec5d31e3 MC |
10625 | static int bnxt_fw_init_one(struct bnxt *bp) |
10626 | { | |
10627 | int rc; | |
10628 | ||
10629 | rc = bnxt_fw_init_one_p1(bp); | |
10630 | if (rc) { | |
10631 | netdev_err(bp->dev, "Firmware init phase 1 failed\n"); | |
10632 | return rc; | |
10633 | } | |
10634 | rc = bnxt_fw_init_one_p2(bp); | |
10635 | if (rc) { | |
10636 | netdev_err(bp->dev, "Firmware init phase 2 failed\n"); | |
10637 | return rc; | |
10638 | } | |
10639 | rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false); | |
10640 | if (rc) | |
10641 | return rc; | |
937f188c VV |
10642 | |
10643 | /* In case fw capabilities have changed, destroy the unneeded | |
10644 | * reporters and create newly capable ones. | |
10645 | */ | |
10646 | bnxt_dl_fw_reporters_destroy(bp, false); | |
10647 | bnxt_dl_fw_reporters_create(bp); | |
ec5d31e3 MC |
10648 | bnxt_fw_init_one_p3(bp); |
10649 | return 0; | |
10650 | } | |
10651 | ||
cbb51067 MC |
10652 | static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx) |
10653 | { | |
10654 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
10655 | u32 reg = fw_health->fw_reset_seq_regs[reg_idx]; | |
10656 | u32 val = fw_health->fw_reset_seq_vals[reg_idx]; | |
10657 | u32 reg_type, reg_off, delay_msecs; | |
10658 | ||
10659 | delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx]; | |
10660 | reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); | |
10661 | reg_off = BNXT_FW_HEALTH_REG_OFF(reg); | |
10662 | switch (reg_type) { | |
10663 | case BNXT_FW_HEALTH_REG_TYPE_CFG: | |
10664 | pci_write_config_dword(bp->pdev, reg_off, val); | |
10665 | break; | |
10666 | case BNXT_FW_HEALTH_REG_TYPE_GRC: | |
10667 | writel(reg_off & BNXT_GRC_BASE_MASK, | |
10668 | bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); | |
10669 | reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000; | |
10670 | /* fall through */ | |
10671 | case BNXT_FW_HEALTH_REG_TYPE_BAR0: | |
10672 | writel(val, bp->bar0 + reg_off); | |
10673 | break; | |
10674 | case BNXT_FW_HEALTH_REG_TYPE_BAR1: | |
10675 | writel(val, bp->bar1 + reg_off); | |
10676 | break; | |
10677 | } | |
10678 | if (delay_msecs) { | |
10679 | pci_read_config_dword(bp->pdev, 0, &val); | |
10680 | msleep(delay_msecs); | |
10681 | } | |
10682 | } | |
10683 | ||
10684 | static void bnxt_reset_all(struct bnxt *bp) | |
10685 | { | |
10686 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
e07ab202 VV |
10687 | int i, rc; |
10688 | ||
10689 | if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { | |
10690 | #ifdef CONFIG_TEE_BNXT_FW | |
10691 | rc = tee_bnxt_fw_load(); | |
10692 | if (rc) | |
10693 | netdev_err(bp->dev, "Unable to reset FW rc=%d\n", rc); | |
10694 | bp->fw_reset_timestamp = jiffies; | |
10695 | #endif | |
10696 | return; | |
10697 | } | |
cbb51067 MC |
10698 | |
10699 | if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) { | |
10700 | for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) | |
10701 | bnxt_fw_reset_writel(bp, i); | |
10702 | } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) { | |
10703 | struct hwrm_fw_reset_input req = {0}; | |
cbb51067 MC |
10704 | |
10705 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1); | |
10706 | req.resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); | |
10707 | req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP; | |
10708 | req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP; | |
10709 | req.flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; | |
10710 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
10711 | if (rc) | |
10712 | netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc); | |
10713 | } | |
10714 | bp->fw_reset_timestamp = jiffies; | |
10715 | } | |
10716 | ||
230d1f0d MC |
10717 | static void bnxt_fw_reset_task(struct work_struct *work) |
10718 | { | |
10719 | struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work); | |
10720 | int rc; | |
10721 | ||
10722 | if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { | |
10723 | netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n"); | |
10724 | return; | |
10725 | } | |
10726 | ||
10727 | switch (bp->fw_reset_state) { | |
e72cb7d6 MC |
10728 | case BNXT_FW_RESET_STATE_POLL_VF: { |
10729 | int n = bnxt_get_registered_vfs(bp); | |
4037eb71 | 10730 | int tmo; |
e72cb7d6 MC |
10731 | |
10732 | if (n < 0) { | |
230d1f0d | 10733 | netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n", |
e72cb7d6 | 10734 | n, jiffies_to_msecs(jiffies - |
230d1f0d MC |
10735 | bp->fw_reset_timestamp)); |
10736 | goto fw_reset_abort; | |
e72cb7d6 | 10737 | } else if (n > 0) { |
230d1f0d MC |
10738 | if (time_after(jiffies, bp->fw_reset_timestamp + |
10739 | (bp->fw_reset_max_dsecs * HZ / 10))) { | |
10740 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
10741 | bp->fw_reset_state = 0; | |
e72cb7d6 MC |
10742 | netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n", |
10743 | n); | |
230d1f0d MC |
10744 | return; |
10745 | } | |
10746 | bnxt_queue_fw_reset_work(bp, HZ / 10); | |
10747 | return; | |
10748 | } | |
10749 | bp->fw_reset_timestamp = jiffies; | |
10750 | rtnl_lock(); | |
10751 | bnxt_fw_reset_close(bp); | |
4037eb71 VV |
10752 | if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { |
10753 | bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; | |
10754 | tmo = HZ / 10; | |
10755 | } else { | |
10756 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
10757 | tmo = bp->fw_reset_min_dsecs * HZ / 10; | |
10758 | } | |
230d1f0d | 10759 | rtnl_unlock(); |
4037eb71 | 10760 | bnxt_queue_fw_reset_work(bp, tmo); |
230d1f0d | 10761 | return; |
e72cb7d6 | 10762 | } |
4037eb71 VV |
10763 | case BNXT_FW_RESET_STATE_POLL_FW_DOWN: { |
10764 | u32 val; | |
10765 | ||
10766 | val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); | |
10767 | if (!(val & BNXT_FW_STATUS_SHUTDOWN) && | |
10768 | !time_after(jiffies, bp->fw_reset_timestamp + | |
10769 | (bp->fw_reset_max_dsecs * HZ / 10))) { | |
10770 | bnxt_queue_fw_reset_work(bp, HZ / 5); | |
10771 | return; | |
10772 | } | |
10773 | ||
10774 | if (!bp->fw_health->master) { | |
10775 | u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs; | |
10776 | ||
10777 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
10778 | bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); | |
10779 | return; | |
10780 | } | |
10781 | bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; | |
10782 | } | |
10783 | /* fall through */ | |
c6a9e7aa | 10784 | case BNXT_FW_RESET_STATE_RESET_FW: |
cbb51067 MC |
10785 | bnxt_reset_all(bp); |
10786 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
c6a9e7aa | 10787 | bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10); |
cbb51067 | 10788 | return; |
230d1f0d | 10789 | case BNXT_FW_RESET_STATE_ENABLE_DEV: |
0797c10d | 10790 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) { |
d1db9e16 MC |
10791 | u32 val; |
10792 | ||
10793 | val = bnxt_fw_health_readl(bp, | |
10794 | BNXT_FW_RESET_INPROG_REG); | |
10795 | if (val) | |
10796 | netdev_warn(bp->dev, "FW reset inprog %x after min wait time.\n", | |
10797 | val); | |
10798 | } | |
b4fff207 | 10799 | clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); |
230d1f0d MC |
10800 | if (pci_enable_device(bp->pdev)) { |
10801 | netdev_err(bp->dev, "Cannot re-enable PCI device\n"); | |
10802 | goto fw_reset_abort; | |
10803 | } | |
10804 | pci_set_master(bp->pdev); | |
10805 | bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW; | |
10806 | /* fall through */ | |
10807 | case BNXT_FW_RESET_STATE_POLL_FW: | |
10808 | bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT; | |
10809 | rc = __bnxt_hwrm_ver_get(bp, true); | |
10810 | if (rc) { | |
10811 | if (time_after(jiffies, bp->fw_reset_timestamp + | |
10812 | (bp->fw_reset_max_dsecs * HZ / 10))) { | |
10813 | netdev_err(bp->dev, "Firmware reset aborted\n"); | |
10814 | goto fw_reset_abort; | |
10815 | } | |
10816 | bnxt_queue_fw_reset_work(bp, HZ / 5); | |
10817 | return; | |
10818 | } | |
10819 | bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; | |
10820 | bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING; | |
10821 | /* fall through */ | |
10822 | case BNXT_FW_RESET_STATE_OPENING: | |
10823 | while (!rtnl_trylock()) { | |
10824 | bnxt_queue_fw_reset_work(bp, HZ / 10); | |
10825 | return; | |
10826 | } | |
10827 | rc = bnxt_open(bp->dev); | |
10828 | if (rc) { | |
10829 | netdev_err(bp->dev, "bnxt_open_nic() failed\n"); | |
10830 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
10831 | dev_close(bp->dev); | |
10832 | } | |
230d1f0d MC |
10833 | |
10834 | bp->fw_reset_state = 0; | |
10835 | /* Make sure fw_reset_state is 0 before clearing the flag */ | |
10836 | smp_mb__before_atomic(); | |
10837 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
f3a6d206 | 10838 | bnxt_ulp_start(bp, rc); |
12de2ead MC |
10839 | if (!rc) |
10840 | bnxt_reenable_sriov(bp); | |
737d7a6c | 10841 | bnxt_dl_health_recovery_done(bp); |
e4e38237 | 10842 | bnxt_dl_health_status_update(bp, true); |
f3a6d206 | 10843 | rtnl_unlock(); |
230d1f0d MC |
10844 | break; |
10845 | } | |
10846 | return; | |
10847 | ||
10848 | fw_reset_abort: | |
10849 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
e4e38237 VV |
10850 | if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF) |
10851 | bnxt_dl_health_status_update(bp, false); | |
230d1f0d MC |
10852 | bp->fw_reset_state = 0; |
10853 | rtnl_lock(); | |
10854 | dev_close(bp->dev); | |
10855 | rtnl_unlock(); | |
10856 | } | |
10857 | ||
c0c050c5 MC |
10858 | static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) |
10859 | { | |
10860 | int rc; | |
10861 | struct bnxt *bp = netdev_priv(dev); | |
10862 | ||
10863 | SET_NETDEV_DEV(dev, &pdev->dev); | |
10864 | ||
10865 | /* enable device (incl. PCI PM wakeup), and bus-mastering */ | |
10866 | rc = pci_enable_device(pdev); | |
10867 | if (rc) { | |
10868 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); | |
10869 | goto init_err; | |
10870 | } | |
10871 | ||
10872 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
10873 | dev_err(&pdev->dev, | |
10874 | "Cannot find PCI device base address, aborting\n"); | |
10875 | rc = -ENODEV; | |
10876 | goto init_err_disable; | |
10877 | } | |
10878 | ||
10879 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
10880 | if (rc) { | |
10881 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); | |
10882 | goto init_err_disable; | |
10883 | } | |
10884 | ||
10885 | if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && | |
10886 | dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { | |
10887 | dev_err(&pdev->dev, "System does not support DMA, aborting\n"); | |
10888 | goto init_err_disable; | |
10889 | } | |
10890 | ||
10891 | pci_set_master(pdev); | |
10892 | ||
10893 | bp->dev = dev; | |
10894 | bp->pdev = pdev; | |
10895 | ||
10896 | bp->bar0 = pci_ioremap_bar(pdev, 0); | |
10897 | if (!bp->bar0) { | |
10898 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); | |
10899 | rc = -ENOMEM; | |
10900 | goto init_err_release; | |
10901 | } | |
10902 | ||
10903 | bp->bar1 = pci_ioremap_bar(pdev, 2); | |
10904 | if (!bp->bar1) { | |
10905 | dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n"); | |
10906 | rc = -ENOMEM; | |
10907 | goto init_err_release; | |
10908 | } | |
10909 | ||
10910 | bp->bar2 = pci_ioremap_bar(pdev, 4); | |
10911 | if (!bp->bar2) { | |
10912 | dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); | |
10913 | rc = -ENOMEM; | |
10914 | goto init_err_release; | |
10915 | } | |
10916 | ||
6316ea6d SB |
10917 | pci_enable_pcie_error_reporting(pdev); |
10918 | ||
c0c050c5 | 10919 | INIT_WORK(&bp->sp_task, bnxt_sp_task); |
230d1f0d | 10920 | INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task); |
c0c050c5 MC |
10921 | |
10922 | spin_lock_init(&bp->ntp_fltr_lock); | |
697197e5 MC |
10923 | #if BITS_PER_LONG == 32 |
10924 | spin_lock_init(&bp->db_lock); | |
10925 | #endif | |
c0c050c5 MC |
10926 | |
10927 | bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; | |
10928 | bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; | |
10929 | ||
18775aa8 | 10930 | bnxt_init_dflt_coal(bp); |
51f30785 | 10931 | |
e99e88a9 | 10932 | timer_setup(&bp->timer, bnxt_timer, 0); |
c0c050c5 MC |
10933 | bp->current_interval = BNXT_TIMER_INTERVAL; |
10934 | ||
caefe526 | 10935 | clear_bit(BNXT_STATE_OPEN, &bp->state); |
c0c050c5 MC |
10936 | return 0; |
10937 | ||
10938 | init_err_release: | |
17086399 | 10939 | bnxt_unmap_bars(bp, pdev); |
c0c050c5 MC |
10940 | pci_release_regions(pdev); |
10941 | ||
10942 | init_err_disable: | |
10943 | pci_disable_device(pdev); | |
10944 | ||
10945 | init_err: | |
10946 | return rc; | |
10947 | } | |
10948 | ||
10949 | /* rtnl_lock held */ | |
10950 | static int bnxt_change_mac_addr(struct net_device *dev, void *p) | |
10951 | { | |
10952 | struct sockaddr *addr = p; | |
1fc2cfd0 JH |
10953 | struct bnxt *bp = netdev_priv(dev); |
10954 | int rc = 0; | |
c0c050c5 MC |
10955 | |
10956 | if (!is_valid_ether_addr(addr->sa_data)) | |
10957 | return -EADDRNOTAVAIL; | |
10958 | ||
c1a7bdff MC |
10959 | if (ether_addr_equal(addr->sa_data, dev->dev_addr)) |
10960 | return 0; | |
10961 | ||
28ea334b | 10962 | rc = bnxt_approve_mac(bp, addr->sa_data, true); |
84c33dd3 MC |
10963 | if (rc) |
10964 | return rc; | |
bdd4347b | 10965 | |
c0c050c5 | 10966 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
1fc2cfd0 JH |
10967 | if (netif_running(dev)) { |
10968 | bnxt_close_nic(bp, false, false); | |
10969 | rc = bnxt_open_nic(bp, false, false); | |
10970 | } | |
c0c050c5 | 10971 | |
1fc2cfd0 | 10972 | return rc; |
c0c050c5 MC |
10973 | } |
10974 | ||
10975 | /* rtnl_lock held */ | |
10976 | static int bnxt_change_mtu(struct net_device *dev, int new_mtu) | |
10977 | { | |
10978 | struct bnxt *bp = netdev_priv(dev); | |
10979 | ||
c0c050c5 MC |
10980 | if (netif_running(dev)) |
10981 | bnxt_close_nic(bp, false, false); | |
10982 | ||
10983 | dev->mtu = new_mtu; | |
10984 | bnxt_set_ring_params(bp); | |
10985 | ||
10986 | if (netif_running(dev)) | |
10987 | return bnxt_open_nic(bp, false, false); | |
10988 | ||
10989 | return 0; | |
10990 | } | |
10991 | ||
c5e3deb8 | 10992 | int bnxt_setup_mq_tc(struct net_device *dev, u8 tc) |
c0c050c5 MC |
10993 | { |
10994 | struct bnxt *bp = netdev_priv(dev); | |
3ffb6a39 | 10995 | bool sh = false; |
d1e7925e | 10996 | int rc; |
16e5cc64 | 10997 | |
c0c050c5 | 10998 | if (tc > bp->max_tc) { |
b451c8b6 | 10999 | netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n", |
c0c050c5 MC |
11000 | tc, bp->max_tc); |
11001 | return -EINVAL; | |
11002 | } | |
11003 | ||
11004 | if (netdev_get_num_tc(dev) == tc) | |
11005 | return 0; | |
11006 | ||
3ffb6a39 MC |
11007 | if (bp->flags & BNXT_FLAG_SHARED_RINGS) |
11008 | sh = true; | |
11009 | ||
98fdbe73 MC |
11010 | rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings, |
11011 | sh, tc, bp->tx_nr_rings_xdp); | |
d1e7925e MC |
11012 | if (rc) |
11013 | return rc; | |
c0c050c5 MC |
11014 | |
11015 | /* Needs to close the device and do hw resource re-allocations */ | |
11016 | if (netif_running(bp->dev)) | |
11017 | bnxt_close_nic(bp, true, false); | |
11018 | ||
11019 | if (tc) { | |
11020 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; | |
11021 | netdev_set_num_tc(dev, tc); | |
11022 | } else { | |
11023 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc; | |
11024 | netdev_reset_tc(dev); | |
11025 | } | |
87e9b377 | 11026 | bp->tx_nr_rings += bp->tx_nr_rings_xdp; |
3ffb6a39 MC |
11027 | bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : |
11028 | bp->tx_nr_rings + bp->rx_nr_rings; | |
c0c050c5 MC |
11029 | |
11030 | if (netif_running(bp->dev)) | |
11031 | return bnxt_open_nic(bp, true, false); | |
11032 | ||
11033 | return 0; | |
11034 | } | |
11035 | ||
9e0fd15d JP |
11036 | static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data, |
11037 | void *cb_priv) | |
c5e3deb8 | 11038 | { |
9e0fd15d | 11039 | struct bnxt *bp = cb_priv; |
de4784ca | 11040 | |
312324f1 JK |
11041 | if (!bnxt_tc_flower_enabled(bp) || |
11042 | !tc_cls_can_offload_and_chain0(bp->dev, type_data)) | |
38cf0426 | 11043 | return -EOPNOTSUPP; |
c5e3deb8 | 11044 | |
9e0fd15d JP |
11045 | switch (type) { |
11046 | case TC_SETUP_CLSFLOWER: | |
11047 | return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data); | |
11048 | default: | |
11049 | return -EOPNOTSUPP; | |
11050 | } | |
11051 | } | |
11052 | ||
627c89d0 | 11053 | LIST_HEAD(bnxt_block_cb_list); |
955bcb6e | 11054 | |
2ae7408f SP |
11055 | static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type, |
11056 | void *type_data) | |
11057 | { | |
4e95bc26 PNA |
11058 | struct bnxt *bp = netdev_priv(dev); |
11059 | ||
2ae7408f | 11060 | switch (type) { |
9e0fd15d | 11061 | case TC_SETUP_BLOCK: |
955bcb6e PNA |
11062 | return flow_block_cb_setup_simple(type_data, |
11063 | &bnxt_block_cb_list, | |
4e95bc26 PNA |
11064 | bnxt_setup_tc_block_cb, |
11065 | bp, bp, true); | |
575ed7d3 | 11066 | case TC_SETUP_QDISC_MQPRIO: { |
2ae7408f SP |
11067 | struct tc_mqprio_qopt *mqprio = type_data; |
11068 | ||
11069 | mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; | |
56f36acd | 11070 | |
2ae7408f SP |
11071 | return bnxt_setup_mq_tc(dev, mqprio->num_tc); |
11072 | } | |
11073 | default: | |
11074 | return -EOPNOTSUPP; | |
11075 | } | |
c5e3deb8 MC |
11076 | } |
11077 | ||
c0c050c5 MC |
11078 | #ifdef CONFIG_RFS_ACCEL |
11079 | static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, | |
11080 | struct bnxt_ntuple_filter *f2) | |
11081 | { | |
11082 | struct flow_keys *keys1 = &f1->fkeys; | |
11083 | struct flow_keys *keys2 = &f2->fkeys; | |
11084 | ||
6fc7caa8 MC |
11085 | if (keys1->basic.n_proto != keys2->basic.n_proto || |
11086 | keys1->basic.ip_proto != keys2->basic.ip_proto) | |
11087 | return false; | |
11088 | ||
11089 | if (keys1->basic.n_proto == htons(ETH_P_IP)) { | |
11090 | if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src || | |
11091 | keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst) | |
11092 | return false; | |
11093 | } else { | |
11094 | if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src, | |
11095 | sizeof(keys1->addrs.v6addrs.src)) || | |
11096 | memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst, | |
11097 | sizeof(keys1->addrs.v6addrs.dst))) | |
11098 | return false; | |
11099 | } | |
11100 | ||
11101 | if (keys1->ports.ports == keys2->ports.ports && | |
61aad724 | 11102 | keys1->control.flags == keys2->control.flags && |
a54c4d74 MC |
11103 | ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) && |
11104 | ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr)) | |
c0c050c5 MC |
11105 | return true; |
11106 | ||
11107 | return false; | |
11108 | } | |
11109 | ||
11110 | static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, | |
11111 | u16 rxq_index, u32 flow_id) | |
11112 | { | |
11113 | struct bnxt *bp = netdev_priv(dev); | |
11114 | struct bnxt_ntuple_filter *fltr, *new_fltr; | |
11115 | struct flow_keys *fkeys; | |
11116 | struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); | |
a54c4d74 | 11117 | int rc = 0, idx, bit_id, l2_idx = 0; |
c0c050c5 | 11118 | struct hlist_head *head; |
f47d0e19 | 11119 | u32 flags; |
c0c050c5 | 11120 | |
a54c4d74 MC |
11121 | if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) { |
11122 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; | |
11123 | int off = 0, j; | |
11124 | ||
11125 | netif_addr_lock_bh(dev); | |
11126 | for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) { | |
11127 | if (ether_addr_equal(eth->h_dest, | |
11128 | vnic->uc_list + off)) { | |
11129 | l2_idx = j + 1; | |
11130 | break; | |
11131 | } | |
11132 | } | |
11133 | netif_addr_unlock_bh(dev); | |
11134 | if (!l2_idx) | |
11135 | return -EINVAL; | |
11136 | } | |
c0c050c5 MC |
11137 | new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); |
11138 | if (!new_fltr) | |
11139 | return -ENOMEM; | |
11140 | ||
11141 | fkeys = &new_fltr->fkeys; | |
11142 | if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { | |
11143 | rc = -EPROTONOSUPPORT; | |
11144 | goto err_free; | |
11145 | } | |
11146 | ||
dda0e746 MC |
11147 | if ((fkeys->basic.n_proto != htons(ETH_P_IP) && |
11148 | fkeys->basic.n_proto != htons(ETH_P_IPV6)) || | |
c0c050c5 MC |
11149 | ((fkeys->basic.ip_proto != IPPROTO_TCP) && |
11150 | (fkeys->basic.ip_proto != IPPROTO_UDP))) { | |
11151 | rc = -EPROTONOSUPPORT; | |
11152 | goto err_free; | |
11153 | } | |
dda0e746 MC |
11154 | if (fkeys->basic.n_proto == htons(ETH_P_IPV6) && |
11155 | bp->hwrm_spec_code < 0x10601) { | |
11156 | rc = -EPROTONOSUPPORT; | |
11157 | goto err_free; | |
11158 | } | |
f47d0e19 MC |
11159 | flags = fkeys->control.flags; |
11160 | if (((flags & FLOW_DIS_ENCAPSULATION) && | |
11161 | bp->hwrm_spec_code < 0x10601) || (flags & FLOW_DIS_IS_FRAGMENT)) { | |
61aad724 MC |
11162 | rc = -EPROTONOSUPPORT; |
11163 | goto err_free; | |
11164 | } | |
c0c050c5 | 11165 | |
a54c4d74 | 11166 | memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN); |
c0c050c5 MC |
11167 | memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); |
11168 | ||
11169 | idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; | |
11170 | head = &bp->ntp_fltr_hash_tbl[idx]; | |
11171 | rcu_read_lock(); | |
11172 | hlist_for_each_entry_rcu(fltr, head, hash) { | |
11173 | if (bnxt_fltr_match(fltr, new_fltr)) { | |
11174 | rcu_read_unlock(); | |
11175 | rc = 0; | |
11176 | goto err_free; | |
11177 | } | |
11178 | } | |
11179 | rcu_read_unlock(); | |
11180 | ||
11181 | spin_lock_bh(&bp->ntp_fltr_lock); | |
84e86b98 MC |
11182 | bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, |
11183 | BNXT_NTP_FLTR_MAX_FLTR, 0); | |
11184 | if (bit_id < 0) { | |
c0c050c5 MC |
11185 | spin_unlock_bh(&bp->ntp_fltr_lock); |
11186 | rc = -ENOMEM; | |
11187 | goto err_free; | |
11188 | } | |
11189 | ||
84e86b98 | 11190 | new_fltr->sw_id = (u16)bit_id; |
c0c050c5 | 11191 | new_fltr->flow_id = flow_id; |
a54c4d74 | 11192 | new_fltr->l2_fltr_idx = l2_idx; |
c0c050c5 MC |
11193 | new_fltr->rxq = rxq_index; |
11194 | hlist_add_head_rcu(&new_fltr->hash, head); | |
11195 | bp->ntp_fltr_count++; | |
11196 | spin_unlock_bh(&bp->ntp_fltr_lock); | |
11197 | ||
11198 | set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); | |
c213eae8 | 11199 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
11200 | |
11201 | return new_fltr->sw_id; | |
11202 | ||
11203 | err_free: | |
11204 | kfree(new_fltr); | |
11205 | return rc; | |
11206 | } | |
11207 | ||
11208 | static void bnxt_cfg_ntp_filters(struct bnxt *bp) | |
11209 | { | |
11210 | int i; | |
11211 | ||
11212 | for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { | |
11213 | struct hlist_head *head; | |
11214 | struct hlist_node *tmp; | |
11215 | struct bnxt_ntuple_filter *fltr; | |
11216 | int rc; | |
11217 | ||
11218 | head = &bp->ntp_fltr_hash_tbl[i]; | |
11219 | hlist_for_each_entry_safe(fltr, tmp, head, hash) { | |
11220 | bool del = false; | |
11221 | ||
11222 | if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { | |
11223 | if (rps_may_expire_flow(bp->dev, fltr->rxq, | |
11224 | fltr->flow_id, | |
11225 | fltr->sw_id)) { | |
11226 | bnxt_hwrm_cfa_ntuple_filter_free(bp, | |
11227 | fltr); | |
11228 | del = true; | |
11229 | } | |
11230 | } else { | |
11231 | rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, | |
11232 | fltr); | |
11233 | if (rc) | |
11234 | del = true; | |
11235 | else | |
11236 | set_bit(BNXT_FLTR_VALID, &fltr->state); | |
11237 | } | |
11238 | ||
11239 | if (del) { | |
11240 | spin_lock_bh(&bp->ntp_fltr_lock); | |
11241 | hlist_del_rcu(&fltr->hash); | |
11242 | bp->ntp_fltr_count--; | |
11243 | spin_unlock_bh(&bp->ntp_fltr_lock); | |
11244 | synchronize_rcu(); | |
11245 | clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); | |
11246 | kfree(fltr); | |
11247 | } | |
11248 | } | |
11249 | } | |
19241368 | 11250 | if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event)) |
9a005c38 | 11251 | netdev_info(bp->dev, "Receive PF driver unload event!\n"); |
c0c050c5 MC |
11252 | } |
11253 | ||
11254 | #else | |
11255 | ||
11256 | static void bnxt_cfg_ntp_filters(struct bnxt *bp) | |
11257 | { | |
11258 | } | |
11259 | ||
11260 | #endif /* CONFIG_RFS_ACCEL */ | |
11261 | ||
ad51b8e9 AD |
11262 | static void bnxt_udp_tunnel_add(struct net_device *dev, |
11263 | struct udp_tunnel_info *ti) | |
c0c050c5 MC |
11264 | { |
11265 | struct bnxt *bp = netdev_priv(dev); | |
11266 | ||
ad51b8e9 | 11267 | if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) |
c0c050c5 MC |
11268 | return; |
11269 | ||
ad51b8e9 | 11270 | if (!netif_running(dev)) |
c0c050c5 MC |
11271 | return; |
11272 | ||
ad51b8e9 AD |
11273 | switch (ti->type) { |
11274 | case UDP_TUNNEL_TYPE_VXLAN: | |
11275 | if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port) | |
11276 | return; | |
c0c050c5 | 11277 | |
ad51b8e9 AD |
11278 | bp->vxlan_port_cnt++; |
11279 | if (bp->vxlan_port_cnt == 1) { | |
11280 | bp->vxlan_port = ti->port; | |
11281 | set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event); | |
c213eae8 | 11282 | bnxt_queue_sp_work(bp); |
ad51b8e9 AD |
11283 | } |
11284 | break; | |
7cdd5fc3 AD |
11285 | case UDP_TUNNEL_TYPE_GENEVE: |
11286 | if (bp->nge_port_cnt && bp->nge_port != ti->port) | |
11287 | return; | |
11288 | ||
11289 | bp->nge_port_cnt++; | |
11290 | if (bp->nge_port_cnt == 1) { | |
11291 | bp->nge_port = ti->port; | |
11292 | set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event); | |
11293 | } | |
11294 | break; | |
ad51b8e9 AD |
11295 | default: |
11296 | return; | |
c0c050c5 | 11297 | } |
ad51b8e9 | 11298 | |
c213eae8 | 11299 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
11300 | } |
11301 | ||
ad51b8e9 AD |
11302 | static void bnxt_udp_tunnel_del(struct net_device *dev, |
11303 | struct udp_tunnel_info *ti) | |
c0c050c5 MC |
11304 | { |
11305 | struct bnxt *bp = netdev_priv(dev); | |
11306 | ||
ad51b8e9 | 11307 | if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) |
c0c050c5 MC |
11308 | return; |
11309 | ||
ad51b8e9 | 11310 | if (!netif_running(dev)) |
c0c050c5 MC |
11311 | return; |
11312 | ||
ad51b8e9 AD |
11313 | switch (ti->type) { |
11314 | case UDP_TUNNEL_TYPE_VXLAN: | |
11315 | if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port) | |
11316 | return; | |
c0c050c5 MC |
11317 | bp->vxlan_port_cnt--; |
11318 | ||
ad51b8e9 AD |
11319 | if (bp->vxlan_port_cnt != 0) |
11320 | return; | |
11321 | ||
11322 | set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event); | |
11323 | break; | |
7cdd5fc3 AD |
11324 | case UDP_TUNNEL_TYPE_GENEVE: |
11325 | if (!bp->nge_port_cnt || bp->nge_port != ti->port) | |
11326 | return; | |
11327 | bp->nge_port_cnt--; | |
11328 | ||
11329 | if (bp->nge_port_cnt != 0) | |
11330 | return; | |
11331 | ||
11332 | set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event); | |
11333 | break; | |
ad51b8e9 AD |
11334 | default: |
11335 | return; | |
c0c050c5 | 11336 | } |
ad51b8e9 | 11337 | |
c213eae8 | 11338 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
11339 | } |
11340 | ||
39d8ba2e MC |
11341 | static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, |
11342 | struct net_device *dev, u32 filter_mask, | |
11343 | int nlflags) | |
11344 | { | |
11345 | struct bnxt *bp = netdev_priv(dev); | |
11346 | ||
11347 | return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0, | |
11348 | nlflags, filter_mask, NULL); | |
11349 | } | |
11350 | ||
11351 | static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, | |
2fd527b7 | 11352 | u16 flags, struct netlink_ext_ack *extack) |
39d8ba2e MC |
11353 | { |
11354 | struct bnxt *bp = netdev_priv(dev); | |
11355 | struct nlattr *attr, *br_spec; | |
11356 | int rem, rc = 0; | |
11357 | ||
11358 | if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp)) | |
11359 | return -EOPNOTSUPP; | |
11360 | ||
11361 | br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); | |
11362 | if (!br_spec) | |
11363 | return -EINVAL; | |
11364 | ||
11365 | nla_for_each_nested(attr, br_spec, rem) { | |
11366 | u16 mode; | |
11367 | ||
11368 | if (nla_type(attr) != IFLA_BRIDGE_MODE) | |
11369 | continue; | |
11370 | ||
11371 | if (nla_len(attr) < sizeof(mode)) | |
11372 | return -EINVAL; | |
11373 | ||
11374 | mode = nla_get_u16(attr); | |
11375 | if (mode == bp->br_mode) | |
11376 | break; | |
11377 | ||
11378 | rc = bnxt_hwrm_set_br_mode(bp, mode); | |
11379 | if (!rc) | |
11380 | bp->br_mode = mode; | |
11381 | break; | |
11382 | } | |
11383 | return rc; | |
11384 | } | |
11385 | ||
52d5254a FF |
11386 | int bnxt_get_port_parent_id(struct net_device *dev, |
11387 | struct netdev_phys_item_id *ppid) | |
c124a62f | 11388 | { |
52d5254a FF |
11389 | struct bnxt *bp = netdev_priv(dev); |
11390 | ||
c124a62f SP |
11391 | if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV) |
11392 | return -EOPNOTSUPP; | |
11393 | ||
11394 | /* The PF and it's VF-reps only support the switchdev framework */ | |
d061b241 | 11395 | if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_DSN_VALID)) |
c124a62f SP |
11396 | return -EOPNOTSUPP; |
11397 | ||
b014232f VV |
11398 | ppid->id_len = sizeof(bp->dsn); |
11399 | memcpy(ppid->id, bp->dsn, ppid->id_len); | |
c124a62f | 11400 | |
52d5254a | 11401 | return 0; |
c124a62f SP |
11402 | } |
11403 | ||
c9c49a65 JP |
11404 | static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev) |
11405 | { | |
11406 | struct bnxt *bp = netdev_priv(dev); | |
11407 | ||
11408 | return &bp->dl_port; | |
11409 | } | |
11410 | ||
c0c050c5 MC |
11411 | static const struct net_device_ops bnxt_netdev_ops = { |
11412 | .ndo_open = bnxt_open, | |
11413 | .ndo_start_xmit = bnxt_start_xmit, | |
11414 | .ndo_stop = bnxt_close, | |
11415 | .ndo_get_stats64 = bnxt_get_stats64, | |
11416 | .ndo_set_rx_mode = bnxt_set_rx_mode, | |
11417 | .ndo_do_ioctl = bnxt_ioctl, | |
11418 | .ndo_validate_addr = eth_validate_addr, | |
11419 | .ndo_set_mac_address = bnxt_change_mac_addr, | |
11420 | .ndo_change_mtu = bnxt_change_mtu, | |
11421 | .ndo_fix_features = bnxt_fix_features, | |
11422 | .ndo_set_features = bnxt_set_features, | |
11423 | .ndo_tx_timeout = bnxt_tx_timeout, | |
11424 | #ifdef CONFIG_BNXT_SRIOV | |
11425 | .ndo_get_vf_config = bnxt_get_vf_config, | |
11426 | .ndo_set_vf_mac = bnxt_set_vf_mac, | |
11427 | .ndo_set_vf_vlan = bnxt_set_vf_vlan, | |
11428 | .ndo_set_vf_rate = bnxt_set_vf_bw, | |
11429 | .ndo_set_vf_link_state = bnxt_set_vf_link_state, | |
11430 | .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, | |
746df139 | 11431 | .ndo_set_vf_trust = bnxt_set_vf_trust, |
c0c050c5 MC |
11432 | #endif |
11433 | .ndo_setup_tc = bnxt_setup_tc, | |
11434 | #ifdef CONFIG_RFS_ACCEL | |
11435 | .ndo_rx_flow_steer = bnxt_rx_flow_steer, | |
11436 | #endif | |
ad51b8e9 AD |
11437 | .ndo_udp_tunnel_add = bnxt_udp_tunnel_add, |
11438 | .ndo_udp_tunnel_del = bnxt_udp_tunnel_del, | |
f4e63525 | 11439 | .ndo_bpf = bnxt_xdp, |
f18c2b77 | 11440 | .ndo_xdp_xmit = bnxt_xdp_xmit, |
39d8ba2e MC |
11441 | .ndo_bridge_getlink = bnxt_bridge_getlink, |
11442 | .ndo_bridge_setlink = bnxt_bridge_setlink, | |
c9c49a65 | 11443 | .ndo_get_devlink_port = bnxt_get_devlink_port, |
c0c050c5 MC |
11444 | }; |
11445 | ||
11446 | static void bnxt_remove_one(struct pci_dev *pdev) | |
11447 | { | |
11448 | struct net_device *dev = pci_get_drvdata(pdev); | |
11449 | struct bnxt *bp = netdev_priv(dev); | |
11450 | ||
7e334fc8 | 11451 | if (BNXT_PF(bp)) |
c0c050c5 MC |
11452 | bnxt_sriov_disable(bp); |
11453 | ||
7e334fc8 | 11454 | bnxt_dl_fw_reporters_destroy(bp, true); |
6316ea6d | 11455 | pci_disable_pcie_error_reporting(pdev); |
c0c050c5 | 11456 | unregister_netdev(dev); |
cda2cab0 | 11457 | bnxt_dl_unregister(bp); |
2ae7408f | 11458 | bnxt_shutdown_tc(bp); |
c213eae8 | 11459 | bnxt_cancel_sp_work(bp); |
c0c050c5 MC |
11460 | bp->sp_event = 0; |
11461 | ||
7809592d | 11462 | bnxt_clear_int_mode(bp); |
be58a0da | 11463 | bnxt_hwrm_func_drv_unrgtr(bp); |
c0c050c5 | 11464 | bnxt_free_hwrm_resources(bp); |
e605db80 | 11465 | bnxt_free_hwrm_short_cmd_req(bp); |
eb513658 | 11466 | bnxt_ethtool_free(bp); |
7df4ae9f | 11467 | bnxt_dcb_free(bp); |
a588e458 MC |
11468 | kfree(bp->edev); |
11469 | bp->edev = NULL; | |
8280b38e VV |
11470 | kfree(bp->fw_health); |
11471 | bp->fw_health = NULL; | |
c20dc142 | 11472 | bnxt_cleanup_pci(bp); |
98f04cf0 MC |
11473 | bnxt_free_ctx_mem(bp); |
11474 | kfree(bp->ctx); | |
11475 | bp->ctx = NULL; | |
fd3ab1c7 | 11476 | bnxt_free_port_stats(bp); |
c0c050c5 | 11477 | free_netdev(dev); |
c0c050c5 MC |
11478 | } |
11479 | ||
ba642ab7 | 11480 | static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt) |
c0c050c5 MC |
11481 | { |
11482 | int rc = 0; | |
11483 | struct bnxt_link_info *link_info = &bp->link_info; | |
c0c050c5 | 11484 | |
170ce013 MC |
11485 | rc = bnxt_hwrm_phy_qcaps(bp); |
11486 | if (rc) { | |
11487 | netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n", | |
11488 | rc); | |
11489 | return rc; | |
11490 | } | |
43a5107d MC |
11491 | if (!fw_dflt) |
11492 | return 0; | |
11493 | ||
c0c050c5 MC |
11494 | rc = bnxt_update_link(bp, false); |
11495 | if (rc) { | |
11496 | netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", | |
11497 | rc); | |
11498 | return rc; | |
11499 | } | |
11500 | ||
93ed8117 MC |
11501 | /* Older firmware does not have supported_auto_speeds, so assume |
11502 | * that all supported speeds can be autonegotiated. | |
11503 | */ | |
11504 | if (link_info->auto_link_speeds && !link_info->support_auto_speeds) | |
11505 | link_info->support_auto_speeds = link_info->support_speeds; | |
11506 | ||
8119e49b | 11507 | bnxt_init_ethtool_link_settings(bp); |
ba642ab7 | 11508 | return 0; |
c0c050c5 MC |
11509 | } |
11510 | ||
11511 | static int bnxt_get_max_irq(struct pci_dev *pdev) | |
11512 | { | |
11513 | u16 ctrl; | |
11514 | ||
11515 | if (!pdev->msix_cap) | |
11516 | return 1; | |
11517 | ||
11518 | pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); | |
11519 | return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; | |
11520 | } | |
11521 | ||
6e6c5a57 MC |
11522 | static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, |
11523 | int *max_cp) | |
c0c050c5 | 11524 | { |
6a4f2947 | 11525 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; |
e30fbc33 | 11526 | int max_ring_grps = 0, max_irq; |
c0c050c5 | 11527 | |
6a4f2947 MC |
11528 | *max_tx = hw_resc->max_tx_rings; |
11529 | *max_rx = hw_resc->max_rx_rings; | |
e30fbc33 MC |
11530 | *max_cp = bnxt_get_max_func_cp_rings_for_en(bp); |
11531 | max_irq = min_t(int, bnxt_get_max_func_irqs(bp) - | |
11532 | bnxt_get_ulp_msix_num(bp), | |
c027c6b4 | 11533 | hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp)); |
e30fbc33 MC |
11534 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) |
11535 | *max_cp = min_t(int, *max_cp, max_irq); | |
6a4f2947 | 11536 | max_ring_grps = hw_resc->max_hw_ring_grps; |
76595193 PS |
11537 | if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) { |
11538 | *max_cp -= 1; | |
11539 | *max_rx -= 2; | |
11540 | } | |
c0c050c5 MC |
11541 | if (bp->flags & BNXT_FLAG_AGG_RINGS) |
11542 | *max_rx >>= 1; | |
e30fbc33 MC |
11543 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
11544 | bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false); | |
11545 | /* On P5 chips, max_cp output param should be available NQs */ | |
11546 | *max_cp = max_irq; | |
11547 | } | |
b72d4a68 | 11548 | *max_rx = min_t(int, *max_rx, max_ring_grps); |
6e6c5a57 MC |
11549 | } |
11550 | ||
11551 | int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) | |
11552 | { | |
11553 | int rx, tx, cp; | |
11554 | ||
11555 | _bnxt_get_max_rings(bp, &rx, &tx, &cp); | |
78f058a4 MC |
11556 | *max_rx = rx; |
11557 | *max_tx = tx; | |
6e6c5a57 MC |
11558 | if (!rx || !tx || !cp) |
11559 | return -ENOMEM; | |
11560 | ||
6e6c5a57 MC |
11561 | return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); |
11562 | } | |
11563 | ||
e4060d30 MC |
11564 | static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx, |
11565 | bool shared) | |
11566 | { | |
11567 | int rc; | |
11568 | ||
11569 | rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); | |
bdbd1eb5 MC |
11570 | if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) { |
11571 | /* Not enough rings, try disabling agg rings. */ | |
11572 | bp->flags &= ~BNXT_FLAG_AGG_RINGS; | |
11573 | rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); | |
07f4fde5 MC |
11574 | if (rc) { |
11575 | /* set BNXT_FLAG_AGG_RINGS back for consistency */ | |
11576 | bp->flags |= BNXT_FLAG_AGG_RINGS; | |
bdbd1eb5 | 11577 | return rc; |
07f4fde5 | 11578 | } |
bdbd1eb5 | 11579 | bp->flags |= BNXT_FLAG_NO_AGG_RINGS; |
1054aee8 MC |
11580 | bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); |
11581 | bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); | |
bdbd1eb5 MC |
11582 | bnxt_set_ring_params(bp); |
11583 | } | |
e4060d30 MC |
11584 | |
11585 | if (bp->flags & BNXT_FLAG_ROCE_CAP) { | |
11586 | int max_cp, max_stat, max_irq; | |
11587 | ||
11588 | /* Reserve minimum resources for RoCE */ | |
11589 | max_cp = bnxt_get_max_func_cp_rings(bp); | |
11590 | max_stat = bnxt_get_max_func_stat_ctxs(bp); | |
11591 | max_irq = bnxt_get_max_func_irqs(bp); | |
11592 | if (max_cp <= BNXT_MIN_ROCE_CP_RINGS || | |
11593 | max_irq <= BNXT_MIN_ROCE_CP_RINGS || | |
11594 | max_stat <= BNXT_MIN_ROCE_STAT_CTXS) | |
11595 | return 0; | |
11596 | ||
11597 | max_cp -= BNXT_MIN_ROCE_CP_RINGS; | |
11598 | max_irq -= BNXT_MIN_ROCE_CP_RINGS; | |
11599 | max_stat -= BNXT_MIN_ROCE_STAT_CTXS; | |
11600 | max_cp = min_t(int, max_cp, max_irq); | |
11601 | max_cp = min_t(int, max_cp, max_stat); | |
11602 | rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared); | |
11603 | if (rc) | |
11604 | rc = 0; | |
11605 | } | |
11606 | return rc; | |
11607 | } | |
11608 | ||
58ea801a MC |
11609 | /* In initial default shared ring setting, each shared ring must have a |
11610 | * RX/TX ring pair. | |
11611 | */ | |
11612 | static void bnxt_trim_dflt_sh_rings(struct bnxt *bp) | |
11613 | { | |
11614 | bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings); | |
11615 | bp->rx_nr_rings = bp->cp_nr_rings; | |
11616 | bp->tx_nr_rings_per_tc = bp->cp_nr_rings; | |
11617 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc; | |
11618 | } | |
11619 | ||
702c221c | 11620 | static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh) |
6e6c5a57 MC |
11621 | { |
11622 | int dflt_rings, max_rx_rings, max_tx_rings, rc; | |
6e6c5a57 | 11623 | |
2773dfb2 MC |
11624 | if (!bnxt_can_reserve_rings(bp)) |
11625 | return 0; | |
11626 | ||
6e6c5a57 MC |
11627 | if (sh) |
11628 | bp->flags |= BNXT_FLAG_SHARED_RINGS; | |
d629522e | 11629 | dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues(); |
1d3ef13d MC |
11630 | /* Reduce default rings on multi-port cards so that total default |
11631 | * rings do not exceed CPU count. | |
11632 | */ | |
11633 | if (bp->port_count > 1) { | |
11634 | int max_rings = | |
11635 | max_t(int, num_online_cpus() / bp->port_count, 1); | |
11636 | ||
11637 | dflt_rings = min_t(int, dflt_rings, max_rings); | |
11638 | } | |
e4060d30 | 11639 | rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh); |
6e6c5a57 MC |
11640 | if (rc) |
11641 | return rc; | |
11642 | bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); | |
11643 | bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); | |
58ea801a MC |
11644 | if (sh) |
11645 | bnxt_trim_dflt_sh_rings(bp); | |
11646 | else | |
11647 | bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings; | |
11648 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc; | |
391be5c2 | 11649 | |
674f50a5 | 11650 | rc = __bnxt_reserve_rings(bp); |
391be5c2 MC |
11651 | if (rc) |
11652 | netdev_warn(bp->dev, "Unable to reserve tx rings\n"); | |
58ea801a MC |
11653 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; |
11654 | if (sh) | |
11655 | bnxt_trim_dflt_sh_rings(bp); | |
391be5c2 | 11656 | |
674f50a5 MC |
11657 | /* Rings may have been trimmed, re-reserve the trimmed rings. */ |
11658 | if (bnxt_need_reserve_rings(bp)) { | |
11659 | rc = __bnxt_reserve_rings(bp); | |
11660 | if (rc) | |
11661 | netdev_warn(bp->dev, "2nd rings reservation failed.\n"); | |
11662 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; | |
11663 | } | |
76595193 PS |
11664 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { |
11665 | bp->rx_nr_rings++; | |
11666 | bp->cp_nr_rings++; | |
11667 | } | |
6e6c5a57 | 11668 | return rc; |
c0c050c5 MC |
11669 | } |
11670 | ||
47558acd MC |
11671 | static int bnxt_init_dflt_ring_mode(struct bnxt *bp) |
11672 | { | |
11673 | int rc; | |
11674 | ||
11675 | if (bp->tx_nr_rings) | |
11676 | return 0; | |
11677 | ||
6b95c3e9 MC |
11678 | bnxt_ulp_irq_stop(bp); |
11679 | bnxt_clear_int_mode(bp); | |
47558acd MC |
11680 | rc = bnxt_set_dflt_rings(bp, true); |
11681 | if (rc) { | |
11682 | netdev_err(bp->dev, "Not enough rings available.\n"); | |
6b95c3e9 | 11683 | goto init_dflt_ring_err; |
47558acd MC |
11684 | } |
11685 | rc = bnxt_init_int_mode(bp); | |
11686 | if (rc) | |
6b95c3e9 MC |
11687 | goto init_dflt_ring_err; |
11688 | ||
47558acd MC |
11689 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; |
11690 | if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) { | |
11691 | bp->flags |= BNXT_FLAG_RFS; | |
11692 | bp->dev->features |= NETIF_F_NTUPLE; | |
11693 | } | |
6b95c3e9 MC |
11694 | init_dflt_ring_err: |
11695 | bnxt_ulp_irq_restart(bp, rc); | |
11696 | return rc; | |
47558acd MC |
11697 | } |
11698 | ||
80fcaf46 | 11699 | int bnxt_restore_pf_fw_resources(struct bnxt *bp) |
7b08f661 | 11700 | { |
80fcaf46 MC |
11701 | int rc; |
11702 | ||
7b08f661 MC |
11703 | ASSERT_RTNL(); |
11704 | bnxt_hwrm_func_qcaps(bp); | |
1a037782 VD |
11705 | |
11706 | if (netif_running(bp->dev)) | |
11707 | __bnxt_close_nic(bp, true, false); | |
11708 | ||
ec86f14e | 11709 | bnxt_ulp_irq_stop(bp); |
80fcaf46 MC |
11710 | bnxt_clear_int_mode(bp); |
11711 | rc = bnxt_init_int_mode(bp); | |
ec86f14e | 11712 | bnxt_ulp_irq_restart(bp, rc); |
1a037782 VD |
11713 | |
11714 | if (netif_running(bp->dev)) { | |
11715 | if (rc) | |
11716 | dev_close(bp->dev); | |
11717 | else | |
11718 | rc = bnxt_open_nic(bp, true, false); | |
11719 | } | |
11720 | ||
80fcaf46 | 11721 | return rc; |
7b08f661 MC |
11722 | } |
11723 | ||
a22a6ac2 MC |
11724 | static int bnxt_init_mac_addr(struct bnxt *bp) |
11725 | { | |
11726 | int rc = 0; | |
11727 | ||
11728 | if (BNXT_PF(bp)) { | |
11729 | memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN); | |
11730 | } else { | |
11731 | #ifdef CONFIG_BNXT_SRIOV | |
11732 | struct bnxt_vf_info *vf = &bp->vf; | |
28ea334b | 11733 | bool strict_approval = true; |
a22a6ac2 MC |
11734 | |
11735 | if (is_valid_ether_addr(vf->mac_addr)) { | |
91cdda40 | 11736 | /* overwrite netdev dev_addr with admin VF MAC */ |
a22a6ac2 | 11737 | memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN); |
28ea334b MC |
11738 | /* Older PF driver or firmware may not approve this |
11739 | * correctly. | |
11740 | */ | |
11741 | strict_approval = false; | |
a22a6ac2 MC |
11742 | } else { |
11743 | eth_hw_addr_random(bp->dev); | |
a22a6ac2 | 11744 | } |
28ea334b | 11745 | rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval); |
a22a6ac2 MC |
11746 | #endif |
11747 | } | |
11748 | return rc; | |
11749 | } | |
11750 | ||
03213a99 JP |
11751 | static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[]) |
11752 | { | |
11753 | struct pci_dev *pdev = bp->pdev; | |
8d85b75b | 11754 | u64 qword; |
03213a99 | 11755 | |
8d85b75b JK |
11756 | qword = pci_get_dsn(pdev); |
11757 | if (!qword) { | |
11758 | netdev_info(bp->dev, "Unable to read adapter's DSN\n"); | |
03213a99 JP |
11759 | return -EOPNOTSUPP; |
11760 | } | |
11761 | ||
8d85b75b JK |
11762 | put_unaligned_le64(qword, dsn); |
11763 | ||
d061b241 | 11764 | bp->flags |= BNXT_FLAG_DSN_VALID; |
03213a99 JP |
11765 | return 0; |
11766 | } | |
11767 | ||
c0c050c5 MC |
11768 | static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
11769 | { | |
c0c050c5 MC |
11770 | struct net_device *dev; |
11771 | struct bnxt *bp; | |
6e6c5a57 | 11772 | int rc, max_irqs; |
c0c050c5 | 11773 | |
4e00338a | 11774 | if (pci_is_bridge(pdev)) |
fa853dda PS |
11775 | return -ENODEV; |
11776 | ||
8743db4a VV |
11777 | /* Clear any pending DMA transactions from crash kernel |
11778 | * while loading driver in capture kernel. | |
11779 | */ | |
11780 | if (is_kdump_kernel()) { | |
11781 | pci_clear_master(pdev); | |
11782 | pcie_flr(pdev); | |
11783 | } | |
11784 | ||
c0c050c5 MC |
11785 | max_irqs = bnxt_get_max_irq(pdev); |
11786 | dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); | |
11787 | if (!dev) | |
11788 | return -ENOMEM; | |
11789 | ||
11790 | bp = netdev_priv(dev); | |
9c1fabdf | 11791 | bnxt_set_max_func_irqs(bp, max_irqs); |
c0c050c5 MC |
11792 | |
11793 | if (bnxt_vf_pciid(ent->driver_data)) | |
11794 | bp->flags |= BNXT_FLAG_VF; | |
11795 | ||
2bcfa6f6 | 11796 | if (pdev->msix_cap) |
c0c050c5 | 11797 | bp->flags |= BNXT_FLAG_MSIX_CAP; |
c0c050c5 MC |
11798 | |
11799 | rc = bnxt_init_board(pdev, dev); | |
11800 | if (rc < 0) | |
11801 | goto init_err_free; | |
11802 | ||
11803 | dev->netdev_ops = &bnxt_netdev_ops; | |
11804 | dev->watchdog_timeo = BNXT_TX_TIMEOUT; | |
11805 | dev->ethtool_ops = &bnxt_ethtool_ops; | |
c0c050c5 MC |
11806 | pci_set_drvdata(pdev, dev); |
11807 | ||
3e8060fa PS |
11808 | rc = bnxt_alloc_hwrm_resources(bp); |
11809 | if (rc) | |
17086399 | 11810 | goto init_err_pci_clean; |
3e8060fa PS |
11811 | |
11812 | mutex_init(&bp->hwrm_cmd_lock); | |
ba642ab7 | 11813 | mutex_init(&bp->link_lock); |
7c380918 MC |
11814 | |
11815 | rc = bnxt_fw_init_one_p1(bp); | |
3e8060fa | 11816 | if (rc) |
17086399 | 11817 | goto init_err_pci_clean; |
3e8060fa | 11818 | |
e38287b7 MC |
11819 | if (BNXT_CHIP_P5(bp)) |
11820 | bp->flags |= BNXT_FLAG_CHIP_P5; | |
11821 | ||
7c380918 | 11822 | rc = bnxt_fw_init_one_p2(bp); |
3c2217a6 MC |
11823 | if (rc) |
11824 | goto init_err_pci_clean; | |
11825 | ||
c0c050c5 MC |
11826 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | |
11827 | NETIF_F_TSO | NETIF_F_TSO6 | | |
11828 | NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | | |
7e13318d | 11829 | NETIF_F_GSO_IPXIP4 | |
152971ee AD |
11830 | NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | |
11831 | NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH | | |
3e8060fa PS |
11832 | NETIF_F_RXCSUM | NETIF_F_GRO; |
11833 | ||
e38287b7 | 11834 | if (BNXT_SUPPORTS_TPA(bp)) |
3e8060fa | 11835 | dev->hw_features |= NETIF_F_LRO; |
c0c050c5 | 11836 | |
c0c050c5 MC |
11837 | dev->hw_enc_features = |
11838 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | | |
11839 | NETIF_F_TSO | NETIF_F_TSO6 | | |
11840 | NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | | |
152971ee | 11841 | NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | |
7e13318d | 11842 | NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL; |
152971ee AD |
11843 | dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM | |
11844 | NETIF_F_GSO_GRE_CSUM; | |
c0c050c5 MC |
11845 | dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; |
11846 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | | |
11847 | NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX; | |
e38287b7 | 11848 | if (BNXT_SUPPORTS_TPA(bp)) |
1054aee8 | 11849 | dev->hw_features |= NETIF_F_GRO_HW; |
c0c050c5 | 11850 | dev->features |= dev->hw_features | NETIF_F_HIGHDMA; |
1054aee8 MC |
11851 | if (dev->features & NETIF_F_GRO_HW) |
11852 | dev->features &= ~NETIF_F_LRO; | |
c0c050c5 MC |
11853 | dev->priv_flags |= IFF_UNICAST_FLT; |
11854 | ||
11855 | #ifdef CONFIG_BNXT_SRIOV | |
11856 | init_waitqueue_head(&bp->sriov_cfg_wait); | |
4ab0c6a8 | 11857 | mutex_init(&bp->sriov_lock); |
c0c050c5 | 11858 | #endif |
e38287b7 MC |
11859 | if (BNXT_SUPPORTS_TPA(bp)) { |
11860 | bp->gro_func = bnxt_gro_func_5730x; | |
67912c36 | 11861 | if (BNXT_CHIP_P4(bp)) |
e38287b7 | 11862 | bp->gro_func = bnxt_gro_func_5731x; |
67912c36 MC |
11863 | else if (BNXT_CHIP_P5(bp)) |
11864 | bp->gro_func = bnxt_gro_func_5750x; | |
e38287b7 MC |
11865 | } |
11866 | if (!BNXT_CHIP_P4_PLUS(bp)) | |
434c975a | 11867 | bp->flags |= BNXT_FLAG_DOUBLE_DB; |
309369c9 | 11868 | |
a588e458 MC |
11869 | bp->ulp_probe = bnxt_ulp_probe; |
11870 | ||
a22a6ac2 MC |
11871 | rc = bnxt_init_mac_addr(bp); |
11872 | if (rc) { | |
11873 | dev_err(&pdev->dev, "Unable to initialize mac address.\n"); | |
11874 | rc = -EADDRNOTAVAIL; | |
11875 | goto init_err_pci_clean; | |
11876 | } | |
c0c050c5 | 11877 | |
2e9217d1 VV |
11878 | if (BNXT_PF(bp)) { |
11879 | /* Read the adapter's DSN to use as the eswitch switch_id */ | |
b014232f | 11880 | rc = bnxt_pcie_dsn_get(bp, bp->dsn); |
2e9217d1 | 11881 | } |
567b2abe | 11882 | |
7eb9bb3a MC |
11883 | /* MTU range: 60 - FW defined max */ |
11884 | dev->min_mtu = ETH_ZLEN; | |
11885 | dev->max_mtu = bp->max_mtu; | |
11886 | ||
ba642ab7 | 11887 | rc = bnxt_probe_phy(bp, true); |
d5430d31 MC |
11888 | if (rc) |
11889 | goto init_err_pci_clean; | |
11890 | ||
c61fb99c | 11891 | bnxt_set_rx_skb_mode(bp, false); |
c0c050c5 MC |
11892 | bnxt_set_tpa_flags(bp); |
11893 | bnxt_set_ring_params(bp); | |
702c221c | 11894 | rc = bnxt_set_dflt_rings(bp, true); |
bdbd1eb5 MC |
11895 | if (rc) { |
11896 | netdev_err(bp->dev, "Not enough rings available.\n"); | |
11897 | rc = -ENOMEM; | |
17086399 | 11898 | goto init_err_pci_clean; |
bdbd1eb5 | 11899 | } |
c0c050c5 | 11900 | |
ba642ab7 | 11901 | bnxt_fw_init_one_p3(bp); |
2bcfa6f6 | 11902 | |
c0c050c5 MC |
11903 | if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX) |
11904 | bp->flags |= BNXT_FLAG_STRIP_VLAN; | |
11905 | ||
7809592d | 11906 | rc = bnxt_init_int_mode(bp); |
c0c050c5 | 11907 | if (rc) |
17086399 | 11908 | goto init_err_pci_clean; |
c0c050c5 | 11909 | |
832aed16 MC |
11910 | /* No TC has been set yet and rings may have been trimmed due to |
11911 | * limited MSIX, so we re-initialize the TX rings per TC. | |
11912 | */ | |
11913 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; | |
11914 | ||
c213eae8 MC |
11915 | if (BNXT_PF(bp)) { |
11916 | if (!bnxt_pf_wq) { | |
11917 | bnxt_pf_wq = | |
11918 | create_singlethread_workqueue("bnxt_pf_wq"); | |
11919 | if (!bnxt_pf_wq) { | |
11920 | dev_err(&pdev->dev, "Unable to create workqueue.\n"); | |
11921 | goto init_err_pci_clean; | |
11922 | } | |
11923 | } | |
2ae7408f | 11924 | bnxt_init_tc(bp); |
c213eae8 | 11925 | } |
2ae7408f | 11926 | |
cda2cab0 VV |
11927 | bnxt_dl_register(bp); |
11928 | ||
7809592d MC |
11929 | rc = register_netdev(dev); |
11930 | if (rc) | |
cda2cab0 | 11931 | goto init_err_cleanup; |
7809592d | 11932 | |
cda2cab0 VV |
11933 | if (BNXT_PF(bp)) |
11934 | devlink_port_type_eth_set(&bp->dl_port, bp->dev); | |
7e334fc8 | 11935 | bnxt_dl_fw_reporters_create(bp); |
4ab0c6a8 | 11936 | |
c0c050c5 MC |
11937 | netdev_info(dev, "%s found at mem %lx, node addr %pM\n", |
11938 | board_info[ent->driver_data].name, | |
11939 | (long)pci_resource_start(pdev, 0), dev->dev_addr); | |
af125b75 | 11940 | pcie_print_link_status(pdev); |
90c4f788 | 11941 | |
c0c050c5 MC |
11942 | return 0; |
11943 | ||
cda2cab0 VV |
11944 | init_err_cleanup: |
11945 | bnxt_dl_unregister(bp); | |
2ae7408f | 11946 | bnxt_shutdown_tc(bp); |
7809592d MC |
11947 | bnxt_clear_int_mode(bp); |
11948 | ||
17086399 | 11949 | init_err_pci_clean: |
bdb38602 | 11950 | bnxt_hwrm_func_drv_unrgtr(bp); |
f9099d61 | 11951 | bnxt_free_hwrm_short_cmd_req(bp); |
a2bf74f4 | 11952 | bnxt_free_hwrm_resources(bp); |
98f04cf0 MC |
11953 | bnxt_free_ctx_mem(bp); |
11954 | kfree(bp->ctx); | |
11955 | bp->ctx = NULL; | |
07f83d72 MC |
11956 | kfree(bp->fw_health); |
11957 | bp->fw_health = NULL; | |
17086399 | 11958 | bnxt_cleanup_pci(bp); |
c0c050c5 MC |
11959 | |
11960 | init_err_free: | |
11961 | free_netdev(dev); | |
11962 | return rc; | |
11963 | } | |
11964 | ||
d196ece7 MC |
11965 | static void bnxt_shutdown(struct pci_dev *pdev) |
11966 | { | |
11967 | struct net_device *dev = pci_get_drvdata(pdev); | |
11968 | struct bnxt *bp; | |
11969 | ||
11970 | if (!dev) | |
11971 | return; | |
11972 | ||
11973 | rtnl_lock(); | |
11974 | bp = netdev_priv(dev); | |
11975 | if (!bp) | |
11976 | goto shutdown_exit; | |
11977 | ||
11978 | if (netif_running(dev)) | |
11979 | dev_close(dev); | |
11980 | ||
a7f3f939 | 11981 | bnxt_ulp_shutdown(bp); |
5567ae4a VV |
11982 | bnxt_clear_int_mode(bp); |
11983 | pci_disable_device(pdev); | |
a7f3f939 | 11984 | |
d196ece7 | 11985 | if (system_state == SYSTEM_POWER_OFF) { |
d196ece7 MC |
11986 | pci_wake_from_d3(pdev, bp->wol); |
11987 | pci_set_power_state(pdev, PCI_D3hot); | |
11988 | } | |
11989 | ||
11990 | shutdown_exit: | |
11991 | rtnl_unlock(); | |
11992 | } | |
11993 | ||
f65a2044 MC |
11994 | #ifdef CONFIG_PM_SLEEP |
11995 | static int bnxt_suspend(struct device *device) | |
11996 | { | |
f521eaa9 | 11997 | struct net_device *dev = dev_get_drvdata(device); |
f65a2044 MC |
11998 | struct bnxt *bp = netdev_priv(dev); |
11999 | int rc = 0; | |
12000 | ||
12001 | rtnl_lock(); | |
6a68749d | 12002 | bnxt_ulp_stop(bp); |
f65a2044 MC |
12003 | if (netif_running(dev)) { |
12004 | netif_device_detach(dev); | |
12005 | rc = bnxt_close(dev); | |
12006 | } | |
12007 | bnxt_hwrm_func_drv_unrgtr(bp); | |
ef02af8c | 12008 | pci_disable_device(bp->pdev); |
f9b69d7f VV |
12009 | bnxt_free_ctx_mem(bp); |
12010 | kfree(bp->ctx); | |
12011 | bp->ctx = NULL; | |
f65a2044 MC |
12012 | rtnl_unlock(); |
12013 | return rc; | |
12014 | } | |
12015 | ||
12016 | static int bnxt_resume(struct device *device) | |
12017 | { | |
f521eaa9 | 12018 | struct net_device *dev = dev_get_drvdata(device); |
f65a2044 MC |
12019 | struct bnxt *bp = netdev_priv(dev); |
12020 | int rc = 0; | |
12021 | ||
12022 | rtnl_lock(); | |
ef02af8c MC |
12023 | rc = pci_enable_device(bp->pdev); |
12024 | if (rc) { | |
12025 | netdev_err(dev, "Cannot re-enable PCI device during resume, err = %d\n", | |
12026 | rc); | |
12027 | goto resume_exit; | |
12028 | } | |
12029 | pci_set_master(bp->pdev); | |
f92335d8 | 12030 | if (bnxt_hwrm_ver_get(bp)) { |
f65a2044 MC |
12031 | rc = -ENODEV; |
12032 | goto resume_exit; | |
12033 | } | |
12034 | rc = bnxt_hwrm_func_reset(bp); | |
12035 | if (rc) { | |
12036 | rc = -EBUSY; | |
12037 | goto resume_exit; | |
12038 | } | |
f92335d8 | 12039 | |
f9b69d7f VV |
12040 | if (bnxt_hwrm_queue_qportcfg(bp)) { |
12041 | rc = -ENODEV; | |
12042 | goto resume_exit; | |
12043 | } | |
12044 | ||
12045 | if (bp->hwrm_spec_code >= 0x10803) { | |
12046 | if (bnxt_alloc_ctx_mem(bp)) { | |
12047 | rc = -ENODEV; | |
12048 | goto resume_exit; | |
12049 | } | |
12050 | } | |
f92335d8 VV |
12051 | if (BNXT_NEW_RM(bp)) |
12052 | bnxt_hwrm_func_resc_qcaps(bp, false); | |
12053 | ||
12054 | if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) { | |
12055 | rc = -ENODEV; | |
12056 | goto resume_exit; | |
12057 | } | |
12058 | ||
f65a2044 MC |
12059 | bnxt_get_wol_settings(bp); |
12060 | if (netif_running(dev)) { | |
12061 | rc = bnxt_open(dev); | |
12062 | if (!rc) | |
12063 | netif_device_attach(dev); | |
12064 | } | |
12065 | ||
12066 | resume_exit: | |
6a68749d | 12067 | bnxt_ulp_start(bp, rc); |
f65a2044 MC |
12068 | rtnl_unlock(); |
12069 | return rc; | |
12070 | } | |
12071 | ||
12072 | static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume); | |
12073 | #define BNXT_PM_OPS (&bnxt_pm_ops) | |
12074 | ||
12075 | #else | |
12076 | ||
12077 | #define BNXT_PM_OPS NULL | |
12078 | ||
12079 | #endif /* CONFIG_PM_SLEEP */ | |
12080 | ||
6316ea6d SB |
12081 | /** |
12082 | * bnxt_io_error_detected - called when PCI error is detected | |
12083 | * @pdev: Pointer to PCI device | |
12084 | * @state: The current pci connection state | |
12085 | * | |
12086 | * This function is called after a PCI bus error affecting | |
12087 | * this device has been detected. | |
12088 | */ | |
12089 | static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev, | |
12090 | pci_channel_state_t state) | |
12091 | { | |
12092 | struct net_device *netdev = pci_get_drvdata(pdev); | |
a588e458 | 12093 | struct bnxt *bp = netdev_priv(netdev); |
6316ea6d SB |
12094 | |
12095 | netdev_info(netdev, "PCI I/O error detected\n"); | |
12096 | ||
12097 | rtnl_lock(); | |
12098 | netif_device_detach(netdev); | |
12099 | ||
a588e458 MC |
12100 | bnxt_ulp_stop(bp); |
12101 | ||
6316ea6d SB |
12102 | if (state == pci_channel_io_perm_failure) { |
12103 | rtnl_unlock(); | |
12104 | return PCI_ERS_RESULT_DISCONNECT; | |
12105 | } | |
12106 | ||
12107 | if (netif_running(netdev)) | |
12108 | bnxt_close(netdev); | |
12109 | ||
12110 | pci_disable_device(pdev); | |
12111 | rtnl_unlock(); | |
12112 | ||
12113 | /* Request a slot slot reset. */ | |
12114 | return PCI_ERS_RESULT_NEED_RESET; | |
12115 | } | |
12116 | ||
12117 | /** | |
12118 | * bnxt_io_slot_reset - called after the pci bus has been reset. | |
12119 | * @pdev: Pointer to PCI device | |
12120 | * | |
12121 | * Restart the card from scratch, as if from a cold-boot. | |
12122 | * At this point, the card has exprienced a hard reset, | |
12123 | * followed by fixups by BIOS, and has its config space | |
12124 | * set up identically to what it was at cold boot. | |
12125 | */ | |
12126 | static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) | |
12127 | { | |
12128 | struct net_device *netdev = pci_get_drvdata(pdev); | |
12129 | struct bnxt *bp = netdev_priv(netdev); | |
12130 | int err = 0; | |
12131 | pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; | |
12132 | ||
12133 | netdev_info(bp->dev, "PCI Slot Reset\n"); | |
12134 | ||
12135 | rtnl_lock(); | |
12136 | ||
12137 | if (pci_enable_device(pdev)) { | |
12138 | dev_err(&pdev->dev, | |
12139 | "Cannot re-enable PCI device after reset.\n"); | |
12140 | } else { | |
12141 | pci_set_master(pdev); | |
12142 | ||
aa8ed021 MC |
12143 | err = bnxt_hwrm_func_reset(bp); |
12144 | if (!err && netif_running(netdev)) | |
6316ea6d SB |
12145 | err = bnxt_open(netdev); |
12146 | ||
aa46dfff | 12147 | if (!err) |
6316ea6d | 12148 | result = PCI_ERS_RESULT_RECOVERED; |
aa46dfff | 12149 | bnxt_ulp_start(bp, err); |
6316ea6d SB |
12150 | } |
12151 | ||
12152 | if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev)) | |
12153 | dev_close(netdev); | |
12154 | ||
12155 | rtnl_unlock(); | |
12156 | ||
6316ea6d SB |
12157 | return PCI_ERS_RESULT_RECOVERED; |
12158 | } | |
12159 | ||
12160 | /** | |
12161 | * bnxt_io_resume - called when traffic can start flowing again. | |
12162 | * @pdev: Pointer to PCI device | |
12163 | * | |
12164 | * This callback is called when the error recovery driver tells | |
12165 | * us that its OK to resume normal operation. | |
12166 | */ | |
12167 | static void bnxt_io_resume(struct pci_dev *pdev) | |
12168 | { | |
12169 | struct net_device *netdev = pci_get_drvdata(pdev); | |
12170 | ||
12171 | rtnl_lock(); | |
12172 | ||
12173 | netif_device_attach(netdev); | |
12174 | ||
12175 | rtnl_unlock(); | |
12176 | } | |
12177 | ||
12178 | static const struct pci_error_handlers bnxt_err_handler = { | |
12179 | .error_detected = bnxt_io_error_detected, | |
12180 | .slot_reset = bnxt_io_slot_reset, | |
12181 | .resume = bnxt_io_resume | |
12182 | }; | |
12183 | ||
c0c050c5 MC |
12184 | static struct pci_driver bnxt_pci_driver = { |
12185 | .name = DRV_MODULE_NAME, | |
12186 | .id_table = bnxt_pci_tbl, | |
12187 | .probe = bnxt_init_one, | |
12188 | .remove = bnxt_remove_one, | |
d196ece7 | 12189 | .shutdown = bnxt_shutdown, |
f65a2044 | 12190 | .driver.pm = BNXT_PM_OPS, |
6316ea6d | 12191 | .err_handler = &bnxt_err_handler, |
c0c050c5 MC |
12192 | #if defined(CONFIG_BNXT_SRIOV) |
12193 | .sriov_configure = bnxt_sriov_configure, | |
12194 | #endif | |
12195 | }; | |
12196 | ||
c213eae8 MC |
12197 | static int __init bnxt_init(void) |
12198 | { | |
cabfb09d | 12199 | bnxt_debug_init(); |
c213eae8 MC |
12200 | return pci_register_driver(&bnxt_pci_driver); |
12201 | } | |
12202 | ||
12203 | static void __exit bnxt_exit(void) | |
12204 | { | |
12205 | pci_unregister_driver(&bnxt_pci_driver); | |
12206 | if (bnxt_pf_wq) | |
12207 | destroy_workqueue(bnxt_pf_wq); | |
cabfb09d | 12208 | bnxt_debug_exit(); |
c213eae8 MC |
12209 | } |
12210 | ||
12211 | module_init(bnxt_init); | |
12212 | module_exit(bnxt_exit); |