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bnxt_en: Refactor bnxt_poll_work().
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
CommitLineData
c0c050c5
MC		 1/* Broadcom NetXtreme-C/E network driver.
2 *
11f15ed3 3 * Copyright (c) 2014-2016 Broadcom Corporation
894aa69a 4 * Copyright (c) 2016-2018 Broadcom Limited
c0c050c5
MC		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12
13#include <linux/stringify.h>
14#include <linux/kernel.h>
15#include <linux/timer.h>
16#include <linux/errno.h>
17#include <linux/ioport.h>
18#include <linux/slab.h>
19#include <linux/vmalloc.h>
20#include <linux/interrupt.h>
21#include <linux/pci.h>
22#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24#include <linux/skbuff.h>
25#include <linux/dma-mapping.h>
26#include <linux/bitops.h>
27#include <linux/io.h>
28#include <linux/irq.h>
29#include <linux/delay.h>
30#include <asm/byteorder.h>
31#include <asm/page.h>
32#include <linux/time.h>
33#include <linux/mii.h>
34#include <linux/if.h>
35#include <linux/if_vlan.h>
32e8239c 36#include <linux/if_bridge.h>
5ac67d8b 37#include <linux/rtc.h>
c6d30e83 38#include <linux/bpf.h>
c0c050c5
MC		 39#include <net/ip.h>
40#include <net/tcp.h>
41#include <net/udp.h>
42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
ad51b8e9 44#include <net/udp_tunnel.h>
c0c050c5
MC		 45#include <linux/workqueue.h>
46#include <linux/prefetch.h>
47#include <linux/cache.h>
48#include <linux/log2.h>
49#include <linux/aer.h>
50#include <linux/bitmap.h>
51#include <linux/cpu_rmap.h>
56f0fd80 52#include <linux/cpumask.h>
2ae7408f 53#include <net/pkt_cls.h>
cde49a42
VV		 54#include <linux/hwmon.h>
55#include <linux/hwmon-sysfs.h>
c0c050c5
MC		 56
57#include "bnxt_hsi.h"
58#include "bnxt.h"
a588e458 59#include "bnxt_ulp.h"
c0c050c5
MC		 60#include "bnxt_sriov.h"
61#include "bnxt_ethtool.h"
7df4ae9f 62#include "bnxt_dcb.h"
c6d30e83 63#include "bnxt_xdp.h"
4ab0c6a8 64#include "bnxt_vfr.h"
2ae7408f 65#include "bnxt_tc.h"
3c467bf3 66#include "bnxt_devlink.h"
cabfb09d 67#include "bnxt_debugfs.h"
c0c050c5
MC		 68
69#define BNXT_TX_TIMEOUT (5 * HZ)
70
71static const char version[] =
72 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
73
74MODULE_LICENSE("GPL");
75MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
76MODULE_VERSION(DRV_MODULE_VERSION);
77
78#define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
79#define BNXT_RX_DMA_OFFSET NET_SKB_PAD
80#define BNXT_RX_COPY_THRESH 256
81
4419dbe6 82#define BNXT_TX_PUSH_THRESH 164
c0c050c5
MC		 83
84enum board_idx {
fbc9a523 85 BCM57301,
c0c050c5
MC		 86 BCM57302,
87 BCM57304,
1f681688 88 BCM57417_NPAR,
fa853dda 89 BCM58700,
b24eb6ae
MC		 90 BCM57311,
91 BCM57312,
fbc9a523 92 BCM57402,
c0c050c5
MC		 93 BCM57404,
94 BCM57406,
1f681688
MC		 95 BCM57402_NPAR,
96 BCM57407,
b24eb6ae
MC		 97 BCM57412,
98 BCM57414,
99 BCM57416,
100 BCM57417,
1f681688 101 BCM57412_NPAR,
5049e33b 102 BCM57314,
1f681688
MC		 103 BCM57417_SFP,
104 BCM57416_SFP,
105 BCM57404_NPAR,
106 BCM57406_NPAR,
107 BCM57407_SFP,
adbc8305 108 BCM57407_NPAR,
1f681688
MC		 109 BCM57414_NPAR,
110 BCM57416_NPAR,
32b40798
DK		 111 BCM57452,
112 BCM57454,
92abef36 113 BCM5745x_NPAR,
4a58139b 114 BCM58802,
8ed693b7 115 BCM58804,
4a58139b 116 BCM58808,
adbc8305
MC		 117 NETXTREME_E_VF,
118 NETXTREME_C_VF,
618784e3 119 NETXTREME_S_VF,
c0c050c5
MC		 120};
121
122/* indexed by enum above */
123static const struct {
124 char *name;
125} board_info[] = {
27573a7d
SB		 126 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
127 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
128 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
129 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
130 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
131 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
132 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
133 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
134 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
135 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
136 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
137 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
138 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
139 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
140 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
141 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
142 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
143 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
144 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
145 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
146 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
147 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
148 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
149 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
150 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
151 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
152 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
153 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
92abef36 154 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
27573a7d 155 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
8ed693b7 156 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
27573a7d
SB		 157 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
158 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
159 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
618784e3 160 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
c0c050c5
MC		 161};
162
163static const struct pci_device_id bnxt_pci_tbl[] = {
92abef36
VV		 164 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
165 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
4a58139b 166 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
adbc8305 167 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
fbc9a523 168 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
c0c050c5
MC		 169 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
170 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
1f681688 171 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
fa853dda 172 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
b24eb6ae
MC		 173 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
174 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
fbc9a523 175 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
c0c050c5
MC		 176 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
177 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
1f681688
MC		 178 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
179 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
b24eb6ae
MC		 180 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
181 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
182 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
183 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
1f681688 184 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
5049e33b 185 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
1f681688
MC		 186 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
187 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
188 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
189 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
190 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
adbc8305
MC		 191 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
192 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
1f681688 193 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
adbc8305 194 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
1f681688 195 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
adbc8305 196 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
4a58139b 197 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
32b40798 198 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
4a58139b 199 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
8ed693b7 200 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
c0c050c5 201#ifdef CONFIG_BNXT_SRIOV
c7ef35eb
DK		 202 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
203 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
adbc8305
MC		 204 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
205 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
206 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
207 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
208 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
209 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
618784e3 210 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
c0c050c5
MC		 211#endif
212 { 0 }
213};
214
215MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
216
217static const u16 bnxt_vf_req_snif[] = {
218 HWRM_FUNC_CFG,
91cdda40 219 HWRM_FUNC_VF_CFG,
c0c050c5
MC		 220 HWRM_PORT_PHY_QCFG,
221 HWRM_CFA_L2_FILTER_ALLOC,
222};
223
25be8623 224static const u16 bnxt_async_events_arr[] = {
87c374de
MC		 225 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
226 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
227 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
228 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
229 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
25be8623
MC		 230};
231
c213eae8
MC		 232static struct workqueue_struct *bnxt_pf_wq;
233
c0c050c5
MC		 234static bool bnxt_vf_pciid(enum board_idx idx)
235{
618784e3
RM		 236 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
237 idx == NETXTREME_S_VF);
c0c050c5
MC		 238}
239
240#define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
241#define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
242#define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
243
c0c050c5
MC		 244#define BNXT_CP_DB_IRQ_DIS(db) \
245 writel(DB_CP_IRQ_DIS_FLAGS, db)
246
697197e5
MC		 247#define BNXT_DB_CQ(db, idx) \
248 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
249
250#define BNXT_DB_NQ_P5(db, idx) \
251 writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell)
252
253#define BNXT_DB_CQ_ARM(db, idx) \
254 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
255
256#define BNXT_DB_NQ_ARM_P5(db, idx) \
257 writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell)
258
259static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
260{
261 if (bp->flags & BNXT_FLAG_CHIP_P5)
262 BNXT_DB_NQ_P5(db, idx);
263 else
264 BNXT_DB_CQ(db, idx);
265}
266
267static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
268{
269 if (bp->flags & BNXT_FLAG_CHIP_P5)
270 BNXT_DB_NQ_ARM_P5(db, idx);
271 else
272 BNXT_DB_CQ_ARM(db, idx);
273}
274
275static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
276{
277 if (bp->flags & BNXT_FLAG_CHIP_P5)
278 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx),
279 db->doorbell);
280 else
281 BNXT_DB_CQ(db, idx);
282}
283
38413406 284const u16 bnxt_lhint_arr[] = {
c0c050c5
MC		 285 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
286 TX_BD_FLAGS_LHINT_512_TO_1023,
287 TX_BD_FLAGS_LHINT_1024_TO_2047,
288 TX_BD_FLAGS_LHINT_1024_TO_2047,
289 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
290 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
291 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
292 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
293 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
294 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
295 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
296 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
297 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
298 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
299 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
300 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
301 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
302 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
303 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
304};
305
ee5c7fb3
SP		 306static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
307{
308 struct metadata_dst *md_dst = skb_metadata_dst(skb);
309
310 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
311 return 0;
312
313 return md_dst->u.port_info.port_id;
314}
315
c0c050c5
MC		 316static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
317{
318 struct bnxt *bp = netdev_priv(dev);
319 struct tx_bd *txbd;
320 struct tx_bd_ext *txbd1;
321 struct netdev_queue *txq;
322 int i;
323 dma_addr_t mapping;
324 unsigned int length, pad = 0;
325 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
326 u16 prod, last_frag;
327 struct pci_dev *pdev = bp->pdev;
c0c050c5
MC		 328 struct bnxt_tx_ring_info *txr;
329 struct bnxt_sw_tx_bd *tx_buf;
330
331 i = skb_get_queue_mapping(skb);
332 if (unlikely(i >= bp->tx_nr_rings)) {
333 dev_kfree_skb_any(skb);
334 return NETDEV_TX_OK;
335 }
336
c0c050c5 337 txq = netdev_get_tx_queue(dev, i);
a960dec9 338 txr = &bp->tx_ring[bp->tx_ring_map[i]];
c0c050c5
MC		 339 prod = txr->tx_prod;
340
341 free_size = bnxt_tx_avail(bp, txr);
342 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
343 netif_tx_stop_queue(txq);
344 return NETDEV_TX_BUSY;
345 }
346
347 length = skb->len;
348 len = skb_headlen(skb);
349 last_frag = skb_shinfo(skb)->nr_frags;
350
351 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
352
353 txbd->tx_bd_opaque = prod;
354
355 tx_buf = &txr->tx_buf_ring[prod];
356 tx_buf->skb = skb;
357 tx_buf->nr_frags = last_frag;
358
359 vlan_tag_flags = 0;
ee5c7fb3 360 cfa_action = bnxt_xmit_get_cfa_action(skb);
c0c050c5
MC		 361 if (skb_vlan_tag_present(skb)) {
362 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
363 skb_vlan_tag_get(skb);
364 /* Currently supports 8021Q, 8021AD vlan offloads
365 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
366 */
367 if (skb->vlan_proto == htons(ETH_P_8021Q))
368 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
369 }
370
371 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
4419dbe6
MC		 372 struct tx_push_buffer *tx_push_buf = txr->tx_push;
373 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
374 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
697197e5 375 void __iomem *db = txr->tx_db.doorbell;
4419dbe6
MC		 376 void *pdata = tx_push_buf->data;
377 u64 *end;
378 int j, push_len;
c0c050c5
MC		 379
380 /* Set COAL_NOW to be ready quickly for the next push */
381 tx_push->tx_bd_len_flags_type =
382 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
383 TX_BD_TYPE_LONG_TX_BD |
384 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
385 TX_BD_FLAGS_COAL_NOW |
386 TX_BD_FLAGS_PACKET_END |
387 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
388
389 if (skb->ip_summed == CHECKSUM_PARTIAL)
390 tx_push1->tx_bd_hsize_lflags =
391 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
392 else
393 tx_push1->tx_bd_hsize_lflags = 0;
394
395 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
ee5c7fb3
SP		 396 tx_push1->tx_bd_cfa_action =
397 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
c0c050c5 398
fbb0fa8b
MC		 399 end = pdata + length;
400 end = PTR_ALIGN(end, 8) - 1;
4419dbe6
MC		 401 *end = 0;
402
c0c050c5
MC		 403 skb_copy_from_linear_data(skb, pdata, len);
404 pdata += len;
405 for (j = 0; j < last_frag; j++) {
406 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
407 void *fptr;
408
409 fptr = skb_frag_address_safe(frag);
410 if (!fptr)
411 goto normal_tx;
412
413 memcpy(pdata, fptr, skb_frag_size(frag));
414 pdata += skb_frag_size(frag);
415 }
416
4419dbe6
MC		 417 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
418 txbd->tx_bd_haddr = txr->data_mapping;
c0c050c5
MC		 419 prod = NEXT_TX(prod);
420 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
421 memcpy(txbd, tx_push1, sizeof(*txbd));
422 prod = NEXT_TX(prod);
4419dbe6 423 tx_push->doorbell =
c0c050c5
MC		 424 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
425 txr->tx_prod = prod;
426
b9a8460a 427 tx_buf->is_push = 1;
c0c050c5 428 netdev_tx_sent_queue(txq, skb->len);
b9a8460a 429 wmb(); /* Sync is_push and byte queue before pushing data */
c0c050c5 430
4419dbe6
MC		 431 push_len = (length + sizeof(*tx_push) + 7) / 8;
432 if (push_len > 16) {
697197e5
MC		 433 __iowrite64_copy(db, tx_push_buf, 16);
434 __iowrite32_copy(db + 4, tx_push_buf + 1,
9d13744b 435 (push_len - 16) << 1);
4419dbe6 436 } else {
697197e5 437 __iowrite64_copy(db, tx_push_buf, push_len);
4419dbe6 438 }
c0c050c5 439
c0c050c5
MC		 440 goto tx_done;
441 }
442
443normal_tx:
444 if (length < BNXT_MIN_PKT_SIZE) {
445 pad = BNXT_MIN_PKT_SIZE - length;
446 if (skb_pad(skb, pad)) {
447 /* SKB already freed. */
448 tx_buf->skb = NULL;
449 return NETDEV_TX_OK;
450 }
451 length = BNXT_MIN_PKT_SIZE;
452 }
453
454 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
455
456 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
457 dev_kfree_skb_any(skb);
458 tx_buf->skb = NULL;
459 return NETDEV_TX_OK;
460 }
461
462 dma_unmap_addr_set(tx_buf, mapping, mapping);
463 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
464 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
465
466 txbd->tx_bd_haddr = cpu_to_le64(mapping);
467
468 prod = NEXT_TX(prod);
469 txbd1 = (struct tx_bd_ext *)
470 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
471
472 txbd1->tx_bd_hsize_lflags = 0;
473 if (skb_is_gso(skb)) {
474 u32 hdr_len;
475
476 if (skb->encapsulation)
477 hdr_len = skb_inner_network_offset(skb) +
478 skb_inner_network_header_len(skb) +
479 inner_tcp_hdrlen(skb);
480 else
481 hdr_len = skb_transport_offset(skb) +
482 tcp_hdrlen(skb);
483
484 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
485 TX_BD_FLAGS_T_IPID |
486 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
487 length = skb_shinfo(skb)->gso_size;
488 txbd1->tx_bd_mss = cpu_to_le32(length);
489 length += hdr_len;
490 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
491 txbd1->tx_bd_hsize_lflags =
492 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
493 txbd1->tx_bd_mss = 0;
494 }
495
496 length >>= 9;
497 flags |= bnxt_lhint_arr[length];
498 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
499
500 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
ee5c7fb3
SP		 501 txbd1->tx_bd_cfa_action =
502 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
c0c050c5
MC		 503 for (i = 0; i < last_frag; i++) {
504 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
505
506 prod = NEXT_TX(prod);
507 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
508
509 len = skb_frag_size(frag);
510 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
511 DMA_TO_DEVICE);
512
513 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
514 goto tx_dma_error;
515
516 tx_buf = &txr->tx_buf_ring[prod];
517 dma_unmap_addr_set(tx_buf, mapping, mapping);
518
519 txbd->tx_bd_haddr = cpu_to_le64(mapping);
520
521 flags = len << TX_BD_LEN_SHIFT;
522 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
523 }
524
525 flags &= ~TX_BD_LEN;
526 txbd->tx_bd_len_flags_type =
527 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
528 TX_BD_FLAGS_PACKET_END);
529
530 netdev_tx_sent_queue(txq, skb->len);
531
532 /* Sync BD data before updating doorbell */
533 wmb();
534
535 prod = NEXT_TX(prod);
536 txr->tx_prod = prod;
537
ffe40645 538 if (!skb->xmit_more || netif_xmit_stopped(txq))
697197e5 539 bnxt_db_write(bp, &txr->tx_db, prod);
c0c050c5
MC		 540
541tx_done:
542
543 mmiowb();
544
545 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
4d172f21 546 if (skb->xmit_more && !tx_buf->is_push)
697197e5 547 bnxt_db_write(bp, &txr->tx_db, prod);
4d172f21 548
c0c050c5
MC		 549 netif_tx_stop_queue(txq);
550
551 /* netif_tx_stop_queue() must be done before checking
552 * tx index in bnxt_tx_avail() below, because in
553 * bnxt_tx_int(), we update tx index before checking for
554 * netif_tx_queue_stopped().
555 */
556 smp_mb();
557 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
558 netif_tx_wake_queue(txq);
559 }
560 return NETDEV_TX_OK;
561
562tx_dma_error:
563 last_frag = i;
564
565 /* start back at beginning and unmap skb */
566 prod = txr->tx_prod;
567 tx_buf = &txr->tx_buf_ring[prod];
568 tx_buf->skb = NULL;
569 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
570 skb_headlen(skb), PCI_DMA_TODEVICE);
571 prod = NEXT_TX(prod);
572
573 /* unmap remaining mapped pages */
574 for (i = 0; i < last_frag; i++) {
575 prod = NEXT_TX(prod);
576 tx_buf = &txr->tx_buf_ring[prod];
577 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
578 skb_frag_size(&skb_shinfo(skb)->frags[i]),
579 PCI_DMA_TODEVICE);
580 }
581
582 dev_kfree_skb_any(skb);
583 return NETDEV_TX_OK;
584}
585
586static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
587{
b6ab4b01 588 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
a960dec9 589 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
c0c050c5
MC		 590 u16 cons = txr->tx_cons;
591 struct pci_dev *pdev = bp->pdev;
592 int i;
593 unsigned int tx_bytes = 0;
594
595 for (i = 0; i < nr_pkts; i++) {
596 struct bnxt_sw_tx_bd *tx_buf;
597 struct sk_buff *skb;
598 int j, last;
599
600 tx_buf = &txr->tx_buf_ring[cons];
601 cons = NEXT_TX(cons);
602 skb = tx_buf->skb;
603 tx_buf->skb = NULL;
604
605 if (tx_buf->is_push) {
606 tx_buf->is_push = 0;
607 goto next_tx_int;
608 }
609
610 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
611 skb_headlen(skb), PCI_DMA_TODEVICE);
612 last = tx_buf->nr_frags;
613
614 for (j = 0; j < last; j++) {
615 cons = NEXT_TX(cons);
616 tx_buf = &txr->tx_buf_ring[cons];
617 dma_unmap_page(
618 &pdev->dev,
619 dma_unmap_addr(tx_buf, mapping),
620 skb_frag_size(&skb_shinfo(skb)->frags[j]),
621 PCI_DMA_TODEVICE);
622 }
623
624next_tx_int:
625 cons = NEXT_TX(cons);
626
627 tx_bytes += skb->len;
628 dev_kfree_skb_any(skb);
629 }
630
631 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
632 txr->tx_cons = cons;
633
634 /* Need to make the tx_cons update visible to bnxt_start_xmit()
635 * before checking for netif_tx_queue_stopped(). Without the
636 * memory barrier, there is a small possibility that bnxt_start_xmit()
637 * will miss it and cause the queue to be stopped forever.
638 */
639 smp_mb();
640
641 if (unlikely(netif_tx_queue_stopped(txq)) &&
642 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
643 __netif_tx_lock(txq, smp_processor_id());
644 if (netif_tx_queue_stopped(txq) &&
645 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
646 txr->dev_state != BNXT_DEV_STATE_CLOSING)
647 netif_tx_wake_queue(txq);
648 __netif_tx_unlock(txq);
649 }
650}
651
c61fb99c
MC		 652static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
653 gfp_t gfp)
654{
655 struct device *dev = &bp->pdev->dev;
656 struct page *page;
657
658 page = alloc_page(gfp);
659 if (!page)
660 return NULL;
661
c519fe9a
SN		 662 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
663 DMA_ATTR_WEAK_ORDERING);
c61fb99c
MC		 664 if (dma_mapping_error(dev, *mapping)) {
665 __free_page(page);
666 return NULL;
667 }
668 *mapping += bp->rx_dma_offset;
669 return page;
670}
671
c0c050c5
MC		 672static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
673 gfp_t gfp)
674{
675 u8 *data;
676 struct pci_dev *pdev = bp->pdev;
677
678 data = kmalloc(bp->rx_buf_size, gfp);
679 if (!data)
680 return NULL;
681
c519fe9a
SN		 682 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
683 bp->rx_buf_use_size, bp->rx_dir,
684 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 685
686 if (dma_mapping_error(&pdev->dev, *mapping)) {
687 kfree(data);
688 data = NULL;
689 }
690 return data;
691}
692
38413406
MC		 693int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
694 u16 prod, gfp_t gfp)
c0c050c5
MC		 695{
696 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
697 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
c0c050c5
MC		 698 dma_addr_t mapping;
699
c61fb99c
MC		 700 if (BNXT_RX_PAGE_MODE(bp)) {
701 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
c0c050c5 702
c61fb99c
MC		 703 if (!page)
704 return -ENOMEM;
705
706 rx_buf->data = page;
707 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
708 } else {
709 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
710
711 if (!data)
712 return -ENOMEM;
713
714 rx_buf->data = data;
715 rx_buf->data_ptr = data + bp->rx_offset;
716 }
11cd119d 717 rx_buf->mapping = mapping;
c0c050c5
MC		 718
719 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
c0c050c5
MC		 720 return 0;
721}
722
c6d30e83 723void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
c0c050c5
MC		 724{
725 u16 prod = rxr->rx_prod;
726 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
727 struct rx_bd *cons_bd, *prod_bd;
728
729 prod_rx_buf = &rxr->rx_buf_ring[prod];
730 cons_rx_buf = &rxr->rx_buf_ring[cons];
731
732 prod_rx_buf->data = data;
6bb19474 733 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
c0c050c5 734
11cd119d 735 prod_rx_buf->mapping = cons_rx_buf->mapping;
c0c050c5
MC		 736
737 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
738 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
739
740 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
741}
742
743static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
744{
745 u16 next, max = rxr->rx_agg_bmap_size;
746
747 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
748 if (next >= max)
749 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
750 return next;
751}
752
753static inline int bnxt_alloc_rx_page(struct bnxt *bp,
754 struct bnxt_rx_ring_info *rxr,
755 u16 prod, gfp_t gfp)
756{
757 struct rx_bd *rxbd =
758 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
759 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
760 struct pci_dev *pdev = bp->pdev;
761 struct page *page;
762 dma_addr_t mapping;
763 u16 sw_prod = rxr->rx_sw_agg_prod;
89d0a06c 764 unsigned int offset = 0;
c0c050c5 765
89d0a06c
MC		 766 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
767 page = rxr->rx_page;
768 if (!page) {
769 page = alloc_page(gfp);
770 if (!page)
771 return -ENOMEM;
772 rxr->rx_page = page;
773 rxr->rx_page_offset = 0;
774 }
775 offset = rxr->rx_page_offset;
776 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
777 if (rxr->rx_page_offset == PAGE_SIZE)
778 rxr->rx_page = NULL;
779 else
780 get_page(page);
781 } else {
782 page = alloc_page(gfp);
783 if (!page)
784 return -ENOMEM;
785 }
c0c050c5 786
c519fe9a
SN		 787 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
788 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
789 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 790 if (dma_mapping_error(&pdev->dev, mapping)) {
791 __free_page(page);
792 return -EIO;
793 }
794
795 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
796 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
797
798 __set_bit(sw_prod, rxr->rx_agg_bmap);
799 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
800 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
801
802 rx_agg_buf->page = page;
89d0a06c 803 rx_agg_buf->offset = offset;
c0c050c5
MC		 804 rx_agg_buf->mapping = mapping;
805 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
806 rxbd->rx_bd_opaque = sw_prod;
807 return 0;
808}
809
e44758b7 810static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
c0c050c5
MC		 811 u32 agg_bufs)
812{
e44758b7 813 struct bnxt_napi *bnapi = cpr->bnapi;
c0c050c5 814 struct bnxt *bp = bnapi->bp;
b6ab4b01 815 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 816 u16 prod = rxr->rx_agg_prod;
817 u16 sw_prod = rxr->rx_sw_agg_prod;
818 u32 i;
819
820 for (i = 0; i < agg_bufs; i++) {
821 u16 cons;
822 struct rx_agg_cmp *agg;
823 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
824 struct rx_bd *prod_bd;
825 struct page *page;
826
827 agg = (struct rx_agg_cmp *)
828 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
829 cons = agg->rx_agg_cmp_opaque;
830 __clear_bit(cons, rxr->rx_agg_bmap);
831
832 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
833 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
834
835 __set_bit(sw_prod, rxr->rx_agg_bmap);
836 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
837 cons_rx_buf = &rxr->rx_agg_ring[cons];
838
839 /* It is possible for sw_prod to be equal to cons, so
840 * set cons_rx_buf->page to NULL first.
841 */
842 page = cons_rx_buf->page;
843 cons_rx_buf->page = NULL;
844 prod_rx_buf->page = page;
89d0a06c 845 prod_rx_buf->offset = cons_rx_buf->offset;
c0c050c5
MC		 846
847 prod_rx_buf->mapping = cons_rx_buf->mapping;
848
849 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
850
851 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
852 prod_bd->rx_bd_opaque = sw_prod;
853
854 prod = NEXT_RX_AGG(prod);
855 sw_prod = NEXT_RX_AGG(sw_prod);
856 cp_cons = NEXT_CMP(cp_cons);
857 }
858 rxr->rx_agg_prod = prod;
859 rxr->rx_sw_agg_prod = sw_prod;
860}
861
c61fb99c
MC		 862static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
863 struct bnxt_rx_ring_info *rxr,
864 u16 cons, void *data, u8 *data_ptr,
865 dma_addr_t dma_addr,
866 unsigned int offset_and_len)
867{
868 unsigned int payload = offset_and_len >> 16;
869 unsigned int len = offset_and_len & 0xffff;
870 struct skb_frag_struct *frag;
871 struct page *page = data;
872 u16 prod = rxr->rx_prod;
873 struct sk_buff *skb;
874 int off, err;
875
876 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
877 if (unlikely(err)) {
878 bnxt_reuse_rx_data(rxr, cons, data);
879 return NULL;
880 }
881 dma_addr -= bp->rx_dma_offset;
c519fe9a
SN		 882 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
883 DMA_ATTR_WEAK_ORDERING);
c61fb99c
MC		 884
885 if (unlikely(!payload))
886 payload = eth_get_headlen(data_ptr, len);
887
888 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
889 if (!skb) {
890 __free_page(page);
891 return NULL;
892 }
893
894 off = (void *)data_ptr - page_address(page);
895 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
896 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
897 payload + NET_IP_ALIGN);
898
899 frag = &skb_shinfo(skb)->frags[0];
900 skb_frag_size_sub(frag, payload);
901 frag->page_offset += payload;
902 skb->data_len -= payload;
903 skb->tail += payload;
904
905 return skb;
906}
907
c0c050c5
MC		 908static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
909 struct bnxt_rx_ring_info *rxr, u16 cons,
6bb19474
MC		 910 void *data, u8 *data_ptr,
911 dma_addr_t dma_addr,
912 unsigned int offset_and_len)
c0c050c5 913{
6bb19474 914 u16 prod = rxr->rx_prod;
c0c050c5 915 struct sk_buff *skb;
6bb19474 916 int err;
c0c050c5
MC		 917
918 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
919 if (unlikely(err)) {
920 bnxt_reuse_rx_data(rxr, cons, data);
921 return NULL;
922 }
923
924 skb = build_skb(data, 0);
c519fe9a
SN		 925 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
926 bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 927 if (!skb) {
928 kfree(data);
929 return NULL;
930 }
931
b3dba77c 932 skb_reserve(skb, bp->rx_offset);
6bb19474 933 skb_put(skb, offset_and_len & 0xffff);
c0c050c5
MC		 934 return skb;
935}
936
e44758b7
MC		 937static struct sk_buff *bnxt_rx_pages(struct bnxt *bp,
938 struct bnxt_cp_ring_info *cpr,
c0c050c5
MC		 939 struct sk_buff *skb, u16 cp_cons,
940 u32 agg_bufs)
941{
e44758b7 942 struct bnxt_napi *bnapi = cpr->bnapi;
c0c050c5 943 struct pci_dev *pdev = bp->pdev;
b6ab4b01 944 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 945 u16 prod = rxr->rx_agg_prod;
946 u32 i;
947
948 for (i = 0; i < agg_bufs; i++) {
949 u16 cons, frag_len;
950 struct rx_agg_cmp *agg;
951 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
952 struct page *page;
953 dma_addr_t mapping;
954
955 agg = (struct rx_agg_cmp *)
956 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
957 cons = agg->rx_agg_cmp_opaque;
958 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
959 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
960
961 cons_rx_buf = &rxr->rx_agg_ring[cons];
89d0a06c
MC		 962 skb_fill_page_desc(skb, i, cons_rx_buf->page,
963 cons_rx_buf->offset, frag_len);
c0c050c5
MC		 964 __clear_bit(cons, rxr->rx_agg_bmap);
965
966 /* It is possible for bnxt_alloc_rx_page() to allocate
967 * a sw_prod index that equals the cons index, so we
968 * need to clear the cons entry now.
969 */
11cd119d 970 mapping = cons_rx_buf->mapping;
c0c050c5
MC		 971 page = cons_rx_buf->page;
972 cons_rx_buf->page = NULL;
973
974 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
975 struct skb_shared_info *shinfo;
976 unsigned int nr_frags;
977
978 shinfo = skb_shinfo(skb);
979 nr_frags = --shinfo->nr_frags;
980 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
981
982 dev_kfree_skb(skb);
983
984 cons_rx_buf->page = page;
985
986 /* Update prod since possibly some pages have been
987 * allocated already.
988 */
989 rxr->rx_agg_prod = prod;
e44758b7 990 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs - i);
c0c050c5
MC		 991 return NULL;
992 }
993
c519fe9a
SN		 994 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
995 PCI_DMA_FROMDEVICE,
996 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 997
998 skb->data_len += frag_len;
999 skb->len += frag_len;
1000 skb->truesize += PAGE_SIZE;
1001
1002 prod = NEXT_RX_AGG(prod);
1003 cp_cons = NEXT_CMP(cp_cons);
1004 }
1005 rxr->rx_agg_prod = prod;
1006 return skb;
1007}
1008
1009static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1010 u8 agg_bufs, u32 *raw_cons)
1011{
1012 u16 last;
1013 struct rx_agg_cmp *agg;
1014
1015 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
1016 last = RING_CMP(*raw_cons);
1017 agg = (struct rx_agg_cmp *)
1018 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1019 return RX_AGG_CMP_VALID(agg, *raw_cons);
1020}
1021
1022static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1023 unsigned int len,
1024 dma_addr_t mapping)
1025{
1026 struct bnxt *bp = bnapi->bp;
1027 struct pci_dev *pdev = bp->pdev;
1028 struct sk_buff *skb;
1029
1030 skb = napi_alloc_skb(&bnapi->napi, len);
1031 if (!skb)
1032 return NULL;
1033
745fc05c
MC		 1034 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1035 bp->rx_dir);
c0c050c5 1036
6bb19474
MC		 1037 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1038 len + NET_IP_ALIGN);
c0c050c5 1039
745fc05c
MC		 1040 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1041 bp->rx_dir);
c0c050c5
MC		 1042
1043 skb_put(skb, len);
1044 return skb;
1045}
1046
e44758b7 1047static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
fa7e2812
MC		 1048 u32 *raw_cons, void *cmp)
1049{
fa7e2812
MC		 1050 struct rx_cmp *rxcmp = cmp;
1051 u32 tmp_raw_cons = *raw_cons;
1052 u8 cmp_type, agg_bufs = 0;
1053
1054 cmp_type = RX_CMP_TYPE(rxcmp);
1055
1056 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1057 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1058 RX_CMP_AGG_BUFS) >>
1059 RX_CMP_AGG_BUFS_SHIFT;
1060 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1061 struct rx_tpa_end_cmp *tpa_end = cmp;
1062
1063 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1064 RX_TPA_END_CMP_AGG_BUFS) >>
1065 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1066 }
1067
1068 if (agg_bufs) {
1069 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1070 return -EBUSY;
1071 }
1072 *raw_cons = tmp_raw_cons;
1073 return 0;
1074}
1075
c213eae8
MC		 1076static void bnxt_queue_sp_work(struct bnxt *bp)
1077{
1078 if (BNXT_PF(bp))
1079 queue_work(bnxt_pf_wq, &bp->sp_task);
1080 else
1081 schedule_work(&bp->sp_task);
1082}
1083
1084static void bnxt_cancel_sp_work(struct bnxt *bp)
1085{
1086 if (BNXT_PF(bp))
1087 flush_workqueue(bnxt_pf_wq);
1088 else
1089 cancel_work_sync(&bp->sp_task);
1090}
1091
fa7e2812
MC		 1092static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1093{
1094 if (!rxr->bnapi->in_reset) {
1095 rxr->bnapi->in_reset = true;
1096 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
c213eae8 1097 bnxt_queue_sp_work(bp);
fa7e2812
MC		 1098 }
1099 rxr->rx_next_cons = 0xffff;
1100}
1101
c0c050c5
MC		 1102static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1103 struct rx_tpa_start_cmp *tpa_start,
1104 struct rx_tpa_start_cmp_ext *tpa_start1)
1105{
1106 u8 agg_id = TPA_START_AGG_ID(tpa_start);
1107 u16 cons, prod;
1108 struct bnxt_tpa_info *tpa_info;
1109 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1110 struct rx_bd *prod_bd;
1111 dma_addr_t mapping;
1112
1113 cons = tpa_start->rx_tpa_start_cmp_opaque;
1114 prod = rxr->rx_prod;
1115 cons_rx_buf = &rxr->rx_buf_ring[cons];
1116 prod_rx_buf = &rxr->rx_buf_ring[prod];
1117 tpa_info = &rxr->rx_tpa[agg_id];
1118
fa7e2812
MC		 1119 if (unlikely(cons != rxr->rx_next_cons)) {
1120 bnxt_sched_reset(bp, rxr);
1121 return;
1122 }
ee5c7fb3
SP		 1123 /* Store cfa_code in tpa_info to use in tpa_end
1124 * completion processing.
1125 */
1126 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
c0c050c5 1127 prod_rx_buf->data = tpa_info->data;
6bb19474 1128 prod_rx_buf->data_ptr = tpa_info->data_ptr;
c0c050c5
MC		 1129
1130 mapping = tpa_info->mapping;
11cd119d 1131 prod_rx_buf->mapping = mapping;
c0c050c5
MC		 1132
1133 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1134
1135 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1136
1137 tpa_info->data = cons_rx_buf->data;
6bb19474 1138 tpa_info->data_ptr = cons_rx_buf->data_ptr;
c0c050c5 1139 cons_rx_buf->data = NULL;
11cd119d 1140 tpa_info->mapping = cons_rx_buf->mapping;
c0c050c5
MC		 1141
1142 tpa_info->len =
1143 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1144 RX_TPA_START_CMP_LEN_SHIFT;
1145 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1146 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1147
1148 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1149 tpa_info->gso_type = SKB_GSO_TCPV4;
1150 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
50f011b6 1151 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
c0c050c5
MC		 1152 tpa_info->gso_type = SKB_GSO_TCPV6;
1153 tpa_info->rss_hash =
1154 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1155 } else {
1156 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1157 tpa_info->gso_type = 0;
1158 if (netif_msg_rx_err(bp))
1159 netdev_warn(bp->dev, "TPA packet without valid hash\n");
1160 }
1161 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1162 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
94758f8d 1163 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
c0c050c5
MC		 1164
1165 rxr->rx_prod = NEXT_RX(prod);
1166 cons = NEXT_RX(cons);
376a5b86 1167 rxr->rx_next_cons = NEXT_RX(cons);
c0c050c5
MC		 1168 cons_rx_buf = &rxr->rx_buf_ring[cons];
1169
1170 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1171 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1172 cons_rx_buf->data = NULL;
1173}
1174
e44758b7
MC		 1175static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
1176 u32 agg_bufs)
c0c050c5
MC		 1177{
1178 if (agg_bufs)
e44758b7 1179 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
c0c050c5
MC		 1180}
1181
94758f8d
MC		 1182static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1183 int payload_off, int tcp_ts,
1184 struct sk_buff *skb)
1185{
1186#ifdef CONFIG_INET
1187 struct tcphdr *th;
1188 int len, nw_off;
1189 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1190 u32 hdr_info = tpa_info->hdr_info;
1191 bool loopback = false;
1192
1193 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1194 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1195 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1196
1197 /* If the packet is an internal loopback packet, the offsets will
1198 * have an extra 4 bytes.
1199 */
1200 if (inner_mac_off == 4) {
1201 loopback = true;
1202 } else if (inner_mac_off > 4) {
1203 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1204 ETH_HLEN - 2));
1205
1206 /* We only support inner iPv4/ipv6. If we don't see the
1207 * correct protocol ID, it must be a loopback packet where
1208 * the offsets are off by 4.
1209 */
09a7636a 1210 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
94758f8d
MC		 1211 loopback = true;
1212 }
1213 if (loopback) {
1214 /* internal loopback packet, subtract all offsets by 4 */
1215 inner_ip_off -= 4;
1216 inner_mac_off -= 4;
1217 outer_ip_off -= 4;
1218 }
1219
1220 nw_off = inner_ip_off - ETH_HLEN;
1221 skb_set_network_header(skb, nw_off);
1222 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1223 struct ipv6hdr *iph = ipv6_hdr(skb);
1224
1225 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1226 len = skb->len - skb_transport_offset(skb);
1227 th = tcp_hdr(skb);
1228 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1229 } else {
1230 struct iphdr *iph = ip_hdr(skb);
1231
1232 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1233 len = skb->len - skb_transport_offset(skb);
1234 th = tcp_hdr(skb);
1235 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1236 }
1237
1238 if (inner_mac_off) { /* tunnel */
1239 struct udphdr *uh = NULL;
1240 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1241 ETH_HLEN - 2));
1242
1243 if (proto == htons(ETH_P_IP)) {
1244 struct iphdr *iph = (struct iphdr *)skb->data;
1245
1246 if (iph->protocol == IPPROTO_UDP)
1247 uh = (struct udphdr *)(iph + 1);
1248 } else {
1249 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1250
1251 if (iph->nexthdr == IPPROTO_UDP)
1252 uh = (struct udphdr *)(iph + 1);
1253 }
1254 if (uh) {
1255 if (uh->check)
1256 skb_shinfo(skb)->gso_type |=
1257 SKB_GSO_UDP_TUNNEL_CSUM;
1258 else
1259 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1260 }
1261 }
1262#endif
1263 return skb;
1264}
1265
c0c050c5
MC		 1266#define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1267#define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1268
309369c9
MC		 1269static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1270 int payload_off, int tcp_ts,
c0c050c5
MC		 1271 struct sk_buff *skb)
1272{
d1611c3a 1273#ifdef CONFIG_INET
c0c050c5 1274 struct tcphdr *th;
719ca811 1275 int len, nw_off, tcp_opt_len = 0;
27e24189 1276
309369c9 1277 if (tcp_ts)
c0c050c5
MC		 1278 tcp_opt_len = 12;
1279
c0c050c5
MC		 1280 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1281 struct iphdr *iph;
1282
1283 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1284 ETH_HLEN;
1285 skb_set_network_header(skb, nw_off);
1286 iph = ip_hdr(skb);
1287 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1288 len = skb->len - skb_transport_offset(skb);
1289 th = tcp_hdr(skb);
1290 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1291 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1292 struct ipv6hdr *iph;
1293
1294 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1295 ETH_HLEN;
1296 skb_set_network_header(skb, nw_off);
1297 iph = ipv6_hdr(skb);
1298 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1299 len = skb->len - skb_transport_offset(skb);
1300 th = tcp_hdr(skb);
1301 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1302 } else {
1303 dev_kfree_skb_any(skb);
1304 return NULL;
1305 }
c0c050c5
MC		 1306
1307 if (nw_off) { /* tunnel */
1308 struct udphdr *uh = NULL;
1309
1310 if (skb->protocol == htons(ETH_P_IP)) {
1311 struct iphdr *iph = (struct iphdr *)skb->data;
1312
1313 if (iph->protocol == IPPROTO_UDP)
1314 uh = (struct udphdr *)(iph + 1);
1315 } else {
1316 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1317
1318 if (iph->nexthdr == IPPROTO_UDP)
1319 uh = (struct udphdr *)(iph + 1);
1320 }
1321 if (uh) {
1322 if (uh->check)
1323 skb_shinfo(skb)->gso_type |=
1324 SKB_GSO_UDP_TUNNEL_CSUM;
1325 else
1326 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1327 }
1328 }
1329#endif
1330 return skb;
1331}
1332
309369c9
MC		 1333static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1334 struct bnxt_tpa_info *tpa_info,
1335 struct rx_tpa_end_cmp *tpa_end,
1336 struct rx_tpa_end_cmp_ext *tpa_end1,
1337 struct sk_buff *skb)
1338{
1339#ifdef CONFIG_INET
1340 int payload_off;
1341 u16 segs;
1342
1343 segs = TPA_END_TPA_SEGS(tpa_end);
1344 if (segs == 1)
1345 return skb;
1346
1347 NAPI_GRO_CB(skb)->count = segs;
1348 skb_shinfo(skb)->gso_size =
1349 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1350 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1351 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1352 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1353 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1354 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
5910906c
MC		 1355 if (likely(skb))
1356 tcp_gro_complete(skb);
309369c9
MC		 1357#endif
1358 return skb;
1359}
1360
ee5c7fb3
SP		 1361/* Given the cfa_code of a received packet determine which
1362 * netdev (vf-rep or PF) the packet is destined to.
1363 */
1364static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1365{
1366 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1367
1368 /* if vf-rep dev is NULL, the must belongs to the PF */
1369 return dev ? dev : bp->dev;
1370}
1371
c0c050c5 1372static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
e44758b7 1373 struct bnxt_cp_ring_info *cpr,
c0c050c5
MC		 1374 u32 *raw_cons,
1375 struct rx_tpa_end_cmp *tpa_end,
1376 struct rx_tpa_end_cmp_ext *tpa_end1,
4e5dbbda 1377 u8 *event)
c0c050c5 1378{
e44758b7 1379 struct bnxt_napi *bnapi = cpr->bnapi;
b6ab4b01 1380 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5 1381 u8 agg_id = TPA_END_AGG_ID(tpa_end);
6bb19474 1382 u8 *data_ptr, agg_bufs;
c0c050c5
MC		 1383 u16 cp_cons = RING_CMP(*raw_cons);
1384 unsigned int len;
1385 struct bnxt_tpa_info *tpa_info;
1386 dma_addr_t mapping;
1387 struct sk_buff *skb;
6bb19474 1388 void *data;
c0c050c5 1389
fa7e2812 1390 if (unlikely(bnapi->in_reset)) {
e44758b7 1391 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
fa7e2812
MC		 1392
1393 if (rc < 0)
1394 return ERR_PTR(-EBUSY);
1395 return NULL;
1396 }
1397
c0c050c5
MC		 1398 tpa_info = &rxr->rx_tpa[agg_id];
1399 data = tpa_info->data;
6bb19474
MC		 1400 data_ptr = tpa_info->data_ptr;
1401 prefetch(data_ptr);
c0c050c5
MC		 1402 len = tpa_info->len;
1403 mapping = tpa_info->mapping;
1404
1405 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1406 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1407
1408 if (agg_bufs) {
1409 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1410 return ERR_PTR(-EBUSY);
1411
4e5dbbda 1412 *event |= BNXT_AGG_EVENT;
c0c050c5
MC		 1413 cp_cons = NEXT_CMP(cp_cons);
1414 }
1415
69c149e2 1416 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
e44758b7 1417 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
69c149e2
MC		 1418 if (agg_bufs > MAX_SKB_FRAGS)
1419 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1420 agg_bufs, (int)MAX_SKB_FRAGS);
c0c050c5
MC		 1421 return NULL;
1422 }
1423
1424 if (len <= bp->rx_copy_thresh) {
6bb19474 1425 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
c0c050c5 1426 if (!skb) {
e44758b7 1427 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
c0c050c5
MC		 1428 return NULL;
1429 }
1430 } else {
1431 u8 *new_data;
1432 dma_addr_t new_mapping;
1433
1434 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1435 if (!new_data) {
e44758b7 1436 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
c0c050c5
MC		 1437 return NULL;
1438 }
1439
1440 tpa_info->data = new_data;
b3dba77c 1441 tpa_info->data_ptr = new_data + bp->rx_offset;
c0c050c5
MC		 1442 tpa_info->mapping = new_mapping;
1443
1444 skb = build_skb(data, 0);
c519fe9a
SN		 1445 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1446 bp->rx_buf_use_size, bp->rx_dir,
1447 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 1448
1449 if (!skb) {
1450 kfree(data);
e44758b7 1451 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
c0c050c5
MC		 1452 return NULL;
1453 }
b3dba77c 1454 skb_reserve(skb, bp->rx_offset);
c0c050c5
MC		 1455 skb_put(skb, len);
1456 }
1457
1458 if (agg_bufs) {
e44758b7 1459 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
c0c050c5
MC		 1460 if (!skb) {
1461 /* Page reuse already handled by bnxt_rx_pages(). */
1462 return NULL;
1463 }
1464 }
ee5c7fb3
SP		 1465
1466 skb->protocol =
1467 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
c0c050c5
MC		 1468
1469 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1470 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1471
8852ddb4
MC		 1472 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1473 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
c0c050c5
MC		 1474 u16 vlan_proto = tpa_info->metadata >>
1475 RX_CMP_FLAGS2_METADATA_TPID_SFT;
ed7bc602 1476 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
c0c050c5 1477
8852ddb4 1478 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
c0c050c5
MC		 1479 }
1480
1481 skb_checksum_none_assert(skb);
1482 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1483 skb->ip_summed = CHECKSUM_UNNECESSARY;
1484 skb->csum_level =
1485 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1486 }
1487
1488 if (TPA_END_GRO(tpa_end))
309369c9 1489 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
c0c050c5
MC		 1490
1491 return skb;
1492}
1493
ee5c7fb3
SP		 1494static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1495 struct sk_buff *skb)
1496{
1497 if (skb->dev != bp->dev) {
1498 /* this packet belongs to a vf-rep */
1499 bnxt_vf_rep_rx(bp, skb);
1500 return;
1501 }
1502 skb_record_rx_queue(skb, bnapi->index);
1503 napi_gro_receive(&bnapi->napi, skb);
1504}
1505
c0c050c5
MC		 1506/* returns the following:
1507 * 1 - 1 packet successfully received
1508 * 0 - successful TPA_START, packet not completed yet
1509 * -EBUSY - completion ring does not have all the agg buffers yet
1510 * -ENOMEM - packet aborted due to out of memory
1511 * -EIO - packet aborted due to hw error indicated in BD
1512 */
e44758b7
MC		 1513static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1514 u32 *raw_cons, u8 *event)
c0c050c5 1515{
e44758b7 1516 struct bnxt_napi *bnapi = cpr->bnapi;
b6ab4b01 1517 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1518 struct net_device *dev = bp->dev;
1519 struct rx_cmp *rxcmp;
1520 struct rx_cmp_ext *rxcmp1;
1521 u32 tmp_raw_cons = *raw_cons;
ee5c7fb3 1522 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
c0c050c5
MC		 1523 struct bnxt_sw_rx_bd *rx_buf;
1524 unsigned int len;
6bb19474 1525 u8 *data_ptr, agg_bufs, cmp_type;
c0c050c5
MC		 1526 dma_addr_t dma_addr;
1527 struct sk_buff *skb;
6bb19474 1528 void *data;
c0c050c5 1529 int rc = 0;
c61fb99c 1530 u32 misc;
c0c050c5
MC		 1531
1532 rxcmp = (struct rx_cmp *)
1533 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1534
1535 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1536 cp_cons = RING_CMP(tmp_raw_cons);
1537 rxcmp1 = (struct rx_cmp_ext *)
1538 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1539
1540 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1541 return -EBUSY;
1542
1543 cmp_type = RX_CMP_TYPE(rxcmp);
1544
1545 prod = rxr->rx_prod;
1546
1547 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1548 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1549 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1550
4e5dbbda 1551 *event |= BNXT_RX_EVENT;
e7e70fa6 1552 goto next_rx_no_prod_no_len;
c0c050c5
MC		 1553
1554 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
e44758b7 1555 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
c0c050c5 1556 (struct rx_tpa_end_cmp *)rxcmp,
4e5dbbda 1557 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
c0c050c5 1558
1fac4b2f 1559 if (IS_ERR(skb))
c0c050c5
MC		 1560 return -EBUSY;
1561
1562 rc = -ENOMEM;
1563 if (likely(skb)) {
ee5c7fb3 1564 bnxt_deliver_skb(bp, bnapi, skb);
c0c050c5
MC		 1565 rc = 1;
1566 }
4e5dbbda 1567 *event |= BNXT_RX_EVENT;
e7e70fa6 1568 goto next_rx_no_prod_no_len;
c0c050c5
MC		 1569 }
1570
1571 cons = rxcmp->rx_cmp_opaque;
1572 rx_buf = &rxr->rx_buf_ring[cons];
1573 data = rx_buf->data;
6bb19474 1574 data_ptr = rx_buf->data_ptr;
fa7e2812 1575 if (unlikely(cons != rxr->rx_next_cons)) {
e44758b7 1576 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp);
fa7e2812
MC		 1577
1578 bnxt_sched_reset(bp, rxr);
1579 return rc1;
1580 }
6bb19474 1581 prefetch(data_ptr);
c0c050c5 1582
c61fb99c
MC		 1583 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1584 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
c0c050c5
MC		 1585
1586 if (agg_bufs) {
1587 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1588 return -EBUSY;
1589
1590 cp_cons = NEXT_CMP(cp_cons);
4e5dbbda 1591 *event |= BNXT_AGG_EVENT;
c0c050c5 1592 }
4e5dbbda 1593 *event |= BNXT_RX_EVENT;
c0c050c5
MC		 1594
1595 rx_buf->data = NULL;
1596 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1597 bnxt_reuse_rx_data(rxr, cons, data);
1598 if (agg_bufs)
e44758b7 1599 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
c0c050c5
MC		 1600
1601 rc = -EIO;
1602 goto next_rx;
1603 }
1604
1605 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
11cd119d 1606 dma_addr = rx_buf->mapping;
c0c050c5 1607
c6d30e83
MC		 1608 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1609 rc = 1;
1610 goto next_rx;
1611 }
1612
c0c050c5 1613 if (len <= bp->rx_copy_thresh) {
6bb19474 1614 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
c0c050c5
MC		 1615 bnxt_reuse_rx_data(rxr, cons, data);
1616 if (!skb) {
1617 rc = -ENOMEM;
1618 goto next_rx;
1619 }
1620 } else {
c61fb99c
MC		 1621 u32 payload;
1622
c6d30e83
MC		 1623 if (rx_buf->data_ptr == data_ptr)
1624 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1625 else
1626 payload = 0;
6bb19474 1627 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
c61fb99c 1628 payload | len);
c0c050c5
MC		 1629 if (!skb) {
1630 rc = -ENOMEM;
1631 goto next_rx;
1632 }
1633 }
1634
1635 if (agg_bufs) {
e44758b7 1636 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
c0c050c5
MC		 1637 if (!skb) {
1638 rc = -ENOMEM;
1639 goto next_rx;
1640 }
1641 }
1642
1643 if (RX_CMP_HASH_VALID(rxcmp)) {
1644 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1645 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1646
1647 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1648 if (hash_type != 1 && hash_type != 3)
1649 type = PKT_HASH_TYPE_L3;
1650 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1651 }
1652
ee5c7fb3
SP		 1653 cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1654 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
c0c050c5 1655
8852ddb4
MC		 1656 if ((rxcmp1->rx_cmp_flags2 &
1657 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1658 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
c0c050c5 1659 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
ed7bc602 1660 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
c0c050c5
MC		 1661 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1662
8852ddb4 1663 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
c0c050c5
MC		 1664 }
1665
1666 skb_checksum_none_assert(skb);
1667 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1668 if (dev->features & NETIF_F_RXCSUM) {
1669 skb->ip_summed = CHECKSUM_UNNECESSARY;
1670 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1671 }
1672 } else {
665e350d
SB		 1673 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1674 if (dev->features & NETIF_F_RXCSUM)
1675 cpr->rx_l4_csum_errors++;
1676 }
c0c050c5
MC		 1677 }
1678
ee5c7fb3 1679 bnxt_deliver_skb(bp, bnapi, skb);
c0c050c5
MC		 1680 rc = 1;
1681
1682next_rx:
1683 rxr->rx_prod = NEXT_RX(prod);
376a5b86 1684 rxr->rx_next_cons = NEXT_RX(cons);
c0c050c5 1685
6a8788f2
AG		 1686 cpr->rx_packets += 1;
1687 cpr->rx_bytes += len;
e7e70fa6
CIK		 1688
1689next_rx_no_prod_no_len:
c0c050c5
MC		 1690 *raw_cons = tmp_raw_cons;
1691
1692 return rc;
1693}
1694
2270bc5d
MC		 1695/* In netpoll mode, if we are using a combined completion ring, we need to
1696 * discard the rx packets and recycle the buffers.
1697 */
e44758b7
MC		 1698static int bnxt_force_rx_discard(struct bnxt *bp,
1699 struct bnxt_cp_ring_info *cpr,
2270bc5d
MC		 1700 u32 *raw_cons, u8 *event)
1701{
2270bc5d
MC		 1702 u32 tmp_raw_cons = *raw_cons;
1703 struct rx_cmp_ext *rxcmp1;
1704 struct rx_cmp *rxcmp;
1705 u16 cp_cons;
1706 u8 cmp_type;
1707
1708 cp_cons = RING_CMP(tmp_raw_cons);
1709 rxcmp = (struct rx_cmp *)
1710 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1711
1712 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1713 cp_cons = RING_CMP(tmp_raw_cons);
1714 rxcmp1 = (struct rx_cmp_ext *)
1715 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1716
1717 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1718 return -EBUSY;
1719
1720 cmp_type = RX_CMP_TYPE(rxcmp);
1721 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1722 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1723 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1724 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1725 struct rx_tpa_end_cmp_ext *tpa_end1;
1726
1727 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1728 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1729 cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1730 }
e44758b7 1731 return bnxt_rx_pkt(bp, cpr, raw_cons, event);
2270bc5d
MC		 1732}
1733
4bb13abf 1734#define BNXT_GET_EVENT_PORT(data) \
87c374de
MC		 1735 ((data) & \
1736 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
4bb13abf 1737
c0c050c5
MC		 1738static int bnxt_async_event_process(struct bnxt *bp,
1739 struct hwrm_async_event_cmpl *cmpl)
1740{
1741 u16 event_id = le16_to_cpu(cmpl->event_id);
1742
1743 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1744 switch (event_id) {
87c374de 1745 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
8cbde117
MC		 1746 u32 data1 = le32_to_cpu(cmpl->event_data1);
1747 struct bnxt_link_info *link_info = &bp->link_info;
1748
1749 if (BNXT_VF(bp))
1750 goto async_event_process_exit;
a8168b6c
MC		 1751
1752 /* print unsupported speed warning in forced speed mode only */
1753 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1754 (data1 & 0x20000)) {
8cbde117
MC		 1755 u16 fw_speed = link_info->force_link_speed;
1756 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1757
a8168b6c
MC		 1758 if (speed != SPEED_UNKNOWN)
1759 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1760 speed);
8cbde117 1761 }
286ef9d6 1762 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
8cbde117 1763 }
bc171e87 1764 /* fall through */
87c374de 1765 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
c0c050c5 1766 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
19241368 1767 break;
87c374de 1768 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
19241368 1769 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
c0c050c5 1770 break;
87c374de 1771 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
4bb13abf
MC		 1772 u32 data1 = le32_to_cpu(cmpl->event_data1);
1773 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1774
1775 if (BNXT_VF(bp))
1776 break;
1777
1778 if (bp->pf.port_id != port_id)
1779 break;
1780
4bb13abf
MC		 1781 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1782 break;
1783 }
87c374de 1784 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
fc0f1929
MC		 1785 if (BNXT_PF(bp))
1786 goto async_event_process_exit;
1787 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1788 break;
c0c050c5 1789 default:
19241368 1790 goto async_event_process_exit;
c0c050c5 1791 }
c213eae8 1792 bnxt_queue_sp_work(bp);
19241368 1793async_event_process_exit:
a588e458 1794 bnxt_ulp_async_events(bp, cmpl);
c0c050c5
MC		 1795 return 0;
1796}
1797
1798static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1799{
1800 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1801 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1802 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1803 (struct hwrm_fwd_req_cmpl *)txcmp;
1804
1805 switch (cmpl_type) {
1806 case CMPL_BASE_TYPE_HWRM_DONE:
1807 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1808 if (seq_id == bp->hwrm_intr_seq_id)
1809 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1810 else
1811 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1812 break;
1813
1814 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1815 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1816
1817 if ((vf_id < bp->pf.first_vf_id) ||
1818 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1819 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1820 vf_id);
1821 return -EINVAL;
1822 }
1823
1824 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1825 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
c213eae8 1826 bnxt_queue_sp_work(bp);
c0c050c5
MC		 1827 break;
1828
1829 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1830 bnxt_async_event_process(bp,
1831 (struct hwrm_async_event_cmpl *)txcmp);
1832
1833 default:
1834 break;
1835 }
1836
1837 return 0;
1838}
1839
1840static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1841{
1842 struct bnxt_napi *bnapi = dev_instance;
1843 struct bnxt *bp = bnapi->bp;
1844 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1845 u32 cons = RING_CMP(cpr->cp_raw_cons);
1846
6a8788f2 1847 cpr->event_ctr++;
c0c050c5
MC		 1848 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1849 napi_schedule(&bnapi->napi);
1850 return IRQ_HANDLED;
1851}
1852
1853static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1854{
1855 u32 raw_cons = cpr->cp_raw_cons;
1856 u16 cons = RING_CMP(raw_cons);
1857 struct tx_cmp *txcmp;
1858
1859 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1860
1861 return TX_CMP_VALID(txcmp, raw_cons);
1862}
1863
c0c050c5
MC		 1864static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1865{
1866 struct bnxt_napi *bnapi = dev_instance;
1867 struct bnxt *bp = bnapi->bp;
1868 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1869 u32 cons = RING_CMP(cpr->cp_raw_cons);
1870 u32 int_status;
1871
1872 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1873
1874 if (!bnxt_has_work(bp, cpr)) {
11809490 1875 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
c0c050c5
MC		 1876 /* return if erroneous interrupt */
1877 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1878 return IRQ_NONE;
1879 }
1880
1881 /* disable ring IRQ */
697197e5 1882 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
c0c050c5
MC		 1883
1884 /* Return here if interrupt is shared and is disabled. */
1885 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1886 return IRQ_HANDLED;
1887
1888 napi_schedule(&bnapi->napi);
1889 return IRQ_HANDLED;
1890}
1891
3675b92f
MC		 1892static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1893 int budget)
c0c050c5 1894{
e44758b7 1895 struct bnxt_napi *bnapi = cpr->bnapi;
c0c050c5
MC		 1896 u32 raw_cons = cpr->cp_raw_cons;
1897 u32 cons;
1898 int tx_pkts = 0;
1899 int rx_pkts = 0;
4e5dbbda 1900 u8 event = 0;
c0c050c5
MC		 1901 struct tx_cmp *txcmp;
1902
1903 while (1) {
1904 int rc;
1905
1906 cons = RING_CMP(raw_cons);
1907 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1908
1909 if (!TX_CMP_VALID(txcmp, raw_cons))
1910 break;
1911
67a95e20
MC		 1912 /* The valid test of the entry must be done first before
1913 * reading any further.
1914 */
b67daab0 1915 dma_rmb();
3675b92f 1916 cpr->had_work_done = 1;
c0c050c5
MC		 1917 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1918 tx_pkts++;
1919 /* return full budget so NAPI will complete. */
73f21c65 1920 if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
c0c050c5 1921 rx_pkts = budget;
73f21c65
MC		 1922 raw_cons = NEXT_RAW_CMP(raw_cons);
1923 break;
1924 }
c0c050c5 1925 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2270bc5d 1926 if (likely(budget))
e44758b7 1927 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2270bc5d 1928 else
e44758b7 1929 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
2270bc5d 1930 &event);
c0c050c5
MC		 1931 if (likely(rc >= 0))
1932 rx_pkts += rc;
903649e7
MC		 1933 /* Increment rx_pkts when rc is -ENOMEM to count towards
1934 * the NAPI budget. Otherwise, we may potentially loop
1935 * here forever if we consistently cannot allocate
1936 * buffers.
1937 */
2edbdb31 1938 else if (rc == -ENOMEM && budget)
903649e7 1939 rx_pkts++;
c0c050c5
MC		 1940 else if (rc == -EBUSY) /* partial completion */
1941 break;
c0c050c5
MC		 1942 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1943 CMPL_BASE_TYPE_HWRM_DONE) ||
1944 (TX_CMP_TYPE(txcmp) ==
1945 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1946 (TX_CMP_TYPE(txcmp) ==
1947 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1948 bnxt_hwrm_handler(bp, txcmp);
1949 }
1950 raw_cons = NEXT_RAW_CMP(raw_cons);
1951
73f21c65 1952 if (rx_pkts && rx_pkts == budget)
c0c050c5
MC		 1953 break;
1954 }
1955
38413406
MC		 1956 if (event & BNXT_TX_EVENT) {
1957 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
38413406
MC		 1958 u16 prod = txr->tx_prod;
1959
1960 /* Sync BD data before updating doorbell */
1961 wmb();
1962
697197e5 1963 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
38413406
MC		 1964 }
1965
c0c050c5 1966 cpr->cp_raw_cons = raw_cons;
3675b92f
MC		 1967 bnapi->tx_pkts += tx_pkts;
1968 bnapi->events |= event;
1969 return rx_pkts;
1970}
c0c050c5 1971
3675b92f
MC		 1972static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi)
1973{
1974 if (bnapi->tx_pkts) {
1975 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts);
1976 bnapi->tx_pkts = 0;
1977 }
c0c050c5 1978
3675b92f 1979 if (bnapi->events & BNXT_RX_EVENT) {
b6ab4b01 1980 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5 1981
697197e5 1982 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
3675b92f 1983 if (bnapi->events & BNXT_AGG_EVENT)
697197e5 1984 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
c0c050c5 1985 }
3675b92f
MC		 1986 bnapi->events = 0;
1987}
1988
1989static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1990 int budget)
1991{
1992 struct bnxt_napi *bnapi = cpr->bnapi;
1993 int rx_pkts;
1994
1995 rx_pkts = __bnxt_poll_work(bp, cpr, budget);
1996
1997 /* ACK completion ring before freeing tx ring and producing new
1998 * buffers in rx/agg rings to prevent overflowing the completion
1999 * ring.
2000 */
2001 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
2002
2003 __bnxt_poll_work_done(bp, bnapi);
c0c050c5
MC		 2004 return rx_pkts;
2005}
2006
10bbdaf5
PS		 2007static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
2008{
2009 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2010 struct bnxt *bp = bnapi->bp;
2011 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2012 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2013 struct tx_cmp *txcmp;
2014 struct rx_cmp_ext *rxcmp1;
2015 u32 cp_cons, tmp_raw_cons;
2016 u32 raw_cons = cpr->cp_raw_cons;
2017 u32 rx_pkts = 0;
4e5dbbda 2018 u8 event = 0;
10bbdaf5
PS		 2019
2020 while (1) {
2021 int rc;
2022
2023 cp_cons = RING_CMP(raw_cons);
2024 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2025
2026 if (!TX_CMP_VALID(txcmp, raw_cons))
2027 break;
2028
2029 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2030 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2031 cp_cons = RING_CMP(tmp_raw_cons);
2032 rxcmp1 = (struct rx_cmp_ext *)
2033 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2034
2035 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2036 break;
2037
2038 /* force an error to recycle the buffer */
2039 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2040 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2041
e44758b7 2042 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2edbdb31 2043 if (likely(rc == -EIO) && budget)
10bbdaf5
PS		 2044 rx_pkts++;
2045 else if (rc == -EBUSY) /* partial completion */
2046 break;
2047 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2048 CMPL_BASE_TYPE_HWRM_DONE)) {
2049 bnxt_hwrm_handler(bp, txcmp);
2050 } else {
2051 netdev_err(bp->dev,
2052 "Invalid completion received on special ring\n");
2053 }
2054 raw_cons = NEXT_RAW_CMP(raw_cons);
2055
2056 if (rx_pkts == budget)
2057 break;
2058 }
2059
2060 cpr->cp_raw_cons = raw_cons;
697197e5
MC		 2061 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
2062 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
10bbdaf5 2063
434c975a 2064 if (event & BNXT_AGG_EVENT)
697197e5 2065 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
10bbdaf5
PS		 2066
2067 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
6ad20165 2068 napi_complete_done(napi, rx_pkts);
697197e5 2069 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
10bbdaf5
PS		 2070 }
2071 return rx_pkts;
2072}
2073
c0c050c5
MC		 2074static int bnxt_poll(struct napi_struct *napi, int budget)
2075{
2076 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2077 struct bnxt *bp = bnapi->bp;
2078 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2079 int work_done = 0;
2080
c0c050c5 2081 while (1) {
e44758b7 2082 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
c0c050c5 2083
73f21c65
MC		 2084 if (work_done >= budget) {
2085 if (!budget)
697197e5 2086 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
c0c050c5 2087 break;
73f21c65 2088 }
c0c050c5
MC		 2089
2090 if (!bnxt_has_work(bp, cpr)) {
e7b95691 2091 if (napi_complete_done(napi, work_done))
697197e5 2092 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
c0c050c5
MC		 2093 break;
2094 }
2095 }
6a8788f2
AG		 2096 if (bp->flags & BNXT_FLAG_DIM) {
2097 struct net_dim_sample dim_sample;
2098
2099 net_dim_sample(cpr->event_ctr,
2100 cpr->rx_packets,
2101 cpr->rx_bytes,
2102 &dim_sample);
2103 net_dim(&cpr->dim, dim_sample);
2104 }
c0c050c5 2105 mmiowb();
c0c050c5
MC		 2106 return work_done;
2107}
2108
c0c050c5
MC		 2109static void bnxt_free_tx_skbs(struct bnxt *bp)
2110{
2111 int i, max_idx;
2112 struct pci_dev *pdev = bp->pdev;
2113
b6ab4b01 2114 if (!bp->tx_ring)
c0c050c5
MC		 2115 return;
2116
2117 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2118 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2119 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2120 int j;
2121
c0c050c5
MC		 2122 for (j = 0; j < max_idx;) {
2123 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2124 struct sk_buff *skb = tx_buf->skb;
2125 int k, last;
2126
2127 if (!skb) {
2128 j++;
2129 continue;
2130 }
2131
2132 tx_buf->skb = NULL;
2133
2134 if (tx_buf->is_push) {
2135 dev_kfree_skb(skb);
2136 j += 2;
2137 continue;
2138 }
2139
2140 dma_unmap_single(&pdev->dev,
2141 dma_unmap_addr(tx_buf, mapping),
2142 skb_headlen(skb),
2143 PCI_DMA_TODEVICE);
2144
2145 last = tx_buf->nr_frags;
2146 j += 2;
d612a579
MC		 2147 for (k = 0; k < last; k++, j++) {
2148 int ring_idx = j & bp->tx_ring_mask;
c0c050c5
MC		 2149 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2150
d612a579 2151 tx_buf = &txr->tx_buf_ring[ring_idx];
c0c050c5
MC		 2152 dma_unmap_page(
2153 &pdev->dev,
2154 dma_unmap_addr(tx_buf, mapping),
2155 skb_frag_size(frag), PCI_DMA_TODEVICE);
2156 }
2157 dev_kfree_skb(skb);
2158 }
2159 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2160 }
2161}
2162
2163static void bnxt_free_rx_skbs(struct bnxt *bp)
2164{
2165 int i, max_idx, max_agg_idx;
2166 struct pci_dev *pdev = bp->pdev;
2167
b6ab4b01 2168 if (!bp->rx_ring)
c0c050c5
MC		 2169 return;
2170
2171 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2172 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2173 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 2174 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 2175 int j;
2176
c0c050c5
MC		 2177 if (rxr->rx_tpa) {
2178 for (j = 0; j < MAX_TPA; j++) {
2179 struct bnxt_tpa_info *tpa_info =
2180 &rxr->rx_tpa[j];
2181 u8 *data = tpa_info->data;
2182
2183 if (!data)
2184 continue;
2185
c519fe9a
SN		 2186 dma_unmap_single_attrs(&pdev->dev,
2187 tpa_info->mapping,
2188 bp->rx_buf_use_size,
2189 bp->rx_dir,
2190 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 2191
2192 tpa_info->data = NULL;
2193
2194 kfree(data);
2195 }
2196 }
2197
2198 for (j = 0; j < max_idx; j++) {
2199 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
3ed3a83e 2200 dma_addr_t mapping = rx_buf->mapping;
6bb19474 2201 void *data = rx_buf->data;
c0c050c5
MC		 2202
2203 if (!data)
2204 continue;
2205
c0c050c5
MC		 2206 rx_buf->data = NULL;
2207
3ed3a83e
MC		 2208 if (BNXT_RX_PAGE_MODE(bp)) {
2209 mapping -= bp->rx_dma_offset;
c519fe9a
SN		 2210 dma_unmap_page_attrs(&pdev->dev, mapping,
2211 PAGE_SIZE, bp->rx_dir,
2212 DMA_ATTR_WEAK_ORDERING);
c61fb99c 2213 __free_page(data);
3ed3a83e 2214 } else {
c519fe9a
SN		 2215 dma_unmap_single_attrs(&pdev->dev, mapping,
2216 bp->rx_buf_use_size,
2217 bp->rx_dir,
2218 DMA_ATTR_WEAK_ORDERING);
c61fb99c 2219 kfree(data);
3ed3a83e 2220 }
c0c050c5
MC		 2221 }
2222
2223 for (j = 0; j < max_agg_idx; j++) {
2224 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2225 &rxr->rx_agg_ring[j];
2226 struct page *page = rx_agg_buf->page;
2227
2228 if (!page)
2229 continue;
2230
c519fe9a
SN		 2231 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2232 BNXT_RX_PAGE_SIZE,
2233 PCI_DMA_FROMDEVICE,
2234 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 2235
2236 rx_agg_buf->page = NULL;
2237 __clear_bit(j, rxr->rx_agg_bmap);
2238
2239 __free_page(page);
2240 }
89d0a06c
MC		 2241 if (rxr->rx_page) {
2242 __free_page(rxr->rx_page);
2243 rxr->rx_page = NULL;
2244 }
c0c050c5
MC		 2245 }
2246}
2247
2248static void bnxt_free_skbs(struct bnxt *bp)
2249{
2250 bnxt_free_tx_skbs(bp);
2251 bnxt_free_rx_skbs(bp);
2252}
2253
6fe19886 2254static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
c0c050c5
MC		 2255{
2256 struct pci_dev *pdev = bp->pdev;
2257 int i;
2258
6fe19886
MC		 2259 for (i = 0; i < rmem->nr_pages; i++) {
2260 if (!rmem->pg_arr[i])
c0c050c5
MC		 2261 continue;
2262
6fe19886
MC		 2263 dma_free_coherent(&pdev->dev, rmem->page_size,
2264 rmem->pg_arr[i], rmem->dma_arr[i]);
c0c050c5 2265
6fe19886 2266 rmem->pg_arr[i] = NULL;
c0c050c5 2267 }
6fe19886
MC		 2268 if (rmem->pg_tbl) {
2269 dma_free_coherent(&pdev->dev, rmem->nr_pages * 8,
2270 rmem->pg_tbl, rmem->pg_tbl_map);
2271 rmem->pg_tbl = NULL;
c0c050c5 2272 }
6fe19886
MC		 2273 if (rmem->vmem_size && *rmem->vmem) {
2274 vfree(*rmem->vmem);
2275 *rmem->vmem = NULL;
c0c050c5
MC		 2276 }
2277}
2278
6fe19886 2279static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
c0c050c5 2280{
c0c050c5 2281 struct pci_dev *pdev = bp->pdev;
66cca20a 2282 u64 valid_bit = 0;
6fe19886 2283 int i;
c0c050c5 2284
66cca20a
MC		 2285 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
2286 valid_bit = PTU_PTE_VALID;
6fe19886
MC		 2287 if (rmem->nr_pages > 1) {
2288 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev,
2289 rmem->nr_pages * 8,
2290 &rmem->pg_tbl_map,
c0c050c5 2291 GFP_KERNEL);
6fe19886 2292 if (!rmem->pg_tbl)
c0c050c5
MC		 2293 return -ENOMEM;
2294 }
2295
6fe19886 2296 for (i = 0; i < rmem->nr_pages; i++) {
66cca20a
MC		 2297 u64 extra_bits = valid_bit;
2298
6fe19886
MC		 2299 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2300 rmem->page_size,
2301 &rmem->dma_arr[i],
c0c050c5 2302 GFP_KERNEL);
6fe19886 2303 if (!rmem->pg_arr[i])
c0c050c5
MC		 2304 return -ENOMEM;
2305
66cca20a
MC		 2306 if (rmem->nr_pages > 1) {
2307 if (i == rmem->nr_pages - 2 &&
2308 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2309 extra_bits |= PTU_PTE_NEXT_TO_LAST;
2310 else if (i == rmem->nr_pages - 1 &&
2311 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2312 extra_bits |= PTU_PTE_LAST;
2313 rmem->pg_tbl[i] =
2314 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
2315 }
c0c050c5
MC		 2316 }
2317
6fe19886
MC		 2318 if (rmem->vmem_size) {
2319 *rmem->vmem = vzalloc(rmem->vmem_size);
2320 if (!(*rmem->vmem))
c0c050c5
MC		 2321 return -ENOMEM;
2322 }
2323 return 0;
2324}
2325
2326static void bnxt_free_rx_rings(struct bnxt *bp)
2327{
2328 int i;
2329
b6ab4b01 2330 if (!bp->rx_ring)
c0c050c5
MC		 2331 return;
2332
2333 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 2334 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 2335 struct bnxt_ring_struct *ring;
2336
c6d30e83
MC		 2337 if (rxr->xdp_prog)
2338 bpf_prog_put(rxr->xdp_prog);
2339
96a8604f
JDB		 2340 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2341 xdp_rxq_info_unreg(&rxr->xdp_rxq);
2342
c0c050c5
MC		 2343 kfree(rxr->rx_tpa);
2344 rxr->rx_tpa = NULL;
2345
2346 kfree(rxr->rx_agg_bmap);
2347 rxr->rx_agg_bmap = NULL;
2348
2349 ring = &rxr->rx_ring_struct;
6fe19886 2350 bnxt_free_ring(bp, &ring->ring_mem);
c0c050c5
MC		 2351
2352 ring = &rxr->rx_agg_ring_struct;
6fe19886 2353 bnxt_free_ring(bp, &ring->ring_mem);
c0c050c5
MC		 2354 }
2355}
2356
2357static int bnxt_alloc_rx_rings(struct bnxt *bp)
2358{
2359 int i, rc, agg_rings = 0, tpa_rings = 0;
2360
b6ab4b01
MC		 2361 if (!bp->rx_ring)
2362 return -ENOMEM;
2363
c0c050c5
MC		 2364 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2365 agg_rings = 1;
2366
2367 if (bp->flags & BNXT_FLAG_TPA)
2368 tpa_rings = 1;
2369
2370 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 2371 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 2372 struct bnxt_ring_struct *ring;
2373
c0c050c5
MC		 2374 ring = &rxr->rx_ring_struct;
2375
96a8604f
JDB		 2376 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2377 if (rc < 0)
2378 return rc;
2379
6fe19886 2380 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
c0c050c5
MC		 2381 if (rc)
2382 return rc;
2383
2c61d211 2384 ring->grp_idx = i;
c0c050c5
MC		 2385 if (agg_rings) {
2386 u16 mem_size;
2387
2388 ring = &rxr->rx_agg_ring_struct;
6fe19886 2389 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
c0c050c5
MC		 2390 if (rc)
2391 return rc;
2392
9899bb59 2393 ring->grp_idx = i;
c0c050c5
MC		 2394 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2395 mem_size = rxr->rx_agg_bmap_size / 8;
2396 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2397 if (!rxr->rx_agg_bmap)
2398 return -ENOMEM;
2399
2400 if (tpa_rings) {
2401 rxr->rx_tpa = kcalloc(MAX_TPA,
2402 sizeof(struct bnxt_tpa_info),
2403 GFP_KERNEL);
2404 if (!rxr->rx_tpa)
2405 return -ENOMEM;
2406 }
2407 }
2408 }
2409 return 0;
2410}
2411
2412static void bnxt_free_tx_rings(struct bnxt *bp)
2413{
2414 int i;
2415 struct pci_dev *pdev = bp->pdev;
2416
b6ab4b01 2417 if (!bp->tx_ring)
c0c050c5
MC		 2418 return;
2419
2420 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2421 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2422 struct bnxt_ring_struct *ring;
2423
c0c050c5
MC		 2424 if (txr->tx_push) {
2425 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2426 txr->tx_push, txr->tx_push_mapping);
2427 txr->tx_push = NULL;
2428 }
2429
2430 ring = &txr->tx_ring_struct;
2431
6fe19886 2432 bnxt_free_ring(bp, &ring->ring_mem);
c0c050c5
MC		 2433 }
2434}
2435
2436static int bnxt_alloc_tx_rings(struct bnxt *bp)
2437{
2438 int i, j, rc;
2439 struct pci_dev *pdev = bp->pdev;
2440
2441 bp->tx_push_size = 0;
2442 if (bp->tx_push_thresh) {
2443 int push_size;
2444
2445 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2446 bp->tx_push_thresh);
2447
4419dbe6 2448 if (push_size > 256) {
c0c050c5
MC		 2449 push_size = 0;
2450 bp->tx_push_thresh = 0;
2451 }
2452
2453 bp->tx_push_size = push_size;
2454 }
2455
2456 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2457 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5 2458 struct bnxt_ring_struct *ring;
2e8ef77e 2459 u8 qidx;
c0c050c5 2460
c0c050c5
MC		 2461 ring = &txr->tx_ring_struct;
2462
6fe19886 2463 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
c0c050c5
MC		 2464 if (rc)
2465 return rc;
2466
9899bb59 2467 ring->grp_idx = txr->bnapi->index;
c0c050c5 2468 if (bp->tx_push_size) {
c0c050c5
MC		 2469 dma_addr_t mapping;
2470
2471 /* One pre-allocated DMA buffer to backup
2472 * TX push operation
2473 */
2474 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2475 bp->tx_push_size,
2476 &txr->tx_push_mapping,
2477 GFP_KERNEL);
2478
2479 if (!txr->tx_push)
2480 return -ENOMEM;
2481
c0c050c5
MC		 2482 mapping = txr->tx_push_mapping +
2483 sizeof(struct tx_push_bd);
4419dbe6 2484 txr->data_mapping = cpu_to_le64(mapping);
c0c050c5 2485
4419dbe6 2486 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
c0c050c5 2487 }
2e8ef77e
MC		 2488 qidx = bp->tc_to_qidx[j];
2489 ring->queue_id = bp->q_info[qidx].queue_id;
5f449249
MC		 2490 if (i < bp->tx_nr_rings_xdp)
2491 continue;
c0c050c5
MC		 2492 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2493 j++;
2494 }
2495 return 0;
2496}
2497
2498static void bnxt_free_cp_rings(struct bnxt *bp)
2499{
2500 int i;
2501
2502 if (!bp->bnapi)
2503 return;
2504
2505 for (i = 0; i < bp->cp_nr_rings; i++) {
2506 struct bnxt_napi *bnapi = bp->bnapi[i];
2507 struct bnxt_cp_ring_info *cpr;
2508 struct bnxt_ring_struct *ring;
50e3ab78 2509 int j;
c0c050c5
MC		 2510
2511 if (!bnapi)
2512 continue;
2513
2514 cpr = &bnapi->cp_ring;
2515 ring = &cpr->cp_ring_struct;
2516
6fe19886 2517 bnxt_free_ring(bp, &ring->ring_mem);
50e3ab78
MC		 2518
2519 for (j = 0; j < 2; j++) {
2520 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2521
2522 if (cpr2) {
2523 ring = &cpr2->cp_ring_struct;
2524 bnxt_free_ring(bp, &ring->ring_mem);
2525 kfree(cpr2);
2526 cpr->cp_ring_arr[j] = NULL;
2527 }
2528 }
c0c050c5
MC		 2529 }
2530}
2531
50e3ab78
MC		 2532static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)
2533{
2534 struct bnxt_ring_mem_info *rmem;
2535 struct bnxt_ring_struct *ring;
2536 struct bnxt_cp_ring_info *cpr;
2537 int rc;
2538
2539 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
2540 if (!cpr)
2541 return NULL;
2542
2543 ring = &cpr->cp_ring_struct;
2544 rmem = &ring->ring_mem;
2545 rmem->nr_pages = bp->cp_nr_pages;
2546 rmem->page_size = HW_CMPD_RING_SIZE;
2547 rmem->pg_arr = (void **)cpr->cp_desc_ring;
2548 rmem->dma_arr = cpr->cp_desc_mapping;
2549 rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
2550 rc = bnxt_alloc_ring(bp, rmem);
2551 if (rc) {
2552 bnxt_free_ring(bp, rmem);
2553 kfree(cpr);
2554 cpr = NULL;
2555 }
2556 return cpr;
2557}
2558
c0c050c5
MC		 2559static int bnxt_alloc_cp_rings(struct bnxt *bp)
2560{
50e3ab78 2561 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
e5811b8c 2562 int i, rc, ulp_base_vec, ulp_msix;
c0c050c5 2563
e5811b8c
MC		 2564 ulp_msix = bnxt_get_ulp_msix_num(bp);
2565 ulp_base_vec = bnxt_get_ulp_msix_base(bp);
c0c050c5
MC		 2566 for (i = 0; i < bp->cp_nr_rings; i++) {
2567 struct bnxt_napi *bnapi = bp->bnapi[i];
2568 struct bnxt_cp_ring_info *cpr;
2569 struct bnxt_ring_struct *ring;
2570
2571 if (!bnapi)
2572 continue;
2573
2574 cpr = &bnapi->cp_ring;
50e3ab78 2575 cpr->bnapi = bnapi;
c0c050c5
MC		 2576 ring = &cpr->cp_ring_struct;
2577
6fe19886 2578 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
c0c050c5
MC		 2579 if (rc)
2580 return rc;
e5811b8c
MC		 2581
2582 if (ulp_msix && i >= ulp_base_vec)
2583 ring->map_idx = i + ulp_msix;
2584 else
2585 ring->map_idx = i;
50e3ab78
MC		 2586
2587 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
2588 continue;
2589
2590 if (i < bp->rx_nr_rings) {
2591 struct bnxt_cp_ring_info *cpr2 =
2592 bnxt_alloc_cp_sub_ring(bp);
2593
2594 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
2595 if (!cpr2)
2596 return -ENOMEM;
2597 cpr2->bnapi = bnapi;
2598 }
2599 if ((sh && i < bp->tx_nr_rings) ||
2600 (!sh && i >= bp->rx_nr_rings)) {
2601 struct bnxt_cp_ring_info *cpr2 =
2602 bnxt_alloc_cp_sub_ring(bp);
2603
2604 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
2605 if (!cpr2)
2606 return -ENOMEM;
2607 cpr2->bnapi = bnapi;
2608 }
c0c050c5
MC		 2609 }
2610 return 0;
2611}
2612
2613static void bnxt_init_ring_struct(struct bnxt *bp)
2614{
2615 int i;
2616
2617 for (i = 0; i < bp->cp_nr_rings; i++) {
2618 struct bnxt_napi *bnapi = bp->bnapi[i];
6fe19886 2619 struct bnxt_ring_mem_info *rmem;
c0c050c5
MC		 2620 struct bnxt_cp_ring_info *cpr;
2621 struct bnxt_rx_ring_info *rxr;
2622 struct bnxt_tx_ring_info *txr;
2623 struct bnxt_ring_struct *ring;
2624
2625 if (!bnapi)
2626 continue;
2627
2628 cpr = &bnapi->cp_ring;
2629 ring = &cpr->cp_ring_struct;
6fe19886
MC		 2630 rmem = &ring->ring_mem;
2631 rmem->nr_pages = bp->cp_nr_pages;
2632 rmem->page_size = HW_CMPD_RING_SIZE;
2633 rmem->pg_arr = (void **)cpr->cp_desc_ring;
2634 rmem->dma_arr = cpr->cp_desc_mapping;
2635 rmem->vmem_size = 0;
c0c050c5 2636
b6ab4b01 2637 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 2638 if (!rxr)
2639 goto skip_rx;
2640
c0c050c5 2641 ring = &rxr->rx_ring_struct;
6fe19886
MC		 2642 rmem = &ring->ring_mem;
2643 rmem->nr_pages = bp->rx_nr_pages;
2644 rmem->page_size = HW_RXBD_RING_SIZE;
2645 rmem->pg_arr = (void **)rxr->rx_desc_ring;
2646 rmem->dma_arr = rxr->rx_desc_mapping;
2647 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2648 rmem->vmem = (void **)&rxr->rx_buf_ring;
c0c050c5
MC		 2649
2650 ring = &rxr->rx_agg_ring_struct;
6fe19886
MC		 2651 rmem = &ring->ring_mem;
2652 rmem->nr_pages = bp->rx_agg_nr_pages;
2653 rmem->page_size = HW_RXBD_RING_SIZE;
2654 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
2655 rmem->dma_arr = rxr->rx_agg_desc_mapping;
2656 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2657 rmem->vmem = (void **)&rxr->rx_agg_ring;
c0c050c5 2658
3b2b7d9d 2659skip_rx:
b6ab4b01 2660 txr = bnapi->tx_ring;
3b2b7d9d
MC		 2661 if (!txr)
2662 continue;
2663
c0c050c5 2664 ring = &txr->tx_ring_struct;
6fe19886
MC		 2665 rmem = &ring->ring_mem;
2666 rmem->nr_pages = bp->tx_nr_pages;
2667 rmem->page_size = HW_RXBD_RING_SIZE;
2668 rmem->pg_arr = (void **)txr->tx_desc_ring;
2669 rmem->dma_arr = txr->tx_desc_mapping;
2670 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2671 rmem->vmem = (void **)&txr->tx_buf_ring;
c0c050c5
MC		 2672 }
2673}
2674
2675static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2676{
2677 int i;
2678 u32 prod;
2679 struct rx_bd **rx_buf_ring;
2680
6fe19886
MC		 2681 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
2682 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
c0c050c5
MC		 2683 int j;
2684 struct rx_bd *rxbd;
2685
2686 rxbd = rx_buf_ring[i];
2687 if (!rxbd)
2688 continue;
2689
2690 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2691 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2692 rxbd->rx_bd_opaque = prod;
2693 }
2694 }
2695}
2696
2697static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2698{
2699 struct net_device *dev = bp->dev;
c0c050c5
MC		 2700 struct bnxt_rx_ring_info *rxr;
2701 struct bnxt_ring_struct *ring;
2702 u32 prod, type;
2703 int i;
2704
c0c050c5
MC		 2705 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2706 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2707
2708 if (NET_IP_ALIGN == 2)
2709 type |= RX_BD_FLAGS_SOP;
2710
b6ab4b01 2711 rxr = &bp->rx_ring[ring_nr];
c0c050c5
MC		 2712 ring = &rxr->rx_ring_struct;
2713 bnxt_init_rxbd_pages(ring, type);
2714
c6d30e83
MC		 2715 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2716 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2717 if (IS_ERR(rxr->xdp_prog)) {
2718 int rc = PTR_ERR(rxr->xdp_prog);
2719
2720 rxr->xdp_prog = NULL;
2721 return rc;
2722 }
2723 }
c0c050c5
MC		 2724 prod = rxr->rx_prod;
2725 for (i = 0; i < bp->rx_ring_size; i++) {
2726 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2727 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2728 ring_nr, i, bp->rx_ring_size);
2729 break;
2730 }
2731 prod = NEXT_RX(prod);
2732 }
2733 rxr->rx_prod = prod;
2734 ring->fw_ring_id = INVALID_HW_RING_ID;
2735
edd0c2cc
MC		 2736 ring = &rxr->rx_agg_ring_struct;
2737 ring->fw_ring_id = INVALID_HW_RING_ID;
2738
c0c050c5
MC		 2739 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2740 return 0;
2741
2839f28b 2742 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
c0c050c5
MC		 2743 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2744
2745 bnxt_init_rxbd_pages(ring, type);
2746
2747 prod = rxr->rx_agg_prod;
2748 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2749 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2750 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2751 ring_nr, i, bp->rx_ring_size);
2752 break;
2753 }
2754 prod = NEXT_RX_AGG(prod);
2755 }
2756 rxr->rx_agg_prod = prod;
c0c050c5
MC		 2757
2758 if (bp->flags & BNXT_FLAG_TPA) {
2759 if (rxr->rx_tpa) {
2760 u8 *data;
2761 dma_addr_t mapping;
2762
2763 for (i = 0; i < MAX_TPA; i++) {
2764 data = __bnxt_alloc_rx_data(bp, &mapping,
2765 GFP_KERNEL);
2766 if (!data)
2767 return -ENOMEM;
2768
2769 rxr->rx_tpa[i].data = data;
b3dba77c 2770 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
c0c050c5
MC		 2771 rxr->rx_tpa[i].mapping = mapping;
2772 }
2773 } else {
2774 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2775 return -ENOMEM;
2776 }
2777 }
2778
2779 return 0;
2780}
2781
2247925f
SP		 2782static void bnxt_init_cp_rings(struct bnxt *bp)
2783{
3e08b184 2784 int i, j;
2247925f
SP		 2785
2786 for (i = 0; i < bp->cp_nr_rings; i++) {
2787 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2788 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2789
2790 ring->fw_ring_id = INVALID_HW_RING_ID;
6a8788f2
AG		 2791 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2792 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
3e08b184
MC		 2793 for (j = 0; j < 2; j++) {
2794 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2795
2796 if (!cpr2)
2797 continue;
2798
2799 ring = &cpr2->cp_ring_struct;
2800 ring->fw_ring_id = INVALID_HW_RING_ID;
2801 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2802 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2803 }
2247925f
SP		 2804 }
2805}
2806
c0c050c5
MC		 2807static int bnxt_init_rx_rings(struct bnxt *bp)
2808{
2809 int i, rc = 0;
2810
c61fb99c 2811 if (BNXT_RX_PAGE_MODE(bp)) {
c6d30e83
MC		 2812 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2813 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
c61fb99c
MC		 2814 } else {
2815 bp->rx_offset = BNXT_RX_OFFSET;
2816 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2817 }
b3dba77c 2818
c0c050c5
MC		 2819 for (i = 0; i < bp->rx_nr_rings; i++) {
2820 rc = bnxt_init_one_rx_ring(bp, i);
2821 if (rc)
2822 break;
2823 }
2824
2825 return rc;
2826}
2827
2828static int bnxt_init_tx_rings(struct bnxt *bp)
2829{
2830 u16 i;
2831
2832 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2833 MAX_SKB_FRAGS + 1);
2834
2835 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2836 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2837 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2838
2839 ring->fw_ring_id = INVALID_HW_RING_ID;
2840 }
2841
2842 return 0;
2843}
2844
2845static void bnxt_free_ring_grps(struct bnxt *bp)
2846{
2847 kfree(bp->grp_info);
2848 bp->grp_info = NULL;
2849}
2850
2851static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2852{
2853 int i;
2854
2855 if (irq_re_init) {
2856 bp->grp_info = kcalloc(bp->cp_nr_rings,
2857 sizeof(struct bnxt_ring_grp_info),
2858 GFP_KERNEL);
2859 if (!bp->grp_info)
2860 return -ENOMEM;
2861 }
2862 for (i = 0; i < bp->cp_nr_rings; i++) {
2863 if (irq_re_init)
2864 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2865 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2866 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2867 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2868 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2869 }
2870 return 0;
2871}
2872
2873static void bnxt_free_vnics(struct bnxt *bp)
2874{
2875 kfree(bp->vnic_info);
2876 bp->vnic_info = NULL;
2877 bp->nr_vnics = 0;
2878}
2879
2880static int bnxt_alloc_vnics(struct bnxt *bp)
2881{
2882 int num_vnics = 1;
2883
2884#ifdef CONFIG_RFS_ACCEL
2885 if (bp->flags & BNXT_FLAG_RFS)
2886 num_vnics += bp->rx_nr_rings;
2887#endif
2888
dc52c6c7
PS		 2889 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2890 num_vnics++;
2891
c0c050c5
MC		 2892 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2893 GFP_KERNEL);
2894 if (!bp->vnic_info)
2895 return -ENOMEM;
2896
2897 bp->nr_vnics = num_vnics;
2898 return 0;
2899}
2900
2901static void bnxt_init_vnics(struct bnxt *bp)
2902{
2903 int i;
2904
2905 for (i = 0; i < bp->nr_vnics; i++) {
2906 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
44c6f72a 2907 int j;
c0c050c5
MC		 2908
2909 vnic->fw_vnic_id = INVALID_HW_RING_ID;
44c6f72a
MC		 2910 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
2911 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
2912
c0c050c5
MC		 2913 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2914
2915 if (bp->vnic_info[i].rss_hash_key) {
2916 if (i == 0)
2917 prandom_bytes(vnic->rss_hash_key,
2918 HW_HASH_KEY_SIZE);
2919 else
2920 memcpy(vnic->rss_hash_key,
2921 bp->vnic_info[0].rss_hash_key,
2922 HW_HASH_KEY_SIZE);
2923 }
2924 }
2925}
2926
2927static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2928{
2929 int pages;
2930
2931 pages = ring_size / desc_per_pg;
2932
2933 if (!pages)
2934 return 1;
2935
2936 pages++;
2937
2938 while (pages & (pages - 1))
2939 pages++;
2940
2941 return pages;
2942}
2943
c6d30e83 2944void bnxt_set_tpa_flags(struct bnxt *bp)
c0c050c5
MC		 2945{
2946 bp->flags &= ~BNXT_FLAG_TPA;
341138c3
MC		 2947 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2948 return;
c0c050c5
MC		 2949 if (bp->dev->features & NETIF_F_LRO)
2950 bp->flags |= BNXT_FLAG_LRO;
1054aee8 2951 else if (bp->dev->features & NETIF_F_GRO_HW)
c0c050c5
MC		 2952 bp->flags |= BNXT_FLAG_GRO;
2953}
2954
2955/* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2956 * be set on entry.
2957 */
2958void bnxt_set_ring_params(struct bnxt *bp)
2959{
2960 u32 ring_size, rx_size, rx_space;
2961 u32 agg_factor = 0, agg_ring_size = 0;
2962
2963 /* 8 for CRC and VLAN */
2964 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2965
2966 rx_space = rx_size + NET_SKB_PAD +
2967 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2968
2969 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2970 ring_size = bp->rx_ring_size;
2971 bp->rx_agg_ring_size = 0;
2972 bp->rx_agg_nr_pages = 0;
2973
2974 if (bp->flags & BNXT_FLAG_TPA)
2839f28b 2975 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
c0c050c5
MC		 2976
2977 bp->flags &= ~BNXT_FLAG_JUMBO;
bdbd1eb5 2978 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
c0c050c5
MC		 2979 u32 jumbo_factor;
2980
2981 bp->flags |= BNXT_FLAG_JUMBO;
2982 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2983 if (jumbo_factor > agg_factor)
2984 agg_factor = jumbo_factor;
2985 }
2986 agg_ring_size = ring_size * agg_factor;
2987
2988 if (agg_ring_size) {
2989 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2990 RX_DESC_CNT);
2991 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2992 u32 tmp = agg_ring_size;
2993
2994 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2995 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2996 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2997 tmp, agg_ring_size);
2998 }
2999 bp->rx_agg_ring_size = agg_ring_size;
3000 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
3001 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
3002 rx_space = rx_size + NET_SKB_PAD +
3003 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3004 }
3005
3006 bp->rx_buf_use_size = rx_size;
3007 bp->rx_buf_size = rx_space;
3008
3009 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
3010 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
3011
3012 ring_size = bp->tx_ring_size;
3013 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
3014 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
3015
3016 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
3017 bp->cp_ring_size = ring_size;
3018
3019 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
3020 if (bp->cp_nr_pages > MAX_CP_PAGES) {
3021 bp->cp_nr_pages = MAX_CP_PAGES;
3022 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
3023 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
3024 ring_size, bp->cp_ring_size);
3025 }
3026 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
3027 bp->cp_ring_mask = bp->cp_bit - 1;
3028}
3029
96a8604f
JDB		 3030/* Changing allocation mode of RX rings.
3031 * TODO: Update when extending xdp_rxq_info to support allocation modes.
3032 */
c61fb99c 3033int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
6bb19474 3034{
c61fb99c
MC		 3035 if (page_mode) {
3036 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
3037 return -EOPNOTSUPP;
7eb9bb3a
MC		 3038 bp->dev->max_mtu =
3039 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
c61fb99c
MC		 3040 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
3041 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
c61fb99c
MC		 3042 bp->rx_dir = DMA_BIDIRECTIONAL;
3043 bp->rx_skb_func = bnxt_rx_page_skb;
1054aee8
MC		 3044 /* Disable LRO or GRO_HW */
3045 netdev_update_features(bp->dev);
c61fb99c 3046 } else {
7eb9bb3a 3047 bp->dev->max_mtu = bp->max_mtu;
c61fb99c
MC		 3048 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
3049 bp->rx_dir = DMA_FROM_DEVICE;
3050 bp->rx_skb_func = bnxt_rx_skb;
3051 }
6bb19474
MC		 3052 return 0;
3053}
3054
c0c050c5
MC		 3055static void bnxt_free_vnic_attributes(struct bnxt *bp)
3056{
3057 int i;
3058 struct bnxt_vnic_info *vnic;
3059 struct pci_dev *pdev = bp->pdev;
3060
3061 if (!bp->vnic_info)
3062 return;
3063
3064 for (i = 0; i < bp->nr_vnics; i++) {
3065 vnic = &bp->vnic_info[i];
3066
3067 kfree(vnic->fw_grp_ids);
3068 vnic->fw_grp_ids = NULL;
3069
3070 kfree(vnic->uc_list);
3071 vnic->uc_list = NULL;
3072
3073 if (vnic->mc_list) {
3074 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
3075 vnic->mc_list, vnic->mc_list_mapping);
3076 vnic->mc_list = NULL;
3077 }
3078
3079 if (vnic->rss_table) {
3080 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3081 vnic->rss_table,
3082 vnic->rss_table_dma_addr);
3083 vnic->rss_table = NULL;
3084 }
3085
3086 vnic->rss_hash_key = NULL;
3087 vnic->flags = 0;
3088 }
3089}
3090
3091static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
3092{
3093 int i, rc = 0, size;
3094 struct bnxt_vnic_info *vnic;
3095 struct pci_dev *pdev = bp->pdev;
3096 int max_rings;
3097
3098 for (i = 0; i < bp->nr_vnics; i++) {
3099 vnic = &bp->vnic_info[i];
3100
3101 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
3102 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
3103
3104 if (mem_size > 0) {
3105 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
3106 if (!vnic->uc_list) {
3107 rc = -ENOMEM;
3108 goto out;
3109 }
3110 }
3111 }
3112
3113 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
3114 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
3115 vnic->mc_list =
3116 dma_alloc_coherent(&pdev->dev,
3117 vnic->mc_list_size,
3118 &vnic->mc_list_mapping,
3119 GFP_KERNEL);
3120 if (!vnic->mc_list) {
3121 rc = -ENOMEM;
3122 goto out;
3123 }
3124 }
3125
44c6f72a
MC		 3126 if (bp->flags & BNXT_FLAG_CHIP_P5)
3127 goto vnic_skip_grps;
3128
c0c050c5
MC		 3129 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3130 max_rings = bp->rx_nr_rings;
3131 else
3132 max_rings = 1;
3133
3134 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
3135 if (!vnic->fw_grp_ids) {
3136 rc = -ENOMEM;
3137 goto out;
3138 }
44c6f72a 3139vnic_skip_grps:
ae10ae74
MC		 3140 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3141 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
3142 continue;
3143
c0c050c5
MC		 3144 /* Allocate rss table and hash key */
3145 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3146 &vnic->rss_table_dma_addr,
3147 GFP_KERNEL);
3148 if (!vnic->rss_table) {
3149 rc = -ENOMEM;
3150 goto out;
3151 }
3152
3153 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3154
3155 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3156 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3157 }
3158 return 0;
3159
3160out:
3161 return rc;
3162}
3163
3164static void bnxt_free_hwrm_resources(struct bnxt *bp)
3165{
3166 struct pci_dev *pdev = bp->pdev;
3167
a2bf74f4
VD		 3168 if (bp->hwrm_cmd_resp_addr) {
3169 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3170 bp->hwrm_cmd_resp_dma_addr);
3171 bp->hwrm_cmd_resp_addr = NULL;
3172 }
c0c050c5
MC		 3173}
3174
3175static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3176{
3177 struct pci_dev *pdev = bp->pdev;
3178
3179 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3180 &bp->hwrm_cmd_resp_dma_addr,
3181 GFP_KERNEL);
3182 if (!bp->hwrm_cmd_resp_addr)
3183 return -ENOMEM;
c0c050c5
MC		 3184
3185 return 0;
3186}
3187
e605db80
DK		 3188static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3189{
3190 if (bp->hwrm_short_cmd_req_addr) {
3191 struct pci_dev *pdev = bp->pdev;
3192
1dfddc41 3193 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
e605db80
DK		 3194 bp->hwrm_short_cmd_req_addr,
3195 bp->hwrm_short_cmd_req_dma_addr);
3196 bp->hwrm_short_cmd_req_addr = NULL;
3197 }
3198}
3199
3200static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3201{
3202 struct pci_dev *pdev = bp->pdev;
3203
3204 bp->hwrm_short_cmd_req_addr =
1dfddc41 3205 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
e605db80
DK		 3206 &bp->hwrm_short_cmd_req_dma_addr,
3207 GFP_KERNEL);
3208 if (!bp->hwrm_short_cmd_req_addr)
3209 return -ENOMEM;
3210
3211 return 0;
3212}
3213
c0c050c5
MC		 3214static void bnxt_free_stats(struct bnxt *bp)
3215{
3216 u32 size, i;
3217 struct pci_dev *pdev = bp->pdev;
3218
00db3cba
VV		 3219 bp->flags &= ~BNXT_FLAG_PORT_STATS;
3220 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3221
3bdf56c4
MC		 3222 if (bp->hw_rx_port_stats) {
3223 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3224 bp->hw_rx_port_stats,
3225 bp->hw_rx_port_stats_map);
3226 bp->hw_rx_port_stats = NULL;
00db3cba
VV		 3227 }
3228
36e53349
MC		 3229 if (bp->hw_tx_port_stats_ext) {
3230 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext),
3231 bp->hw_tx_port_stats_ext,
3232 bp->hw_tx_port_stats_ext_map);
3233 bp->hw_tx_port_stats_ext = NULL;
3234 }
3235
00db3cba
VV		 3236 if (bp->hw_rx_port_stats_ext) {
3237 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3238 bp->hw_rx_port_stats_ext,
3239 bp->hw_rx_port_stats_ext_map);
3240 bp->hw_rx_port_stats_ext = NULL;
3bdf56c4
MC		 3241 }
3242
c0c050c5
MC		 3243 if (!bp->bnapi)
3244 return;
3245
3246 size = sizeof(struct ctx_hw_stats);
3247
3248 for (i = 0; i < bp->cp_nr_rings; i++) {
3249 struct bnxt_napi *bnapi = bp->bnapi[i];
3250 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3251
3252 if (cpr->hw_stats) {
3253 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3254 cpr->hw_stats_map);
3255 cpr->hw_stats = NULL;
3256 }
3257 }
3258}
3259
3260static int bnxt_alloc_stats(struct bnxt *bp)
3261{
3262 u32 size, i;
3263 struct pci_dev *pdev = bp->pdev;
3264
3265 size = sizeof(struct ctx_hw_stats);
3266
3267 for (i = 0; i < bp->cp_nr_rings; i++) {
3268 struct bnxt_napi *bnapi = bp->bnapi[i];
3269 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3270
3271 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3272 &cpr->hw_stats_map,
3273 GFP_KERNEL);
3274 if (!cpr->hw_stats)
3275 return -ENOMEM;
3276
3277 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3278 }
3bdf56c4 3279
3e8060fa 3280 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3bdf56c4
MC		 3281 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3282 sizeof(struct tx_port_stats) + 1024;
3283
3284 bp->hw_rx_port_stats =
3285 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3286 &bp->hw_rx_port_stats_map,
3287 GFP_KERNEL);
3288 if (!bp->hw_rx_port_stats)
3289 return -ENOMEM;
3290
3291 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
3292 512;
3293 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3294 sizeof(struct rx_port_stats) + 512;
3295 bp->flags |= BNXT_FLAG_PORT_STATS;
00db3cba
VV		 3296
3297 /* Display extended statistics only if FW supports it */
3298 if (bp->hwrm_spec_code < 0x10804 ||
3299 bp->hwrm_spec_code == 0x10900)
3300 return 0;
3301
3302 bp->hw_rx_port_stats_ext =
3303 dma_zalloc_coherent(&pdev->dev,
3304 sizeof(struct rx_port_stats_ext),
3305 &bp->hw_rx_port_stats_ext_map,
3306 GFP_KERNEL);
3307 if (!bp->hw_rx_port_stats_ext)
3308 return 0;
3309
36e53349
MC		 3310 if (bp->hwrm_spec_code >= 0x10902) {
3311 bp->hw_tx_port_stats_ext =
3312 dma_zalloc_coherent(&pdev->dev,
3313 sizeof(struct tx_port_stats_ext),
3314 &bp->hw_tx_port_stats_ext_map,
3315 GFP_KERNEL);
3316 }
00db3cba 3317 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
3bdf56c4 3318 }
c0c050c5
MC		 3319 return 0;
3320}
3321
3322static void bnxt_clear_ring_indices(struct bnxt *bp)
3323{
3324 int i;
3325
3326 if (!bp->bnapi)
3327 return;
3328
3329 for (i = 0; i < bp->cp_nr_rings; i++) {
3330 struct bnxt_napi *bnapi = bp->bnapi[i];
3331 struct bnxt_cp_ring_info *cpr;
3332 struct bnxt_rx_ring_info *rxr;
3333 struct bnxt_tx_ring_info *txr;
3334
3335 if (!bnapi)
3336 continue;
3337
3338 cpr = &bnapi->cp_ring;
3339 cpr->cp_raw_cons = 0;
3340
b6ab4b01 3341 txr = bnapi->tx_ring;
3b2b7d9d
MC		 3342 if (txr) {
3343 txr->tx_prod = 0;
3344 txr->tx_cons = 0;
3345 }
c0c050c5 3346
b6ab4b01 3347 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 3348 if (rxr) {
3349 rxr->rx_prod = 0;
3350 rxr->rx_agg_prod = 0;
3351 rxr->rx_sw_agg_prod = 0;
376a5b86 3352 rxr->rx_next_cons = 0;
3b2b7d9d 3353 }
c0c050c5
MC		 3354 }
3355}
3356
3357static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3358{
3359#ifdef CONFIG_RFS_ACCEL
3360 int i;
3361
3362 /* Under rtnl_lock and all our NAPIs have been disabled. It's
3363 * safe to delete the hash table.
3364 */
3365 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3366 struct hlist_head *head;
3367 struct hlist_node *tmp;
3368 struct bnxt_ntuple_filter *fltr;
3369
3370 head = &bp->ntp_fltr_hash_tbl[i];
3371 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3372 hlist_del(&fltr->hash);
3373 kfree(fltr);
3374 }
3375 }
3376 if (irq_reinit) {
3377 kfree(bp->ntp_fltr_bmap);
3378 bp->ntp_fltr_bmap = NULL;
3379 }
3380 bp->ntp_fltr_count = 0;
3381#endif
3382}
3383
3384static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3385{
3386#ifdef CONFIG_RFS_ACCEL
3387 int i, rc = 0;
3388
3389 if (!(bp->flags & BNXT_FLAG_RFS))
3390 return 0;
3391
3392 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3393 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3394
3395 bp->ntp_fltr_count = 0;
ac45bd93
DC		 3396 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3397 sizeof(long),
c0c050c5
MC		 3398 GFP_KERNEL);
3399
3400 if (!bp->ntp_fltr_bmap)
3401 rc = -ENOMEM;
3402
3403 return rc;
3404#else
3405 return 0;
3406#endif
3407}
3408
3409static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3410{
3411 bnxt_free_vnic_attributes(bp);
3412 bnxt_free_tx_rings(bp);
3413 bnxt_free_rx_rings(bp);
3414 bnxt_free_cp_rings(bp);
3415 bnxt_free_ntp_fltrs(bp, irq_re_init);
3416 if (irq_re_init) {
3417 bnxt_free_stats(bp);
3418 bnxt_free_ring_grps(bp);
3419 bnxt_free_vnics(bp);
a960dec9
MC		 3420 kfree(bp->tx_ring_map);
3421 bp->tx_ring_map = NULL;
b6ab4b01
MC		 3422 kfree(bp->tx_ring);
3423 bp->tx_ring = NULL;
3424 kfree(bp->rx_ring);
3425 bp->rx_ring = NULL;
c0c050c5
MC		 3426 kfree(bp->bnapi);
3427 bp->bnapi = NULL;
3428 } else {
3429 bnxt_clear_ring_indices(bp);
3430 }
3431}
3432
3433static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3434{
01657bcd 3435 int i, j, rc, size, arr_size;
c0c050c5
MC		 3436 void *bnapi;
3437
3438 if (irq_re_init) {
3439 /* Allocate bnapi mem pointer array and mem block for
3440 * all queues
3441 */
3442 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3443 bp->cp_nr_rings);
3444 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3445 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3446 if (!bnapi)
3447 return -ENOMEM;
3448
3449 bp->bnapi = bnapi;
3450 bnapi += arr_size;
3451 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3452 bp->bnapi[i] = bnapi;
3453 bp->bnapi[i]->index = i;
3454 bp->bnapi[i]->bp = bp;
e38287b7
MC		 3455 if (bp->flags & BNXT_FLAG_CHIP_P5) {
3456 struct bnxt_cp_ring_info *cpr =
3457 &bp->bnapi[i]->cp_ring;
3458
3459 cpr->cp_ring_struct.ring_mem.flags =
3460 BNXT_RMEM_RING_PTE_FLAG;
3461 }
c0c050c5
MC		 3462 }
3463
b6ab4b01
MC		 3464 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3465 sizeof(struct bnxt_rx_ring_info),
3466 GFP_KERNEL);
3467 if (!bp->rx_ring)
3468 return -ENOMEM;
3469
3470 for (i = 0; i < bp->rx_nr_rings; i++) {
e38287b7
MC		 3471 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3472
3473 if (bp->flags & BNXT_FLAG_CHIP_P5) {
3474 rxr->rx_ring_struct.ring_mem.flags =
3475 BNXT_RMEM_RING_PTE_FLAG;
3476 rxr->rx_agg_ring_struct.ring_mem.flags =
3477 BNXT_RMEM_RING_PTE_FLAG;
3478 }
3479 rxr->bnapi = bp->bnapi[i];
b6ab4b01
MC		 3480 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3481 }
3482
3483 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3484 sizeof(struct bnxt_tx_ring_info),
3485 GFP_KERNEL);
3486 if (!bp->tx_ring)
3487 return -ENOMEM;
3488
a960dec9
MC		 3489 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3490 GFP_KERNEL);
3491
3492 if (!bp->tx_ring_map)
3493 return -ENOMEM;
3494
01657bcd
MC		 3495 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3496 j = 0;
3497 else
3498 j = bp->rx_nr_rings;
3499
3500 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
e38287b7
MC		 3501 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3502
3503 if (bp->flags & BNXT_FLAG_CHIP_P5)
3504 txr->tx_ring_struct.ring_mem.flags =
3505 BNXT_RMEM_RING_PTE_FLAG;
3506 txr->bnapi = bp->bnapi[j];
3507 bp->bnapi[j]->tx_ring = txr;
5f449249 3508 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
38413406 3509 if (i >= bp->tx_nr_rings_xdp) {
e38287b7 3510 txr->txq_index = i - bp->tx_nr_rings_xdp;
38413406
MC		 3511 bp->bnapi[j]->tx_int = bnxt_tx_int;
3512 } else {
fa3e93e8 3513 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
38413406
MC		 3514 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3515 }
b6ab4b01
MC		 3516 }
3517
c0c050c5
MC		 3518 rc = bnxt_alloc_stats(bp);
3519 if (rc)
3520 goto alloc_mem_err;
3521
3522 rc = bnxt_alloc_ntp_fltrs(bp);
3523 if (rc)
3524 goto alloc_mem_err;
3525
3526 rc = bnxt_alloc_vnics(bp);
3527 if (rc)
3528 goto alloc_mem_err;
3529 }
3530
3531 bnxt_init_ring_struct(bp);
3532
3533 rc = bnxt_alloc_rx_rings(bp);
3534 if (rc)
3535 goto alloc_mem_err;
3536
3537 rc = bnxt_alloc_tx_rings(bp);
3538 if (rc)
3539 goto alloc_mem_err;
3540
3541 rc = bnxt_alloc_cp_rings(bp);
3542 if (rc)
3543 goto alloc_mem_err;
3544
3545 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3546 BNXT_VNIC_UCAST_FLAG;
3547 rc = bnxt_alloc_vnic_attributes(bp);
3548 if (rc)
3549 goto alloc_mem_err;
3550 return 0;
3551
3552alloc_mem_err:
3553 bnxt_free_mem(bp, true);
3554 return rc;
3555}
3556
9d8bc097
MC		 3557static void bnxt_disable_int(struct bnxt *bp)
3558{
3559 int i;
3560
3561 if (!bp->bnapi)
3562 return;
3563
3564 for (i = 0; i < bp->cp_nr_rings; i++) {
3565 struct bnxt_napi *bnapi = bp->bnapi[i];
3566 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
daf1f1e7 3567 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
9d8bc097 3568
daf1f1e7 3569 if (ring->fw_ring_id != INVALID_HW_RING_ID)
697197e5 3570 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
9d8bc097
MC		 3571 }
3572}
3573
e5811b8c
MC		 3574static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
3575{
3576 struct bnxt_napi *bnapi = bp->bnapi[n];
3577 struct bnxt_cp_ring_info *cpr;
3578
3579 cpr = &bnapi->cp_ring;
3580 return cpr->cp_ring_struct.map_idx;
3581}
3582
9d8bc097
MC		 3583static void bnxt_disable_int_sync(struct bnxt *bp)
3584{
3585 int i;
3586
3587 atomic_inc(&bp->intr_sem);
3588
3589 bnxt_disable_int(bp);
e5811b8c
MC		 3590 for (i = 0; i < bp->cp_nr_rings; i++) {
3591 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
3592
3593 synchronize_irq(bp->irq_tbl[map_idx].vector);
3594 }
9d8bc097
MC		 3595}
3596
3597static void bnxt_enable_int(struct bnxt *bp)
3598{
3599 int i;
3600
3601 atomic_set(&bp->intr_sem, 0);
3602 for (i = 0; i < bp->cp_nr_rings; i++) {
3603 struct bnxt_napi *bnapi = bp->bnapi[i];
3604 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3605
697197e5 3606 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
9d8bc097
MC		 3607 }
3608}
3609
c0c050c5
MC		 3610void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3611 u16 cmpl_ring, u16 target_id)
3612{
a8643e16 3613 struct input *req = request;
c0c050c5 3614
a8643e16
MC		 3615 req->req_type = cpu_to_le16(req_type);
3616 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3617 req->target_id = cpu_to_le16(target_id);
c0c050c5
MC		 3618 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3619}
3620
fbfbc485
MC		 3621static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3622 int timeout, bool silent)
c0c050c5 3623{
a11fa2be 3624 int i, intr_process, rc, tmo_count;
a8643e16 3625 struct input *req = msg;
c0c050c5 3626 u32 *data = msg;
845adfe4
MC		 3627 __le32 *resp_len;
3628 u8 *valid;
c0c050c5
MC		 3629 u16 cp_ring_id, len = 0;
3630 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
e605db80 3631 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
ebd5818c 3632 struct hwrm_short_input short_input = {0};
c0c050c5 3633
a8643e16 3634 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
c0c050c5 3635 memset(resp, 0, PAGE_SIZE);
a8643e16 3636 cp_ring_id = le16_to_cpu(req->cmpl_ring);
c0c050c5
MC		 3637 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3638
1dfddc41
MC		 3639 if (msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3640 if (msg_len > bp->hwrm_max_ext_req_len ||
3641 !bp->hwrm_short_cmd_req_addr)
3642 return -EINVAL;
3643 }
3644
3645 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
3646 msg_len > BNXT_HWRM_MAX_REQ_LEN) {
e605db80 3647 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
1dfddc41
MC		 3648 u16 max_msg_len;
3649
3650 /* Set boundary for maximum extended request length for short
3651 * cmd format. If passed up from device use the max supported
3652 * internal req length.
3653 */
3654 max_msg_len = bp->hwrm_max_ext_req_len;
e605db80
DK		 3655
3656 memcpy(short_cmd_req, req, msg_len);
1dfddc41
MC		 3657 if (msg_len < max_msg_len)
3658 memset(short_cmd_req + msg_len, 0,
3659 max_msg_len - msg_len);
e605db80
DK		 3660
3661 short_input.req_type = req->req_type;
3662 short_input.signature =
3663 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3664 short_input.size = cpu_to_le16(msg_len);
3665 short_input.req_addr =
3666 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3667
3668 data = (u32 *)&short_input;
3669 msg_len = sizeof(short_input);
3670
3671 /* Sync memory write before updating doorbell */
3672 wmb();
3673
3674 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3675 }
3676
c0c050c5
MC		 3677 /* Write request msg to hwrm channel */
3678 __iowrite32_copy(bp->bar0, data, msg_len / 4);
3679
e605db80 3680 for (i = msg_len; i < max_req_len; i += 4)
d79979a1
MC		 3681 writel(0, bp->bar0 + i);
3682
c0c050c5
MC		 3683 /* currently supports only one outstanding message */
3684 if (intr_process)
a8643e16 3685 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
c0c050c5
MC		 3686
3687 /* Ring channel doorbell */
3688 writel(1, bp->bar0 + 0x100);
3689
ff4fe81d
MC		 3690 if (!timeout)
3691 timeout = DFLT_HWRM_CMD_TIMEOUT;
9751e8e7
AG		 3692 /* convert timeout to usec */
3693 timeout *= 1000;
ff4fe81d 3694
c0c050c5 3695 i = 0;
9751e8e7
AG		 3696 /* Short timeout for the first few iterations:
3697 * number of loops = number of loops for short timeout +
3698 * number of loops for standard timeout.
3699 */
3700 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
3701 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
3702 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
845adfe4 3703 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
c0c050c5
MC		 3704 if (intr_process) {
3705 /* Wait until hwrm response cmpl interrupt is processed */
3706 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
a11fa2be 3707 i++ < tmo_count) {
9751e8e7
AG		 3708 /* on first few passes, just barely sleep */
3709 if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3710 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3711 HWRM_SHORT_MAX_TIMEOUT);
3712 else
3713 usleep_range(HWRM_MIN_TIMEOUT,
3714 HWRM_MAX_TIMEOUT);
c0c050c5
MC		 3715 }
3716
3717 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3718 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
a8643e16 3719 le16_to_cpu(req->req_type));
c0c050c5
MC		 3720 return -1;
3721 }
845adfe4
MC		 3722 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3723 HWRM_RESP_LEN_SFT;
3724 valid = bp->hwrm_cmd_resp_addr + len - 1;
c0c050c5 3725 } else {
cc559c1a
MC		 3726 int j;
3727
c0c050c5 3728 /* Check if response len is updated */
a11fa2be 3729 for (i = 0; i < tmo_count; i++) {
c0c050c5
MC		 3730 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3731 HWRM_RESP_LEN_SFT;
3732 if (len)
3733 break;
9751e8e7
AG		 3734 /* on first few passes, just barely sleep */
3735 if (i < DFLT_HWRM_CMD_TIMEOUT)
3736 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3737 HWRM_SHORT_MAX_TIMEOUT);
3738 else
3739 usleep_range(HWRM_MIN_TIMEOUT,
3740 HWRM_MAX_TIMEOUT);
c0c050c5
MC		 3741 }
3742
a11fa2be 3743 if (i >= tmo_count) {
c0c050c5 3744 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
cc559c1a
MC		 3745 HWRM_TOTAL_TIMEOUT(i),
3746 le16_to_cpu(req->req_type),
8578d6c1 3747 le16_to_cpu(req->seq_id), len);
c0c050c5
MC		 3748 return -1;
3749 }
3750
845adfe4
MC		 3751 /* Last byte of resp contains valid bit */
3752 valid = bp->hwrm_cmd_resp_addr + len - 1;
cc559c1a 3753 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
845adfe4
MC		 3754 /* make sure we read from updated DMA memory */
3755 dma_rmb();
3756 if (*valid)
c0c050c5 3757 break;
a11fa2be 3758 udelay(1);
c0c050c5
MC		 3759 }
3760
cc559c1a 3761 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
c0c050c5 3762 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
cc559c1a
MC		 3763 HWRM_TOTAL_TIMEOUT(i),
3764 le16_to_cpu(req->req_type),
a8643e16 3765 le16_to_cpu(req->seq_id), len, *valid);
c0c050c5
MC		 3766 return -1;
3767 }
3768 }
3769
845adfe4
MC		 3770 /* Zero valid bit for compatibility. Valid bit in an older spec
3771 * may become a new field in a newer spec. We must make sure that
3772 * a new field not implemented by old spec will read zero.
3773 */
3774 *valid = 0;
c0c050c5 3775 rc = le16_to_cpu(resp->error_code);
fbfbc485 3776 if (rc && !silent)
c0c050c5
MC		 3777 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3778 le16_to_cpu(resp->req_type),
3779 le16_to_cpu(resp->seq_id), rc);
fbfbc485
MC		 3780 return rc;
3781}
3782
3783int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3784{
3785 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
c0c050c5
MC		 3786}
3787
cc72f3b1
MC		 3788int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3789 int timeout)
3790{
3791 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3792}
3793
c0c050c5
MC		 3794int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3795{
3796 int rc;
3797
3798 mutex_lock(&bp->hwrm_cmd_lock);
3799 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3800 mutex_unlock(&bp->hwrm_cmd_lock);
3801 return rc;
3802}
3803
90e20921
MC		 3804int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3805 int timeout)
3806{
3807 int rc;
3808
3809 mutex_lock(&bp->hwrm_cmd_lock);
3810 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3811 mutex_unlock(&bp->hwrm_cmd_lock);
3812 return rc;
3813}
3814
a1653b13
MC		 3815int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3816 int bmap_size)
c0c050c5
MC		 3817{
3818 struct hwrm_func_drv_rgtr_input req = {0};
25be8623
MC		 3819 DECLARE_BITMAP(async_events_bmap, 256);
3820 u32 *events = (u32 *)async_events_bmap;
a1653b13 3821 int i;
c0c050c5
MC		 3822
3823 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3824
3825 req.enables =
a1653b13 3826 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
c0c050c5 3827
25be8623
MC		 3828 memset(async_events_bmap, 0, sizeof(async_events_bmap));
3829 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3830 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3831
a1653b13
MC		 3832 if (bmap && bmap_size) {
3833 for (i = 0; i < bmap_size; i++) {
3834 if (test_bit(i, bmap))
3835 __set_bit(i, async_events_bmap);
3836 }
3837 }
3838
25be8623
MC		 3839 for (i = 0; i < 8; i++)
3840 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3841
a1653b13
MC		 3842 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3843}
3844
3845static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3846{
25e1acd6 3847 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
a1653b13 3848 struct hwrm_func_drv_rgtr_input req = {0};
25e1acd6 3849 int rc;
a1653b13
MC		 3850
3851 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3852
3853 req.enables =
3854 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3855 FUNC_DRV_RGTR_REQ_ENABLES_VER);
3856
11f15ed3 3857 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
d4f52de0
MC		 3858 req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE);
3859 req.ver_maj_8b = DRV_VER_MAJ;
3860 req.ver_min_8b = DRV_VER_MIN;
3861 req.ver_upd_8b = DRV_VER_UPD;
3862 req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
3863 req.ver_min = cpu_to_le16(DRV_VER_MIN);
3864 req.ver_upd = cpu_to_le16(DRV_VER_UPD);
c0c050c5
MC		 3865
3866 if (BNXT_PF(bp)) {
9b0436c3 3867 u32 data[8];
a1653b13 3868 int i;
c0c050c5 3869
9b0436c3
MC		 3870 memset(data, 0, sizeof(data));
3871 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
3872 u16 cmd = bnxt_vf_req_snif[i];
3873 unsigned int bit, idx;
3874
3875 idx = cmd / 32;
3876 bit = cmd % 32;
3877 data[idx] |= 1 << bit;
3878 }
c0c050c5 3879
de68f5de
MC		 3880 for (i = 0; i < 8; i++)
3881 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3882
c0c050c5
MC		 3883 req.enables |=
3884 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3885 }
3886
25e1acd6
MC		 3887 mutex_lock(&bp->hwrm_cmd_lock);
3888 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3889 if (rc)
3890 rc = -EIO;
3891 else if (resp->flags &
3892 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
3893 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
3894 mutex_unlock(&bp->hwrm_cmd_lock);
3895 return rc;
c0c050c5
MC		 3896}
3897
be58a0da
JH		 3898static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3899{
3900 struct hwrm_func_drv_unrgtr_input req = {0};
3901
3902 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3903 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3904}
3905
c0c050c5
MC		 3906static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3907{
3908 u32 rc = 0;
3909 struct hwrm_tunnel_dst_port_free_input req = {0};
3910
3911 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3912 req.tunnel_type = tunnel_type;
3913
3914 switch (tunnel_type) {
3915 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3916 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3917 break;
3918 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3919 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3920 break;
3921 default:
3922 break;
3923 }
3924
3925 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3926 if (rc)
3927 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3928 rc);
3929 return rc;
3930}
3931
3932static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3933 u8 tunnel_type)
3934{
3935 u32 rc = 0;
3936 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3937 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3938
3939 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3940
3941 req.tunnel_type = tunnel_type;
3942 req.tunnel_dst_port_val = port;
3943
3944 mutex_lock(&bp->hwrm_cmd_lock);
3945 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3946 if (rc) {
3947 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3948 rc);
3949 goto err_out;
3950 }
3951
57aac71b
CJ		 3952 switch (tunnel_type) {
3953 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
c0c050c5 3954 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
57aac71b
CJ		 3955 break;
3956 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
c0c050c5 3957 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
57aac71b
CJ		 3958 break;
3959 default:
3960 break;
3961 }
3962
c0c050c5
MC		 3963err_out:
3964 mutex_unlock(&bp->hwrm_cmd_lock);
3965 return rc;
3966}
3967
3968static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3969{
3970 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3971 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3972
3973 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
c193554e 3974 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
c0c050c5
MC		 3975
3976 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3977 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3978 req.mask = cpu_to_le32(vnic->rx_mask);
3979 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3980}
3981
3982#ifdef CONFIG_RFS_ACCEL
3983static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3984 struct bnxt_ntuple_filter *fltr)
3985{
3986 struct hwrm_cfa_ntuple_filter_free_input req = {0};
3987
3988 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3989 req.ntuple_filter_id = fltr->filter_id;
3990 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3991}
3992
3993#define BNXT_NTP_FLTR_FLAGS \
3994 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3995 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3996 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3997 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3998 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3999 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
4000 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
4001 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
4002 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
4003 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
4004 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
4005 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
4006 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
c193554e 4007 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
c0c050c5 4008
61aad724
MC		 4009#define BNXT_NTP_TUNNEL_FLTR_FLAG \
4010 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
4011
c0c050c5
MC		 4012static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
4013 struct bnxt_ntuple_filter *fltr)
4014{
4015 int rc = 0;
4016 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
4017 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4018 bp->hwrm_cmd_resp_addr;
4019 struct flow_keys *keys = &fltr->fkeys;
4020 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
4021
4022 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
a54c4d74 4023 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
c0c050c5
MC		 4024
4025 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
4026
4027 req.ethertype = htons(ETH_P_IP);
4028 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
c193554e 4029 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
c0c050c5
MC		 4030 req.ip_protocol = keys->basic.ip_proto;
4031
dda0e746
MC		 4032 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
4033 int i;
4034
4035 req.ethertype = htons(ETH_P_IPV6);
4036 req.ip_addr_type =
4037 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
4038 *(struct in6_addr *)&req.src_ipaddr[0] =
4039 keys->addrs.v6addrs.src;
4040 *(struct in6_addr *)&req.dst_ipaddr[0] =
4041 keys->addrs.v6addrs.dst;
4042 for (i = 0; i < 4; i++) {
4043 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4044 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4045 }
4046 } else {
4047 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
4048 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4049 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
4050 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4051 }
61aad724
MC		 4052 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
4053 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
4054 req.tunnel_type =
4055 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
4056 }
c0c050c5
MC		 4057
4058 req.src_port = keys->ports.src;
4059 req.src_port_mask = cpu_to_be16(0xffff);
4060 req.dst_port = keys->ports.dst;
4061 req.dst_port_mask = cpu_to_be16(0xffff);
4062
c193554e 4063 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
c0c050c5
MC		 4064 mutex_lock(&bp->hwrm_cmd_lock);
4065 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4066 if (!rc)
4067 fltr->filter_id = resp->ntuple_filter_id;
4068 mutex_unlock(&bp->hwrm_cmd_lock);
4069 return rc;
4070}
4071#endif
4072
4073static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
4074 u8 *mac_addr)
4075{
4076 u32 rc = 0;
4077 struct hwrm_cfa_l2_filter_alloc_input req = {0};
4078 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4079
4080 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
dc52c6c7
PS		 4081 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
4082 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
4083 req.flags |=
4084 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
c193554e 4085 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
c0c050c5
MC		 4086 req.enables =
4087 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
c193554e 4088 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
c0c050c5
MC		 4089 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
4090 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
4091 req.l2_addr_mask[0] = 0xff;
4092 req.l2_addr_mask[1] = 0xff;
4093 req.l2_addr_mask[2] = 0xff;
4094 req.l2_addr_mask[3] = 0xff;
4095 req.l2_addr_mask[4] = 0xff;
4096 req.l2_addr_mask[5] = 0xff;
4097
4098 mutex_lock(&bp->hwrm_cmd_lock);
4099 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4100 if (!rc)
4101 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
4102 resp->l2_filter_id;
4103 mutex_unlock(&bp->hwrm_cmd_lock);
4104 return rc;
4105}
4106
4107static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
4108{
4109 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
4110 int rc = 0;
4111
4112 /* Any associated ntuple filters will also be cleared by firmware. */
4113 mutex_lock(&bp->hwrm_cmd_lock);
4114 for (i = 0; i < num_of_vnics; i++) {
4115 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4116
4117 for (j = 0; j < vnic->uc_filter_count; j++) {
4118 struct hwrm_cfa_l2_filter_free_input req = {0};
4119
4120 bnxt_hwrm_cmd_hdr_init(bp, &req,
4121 HWRM_CFA_L2_FILTER_FREE, -1, -1);
4122
4123 req.l2_filter_id = vnic->fw_l2_filter_id[j];
4124
4125 rc = _hwrm_send_message(bp, &req, sizeof(req),
4126 HWRM_CMD_TIMEOUT);
4127 }
4128 vnic->uc_filter_count = 0;
4129 }
4130 mutex_unlock(&bp->hwrm_cmd_lock);
4131
4132 return rc;
4133}
4134
4135static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
4136{
4137 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4138 struct hwrm_vnic_tpa_cfg_input req = {0};
4139
3c4fe80b
MC		 4140 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4141 return 0;
4142
c0c050c5
MC		 4143 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
4144
4145 if (tpa_flags) {
4146 u16 mss = bp->dev->mtu - 40;
4147 u32 nsegs, n, segs = 0, flags;
4148
4149 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
4150 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
4151 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
4152 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
4153 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
4154 if (tpa_flags & BNXT_FLAG_GRO)
4155 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
4156
4157 req.flags = cpu_to_le32(flags);
4158
4159 req.enables =
4160 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
c193554e
MC		 4161 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
4162 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
c0c050c5
MC		 4163
4164 /* Number of segs are log2 units, and first packet is not
4165 * included as part of this units.
4166 */
2839f28b
MC		 4167 if (mss <= BNXT_RX_PAGE_SIZE) {
4168 n = BNXT_RX_PAGE_SIZE / mss;
c0c050c5
MC		 4169 nsegs = (MAX_SKB_FRAGS - 1) * n;
4170 } else {
2839f28b
MC		 4171 n = mss / BNXT_RX_PAGE_SIZE;
4172 if (mss & (BNXT_RX_PAGE_SIZE - 1))
c0c050c5
MC		 4173 n++;
4174 nsegs = (MAX_SKB_FRAGS - n) / n;
4175 }
4176
4177 segs = ilog2(nsegs);
4178 req.max_agg_segs = cpu_to_le16(segs);
4179 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
c193554e
MC		 4180
4181 req.min_agg_len = cpu_to_le32(512);
c0c050c5
MC		 4182 }
4183 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4184
4185 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4186}
4187
2c61d211
MC		 4188static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)
4189{
4190 struct bnxt_ring_grp_info *grp_info;
4191
4192 grp_info = &bp->grp_info[ring->grp_idx];
4193 return grp_info->cp_fw_ring_id;
4194}
4195
4196static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
4197{
4198 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4199 struct bnxt_napi *bnapi = rxr->bnapi;
4200 struct bnxt_cp_ring_info *cpr;
4201
4202 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
4203 return cpr->cp_ring_struct.fw_ring_id;
4204 } else {
4205 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
4206 }
4207}
4208
4209static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
4210{
4211 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4212 struct bnxt_napi *bnapi = txr->bnapi;
4213 struct bnxt_cp_ring_info *cpr;
4214
4215 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
4216 return cpr->cp_ring_struct.fw_ring_id;
4217 } else {
4218 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
4219 }
4220}
4221
c0c050c5
MC		 4222static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
4223{
4224 u32 i, j, max_rings;
4225 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4226 struct hwrm_vnic_rss_cfg_input req = {0};
4227
7b3af4f7
MC		 4228 if ((bp->flags & BNXT_FLAG_CHIP_P5) ||
4229 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
c0c050c5
MC		 4230 return 0;
4231
4232 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4233 if (set_rss) {
87da7f79 4234 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
50f011b6 4235 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
dc52c6c7
PS		 4236 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
4237 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4238 max_rings = bp->rx_nr_rings - 1;
4239 else
4240 max_rings = bp->rx_nr_rings;
4241 } else {
c0c050c5 4242 max_rings = 1;
dc52c6c7 4243 }
c0c050c5
MC		 4244
4245 /* Fill the RSS indirection table with ring group ids */
4246 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
4247 if (j == max_rings)
4248 j = 0;
4249 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
4250 }
4251
4252 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4253 req.hash_key_tbl_addr =
4254 cpu_to_le64(vnic->rss_hash_key_dma_addr);
4255 }
94ce9caa 4256 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
c0c050c5
MC		 4257 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4258}
4259
7b3af4f7
MC		 4260static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
4261{
4262 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4263 u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings;
4264 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4265 struct hwrm_vnic_rss_cfg_input req = {0};
4266
4267 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4268 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4269 if (!set_rss) {
4270 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4271 return 0;
4272 }
4273 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4274 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4275 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4276 req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
4277 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
4278 for (i = 0, k = 0; i < nr_ctxs; i++) {
4279 __le16 *ring_tbl = vnic->rss_table;
4280 int rc;
4281
4282 req.ring_table_pair_index = i;
4283 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
4284 for (j = 0; j < 64; j++) {
4285 u16 ring_id;
4286
4287 ring_id = rxr->rx_ring_struct.fw_ring_id;
4288 *ring_tbl++ = cpu_to_le16(ring_id);
4289 ring_id = bnxt_cp_ring_for_rx(bp, rxr);
4290 *ring_tbl++ = cpu_to_le16(ring_id);
4291 rxr++;
4292 k++;
4293 if (k == max_rings) {
4294 k = 0;
4295 rxr = &bp->rx_ring[0];
4296 }
4297 }
4298 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4299 if (rc)
4300 return -EIO;
4301 }
4302 return 0;
4303}
4304
c0c050c5
MC		 4305static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
4306{
4307 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4308 struct hwrm_vnic_plcmodes_cfg_input req = {0};
4309
4310 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
4311 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
4312 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
4313 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
4314 req.enables =
4315 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
4316 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
4317 /* thresholds not implemented in firmware yet */
4318 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
4319 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
4320 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4321 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4322}
4323
94ce9caa
PS		 4324static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
4325 u16 ctx_idx)
c0c050c5
MC		 4326{
4327 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
4328
4329 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
4330 req.rss_cos_lb_ctx_id =
94ce9caa 4331 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
c0c050c5
MC		 4332
4333 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
94ce9caa 4334 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
c0c050c5
MC		 4335}
4336
4337static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
4338{
94ce9caa 4339 int i, j;
c0c050c5
MC		 4340
4341 for (i = 0; i < bp->nr_vnics; i++) {
4342 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4343
94ce9caa
PS		 4344 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
4345 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
4346 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
4347 }
c0c050c5
MC		 4348 }
4349 bp->rsscos_nr_ctxs = 0;
4350}
4351
94ce9caa 4352static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
c0c050c5
MC		 4353{
4354 int rc;
4355 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
4356 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
4357 bp->hwrm_cmd_resp_addr;
4358
4359 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
4360 -1);
4361
4362 mutex_lock(&bp->hwrm_cmd_lock);
4363 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4364 if (!rc)
94ce9caa 4365 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
c0c050c5
MC		 4366 le16_to_cpu(resp->rss_cos_lb_ctx_id);
4367 mutex_unlock(&bp->hwrm_cmd_lock);
4368
4369 return rc;
4370}
4371
abe93ad2
MC		 4372static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
4373{
4374 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
4375 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
4376 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
4377}
4378
a588e458 4379int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
c0c050c5 4380{
b81a90d3 4381 unsigned int ring = 0, grp_idx;
c0c050c5
MC		 4382 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4383 struct hwrm_vnic_cfg_input req = {0};
cf6645f8 4384 u16 def_vlan = 0;
c0c050c5
MC		 4385
4386 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
dc52c6c7 4387
7b3af4f7
MC		 4388 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4389 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4390
4391 req.default_rx_ring_id =
4392 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
4393 req.default_cmpl_ring_id =
4394 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
4395 req.enables =
4396 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
4397 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
4398 goto vnic_mru;
4399 }
dc52c6c7 4400 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
c0c050c5 4401 /* Only RSS support for now TBD: COS & LB */
dc52c6c7
PS		 4402 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4403 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4404 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4405 VNIC_CFG_REQ_ENABLES_MRU);
ae10ae74
MC		 4406 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4407 req.rss_rule =
4408 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4409 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4410 VNIC_CFG_REQ_ENABLES_MRU);
4411 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
dc52c6c7
PS		 4412 } else {
4413 req.rss_rule = cpu_to_le16(0xffff);
4414 }
94ce9caa 4415
dc52c6c7
PS		 4416 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4417 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
94ce9caa
PS		 4418 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4419 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4420 } else {
4421 req.cos_rule = cpu_to_le16(0xffff);
4422 }
4423
c0c050c5 4424 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
b81a90d3 4425 ring = 0;
c0c050c5 4426 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
b81a90d3 4427 ring = vnic_id - 1;
76595193
PS		 4428 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4429 ring = bp->rx_nr_rings - 1;
c0c050c5 4430
b81a90d3 4431 grp_idx = bp->rx_ring[ring].bnapi->index;
c0c050c5 4432 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
c0c050c5 4433 req.lb_rule = cpu_to_le16(0xffff);
7b3af4f7 4434vnic_mru:
c0c050c5
MC		 4435 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4436 VLAN_HLEN);
4437
7b3af4f7 4438 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
cf6645f8
MC		 4439#ifdef CONFIG_BNXT_SRIOV
4440 if (BNXT_VF(bp))
4441 def_vlan = bp->vf.vlan;
4442#endif
4443 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
c0c050c5 4444 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
a588e458 4445 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
abe93ad2 4446 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
c0c050c5
MC		 4447
4448 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4449}
4450
4451static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4452{
4453 u32 rc = 0;
4454
4455 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4456 struct hwrm_vnic_free_input req = {0};
4457
4458 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4459 req.vnic_id =
4460 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4461
4462 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4463 if (rc)
4464 return rc;
4465 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4466 }
4467 return rc;
4468}
4469
4470static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4471{
4472 u16 i;
4473
4474 for (i = 0; i < bp->nr_vnics; i++)
4475 bnxt_hwrm_vnic_free_one(bp, i);
4476}
4477
b81a90d3
MC		 4478static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4479 unsigned int start_rx_ring_idx,
4480 unsigned int nr_rings)
c0c050c5 4481{
b81a90d3
MC		 4482 int rc = 0;
4483 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
c0c050c5
MC		 4484 struct hwrm_vnic_alloc_input req = {0};
4485 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
44c6f72a
MC		 4486 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4487
4488 if (bp->flags & BNXT_FLAG_CHIP_P5)
4489 goto vnic_no_ring_grps;
c0c050c5
MC		 4490
4491 /* map ring groups to this vnic */
b81a90d3
MC		 4492 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4493 grp_idx = bp->rx_ring[i].bnapi->index;
4494 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
c0c050c5 4495 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
b81a90d3 4496 j, nr_rings);
c0c050c5
MC		 4497 break;
4498 }
44c6f72a 4499 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
c0c050c5
MC		 4500 }
4501
44c6f72a
MC		 4502vnic_no_ring_grps:
4503 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
4504 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
c0c050c5
MC		 4505 if (vnic_id == 0)
4506 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4507
4508 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4509
4510 mutex_lock(&bp->hwrm_cmd_lock);
4511 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4512 if (!rc)
44c6f72a 4513 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
c0c050c5
MC		 4514 mutex_unlock(&bp->hwrm_cmd_lock);
4515 return rc;
4516}
4517
8fdefd63
MC		 4518static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4519{
4520 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4521 struct hwrm_vnic_qcaps_input req = {0};
4522 int rc;
4523
4524 if (bp->hwrm_spec_code < 0x10600)
4525 return 0;
4526
4527 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4528 mutex_lock(&bp->hwrm_cmd_lock);
4529 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4530 if (!rc) {
abe93ad2
MC		 4531 u32 flags = le32_to_cpu(resp->flags);
4532
41e8d798
MC		 4533 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
4534 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
8fdefd63 4535 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
abe93ad2
MC		 4536 if (flags &
4537 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
4538 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
8fdefd63
MC		 4539 }
4540 mutex_unlock(&bp->hwrm_cmd_lock);
4541 return rc;
4542}
4543
c0c050c5
MC		 4544static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4545{
4546 u16 i;
4547 u32 rc = 0;
4548
44c6f72a
MC		 4549 if (bp->flags & BNXT_FLAG_CHIP_P5)
4550 return 0;
4551
c0c050c5
MC		 4552 mutex_lock(&bp->hwrm_cmd_lock);
4553 for (i = 0; i < bp->rx_nr_rings; i++) {
4554 struct hwrm_ring_grp_alloc_input req = {0};
4555 struct hwrm_ring_grp_alloc_output *resp =
4556 bp->hwrm_cmd_resp_addr;
b81a90d3 4557 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
c0c050c5
MC		 4558
4559 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4560
b81a90d3
MC		 4561 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4562 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4563 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4564 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
c0c050c5
MC		 4565
4566 rc = _hwrm_send_message(bp, &req, sizeof(req),
4567 HWRM_CMD_TIMEOUT);
4568 if (rc)
4569 break;
4570
b81a90d3
MC		 4571 bp->grp_info[grp_idx].fw_grp_id =
4572 le32_to_cpu(resp->ring_group_id);
c0c050c5
MC		 4573 }
4574 mutex_unlock(&bp->hwrm_cmd_lock);
4575 return rc;
4576}
4577
4578static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4579{
4580 u16 i;
4581 u32 rc = 0;
4582 struct hwrm_ring_grp_free_input req = {0};
4583
44c6f72a 4584 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5))
c0c050c5
MC		 4585 return 0;
4586
4587 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4588
4589 mutex_lock(&bp->hwrm_cmd_lock);
4590 for (i = 0; i < bp->cp_nr_rings; i++) {
4591 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4592 continue;
4593 req.ring_group_id =
4594 cpu_to_le32(bp->grp_info[i].fw_grp_id);
4595
4596 rc = _hwrm_send_message(bp, &req, sizeof(req),
4597 HWRM_CMD_TIMEOUT);
4598 if (rc)
4599 break;
4600 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4601 }
4602 mutex_unlock(&bp->hwrm_cmd_lock);
4603 return rc;
4604}
4605
4606static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4607 struct bnxt_ring_struct *ring,
9899bb59 4608 u32 ring_type, u32 map_index)
c0c050c5
MC		 4609{
4610 int rc = 0, err = 0;
4611 struct hwrm_ring_alloc_input req = {0};
4612 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6fe19886 4613 struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
9899bb59 4614 struct bnxt_ring_grp_info *grp_info;
c0c050c5
MC		 4615 u16 ring_id;
4616
4617 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4618
4619 req.enables = 0;
6fe19886
MC		 4620 if (rmem->nr_pages > 1) {
4621 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
c0c050c5
MC		 4622 /* Page size is in log2 units */
4623 req.page_size = BNXT_PAGE_SHIFT;
4624 req.page_tbl_depth = 1;
4625 } else {
6fe19886 4626 req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]);
c0c050c5
MC		 4627 }
4628 req.fbo = 0;
4629 /* Association of ring index with doorbell index and MSIX number */
4630 req.logical_id = cpu_to_le16(map_index);
4631
4632 switch (ring_type) {
2c61d211
MC		 4633 case HWRM_RING_ALLOC_TX: {
4634 struct bnxt_tx_ring_info *txr;
4635
4636 txr = container_of(ring, struct bnxt_tx_ring_info,
4637 tx_ring_struct);
c0c050c5
MC		 4638 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4639 /* Association of transmit ring with completion ring */
9899bb59 4640 grp_info = &bp->grp_info[ring->grp_idx];
2c61d211 4641 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
c0c050c5 4642 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
9899bb59 4643 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
c0c050c5
MC		 4644 req.queue_id = cpu_to_le16(ring->queue_id);
4645 break;
2c61d211 4646 }
c0c050c5
MC		 4647 case HWRM_RING_ALLOC_RX:
4648 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4649 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
23aefdd7
MC		 4650 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4651 u16 flags = 0;
4652
4653 /* Association of rx ring with stats context */
4654 grp_info = &bp->grp_info[ring->grp_idx];
4655 req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
4656 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4657 req.enables |= cpu_to_le32(
4658 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4659 if (NET_IP_ALIGN == 2)
4660 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
4661 req.flags = cpu_to_le16(flags);
4662 }
c0c050c5
MC		 4663 break;
4664 case HWRM_RING_ALLOC_AGG:
23aefdd7
MC		 4665 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4666 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
4667 /* Association of agg ring with rx ring */
4668 grp_info = &bp->grp_info[ring->grp_idx];
4669 req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
4670 req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
4671 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4672 req.enables |= cpu_to_le32(
4673 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
4674 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4675 } else {
4676 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4677 }
c0c050c5
MC		 4678 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4679 break;
4680 case HWRM_RING_ALLOC_CMPL:
bac9a7e0 4681 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
c0c050c5 4682 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
23aefdd7
MC		 4683 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4684 /* Association of cp ring with nq */
4685 grp_info = &bp->grp_info[map_index];
4686 req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
4687 req.cq_handle = cpu_to_le64(ring->handle);
4688 req.enables |= cpu_to_le32(
4689 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
4690 } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
4691 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4692 }
4693 break;
4694 case HWRM_RING_ALLOC_NQ:
4695 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
4696 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
c0c050c5
MC		 4697 if (bp->flags & BNXT_FLAG_USING_MSIX)
4698 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4699 break;
4700 default:
4701 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4702 ring_type);
4703 return -1;
4704 }
4705
4706 mutex_lock(&bp->hwrm_cmd_lock);
4707 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4708 err = le16_to_cpu(resp->error_code);
4709 ring_id = le16_to_cpu(resp->ring_id);
4710 mutex_unlock(&bp->hwrm_cmd_lock);
4711
4712 if (rc || err) {
2727c888
MC		 4713 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
4714 ring_type, rc, err);
4715 return -EIO;
c0c050c5
MC		 4716 }
4717 ring->fw_ring_id = ring_id;
4718 return rc;
4719}
4720
486b5c22
MC		 4721static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4722{
4723 int rc;
4724
4725 if (BNXT_PF(bp)) {
4726 struct hwrm_func_cfg_input req = {0};
4727
4728 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4729 req.fid = cpu_to_le16(0xffff);
4730 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4731 req.async_event_cr = cpu_to_le16(idx);
4732 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4733 } else {
4734 struct hwrm_func_vf_cfg_input req = {0};
4735
4736 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4737 req.enables =
4738 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4739 req.async_event_cr = cpu_to_le16(idx);
4740 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4741 }
4742 return rc;
4743}
4744
697197e5
MC		 4745static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
4746 u32 map_idx, u32 xid)
4747{
4748 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4749 if (BNXT_PF(bp))
4750 db->doorbell = bp->bar1 + 0x10000;
4751 else
4752 db->doorbell = bp->bar1 + 0x4000;
4753 switch (ring_type) {
4754 case HWRM_RING_ALLOC_TX:
4755 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
4756 break;
4757 case HWRM_RING_ALLOC_RX:
4758 case HWRM_RING_ALLOC_AGG:
4759 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
4760 break;
4761 case HWRM_RING_ALLOC_CMPL:
4762 db->db_key64 = DBR_PATH_L2;
4763 break;
4764 case HWRM_RING_ALLOC_NQ:
4765 db->db_key64 = DBR_PATH_L2;
4766 break;
4767 }
4768 db->db_key64 |= (u64)xid << DBR_XID_SFT;
4769 } else {
4770 db->doorbell = bp->bar1 + map_idx * 0x80;
4771 switch (ring_type) {
4772 case HWRM_RING_ALLOC_TX:
4773 db->db_key32 = DB_KEY_TX;
4774 break;
4775 case HWRM_RING_ALLOC_RX:
4776 case HWRM_RING_ALLOC_AGG:
4777 db->db_key32 = DB_KEY_RX;
4778 break;
4779 case HWRM_RING_ALLOC_CMPL:
4780 db->db_key32 = DB_KEY_CP;
4781 break;
4782 }
4783 }
4784}
4785
c0c050c5
MC		 4786static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4787{
4788 int i, rc = 0;
697197e5 4789 u32 type;
c0c050c5 4790
23aefdd7
MC		 4791 if (bp->flags & BNXT_FLAG_CHIP_P5)
4792 type = HWRM_RING_ALLOC_NQ;
4793 else
4794 type = HWRM_RING_ALLOC_CMPL;
edd0c2cc
MC		 4795 for (i = 0; i < bp->cp_nr_rings; i++) {
4796 struct bnxt_napi *bnapi = bp->bnapi[i];
4797 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4798 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
9899bb59 4799 u32 map_idx = ring->map_idx;
c0c050c5 4800
697197e5 4801 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
edd0c2cc
MC		 4802 if (rc)
4803 goto err_out;
697197e5
MC		 4804 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
4805 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
edd0c2cc 4806 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
486b5c22
MC		 4807
4808 if (!i) {
4809 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4810 if (rc)
4811 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4812 }
c0c050c5
MC		 4813 }
4814
697197e5 4815 type = HWRM_RING_ALLOC_TX;
edd0c2cc 4816 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 4817 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3e08b184
MC		 4818 struct bnxt_ring_struct *ring;
4819 u32 map_idx;
c0c050c5 4820
3e08b184
MC		 4821 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4822 struct bnxt_napi *bnapi = txr->bnapi;
4823 struct bnxt_cp_ring_info *cpr, *cpr2;
4824 u32 type2 = HWRM_RING_ALLOC_CMPL;
4825
4826 cpr = &bnapi->cp_ring;
4827 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
4828 ring = &cpr2->cp_ring_struct;
4829 ring->handle = BNXT_TX_HDL;
4830 map_idx = bnapi->index;
4831 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
4832 if (rc)
4833 goto err_out;
4834 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
4835 ring->fw_ring_id);
4836 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
4837 }
4838 ring = &txr->tx_ring_struct;
4839 map_idx = i;
697197e5 4840 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
edd0c2cc
MC		 4841 if (rc)
4842 goto err_out;
697197e5 4843 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
c0c050c5
MC		 4844 }
4845
697197e5 4846 type = HWRM_RING_ALLOC_RX;
edd0c2cc 4847 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4848 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 4849 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3e08b184
MC		 4850 struct bnxt_napi *bnapi = rxr->bnapi;
4851 u32 map_idx = bnapi->index;
c0c050c5 4852
697197e5 4853 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
edd0c2cc
MC		 4854 if (rc)
4855 goto err_out;
697197e5
MC		 4856 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
4857 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
b81a90d3 4858 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
3e08b184
MC		 4859 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4860 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4861 u32 type2 = HWRM_RING_ALLOC_CMPL;
4862 struct bnxt_cp_ring_info *cpr2;
4863
4864 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
4865 ring = &cpr2->cp_ring_struct;
4866 ring->handle = BNXT_RX_HDL;
4867 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
4868 if (rc)
4869 goto err_out;
4870 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
4871 ring->fw_ring_id);
4872 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
4873 }
c0c050c5
MC		 4874 }
4875
4876 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
697197e5 4877 type = HWRM_RING_ALLOC_AGG;
c0c050c5 4878 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4879 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 4880 struct bnxt_ring_struct *ring =
4881 &rxr->rx_agg_ring_struct;
9899bb59 4882 u32 grp_idx = ring->grp_idx;
b81a90d3 4883 u32 map_idx = grp_idx + bp->rx_nr_rings;
c0c050c5 4884
697197e5 4885 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
c0c050c5
MC		 4886 if (rc)
4887 goto err_out;
4888
697197e5
MC		 4889 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
4890 ring->fw_ring_id);
4891 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
b81a90d3 4892 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 4893 }
4894 }
4895err_out:
4896 return rc;
4897}
4898
4899static int hwrm_ring_free_send_msg(struct bnxt *bp,
4900 struct bnxt_ring_struct *ring,
4901 u32 ring_type, int cmpl_ring_id)
4902{
4903 int rc;
4904 struct hwrm_ring_free_input req = {0};
4905 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4906 u16 error_code;
4907
74608fc9 4908 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
c0c050c5
MC		 4909 req.ring_type = ring_type;
4910 req.ring_id = cpu_to_le16(ring->fw_ring_id);
4911
4912 mutex_lock(&bp->hwrm_cmd_lock);
4913 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4914 error_code = le16_to_cpu(resp->error_code);
4915 mutex_unlock(&bp->hwrm_cmd_lock);
4916
4917 if (rc || error_code) {
2727c888
MC		 4918 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
4919 ring_type, rc, error_code);
4920 return -EIO;
c0c050c5
MC		 4921 }
4922 return 0;
4923}
4924
edd0c2cc 4925static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
c0c050c5 4926{
23aefdd7 4927 u32 type;
edd0c2cc 4928 int i;
c0c050c5
MC		 4929
4930 if (!bp->bnapi)
edd0c2cc 4931 return;
c0c050c5 4932
edd0c2cc 4933 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 4934 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 4935 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2c61d211 4936 u32 cmpl_ring_id;
edd0c2cc 4937
2c61d211 4938 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
edd0c2cc
MC		 4939 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4940 hwrm_ring_free_send_msg(bp, ring,
4941 RING_FREE_REQ_RING_TYPE_TX,
4942 close_path ? cmpl_ring_id :
4943 INVALID_HW_RING_ID);
4944 ring->fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 4945 }
4946 }
4947
edd0c2cc 4948 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4949 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 4950 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3 4951 u32 grp_idx = rxr->bnapi->index;
2c61d211 4952 u32 cmpl_ring_id;
edd0c2cc 4953
2c61d211 4954 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
edd0c2cc
MC		 4955 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4956 hwrm_ring_free_send_msg(bp, ring,
4957 RING_FREE_REQ_RING_TYPE_RX,
4958 close_path ? cmpl_ring_id :
4959 INVALID_HW_RING_ID);
4960 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 4961 bp->grp_info[grp_idx].rx_fw_ring_id =
4962 INVALID_HW_RING_ID;
c0c050c5
MC		 4963 }
4964 }
4965
23aefdd7
MC		 4966 if (bp->flags & BNXT_FLAG_CHIP_P5)
4967 type = RING_FREE_REQ_RING_TYPE_RX_AGG;
4968 else
4969 type = RING_FREE_REQ_RING_TYPE_RX;
edd0c2cc 4970 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4971 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 4972 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
b81a90d3 4973 u32 grp_idx = rxr->bnapi->index;
2c61d211 4974 u32 cmpl_ring_id;
edd0c2cc 4975
2c61d211 4976 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
edd0c2cc 4977 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
23aefdd7 4978 hwrm_ring_free_send_msg(bp, ring, type,
edd0c2cc
MC		 4979 close_path ? cmpl_ring_id :
4980 INVALID_HW_RING_ID);
4981 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 4982 bp->grp_info[grp_idx].agg_fw_ring_id =
4983 INVALID_HW_RING_ID;
c0c050c5
MC		 4984 }
4985 }
4986
9d8bc097
MC		 4987 /* The completion rings are about to be freed. After that the
4988 * IRQ doorbell will not work anymore. So we need to disable
4989 * IRQ here.
4990 */
4991 bnxt_disable_int_sync(bp);
4992
23aefdd7
MC		 4993 if (bp->flags & BNXT_FLAG_CHIP_P5)
4994 type = RING_FREE_REQ_RING_TYPE_NQ;
4995 else
4996 type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
edd0c2cc
MC		 4997 for (i = 0; i < bp->cp_nr_rings; i++) {
4998 struct bnxt_napi *bnapi = bp->bnapi[i];
4999 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3e08b184
MC		 5000 struct bnxt_ring_struct *ring;
5001 int j;
edd0c2cc 5002
3e08b184
MC		 5003 for (j = 0; j < 2; j++) {
5004 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
5005
5006 if (cpr2) {
5007 ring = &cpr2->cp_ring_struct;
5008 if (ring->fw_ring_id == INVALID_HW_RING_ID)
5009 continue;
5010 hwrm_ring_free_send_msg(bp, ring,
5011 RING_FREE_REQ_RING_TYPE_L2_CMPL,
5012 INVALID_HW_RING_ID);
5013 ring->fw_ring_id = INVALID_HW_RING_ID;
5014 }
5015 }
5016 ring = &cpr->cp_ring_struct;
edd0c2cc 5017 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
23aefdd7 5018 hwrm_ring_free_send_msg(bp, ring, type,
edd0c2cc
MC		 5019 INVALID_HW_RING_ID);
5020 ring->fw_ring_id = INVALID_HW_RING_ID;
5021 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 5022 }
5023 }
c0c050c5
MC		 5024}
5025
41e8d798
MC		 5026static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5027 bool shared);
5028
674f50a5
MC		 5029static int bnxt_hwrm_get_rings(struct bnxt *bp)
5030{
5031 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5032 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5033 struct hwrm_func_qcfg_input req = {0};
5034 int rc;
5035
5036 if (bp->hwrm_spec_code < 0x10601)
5037 return 0;
5038
5039 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5040 req.fid = cpu_to_le16(0xffff);
5041 mutex_lock(&bp->hwrm_cmd_lock);
5042 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5043 if (rc) {
5044 mutex_unlock(&bp->hwrm_cmd_lock);
5045 return -EIO;
5046 }
5047
5048 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
f1ca94de 5049 if (BNXT_NEW_RM(bp)) {
674f50a5
MC		 5050 u16 cp, stats;
5051
5052 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
5053 hw_resc->resv_hw_ring_grps =
5054 le32_to_cpu(resp->alloc_hw_ring_grps);
5055 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
5056 cp = le16_to_cpu(resp->alloc_cmpl_rings);
5057 stats = le16_to_cpu(resp->alloc_stat_ctx);
5058 cp = min_t(u16, cp, stats);
41e8d798
MC		 5059 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5060 int rx = hw_resc->resv_rx_rings;
5061 int tx = hw_resc->resv_tx_rings;
5062
5063 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5064 rx >>= 1;
5065 if (cp < (rx + tx)) {
5066 bnxt_trim_rings(bp, &rx, &tx, cp, false);
5067 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5068 rx <<= 1;
5069 hw_resc->resv_rx_rings = rx;
5070 hw_resc->resv_tx_rings = tx;
5071 }
5072 cp = le16_to_cpu(resp->alloc_msix);
5073 hw_resc->resv_hw_ring_grps = rx;
5074 }
674f50a5
MC		 5075 hw_resc->resv_cp_rings = cp;
5076 }
5077 mutex_unlock(&bp->hwrm_cmd_lock);
5078 return 0;
5079}
5080
391be5c2
MC		 5081/* Caller must hold bp->hwrm_cmd_lock */
5082int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
5083{
5084 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5085 struct hwrm_func_qcfg_input req = {0};
5086 int rc;
5087
5088 if (bp->hwrm_spec_code < 0x10601)
5089 return 0;
5090
5091 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5092 req.fid = cpu_to_le16(fid);
5093 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5094 if (!rc)
5095 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5096
5097 return rc;
5098}
5099
41e8d798
MC		 5100static bool bnxt_rfs_supported(struct bnxt *bp);
5101
4ed50ef4
MC		 5102static void
5103__bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
5104 int tx_rings, int rx_rings, int ring_grps,
5105 int cp_rings, int vnics)
391be5c2 5106{
674f50a5 5107 u32 enables = 0;
391be5c2 5108
4ed50ef4
MC		 5109 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
5110 req->fid = cpu_to_le16(0xffff);
674f50a5 5111 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
4ed50ef4 5112 req->num_tx_rings = cpu_to_le16(tx_rings);
f1ca94de 5113 if (BNXT_NEW_RM(bp)) {
674f50a5 5114 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
41e8d798
MC		 5115 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5116 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
5117 enables |= tx_rings + ring_grps ?
5118 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5119 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5120 enables |= rx_rings ?
5121 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5122 } else {
5123 enables |= cp_rings ?
5124 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5125 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5126 enables |= ring_grps ?
5127 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
5128 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5129 }
dbe80d44 5130 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
674f50a5 5131
4ed50ef4 5132 req->num_rx_rings = cpu_to_le16(rx_rings);
41e8d798
MC		 5133 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5134 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5135 req->num_msix = cpu_to_le16(cp_rings);
5136 req->num_rsscos_ctxs =
5137 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5138 } else {
5139 req->num_cmpl_rings = cpu_to_le16(cp_rings);
5140 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5141 req->num_rsscos_ctxs = cpu_to_le16(1);
5142 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
5143 bnxt_rfs_supported(bp))
5144 req->num_rsscos_ctxs =
5145 cpu_to_le16(ring_grps + 1);
5146 }
4ed50ef4
MC		 5147 req->num_stat_ctxs = req->num_cmpl_rings;
5148 req->num_vnics = cpu_to_le16(vnics);
674f50a5 5149 }
4ed50ef4
MC		 5150 req->enables = cpu_to_le32(enables);
5151}
5152
5153static void
5154__bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
5155 struct hwrm_func_vf_cfg_input *req, int tx_rings,
5156 int rx_rings, int ring_grps, int cp_rings,
5157 int vnics)
5158{
5159 u32 enables = 0;
5160
5161 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
5162 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
41e8d798
MC		 5163 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
5164 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5165 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5166 enables |= tx_rings + ring_grps ?
5167 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5168 FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5169 } else {
5170 enables |= cp_rings ?
5171 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5172 FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5173 enables |= ring_grps ?
5174 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
5175 }
4ed50ef4 5176 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
41e8d798 5177 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
4ed50ef4 5178
41e8d798 5179 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
4ed50ef4
MC		 5180 req->num_tx_rings = cpu_to_le16(tx_rings);
5181 req->num_rx_rings = cpu_to_le16(rx_rings);
41e8d798
MC		 5182 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5183 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5184 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5185 } else {
5186 req->num_cmpl_rings = cpu_to_le16(cp_rings);
5187 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5188 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
5189 }
4ed50ef4
MC		 5190 req->num_stat_ctxs = req->num_cmpl_rings;
5191 req->num_vnics = cpu_to_le16(vnics);
5192
5193 req->enables = cpu_to_le32(enables);
5194}
5195
5196static int
5197bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5198 int ring_grps, int cp_rings, int vnics)
5199{
5200 struct hwrm_func_cfg_input req = {0};
5201 int rc;
5202
5203 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5204 cp_rings, vnics);
5205 if (!req.enables)
391be5c2
MC		 5206 return 0;
5207
674f50a5
MC		 5208 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5209 if (rc)
5210 return -ENOMEM;
5211
5212 if (bp->hwrm_spec_code < 0x10601)
5213 bp->hw_resc.resv_tx_rings = tx_rings;
5214
5215 rc = bnxt_hwrm_get_rings(bp);
5216 return rc;
5217}
5218
5219static int
5220bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5221 int ring_grps, int cp_rings, int vnics)
5222{
5223 struct hwrm_func_vf_cfg_input req = {0};
674f50a5
MC		 5224 int rc;
5225
f1ca94de 5226 if (!BNXT_NEW_RM(bp)) {
674f50a5 5227 bp->hw_resc.resv_tx_rings = tx_rings;
391be5c2 5228 return 0;
674f50a5 5229 }
391be5c2 5230
4ed50ef4
MC		 5231 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5232 cp_rings, vnics);
391be5c2 5233 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
674f50a5
MC		 5234 if (rc)
5235 return -ENOMEM;
5236
5237 rc = bnxt_hwrm_get_rings(bp);
5238 return rc;
5239}
5240
5241static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
5242 int cp, int vnic)
5243{
5244 if (BNXT_PF(bp))
5245 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, vnic);
5246 else
5247 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, vnic);
5248}
5249
08654eb2
MC		 5250static int bnxt_cp_rings_in_use(struct bnxt *bp)
5251{
5252 int cp = bp->cp_nr_rings;
5253 int ulp_msix, ulp_base;
5254
5255 ulp_msix = bnxt_get_ulp_msix_num(bp);
5256 if (ulp_msix) {
5257 ulp_base = bnxt_get_ulp_msix_base(bp);
5258 cp += ulp_msix;
5259 if ((ulp_base + ulp_msix) > cp)
5260 cp = ulp_base + ulp_msix;
5261 }
5262 return cp;
5263}
5264
4e41dc5d
MC		 5265static bool bnxt_need_reserve_rings(struct bnxt *bp)
5266{
5267 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
fbcfc8e4 5268 int cp = bnxt_cp_rings_in_use(bp);
4e41dc5d
MC		 5269 int rx = bp->rx_nr_rings;
5270 int vnic = 1, grp = rx;
5271
5272 if (bp->hwrm_spec_code < 0x10601)
5273 return false;
5274
5275 if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
5276 return true;
5277
41e8d798 5278 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
4e41dc5d
MC		 5279 vnic = rx + 1;
5280 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5281 rx <<= 1;
f1ca94de 5282 if (BNXT_NEW_RM(bp) &&
4e41dc5d 5283 (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
41e8d798
MC		 5284 hw_resc->resv_vnics != vnic ||
5285 (hw_resc->resv_hw_ring_grps != grp &&
5286 !(bp->flags & BNXT_FLAG_CHIP_P5))))
4e41dc5d
MC		 5287 return true;
5288 return false;
5289}
5290
674f50a5
MC		 5291static int __bnxt_reserve_rings(struct bnxt *bp)
5292{
5293 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
fbcfc8e4 5294 int cp = bnxt_cp_rings_in_use(bp);
674f50a5
MC		 5295 int tx = bp->tx_nr_rings;
5296 int rx = bp->rx_nr_rings;
674f50a5
MC		 5297 int grp, rx_rings, rc;
5298 bool sh = false;
5299 int vnic = 1;
5300
4e41dc5d 5301 if (!bnxt_need_reserve_rings(bp))
674f50a5
MC		 5302 return 0;
5303
5304 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5305 sh = true;
41e8d798 5306 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
674f50a5
MC		 5307 vnic = rx + 1;
5308 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5309 rx <<= 1;
674f50a5 5310 grp = bp->rx_nr_rings;
674f50a5
MC		 5311
5312 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, vnic);
391be5c2
MC		 5313 if (rc)
5314 return rc;
5315
674f50a5 5316 tx = hw_resc->resv_tx_rings;
f1ca94de 5317 if (BNXT_NEW_RM(bp)) {
674f50a5
MC		 5318 rx = hw_resc->resv_rx_rings;
5319 cp = hw_resc->resv_cp_rings;
5320 grp = hw_resc->resv_hw_ring_grps;
5321 vnic = hw_resc->resv_vnics;
5322 }
5323
5324 rx_rings = rx;
5325 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5326 if (rx >= 2) {
5327 rx_rings = rx >> 1;
5328 } else {
5329 if (netif_running(bp->dev))
5330 return -ENOMEM;
5331
5332 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
5333 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
5334 bp->dev->hw_features &= ~NETIF_F_LRO;
5335 bp->dev->features &= ~NETIF_F_LRO;
5336 bnxt_set_ring_params(bp);
5337 }
5338 }
5339 rx_rings = min_t(int, rx_rings, grp);
5340 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
5341 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5342 rx = rx_rings << 1;
5343 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
5344 bp->tx_nr_rings = tx;
5345 bp->rx_nr_rings = rx_rings;
5346 bp->cp_nr_rings = cp;
5347
5348 if (!tx || !rx || !cp || !grp || !vnic)
5349 return -ENOMEM;
5350
391be5c2
MC		 5351 return rc;
5352}
5353
8f23d638 5354static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6fc2ffdf 5355 int ring_grps, int cp_rings, int vnics)
98fdbe73 5356{
8f23d638 5357 struct hwrm_func_vf_cfg_input req = {0};
6fc2ffdf 5358 u32 flags;
98fdbe73
MC		 5359 int rc;
5360
f1ca94de 5361 if (!BNXT_NEW_RM(bp))
98fdbe73
MC		 5362 return 0;
5363
6fc2ffdf
EW		 5364 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5365 cp_rings, vnics);
8f23d638
MC		 5366 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
5367 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5368 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
8f23d638 5369 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
41e8d798
MC		 5370 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
5371 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
5372 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5373 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
8f23d638
MC		 5374
5375 req.flags = cpu_to_le32(flags);
8f23d638
MC		 5376 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5377 if (rc)
5378 return -ENOMEM;
5379 return 0;
5380}
5381
5382static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6fc2ffdf 5383 int ring_grps, int cp_rings, int vnics)
8f23d638
MC		 5384{
5385 struct hwrm_func_cfg_input req = {0};
6fc2ffdf 5386 u32 flags;
8f23d638 5387 int rc;
98fdbe73 5388
6fc2ffdf
EW		 5389 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5390 cp_rings, vnics);
8f23d638 5391 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
41e8d798 5392 if (BNXT_NEW_RM(bp)) {
8f23d638
MC		 5393 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5394 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
8f23d638
MC		 5395 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5396 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
41e8d798
MC		 5397 if (bp->flags & BNXT_FLAG_CHIP_P5)
5398 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
5399 else
5400 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5401 }
6fc2ffdf 5402
8f23d638 5403 req.flags = cpu_to_le32(flags);
98fdbe73
MC		 5404 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5405 if (rc)
5406 return -ENOMEM;
5407 return 0;
5408}
5409
8f23d638 5410static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6fc2ffdf 5411 int ring_grps, int cp_rings, int vnics)
8f23d638
MC		 5412{
5413 if (bp->hwrm_spec_code < 0x10801)
5414 return 0;
5415
5416 if (BNXT_PF(bp))
5417 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
6fc2ffdf 5418 ring_grps, cp_rings, vnics);
8f23d638
MC		 5419
5420 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
6fc2ffdf 5421 cp_rings, vnics);
8f23d638
MC		 5422}
5423
74706afa
MC		 5424static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
5425{
5426 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5427 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5428 struct hwrm_ring_aggint_qcaps_input req = {0};
5429 int rc;
5430
5431 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
5432 coal_cap->num_cmpl_dma_aggr_max = 63;
5433 coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
5434 coal_cap->cmpl_aggr_dma_tmr_max = 65535;
5435 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
5436 coal_cap->int_lat_tmr_min_max = 65535;
5437 coal_cap->int_lat_tmr_max_max = 65535;
5438 coal_cap->num_cmpl_aggr_int_max = 65535;
5439 coal_cap->timer_units = 80;
5440
5441 if (bp->hwrm_spec_code < 0x10902)
5442 return;
5443
5444 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1);
5445 mutex_lock(&bp->hwrm_cmd_lock);
5446 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5447 if (!rc) {
5448 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
58590c8d 5449 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
74706afa
MC		 5450 coal_cap->num_cmpl_dma_aggr_max =
5451 le16_to_cpu(resp->num_cmpl_dma_aggr_max);
5452 coal_cap->num_cmpl_dma_aggr_during_int_max =
5453 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
5454 coal_cap->cmpl_aggr_dma_tmr_max =
5455 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
5456 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
5457 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
5458 coal_cap->int_lat_tmr_min_max =
5459 le16_to_cpu(resp->int_lat_tmr_min_max);
5460 coal_cap->int_lat_tmr_max_max =
5461 le16_to_cpu(resp->int_lat_tmr_max_max);
5462 coal_cap->num_cmpl_aggr_int_max =
5463 le16_to_cpu(resp->num_cmpl_aggr_int_max);
5464 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
5465 }
5466 mutex_unlock(&bp->hwrm_cmd_lock);
5467}
5468
5469static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
5470{
5471 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5472
5473 return usec * 1000 / coal_cap->timer_units;
5474}
5475
5476static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
5477 struct bnxt_coal *hw_coal,
bb053f52
MC		 5478 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5479{
74706afa
MC		 5480 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5481 u32 cmpl_params = coal_cap->cmpl_params;
5482 u16 val, tmr, max, flags = 0;
f8503969
MC		 5483
5484 max = hw_coal->bufs_per_record * 128;
5485 if (hw_coal->budget)
5486 max = hw_coal->bufs_per_record * hw_coal->budget;
74706afa 5487 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
f8503969
MC		 5488
5489 val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
5490 req->num_cmpl_aggr_int = cpu_to_le16(val);
b153cbc5 5491
74706afa 5492 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
f8503969
MC		 5493 req->num_cmpl_dma_aggr = cpu_to_le16(val);
5494
74706afa
MC		 5495 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
5496 coal_cap->num_cmpl_dma_aggr_during_int_max);
f8503969
MC		 5497 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
5498
74706afa
MC		 5499 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
5500 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
f8503969
MC		 5501 req->int_lat_tmr_max = cpu_to_le16(tmr);
5502
5503 /* min timer set to 1/2 of interrupt timer */
74706afa
MC		 5504 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
5505 val = tmr / 2;
5506 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
5507 req->int_lat_tmr_min = cpu_to_le16(val);
5508 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5509 }
f8503969
MC		 5510
5511 /* buf timer set to 1/4 of interrupt timer */
74706afa 5512 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
f8503969
MC		 5513 req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
5514
74706afa
MC		 5515 if (cmpl_params &
5516 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
5517 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
5518 val = clamp_t(u16, tmr, 1,
5519 coal_cap->cmpl_aggr_dma_tmr_during_int_max);
5520 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
5521 req->enables |=
5522 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
5523 }
f8503969 5524
74706afa
MC		 5525 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
5526 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
5527 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
5528 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
f8503969 5529 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
bb053f52 5530 req->flags = cpu_to_le16(flags);
74706afa 5531 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
bb053f52
MC		 5532}
5533
58590c8d
MC		 5534/* Caller holds bp->hwrm_cmd_lock */
5535static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi,
5536 struct bnxt_coal *hw_coal)
5537{
5538 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5539 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5540 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5541 u32 nq_params = coal_cap->nq_params;
5542 u16 tmr;
5543
5544 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
5545 return 0;
5546
5547 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5548 -1, -1);
5549 req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
5550 req.flags =
5551 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
5552
5553 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
5554 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
5555 req.int_lat_tmr_min = cpu_to_le16(tmr);
5556 req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5557 return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5558}
5559
6a8788f2
AG		 5560int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
5561{
5562 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
5563 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5564 struct bnxt_coal coal;
6a8788f2
AG		 5565
5566 /* Tick values in micro seconds.
5567 * 1 coal_buf x bufs_per_record = 1 completion record.
5568 */
5569 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
5570
5571 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
5572 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
5573
5574 if (!bnapi->rx_ring)
5575 return -ENODEV;
5576
5577 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5578 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5579
74706afa 5580 bnxt_hwrm_set_coal_params(bp, &coal, &req_rx);
6a8788f2 5581
2c61d211 5582 req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
6a8788f2
AG		 5583
5584 return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
5585 HWRM_CMD_TIMEOUT);
5586}
5587
c0c050c5
MC		 5588int bnxt_hwrm_set_coal(struct bnxt *bp)
5589{
5590 int i, rc = 0;
dfc9c94a
MC		 5591 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
5592 req_tx = {0}, *req;
c0c050c5 5593
dfc9c94a
MC		 5594 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5595 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5596 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
5597 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
c0c050c5 5598
74706afa
MC		 5599 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx);
5600 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx);
c0c050c5
MC		 5601
5602 mutex_lock(&bp->hwrm_cmd_lock);
5603 for (i = 0; i < bp->cp_nr_rings; i++) {
dfc9c94a 5604 struct bnxt_napi *bnapi = bp->bnapi[i];
58590c8d 5605 struct bnxt_coal *hw_coal;
2c61d211 5606 u16 ring_id;
c0c050c5 5607
dfc9c94a 5608 req = &req_rx;
2c61d211
MC		 5609 if (!bnapi->rx_ring) {
5610 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
dfc9c94a 5611 req = &req_tx;
2c61d211
MC		 5612 } else {
5613 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
5614 }
5615 req->ring_id = cpu_to_le16(ring_id);
dfc9c94a
MC		 5616
5617 rc = _hwrm_send_message(bp, req, sizeof(*req),
c0c050c5
MC		 5618 HWRM_CMD_TIMEOUT);
5619 if (rc)
5620 break;
58590c8d
MC		 5621
5622 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5623 continue;
5624
5625 if (bnapi->rx_ring && bnapi->tx_ring) {
5626 req = &req_tx;
5627 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5628 req->ring_id = cpu_to_le16(ring_id);
5629 rc = _hwrm_send_message(bp, req, sizeof(*req),
5630 HWRM_CMD_TIMEOUT);
5631 if (rc)
5632 break;
5633 }
5634 if (bnapi->rx_ring)
5635 hw_coal = &bp->rx_coal;
5636 else
5637 hw_coal = &bp->tx_coal;
5638 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
c0c050c5
MC		 5639 }
5640 mutex_unlock(&bp->hwrm_cmd_lock);
5641 return rc;
5642}
5643
5644static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
5645{
5646 int rc = 0, i;
5647 struct hwrm_stat_ctx_free_input req = {0};
5648
5649 if (!bp->bnapi)
5650 return 0;
5651
3e8060fa
PS		 5652 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5653 return 0;
5654
c0c050c5
MC		 5655 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
5656
5657 mutex_lock(&bp->hwrm_cmd_lock);
5658 for (i = 0; i < bp->cp_nr_rings; i++) {
5659 struct bnxt_napi *bnapi = bp->bnapi[i];
5660 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5661
5662 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
5663 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
5664
5665 rc = _hwrm_send_message(bp, &req, sizeof(req),
5666 HWRM_CMD_TIMEOUT);
5667 if (rc)
5668 break;
5669
5670 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
5671 }
5672 }
5673 mutex_unlock(&bp->hwrm_cmd_lock);
5674 return rc;
5675}
5676
5677static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
5678{
5679 int rc = 0, i;
5680 struct hwrm_stat_ctx_alloc_input req = {0};
5681 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5682
3e8060fa
PS		 5683 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5684 return 0;
5685
c0c050c5
MC		 5686 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
5687
51f30785 5688 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
c0c050c5
MC		 5689
5690 mutex_lock(&bp->hwrm_cmd_lock);
5691 for (i = 0; i < bp->cp_nr_rings; i++) {
5692 struct bnxt_napi *bnapi = bp->bnapi[i];
5693 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5694
5695 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
5696
5697 rc = _hwrm_send_message(bp, &req, sizeof(req),
5698 HWRM_CMD_TIMEOUT);
5699 if (rc)
5700 break;
5701
5702 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
5703
5704 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
5705 }
5706 mutex_unlock(&bp->hwrm_cmd_lock);
89aa8445 5707 return rc;
c0c050c5
MC		 5708}
5709
cf6645f8
MC		 5710static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
5711{
5712 struct hwrm_func_qcfg_input req = {0};
567b2abe 5713 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
9315edca 5714 u16 flags;
cf6645f8
MC		 5715 int rc;
5716
5717 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5718 req.fid = cpu_to_le16(0xffff);
5719 mutex_lock(&bp->hwrm_cmd_lock);
5720 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5721 if (rc)
5722 goto func_qcfg_exit;
5723
5724#ifdef CONFIG_BNXT_SRIOV
5725 if (BNXT_VF(bp)) {
cf6645f8
MC		 5726 struct bnxt_vf_info *vf = &bp->vf;
5727
5728 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
5729 }
5730#endif
9315edca
MC		 5731 flags = le16_to_cpu(resp->flags);
5732 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
5733 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
97381a18 5734 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
9315edca 5735 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
97381a18 5736 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
9315edca
MC		 5737 }
5738 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
5739 bp->flags |= BNXT_FLAG_MULTI_HOST;
bc39f885 5740
567b2abe
SB		 5741 switch (resp->port_partition_type) {
5742 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
5743 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
5744 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
5745 bp->port_partition_type = resp->port_partition_type;
5746 break;
5747 }
32e8239c
MC		 5748 if (bp->hwrm_spec_code < 0x10707 ||
5749 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
5750 bp->br_mode = BRIDGE_MODE_VEB;
5751 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
5752 bp->br_mode = BRIDGE_MODE_VEPA;
5753 else
5754 bp->br_mode = BRIDGE_MODE_UNDEF;
cf6645f8 5755
7eb9bb3a
MC		 5756 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
5757 if (!bp->max_mtu)
5758 bp->max_mtu = BNXT_MAX_MTU;
5759
cf6645f8
MC		 5760func_qcfg_exit:
5761 mutex_unlock(&bp->hwrm_cmd_lock);
5762 return rc;
5763}
5764
98f04cf0
MC		 5765static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5766{
5767 struct hwrm_func_backing_store_qcaps_input req = {0};
5768 struct hwrm_func_backing_store_qcaps_output *resp =
5769 bp->hwrm_cmd_resp_addr;
5770 int rc;
5771
5772 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
5773 return 0;
5774
5775 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1);
5776 mutex_lock(&bp->hwrm_cmd_lock);
5777 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5778 if (!rc) {
5779 struct bnxt_ctx_pg_info *ctx_pg;
5780 struct bnxt_ctx_mem_info *ctx;
5781 int i;
5782
5783 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
5784 if (!ctx) {
5785 rc = -ENOMEM;
5786 goto ctx_err;
5787 }
5788 ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL);
5789 if (!ctx_pg) {
5790 kfree(ctx);
5791 rc = -ENOMEM;
5792 goto ctx_err;
5793 }
5794 for (i = 0; i < bp->max_q + 1; i++, ctx_pg++)
5795 ctx->tqm_mem[i] = ctx_pg;
5796
5797 bp->ctx = ctx;
5798 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
5799 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
5800 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
5801 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
5802 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
5803 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
5804 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
5805 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
5806 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
5807 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
5808 ctx->vnic_max_vnic_entries =
5809 le16_to_cpu(resp->vnic_max_vnic_entries);
5810 ctx->vnic_max_ring_table_entries =
5811 le16_to_cpu(resp->vnic_max_ring_table_entries);
5812 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
5813 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
5814 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
5815 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
5816 ctx->tqm_min_entries_per_ring =
5817 le32_to_cpu(resp->tqm_min_entries_per_ring);
5818 ctx->tqm_max_entries_per_ring =
5819 le32_to_cpu(resp->tqm_max_entries_per_ring);
5820 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5821 if (!ctx->tqm_entries_multiple)
5822 ctx->tqm_entries_multiple = 1;
5823 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
5824 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
5825 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
5826 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
5827 } else {
5828 rc = 0;
5829 }
5830ctx_err:
5831 mutex_unlock(&bp->hwrm_cmd_lock);
5832 return rc;
5833}
5834
1b9394e5
MC		 5835static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr,
5836 __le64 *pg_dir)
5837{
5838 u8 pg_size = 0;
5839
5840 if (BNXT_PAGE_SHIFT == 13)
5841 pg_size = 1 << 4;
5842 else if (BNXT_PAGE_SIZE == 16)
5843 pg_size = 2 << 4;
5844
5845 *pg_attr = pg_size;
5846 if (rmem->nr_pages > 1) {
5847 *pg_attr |= 1;
5848 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
5849 } else {
5850 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
5851 }
5852}
5853
5854#define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \
5855 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \
5856 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \
5857 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \
5858 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \
5859 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
5860
5861static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
5862{
5863 struct hwrm_func_backing_store_cfg_input req = {0};
5864 struct bnxt_ctx_mem_info *ctx = bp->ctx;
5865 struct bnxt_ctx_pg_info *ctx_pg;
5866 __le32 *num_entries;
5867 __le64 *pg_dir;
5868 u8 *pg_attr;
5869 int i, rc;
5870 u32 ena;
5871
5872 if (!ctx)
5873 return 0;
5874
5875 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1);
5876 req.enables = cpu_to_le32(enables);
5877
5878 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
5879 ctx_pg = &ctx->qp_mem;
5880 req.qp_num_entries = cpu_to_le32(ctx_pg->entries);
5881 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
5882 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
5883 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
5884 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5885 &req.qpc_pg_size_qpc_lvl,
5886 &req.qpc_page_dir);
5887 }
5888 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
5889 ctx_pg = &ctx->srq_mem;
5890 req.srq_num_entries = cpu_to_le32(ctx_pg->entries);
5891 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
5892 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
5893 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5894 &req.srq_pg_size_srq_lvl,
5895 &req.srq_page_dir);
5896 }
5897 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
5898 ctx_pg = &ctx->cq_mem;
5899 req.cq_num_entries = cpu_to_le32(ctx_pg->entries);
5900 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
5901 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
5902 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl,
5903 &req.cq_page_dir);
5904 }
5905 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
5906 ctx_pg = &ctx->vnic_mem;
5907 req.vnic_num_vnic_entries =
5908 cpu_to_le16(ctx->vnic_max_vnic_entries);
5909 req.vnic_num_ring_table_entries =
5910 cpu_to_le16(ctx->vnic_max_ring_table_entries);
5911 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
5912 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5913 &req.vnic_pg_size_vnic_lvl,
5914 &req.vnic_page_dir);
5915 }
5916 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
5917 ctx_pg = &ctx->stat_mem;
5918 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
5919 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
5920 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5921 &req.stat_pg_size_stat_lvl,
5922 &req.stat_page_dir);
5923 }
5924 for (i = 0, num_entries = &req.tqm_sp_num_entries,
5925 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl,
5926 pg_dir = &req.tqm_sp_page_dir,
5927 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
5928 i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5929 if (!(enables & ena))
5930 continue;
5931
5932 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
5933 ctx_pg = ctx->tqm_mem[i];
5934 *num_entries = cpu_to_le32(ctx_pg->entries);
5935 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5936 }
5937 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5938 if (rc)
5939 rc = -EIO;
5940 return rc;
5941}
5942
98f04cf0
MC		 5943static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
5944 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size)
5945{
5946 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
5947
5948 if (!mem_size)
5949 return 0;
5950
5951 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
5952 if (rmem->nr_pages > MAX_CTX_PAGES) {
5953 rmem->nr_pages = 0;
5954 return -EINVAL;
5955 }
5956 rmem->page_size = BNXT_PAGE_SIZE;
5957 rmem->pg_arr = ctx_pg->ctx_pg_arr;
5958 rmem->dma_arr = ctx_pg->ctx_dma_arr;
1b9394e5 5959 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
98f04cf0
MC		 5960 return bnxt_alloc_ring(bp, rmem);
5961}
5962
5963static void bnxt_free_ctx_mem(struct bnxt *bp)
5964{
5965 struct bnxt_ctx_mem_info *ctx = bp->ctx;
5966 int i;
5967
5968 if (!ctx)
5969 return;
5970
5971 if (ctx->tqm_mem[0]) {
5972 for (i = 0; i < bp->max_q + 1; i++)
5973 bnxt_free_ring(bp, &ctx->tqm_mem[i]->ring_mem);
5974 kfree(ctx->tqm_mem[0]);
5975 ctx->tqm_mem[0] = NULL;
5976 }
5977
5978 bnxt_free_ring(bp, &ctx->stat_mem.ring_mem);
5979 bnxt_free_ring(bp, &ctx->vnic_mem.ring_mem);
5980 bnxt_free_ring(bp, &ctx->cq_mem.ring_mem);
5981 bnxt_free_ring(bp, &ctx->srq_mem.ring_mem);
5982 bnxt_free_ring(bp, &ctx->qp_mem.ring_mem);
5983 ctx->flags &= ~BNXT_CTX_FLAG_INITED;
5984}
5985
5986static int bnxt_alloc_ctx_mem(struct bnxt *bp)
5987{
5988 struct bnxt_ctx_pg_info *ctx_pg;
5989 struct bnxt_ctx_mem_info *ctx;
1b9394e5 5990 u32 mem_size, ena, entries;
98f04cf0
MC		 5991 int i, rc;
5992
5993 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
5994 if (rc) {
5995 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
5996 rc);
5997 return rc;
5998 }
5999 ctx = bp->ctx;
6000 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
6001 return 0;
6002
6003 ctx_pg = &ctx->qp_mem;
6004 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
6005 mem_size = ctx->qp_entry_size * ctx_pg->entries;
6006 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size);
6007 if (rc)
6008 return rc;
6009
6010 ctx_pg = &ctx->srq_mem;
6011 ctx_pg->entries = ctx->srq_max_l2_entries;
6012 mem_size = ctx->srq_entry_size * ctx_pg->entries;
6013 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size);
6014 if (rc)
6015 return rc;
6016
6017 ctx_pg = &ctx->cq_mem;
6018 ctx_pg->entries = ctx->cq_max_l2_entries;
6019 mem_size = ctx->cq_entry_size * ctx_pg->entries;
6020 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size);
6021 if (rc)
6022 return rc;
6023
6024 ctx_pg = &ctx->vnic_mem;
6025 ctx_pg->entries = ctx->vnic_max_vnic_entries +
6026 ctx->vnic_max_ring_table_entries;
6027 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
6028 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size);
6029 if (rc)
6030 return rc;
6031
6032 ctx_pg = &ctx->stat_mem;
6033 ctx_pg->entries = ctx->stat_max_entries;
6034 mem_size = ctx->stat_entry_size * ctx_pg->entries;
6035 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size);
6036 if (rc)
6037 return rc;
6038
6039 entries = ctx->qp_max_l2_entries;
6040 entries = roundup(entries, ctx->tqm_entries_multiple);
6041 entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring,
6042 ctx->tqm_max_entries_per_ring);
1b9394e5 6043 for (i = 0, ena = 0; i < bp->max_q + 1; i++) {
98f04cf0
MC		 6044 ctx_pg = ctx->tqm_mem[i];
6045 ctx_pg->entries = entries;
6046 mem_size = ctx->tqm_entry_size * entries;
6047 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size);
6048 if (rc)
6049 return rc;
1b9394e5 6050 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
98f04cf0 6051 }
1b9394e5
MC		 6052 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
6053 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
6054 if (rc)
6055 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
6056 rc);
6057 else
6058 ctx->flags |= BNXT_CTX_FLAG_INITED;
6059
98f04cf0
MC		 6060 return 0;
6061}
6062
db4723b3 6063int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
be0dd9c4
MC		 6064{
6065 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6066 struct hwrm_func_resource_qcaps_input req = {0};
6067 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6068 int rc;
6069
6070 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
6071 req.fid = cpu_to_le16(0xffff);
6072
6073 mutex_lock(&bp->hwrm_cmd_lock);
6074 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6075 if (rc) {
6076 rc = -EIO;
6077 goto hwrm_func_resc_qcaps_exit;
6078 }
6079
db4723b3
MC		 6080 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
6081 if (!all)
6082 goto hwrm_func_resc_qcaps_exit;
6083
be0dd9c4
MC		 6084 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
6085 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6086 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
6087 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6088 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
6089 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6090 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
6091 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6092 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
6093 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
6094 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
6095 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6096 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
6097 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6098 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
6099 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6100
9c1fabdf
MC		 6101 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6102 u16 max_msix = le16_to_cpu(resp->max_msix);
6103
6104 hw_resc->max_irqs = min_t(u16, hw_resc->max_irqs, max_msix);
6105 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
6106 }
6107
4673d664
MC		 6108 if (BNXT_PF(bp)) {
6109 struct bnxt_pf_info *pf = &bp->pf;
6110
6111 pf->vf_resv_strategy =
6112 le16_to_cpu(resp->vf_reservation_strategy);
bf82736d 6113 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
4673d664
MC		 6114 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
6115 }
be0dd9c4
MC		 6116hwrm_func_resc_qcaps_exit:
6117 mutex_unlock(&bp->hwrm_cmd_lock);
6118 return rc;
6119}
6120
6121static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
c0c050c5
MC		 6122{
6123 int rc = 0;
6124 struct hwrm_func_qcaps_input req = {0};
6125 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6a4f2947
MC		 6126 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6127 u32 flags;
c0c050c5
MC		 6128
6129 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
6130 req.fid = cpu_to_le16(0xffff);
6131
6132 mutex_lock(&bp->hwrm_cmd_lock);
6133 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6134 if (rc)
6135 goto hwrm_func_qcaps_exit;
6136
6a4f2947
MC		 6137 flags = le32_to_cpu(resp->flags);
6138 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
e4060d30 6139 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
6a4f2947 6140 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
e4060d30
MC		 6141 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
6142
7cc5a20e 6143 bp->tx_push_thresh = 0;
6a4f2947 6144 if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
7cc5a20e
MC		 6145 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
6146
6a4f2947
MC		 6147 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6148 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6149 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6150 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6151 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
6152 if (!hw_resc->max_hw_ring_grps)
6153 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
6154 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6155 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6156 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6157
c0c050c5
MC		 6158 if (BNXT_PF(bp)) {
6159 struct bnxt_pf_info *pf = &bp->pf;
6160
6161 pf->fw_fid = le16_to_cpu(resp->fid);
6162 pf->port_id = le16_to_cpu(resp->port_id);
87027db1 6163 bp->dev->dev_port = pf->port_id;
11f15ed3 6164 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
c0c050c5
MC		 6165 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
6166 pf->max_vfs = le16_to_cpu(resp->max_vfs);
6167 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
6168 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
6169 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
6170 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
6171 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
6172 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
6a4f2947 6173 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
c1ef146a 6174 bp->flags |= BNXT_FLAG_WOL_CAP;
c0c050c5 6175 } else {
379a80a1 6176#ifdef CONFIG_BNXT_SRIOV
c0c050c5
MC		 6177 struct bnxt_vf_info *vf = &bp->vf;
6178
6179 vf->fw_fid = le16_to_cpu(resp->fid);
7cc5a20e 6180 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
379a80a1 6181#endif
c0c050c5
MC		 6182 }
6183
c0c050c5
MC		 6184hwrm_func_qcaps_exit:
6185 mutex_unlock(&bp->hwrm_cmd_lock);
6186 return rc;
6187}
6188
be0dd9c4
MC		 6189static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
6190{
6191 int rc;
6192
6193 rc = __bnxt_hwrm_func_qcaps(bp);
6194 if (rc)
6195 return rc;
6196 if (bp->hwrm_spec_code >= 0x10803) {
98f04cf0
MC		 6197 rc = bnxt_alloc_ctx_mem(bp);
6198 if (rc)
6199 return rc;
db4723b3 6200 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
be0dd9c4 6201 if (!rc)
97381a18 6202 bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
be0dd9c4
MC		 6203 }
6204 return 0;
6205}
6206
c0c050c5
MC		 6207static int bnxt_hwrm_func_reset(struct bnxt *bp)
6208{
6209 struct hwrm_func_reset_input req = {0};
6210
6211 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
6212 req.enables = 0;
6213
6214 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
6215}
6216
6217static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
6218{
6219 int rc = 0;
6220 struct hwrm_queue_qportcfg_input req = {0};
6221 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
aabfc016
MC		 6222 u8 i, j, *qptr;
6223 bool no_rdma;
c0c050c5
MC		 6224
6225 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
6226
6227 mutex_lock(&bp->hwrm_cmd_lock);
6228 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6229 if (rc)
6230 goto qportcfg_exit;
6231
6232 if (!resp->max_configurable_queues) {
6233 rc = -EINVAL;
6234 goto qportcfg_exit;
6235 }
6236 bp->max_tc = resp->max_configurable_queues;
87c374de 6237 bp->max_lltc = resp->max_configurable_lossless_queues;
c0c050c5
MC		 6238 if (bp->max_tc > BNXT_MAX_QUEUE)
6239 bp->max_tc = BNXT_MAX_QUEUE;
6240
aabfc016
MC		 6241 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
6242 qptr = &resp->queue_id0;
6243 for (i = 0, j = 0; i < bp->max_tc; i++) {
98f04cf0
MC		 6244 bp->q_info[j].queue_id = *qptr;
6245 bp->q_ids[i] = *qptr++;
aabfc016
MC		 6246 bp->q_info[j].queue_profile = *qptr++;
6247 bp->tc_to_qidx[j] = j;
6248 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
6249 (no_rdma && BNXT_PF(bp)))
6250 j++;
6251 }
98f04cf0 6252 bp->max_q = bp->max_tc;
aabfc016
MC		 6253 bp->max_tc = max_t(u8, j, 1);
6254
441cabbb
MC		 6255 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
6256 bp->max_tc = 1;
6257
87c374de
MC		 6258 if (bp->max_lltc > bp->max_tc)
6259 bp->max_lltc = bp->max_tc;
6260
c0c050c5
MC		 6261qportcfg_exit:
6262 mutex_unlock(&bp->hwrm_cmd_lock);
6263 return rc;
6264}
6265
6266static int bnxt_hwrm_ver_get(struct bnxt *bp)
6267{
6268 int rc;
6269 struct hwrm_ver_get_input req = {0};
6270 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
e605db80 6271 u32 dev_caps_cfg;
c0c050c5 6272
e6ef2699 6273 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
c0c050c5
MC		 6274 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
6275 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6276 req.hwrm_intf_min = HWRM_VERSION_MINOR;
6277 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6278 mutex_lock(&bp->hwrm_cmd_lock);
6279 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6280 if (rc)
6281 goto hwrm_ver_get_exit;
6282
6283 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
6284
894aa69a
MC		 6285 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
6286 resp->hwrm_intf_min_8b << 8 |
6287 resp->hwrm_intf_upd_8b;
6288 if (resp->hwrm_intf_maj_8b < 1) {
c193554e 6289 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
894aa69a
MC		 6290 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
6291 resp->hwrm_intf_upd_8b);
c193554e 6292 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
c0c050c5 6293 }
431aa1eb 6294 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
894aa69a
MC		 6295 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
6296 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
c0c050c5 6297
ff4fe81d
MC		 6298 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
6299 if (!bp->hwrm_cmd_timeout)
6300 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
6301
1dfddc41 6302 if (resp->hwrm_intf_maj_8b >= 1) {
e6ef2699 6303 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
1dfddc41
MC		 6304 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
6305 }
6306 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
6307 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
e6ef2699 6308
659c805c 6309 bp->chip_num = le16_to_cpu(resp->chip_num);
3e8060fa
PS		 6310 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
6311 !resp->chip_metal)
6312 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
659c805c 6313
e605db80
DK		 6314 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
6315 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
6316 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
97381a18 6317 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
e605db80 6318
c0c050c5
MC		 6319hwrm_ver_get_exit:
6320 mutex_unlock(&bp->hwrm_cmd_lock);
6321 return rc;
6322}
6323
5ac67d8b
RS		 6324int bnxt_hwrm_fw_set_time(struct bnxt *bp)
6325{
6326 struct hwrm_fw_set_time_input req = {0};
7dfaa7bc
AB		 6327 struct tm tm;
6328 time64_t now = ktime_get_real_seconds();
5ac67d8b 6329
ca2c39e2
MC		 6330 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
6331 bp->hwrm_spec_code < 0x10400)
5ac67d8b
RS		 6332 return -EOPNOTSUPP;
6333
7dfaa7bc 6334 time64_to_tm(now, 0, &tm);
5ac67d8b
RS		 6335 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
6336 req.year = cpu_to_le16(1900 + tm.tm_year);
6337 req.month = 1 + tm.tm_mon;
6338 req.day = tm.tm_mday;
6339 req.hour = tm.tm_hour;
6340 req.minute = tm.tm_min;
6341 req.second = tm.tm_sec;
6342 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6343}
6344
3bdf56c4
MC		 6345static int bnxt_hwrm_port_qstats(struct bnxt *bp)
6346{
6347 int rc;
6348 struct bnxt_pf_info *pf = &bp->pf;
6349 struct hwrm_port_qstats_input req = {0};
6350
6351 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
6352 return 0;
6353
6354 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
6355 req.port_id = cpu_to_le16(pf->port_id);
6356 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
6357 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
6358 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6359 return rc;
6360}
6361
00db3cba
VV		 6362static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp)
6363{
36e53349 6364 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
00db3cba
VV		 6365 struct hwrm_port_qstats_ext_input req = {0};
6366 struct bnxt_pf_info *pf = &bp->pf;
36e53349 6367 int rc;
00db3cba
VV		 6368
6369 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
6370 return 0;
6371
6372 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
6373 req.port_id = cpu_to_le16(pf->port_id);
6374 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
6375 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map);
36e53349
MC		 6376 req.tx_stat_size = cpu_to_le16(sizeof(struct tx_port_stats_ext));
6377 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map);
6378 mutex_lock(&bp->hwrm_cmd_lock);
6379 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6380 if (!rc) {
6381 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8;
6382 bp->fw_tx_stats_ext_size = le16_to_cpu(resp->tx_stat_size) / 8;
6383 } else {
6384 bp->fw_rx_stats_ext_size = 0;
6385 bp->fw_tx_stats_ext_size = 0;
6386 }
6387 mutex_unlock(&bp->hwrm_cmd_lock);
6388 return rc;
00db3cba
VV		 6389}
6390
c0c050c5
MC		 6391static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
6392{
6393 if (bp->vxlan_port_cnt) {
6394 bnxt_hwrm_tunnel_dst_port_free(
6395 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6396 }
6397 bp->vxlan_port_cnt = 0;
6398 if (bp->nge_port_cnt) {
6399 bnxt_hwrm_tunnel_dst_port_free(
6400 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6401 }
6402 bp->nge_port_cnt = 0;
6403}
6404
6405static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
6406{
6407 int rc, i;
6408 u32 tpa_flags = 0;
6409
6410 if (set_tpa)
6411 tpa_flags = bp->flags & BNXT_FLAG_TPA;
6412 for (i = 0; i < bp->nr_vnics; i++) {
6413 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
6414 if (rc) {
6415 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
23e12c89 6416 i, rc);
c0c050c5
MC		 6417 return rc;
6418 }
6419 }
6420 return 0;
6421}
6422
6423static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
6424{
6425 int i;
6426
6427 for (i = 0; i < bp->nr_vnics; i++)
6428 bnxt_hwrm_vnic_set_rss(bp, i, false);
6429}
6430
6431static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
6432 bool irq_re_init)
6433{
6434 if (bp->vnic_info) {
6435 bnxt_hwrm_clear_vnic_filter(bp);
6436 /* clear all RSS setting before free vnic ctx */
6437 bnxt_hwrm_clear_vnic_rss(bp);
6438 bnxt_hwrm_vnic_ctx_free(bp);
6439 /* before free the vnic, undo the vnic tpa settings */
6440 if (bp->flags & BNXT_FLAG_TPA)
6441 bnxt_set_tpa(bp, false);
6442 bnxt_hwrm_vnic_free(bp);
6443 }
6444 bnxt_hwrm_ring_free(bp, close_path);
6445 bnxt_hwrm_ring_grp_free(bp);
6446 if (irq_re_init) {
6447 bnxt_hwrm_stat_ctx_free(bp);
6448 bnxt_hwrm_free_tunnel_ports(bp);
6449 }
6450}
6451
39d8ba2e
MC		 6452static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
6453{
6454 struct hwrm_func_cfg_input req = {0};
6455 int rc;
6456
6457 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
6458 req.fid = cpu_to_le16(0xffff);
6459 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
6460 if (br_mode == BRIDGE_MODE_VEB)
6461 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
6462 else if (br_mode == BRIDGE_MODE_VEPA)
6463 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
6464 else
6465 return -EINVAL;
6466 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6467 if (rc)
6468 rc = -EIO;
6469 return rc;
6470}
6471
c3480a60
MC		 6472static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
6473{
6474 struct hwrm_func_cfg_input req = {0};
6475 int rc;
6476
6477 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
6478 return 0;
6479
6480 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
6481 req.fid = cpu_to_le16(0xffff);
6482 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
d4f52de0 6483 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
c3480a60 6484 if (size == 128)
d4f52de0 6485 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
c3480a60
MC		 6486
6487 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6488 if (rc)
6489 rc = -EIO;
6490 return rc;
6491}
6492
7b3af4f7 6493static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
c0c050c5 6494{
ae10ae74 6495 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
c0c050c5
MC		 6496 int rc;
6497
ae10ae74
MC		 6498 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
6499 goto skip_rss_ctx;
6500
c0c050c5 6501 /* allocate context for vnic */
94ce9caa 6502 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
c0c050c5
MC		 6503 if (rc) {
6504 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
6505 vnic_id, rc);
6506 goto vnic_setup_err;
6507 }
6508 bp->rsscos_nr_ctxs++;
6509
94ce9caa
PS		 6510 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6511 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
6512 if (rc) {
6513 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
6514 vnic_id, rc);
6515 goto vnic_setup_err;
6516 }
6517 bp->rsscos_nr_ctxs++;
6518 }
6519
ae10ae74 6520skip_rss_ctx:
c0c050c5
MC		 6521 /* configure default vnic, ring grp */
6522 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
6523 if (rc) {
6524 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
6525 vnic_id, rc);
6526 goto vnic_setup_err;
6527 }
6528
6529 /* Enable RSS hashing on vnic */
6530 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
6531 if (rc) {
6532 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
6533 vnic_id, rc);
6534 goto vnic_setup_err;
6535 }
6536
6537 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
6538 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
6539 if (rc) {
6540 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
6541 vnic_id, rc);
6542 }
6543 }
6544
6545vnic_setup_err:
6546 return rc;
6547}
6548
7b3af4f7
MC		 6549static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
6550{
6551 int rc, i, nr_ctxs;
6552
6553 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
6554 for (i = 0; i < nr_ctxs; i++) {
6555 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
6556 if (rc) {
6557 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
6558 vnic_id, i, rc);
6559 break;
6560 }
6561 bp->rsscos_nr_ctxs++;
6562 }
6563 if (i < nr_ctxs)
6564 return -ENOMEM;
6565
6566 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
6567 if (rc) {
6568 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
6569 vnic_id, rc);
6570 return rc;
6571 }
6572 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
6573 if (rc) {
6574 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
6575 vnic_id, rc);
6576 return rc;
6577 }
6578 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
6579 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
6580 if (rc) {
6581 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
6582 vnic_id, rc);
6583 }
6584 }
6585 return rc;
6586}
6587
6588static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
6589{
6590 if (bp->flags & BNXT_FLAG_CHIP_P5)
6591 return __bnxt_setup_vnic_p5(bp, vnic_id);
6592 else
6593 return __bnxt_setup_vnic(bp, vnic_id);
6594}
6595
c0c050c5
MC		 6596static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
6597{
6598#ifdef CONFIG_RFS_ACCEL
6599 int i, rc = 0;
6600
6601 for (i = 0; i < bp->rx_nr_rings; i++) {
ae10ae74 6602 struct bnxt_vnic_info *vnic;
c0c050c5
MC		 6603 u16 vnic_id = i + 1;
6604 u16 ring_id = i;
6605
6606 if (vnic_id >= bp->nr_vnics)
6607 break;
6608
ae10ae74
MC		 6609 vnic = &bp->vnic_info[vnic_id];
6610 vnic->flags |= BNXT_VNIC_RFS_FLAG;
6611 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6612 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
b81a90d3 6613 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
c0c050c5
MC		 6614 if (rc) {
6615 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
6616 vnic_id, rc);
6617 break;
6618 }
6619 rc = bnxt_setup_vnic(bp, vnic_id);
6620 if (rc)
6621 break;
6622 }
6623 return rc;
6624#else
6625 return 0;
6626#endif
6627}
6628
17c71ac3
MC		 6629/* Allow PF and VF with default VLAN to be in promiscuous mode */
6630static bool bnxt_promisc_ok(struct bnxt *bp)
6631{
6632#ifdef CONFIG_BNXT_SRIOV
6633 if (BNXT_VF(bp) && !bp->vf.vlan)
6634 return false;
6635#endif
6636 return true;
6637}
6638
dc52c6c7
PS		 6639static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
6640{
6641 unsigned int rc = 0;
6642
6643 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
6644 if (rc) {
6645 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
6646 rc);
6647 return rc;
6648 }
6649
6650 rc = bnxt_hwrm_vnic_cfg(bp, 1);
6651 if (rc) {
6652 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
6653 rc);
6654 return rc;
6655 }
6656 return rc;
6657}
6658
b664f008 6659static int bnxt_cfg_rx_mode(struct bnxt *);
7d2837dd 6660static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
b664f008 6661
c0c050c5
MC		 6662static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
6663{
7d2837dd 6664 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
c0c050c5 6665 int rc = 0;
76595193 6666 unsigned int rx_nr_rings = bp->rx_nr_rings;
c0c050c5
MC		 6667
6668 if (irq_re_init) {
6669 rc = bnxt_hwrm_stat_ctx_alloc(bp);
6670 if (rc) {
6671 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
6672 rc);
6673 goto err_out;
6674 }
6675 }
6676
6677 rc = bnxt_hwrm_ring_alloc(bp);
6678 if (rc) {
6679 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
6680 goto err_out;
6681 }
6682
6683 rc = bnxt_hwrm_ring_grp_alloc(bp);
6684 if (rc) {
6685 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
6686 goto err_out;
6687 }
6688
76595193
PS		 6689 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6690 rx_nr_rings--;
6691
c0c050c5 6692 /* default vnic 0 */
76595193 6693 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
c0c050c5
MC		 6694 if (rc) {
6695 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
6696 goto err_out;
6697 }
6698
6699 rc = bnxt_setup_vnic(bp, 0);
6700 if (rc)
6701 goto err_out;
6702
6703 if (bp->flags & BNXT_FLAG_RFS) {
6704 rc = bnxt_alloc_rfs_vnics(bp);
6705 if (rc)
6706 goto err_out;
6707 }
6708
6709 if (bp->flags & BNXT_FLAG_TPA) {
6710 rc = bnxt_set_tpa(bp, true);
6711 if (rc)
6712 goto err_out;
6713 }
6714
6715 if (BNXT_VF(bp))
6716 bnxt_update_vf_mac(bp);
6717
6718 /* Filter for default vnic 0 */
6719 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
6720 if (rc) {
6721 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
6722 goto err_out;
6723 }
7d2837dd 6724 vnic->uc_filter_count = 1;
c0c050c5 6725
30e33848
MC		 6726 vnic->rx_mask = 0;
6727 if (bp->dev->flags & IFF_BROADCAST)
6728 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
c0c050c5 6729
17c71ac3 6730 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7d2837dd
MC		 6731 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6732
6733 if (bp->dev->flags & IFF_ALLMULTI) {
6734 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6735 vnic->mc_list_count = 0;
6736 } else {
6737 u32 mask = 0;
6738
6739 bnxt_mc_list_updated(bp, &mask);
6740 vnic->rx_mask |= mask;
6741 }
c0c050c5 6742
b664f008
MC		 6743 rc = bnxt_cfg_rx_mode(bp);
6744 if (rc)
c0c050c5 6745 goto err_out;
c0c050c5
MC		 6746
6747 rc = bnxt_hwrm_set_coal(bp);
6748 if (rc)
6749 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
dc52c6c7
PS		 6750 rc);
6751
6752 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6753 rc = bnxt_setup_nitroa0_vnic(bp);
6754 if (rc)
6755 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
6756 rc);
6757 }
c0c050c5 6758
cf6645f8
MC		 6759 if (BNXT_VF(bp)) {
6760 bnxt_hwrm_func_qcfg(bp);
6761 netdev_update_features(bp->dev);
6762 }
6763
c0c050c5
MC		 6764 return 0;
6765
6766err_out:
6767 bnxt_hwrm_resource_free(bp, 0, true);
6768
6769 return rc;
6770}
6771
6772static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
6773{
6774 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
6775 return 0;
6776}
6777
6778static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
6779{
2247925f 6780 bnxt_init_cp_rings(bp);
c0c050c5
MC		 6781 bnxt_init_rx_rings(bp);
6782 bnxt_init_tx_rings(bp);
6783 bnxt_init_ring_grps(bp, irq_re_init);
6784 bnxt_init_vnics(bp);
6785
6786 return bnxt_init_chip(bp, irq_re_init);
6787}
6788
c0c050c5
MC		 6789static int bnxt_set_real_num_queues(struct bnxt *bp)
6790{
6791 int rc;
6792 struct net_device *dev = bp->dev;
6793
5f449249
MC		 6794 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
6795 bp->tx_nr_rings_xdp);
c0c050c5
MC		 6796 if (rc)
6797 return rc;
6798
6799 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
6800 if (rc)
6801 return rc;
6802
6803#ifdef CONFIG_RFS_ACCEL
45019a18 6804 if (bp->flags & BNXT_FLAG_RFS)
c0c050c5 6805 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
c0c050c5
MC		 6806#endif
6807
6808 return rc;
6809}
6810
6e6c5a57
MC		 6811static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
6812 bool shared)
6813{
6814 int _rx = *rx, _tx = *tx;
6815
6816 if (shared) {
6817 *rx = min_t(int, _rx, max);
6818 *tx = min_t(int, _tx, max);
6819 } else {
6820 if (max < 2)
6821 return -ENOMEM;
6822
6823 while (_rx + _tx > max) {
6824 if (_rx > _tx && _rx > 1)
6825 _rx--;
6826 else if (_tx > 1)
6827 _tx--;
6828 }
6829 *rx = _rx;
6830 *tx = _tx;
6831 }
6832 return 0;
6833}
6834
7809592d
MC		 6835static void bnxt_setup_msix(struct bnxt *bp)
6836{
6837 const int len = sizeof(bp->irq_tbl[0].name);
6838 struct net_device *dev = bp->dev;
6839 int tcs, i;
6840
6841 tcs = netdev_get_num_tc(dev);
6842 if (tcs > 1) {
d1e7925e 6843 int i, off, count;
7809592d 6844
d1e7925e
MC		 6845 for (i = 0; i < tcs; i++) {
6846 count = bp->tx_nr_rings_per_tc;
6847 off = i * count;
6848 netdev_set_tc_queue(dev, i, count, off);
7809592d
MC		 6849 }
6850 }
6851
6852 for (i = 0; i < bp->cp_nr_rings; i++) {
e5811b8c 6853 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7809592d
MC		 6854 char *attr;
6855
6856 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6857 attr = "TxRx";
6858 else if (i < bp->rx_nr_rings)
6859 attr = "rx";
6860 else
6861 attr = "tx";
6862
e5811b8c
MC		 6863 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
6864 attr, i);
6865 bp->irq_tbl[map_idx].handler = bnxt_msix;
7809592d
MC		 6866 }
6867}
6868
6869static void bnxt_setup_inta(struct bnxt *bp)
6870{
6871 const int len = sizeof(bp->irq_tbl[0].name);
6872
6873 if (netdev_get_num_tc(bp->dev))
6874 netdev_reset_tc(bp->dev);
6875
6876 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
6877 0);
6878 bp->irq_tbl[0].handler = bnxt_inta;
6879}
6880
6881static int bnxt_setup_int_mode(struct bnxt *bp)
6882{
6883 int rc;
6884
6885 if (bp->flags & BNXT_FLAG_USING_MSIX)
6886 bnxt_setup_msix(bp);
6887 else
6888 bnxt_setup_inta(bp);
6889
6890 rc = bnxt_set_real_num_queues(bp);
6891 return rc;
6892}
6893
b7429954 6894#ifdef CONFIG_RFS_ACCEL
8079e8f1
MC		 6895static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
6896{
6a4f2947 6897 return bp->hw_resc.max_rsscos_ctxs;
8079e8f1
MC		 6898}
6899
6900static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
6901{
6a4f2947 6902 return bp->hw_resc.max_vnics;
8079e8f1 6903}
b7429954 6904#endif
8079e8f1 6905
e4060d30
MC		 6906unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
6907{
6a4f2947 6908 return bp->hw_resc.max_stat_ctxs;
e4060d30
MC		 6909}
6910
a588e458
MC		 6911void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
6912{
6a4f2947 6913 bp->hw_resc.max_stat_ctxs = max;
a588e458
MC		 6914}
6915
e4060d30
MC		 6916unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
6917{
6a4f2947 6918 return bp->hw_resc.max_cp_rings;
e4060d30
MC		 6919}
6920
00fe9c32 6921unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
a588e458 6922{
00fe9c32 6923 return bp->hw_resc.max_cp_rings - bnxt_get_ulp_msix_num(bp);
a588e458
MC		 6924}
6925
ad95c27b 6926static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
7809592d 6927{
6a4f2947
MC		 6928 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6929
6930 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
7809592d
MC		 6931}
6932
30f52947 6933static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
33c2657e 6934{
6a4f2947 6935 bp->hw_resc.max_irqs = max_irqs;
33c2657e
MC		 6936}
6937
fbcfc8e4
MC		 6938int bnxt_get_avail_msix(struct bnxt *bp, int num)
6939{
6940 int max_cp = bnxt_get_max_func_cp_rings(bp);
6941 int max_irq = bnxt_get_max_func_irqs(bp);
6942 int total_req = bp->cp_nr_rings + num;
6943 int max_idx, avail_msix;
6944
6945 max_idx = min_t(int, bp->total_irqs, max_cp);
6946 avail_msix = max_idx - bp->cp_nr_rings;
f1ca94de 6947 if (!BNXT_NEW_RM(bp) || avail_msix >= num)
fbcfc8e4
MC		 6948 return avail_msix;
6949
6950 if (max_irq < total_req) {
6951 num = max_irq - bp->cp_nr_rings;
6952 if (num <= 0)
6953 return 0;
6954 }
6955 return num;
6956}
6957
08654eb2
MC		 6958static int bnxt_get_num_msix(struct bnxt *bp)
6959{
f1ca94de 6960 if (!BNXT_NEW_RM(bp))
08654eb2
MC		 6961 return bnxt_get_max_func_irqs(bp);
6962
6963 return bnxt_cp_rings_in_use(bp);
6964}
6965
7809592d 6966static int bnxt_init_msix(struct bnxt *bp)
c0c050c5 6967{
fbcfc8e4 6968 int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
7809592d 6969 struct msix_entry *msix_ent;
c0c050c5 6970
08654eb2
MC		 6971 total_vecs = bnxt_get_num_msix(bp);
6972 max = bnxt_get_max_func_irqs(bp);
6973 if (total_vecs > max)
6974 total_vecs = max;
6975
2773dfb2
MC		 6976 if (!total_vecs)
6977 return 0;
6978
c0c050c5
MC		 6979 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
6980 if (!msix_ent)
6981 return -ENOMEM;
6982
6983 for (i = 0; i < total_vecs; i++) {
6984 msix_ent[i].entry = i;
6985 msix_ent[i].vector = 0;
6986 }
6987
01657bcd
MC		 6988 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
6989 min = 2;
6990
6991 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
fbcfc8e4
MC		 6992 ulp_msix = bnxt_get_ulp_msix_num(bp);
6993 if (total_vecs < 0 || total_vecs < ulp_msix) {
c0c050c5
MC		 6994 rc = -ENODEV;
6995 goto msix_setup_exit;
6996 }
6997
6998 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
6999 if (bp->irq_tbl) {
7809592d
MC		 7000 for (i = 0; i < total_vecs; i++)
7001 bp->irq_tbl[i].vector = msix_ent[i].vector;
c0c050c5 7002
7809592d 7003 bp->total_irqs = total_vecs;
c0c050c5 7004 /* Trim rings based upon num of vectors allocated */
6e6c5a57 7005 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
fbcfc8e4 7006 total_vecs - ulp_msix, min == 1);
6e6c5a57
MC		 7007 if (rc)
7008 goto msix_setup_exit;
7009
7809592d
MC		 7010 bp->cp_nr_rings = (min == 1) ?
7011 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7012 bp->tx_nr_rings + bp->rx_nr_rings;
c0c050c5 7013
c0c050c5
MC		 7014 } else {
7015 rc = -ENOMEM;
7016 goto msix_setup_exit;
7017 }
7018 bp->flags |= BNXT_FLAG_USING_MSIX;
7019 kfree(msix_ent);
7020 return 0;
7021
7022msix_setup_exit:
7809592d
MC		 7023 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
7024 kfree(bp->irq_tbl);
7025 bp->irq_tbl = NULL;
c0c050c5
MC		 7026 pci_disable_msix(bp->pdev);
7027 kfree(msix_ent);
7028 return rc;
7029}
7030
7809592d 7031static int bnxt_init_inta(struct bnxt *bp)
c0c050c5 7032{
c0c050c5 7033 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
7809592d
MC		 7034 if (!bp->irq_tbl)
7035 return -ENOMEM;
7036
7037 bp->total_irqs = 1;
c0c050c5
MC		 7038 bp->rx_nr_rings = 1;
7039 bp->tx_nr_rings = 1;
7040 bp->cp_nr_rings = 1;
01657bcd 7041 bp->flags |= BNXT_FLAG_SHARED_RINGS;
c0c050c5 7042 bp->irq_tbl[0].vector = bp->pdev->irq;
7809592d 7043 return 0;
c0c050c5
MC		 7044}
7045
7809592d 7046static int bnxt_init_int_mode(struct bnxt *bp)
c0c050c5
MC		 7047{
7048 int rc = 0;
7049
7050 if (bp->flags & BNXT_FLAG_MSIX_CAP)
7809592d 7051 rc = bnxt_init_msix(bp);
c0c050c5 7052
1fa72e29 7053 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
c0c050c5 7054 /* fallback to INTA */
7809592d 7055 rc = bnxt_init_inta(bp);
c0c050c5
MC		 7056 }
7057 return rc;
7058}
7059
7809592d
MC		 7060static void bnxt_clear_int_mode(struct bnxt *bp)
7061{
7062 if (bp->flags & BNXT_FLAG_USING_MSIX)
7063 pci_disable_msix(bp->pdev);
7064
7065 kfree(bp->irq_tbl);
7066 bp->irq_tbl = NULL;
7067 bp->flags &= ~BNXT_FLAG_USING_MSIX;
7068}
7069
fbcfc8e4 7070int bnxt_reserve_rings(struct bnxt *bp)
674f50a5 7071{
674f50a5
MC		 7072 int tcs = netdev_get_num_tc(bp->dev);
7073 int rc;
7074
7075 if (!bnxt_need_reserve_rings(bp))
7076 return 0;
7077
7078 rc = __bnxt_reserve_rings(bp);
7079 if (rc) {
7080 netdev_err(bp->dev, "ring reservation failure rc: %d\n", rc);
7081 return rc;
7082 }
f1ca94de 7083 if (BNXT_NEW_RM(bp) && (bnxt_get_num_msix(bp) != bp->total_irqs)) {
ec86f14e 7084 bnxt_ulp_irq_stop(bp);
674f50a5
MC		 7085 bnxt_clear_int_mode(bp);
7086 rc = bnxt_init_int_mode(bp);
ec86f14e 7087 bnxt_ulp_irq_restart(bp, rc);
674f50a5
MC		 7088 if (rc)
7089 return rc;
7090 }
7091 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
7092 netdev_err(bp->dev, "tx ring reservation failure\n");
7093 netdev_reset_tc(bp->dev);
7094 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
7095 return -ENOMEM;
7096 }
7097 bp->num_stat_ctxs = bp->cp_nr_rings;
7098 return 0;
7099}
7100
c0c050c5
MC		 7101static void bnxt_free_irq(struct bnxt *bp)
7102{
7103 struct bnxt_irq *irq;
7104 int i;
7105
7106#ifdef CONFIG_RFS_ACCEL
7107 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
7108 bp->dev->rx_cpu_rmap = NULL;
7109#endif
cb98526b 7110 if (!bp->irq_tbl || !bp->bnapi)
c0c050c5
MC		 7111 return;
7112
7113 for (i = 0; i < bp->cp_nr_rings; i++) {
e5811b8c
MC		 7114 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7115
7116 irq = &bp->irq_tbl[map_idx];
56f0fd80
VV		 7117 if (irq->requested) {
7118 if (irq->have_cpumask) {
7119 irq_set_affinity_hint(irq->vector, NULL);
7120 free_cpumask_var(irq->cpu_mask);
7121 irq->have_cpumask = 0;
7122 }
c0c050c5 7123 free_irq(irq->vector, bp->bnapi[i]);
56f0fd80
VV		 7124 }
7125
c0c050c5
MC		 7126 irq->requested = 0;
7127 }
c0c050c5
MC		 7128}
7129
7130static int bnxt_request_irq(struct bnxt *bp)
7131{
b81a90d3 7132 int i, j, rc = 0;
c0c050c5
MC		 7133 unsigned long flags = 0;
7134#ifdef CONFIG_RFS_ACCEL
e5811b8c 7135 struct cpu_rmap *rmap;
c0c050c5
MC		 7136#endif
7137
e5811b8c
MC		 7138 rc = bnxt_setup_int_mode(bp);
7139 if (rc) {
7140 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
7141 rc);
7142 return rc;
7143 }
7144#ifdef CONFIG_RFS_ACCEL
7145 rmap = bp->dev->rx_cpu_rmap;
7146#endif
c0c050c5
MC		 7147 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
7148 flags = IRQF_SHARED;
7149
b81a90d3 7150 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
e5811b8c
MC		 7151 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7152 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
7153
c0c050c5 7154#ifdef CONFIG_RFS_ACCEL
b81a90d3 7155 if (rmap && bp->bnapi[i]->rx_ring) {
c0c050c5
MC		 7156 rc = irq_cpu_rmap_add(rmap, irq->vector);
7157 if (rc)
7158 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
b81a90d3
MC		 7159 j);
7160 j++;
c0c050c5
MC		 7161 }
7162#endif
7163 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
7164 bp->bnapi[i]);
7165 if (rc)
7166 break;
7167
7168 irq->requested = 1;
56f0fd80
VV		 7169
7170 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
7171 int numa_node = dev_to_node(&bp->pdev->dev);
7172
7173 irq->have_cpumask = 1;
7174 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
7175 irq->cpu_mask);
7176 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
7177 if (rc) {
7178 netdev_warn(bp->dev,
7179 "Set affinity failed, IRQ = %d\n",
7180 irq->vector);
7181 break;
7182 }
7183 }
c0c050c5
MC		 7184 }
7185 return rc;
7186}
7187
7188static void bnxt_del_napi(struct bnxt *bp)
7189{
7190 int i;
7191
7192 if (!bp->bnapi)
7193 return;
7194
7195 for (i = 0; i < bp->cp_nr_rings; i++) {
7196 struct bnxt_napi *bnapi = bp->bnapi[i];
7197
7198 napi_hash_del(&bnapi->napi);
7199 netif_napi_del(&bnapi->napi);
7200 }
e5f6f564
ED		 7201 /* We called napi_hash_del() before netif_napi_del(), we need
7202 * to respect an RCU grace period before freeing napi structures.
7203 */
7204 synchronize_net();
c0c050c5
MC		 7205}
7206
7207static void bnxt_init_napi(struct bnxt *bp)
7208{
7209 int i;
10bbdaf5 7210 unsigned int cp_nr_rings = bp->cp_nr_rings;
c0c050c5
MC		 7211 struct bnxt_napi *bnapi;
7212
7213 if (bp->flags & BNXT_FLAG_USING_MSIX) {
10bbdaf5
PS		 7214 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7215 cp_nr_rings--;
7216 for (i = 0; i < cp_nr_rings; i++) {
c0c050c5
MC		 7217 bnapi = bp->bnapi[i];
7218 netif_napi_add(bp->dev, &bnapi->napi,
7219 bnxt_poll, 64);
c0c050c5 7220 }
10bbdaf5
PS		 7221 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7222 bnapi = bp->bnapi[cp_nr_rings];
7223 netif_napi_add(bp->dev, &bnapi->napi,
7224 bnxt_poll_nitroa0, 64);
10bbdaf5 7225 }
c0c050c5
MC		 7226 } else {
7227 bnapi = bp->bnapi[0];
7228 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
c0c050c5
MC		 7229 }
7230}
7231
7232static void bnxt_disable_napi(struct bnxt *bp)
7233{
7234 int i;
7235
7236 if (!bp->bnapi)
7237 return;
7238
0bc0b97f
AG		 7239 for (i = 0; i < bp->cp_nr_rings; i++) {
7240 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7241
7242 if (bp->bnapi[i]->rx_ring)
7243 cancel_work_sync(&cpr->dim.work);
7244
c0c050c5 7245 napi_disable(&bp->bnapi[i]->napi);
0bc0b97f 7246 }
c0c050c5
MC		 7247}
7248
7249static void bnxt_enable_napi(struct bnxt *bp)
7250{
7251 int i;
7252
7253 for (i = 0; i < bp->cp_nr_rings; i++) {
6a8788f2 7254 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
fa7e2812 7255 bp->bnapi[i]->in_reset = false;
6a8788f2
AG		 7256
7257 if (bp->bnapi[i]->rx_ring) {
7258 INIT_WORK(&cpr->dim.work, bnxt_dim_work);
7259 cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
7260 }
c0c050c5
MC		 7261 napi_enable(&bp->bnapi[i]->napi);
7262 }
7263}
7264
7df4ae9f 7265void bnxt_tx_disable(struct bnxt *bp)
c0c050c5
MC		 7266{
7267 int i;
c0c050c5 7268 struct bnxt_tx_ring_info *txr;
c0c050c5 7269
b6ab4b01 7270 if (bp->tx_ring) {
c0c050c5 7271 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 7272 txr = &bp->tx_ring[i];
c0c050c5 7273 txr->dev_state = BNXT_DEV_STATE_CLOSING;
c0c050c5
MC		 7274 }
7275 }
7276 /* Stop all TX queues */
7277 netif_tx_disable(bp->dev);
7278 netif_carrier_off(bp->dev);
7279}
7280
7df4ae9f 7281void bnxt_tx_enable(struct bnxt *bp)
c0c050c5
MC		 7282{
7283 int i;
c0c050c5 7284 struct bnxt_tx_ring_info *txr;
c0c050c5
MC		 7285
7286 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 7287 txr = &bp->tx_ring[i];
c0c050c5
MC		 7288 txr->dev_state = 0;
7289 }
7290 netif_tx_wake_all_queues(bp->dev);
7291 if (bp->link_info.link_up)
7292 netif_carrier_on(bp->dev);
7293}
7294
7295static void bnxt_report_link(struct bnxt *bp)
7296{
7297 if (bp->link_info.link_up) {
7298 const char *duplex;
7299 const char *flow_ctrl;
38a21b34
DK		 7300 u32 speed;
7301 u16 fec;
c0c050c5
MC		 7302
7303 netif_carrier_on(bp->dev);
7304 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
7305 duplex = "full";
7306 else
7307 duplex = "half";
7308 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
7309 flow_ctrl = "ON - receive & transmit";
7310 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
7311 flow_ctrl = "ON - transmit";
7312 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
7313 flow_ctrl = "ON - receive";
7314 else
7315 flow_ctrl = "none";
7316 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
38a21b34 7317 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
c0c050c5 7318 speed, duplex, flow_ctrl);
170ce013
MC		 7319 if (bp->flags & BNXT_FLAG_EEE_CAP)
7320 netdev_info(bp->dev, "EEE is %s\n",
7321 bp->eee.eee_active ? "active" :
7322 "not active");
e70c752f
MC		 7323 fec = bp->link_info.fec_cfg;
7324 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
7325 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
7326 (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
7327 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
7328 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
c0c050c5
MC		 7329 } else {
7330 netif_carrier_off(bp->dev);
7331 netdev_err(bp->dev, "NIC Link is Down\n");
7332 }
7333}
7334
170ce013
MC		 7335static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
7336{
7337 int rc = 0;
7338 struct hwrm_port_phy_qcaps_input req = {0};
7339 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
93ed8117 7340 struct bnxt_link_info *link_info = &bp->link_info;
170ce013
MC		 7341
7342 if (bp->hwrm_spec_code < 0x10201)
7343 return 0;
7344
7345 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
7346
7347 mutex_lock(&bp->hwrm_cmd_lock);
7348 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7349 if (rc)
7350 goto hwrm_phy_qcaps_exit;
7351
acb20054 7352 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
170ce013
MC		 7353 struct ethtool_eee *eee = &bp->eee;
7354 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
7355
7356 bp->flags |= BNXT_FLAG_EEE_CAP;
7357 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7358 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
7359 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
7360 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
7361 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
7362 }
55fd0cf3
MC		 7363 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) {
7364 if (bp->test_info)
7365 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK;
7366 }
520ad89a
MC		 7367 if (resp->supported_speeds_auto_mode)
7368 link_info->support_auto_speeds =
7369 le16_to_cpu(resp->supported_speeds_auto_mode);
170ce013 7370
d5430d31
MC		 7371 bp->port_count = resp->port_cnt;
7372
170ce013
MC		 7373hwrm_phy_qcaps_exit:
7374 mutex_unlock(&bp->hwrm_cmd_lock);
7375 return rc;
7376}
7377
c0c050c5
MC		 7378static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
7379{
7380 int rc = 0;
7381 struct bnxt_link_info *link_info = &bp->link_info;
7382 struct hwrm_port_phy_qcfg_input req = {0};
7383 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
7384 u8 link_up = link_info->link_up;
286ef9d6 7385 u16 diff;
c0c050c5
MC		 7386
7387 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
7388
7389 mutex_lock(&bp->hwrm_cmd_lock);
7390 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7391 if (rc) {
7392 mutex_unlock(&bp->hwrm_cmd_lock);
7393 return rc;
7394 }
7395
7396 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
7397 link_info->phy_link_status = resp->link;
acb20054
MC		 7398 link_info->duplex = resp->duplex_cfg;
7399 if (bp->hwrm_spec_code >= 0x10800)
7400 link_info->duplex = resp->duplex_state;
c0c050c5
MC		 7401 link_info->pause = resp->pause;
7402 link_info->auto_mode = resp->auto_mode;
7403 link_info->auto_pause_setting = resp->auto_pause;
3277360e 7404 link_info->lp_pause = resp->link_partner_adv_pause;
c0c050c5 7405 link_info->force_pause_setting = resp->force_pause;
acb20054 7406 link_info->duplex_setting = resp->duplex_cfg;
c0c050c5
MC		 7407 if (link_info->phy_link_status == BNXT_LINK_LINK)
7408 link_info->link_speed = le16_to_cpu(resp->link_speed);
7409 else
7410 link_info->link_speed = 0;
7411 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
c0c050c5
MC		 7412 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
7413 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
3277360e
MC		 7414 link_info->lp_auto_link_speeds =
7415 le16_to_cpu(resp->link_partner_adv_speeds);
c0c050c5
MC		 7416 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
7417 link_info->phy_ver[0] = resp->phy_maj;
7418 link_info->phy_ver[1] = resp->phy_min;
7419 link_info->phy_ver[2] = resp->phy_bld;
7420 link_info->media_type = resp->media_type;
03efbec0 7421 link_info->phy_type = resp->phy_type;
11f15ed3 7422 link_info->transceiver = resp->xcvr_pkg_type;
170ce013
MC		 7423 link_info->phy_addr = resp->eee_config_phy_addr &
7424 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
42ee18fe 7425 link_info->module_status = resp->module_status;
170ce013
MC		 7426
7427 if (bp->flags & BNXT_FLAG_EEE_CAP) {
7428 struct ethtool_eee *eee = &bp->eee;
7429 u16 fw_speeds;
7430
7431 eee->eee_active = 0;
7432 if (resp->eee_config_phy_addr &
7433 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
7434 eee->eee_active = 1;
7435 fw_speeds = le16_to_cpu(
7436 resp->link_partner_adv_eee_link_speed_mask);
7437 eee->lp_advertised =
7438 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7439 }
7440
7441 /* Pull initial EEE config */
7442 if (!chng_link_state) {
7443 if (resp->eee_config_phy_addr &
7444 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
7445 eee->eee_enabled = 1;
c0c050c5 7446
170ce013
MC		 7447 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
7448 eee->advertised =
7449 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7450
7451 if (resp->eee_config_phy_addr &
7452 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
7453 __le32 tmr;
7454
7455 eee->tx_lpi_enabled = 1;
7456 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
7457 eee->tx_lpi_timer = le32_to_cpu(tmr) &
7458 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
7459 }
7460 }
7461 }
e70c752f
MC		 7462
7463 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
7464 if (bp->hwrm_spec_code >= 0x10504)
7465 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
7466
c0c050c5
MC		 7467 /* TODO: need to add more logic to report VF link */
7468 if (chng_link_state) {
7469 if (link_info->phy_link_status == BNXT_LINK_LINK)
7470 link_info->link_up = 1;
7471 else
7472 link_info->link_up = 0;
7473 if (link_up != link_info->link_up)
7474 bnxt_report_link(bp);
7475 } else {
7476 /* alwasy link down if not require to update link state */
7477 link_info->link_up = 0;
7478 }
7479 mutex_unlock(&bp->hwrm_cmd_lock);
286ef9d6 7480
dac04907
MC		 7481 if (!BNXT_SINGLE_PF(bp))
7482 return 0;
7483
286ef9d6
MC		 7484 diff = link_info->support_auto_speeds ^ link_info->advertising;
7485 if ((link_info->support_auto_speeds | diff) !=
7486 link_info->support_auto_speeds) {
7487 /* An advertised speed is no longer supported, so we need to
0eaa24b9
MC		 7488 * update the advertisement settings. Caller holds RTNL
7489 * so we can modify link settings.
286ef9d6 7490 */
286ef9d6 7491 link_info->advertising = link_info->support_auto_speeds;
0eaa24b9 7492 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
286ef9d6 7493 bnxt_hwrm_set_link_setting(bp, true, false);
286ef9d6 7494 }
c0c050c5
MC		 7495 return 0;
7496}
7497
10289bec
MC		 7498static void bnxt_get_port_module_status(struct bnxt *bp)
7499{
7500 struct bnxt_link_info *link_info = &bp->link_info;
7501 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
7502 u8 module_status;
7503
7504 if (bnxt_update_link(bp, true))
7505 return;
7506
7507 module_status = link_info->module_status;
7508 switch (module_status) {
7509 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
7510 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
7511 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
7512 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
7513 bp->pf.port_id);
7514 if (bp->hwrm_spec_code >= 0x10201) {
7515 netdev_warn(bp->dev, "Module part number %s\n",
7516 resp->phy_vendor_partnumber);
7517 }
7518 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
7519 netdev_warn(bp->dev, "TX is disabled\n");
7520 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
7521 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
7522 }
7523}
7524
c0c050c5
MC		 7525static void
7526bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
7527{
7528 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
c9ee9516
MC		 7529 if (bp->hwrm_spec_code >= 0x10201)
7530 req->auto_pause =
7531 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
c0c050c5
MC		 7532 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
7533 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
7534 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
49b5c7a1 7535 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
c0c050c5
MC		 7536 req->enables |=
7537 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
7538 } else {
7539 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
7540 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
7541 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
7542 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
7543 req->enables |=
7544 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
c9ee9516
MC		 7545 if (bp->hwrm_spec_code >= 0x10201) {
7546 req->auto_pause = req->force_pause;
7547 req->enables |= cpu_to_le32(
7548 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
7549 }
c0c050c5
MC		 7550 }
7551}
7552
7553static void bnxt_hwrm_set_link_common(struct bnxt *bp,
7554 struct hwrm_port_phy_cfg_input *req)
7555{
7556 u8 autoneg = bp->link_info.autoneg;
7557 u16 fw_link_speed = bp->link_info.req_link_speed;
68515a18 7558 u16 advertising = bp->link_info.advertising;
c0c050c5
MC		 7559
7560 if (autoneg & BNXT_AUTONEG_SPEED) {
7561 req->auto_mode |=
11f15ed3 7562 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
c0c050c5
MC		 7563
7564 req->enables |= cpu_to_le32(
7565 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
7566 req->auto_link_speed_mask = cpu_to_le16(advertising);
7567
7568 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
7569 req->flags |=
7570 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
7571 } else {
7572 req->force_link_speed = cpu_to_le16(fw_link_speed);
7573 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
7574 }
7575
c0c050c5
MC		 7576 /* tell chimp that the setting takes effect immediately */
7577 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
7578}
7579
7580int bnxt_hwrm_set_pause(struct bnxt *bp)
7581{
7582 struct hwrm_port_phy_cfg_input req = {0};
7583 int rc;
7584
7585 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
7586 bnxt_hwrm_set_pause_common(bp, &req);
7587
7588 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
7589 bp->link_info.force_link_chng)
7590 bnxt_hwrm_set_link_common(bp, &req);
7591
7592 mutex_lock(&bp->hwrm_cmd_lock);
7593 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7594 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
7595 /* since changing of pause setting doesn't trigger any link
7596 * change event, the driver needs to update the current pause
7597 * result upon successfully return of the phy_cfg command
7598 */
7599 bp->link_info.pause =
7600 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
7601 bp->link_info.auto_pause_setting = 0;
7602 if (!bp->link_info.force_link_chng)
7603 bnxt_report_link(bp);
7604 }
7605 bp->link_info.force_link_chng = false;
7606 mutex_unlock(&bp->hwrm_cmd_lock);
7607 return rc;
7608}
7609
939f7f0c
MC		 7610static void bnxt_hwrm_set_eee(struct bnxt *bp,
7611 struct hwrm_port_phy_cfg_input *req)
7612{
7613 struct ethtool_eee *eee = &bp->eee;
7614
7615 if (eee->eee_enabled) {
7616 u16 eee_speeds;
7617 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
7618
7619 if (eee->tx_lpi_enabled)
7620 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
7621 else
7622 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
7623
7624 req->flags |= cpu_to_le32(flags);
7625 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
7626 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
7627 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
7628 } else {
7629 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
7630 }
7631}
7632
7633int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
c0c050c5
MC		 7634{
7635 struct hwrm_port_phy_cfg_input req = {0};
7636
7637 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
7638 if (set_pause)
7639 bnxt_hwrm_set_pause_common(bp, &req);
7640
7641 bnxt_hwrm_set_link_common(bp, &req);
939f7f0c
MC		 7642
7643 if (set_eee)
7644 bnxt_hwrm_set_eee(bp, &req);
c0c050c5
MC		 7645 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7646}
7647
33f7d55f
MC		 7648static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
7649{
7650 struct hwrm_port_phy_cfg_input req = {0};
7651
567b2abe 7652 if (!BNXT_SINGLE_PF(bp))
33f7d55f
MC		 7653 return 0;
7654
7655 if (pci_num_vf(bp->pdev))
7656 return 0;
7657
7658 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
16d663a6 7659 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
33f7d55f
MC		 7660 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7661}
7662
25e1acd6
MC		 7663static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
7664{
7665 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
7666 struct hwrm_func_drv_if_change_input req = {0};
7667 bool resc_reinit = false;
7668 int rc;
7669
7670 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
7671 return 0;
7672
7673 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
7674 if (up)
7675 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
7676 mutex_lock(&bp->hwrm_cmd_lock);
7677 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7678 if (!rc && (resp->flags &
7679 cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)))
7680 resc_reinit = true;
7681 mutex_unlock(&bp->hwrm_cmd_lock);
7682
7683 if (up && resc_reinit && BNXT_NEW_RM(bp)) {
7684 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7685
7686 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
7687 hw_resc->resv_cp_rings = 0;
7688 hw_resc->resv_tx_rings = 0;
7689 hw_resc->resv_rx_rings = 0;
7690 hw_resc->resv_hw_ring_grps = 0;
7691 hw_resc->resv_vnics = 0;
6b95c3e9
MC		 7692 bp->tx_nr_rings = 0;
7693 bp->rx_nr_rings = 0;
25e1acd6
MC		 7694 }
7695 return rc;
7696}
7697
5ad2cbee
MC		 7698static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
7699{
7700 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7701 struct hwrm_port_led_qcaps_input req = {0};
7702 struct bnxt_pf_info *pf = &bp->pf;
7703 int rc;
7704
7705 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
7706 return 0;
7707
7708 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
7709 req.port_id = cpu_to_le16(pf->port_id);
7710 mutex_lock(&bp->hwrm_cmd_lock);
7711 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7712 if (rc) {
7713 mutex_unlock(&bp->hwrm_cmd_lock);
7714 return rc;
7715 }
7716 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
7717 int i;
7718
7719 bp->num_leds = resp->num_leds;
7720 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
7721 bp->num_leds);
7722 for (i = 0; i < bp->num_leds; i++) {
7723 struct bnxt_led_info *led = &bp->leds[i];
7724 __le16 caps = led->led_state_caps;
7725
7726 if (!led->led_group_id ||
7727 !BNXT_LED_ALT_BLINK_CAP(caps)) {
7728 bp->num_leds = 0;
7729 break;
7730 }
7731 }
7732 }
7733 mutex_unlock(&bp->hwrm_cmd_lock);
7734 return 0;
7735}
7736
5282db6c
MC		 7737int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
7738{
7739 struct hwrm_wol_filter_alloc_input req = {0};
7740 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
7741 int rc;
7742
7743 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
7744 req.port_id = cpu_to_le16(bp->pf.port_id);
7745 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
7746 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
7747 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
7748 mutex_lock(&bp->hwrm_cmd_lock);
7749 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7750 if (!rc)
7751 bp->wol_filter_id = resp->wol_filter_id;
7752 mutex_unlock(&bp->hwrm_cmd_lock);
7753 return rc;
7754}
7755
7756int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
7757{
7758 struct hwrm_wol_filter_free_input req = {0};
7759 int rc;
7760
7761 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
7762 req.port_id = cpu_to_le16(bp->pf.port_id);
7763 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
7764 req.wol_filter_id = bp->wol_filter_id;
7765 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7766 return rc;
7767}
7768
c1ef146a
MC		 7769static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
7770{
7771 struct hwrm_wol_filter_qcfg_input req = {0};
7772 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
7773 u16 next_handle = 0;
7774 int rc;
7775
7776 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
7777 req.port_id = cpu_to_le16(bp->pf.port_id);
7778 req.handle = cpu_to_le16(handle);
7779 mutex_lock(&bp->hwrm_cmd_lock);
7780 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7781 if (!rc) {
7782 next_handle = le16_to_cpu(resp->next_handle);
7783 if (next_handle != 0) {
7784 if (resp->wol_type ==
7785 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
7786 bp->wol = 1;
7787 bp->wol_filter_id = resp->wol_filter_id;
7788 }
7789 }
7790 }
7791 mutex_unlock(&bp->hwrm_cmd_lock);
7792 return next_handle;
7793}
7794
7795static void bnxt_get_wol_settings(struct bnxt *bp)
7796{
7797 u16 handle = 0;
7798
7799 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
7800 return;
7801
7802 do {
7803 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
7804 } while (handle && handle != 0xffff);
7805}
7806
cde49a42
VV		 7807#ifdef CONFIG_BNXT_HWMON
7808static ssize_t bnxt_show_temp(struct device *dev,
7809 struct device_attribute *devattr, char *buf)
7810{
7811 struct hwrm_temp_monitor_query_input req = {0};
7812 struct hwrm_temp_monitor_query_output *resp;
7813 struct bnxt *bp = dev_get_drvdata(dev);
7814 u32 temp = 0;
7815
7816 resp = bp->hwrm_cmd_resp_addr;
7817 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
7818 mutex_lock(&bp->hwrm_cmd_lock);
7819 if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT))
7820 temp = resp->temp * 1000; /* display millidegree */
7821 mutex_unlock(&bp->hwrm_cmd_lock);
7822
7823 return sprintf(buf, "%u\n", temp);
7824}
7825static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
7826
7827static struct attribute *bnxt_attrs[] = {
7828 &sensor_dev_attr_temp1_input.dev_attr.attr,
7829 NULL
7830};
7831ATTRIBUTE_GROUPS(bnxt);
7832
7833static void bnxt_hwmon_close(struct bnxt *bp)
7834{
7835 if (bp->hwmon_dev) {
7836 hwmon_device_unregister(bp->hwmon_dev);
7837 bp->hwmon_dev = NULL;
7838 }
7839}
7840
7841static void bnxt_hwmon_open(struct bnxt *bp)
7842{
7843 struct pci_dev *pdev = bp->pdev;
7844
7845 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
7846 DRV_MODULE_NAME, bp,
7847 bnxt_groups);
7848 if (IS_ERR(bp->hwmon_dev)) {
7849 bp->hwmon_dev = NULL;
7850 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
7851 }
7852}
7853#else
7854static void bnxt_hwmon_close(struct bnxt *bp)
7855{
7856}
7857
7858static void bnxt_hwmon_open(struct bnxt *bp)
7859{
7860}
7861#endif
7862
939f7f0c
MC		 7863static bool bnxt_eee_config_ok(struct bnxt *bp)
7864{
7865 struct ethtool_eee *eee = &bp->eee;
7866 struct bnxt_link_info *link_info = &bp->link_info;
7867
7868 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
7869 return true;
7870
7871 if (eee->eee_enabled) {
7872 u32 advertising =
7873 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
7874
7875 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
7876 eee->eee_enabled = 0;
7877 return false;
7878 }
7879 if (eee->advertised & ~advertising) {
7880 eee->advertised = advertising & eee->supported;
7881 return false;
7882 }
7883 }
7884 return true;
7885}
7886
c0c050c5
MC		 7887static int bnxt_update_phy_setting(struct bnxt *bp)
7888{
7889 int rc;
7890 bool update_link = false;
7891 bool update_pause = false;
939f7f0c 7892 bool update_eee = false;
c0c050c5
MC		 7893 struct bnxt_link_info *link_info = &bp->link_info;
7894
7895 rc = bnxt_update_link(bp, true);
7896 if (rc) {
7897 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
7898 rc);
7899 return rc;
7900 }
33dac24a
MC		 7901 if (!BNXT_SINGLE_PF(bp))
7902 return 0;
7903
c0c050c5 7904 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
c9ee9516
MC		 7905 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
7906 link_info->req_flow_ctrl)
c0c050c5
MC		 7907 update_pause = true;
7908 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
7909 link_info->force_pause_setting != link_info->req_flow_ctrl)
7910 update_pause = true;
c0c050c5
MC		 7911 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
7912 if (BNXT_AUTO_MODE(link_info->auto_mode))
7913 update_link = true;
7914 if (link_info->req_link_speed != link_info->force_link_speed)
7915 update_link = true;
de73018f
MC		 7916 if (link_info->req_duplex != link_info->duplex_setting)
7917 update_link = true;
c0c050c5
MC		 7918 } else {
7919 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
7920 update_link = true;
7921 if (link_info->advertising != link_info->auto_link_speeds)
7922 update_link = true;
c0c050c5
MC		 7923 }
7924
16d663a6
MC		 7925 /* The last close may have shutdown the link, so need to call
7926 * PHY_CFG to bring it back up.
7927 */
7928 if (!netif_carrier_ok(bp->dev))
7929 update_link = true;
7930
939f7f0c
MC		 7931 if (!bnxt_eee_config_ok(bp))
7932 update_eee = true;
7933
c0c050c5 7934 if (update_link)
939f7f0c 7935 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
c0c050c5
MC		 7936 else if (update_pause)
7937 rc = bnxt_hwrm_set_pause(bp);
7938 if (rc) {
7939 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
7940 rc);
7941 return rc;
7942 }
7943
7944 return rc;
7945}
7946
11809490
JH		 7947/* Common routine to pre-map certain register block to different GRC window.
7948 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
7949 * in PF and 3 windows in VF that can be customized to map in different
7950 * register blocks.
7951 */
7952static void bnxt_preset_reg_win(struct bnxt *bp)
7953{
7954 if (BNXT_PF(bp)) {
7955 /* CAG registers map to GRC window #4 */
7956 writel(BNXT_CAG_REG_BASE,
7957 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
7958 }
7959}
7960
47558acd
MC		 7961static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
7962
c0c050c5
MC		 7963static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
7964{
7965 int rc = 0;
7966
11809490 7967 bnxt_preset_reg_win(bp);
c0c050c5
MC		 7968 netif_carrier_off(bp->dev);
7969 if (irq_re_init) {
47558acd
MC		 7970 /* Reserve rings now if none were reserved at driver probe. */
7971 rc = bnxt_init_dflt_ring_mode(bp);
7972 if (rc) {
7973 netdev_err(bp->dev, "Failed to reserve default rings at open\n");
7974 return rc;
7975 }
c0c050c5 7976 }
41e8d798
MC		 7977 rc = bnxt_reserve_rings(bp);
7978 if (rc)
7979 return rc;
c0c050c5
MC		 7980 if ((bp->flags & BNXT_FLAG_RFS) &&
7981 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
7982 /* disable RFS if falling back to INTA */
7983 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
7984 bp->flags &= ~BNXT_FLAG_RFS;
7985 }
7986
7987 rc = bnxt_alloc_mem(bp, irq_re_init);
7988 if (rc) {
7989 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
7990 goto open_err_free_mem;
7991 }
7992
7993 if (irq_re_init) {
7994 bnxt_init_napi(bp);
7995 rc = bnxt_request_irq(bp);
7996 if (rc) {
7997 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
c58387ab 7998 goto open_err_irq;
c0c050c5
MC		 7999 }
8000 }
8001
8002 bnxt_enable_napi(bp);
cabfb09d 8003 bnxt_debug_dev_init(bp);
c0c050c5
MC		 8004
8005 rc = bnxt_init_nic(bp, irq_re_init);
8006 if (rc) {
8007 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8008 goto open_err;
8009 }
8010
8011 if (link_re_init) {
e2dc9b6e 8012 mutex_lock(&bp->link_lock);
c0c050c5 8013 rc = bnxt_update_phy_setting(bp);
e2dc9b6e 8014 mutex_unlock(&bp->link_lock);
a1ef4a79 8015 if (rc) {
ba41d46f 8016 netdev_warn(bp->dev, "failed to update phy settings\n");
a1ef4a79
MC		 8017 if (BNXT_SINGLE_PF(bp)) {
8018 bp->link_info.phy_retry = true;
8019 bp->link_info.phy_retry_expires =
8020 jiffies + 5 * HZ;
8021 }
8022 }
c0c050c5
MC		 8023 }
8024
7cdd5fc3 8025 if (irq_re_init)
ad51b8e9 8026 udp_tunnel_get_rx_info(bp->dev);
c0c050c5 8027
caefe526 8028 set_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 8029 bnxt_enable_int(bp);
8030 /* Enable TX queues */
8031 bnxt_tx_enable(bp);
8032 mod_timer(&bp->timer, jiffies + bp->current_interval);
10289bec
MC		 8033 /* Poll link status and check for SFP+ module status */
8034 bnxt_get_port_module_status(bp);
c0c050c5 8035
ee5c7fb3
SP		 8036 /* VF-reps may need to be re-opened after the PF is re-opened */
8037 if (BNXT_PF(bp))
8038 bnxt_vf_reps_open(bp);
c0c050c5
MC		 8039 return 0;
8040
8041open_err:
cabfb09d 8042 bnxt_debug_dev_exit(bp);
c0c050c5 8043 bnxt_disable_napi(bp);
c58387ab
VG		 8044
8045open_err_irq:
c0c050c5
MC		 8046 bnxt_del_napi(bp);
8047
8048open_err_free_mem:
8049 bnxt_free_skbs(bp);
8050 bnxt_free_irq(bp);
8051 bnxt_free_mem(bp, true);
8052 return rc;
8053}
8054
8055/* rtnl_lock held */
8056int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8057{
8058 int rc = 0;
8059
8060 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
8061 if (rc) {
8062 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
8063 dev_close(bp->dev);
8064 }
8065 return rc;
8066}
8067
f7dc1ea6
MC		 8068/* rtnl_lock held, open the NIC half way by allocating all resources, but
8069 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
8070 * self tests.
8071 */
8072int bnxt_half_open_nic(struct bnxt *bp)
8073{
8074 int rc = 0;
8075
8076 rc = bnxt_alloc_mem(bp, false);
8077 if (rc) {
8078 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8079 goto half_open_err;
8080 }
8081 rc = bnxt_init_nic(bp, false);
8082 if (rc) {
8083 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8084 goto half_open_err;
8085 }
8086 return 0;
8087
8088half_open_err:
8089 bnxt_free_skbs(bp);
8090 bnxt_free_mem(bp, false);
8091 dev_close(bp->dev);
8092 return rc;
8093}
8094
8095/* rtnl_lock held, this call can only be made after a previous successful
8096 * call to bnxt_half_open_nic().
8097 */
8098void bnxt_half_close_nic(struct bnxt *bp)
8099{
8100 bnxt_hwrm_resource_free(bp, false, false);
8101 bnxt_free_skbs(bp);
8102 bnxt_free_mem(bp, false);
8103}
8104
c0c050c5
MC		 8105static int bnxt_open(struct net_device *dev)
8106{
8107 struct bnxt *bp = netdev_priv(dev);
25e1acd6 8108 int rc;
c0c050c5 8109
25e1acd6
MC		 8110 bnxt_hwrm_if_change(bp, true);
8111 rc = __bnxt_open_nic(bp, true, true);
8112 if (rc)
8113 bnxt_hwrm_if_change(bp, false);
cde49a42
VV		 8114
8115 bnxt_hwmon_open(bp);
8116
25e1acd6 8117 return rc;
c0c050c5
MC		 8118}
8119
f9b76ebd
MC		 8120static bool bnxt_drv_busy(struct bnxt *bp)
8121{
8122 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
8123 test_bit(BNXT_STATE_READ_STATS, &bp->state));
8124}
8125
86e953db
MC		 8126static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
8127 bool link_re_init)
c0c050c5 8128{
ee5c7fb3
SP		 8129 /* Close the VF-reps before closing PF */
8130 if (BNXT_PF(bp))
8131 bnxt_vf_reps_close(bp);
86e953db 8132
c0c050c5
MC		 8133 /* Change device state to avoid TX queue wake up's */
8134 bnxt_tx_disable(bp);
8135
caefe526 8136 clear_bit(BNXT_STATE_OPEN, &bp->state);
4cebdcec 8137 smp_mb__after_atomic();
f9b76ebd 8138 while (bnxt_drv_busy(bp))
4cebdcec 8139 msleep(20);
c0c050c5 8140
9d8bc097 8141 /* Flush rings and and disable interrupts */
c0c050c5
MC		 8142 bnxt_shutdown_nic(bp, irq_re_init);
8143
8144 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
8145
cabfb09d 8146 bnxt_debug_dev_exit(bp);
c0c050c5 8147 bnxt_disable_napi(bp);
c0c050c5
MC		 8148 del_timer_sync(&bp->timer);
8149 bnxt_free_skbs(bp);
8150
8151 if (irq_re_init) {
8152 bnxt_free_irq(bp);
8153 bnxt_del_napi(bp);
8154 }
8155 bnxt_free_mem(bp, irq_re_init);
86e953db
MC		 8156}
8157
8158int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8159{
8160 int rc = 0;
8161
8162#ifdef CONFIG_BNXT_SRIOV
8163 if (bp->sriov_cfg) {
8164 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
8165 !bp->sriov_cfg,
8166 BNXT_SRIOV_CFG_WAIT_TMO);
8167 if (rc)
8168 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
8169 }
8170#endif
8171 __bnxt_close_nic(bp, irq_re_init, link_re_init);
c0c050c5
MC		 8172 return rc;
8173}
8174
8175static int bnxt_close(struct net_device *dev)
8176{
8177 struct bnxt *bp = netdev_priv(dev);
8178
cde49a42 8179 bnxt_hwmon_close(bp);
c0c050c5 8180 bnxt_close_nic(bp, true, true);
33f7d55f 8181 bnxt_hwrm_shutdown_link(bp);
25e1acd6 8182 bnxt_hwrm_if_change(bp, false);
c0c050c5
MC		 8183 return 0;
8184}
8185
8186/* rtnl_lock held */
8187static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8188{
8189 switch (cmd) {
8190 case SIOCGMIIPHY:
8191 /* fallthru */
8192 case SIOCGMIIREG: {
8193 if (!netif_running(dev))
8194 return -EAGAIN;
8195
8196 return 0;
8197 }
8198
8199 case SIOCSMIIREG:
8200 if (!netif_running(dev))
8201 return -EAGAIN;
8202
8203 return 0;
8204
8205 default:
8206 /* do nothing */
8207 break;
8208 }
8209 return -EOPNOTSUPP;
8210}
8211
bc1f4470 8212static void
c0c050c5
MC		 8213bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
8214{
8215 u32 i;
8216 struct bnxt *bp = netdev_priv(dev);
8217
f9b76ebd
MC		 8218 set_bit(BNXT_STATE_READ_STATS, &bp->state);
8219 /* Make sure bnxt_close_nic() sees that we are reading stats before
8220 * we check the BNXT_STATE_OPEN flag.
8221 */
8222 smp_mb__after_atomic();
8223 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
8224 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
bc1f4470 8225 return;
f9b76ebd 8226 }
c0c050c5
MC		 8227
8228 /* TODO check if we need to synchronize with bnxt_close path */
8229 for (i = 0; i < bp->cp_nr_rings; i++) {
8230 struct bnxt_napi *bnapi = bp->bnapi[i];
8231 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
8232 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
8233
8234 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
8235 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
8236 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
8237
8238 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
8239 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
8240 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
8241
8242 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
8243 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
8244 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
8245
8246 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
8247 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
8248 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
8249
8250 stats->rx_missed_errors +=
8251 le64_to_cpu(hw_stats->rx_discard_pkts);
8252
8253 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
8254
c0c050c5
MC		 8255 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
8256 }
8257
9947f83f
MC		 8258 if (bp->flags & BNXT_FLAG_PORT_STATS) {
8259 struct rx_port_stats *rx = bp->hw_rx_port_stats;
8260 struct tx_port_stats *tx = bp->hw_tx_port_stats;
8261
8262 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
8263 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
8264 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
8265 le64_to_cpu(rx->rx_ovrsz_frames) +
8266 le64_to_cpu(rx->rx_runt_frames);
8267 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
8268 le64_to_cpu(rx->rx_jbr_frames);
8269 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
8270 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
8271 stats->tx_errors = le64_to_cpu(tx->tx_err);
8272 }
f9b76ebd 8273 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
c0c050c5
MC		 8274}
8275
8276static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
8277{
8278 struct net_device *dev = bp->dev;
8279 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8280 struct netdev_hw_addr *ha;
8281 u8 *haddr;
8282 int mc_count = 0;
8283 bool update = false;
8284 int off = 0;
8285
8286 netdev_for_each_mc_addr(ha, dev) {
8287 if (mc_count >= BNXT_MAX_MC_ADDRS) {
8288 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8289 vnic->mc_list_count = 0;
8290 return false;
8291 }
8292 haddr = ha->addr;
8293 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
8294 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
8295 update = true;
8296 }
8297 off += ETH_ALEN;
8298 mc_count++;
8299 }
8300 if (mc_count)
8301 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
8302
8303 if (mc_count != vnic->mc_list_count) {
8304 vnic->mc_list_count = mc_count;
8305 update = true;
8306 }
8307 return update;
8308}
8309
8310static bool bnxt_uc_list_updated(struct bnxt *bp)
8311{
8312 struct net_device *dev = bp->dev;
8313 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8314 struct netdev_hw_addr *ha;
8315 int off = 0;
8316
8317 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
8318 return true;
8319
8320 netdev_for_each_uc_addr(ha, dev) {
8321 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
8322 return true;
8323
8324 off += ETH_ALEN;
8325 }
8326 return false;
8327}
8328
8329static void bnxt_set_rx_mode(struct net_device *dev)
8330{
8331 struct bnxt *bp = netdev_priv(dev);
8332 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8333 u32 mask = vnic->rx_mask;
8334 bool mc_update = false;
8335 bool uc_update;
8336
8337 if (!netif_running(dev))
8338 return;
8339
8340 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
8341 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
30e33848
MC		 8342 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
8343 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
c0c050c5 8344
17c71ac3 8345 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
c0c050c5
MC		 8346 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
8347
8348 uc_update = bnxt_uc_list_updated(bp);
8349
30e33848
MC		 8350 if (dev->flags & IFF_BROADCAST)
8351 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
c0c050c5
MC		 8352 if (dev->flags & IFF_ALLMULTI) {
8353 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8354 vnic->mc_list_count = 0;
8355 } else {
8356 mc_update = bnxt_mc_list_updated(bp, &mask);
8357 }
8358
8359 if (mask != vnic->rx_mask || uc_update || mc_update) {
8360 vnic->rx_mask = mask;
8361
8362 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
c213eae8 8363 bnxt_queue_sp_work(bp);
c0c050c5
MC		 8364 }
8365}
8366
b664f008 8367static int bnxt_cfg_rx_mode(struct bnxt *bp)
c0c050c5
MC		 8368{
8369 struct net_device *dev = bp->dev;
8370 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8371 struct netdev_hw_addr *ha;
8372 int i, off = 0, rc;
8373 bool uc_update;
8374
8375 netif_addr_lock_bh(dev);
8376 uc_update = bnxt_uc_list_updated(bp);
8377 netif_addr_unlock_bh(dev);
8378
8379 if (!uc_update)
8380 goto skip_uc;
8381
8382 mutex_lock(&bp->hwrm_cmd_lock);
8383 for (i = 1; i < vnic->uc_filter_count; i++) {
8384 struct hwrm_cfa_l2_filter_free_input req = {0};
8385
8386 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
8387 -1);
8388
8389 req.l2_filter_id = vnic->fw_l2_filter_id[i];
8390
8391 rc = _hwrm_send_message(bp, &req, sizeof(req),
8392 HWRM_CMD_TIMEOUT);
8393 }
8394 mutex_unlock(&bp->hwrm_cmd_lock);
8395
8396 vnic->uc_filter_count = 1;
8397
8398 netif_addr_lock_bh(dev);
8399 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
8400 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
8401 } else {
8402 netdev_for_each_uc_addr(ha, dev) {
8403 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
8404 off += ETH_ALEN;
8405 vnic->uc_filter_count++;
8406 }
8407 }
8408 netif_addr_unlock_bh(dev);
8409
8410 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
8411 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
8412 if (rc) {
8413 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
8414 rc);
8415 vnic->uc_filter_count = i;
b664f008 8416 return rc;
c0c050c5
MC		 8417 }
8418 }
8419
8420skip_uc:
8421 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
8422 if (rc)
8423 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
8424 rc);
b664f008
MC		 8425
8426 return rc;
c0c050c5
MC		 8427}
8428
2773dfb2
MC		 8429static bool bnxt_can_reserve_rings(struct bnxt *bp)
8430{
8431#ifdef CONFIG_BNXT_SRIOV
f1ca94de 8432 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
2773dfb2
MC		 8433 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8434
8435 /* No minimum rings were provisioned by the PF. Don't
8436 * reserve rings by default when device is down.
8437 */
8438 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
8439 return true;
8440
8441 if (!netif_running(bp->dev))
8442 return false;
8443 }
8444#endif
8445 return true;
8446}
8447
8079e8f1
MC		 8448/* If the chip and firmware supports RFS */
8449static bool bnxt_rfs_supported(struct bnxt *bp)
8450{
41e8d798
MC		 8451 if (bp->flags & BNXT_FLAG_CHIP_P5)
8452 return false;
8079e8f1
MC		 8453 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
8454 return true;
ae10ae74
MC		 8455 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
8456 return true;
8079e8f1
MC		 8457 return false;
8458}
8459
8460/* If runtime conditions support RFS */
2bcfa6f6
MC		 8461static bool bnxt_rfs_capable(struct bnxt *bp)
8462{
8463#ifdef CONFIG_RFS_ACCEL
8079e8f1 8464 int vnics, max_vnics, max_rss_ctxs;
2bcfa6f6 8465
41e8d798
MC		 8466 if (bp->flags & BNXT_FLAG_CHIP_P5)
8467 return false;
2773dfb2 8468 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
2bcfa6f6
MC		 8469 return false;
8470
8471 vnics = 1 + bp->rx_nr_rings;
8079e8f1
MC		 8472 max_vnics = bnxt_get_max_func_vnics(bp);
8473 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
ae10ae74
MC		 8474
8475 /* RSS contexts not a limiting factor */
8476 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
8477 max_rss_ctxs = max_vnics;
8079e8f1 8478 if (vnics > max_vnics || vnics > max_rss_ctxs) {
6a1eef5b
MC		 8479 if (bp->rx_nr_rings > 1)
8480 netdev_warn(bp->dev,
8481 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
8482 min(max_rss_ctxs - 1, max_vnics - 1));
2bcfa6f6 8483 return false;
a2304909 8484 }
2bcfa6f6 8485
f1ca94de 8486 if (!BNXT_NEW_RM(bp))
6a1eef5b
MC		 8487 return true;
8488
8489 if (vnics == bp->hw_resc.resv_vnics)
8490 return true;
8491
8492 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, vnics);
8493 if (vnics <= bp->hw_resc.resv_vnics)
8494 return true;
8495
8496 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
8497 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 1);
8498 return false;
2bcfa6f6
MC		 8499#else
8500 return false;
8501#endif
8502}
8503
c0c050c5
MC		 8504static netdev_features_t bnxt_fix_features(struct net_device *dev,
8505 netdev_features_t features)
8506{
2bcfa6f6
MC		 8507 struct bnxt *bp = netdev_priv(dev);
8508
a2304909 8509 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
2bcfa6f6 8510 features &= ~NETIF_F_NTUPLE;
5a9f6b23 8511
1054aee8
MC		 8512 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
8513 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
8514
8515 if (!(features & NETIF_F_GRO))
8516 features &= ~NETIF_F_GRO_HW;
8517
8518 if (features & NETIF_F_GRO_HW)
8519 features &= ~NETIF_F_LRO;
8520
5a9f6b23
MC		 8521 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
8522 * turned on or off together.
8523 */
8524 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
8525 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
8526 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
8527 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
8528 NETIF_F_HW_VLAN_STAG_RX);
8529 else
8530 features |= NETIF_F_HW_VLAN_CTAG_RX |
8531 NETIF_F_HW_VLAN_STAG_RX;
8532 }
cf6645f8
MC		 8533#ifdef CONFIG_BNXT_SRIOV
8534 if (BNXT_VF(bp)) {
8535 if (bp->vf.vlan) {
8536 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
8537 NETIF_F_HW_VLAN_STAG_RX);
8538 }
8539 }
8540#endif
c0c050c5
MC		 8541 return features;
8542}
8543
8544static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
8545{
8546 struct bnxt *bp = netdev_priv(dev);
8547 u32 flags = bp->flags;
8548 u32 changes;
8549 int rc = 0;
8550 bool re_init = false;
8551 bool update_tpa = false;
8552
8553 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
1054aee8 8554 if (features & NETIF_F_GRO_HW)
c0c050c5 8555 flags |= BNXT_FLAG_GRO;
1054aee8 8556 else if (features & NETIF_F_LRO)
c0c050c5
MC		 8557 flags |= BNXT_FLAG_LRO;
8558
bdbd1eb5
MC		 8559 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
8560 flags &= ~BNXT_FLAG_TPA;
8561
c0c050c5
MC		 8562 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8563 flags |= BNXT_FLAG_STRIP_VLAN;
8564
8565 if (features & NETIF_F_NTUPLE)
8566 flags |= BNXT_FLAG_RFS;
8567
8568 changes = flags ^ bp->flags;
8569 if (changes & BNXT_FLAG_TPA) {
8570 update_tpa = true;
8571 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
8572 (flags & BNXT_FLAG_TPA) == 0)
8573 re_init = true;
8574 }
8575
8576 if (changes & ~BNXT_FLAG_TPA)
8577 re_init = true;
8578
8579 if (flags != bp->flags) {
8580 u32 old_flags = bp->flags;
8581
8582 bp->flags = flags;
8583
2bcfa6f6 8584 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
c0c050c5
MC		 8585 if (update_tpa)
8586 bnxt_set_ring_params(bp);
8587 return rc;
8588 }
8589
8590 if (re_init) {
8591 bnxt_close_nic(bp, false, false);
8592 if (update_tpa)
8593 bnxt_set_ring_params(bp);
8594
8595 return bnxt_open_nic(bp, false, false);
8596 }
8597 if (update_tpa) {
8598 rc = bnxt_set_tpa(bp,
8599 (flags & BNXT_FLAG_TPA) ?
8600 true : false);
8601 if (rc)
8602 bp->flags = old_flags;
8603 }
8604 }
8605 return rc;
8606}
8607
9f554590
MC		 8608static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
8609{
b6ab4b01 8610 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9f554590
MC		 8611 int i = bnapi->index;
8612
3b2b7d9d
MC		 8613 if (!txr)
8614 return;
8615
9f554590
MC		 8616 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
8617 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
8618 txr->tx_cons);
8619}
8620
8621static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
8622{
b6ab4b01 8623 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9f554590
MC		 8624 int i = bnapi->index;
8625
3b2b7d9d
MC		 8626 if (!rxr)
8627 return;
8628
9f554590
MC		 8629 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
8630 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
8631 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
8632 rxr->rx_sw_agg_prod);
8633}
8634
8635static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
8636{
8637 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
8638 int i = bnapi->index;
8639
8640 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
8641 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
8642}
8643
c0c050c5
MC		 8644static void bnxt_dbg_dump_states(struct bnxt *bp)
8645{
8646 int i;
8647 struct bnxt_napi *bnapi;
c0c050c5
MC		 8648
8649 for (i = 0; i < bp->cp_nr_rings; i++) {
8650 bnapi = bp->bnapi[i];
c0c050c5 8651 if (netif_msg_drv(bp)) {
9f554590
MC		 8652 bnxt_dump_tx_sw_state(bnapi);
8653 bnxt_dump_rx_sw_state(bnapi);
8654 bnxt_dump_cp_sw_state(bnapi);
c0c050c5
MC		 8655 }
8656 }
8657}
8658
6988bd92 8659static void bnxt_reset_task(struct bnxt *bp, bool silent)
c0c050c5 8660{
6988bd92
MC		 8661 if (!silent)
8662 bnxt_dbg_dump_states(bp);
028de140 8663 if (netif_running(bp->dev)) {
b386cd36
MC		 8664 int rc;
8665
8666 if (!silent)
8667 bnxt_ulp_stop(bp);
028de140 8668 bnxt_close_nic(bp, false, false);
b386cd36
MC		 8669 rc = bnxt_open_nic(bp, false, false);
8670 if (!silent && !rc)
8671 bnxt_ulp_start(bp);
028de140 8672 }
c0c050c5
MC		 8673}
8674
8675static void bnxt_tx_timeout(struct net_device *dev)
8676{
8677 struct bnxt *bp = netdev_priv(dev);
8678
8679 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
8680 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
c213eae8 8681 bnxt_queue_sp_work(bp);
c0c050c5
MC		 8682}
8683
e99e88a9 8684static void bnxt_timer(struct timer_list *t)
c0c050c5 8685{
e99e88a9 8686 struct bnxt *bp = from_timer(bp, t, timer);
c0c050c5
MC		 8687 struct net_device *dev = bp->dev;
8688
8689 if (!netif_running(dev))
8690 return;
8691
8692 if (atomic_read(&bp->intr_sem) != 0)
8693 goto bnxt_restart_timer;
8694
adcc331e
MC		 8695 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
8696 bp->stats_coal_ticks) {
3bdf56c4 8697 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
c213eae8 8698 bnxt_queue_sp_work(bp);
3bdf56c4 8699 }
5a84acbe
SP		 8700
8701 if (bnxt_tc_flower_enabled(bp)) {
8702 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
8703 bnxt_queue_sp_work(bp);
8704 }
a1ef4a79
MC		 8705
8706 if (bp->link_info.phy_retry) {
8707 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
8708 bp->link_info.phy_retry = 0;
8709 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
8710 } else {
8711 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
8712 bnxt_queue_sp_work(bp);
8713 }
8714 }
c0c050c5
MC		 8715bnxt_restart_timer:
8716 mod_timer(&bp->timer, jiffies + bp->current_interval);
8717}
8718
a551ee94 8719static void bnxt_rtnl_lock_sp(struct bnxt *bp)
6988bd92 8720{
a551ee94
MC		 8721 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
8722 * set. If the device is being closed, bnxt_close() may be holding
6988bd92
MC		 8723 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
8724 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
8725 */
8726 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
8727 rtnl_lock();
a551ee94
MC		 8728}
8729
8730static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
8731{
6988bd92
MC		 8732 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
8733 rtnl_unlock();
8734}
8735
a551ee94
MC		 8736/* Only called from bnxt_sp_task() */
8737static void bnxt_reset(struct bnxt *bp, bool silent)
8738{
8739 bnxt_rtnl_lock_sp(bp);
8740 if (test_bit(BNXT_STATE_OPEN, &bp->state))
8741 bnxt_reset_task(bp, silent);
8742 bnxt_rtnl_unlock_sp(bp);
8743}
8744
c0c050c5
MC		 8745static void bnxt_cfg_ntp_filters(struct bnxt *);
8746
8747static void bnxt_sp_task(struct work_struct *work)
8748{
8749 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
c0c050c5 8750
4cebdcec
MC		 8751 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
8752 smp_mb__after_atomic();
8753 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
8754 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5 8755 return;
4cebdcec 8756 }
c0c050c5
MC		 8757
8758 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
8759 bnxt_cfg_rx_mode(bp);
8760
8761 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
8762 bnxt_cfg_ntp_filters(bp);
c0c050c5
MC		 8763 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
8764 bnxt_hwrm_exec_fwd_req(bp);
8765 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
8766 bnxt_hwrm_tunnel_dst_port_alloc(
8767 bp, bp->vxlan_port,
8768 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
8769 }
8770 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
8771 bnxt_hwrm_tunnel_dst_port_free(
8772 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
8773 }
7cdd5fc3
AD		 8774 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
8775 bnxt_hwrm_tunnel_dst_port_alloc(
8776 bp, bp->nge_port,
8777 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
8778 }
8779 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
8780 bnxt_hwrm_tunnel_dst_port_free(
8781 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
8782 }
00db3cba 8783 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
3bdf56c4 8784 bnxt_hwrm_port_qstats(bp);
00db3cba
VV		 8785 bnxt_hwrm_port_qstats_ext(bp);
8786 }
3bdf56c4 8787
0eaa24b9 8788 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
e2dc9b6e 8789 int rc;
0eaa24b9 8790
e2dc9b6e 8791 mutex_lock(&bp->link_lock);
0eaa24b9
MC		 8792 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
8793 &bp->sp_event))
8794 bnxt_hwrm_phy_qcaps(bp);
8795
e2dc9b6e
MC		 8796 rc = bnxt_update_link(bp, true);
8797 mutex_unlock(&bp->link_lock);
0eaa24b9
MC		 8798 if (rc)
8799 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
8800 rc);
8801 }
a1ef4a79
MC		 8802 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
8803 int rc;
8804
8805 mutex_lock(&bp->link_lock);
8806 rc = bnxt_update_phy_setting(bp);
8807 mutex_unlock(&bp->link_lock);
8808 if (rc) {
8809 netdev_warn(bp->dev, "update phy settings retry failed\n");
8810 } else {
8811 bp->link_info.phy_retry = false;
8812 netdev_info(bp->dev, "update phy settings retry succeeded\n");
8813 }
8814 }
90c694bb 8815 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
e2dc9b6e
MC		 8816 mutex_lock(&bp->link_lock);
8817 bnxt_get_port_module_status(bp);
8818 mutex_unlock(&bp->link_lock);
90c694bb 8819 }
5a84acbe
SP		 8820
8821 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
8822 bnxt_tc_flow_stats_work(bp);
8823
e2dc9b6e
MC		 8824 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
8825 * must be the last functions to be called before exiting.
8826 */
6988bd92
MC		 8827 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
8828 bnxt_reset(bp, false);
4cebdcec 8829
fc0f1929
MC		 8830 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
8831 bnxt_reset(bp, true);
8832
4cebdcec
MC		 8833 smp_mb__before_atomic();
8834 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5
MC		 8835}
8836
d1e7925e 8837/* Under rtnl_lock */
98fdbe73
MC		 8838int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
8839 int tx_xdp)
d1e7925e
MC		 8840{
8841 int max_rx, max_tx, tx_sets = 1;
8842 int tx_rings_needed;
8f23d638 8843 int rx_rings = rx;
6fc2ffdf 8844 int cp, vnics, rc;
d1e7925e 8845
d1e7925e
MC		 8846 if (tcs)
8847 tx_sets = tcs;
8848
8849 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
8850 if (rc)
8851 return rc;
8852
8853 if (max_rx < rx)
8854 return -ENOMEM;
8855
5f449249 8856 tx_rings_needed = tx * tx_sets + tx_xdp;
d1e7925e
MC		 8857 if (max_tx < tx_rings_needed)
8858 return -ENOMEM;
8859
6fc2ffdf
EW		 8860 vnics = 1;
8861 if (bp->flags & BNXT_FLAG_RFS)
8862 vnics += rx_rings;
8863
8f23d638
MC		 8864 if (bp->flags & BNXT_FLAG_AGG_RINGS)
8865 rx_rings <<= 1;
8866 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
f1ca94de 8867 if (BNXT_NEW_RM(bp))
11c3ec7b 8868 cp += bnxt_get_ulp_msix_num(bp);
6fc2ffdf
EW		 8869 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
8870 vnics);
d1e7925e
MC		 8871}
8872
17086399
SP		 8873static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
8874{
8875 if (bp->bar2) {
8876 pci_iounmap(pdev, bp->bar2);
8877 bp->bar2 = NULL;
8878 }
8879
8880 if (bp->bar1) {
8881 pci_iounmap(pdev, bp->bar1);
8882 bp->bar1 = NULL;
8883 }
8884
8885 if (bp->bar0) {
8886 pci_iounmap(pdev, bp->bar0);
8887 bp->bar0 = NULL;
8888 }
8889}
8890
8891static void bnxt_cleanup_pci(struct bnxt *bp)
8892{
8893 bnxt_unmap_bars(bp, bp->pdev);
8894 pci_release_regions(bp->pdev);
8895 pci_disable_device(bp->pdev);
8896}
8897
18775aa8
MC		 8898static void bnxt_init_dflt_coal(struct bnxt *bp)
8899{
8900 struct bnxt_coal *coal;
8901
8902 /* Tick values in micro seconds.
8903 * 1 coal_buf x bufs_per_record = 1 completion record.
8904 */
8905 coal = &bp->rx_coal;
8906 coal->coal_ticks = 14;
8907 coal->coal_bufs = 30;
8908 coal->coal_ticks_irq = 1;
8909 coal->coal_bufs_irq = 2;
05abe4dd 8910 coal->idle_thresh = 50;
18775aa8
MC		 8911 coal->bufs_per_record = 2;
8912 coal->budget = 64; /* NAPI budget */
8913
8914 coal = &bp->tx_coal;
8915 coal->coal_ticks = 28;
8916 coal->coal_bufs = 30;
8917 coal->coal_ticks_irq = 2;
8918 coal->coal_bufs_irq = 2;
8919 coal->bufs_per_record = 1;
8920
8921 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
8922}
8923
c0c050c5
MC		 8924static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
8925{
8926 int rc;
8927 struct bnxt *bp = netdev_priv(dev);
8928
8929 SET_NETDEV_DEV(dev, &pdev->dev);
8930
8931 /* enable device (incl. PCI PM wakeup), and bus-mastering */
8932 rc = pci_enable_device(pdev);
8933 if (rc) {
8934 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
8935 goto init_err;
8936 }
8937
8938 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
8939 dev_err(&pdev->dev,
8940 "Cannot find PCI device base address, aborting\n");
8941 rc = -ENODEV;
8942 goto init_err_disable;
8943 }
8944
8945 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
8946 if (rc) {
8947 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
8948 goto init_err_disable;
8949 }
8950
8951 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
8952 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
8953 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
8954 goto init_err_disable;
8955 }
8956
8957 pci_set_master(pdev);
8958
8959 bp->dev = dev;
8960 bp->pdev = pdev;
8961
8962 bp->bar0 = pci_ioremap_bar(pdev, 0);
8963 if (!bp->bar0) {
8964 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
8965 rc = -ENOMEM;
8966 goto init_err_release;
8967 }
8968
8969 bp->bar1 = pci_ioremap_bar(pdev, 2);
8970 if (!bp->bar1) {
8971 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
8972 rc = -ENOMEM;
8973 goto init_err_release;
8974 }
8975
8976 bp->bar2 = pci_ioremap_bar(pdev, 4);
8977 if (!bp->bar2) {
8978 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
8979 rc = -ENOMEM;
8980 goto init_err_release;
8981 }
8982
6316ea6d
SB		 8983 pci_enable_pcie_error_reporting(pdev);
8984
c0c050c5
MC		 8985 INIT_WORK(&bp->sp_task, bnxt_sp_task);
8986
8987 spin_lock_init(&bp->ntp_fltr_lock);
697197e5
MC		 8988#if BITS_PER_LONG == 32
8989 spin_lock_init(&bp->db_lock);
8990#endif
c0c050c5
MC		 8991
8992 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
8993 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
8994
18775aa8 8995 bnxt_init_dflt_coal(bp);
51f30785 8996
e99e88a9 8997 timer_setup(&bp->timer, bnxt_timer, 0);
c0c050c5
MC		 8998 bp->current_interval = BNXT_TIMER_INTERVAL;
8999
caefe526 9000 clear_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 9001 return 0;
9002
9003init_err_release:
17086399 9004 bnxt_unmap_bars(bp, pdev);
c0c050c5
MC		 9005 pci_release_regions(pdev);
9006
9007init_err_disable:
9008 pci_disable_device(pdev);
9009
9010init_err:
9011 return rc;
9012}
9013
9014/* rtnl_lock held */
9015static int bnxt_change_mac_addr(struct net_device *dev, void *p)
9016{
9017 struct sockaddr *addr = p;
1fc2cfd0
JH		 9018 struct bnxt *bp = netdev_priv(dev);
9019 int rc = 0;
c0c050c5
MC		 9020
9021 if (!is_valid_ether_addr(addr->sa_data))
9022 return -EADDRNOTAVAIL;
9023
c1a7bdff
MC		 9024 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
9025 return 0;
9026
28ea334b 9027 rc = bnxt_approve_mac(bp, addr->sa_data, true);
84c33dd3
MC		 9028 if (rc)
9029 return rc;
bdd4347b 9030
c0c050c5 9031 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1fc2cfd0
JH		 9032 if (netif_running(dev)) {
9033 bnxt_close_nic(bp, false, false);
9034 rc = bnxt_open_nic(bp, false, false);
9035 }
c0c050c5 9036
1fc2cfd0 9037 return rc;
c0c050c5
MC		 9038}
9039
9040/* rtnl_lock held */
9041static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
9042{
9043 struct bnxt *bp = netdev_priv(dev);
9044
c0c050c5
MC		 9045 if (netif_running(dev))
9046 bnxt_close_nic(bp, false, false);
9047
9048 dev->mtu = new_mtu;
9049 bnxt_set_ring_params(bp);
9050
9051 if (netif_running(dev))
9052 return bnxt_open_nic(bp, false, false);
9053
9054 return 0;
9055}
9056
c5e3deb8 9057int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
c0c050c5
MC		 9058{
9059 struct bnxt *bp = netdev_priv(dev);
3ffb6a39 9060 bool sh = false;
d1e7925e 9061 int rc;
16e5cc64 9062
c0c050c5 9063 if (tc > bp->max_tc) {
b451c8b6 9064 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
c0c050c5
MC		 9065 tc, bp->max_tc);
9066 return -EINVAL;
9067 }
9068
9069 if (netdev_get_num_tc(dev) == tc)
9070 return 0;
9071
3ffb6a39
MC		 9072 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
9073 sh = true;
9074
98fdbe73
MC		 9075 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
9076 sh, tc, bp->tx_nr_rings_xdp);
d1e7925e
MC		 9077 if (rc)
9078 return rc;
c0c050c5
MC		 9079
9080 /* Needs to close the device and do hw resource re-allocations */
9081 if (netif_running(bp->dev))
9082 bnxt_close_nic(bp, true, false);
9083
9084 if (tc) {
9085 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
9086 netdev_set_num_tc(dev, tc);
9087 } else {
9088 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
9089 netdev_reset_tc(dev);
9090 }
87e9b377 9091 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
3ffb6a39
MC		 9092 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
9093 bp->tx_nr_rings + bp->rx_nr_rings;
c0c050c5
MC		 9094 bp->num_stat_ctxs = bp->cp_nr_rings;
9095
9096 if (netif_running(bp->dev))
9097 return bnxt_open_nic(bp, true, false);
9098
9099 return 0;
9100}
9101
9e0fd15d
JP		 9102static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
9103 void *cb_priv)
c5e3deb8 9104{
9e0fd15d 9105 struct bnxt *bp = cb_priv;
de4784ca 9106
312324f1
JK		 9107 if (!bnxt_tc_flower_enabled(bp) ||
9108 !tc_cls_can_offload_and_chain0(bp->dev, type_data))
38cf0426 9109 return -EOPNOTSUPP;
c5e3deb8 9110
9e0fd15d
JP		 9111 switch (type) {
9112 case TC_SETUP_CLSFLOWER:
9113 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
9114 default:
9115 return -EOPNOTSUPP;
9116 }
9117}
9118
9119static int bnxt_setup_tc_block(struct net_device *dev,
9120 struct tc_block_offload *f)
9121{
9122 struct bnxt *bp = netdev_priv(dev);
9123
9124 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
9125 return -EOPNOTSUPP;
9126
9127 switch (f->command) {
9128 case TC_BLOCK_BIND:
9129 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
60513bd8 9130 bp, bp, f->extack);
9e0fd15d
JP		 9131 case TC_BLOCK_UNBIND:
9132 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
9133 return 0;
9134 default:
9135 return -EOPNOTSUPP;
9136 }
2ae7408f
SP		 9137}
9138
9139static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
9140 void *type_data)
9141{
9142 switch (type) {
9e0fd15d
JP		 9143 case TC_SETUP_BLOCK:
9144 return bnxt_setup_tc_block(dev, type_data);
575ed7d3 9145 case TC_SETUP_QDISC_MQPRIO: {
2ae7408f
SP		 9146 struct tc_mqprio_qopt *mqprio = type_data;
9147
9148 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
56f36acd 9149
2ae7408f
SP		 9150 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
9151 }
9152 default:
9153 return -EOPNOTSUPP;
9154 }
c5e3deb8
MC		 9155}
9156
c0c050c5
MC		 9157#ifdef CONFIG_RFS_ACCEL
9158static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
9159 struct bnxt_ntuple_filter *f2)
9160{
9161 struct flow_keys *keys1 = &f1->fkeys;
9162 struct flow_keys *keys2 = &f2->fkeys;
9163
9164 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
9165 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
9166 keys1->ports.ports == keys2->ports.ports &&
9167 keys1->basic.ip_proto == keys2->basic.ip_proto &&
9168 keys1->basic.n_proto == keys2->basic.n_proto &&
61aad724 9169 keys1->control.flags == keys2->control.flags &&
a54c4d74
MC		 9170 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
9171 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
c0c050c5
MC		 9172 return true;
9173
9174 return false;
9175}
9176
9177static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
9178 u16 rxq_index, u32 flow_id)
9179{
9180 struct bnxt *bp = netdev_priv(dev);
9181 struct bnxt_ntuple_filter *fltr, *new_fltr;
9182 struct flow_keys *fkeys;
9183 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
a54c4d74 9184 int rc = 0, idx, bit_id, l2_idx = 0;
c0c050c5
MC		 9185 struct hlist_head *head;
9186
a54c4d74
MC		 9187 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
9188 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9189 int off = 0, j;
9190
9191 netif_addr_lock_bh(dev);
9192 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
9193 if (ether_addr_equal(eth->h_dest,
9194 vnic->uc_list + off)) {
9195 l2_idx = j + 1;
9196 break;
9197 }
9198 }
9199 netif_addr_unlock_bh(dev);
9200 if (!l2_idx)
9201 return -EINVAL;
9202 }
c0c050c5
MC		 9203 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
9204 if (!new_fltr)
9205 return -ENOMEM;
9206
9207 fkeys = &new_fltr->fkeys;
9208 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
9209 rc = -EPROTONOSUPPORT;
9210 goto err_free;
9211 }
9212
dda0e746
MC		 9213 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
9214 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
c0c050c5
MC		 9215 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
9216 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
9217 rc = -EPROTONOSUPPORT;
9218 goto err_free;
9219 }
dda0e746
MC		 9220 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
9221 bp->hwrm_spec_code < 0x10601) {
9222 rc = -EPROTONOSUPPORT;
9223 goto err_free;
9224 }
61aad724
MC		 9225 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
9226 bp->hwrm_spec_code < 0x10601) {
9227 rc = -EPROTONOSUPPORT;
9228 goto err_free;
9229 }
c0c050c5 9230
a54c4d74 9231 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
c0c050c5
MC		 9232 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
9233
9234 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
9235 head = &bp->ntp_fltr_hash_tbl[idx];
9236 rcu_read_lock();
9237 hlist_for_each_entry_rcu(fltr, head, hash) {
9238 if (bnxt_fltr_match(fltr, new_fltr)) {
9239 rcu_read_unlock();
9240 rc = 0;
9241 goto err_free;
9242 }
9243 }
9244 rcu_read_unlock();
9245
9246 spin_lock_bh(&bp->ntp_fltr_lock);
84e86b98
MC		 9247 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
9248 BNXT_NTP_FLTR_MAX_FLTR, 0);
9249 if (bit_id < 0) {
c0c050c5
MC		 9250 spin_unlock_bh(&bp->ntp_fltr_lock);
9251 rc = -ENOMEM;
9252 goto err_free;
9253 }
9254
84e86b98 9255 new_fltr->sw_id = (u16)bit_id;
c0c050c5 9256 new_fltr->flow_id = flow_id;
a54c4d74 9257 new_fltr->l2_fltr_idx = l2_idx;
c0c050c5
MC		 9258 new_fltr->rxq = rxq_index;
9259 hlist_add_head_rcu(&new_fltr->hash, head);
9260 bp->ntp_fltr_count++;
9261 spin_unlock_bh(&bp->ntp_fltr_lock);
9262
9263 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
c213eae8 9264 bnxt_queue_sp_work(bp);
c0c050c5
MC		 9265
9266 return new_fltr->sw_id;
9267
9268err_free:
9269 kfree(new_fltr);
9270 return rc;
9271}
9272
9273static void bnxt_cfg_ntp_filters(struct bnxt *bp)
9274{
9275 int i;
9276
9277 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
9278 struct hlist_head *head;
9279 struct hlist_node *tmp;
9280 struct bnxt_ntuple_filter *fltr;
9281 int rc;
9282
9283 head = &bp->ntp_fltr_hash_tbl[i];
9284 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
9285 bool del = false;
9286
9287 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
9288 if (rps_may_expire_flow(bp->dev, fltr->rxq,
9289 fltr->flow_id,
9290 fltr->sw_id)) {
9291 bnxt_hwrm_cfa_ntuple_filter_free(bp,
9292 fltr);
9293 del = true;
9294 }
9295 } else {
9296 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
9297 fltr);
9298 if (rc)
9299 del = true;
9300 else
9301 set_bit(BNXT_FLTR_VALID, &fltr->state);
9302 }
9303
9304 if (del) {
9305 spin_lock_bh(&bp->ntp_fltr_lock);
9306 hlist_del_rcu(&fltr->hash);
9307 bp->ntp_fltr_count--;
9308 spin_unlock_bh(&bp->ntp_fltr_lock);
9309 synchronize_rcu();
9310 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
9311 kfree(fltr);
9312 }
9313 }
9314 }
19241368
JH		 9315 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
9316 netdev_info(bp->dev, "Receive PF driver unload event!");
c0c050c5
MC		 9317}
9318
9319#else
9320
9321static void bnxt_cfg_ntp_filters(struct bnxt *bp)
9322{
9323}
9324
9325#endif /* CONFIG_RFS_ACCEL */
9326
ad51b8e9
AD		 9327static void bnxt_udp_tunnel_add(struct net_device *dev,
9328 struct udp_tunnel_info *ti)
c0c050c5
MC		 9329{
9330 struct bnxt *bp = netdev_priv(dev);
9331
ad51b8e9 9332 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
c0c050c5
MC		 9333 return;
9334
ad51b8e9 9335 if (!netif_running(dev))
c0c050c5
MC		 9336 return;
9337
ad51b8e9
AD		 9338 switch (ti->type) {
9339 case UDP_TUNNEL_TYPE_VXLAN:
9340 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
9341 return;
c0c050c5 9342
ad51b8e9
AD		 9343 bp->vxlan_port_cnt++;
9344 if (bp->vxlan_port_cnt == 1) {
9345 bp->vxlan_port = ti->port;
9346 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
c213eae8 9347 bnxt_queue_sp_work(bp);
ad51b8e9
AD		 9348 }
9349 break;
7cdd5fc3
AD		 9350 case UDP_TUNNEL_TYPE_GENEVE:
9351 if (bp->nge_port_cnt && bp->nge_port != ti->port)
9352 return;
9353
9354 bp->nge_port_cnt++;
9355 if (bp->nge_port_cnt == 1) {
9356 bp->nge_port = ti->port;
9357 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
9358 }
9359 break;
ad51b8e9
AD		 9360 default:
9361 return;
c0c050c5 9362 }
ad51b8e9 9363
c213eae8 9364 bnxt_queue_sp_work(bp);
c0c050c5
MC		 9365}
9366
ad51b8e9
AD		 9367static void bnxt_udp_tunnel_del(struct net_device *dev,
9368 struct udp_tunnel_info *ti)
c0c050c5
MC		 9369{
9370 struct bnxt *bp = netdev_priv(dev);
9371
ad51b8e9 9372 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
c0c050c5
MC		 9373 return;
9374
ad51b8e9 9375 if (!netif_running(dev))
c0c050c5
MC		 9376 return;
9377
ad51b8e9
AD		 9378 switch (ti->type) {
9379 case UDP_TUNNEL_TYPE_VXLAN:
9380 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
9381 return;
c0c050c5
MC		 9382 bp->vxlan_port_cnt--;
9383
ad51b8e9
AD		 9384 if (bp->vxlan_port_cnt != 0)
9385 return;
9386
9387 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
9388 break;
7cdd5fc3
AD		 9389 case UDP_TUNNEL_TYPE_GENEVE:
9390 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
9391 return;
9392 bp->nge_port_cnt--;
9393
9394 if (bp->nge_port_cnt != 0)
9395 return;
9396
9397 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
9398 break;
ad51b8e9
AD		 9399 default:
9400 return;
c0c050c5 9401 }
ad51b8e9 9402
c213eae8 9403 bnxt_queue_sp_work(bp);
c0c050c5
MC		 9404}
9405
39d8ba2e
MC		 9406static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
9407 struct net_device *dev, u32 filter_mask,
9408 int nlflags)
9409{
9410 struct bnxt *bp = netdev_priv(dev);
9411
9412 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
9413 nlflags, filter_mask, NULL);
9414}
9415
9416static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
9417 u16 flags)
9418{
9419 struct bnxt *bp = netdev_priv(dev);
9420 struct nlattr *attr, *br_spec;
9421 int rem, rc = 0;
9422
9423 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
9424 return -EOPNOTSUPP;
9425
9426 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
9427 if (!br_spec)
9428 return -EINVAL;
9429
9430 nla_for_each_nested(attr, br_spec, rem) {
9431 u16 mode;
9432
9433 if (nla_type(attr) != IFLA_BRIDGE_MODE)
9434 continue;
9435
9436 if (nla_len(attr) < sizeof(mode))
9437 return -EINVAL;
9438
9439 mode = nla_get_u16(attr);
9440 if (mode == bp->br_mode)
9441 break;
9442
9443 rc = bnxt_hwrm_set_br_mode(bp, mode);
9444 if (!rc)
9445 bp->br_mode = mode;
9446 break;
9447 }
9448 return rc;
9449}
9450
c124a62f
SP		 9451static int bnxt_get_phys_port_name(struct net_device *dev, char *buf,
9452 size_t len)
9453{
9454 struct bnxt *bp = netdev_priv(dev);
9455 int rc;
9456
9457 /* The PF and it's VF-reps only support the switchdev framework */
9458 if (!BNXT_PF(bp))
9459 return -EOPNOTSUPP;
9460
53f70b8b 9461 rc = snprintf(buf, len, "p%d", bp->pf.port_id);
c124a62f
SP		 9462
9463 if (rc >= len)
9464 return -EOPNOTSUPP;
9465 return 0;
9466}
9467
9468int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr)
9469{
9470 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
9471 return -EOPNOTSUPP;
9472
9473 /* The PF and it's VF-reps only support the switchdev framework */
9474 if (!BNXT_PF(bp))
9475 return -EOPNOTSUPP;
9476
9477 switch (attr->id) {
9478 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
dd4ea1da
SP		 9479 attr->u.ppid.id_len = sizeof(bp->switch_id);
9480 memcpy(attr->u.ppid.id, bp->switch_id, attr->u.ppid.id_len);
c124a62f
SP		 9481 break;
9482 default:
9483 return -EOPNOTSUPP;
9484 }
9485 return 0;
9486}
9487
9488static int bnxt_swdev_port_attr_get(struct net_device *dev,
9489 struct switchdev_attr *attr)
9490{
9491 return bnxt_port_attr_get(netdev_priv(dev), attr);
9492}
9493
9494static const struct switchdev_ops bnxt_switchdev_ops = {
9495 .switchdev_port_attr_get = bnxt_swdev_port_attr_get
9496};
9497
c0c050c5
MC		 9498static const struct net_device_ops bnxt_netdev_ops = {
9499 .ndo_open = bnxt_open,
9500 .ndo_start_xmit = bnxt_start_xmit,
9501 .ndo_stop = bnxt_close,
9502 .ndo_get_stats64 = bnxt_get_stats64,
9503 .ndo_set_rx_mode = bnxt_set_rx_mode,
9504 .ndo_do_ioctl = bnxt_ioctl,
9505 .ndo_validate_addr = eth_validate_addr,
9506 .ndo_set_mac_address = bnxt_change_mac_addr,
9507 .ndo_change_mtu = bnxt_change_mtu,
9508 .ndo_fix_features = bnxt_fix_features,
9509 .ndo_set_features = bnxt_set_features,
9510 .ndo_tx_timeout = bnxt_tx_timeout,
9511#ifdef CONFIG_BNXT_SRIOV
9512 .ndo_get_vf_config = bnxt_get_vf_config,
9513 .ndo_set_vf_mac = bnxt_set_vf_mac,
9514 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
9515 .ndo_set_vf_rate = bnxt_set_vf_bw,
9516 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
9517 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
746df139 9518 .ndo_set_vf_trust = bnxt_set_vf_trust,
c0c050c5
MC		 9519#endif
9520 .ndo_setup_tc = bnxt_setup_tc,
9521#ifdef CONFIG_RFS_ACCEL
9522 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
9523#endif
ad51b8e9
AD		 9524 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
9525 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
f4e63525 9526 .ndo_bpf = bnxt_xdp,
39d8ba2e
MC		 9527 .ndo_bridge_getlink = bnxt_bridge_getlink,
9528 .ndo_bridge_setlink = bnxt_bridge_setlink,
c124a62f 9529 .ndo_get_phys_port_name = bnxt_get_phys_port_name
c0c050c5
MC		 9530};
9531
9532static void bnxt_remove_one(struct pci_dev *pdev)
9533{
9534 struct net_device *dev = pci_get_drvdata(pdev);
9535 struct bnxt *bp = netdev_priv(dev);
9536
4ab0c6a8 9537 if (BNXT_PF(bp)) {
c0c050c5 9538 bnxt_sriov_disable(bp);
4ab0c6a8
SP		 9539 bnxt_dl_unregister(bp);
9540 }
c0c050c5 9541
6316ea6d 9542 pci_disable_pcie_error_reporting(pdev);
c0c050c5 9543 unregister_netdev(dev);
2ae7408f 9544 bnxt_shutdown_tc(bp);
c213eae8 9545 bnxt_cancel_sp_work(bp);
c0c050c5
MC		 9546 bp->sp_event = 0;
9547
7809592d 9548 bnxt_clear_int_mode(bp);
be58a0da 9549 bnxt_hwrm_func_drv_unrgtr(bp);
c0c050c5 9550 bnxt_free_hwrm_resources(bp);
e605db80 9551 bnxt_free_hwrm_short_cmd_req(bp);
eb513658 9552 bnxt_ethtool_free(bp);
7df4ae9f 9553 bnxt_dcb_free(bp);
a588e458
MC		 9554 kfree(bp->edev);
9555 bp->edev = NULL;
98f04cf0
MC		 9556 bnxt_free_ctx_mem(bp);
9557 kfree(bp->ctx);
9558 bp->ctx = NULL;
17086399 9559 bnxt_cleanup_pci(bp);
c0c050c5 9560 free_netdev(dev);
c0c050c5
MC		 9561}
9562
9563static int bnxt_probe_phy(struct bnxt *bp)
9564{
9565 int rc = 0;
9566 struct bnxt_link_info *link_info = &bp->link_info;
c0c050c5 9567
170ce013
MC		 9568 rc = bnxt_hwrm_phy_qcaps(bp);
9569 if (rc) {
9570 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
9571 rc);
9572 return rc;
9573 }
e2dc9b6e 9574 mutex_init(&bp->link_lock);
170ce013 9575
c0c050c5
MC		 9576 rc = bnxt_update_link(bp, false);
9577 if (rc) {
9578 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
9579 rc);
9580 return rc;
9581 }
9582
93ed8117
MC		 9583 /* Older firmware does not have supported_auto_speeds, so assume
9584 * that all supported speeds can be autonegotiated.
9585 */
9586 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
9587 link_info->support_auto_speeds = link_info->support_speeds;
9588
c0c050c5 9589 /*initialize the ethool setting copy with NVM settings */
0d8abf02 9590 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
c9ee9516
MC		 9591 link_info->autoneg = BNXT_AUTONEG_SPEED;
9592 if (bp->hwrm_spec_code >= 0x10201) {
9593 if (link_info->auto_pause_setting &
9594 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
9595 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
9596 } else {
9597 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
9598 }
0d8abf02 9599 link_info->advertising = link_info->auto_link_speeds;
0d8abf02
MC		 9600 } else {
9601 link_info->req_link_speed = link_info->force_link_speed;
9602 link_info->req_duplex = link_info->duplex_setting;
c0c050c5 9603 }
c9ee9516
MC		 9604 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
9605 link_info->req_flow_ctrl =
9606 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
9607 else
9608 link_info->req_flow_ctrl = link_info->force_pause_setting;
c0c050c5
MC		 9609 return rc;
9610}
9611
9612static int bnxt_get_max_irq(struct pci_dev *pdev)
9613{
9614 u16 ctrl;
9615
9616 if (!pdev->msix_cap)
9617 return 1;
9618
9619 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
9620 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
9621}
9622
6e6c5a57
MC		 9623static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
9624 int *max_cp)
c0c050c5 9625{
6a4f2947 9626 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6e6c5a57 9627 int max_ring_grps = 0;
c0c050c5 9628
6a4f2947
MC		 9629 *max_tx = hw_resc->max_tx_rings;
9630 *max_rx = hw_resc->max_rx_rings;
00fe9c32 9631 *max_cp = min_t(int, bnxt_get_max_func_cp_rings_for_en(bp),
c78fe058 9632 hw_resc->max_irqs - bnxt_get_ulp_msix_num(bp));
6a4f2947
MC		 9633 *max_cp = min_t(int, *max_cp, hw_resc->max_stat_ctxs);
9634 max_ring_grps = hw_resc->max_hw_ring_grps;
76595193
PS		 9635 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
9636 *max_cp -= 1;
9637 *max_rx -= 2;
9638 }
c0c050c5
MC		 9639 if (bp->flags & BNXT_FLAG_AGG_RINGS)
9640 *max_rx >>= 1;
b72d4a68 9641 *max_rx = min_t(int, *max_rx, max_ring_grps);
6e6c5a57
MC		 9642}
9643
9644int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
9645{
9646 int rx, tx, cp;
9647
9648 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
78f058a4
MC		 9649 *max_rx = rx;
9650 *max_tx = tx;
6e6c5a57
MC		 9651 if (!rx || !tx || !cp)
9652 return -ENOMEM;
9653
6e6c5a57
MC		 9654 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
9655}
9656
e4060d30
MC		 9657static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
9658 bool shared)
9659{
9660 int rc;
9661
9662 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
bdbd1eb5
MC		 9663 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
9664 /* Not enough rings, try disabling agg rings. */
9665 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
9666 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
07f4fde5
MC		 9667 if (rc) {
9668 /* set BNXT_FLAG_AGG_RINGS back for consistency */
9669 bp->flags |= BNXT_FLAG_AGG_RINGS;
bdbd1eb5 9670 return rc;
07f4fde5 9671 }
bdbd1eb5 9672 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
1054aee8
MC		 9673 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
9674 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
bdbd1eb5
MC		 9675 bnxt_set_ring_params(bp);
9676 }
e4060d30
MC		 9677
9678 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
9679 int max_cp, max_stat, max_irq;
9680
9681 /* Reserve minimum resources for RoCE */
9682 max_cp = bnxt_get_max_func_cp_rings(bp);
9683 max_stat = bnxt_get_max_func_stat_ctxs(bp);
9684 max_irq = bnxt_get_max_func_irqs(bp);
9685 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
9686 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
9687 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
9688 return 0;
9689
9690 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
9691 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
9692 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
9693 max_cp = min_t(int, max_cp, max_irq);
9694 max_cp = min_t(int, max_cp, max_stat);
9695 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
9696 if (rc)
9697 rc = 0;
9698 }
9699 return rc;
9700}
9701
58ea801a
MC		 9702/* In initial default shared ring setting, each shared ring must have a
9703 * RX/TX ring pair.
9704 */
9705static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
9706{
9707 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
9708 bp->rx_nr_rings = bp->cp_nr_rings;
9709 bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
9710 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
9711}
9712
702c221c 9713static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
6e6c5a57
MC		 9714{
9715 int dflt_rings, max_rx_rings, max_tx_rings, rc;
6e6c5a57 9716
2773dfb2
MC		 9717 if (!bnxt_can_reserve_rings(bp))
9718 return 0;
9719
6e6c5a57
MC		 9720 if (sh)
9721 bp->flags |= BNXT_FLAG_SHARED_RINGS;
9722 dflt_rings = netif_get_num_default_rss_queues();
1d3ef13d
MC		 9723 /* Reduce default rings on multi-port cards so that total default
9724 * rings do not exceed CPU count.
9725 */
9726 if (bp->port_count > 1) {
9727 int max_rings =
9728 max_t(int, num_online_cpus() / bp->port_count, 1);
9729
9730 dflt_rings = min_t(int, dflt_rings, max_rings);
9731 }
e4060d30 9732 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6e6c5a57
MC		 9733 if (rc)
9734 return rc;
9735 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
9736 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
58ea801a
MC		 9737 if (sh)
9738 bnxt_trim_dflt_sh_rings(bp);
9739 else
9740 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
9741 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
391be5c2 9742
674f50a5 9743 rc = __bnxt_reserve_rings(bp);
391be5c2
MC		 9744 if (rc)
9745 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
58ea801a
MC		 9746 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
9747 if (sh)
9748 bnxt_trim_dflt_sh_rings(bp);
391be5c2 9749
674f50a5
MC		 9750 /* Rings may have been trimmed, re-reserve the trimmed rings. */
9751 if (bnxt_need_reserve_rings(bp)) {
9752 rc = __bnxt_reserve_rings(bp);
9753 if (rc)
9754 netdev_warn(bp->dev, "2nd rings reservation failed.\n");
9755 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
9756 }
6e6c5a57 9757 bp->num_stat_ctxs = bp->cp_nr_rings;
76595193
PS		 9758 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
9759 bp->rx_nr_rings++;
9760 bp->cp_nr_rings++;
9761 }
6e6c5a57 9762 return rc;
c0c050c5
MC		 9763}
9764
47558acd
MC		 9765static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
9766{
9767 int rc;
9768
9769 if (bp->tx_nr_rings)
9770 return 0;
9771
6b95c3e9
MC		 9772 bnxt_ulp_irq_stop(bp);
9773 bnxt_clear_int_mode(bp);
47558acd
MC		 9774 rc = bnxt_set_dflt_rings(bp, true);
9775 if (rc) {
9776 netdev_err(bp->dev, "Not enough rings available.\n");
6b95c3e9 9777 goto init_dflt_ring_err;
47558acd
MC		 9778 }
9779 rc = bnxt_init_int_mode(bp);
9780 if (rc)
6b95c3e9
MC		 9781 goto init_dflt_ring_err;
9782
47558acd
MC		 9783 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
9784 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
9785 bp->flags |= BNXT_FLAG_RFS;
9786 bp->dev->features |= NETIF_F_NTUPLE;
9787 }
6b95c3e9
MC		 9788init_dflt_ring_err:
9789 bnxt_ulp_irq_restart(bp, rc);
9790 return rc;
47558acd
MC		 9791}
9792
80fcaf46 9793int bnxt_restore_pf_fw_resources(struct bnxt *bp)
7b08f661 9794{
80fcaf46
MC		 9795 int rc;
9796
7b08f661
MC		 9797 ASSERT_RTNL();
9798 bnxt_hwrm_func_qcaps(bp);
1a037782
VD		 9799
9800 if (netif_running(bp->dev))
9801 __bnxt_close_nic(bp, true, false);
9802
ec86f14e 9803 bnxt_ulp_irq_stop(bp);
80fcaf46
MC		 9804 bnxt_clear_int_mode(bp);
9805 rc = bnxt_init_int_mode(bp);
ec86f14e 9806 bnxt_ulp_irq_restart(bp, rc);
1a037782
VD		 9807
9808 if (netif_running(bp->dev)) {
9809 if (rc)
9810 dev_close(bp->dev);
9811 else
9812 rc = bnxt_open_nic(bp, true, false);
9813 }
9814
80fcaf46 9815 return rc;
7b08f661
MC		 9816}
9817
a22a6ac2
MC		 9818static int bnxt_init_mac_addr(struct bnxt *bp)
9819{
9820 int rc = 0;
9821
9822 if (BNXT_PF(bp)) {
9823 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
9824 } else {
9825#ifdef CONFIG_BNXT_SRIOV
9826 struct bnxt_vf_info *vf = &bp->vf;
28ea334b 9827 bool strict_approval = true;
a22a6ac2
MC		 9828
9829 if (is_valid_ether_addr(vf->mac_addr)) {
91cdda40 9830 /* overwrite netdev dev_addr with admin VF MAC */
a22a6ac2 9831 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
28ea334b
MC		 9832 /* Older PF driver or firmware may not approve this
9833 * correctly.
9834 */
9835 strict_approval = false;
a22a6ac2
MC		 9836 } else {
9837 eth_hw_addr_random(bp->dev);
a22a6ac2 9838 }
28ea334b 9839 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
a22a6ac2
MC		 9840#endif
9841 }
9842 return rc;
9843}
9844
c0c050c5
MC		 9845static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
9846{
9847 static int version_printed;
9848 struct net_device *dev;
9849 struct bnxt *bp;
6e6c5a57 9850 int rc, max_irqs;
c0c050c5 9851
4e00338a 9852 if (pci_is_bridge(pdev))
fa853dda
PS		 9853 return -ENODEV;
9854
c0c050c5
MC		 9855 if (version_printed++ == 0)
9856 pr_info("%s", version);
9857
9858 max_irqs = bnxt_get_max_irq(pdev);
9859 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
9860 if (!dev)
9861 return -ENOMEM;
9862
9863 bp = netdev_priv(dev);
9c1fabdf 9864 bnxt_set_max_func_irqs(bp, max_irqs);
c0c050c5
MC		 9865
9866 if (bnxt_vf_pciid(ent->driver_data))
9867 bp->flags |= BNXT_FLAG_VF;
9868
2bcfa6f6 9869 if (pdev->msix_cap)
c0c050c5 9870 bp->flags |= BNXT_FLAG_MSIX_CAP;
c0c050c5
MC		 9871
9872 rc = bnxt_init_board(pdev, dev);
9873 if (rc < 0)
9874 goto init_err_free;
9875
9876 dev->netdev_ops = &bnxt_netdev_ops;
9877 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
9878 dev->ethtool_ops = &bnxt_ethtool_ops;
bc88055a 9879 SWITCHDEV_SET_OPS(dev, &bnxt_switchdev_ops);
c0c050c5
MC		 9880 pci_set_drvdata(pdev, dev);
9881
3e8060fa
PS		 9882 rc = bnxt_alloc_hwrm_resources(bp);
9883 if (rc)
17086399 9884 goto init_err_pci_clean;
3e8060fa
PS		 9885
9886 mutex_init(&bp->hwrm_cmd_lock);
9887 rc = bnxt_hwrm_ver_get(bp);
9888 if (rc)
17086399 9889 goto init_err_pci_clean;
3e8060fa 9890
1dfddc41
MC		 9891 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
9892 bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) {
e605db80
DK		 9893 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
9894 if (rc)
9895 goto init_err_pci_clean;
9896 }
9897
e38287b7
MC		 9898 if (BNXT_CHIP_P5(bp))
9899 bp->flags |= BNXT_FLAG_CHIP_P5;
9900
3c2217a6
MC		 9901 rc = bnxt_hwrm_func_reset(bp);
9902 if (rc)
9903 goto init_err_pci_clean;
9904
5ac67d8b
RS		 9905 bnxt_hwrm_fw_set_time(bp);
9906
c0c050c5
MC		 9907 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
9908 NETIF_F_TSO | NETIF_F_TSO6 |
9909 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
7e13318d 9910 NETIF_F_GSO_IPXIP4 |
152971ee
AD		 9911 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
9912 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
3e8060fa
PS		 9913 NETIF_F_RXCSUM | NETIF_F_GRO;
9914
e38287b7 9915 if (BNXT_SUPPORTS_TPA(bp))
3e8060fa 9916 dev->hw_features |= NETIF_F_LRO;
c0c050c5 9917
c0c050c5
MC		 9918 dev->hw_enc_features =
9919 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
9920 NETIF_F_TSO | NETIF_F_TSO6 |
9921 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
152971ee 9922 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7e13318d 9923 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
152971ee
AD		 9924 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
9925 NETIF_F_GSO_GRE_CSUM;
c0c050c5
MC		 9926 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
9927 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
9928 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
e38287b7 9929 if (BNXT_SUPPORTS_TPA(bp))
1054aee8 9930 dev->hw_features |= NETIF_F_GRO_HW;
c0c050c5 9931 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
1054aee8
MC		 9932 if (dev->features & NETIF_F_GRO_HW)
9933 dev->features &= ~NETIF_F_LRO;
c0c050c5
MC		 9934 dev->priv_flags |= IFF_UNICAST_FLT;
9935
9936#ifdef CONFIG_BNXT_SRIOV
9937 init_waitqueue_head(&bp->sriov_cfg_wait);
4ab0c6a8 9938 mutex_init(&bp->sriov_lock);
c0c050c5 9939#endif
e38287b7
MC		 9940 if (BNXT_SUPPORTS_TPA(bp)) {
9941 bp->gro_func = bnxt_gro_func_5730x;
9942 if (BNXT_CHIP_P4(bp))
9943 bp->gro_func = bnxt_gro_func_5731x;
9944 }
9945 if (!BNXT_CHIP_P4_PLUS(bp))
434c975a 9946 bp->flags |= BNXT_FLAG_DOUBLE_DB;
309369c9 9947
c0c050c5
MC		 9948 rc = bnxt_hwrm_func_drv_rgtr(bp);
9949 if (rc)
17086399 9950 goto init_err_pci_clean;
c0c050c5 9951
a1653b13
MC		 9952 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
9953 if (rc)
17086399 9954 goto init_err_pci_clean;
a1653b13 9955
a588e458
MC		 9956 bp->ulp_probe = bnxt_ulp_probe;
9957
98f04cf0
MC		 9958 rc = bnxt_hwrm_queue_qportcfg(bp);
9959 if (rc) {
9960 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
9961 rc);
9962 rc = -1;
9963 goto init_err_pci_clean;
9964 }
c0c050c5
MC		 9965 /* Get the MAX capabilities for this function */
9966 rc = bnxt_hwrm_func_qcaps(bp);
9967 if (rc) {
9968 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
9969 rc);
9970 rc = -1;
17086399 9971 goto init_err_pci_clean;
c0c050c5 9972 }
a22a6ac2
MC		 9973 rc = bnxt_init_mac_addr(bp);
9974 if (rc) {
9975 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
9976 rc = -EADDRNOTAVAIL;
9977 goto init_err_pci_clean;
9978 }
c0c050c5 9979
567b2abe 9980 bnxt_hwrm_func_qcfg(bp);
5ad2cbee 9981 bnxt_hwrm_port_led_qcaps(bp);
eb513658 9982 bnxt_ethtool_init(bp);
87fe6032 9983 bnxt_dcb_init(bp);
567b2abe 9984
7eb9bb3a
MC		 9985 /* MTU range: 60 - FW defined max */
9986 dev->min_mtu = ETH_ZLEN;
9987 dev->max_mtu = bp->max_mtu;
9988
d5430d31
MC		 9989 rc = bnxt_probe_phy(bp);
9990 if (rc)
9991 goto init_err_pci_clean;
9992
c61fb99c 9993 bnxt_set_rx_skb_mode(bp, false);
c0c050c5
MC		 9994 bnxt_set_tpa_flags(bp);
9995 bnxt_set_ring_params(bp);
702c221c 9996 rc = bnxt_set_dflt_rings(bp, true);
bdbd1eb5
MC		 9997 if (rc) {
9998 netdev_err(bp->dev, "Not enough rings available.\n");
9999 rc = -ENOMEM;
17086399 10000 goto init_err_pci_clean;
bdbd1eb5 10001 }
c0c050c5 10002
87da7f79
MC		 10003 /* Default RSS hash cfg. */
10004 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
10005 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
10006 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
10007 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
e38287b7 10008 if (BNXT_CHIP_P4(bp) && bp->hwrm_spec_code >= 0x10501) {
87da7f79
MC		 10009 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
10010 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
10011 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
10012 }
10013
8fdefd63 10014 bnxt_hwrm_vnic_qcaps(bp);
8079e8f1 10015 if (bnxt_rfs_supported(bp)) {
2bcfa6f6
MC		 10016 dev->hw_features |= NETIF_F_NTUPLE;
10017 if (bnxt_rfs_capable(bp)) {
10018 bp->flags |= BNXT_FLAG_RFS;
10019 dev->features |= NETIF_F_NTUPLE;
10020 }
10021 }
10022
c0c050c5
MC		 10023 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
10024 bp->flags |= BNXT_FLAG_STRIP_VLAN;
10025
7809592d 10026 rc = bnxt_init_int_mode(bp);
c0c050c5 10027 if (rc)
17086399 10028 goto init_err_pci_clean;
c0c050c5 10029
832aed16
MC		 10030 /* No TC has been set yet and rings may have been trimmed due to
10031 * limited MSIX, so we re-initialize the TX rings per TC.
10032 */
10033 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10034
c1ef146a 10035 bnxt_get_wol_settings(bp);
d196ece7
MC		 10036 if (bp->flags & BNXT_FLAG_WOL_CAP)
10037 device_set_wakeup_enable(&pdev->dev, bp->wol);
10038 else
10039 device_set_wakeup_capable(&pdev->dev, false);
c1ef146a 10040
c3480a60
MC		 10041 bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
10042
74706afa
MC		 10043 bnxt_hwrm_coal_params_qcaps(bp);
10044
c213eae8
MC		 10045 if (BNXT_PF(bp)) {
10046 if (!bnxt_pf_wq) {
10047 bnxt_pf_wq =
10048 create_singlethread_workqueue("bnxt_pf_wq");
10049 if (!bnxt_pf_wq) {
10050 dev_err(&pdev->dev, "Unable to create workqueue.\n");
10051 goto init_err_pci_clean;
10052 }
10053 }
2ae7408f 10054 bnxt_init_tc(bp);
c213eae8 10055 }
2ae7408f 10056
7809592d
MC		 10057 rc = register_netdev(dev);
10058 if (rc)
2ae7408f 10059 goto init_err_cleanup_tc;
7809592d 10060
4ab0c6a8
SP		 10061 if (BNXT_PF(bp))
10062 bnxt_dl_register(bp);
10063
c0c050c5
MC		 10064 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
10065 board_info[ent->driver_data].name,
10066 (long)pci_resource_start(pdev, 0), dev->dev_addr);
af125b75 10067 pcie_print_link_status(pdev);
90c4f788 10068
c0c050c5
MC		 10069 return 0;
10070
2ae7408f
SP		 10071init_err_cleanup_tc:
10072 bnxt_shutdown_tc(bp);
7809592d
MC		 10073 bnxt_clear_int_mode(bp);
10074
17086399 10075init_err_pci_clean:
a2bf74f4 10076 bnxt_free_hwrm_resources(bp);
98f04cf0
MC		 10077 bnxt_free_ctx_mem(bp);
10078 kfree(bp->ctx);
10079 bp->ctx = NULL;
17086399 10080 bnxt_cleanup_pci(bp);
c0c050c5
MC		 10081
10082init_err_free:
10083 free_netdev(dev);
10084 return rc;
10085}
10086
d196ece7
MC		 10087static void bnxt_shutdown(struct pci_dev *pdev)
10088{
10089 struct net_device *dev = pci_get_drvdata(pdev);
10090 struct bnxt *bp;
10091
10092 if (!dev)
10093 return;
10094
10095 rtnl_lock();
10096 bp = netdev_priv(dev);
10097 if (!bp)
10098 goto shutdown_exit;
10099
10100 if (netif_running(dev))
10101 dev_close(dev);
10102
a7f3f939
RJ		 10103 bnxt_ulp_shutdown(bp);
10104
d196ece7
MC		 10105 if (system_state == SYSTEM_POWER_OFF) {
10106 bnxt_clear_int_mode(bp);
10107 pci_wake_from_d3(pdev, bp->wol);
10108 pci_set_power_state(pdev, PCI_D3hot);
10109 }
10110
10111shutdown_exit:
10112 rtnl_unlock();
10113}
10114
f65a2044
MC		 10115#ifdef CONFIG_PM_SLEEP
10116static int bnxt_suspend(struct device *device)
10117{
10118 struct pci_dev *pdev = to_pci_dev(device);
10119 struct net_device *dev = pci_get_drvdata(pdev);
10120 struct bnxt *bp = netdev_priv(dev);
10121 int rc = 0;
10122
10123 rtnl_lock();
10124 if (netif_running(dev)) {
10125 netif_device_detach(dev);
10126 rc = bnxt_close(dev);
10127 }
10128 bnxt_hwrm_func_drv_unrgtr(bp);
10129 rtnl_unlock();
10130 return rc;
10131}
10132
10133static int bnxt_resume(struct device *device)
10134{
10135 struct pci_dev *pdev = to_pci_dev(device);
10136 struct net_device *dev = pci_get_drvdata(pdev);
10137 struct bnxt *bp = netdev_priv(dev);
10138 int rc = 0;
10139
10140 rtnl_lock();
10141 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
10142 rc = -ENODEV;
10143 goto resume_exit;
10144 }
10145 rc = bnxt_hwrm_func_reset(bp);
10146 if (rc) {
10147 rc = -EBUSY;
10148 goto resume_exit;
10149 }
10150 bnxt_get_wol_settings(bp);
10151 if (netif_running(dev)) {
10152 rc = bnxt_open(dev);
10153 if (!rc)
10154 netif_device_attach(dev);
10155 }
10156
10157resume_exit:
10158 rtnl_unlock();
10159 return rc;
10160}
10161
10162static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
10163#define BNXT_PM_OPS (&bnxt_pm_ops)
10164
10165#else
10166
10167#define BNXT_PM_OPS NULL
10168
10169#endif /* CONFIG_PM_SLEEP */
10170
6316ea6d
SB		 10171/**
10172 * bnxt_io_error_detected - called when PCI error is detected
10173 * @pdev: Pointer to PCI device
10174 * @state: The current pci connection state
10175 *
10176 * This function is called after a PCI bus error affecting
10177 * this device has been detected.
10178 */
10179static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
10180 pci_channel_state_t state)
10181{
10182 struct net_device *netdev = pci_get_drvdata(pdev);
a588e458 10183 struct bnxt *bp = netdev_priv(netdev);
6316ea6d
SB		 10184
10185 netdev_info(netdev, "PCI I/O error detected\n");
10186
10187 rtnl_lock();
10188 netif_device_detach(netdev);
10189
a588e458
MC		 10190 bnxt_ulp_stop(bp);
10191
6316ea6d
SB		 10192 if (state == pci_channel_io_perm_failure) {
10193 rtnl_unlock();
10194 return PCI_ERS_RESULT_DISCONNECT;
10195 }
10196
10197 if (netif_running(netdev))
10198 bnxt_close(netdev);
10199
10200 pci_disable_device(pdev);
10201 rtnl_unlock();
10202
10203 /* Request a slot slot reset. */
10204 return PCI_ERS_RESULT_NEED_RESET;
10205}
10206
10207/**
10208 * bnxt_io_slot_reset - called after the pci bus has been reset.
10209 * @pdev: Pointer to PCI device
10210 *
10211 * Restart the card from scratch, as if from a cold-boot.
10212 * At this point, the card has exprienced a hard reset,
10213 * followed by fixups by BIOS, and has its config space
10214 * set up identically to what it was at cold boot.
10215 */
10216static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
10217{
10218 struct net_device *netdev = pci_get_drvdata(pdev);
10219 struct bnxt *bp = netdev_priv(netdev);
10220 int err = 0;
10221 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
10222
10223 netdev_info(bp->dev, "PCI Slot Reset\n");
10224
10225 rtnl_lock();
10226
10227 if (pci_enable_device(pdev)) {
10228 dev_err(&pdev->dev,
10229 "Cannot re-enable PCI device after reset.\n");
10230 } else {
10231 pci_set_master(pdev);
10232
aa8ed021
MC		 10233 err = bnxt_hwrm_func_reset(bp);
10234 if (!err && netif_running(netdev))
6316ea6d
SB		 10235 err = bnxt_open(netdev);
10236
a588e458 10237 if (!err) {
6316ea6d 10238 result = PCI_ERS_RESULT_RECOVERED;
a588e458
MC		 10239 bnxt_ulp_start(bp);
10240 }
6316ea6d
SB		 10241 }
10242
10243 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
10244 dev_close(netdev);
10245
10246 rtnl_unlock();
10247
10248 err = pci_cleanup_aer_uncorrect_error_status(pdev);
10249 if (err) {
10250 dev_err(&pdev->dev,
10251 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
10252 err); /* non-fatal, continue */
10253 }
10254
10255 return PCI_ERS_RESULT_RECOVERED;
10256}
10257
10258/**
10259 * bnxt_io_resume - called when traffic can start flowing again.
10260 * @pdev: Pointer to PCI device
10261 *
10262 * This callback is called when the error recovery driver tells
10263 * us that its OK to resume normal operation.
10264 */
10265static void bnxt_io_resume(struct pci_dev *pdev)
10266{
10267 struct net_device *netdev = pci_get_drvdata(pdev);
10268
10269 rtnl_lock();
10270
10271 netif_device_attach(netdev);
10272
10273 rtnl_unlock();
10274}
10275
10276static const struct pci_error_handlers bnxt_err_handler = {
10277 .error_detected = bnxt_io_error_detected,
10278 .slot_reset = bnxt_io_slot_reset,
10279 .resume = bnxt_io_resume
10280};
10281
c0c050c5
MC		 10282static struct pci_driver bnxt_pci_driver = {
10283 .name = DRV_MODULE_NAME,
10284 .id_table = bnxt_pci_tbl,
10285 .probe = bnxt_init_one,
10286 .remove = bnxt_remove_one,
d196ece7 10287 .shutdown = bnxt_shutdown,
f65a2044 10288 .driver.pm = BNXT_PM_OPS,
6316ea6d 10289 .err_handler = &bnxt_err_handler,
c0c050c5
MC		 10290#if defined(CONFIG_BNXT_SRIOV)
10291 .sriov_configure = bnxt_sriov_configure,
10292#endif
10293};
10294
c213eae8
MC		 10295static int __init bnxt_init(void)
10296{
cabfb09d 10297 bnxt_debug_init();
c213eae8
MC		 10298 return pci_register_driver(&bnxt_pci_driver);
10299}
10300
10301static void __exit bnxt_exit(void)
10302{
10303 pci_unregister_driver(&bnxt_pci_driver);
10304 if (bnxt_pf_wq)
10305 destroy_workqueue(bnxt_pf_wq);
cabfb09d 10306 bnxt_debug_exit();
c213eae8
MC		 10307}
10308
10309module_init(bnxt_init);
10310module_exit(bnxt_exit);
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