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Commit | Line | Data |
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c0c050c5 MC |
1 | /* Broadcom NetXtreme-C/E network driver. |
2 | * | |
11f15ed3 | 3 | * Copyright (c) 2014-2016 Broadcom Corporation |
c6cc32a2 | 4 | * Copyright (c) 2016-2019 Broadcom Limited |
c0c050c5 MC |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | ||
13 | #include <linux/stringify.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/timer.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/ioport.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/vmalloc.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/etherdevice.h> | |
24 | #include <linux/skbuff.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/bitops.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/irq.h> | |
29 | #include <linux/delay.h> | |
30 | #include <asm/byteorder.h> | |
31 | #include <asm/page.h> | |
32 | #include <linux/time.h> | |
33 | #include <linux/mii.h> | |
0ca12be9 | 34 | #include <linux/mdio.h> |
c0c050c5 MC |
35 | #include <linux/if.h> |
36 | #include <linux/if_vlan.h> | |
32e8239c | 37 | #include <linux/if_bridge.h> |
5ac67d8b | 38 | #include <linux/rtc.h> |
c6d30e83 | 39 | #include <linux/bpf.h> |
c0c050c5 MC |
40 | #include <net/ip.h> |
41 | #include <net/tcp.h> | |
42 | #include <net/udp.h> | |
43 | #include <net/checksum.h> | |
44 | #include <net/ip6_checksum.h> | |
ad51b8e9 | 45 | #include <net/udp_tunnel.h> |
c0c050c5 MC |
46 | #include <linux/workqueue.h> |
47 | #include <linux/prefetch.h> | |
48 | #include <linux/cache.h> | |
49 | #include <linux/log2.h> | |
50 | #include <linux/aer.h> | |
51 | #include <linux/bitmap.h> | |
52 | #include <linux/cpu_rmap.h> | |
56f0fd80 | 53 | #include <linux/cpumask.h> |
2ae7408f | 54 | #include <net/pkt_cls.h> |
cde49a42 VV |
55 | #include <linux/hwmon.h> |
56 | #include <linux/hwmon-sysfs.h> | |
322b87ca | 57 | #include <net/page_pool.h> |
c0c050c5 MC |
58 | |
59 | #include "bnxt_hsi.h" | |
60 | #include "bnxt.h" | |
a588e458 | 61 | #include "bnxt_ulp.h" |
c0c050c5 MC |
62 | #include "bnxt_sriov.h" |
63 | #include "bnxt_ethtool.h" | |
7df4ae9f | 64 | #include "bnxt_dcb.h" |
c6d30e83 | 65 | #include "bnxt_xdp.h" |
4ab0c6a8 | 66 | #include "bnxt_vfr.h" |
2ae7408f | 67 | #include "bnxt_tc.h" |
3c467bf3 | 68 | #include "bnxt_devlink.h" |
cabfb09d | 69 | #include "bnxt_debugfs.h" |
c0c050c5 MC |
70 | |
71 | #define BNXT_TX_TIMEOUT (5 * HZ) | |
72 | ||
73 | static const char version[] = | |
74 | "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n"; | |
75 | ||
76 | MODULE_LICENSE("GPL"); | |
77 | MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); | |
78 | MODULE_VERSION(DRV_MODULE_VERSION); | |
79 | ||
80 | #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) | |
81 | #define BNXT_RX_DMA_OFFSET NET_SKB_PAD | |
82 | #define BNXT_RX_COPY_THRESH 256 | |
83 | ||
4419dbe6 | 84 | #define BNXT_TX_PUSH_THRESH 164 |
c0c050c5 MC |
85 | |
86 | enum board_idx { | |
fbc9a523 | 87 | BCM57301, |
c0c050c5 MC |
88 | BCM57302, |
89 | BCM57304, | |
1f681688 | 90 | BCM57417_NPAR, |
fa853dda | 91 | BCM58700, |
b24eb6ae MC |
92 | BCM57311, |
93 | BCM57312, | |
fbc9a523 | 94 | BCM57402, |
c0c050c5 MC |
95 | BCM57404, |
96 | BCM57406, | |
1f681688 MC |
97 | BCM57402_NPAR, |
98 | BCM57407, | |
b24eb6ae MC |
99 | BCM57412, |
100 | BCM57414, | |
101 | BCM57416, | |
102 | BCM57417, | |
1f681688 | 103 | BCM57412_NPAR, |
5049e33b | 104 | BCM57314, |
1f681688 MC |
105 | BCM57417_SFP, |
106 | BCM57416_SFP, | |
107 | BCM57404_NPAR, | |
108 | BCM57406_NPAR, | |
109 | BCM57407_SFP, | |
adbc8305 | 110 | BCM57407_NPAR, |
1f681688 MC |
111 | BCM57414_NPAR, |
112 | BCM57416_NPAR, | |
32b40798 DK |
113 | BCM57452, |
114 | BCM57454, | |
92abef36 | 115 | BCM5745x_NPAR, |
1ab968d2 | 116 | BCM57508, |
c6cc32a2 | 117 | BCM57504, |
51fec80d | 118 | BCM57502, |
49c98421 MC |
119 | BCM57508_NPAR, |
120 | BCM57504_NPAR, | |
121 | BCM57502_NPAR, | |
4a58139b | 122 | BCM58802, |
8ed693b7 | 123 | BCM58804, |
4a58139b | 124 | BCM58808, |
adbc8305 MC |
125 | NETXTREME_E_VF, |
126 | NETXTREME_C_VF, | |
618784e3 | 127 | NETXTREME_S_VF, |
b16b6891 | 128 | NETXTREME_E_P5_VF, |
c0c050c5 MC |
129 | }; |
130 | ||
131 | /* indexed by enum above */ | |
132 | static const struct { | |
133 | char *name; | |
134 | } board_info[] = { | |
27573a7d SB |
135 | [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" }, |
136 | [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" }, | |
137 | [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, | |
138 | [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" }, | |
139 | [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" }, | |
140 | [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" }, | |
141 | [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" }, | |
142 | [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" }, | |
143 | [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" }, | |
144 | [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" }, | |
145 | [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" }, | |
146 | [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" }, | |
147 | [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" }, | |
148 | [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" }, | |
149 | [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" }, | |
150 | [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" }, | |
151 | [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" }, | |
152 | [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, | |
153 | [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" }, | |
154 | [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" }, | |
155 | [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" }, | |
156 | [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" }, | |
157 | [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" }, | |
158 | [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" }, | |
159 | [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" }, | |
160 | [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" }, | |
161 | [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" }, | |
162 | [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, | |
92abef36 | 163 | [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" }, |
1ab968d2 | 164 | [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, |
c6cc32a2 | 165 | [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, |
51fec80d | 166 | [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" }, |
49c98421 MC |
167 | [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" }, |
168 | [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" }, | |
169 | [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" }, | |
27573a7d | 170 | [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" }, |
8ed693b7 | 171 | [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, |
27573a7d SB |
172 | [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, |
173 | [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" }, | |
174 | [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" }, | |
618784e3 | 175 | [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" }, |
b16b6891 | 176 | [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" }, |
c0c050c5 MC |
177 | }; |
178 | ||
179 | static const struct pci_device_id bnxt_pci_tbl[] = { | |
92abef36 VV |
180 | { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR }, |
181 | { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR }, | |
4a58139b | 182 | { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 }, |
adbc8305 | 183 | { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR }, |
fbc9a523 | 184 | { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, |
c0c050c5 MC |
185 | { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, |
186 | { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, | |
1f681688 | 187 | { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR }, |
fa853dda | 188 | { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 }, |
b24eb6ae MC |
189 | { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 }, |
190 | { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 }, | |
fbc9a523 | 191 | { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, |
c0c050c5 MC |
192 | { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, |
193 | { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, | |
1f681688 MC |
194 | { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR }, |
195 | { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 }, | |
b24eb6ae MC |
196 | { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 }, |
197 | { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 }, | |
198 | { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 }, | |
199 | { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 }, | |
1f681688 | 200 | { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR }, |
5049e33b | 201 | { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 }, |
1f681688 MC |
202 | { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP }, |
203 | { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP }, | |
204 | { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR }, | |
205 | { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR }, | |
206 | { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP }, | |
adbc8305 MC |
207 | { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR }, |
208 | { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR }, | |
1f681688 | 209 | { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR }, |
adbc8305 | 210 | { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR }, |
1f681688 | 211 | { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR }, |
adbc8305 | 212 | { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR }, |
4a58139b | 213 | { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 }, |
32b40798 | 214 | { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 }, |
1ab968d2 | 215 | { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 }, |
c6cc32a2 | 216 | { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 }, |
51fec80d | 217 | { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 }, |
49c98421 MC |
218 | { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57508_NPAR }, |
219 | { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR }, | |
220 | { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57502_NPAR }, | |
221 | { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57508_NPAR }, | |
222 | { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR }, | |
223 | { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57502_NPAR }, | |
4a58139b | 224 | { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 }, |
8ed693b7 | 225 | { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 }, |
c0c050c5 | 226 | #ifdef CONFIG_BNXT_SRIOV |
c7ef35eb DK |
227 | { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF }, |
228 | { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF }, | |
adbc8305 MC |
229 | { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF }, |
230 | { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF }, | |
231 | { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF }, | |
232 | { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF }, | |
233 | { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF }, | |
234 | { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF }, | |
51fec80d | 235 | { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF }, |
b16b6891 | 236 | { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF }, |
618784e3 | 237 | { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF }, |
c0c050c5 MC |
238 | #endif |
239 | { 0 } | |
240 | }; | |
241 | ||
242 | MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); | |
243 | ||
244 | static const u16 bnxt_vf_req_snif[] = { | |
245 | HWRM_FUNC_CFG, | |
91cdda40 | 246 | HWRM_FUNC_VF_CFG, |
c0c050c5 MC |
247 | HWRM_PORT_PHY_QCFG, |
248 | HWRM_CFA_L2_FILTER_ALLOC, | |
249 | }; | |
250 | ||
25be8623 | 251 | static const u16 bnxt_async_events_arr[] = { |
87c374de | 252 | ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, |
b1613e78 | 253 | ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE, |
87c374de MC |
254 | ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD, |
255 | ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED, | |
256 | ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE, | |
257 | ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, | |
b1613e78 | 258 | ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE, |
2151fe08 | 259 | ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY, |
7e914027 | 260 | ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY, |
25be8623 MC |
261 | }; |
262 | ||
c213eae8 MC |
263 | static struct workqueue_struct *bnxt_pf_wq; |
264 | ||
c0c050c5 MC |
265 | static bool bnxt_vf_pciid(enum board_idx idx) |
266 | { | |
618784e3 | 267 | return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF || |
b16b6891 | 268 | idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF); |
c0c050c5 MC |
269 | } |
270 | ||
271 | #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) | |
272 | #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) | |
273 | #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) | |
274 | ||
c0c050c5 MC |
275 | #define BNXT_CP_DB_IRQ_DIS(db) \ |
276 | writel(DB_CP_IRQ_DIS_FLAGS, db) | |
277 | ||
697197e5 MC |
278 | #define BNXT_DB_CQ(db, idx) \ |
279 | writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell) | |
280 | ||
281 | #define BNXT_DB_NQ_P5(db, idx) \ | |
282 | writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell) | |
283 | ||
284 | #define BNXT_DB_CQ_ARM(db, idx) \ | |
285 | writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell) | |
286 | ||
287 | #define BNXT_DB_NQ_ARM_P5(db, idx) \ | |
288 | writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell) | |
289 | ||
290 | static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) | |
291 | { | |
292 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
293 | BNXT_DB_NQ_P5(db, idx); | |
294 | else | |
295 | BNXT_DB_CQ(db, idx); | |
296 | } | |
297 | ||
298 | static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) | |
299 | { | |
300 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
301 | BNXT_DB_NQ_ARM_P5(db, idx); | |
302 | else | |
303 | BNXT_DB_CQ_ARM(db, idx); | |
304 | } | |
305 | ||
306 | static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) | |
307 | { | |
308 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
309 | writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx), | |
310 | db->doorbell); | |
311 | else | |
312 | BNXT_DB_CQ(db, idx); | |
313 | } | |
314 | ||
38413406 | 315 | const u16 bnxt_lhint_arr[] = { |
c0c050c5 MC |
316 | TX_BD_FLAGS_LHINT_512_AND_SMALLER, |
317 | TX_BD_FLAGS_LHINT_512_TO_1023, | |
318 | TX_BD_FLAGS_LHINT_1024_TO_2047, | |
319 | TX_BD_FLAGS_LHINT_1024_TO_2047, | |
320 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
321 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
322 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
323 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
324 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
325 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
326 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
327 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
328 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
329 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
330 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
331 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
332 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
333 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
334 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
335 | }; | |
336 | ||
ee5c7fb3 SP |
337 | static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb) |
338 | { | |
339 | struct metadata_dst *md_dst = skb_metadata_dst(skb); | |
340 | ||
341 | if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX) | |
342 | return 0; | |
343 | ||
344 | return md_dst->u.port_info.port_id; | |
345 | } | |
346 | ||
c0c050c5 MC |
347 | static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) |
348 | { | |
349 | struct bnxt *bp = netdev_priv(dev); | |
350 | struct tx_bd *txbd; | |
351 | struct tx_bd_ext *txbd1; | |
352 | struct netdev_queue *txq; | |
353 | int i; | |
354 | dma_addr_t mapping; | |
355 | unsigned int length, pad = 0; | |
356 | u32 len, free_size, vlan_tag_flags, cfa_action, flags; | |
357 | u16 prod, last_frag; | |
358 | struct pci_dev *pdev = bp->pdev; | |
c0c050c5 MC |
359 | struct bnxt_tx_ring_info *txr; |
360 | struct bnxt_sw_tx_bd *tx_buf; | |
361 | ||
362 | i = skb_get_queue_mapping(skb); | |
363 | if (unlikely(i >= bp->tx_nr_rings)) { | |
364 | dev_kfree_skb_any(skb); | |
365 | return NETDEV_TX_OK; | |
366 | } | |
367 | ||
c0c050c5 | 368 | txq = netdev_get_tx_queue(dev, i); |
a960dec9 | 369 | txr = &bp->tx_ring[bp->tx_ring_map[i]]; |
c0c050c5 MC |
370 | prod = txr->tx_prod; |
371 | ||
372 | free_size = bnxt_tx_avail(bp, txr); | |
373 | if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { | |
374 | netif_tx_stop_queue(txq); | |
375 | return NETDEV_TX_BUSY; | |
376 | } | |
377 | ||
378 | length = skb->len; | |
379 | len = skb_headlen(skb); | |
380 | last_frag = skb_shinfo(skb)->nr_frags; | |
381 | ||
382 | txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; | |
383 | ||
384 | txbd->tx_bd_opaque = prod; | |
385 | ||
386 | tx_buf = &txr->tx_buf_ring[prod]; | |
387 | tx_buf->skb = skb; | |
388 | tx_buf->nr_frags = last_frag; | |
389 | ||
390 | vlan_tag_flags = 0; | |
ee5c7fb3 | 391 | cfa_action = bnxt_xmit_get_cfa_action(skb); |
c0c050c5 MC |
392 | if (skb_vlan_tag_present(skb)) { |
393 | vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | | |
394 | skb_vlan_tag_get(skb); | |
395 | /* Currently supports 8021Q, 8021AD vlan offloads | |
396 | * QINQ1, QINQ2, QINQ3 vlan headers are deprecated | |
397 | */ | |
398 | if (skb->vlan_proto == htons(ETH_P_8021Q)) | |
399 | vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; | |
400 | } | |
401 | ||
402 | if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) { | |
4419dbe6 MC |
403 | struct tx_push_buffer *tx_push_buf = txr->tx_push; |
404 | struct tx_push_bd *tx_push = &tx_push_buf->push_bd; | |
405 | struct tx_bd_ext *tx_push1 = &tx_push->txbd2; | |
697197e5 | 406 | void __iomem *db = txr->tx_db.doorbell; |
4419dbe6 MC |
407 | void *pdata = tx_push_buf->data; |
408 | u64 *end; | |
409 | int j, push_len; | |
c0c050c5 MC |
410 | |
411 | /* Set COAL_NOW to be ready quickly for the next push */ | |
412 | tx_push->tx_bd_len_flags_type = | |
413 | cpu_to_le32((length << TX_BD_LEN_SHIFT) | | |
414 | TX_BD_TYPE_LONG_TX_BD | | |
415 | TX_BD_FLAGS_LHINT_512_AND_SMALLER | | |
416 | TX_BD_FLAGS_COAL_NOW | | |
417 | TX_BD_FLAGS_PACKET_END | | |
418 | (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); | |
419 | ||
420 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
421 | tx_push1->tx_bd_hsize_lflags = | |
422 | cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); | |
423 | else | |
424 | tx_push1->tx_bd_hsize_lflags = 0; | |
425 | ||
426 | tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); | |
ee5c7fb3 SP |
427 | tx_push1->tx_bd_cfa_action = |
428 | cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); | |
c0c050c5 | 429 | |
fbb0fa8b MC |
430 | end = pdata + length; |
431 | end = PTR_ALIGN(end, 8) - 1; | |
4419dbe6 MC |
432 | *end = 0; |
433 | ||
c0c050c5 MC |
434 | skb_copy_from_linear_data(skb, pdata, len); |
435 | pdata += len; | |
436 | for (j = 0; j < last_frag; j++) { | |
437 | skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; | |
438 | void *fptr; | |
439 | ||
440 | fptr = skb_frag_address_safe(frag); | |
441 | if (!fptr) | |
442 | goto normal_tx; | |
443 | ||
444 | memcpy(pdata, fptr, skb_frag_size(frag)); | |
445 | pdata += skb_frag_size(frag); | |
446 | } | |
447 | ||
4419dbe6 MC |
448 | txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type; |
449 | txbd->tx_bd_haddr = txr->data_mapping; | |
c0c050c5 MC |
450 | prod = NEXT_TX(prod); |
451 | txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; | |
452 | memcpy(txbd, tx_push1, sizeof(*txbd)); | |
453 | prod = NEXT_TX(prod); | |
4419dbe6 | 454 | tx_push->doorbell = |
c0c050c5 MC |
455 | cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); |
456 | txr->tx_prod = prod; | |
457 | ||
b9a8460a | 458 | tx_buf->is_push = 1; |
c0c050c5 | 459 | netdev_tx_sent_queue(txq, skb->len); |
b9a8460a | 460 | wmb(); /* Sync is_push and byte queue before pushing data */ |
c0c050c5 | 461 | |
4419dbe6 MC |
462 | push_len = (length + sizeof(*tx_push) + 7) / 8; |
463 | if (push_len > 16) { | |
697197e5 MC |
464 | __iowrite64_copy(db, tx_push_buf, 16); |
465 | __iowrite32_copy(db + 4, tx_push_buf + 1, | |
9d13744b | 466 | (push_len - 16) << 1); |
4419dbe6 | 467 | } else { |
697197e5 | 468 | __iowrite64_copy(db, tx_push_buf, push_len); |
4419dbe6 | 469 | } |
c0c050c5 | 470 | |
c0c050c5 MC |
471 | goto tx_done; |
472 | } | |
473 | ||
474 | normal_tx: | |
475 | if (length < BNXT_MIN_PKT_SIZE) { | |
476 | pad = BNXT_MIN_PKT_SIZE - length; | |
477 | if (skb_pad(skb, pad)) { | |
478 | /* SKB already freed. */ | |
479 | tx_buf->skb = NULL; | |
480 | return NETDEV_TX_OK; | |
481 | } | |
482 | length = BNXT_MIN_PKT_SIZE; | |
483 | } | |
484 | ||
485 | mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); | |
486 | ||
487 | if (unlikely(dma_mapping_error(&pdev->dev, mapping))) { | |
488 | dev_kfree_skb_any(skb); | |
489 | tx_buf->skb = NULL; | |
490 | return NETDEV_TX_OK; | |
491 | } | |
492 | ||
493 | dma_unmap_addr_set(tx_buf, mapping, mapping); | |
494 | flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | | |
495 | ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); | |
496 | ||
497 | txbd->tx_bd_haddr = cpu_to_le64(mapping); | |
498 | ||
499 | prod = NEXT_TX(prod); | |
500 | txbd1 = (struct tx_bd_ext *) | |
501 | &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; | |
502 | ||
503 | txbd1->tx_bd_hsize_lflags = 0; | |
504 | if (skb_is_gso(skb)) { | |
505 | u32 hdr_len; | |
506 | ||
507 | if (skb->encapsulation) | |
508 | hdr_len = skb_inner_network_offset(skb) + | |
509 | skb_inner_network_header_len(skb) + | |
510 | inner_tcp_hdrlen(skb); | |
511 | else | |
512 | hdr_len = skb_transport_offset(skb) + | |
513 | tcp_hdrlen(skb); | |
514 | ||
515 | txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO | | |
516 | TX_BD_FLAGS_T_IPID | | |
517 | (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); | |
518 | length = skb_shinfo(skb)->gso_size; | |
519 | txbd1->tx_bd_mss = cpu_to_le32(length); | |
520 | length += hdr_len; | |
521 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
522 | txbd1->tx_bd_hsize_lflags = | |
523 | cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); | |
524 | txbd1->tx_bd_mss = 0; | |
525 | } | |
526 | ||
527 | length >>= 9; | |
2b3c6885 MC |
528 | if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) { |
529 | dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n", | |
530 | skb->len); | |
531 | i = 0; | |
532 | goto tx_dma_error; | |
533 | } | |
c0c050c5 MC |
534 | flags |= bnxt_lhint_arr[length]; |
535 | txbd->tx_bd_len_flags_type = cpu_to_le32(flags); | |
536 | ||
537 | txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); | |
ee5c7fb3 SP |
538 | txbd1->tx_bd_cfa_action = |
539 | cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); | |
c0c050c5 MC |
540 | for (i = 0; i < last_frag; i++) { |
541 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
542 | ||
543 | prod = NEXT_TX(prod); | |
544 | txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; | |
545 | ||
546 | len = skb_frag_size(frag); | |
547 | mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, | |
548 | DMA_TO_DEVICE); | |
549 | ||
550 | if (unlikely(dma_mapping_error(&pdev->dev, mapping))) | |
551 | goto tx_dma_error; | |
552 | ||
553 | tx_buf = &txr->tx_buf_ring[prod]; | |
554 | dma_unmap_addr_set(tx_buf, mapping, mapping); | |
555 | ||
556 | txbd->tx_bd_haddr = cpu_to_le64(mapping); | |
557 | ||
558 | flags = len << TX_BD_LEN_SHIFT; | |
559 | txbd->tx_bd_len_flags_type = cpu_to_le32(flags); | |
560 | } | |
561 | ||
562 | flags &= ~TX_BD_LEN; | |
563 | txbd->tx_bd_len_flags_type = | |
564 | cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | | |
565 | TX_BD_FLAGS_PACKET_END); | |
566 | ||
567 | netdev_tx_sent_queue(txq, skb->len); | |
568 | ||
569 | /* Sync BD data before updating doorbell */ | |
570 | wmb(); | |
571 | ||
572 | prod = NEXT_TX(prod); | |
573 | txr->tx_prod = prod; | |
574 | ||
6b16f9ee | 575 | if (!netdev_xmit_more() || netif_xmit_stopped(txq)) |
697197e5 | 576 | bnxt_db_write(bp, &txr->tx_db, prod); |
c0c050c5 MC |
577 | |
578 | tx_done: | |
579 | ||
c0c050c5 | 580 | if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { |
6b16f9ee | 581 | if (netdev_xmit_more() && !tx_buf->is_push) |
697197e5 | 582 | bnxt_db_write(bp, &txr->tx_db, prod); |
4d172f21 | 583 | |
c0c050c5 MC |
584 | netif_tx_stop_queue(txq); |
585 | ||
586 | /* netif_tx_stop_queue() must be done before checking | |
587 | * tx index in bnxt_tx_avail() below, because in | |
588 | * bnxt_tx_int(), we update tx index before checking for | |
589 | * netif_tx_queue_stopped(). | |
590 | */ | |
591 | smp_mb(); | |
592 | if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) | |
593 | netif_tx_wake_queue(txq); | |
594 | } | |
595 | return NETDEV_TX_OK; | |
596 | ||
597 | tx_dma_error: | |
598 | last_frag = i; | |
599 | ||
600 | /* start back at beginning and unmap skb */ | |
601 | prod = txr->tx_prod; | |
602 | tx_buf = &txr->tx_buf_ring[prod]; | |
603 | tx_buf->skb = NULL; | |
604 | dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), | |
605 | skb_headlen(skb), PCI_DMA_TODEVICE); | |
606 | prod = NEXT_TX(prod); | |
607 | ||
608 | /* unmap remaining mapped pages */ | |
609 | for (i = 0; i < last_frag; i++) { | |
610 | prod = NEXT_TX(prod); | |
611 | tx_buf = &txr->tx_buf_ring[prod]; | |
612 | dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), | |
613 | skb_frag_size(&skb_shinfo(skb)->frags[i]), | |
614 | PCI_DMA_TODEVICE); | |
615 | } | |
616 | ||
617 | dev_kfree_skb_any(skb); | |
618 | return NETDEV_TX_OK; | |
619 | } | |
620 | ||
621 | static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) | |
622 | { | |
b6ab4b01 | 623 | struct bnxt_tx_ring_info *txr = bnapi->tx_ring; |
a960dec9 | 624 | struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index); |
c0c050c5 MC |
625 | u16 cons = txr->tx_cons; |
626 | struct pci_dev *pdev = bp->pdev; | |
627 | int i; | |
628 | unsigned int tx_bytes = 0; | |
629 | ||
630 | for (i = 0; i < nr_pkts; i++) { | |
631 | struct bnxt_sw_tx_bd *tx_buf; | |
632 | struct sk_buff *skb; | |
633 | int j, last; | |
634 | ||
635 | tx_buf = &txr->tx_buf_ring[cons]; | |
636 | cons = NEXT_TX(cons); | |
637 | skb = tx_buf->skb; | |
638 | tx_buf->skb = NULL; | |
639 | ||
640 | if (tx_buf->is_push) { | |
641 | tx_buf->is_push = 0; | |
642 | goto next_tx_int; | |
643 | } | |
644 | ||
645 | dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), | |
646 | skb_headlen(skb), PCI_DMA_TODEVICE); | |
647 | last = tx_buf->nr_frags; | |
648 | ||
649 | for (j = 0; j < last; j++) { | |
650 | cons = NEXT_TX(cons); | |
651 | tx_buf = &txr->tx_buf_ring[cons]; | |
652 | dma_unmap_page( | |
653 | &pdev->dev, | |
654 | dma_unmap_addr(tx_buf, mapping), | |
655 | skb_frag_size(&skb_shinfo(skb)->frags[j]), | |
656 | PCI_DMA_TODEVICE); | |
657 | } | |
658 | ||
659 | next_tx_int: | |
660 | cons = NEXT_TX(cons); | |
661 | ||
662 | tx_bytes += skb->len; | |
663 | dev_kfree_skb_any(skb); | |
664 | } | |
665 | ||
666 | netdev_tx_completed_queue(txq, nr_pkts, tx_bytes); | |
667 | txr->tx_cons = cons; | |
668 | ||
669 | /* Need to make the tx_cons update visible to bnxt_start_xmit() | |
670 | * before checking for netif_tx_queue_stopped(). Without the | |
671 | * memory barrier, there is a small possibility that bnxt_start_xmit() | |
672 | * will miss it and cause the queue to be stopped forever. | |
673 | */ | |
674 | smp_mb(); | |
675 | ||
676 | if (unlikely(netif_tx_queue_stopped(txq)) && | |
677 | (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) { | |
678 | __netif_tx_lock(txq, smp_processor_id()); | |
679 | if (netif_tx_queue_stopped(txq) && | |
680 | bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh && | |
681 | txr->dev_state != BNXT_DEV_STATE_CLOSING) | |
682 | netif_tx_wake_queue(txq); | |
683 | __netif_tx_unlock(txq); | |
684 | } | |
685 | } | |
686 | ||
c61fb99c | 687 | static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping, |
322b87ca | 688 | struct bnxt_rx_ring_info *rxr, |
c61fb99c MC |
689 | gfp_t gfp) |
690 | { | |
691 | struct device *dev = &bp->pdev->dev; | |
692 | struct page *page; | |
693 | ||
322b87ca | 694 | page = page_pool_dev_alloc_pages(rxr->page_pool); |
c61fb99c MC |
695 | if (!page) |
696 | return NULL; | |
697 | ||
c519fe9a SN |
698 | *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir, |
699 | DMA_ATTR_WEAK_ORDERING); | |
c61fb99c | 700 | if (dma_mapping_error(dev, *mapping)) { |
322b87ca | 701 | page_pool_recycle_direct(rxr->page_pool, page); |
c61fb99c MC |
702 | return NULL; |
703 | } | |
704 | *mapping += bp->rx_dma_offset; | |
705 | return page; | |
706 | } | |
707 | ||
c0c050c5 MC |
708 | static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping, |
709 | gfp_t gfp) | |
710 | { | |
711 | u8 *data; | |
712 | struct pci_dev *pdev = bp->pdev; | |
713 | ||
714 | data = kmalloc(bp->rx_buf_size, gfp); | |
715 | if (!data) | |
716 | return NULL; | |
717 | ||
c519fe9a SN |
718 | *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset, |
719 | bp->rx_buf_use_size, bp->rx_dir, | |
720 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
721 | |
722 | if (dma_mapping_error(&pdev->dev, *mapping)) { | |
723 | kfree(data); | |
724 | data = NULL; | |
725 | } | |
726 | return data; | |
727 | } | |
728 | ||
38413406 MC |
729 | int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, |
730 | u16 prod, gfp_t gfp) | |
c0c050c5 MC |
731 | { |
732 | struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
733 | struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; | |
c0c050c5 MC |
734 | dma_addr_t mapping; |
735 | ||
c61fb99c | 736 | if (BNXT_RX_PAGE_MODE(bp)) { |
322b87ca AG |
737 | struct page *page = |
738 | __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp); | |
c0c050c5 | 739 | |
c61fb99c MC |
740 | if (!page) |
741 | return -ENOMEM; | |
742 | ||
743 | rx_buf->data = page; | |
744 | rx_buf->data_ptr = page_address(page) + bp->rx_offset; | |
745 | } else { | |
746 | u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp); | |
747 | ||
748 | if (!data) | |
749 | return -ENOMEM; | |
750 | ||
751 | rx_buf->data = data; | |
752 | rx_buf->data_ptr = data + bp->rx_offset; | |
753 | } | |
11cd119d | 754 | rx_buf->mapping = mapping; |
c0c050c5 MC |
755 | |
756 | rxbd->rx_bd_haddr = cpu_to_le64(mapping); | |
c0c050c5 MC |
757 | return 0; |
758 | } | |
759 | ||
c6d30e83 | 760 | void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data) |
c0c050c5 MC |
761 | { |
762 | u16 prod = rxr->rx_prod; | |
763 | struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; | |
764 | struct rx_bd *cons_bd, *prod_bd; | |
765 | ||
766 | prod_rx_buf = &rxr->rx_buf_ring[prod]; | |
767 | cons_rx_buf = &rxr->rx_buf_ring[cons]; | |
768 | ||
769 | prod_rx_buf->data = data; | |
6bb19474 | 770 | prod_rx_buf->data_ptr = cons_rx_buf->data_ptr; |
c0c050c5 | 771 | |
11cd119d | 772 | prod_rx_buf->mapping = cons_rx_buf->mapping; |
c0c050c5 MC |
773 | |
774 | prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
775 | cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; | |
776 | ||
777 | prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; | |
778 | } | |
779 | ||
780 | static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) | |
781 | { | |
782 | u16 next, max = rxr->rx_agg_bmap_size; | |
783 | ||
784 | next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); | |
785 | if (next >= max) | |
786 | next = find_first_zero_bit(rxr->rx_agg_bmap, max); | |
787 | return next; | |
788 | } | |
789 | ||
790 | static inline int bnxt_alloc_rx_page(struct bnxt *bp, | |
791 | struct bnxt_rx_ring_info *rxr, | |
792 | u16 prod, gfp_t gfp) | |
793 | { | |
794 | struct rx_bd *rxbd = | |
795 | &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
796 | struct bnxt_sw_rx_agg_bd *rx_agg_buf; | |
797 | struct pci_dev *pdev = bp->pdev; | |
798 | struct page *page; | |
799 | dma_addr_t mapping; | |
800 | u16 sw_prod = rxr->rx_sw_agg_prod; | |
89d0a06c | 801 | unsigned int offset = 0; |
c0c050c5 | 802 | |
89d0a06c MC |
803 | if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) { |
804 | page = rxr->rx_page; | |
805 | if (!page) { | |
806 | page = alloc_page(gfp); | |
807 | if (!page) | |
808 | return -ENOMEM; | |
809 | rxr->rx_page = page; | |
810 | rxr->rx_page_offset = 0; | |
811 | } | |
812 | offset = rxr->rx_page_offset; | |
813 | rxr->rx_page_offset += BNXT_RX_PAGE_SIZE; | |
814 | if (rxr->rx_page_offset == PAGE_SIZE) | |
815 | rxr->rx_page = NULL; | |
816 | else | |
817 | get_page(page); | |
818 | } else { | |
819 | page = alloc_page(gfp); | |
820 | if (!page) | |
821 | return -ENOMEM; | |
822 | } | |
c0c050c5 | 823 | |
c519fe9a SN |
824 | mapping = dma_map_page_attrs(&pdev->dev, page, offset, |
825 | BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE, | |
826 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
827 | if (dma_mapping_error(&pdev->dev, mapping)) { |
828 | __free_page(page); | |
829 | return -EIO; | |
830 | } | |
831 | ||
832 | if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) | |
833 | sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); | |
834 | ||
835 | __set_bit(sw_prod, rxr->rx_agg_bmap); | |
836 | rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; | |
837 | rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); | |
838 | ||
839 | rx_agg_buf->page = page; | |
89d0a06c | 840 | rx_agg_buf->offset = offset; |
c0c050c5 MC |
841 | rx_agg_buf->mapping = mapping; |
842 | rxbd->rx_bd_haddr = cpu_to_le64(mapping); | |
843 | rxbd->rx_bd_opaque = sw_prod; | |
844 | return 0; | |
845 | } | |
846 | ||
4a228a3a MC |
847 | static struct rx_agg_cmp *bnxt_get_agg(struct bnxt *bp, |
848 | struct bnxt_cp_ring_info *cpr, | |
849 | u16 cp_cons, u16 curr) | |
850 | { | |
851 | struct rx_agg_cmp *agg; | |
852 | ||
853 | cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr)); | |
854 | agg = (struct rx_agg_cmp *) | |
855 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
856 | return agg; | |
857 | } | |
858 | ||
bfcd8d79 MC |
859 | static struct rx_agg_cmp *bnxt_get_tpa_agg_p5(struct bnxt *bp, |
860 | struct bnxt_rx_ring_info *rxr, | |
861 | u16 agg_id, u16 curr) | |
862 | { | |
863 | struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id]; | |
864 | ||
865 | return &tpa_info->agg_arr[curr]; | |
866 | } | |
867 | ||
4a228a3a MC |
868 | static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx, |
869 | u16 start, u32 agg_bufs, bool tpa) | |
c0c050c5 | 870 | { |
e44758b7 | 871 | struct bnxt_napi *bnapi = cpr->bnapi; |
c0c050c5 | 872 | struct bnxt *bp = bnapi->bp; |
b6ab4b01 | 873 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
c0c050c5 MC |
874 | u16 prod = rxr->rx_agg_prod; |
875 | u16 sw_prod = rxr->rx_sw_agg_prod; | |
bfcd8d79 | 876 | bool p5_tpa = false; |
c0c050c5 MC |
877 | u32 i; |
878 | ||
bfcd8d79 MC |
879 | if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) |
880 | p5_tpa = true; | |
881 | ||
c0c050c5 MC |
882 | for (i = 0; i < agg_bufs; i++) { |
883 | u16 cons; | |
884 | struct rx_agg_cmp *agg; | |
885 | struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; | |
886 | struct rx_bd *prod_bd; | |
887 | struct page *page; | |
888 | ||
bfcd8d79 MC |
889 | if (p5_tpa) |
890 | agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i); | |
891 | else | |
892 | agg = bnxt_get_agg(bp, cpr, idx, start + i); | |
c0c050c5 MC |
893 | cons = agg->rx_agg_cmp_opaque; |
894 | __clear_bit(cons, rxr->rx_agg_bmap); | |
895 | ||
896 | if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) | |
897 | sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); | |
898 | ||
899 | __set_bit(sw_prod, rxr->rx_agg_bmap); | |
900 | prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; | |
901 | cons_rx_buf = &rxr->rx_agg_ring[cons]; | |
902 | ||
903 | /* It is possible for sw_prod to be equal to cons, so | |
904 | * set cons_rx_buf->page to NULL first. | |
905 | */ | |
906 | page = cons_rx_buf->page; | |
907 | cons_rx_buf->page = NULL; | |
908 | prod_rx_buf->page = page; | |
89d0a06c | 909 | prod_rx_buf->offset = cons_rx_buf->offset; |
c0c050c5 MC |
910 | |
911 | prod_rx_buf->mapping = cons_rx_buf->mapping; | |
912 | ||
913 | prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
914 | ||
915 | prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); | |
916 | prod_bd->rx_bd_opaque = sw_prod; | |
917 | ||
918 | prod = NEXT_RX_AGG(prod); | |
919 | sw_prod = NEXT_RX_AGG(sw_prod); | |
c0c050c5 MC |
920 | } |
921 | rxr->rx_agg_prod = prod; | |
922 | rxr->rx_sw_agg_prod = sw_prod; | |
923 | } | |
924 | ||
c61fb99c MC |
925 | static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp, |
926 | struct bnxt_rx_ring_info *rxr, | |
927 | u16 cons, void *data, u8 *data_ptr, | |
928 | dma_addr_t dma_addr, | |
929 | unsigned int offset_and_len) | |
930 | { | |
931 | unsigned int payload = offset_and_len >> 16; | |
932 | unsigned int len = offset_and_len & 0xffff; | |
d7840976 | 933 | skb_frag_t *frag; |
c61fb99c MC |
934 | struct page *page = data; |
935 | u16 prod = rxr->rx_prod; | |
936 | struct sk_buff *skb; | |
937 | int off, err; | |
938 | ||
939 | err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); | |
940 | if (unlikely(err)) { | |
941 | bnxt_reuse_rx_data(rxr, cons, data); | |
942 | return NULL; | |
943 | } | |
944 | dma_addr -= bp->rx_dma_offset; | |
c519fe9a SN |
945 | dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir, |
946 | DMA_ATTR_WEAK_ORDERING); | |
3071c517 | 947 | page_pool_release_page(rxr->page_pool, page); |
c61fb99c MC |
948 | |
949 | if (unlikely(!payload)) | |
c43f1255 | 950 | payload = eth_get_headlen(bp->dev, data_ptr, len); |
c61fb99c MC |
951 | |
952 | skb = napi_alloc_skb(&rxr->bnapi->napi, payload); | |
953 | if (!skb) { | |
954 | __free_page(page); | |
955 | return NULL; | |
956 | } | |
957 | ||
958 | off = (void *)data_ptr - page_address(page); | |
959 | skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE); | |
960 | memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN, | |
961 | payload + NET_IP_ALIGN); | |
962 | ||
963 | frag = &skb_shinfo(skb)->frags[0]; | |
964 | skb_frag_size_sub(frag, payload); | |
b54c9d5b | 965 | skb_frag_off_add(frag, payload); |
c61fb99c MC |
966 | skb->data_len -= payload; |
967 | skb->tail += payload; | |
968 | ||
969 | return skb; | |
970 | } | |
971 | ||
c0c050c5 MC |
972 | static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, |
973 | struct bnxt_rx_ring_info *rxr, u16 cons, | |
6bb19474 MC |
974 | void *data, u8 *data_ptr, |
975 | dma_addr_t dma_addr, | |
976 | unsigned int offset_and_len) | |
c0c050c5 | 977 | { |
6bb19474 | 978 | u16 prod = rxr->rx_prod; |
c0c050c5 | 979 | struct sk_buff *skb; |
6bb19474 | 980 | int err; |
c0c050c5 MC |
981 | |
982 | err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); | |
983 | if (unlikely(err)) { | |
984 | bnxt_reuse_rx_data(rxr, cons, data); | |
985 | return NULL; | |
986 | } | |
987 | ||
988 | skb = build_skb(data, 0); | |
c519fe9a SN |
989 | dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, |
990 | bp->rx_dir, DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
991 | if (!skb) { |
992 | kfree(data); | |
993 | return NULL; | |
994 | } | |
995 | ||
b3dba77c | 996 | skb_reserve(skb, bp->rx_offset); |
6bb19474 | 997 | skb_put(skb, offset_and_len & 0xffff); |
c0c050c5 MC |
998 | return skb; |
999 | } | |
1000 | ||
e44758b7 MC |
1001 | static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, |
1002 | struct bnxt_cp_ring_info *cpr, | |
4a228a3a MC |
1003 | struct sk_buff *skb, u16 idx, |
1004 | u32 agg_bufs, bool tpa) | |
c0c050c5 | 1005 | { |
e44758b7 | 1006 | struct bnxt_napi *bnapi = cpr->bnapi; |
c0c050c5 | 1007 | struct pci_dev *pdev = bp->pdev; |
b6ab4b01 | 1008 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
c0c050c5 | 1009 | u16 prod = rxr->rx_agg_prod; |
bfcd8d79 | 1010 | bool p5_tpa = false; |
c0c050c5 MC |
1011 | u32 i; |
1012 | ||
bfcd8d79 MC |
1013 | if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) |
1014 | p5_tpa = true; | |
1015 | ||
c0c050c5 MC |
1016 | for (i = 0; i < agg_bufs; i++) { |
1017 | u16 cons, frag_len; | |
1018 | struct rx_agg_cmp *agg; | |
1019 | struct bnxt_sw_rx_agg_bd *cons_rx_buf; | |
1020 | struct page *page; | |
1021 | dma_addr_t mapping; | |
1022 | ||
bfcd8d79 MC |
1023 | if (p5_tpa) |
1024 | agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i); | |
1025 | else | |
1026 | agg = bnxt_get_agg(bp, cpr, idx, i); | |
c0c050c5 MC |
1027 | cons = agg->rx_agg_cmp_opaque; |
1028 | frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & | |
1029 | RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; | |
1030 | ||
1031 | cons_rx_buf = &rxr->rx_agg_ring[cons]; | |
89d0a06c MC |
1032 | skb_fill_page_desc(skb, i, cons_rx_buf->page, |
1033 | cons_rx_buf->offset, frag_len); | |
c0c050c5 MC |
1034 | __clear_bit(cons, rxr->rx_agg_bmap); |
1035 | ||
1036 | /* It is possible for bnxt_alloc_rx_page() to allocate | |
1037 | * a sw_prod index that equals the cons index, so we | |
1038 | * need to clear the cons entry now. | |
1039 | */ | |
11cd119d | 1040 | mapping = cons_rx_buf->mapping; |
c0c050c5 MC |
1041 | page = cons_rx_buf->page; |
1042 | cons_rx_buf->page = NULL; | |
1043 | ||
1044 | if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { | |
1045 | struct skb_shared_info *shinfo; | |
1046 | unsigned int nr_frags; | |
1047 | ||
1048 | shinfo = skb_shinfo(skb); | |
1049 | nr_frags = --shinfo->nr_frags; | |
1050 | __skb_frag_set_page(&shinfo->frags[nr_frags], NULL); | |
1051 | ||
1052 | dev_kfree_skb(skb); | |
1053 | ||
1054 | cons_rx_buf->page = page; | |
1055 | ||
1056 | /* Update prod since possibly some pages have been | |
1057 | * allocated already. | |
1058 | */ | |
1059 | rxr->rx_agg_prod = prod; | |
4a228a3a | 1060 | bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa); |
c0c050c5 MC |
1061 | return NULL; |
1062 | } | |
1063 | ||
c519fe9a SN |
1064 | dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE, |
1065 | PCI_DMA_FROMDEVICE, | |
1066 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
1067 | |
1068 | skb->data_len += frag_len; | |
1069 | skb->len += frag_len; | |
1070 | skb->truesize += PAGE_SIZE; | |
1071 | ||
1072 | prod = NEXT_RX_AGG(prod); | |
c0c050c5 MC |
1073 | } |
1074 | rxr->rx_agg_prod = prod; | |
1075 | return skb; | |
1076 | } | |
1077 | ||
1078 | static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, | |
1079 | u8 agg_bufs, u32 *raw_cons) | |
1080 | { | |
1081 | u16 last; | |
1082 | struct rx_agg_cmp *agg; | |
1083 | ||
1084 | *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); | |
1085 | last = RING_CMP(*raw_cons); | |
1086 | agg = (struct rx_agg_cmp *) | |
1087 | &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; | |
1088 | return RX_AGG_CMP_VALID(agg, *raw_cons); | |
1089 | } | |
1090 | ||
1091 | static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, | |
1092 | unsigned int len, | |
1093 | dma_addr_t mapping) | |
1094 | { | |
1095 | struct bnxt *bp = bnapi->bp; | |
1096 | struct pci_dev *pdev = bp->pdev; | |
1097 | struct sk_buff *skb; | |
1098 | ||
1099 | skb = napi_alloc_skb(&bnapi->napi, len); | |
1100 | if (!skb) | |
1101 | return NULL; | |
1102 | ||
745fc05c MC |
1103 | dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh, |
1104 | bp->rx_dir); | |
c0c050c5 | 1105 | |
6bb19474 MC |
1106 | memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN, |
1107 | len + NET_IP_ALIGN); | |
c0c050c5 | 1108 | |
745fc05c MC |
1109 | dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh, |
1110 | bp->rx_dir); | |
c0c050c5 MC |
1111 | |
1112 | skb_put(skb, len); | |
1113 | return skb; | |
1114 | } | |
1115 | ||
e44758b7 | 1116 | static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, |
fa7e2812 MC |
1117 | u32 *raw_cons, void *cmp) |
1118 | { | |
fa7e2812 MC |
1119 | struct rx_cmp *rxcmp = cmp; |
1120 | u32 tmp_raw_cons = *raw_cons; | |
1121 | u8 cmp_type, agg_bufs = 0; | |
1122 | ||
1123 | cmp_type = RX_CMP_TYPE(rxcmp); | |
1124 | ||
1125 | if (cmp_type == CMP_TYPE_RX_L2_CMP) { | |
1126 | agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & | |
1127 | RX_CMP_AGG_BUFS) >> | |
1128 | RX_CMP_AGG_BUFS_SHIFT; | |
1129 | } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { | |
1130 | struct rx_tpa_end_cmp *tpa_end = cmp; | |
1131 | ||
bfcd8d79 MC |
1132 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
1133 | return 0; | |
1134 | ||
4a228a3a | 1135 | agg_bufs = TPA_END_AGG_BUFS(tpa_end); |
fa7e2812 MC |
1136 | } |
1137 | ||
1138 | if (agg_bufs) { | |
1139 | if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) | |
1140 | return -EBUSY; | |
1141 | } | |
1142 | *raw_cons = tmp_raw_cons; | |
1143 | return 0; | |
1144 | } | |
1145 | ||
230d1f0d MC |
1146 | static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay) |
1147 | { | |
1148 | if (BNXT_PF(bp)) | |
1149 | queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay); | |
1150 | else | |
1151 | schedule_delayed_work(&bp->fw_reset_task, delay); | |
1152 | } | |
1153 | ||
c213eae8 MC |
1154 | static void bnxt_queue_sp_work(struct bnxt *bp) |
1155 | { | |
1156 | if (BNXT_PF(bp)) | |
1157 | queue_work(bnxt_pf_wq, &bp->sp_task); | |
1158 | else | |
1159 | schedule_work(&bp->sp_task); | |
1160 | } | |
1161 | ||
1162 | static void bnxt_cancel_sp_work(struct bnxt *bp) | |
1163 | { | |
1164 | if (BNXT_PF(bp)) | |
1165 | flush_workqueue(bnxt_pf_wq); | |
1166 | else | |
1167 | cancel_work_sync(&bp->sp_task); | |
1168 | } | |
1169 | ||
fa7e2812 MC |
1170 | static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) |
1171 | { | |
1172 | if (!rxr->bnapi->in_reset) { | |
1173 | rxr->bnapi->in_reset = true; | |
1174 | set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); | |
c213eae8 | 1175 | bnxt_queue_sp_work(bp); |
fa7e2812 MC |
1176 | } |
1177 | rxr->rx_next_cons = 0xffff; | |
1178 | } | |
1179 | ||
ec4d8e7c MC |
1180 | static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) |
1181 | { | |
1182 | struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; | |
1183 | u16 idx = agg_id & MAX_TPA_P5_MASK; | |
1184 | ||
1185 | if (test_bit(idx, map->agg_idx_bmap)) | |
1186 | idx = find_first_zero_bit(map->agg_idx_bmap, | |
1187 | BNXT_AGG_IDX_BMAP_SIZE); | |
1188 | __set_bit(idx, map->agg_idx_bmap); | |
1189 | map->agg_id_tbl[agg_id] = idx; | |
1190 | return idx; | |
1191 | } | |
1192 | ||
1193 | static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) | |
1194 | { | |
1195 | struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; | |
1196 | ||
1197 | __clear_bit(idx, map->agg_idx_bmap); | |
1198 | } | |
1199 | ||
1200 | static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) | |
1201 | { | |
1202 | struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; | |
1203 | ||
1204 | return map->agg_id_tbl[agg_id]; | |
1205 | } | |
1206 | ||
c0c050c5 MC |
1207 | static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, |
1208 | struct rx_tpa_start_cmp *tpa_start, | |
1209 | struct rx_tpa_start_cmp_ext *tpa_start1) | |
1210 | { | |
c0c050c5 | 1211 | struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; |
bfcd8d79 MC |
1212 | struct bnxt_tpa_info *tpa_info; |
1213 | u16 cons, prod, agg_id; | |
c0c050c5 MC |
1214 | struct rx_bd *prod_bd; |
1215 | dma_addr_t mapping; | |
1216 | ||
ec4d8e7c | 1217 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
bfcd8d79 | 1218 | agg_id = TPA_START_AGG_ID_P5(tpa_start); |
ec4d8e7c MC |
1219 | agg_id = bnxt_alloc_agg_idx(rxr, agg_id); |
1220 | } else { | |
bfcd8d79 | 1221 | agg_id = TPA_START_AGG_ID(tpa_start); |
ec4d8e7c | 1222 | } |
c0c050c5 MC |
1223 | cons = tpa_start->rx_tpa_start_cmp_opaque; |
1224 | prod = rxr->rx_prod; | |
1225 | cons_rx_buf = &rxr->rx_buf_ring[cons]; | |
1226 | prod_rx_buf = &rxr->rx_buf_ring[prod]; | |
1227 | tpa_info = &rxr->rx_tpa[agg_id]; | |
1228 | ||
bfcd8d79 MC |
1229 | if (unlikely(cons != rxr->rx_next_cons || |
1230 | TPA_START_ERROR(tpa_start))) { | |
1231 | netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n", | |
1232 | cons, rxr->rx_next_cons, | |
1233 | TPA_START_ERROR_CODE(tpa_start1)); | |
fa7e2812 MC |
1234 | bnxt_sched_reset(bp, rxr); |
1235 | return; | |
1236 | } | |
ee5c7fb3 SP |
1237 | /* Store cfa_code in tpa_info to use in tpa_end |
1238 | * completion processing. | |
1239 | */ | |
1240 | tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1); | |
c0c050c5 | 1241 | prod_rx_buf->data = tpa_info->data; |
6bb19474 | 1242 | prod_rx_buf->data_ptr = tpa_info->data_ptr; |
c0c050c5 MC |
1243 | |
1244 | mapping = tpa_info->mapping; | |
11cd119d | 1245 | prod_rx_buf->mapping = mapping; |
c0c050c5 MC |
1246 | |
1247 | prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
1248 | ||
1249 | prod_bd->rx_bd_haddr = cpu_to_le64(mapping); | |
1250 | ||
1251 | tpa_info->data = cons_rx_buf->data; | |
6bb19474 | 1252 | tpa_info->data_ptr = cons_rx_buf->data_ptr; |
c0c050c5 | 1253 | cons_rx_buf->data = NULL; |
11cd119d | 1254 | tpa_info->mapping = cons_rx_buf->mapping; |
c0c050c5 MC |
1255 | |
1256 | tpa_info->len = | |
1257 | le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> | |
1258 | RX_TPA_START_CMP_LEN_SHIFT; | |
1259 | if (likely(TPA_START_HASH_VALID(tpa_start))) { | |
1260 | u32 hash_type = TPA_START_HASH_TYPE(tpa_start); | |
1261 | ||
1262 | tpa_info->hash_type = PKT_HASH_TYPE_L4; | |
1263 | tpa_info->gso_type = SKB_GSO_TCPV4; | |
1264 | /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ | |
50f011b6 | 1265 | if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1)) |
c0c050c5 MC |
1266 | tpa_info->gso_type = SKB_GSO_TCPV6; |
1267 | tpa_info->rss_hash = | |
1268 | le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); | |
1269 | } else { | |
1270 | tpa_info->hash_type = PKT_HASH_TYPE_NONE; | |
1271 | tpa_info->gso_type = 0; | |
1272 | if (netif_msg_rx_err(bp)) | |
1273 | netdev_warn(bp->dev, "TPA packet without valid hash\n"); | |
1274 | } | |
1275 | tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); | |
1276 | tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); | |
94758f8d | 1277 | tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info); |
bfcd8d79 | 1278 | tpa_info->agg_count = 0; |
c0c050c5 MC |
1279 | |
1280 | rxr->rx_prod = NEXT_RX(prod); | |
1281 | cons = NEXT_RX(cons); | |
376a5b86 | 1282 | rxr->rx_next_cons = NEXT_RX(cons); |
c0c050c5 MC |
1283 | cons_rx_buf = &rxr->rx_buf_ring[cons]; |
1284 | ||
1285 | bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); | |
1286 | rxr->rx_prod = NEXT_RX(rxr->rx_prod); | |
1287 | cons_rx_buf->data = NULL; | |
1288 | } | |
1289 | ||
4a228a3a | 1290 | static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs) |
c0c050c5 MC |
1291 | { |
1292 | if (agg_bufs) | |
4a228a3a | 1293 | bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true); |
c0c050c5 MC |
1294 | } |
1295 | ||
bee5a188 MC |
1296 | #ifdef CONFIG_INET |
1297 | static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto) | |
1298 | { | |
1299 | struct udphdr *uh = NULL; | |
1300 | ||
1301 | if (ip_proto == htons(ETH_P_IP)) { | |
1302 | struct iphdr *iph = (struct iphdr *)skb->data; | |
1303 | ||
1304 | if (iph->protocol == IPPROTO_UDP) | |
1305 | uh = (struct udphdr *)(iph + 1); | |
1306 | } else { | |
1307 | struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; | |
1308 | ||
1309 | if (iph->nexthdr == IPPROTO_UDP) | |
1310 | uh = (struct udphdr *)(iph + 1); | |
1311 | } | |
1312 | if (uh) { | |
1313 | if (uh->check) | |
1314 | skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM; | |
1315 | else | |
1316 | skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; | |
1317 | } | |
1318 | } | |
1319 | #endif | |
1320 | ||
94758f8d MC |
1321 | static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info, |
1322 | int payload_off, int tcp_ts, | |
1323 | struct sk_buff *skb) | |
1324 | { | |
1325 | #ifdef CONFIG_INET | |
1326 | struct tcphdr *th; | |
1327 | int len, nw_off; | |
1328 | u16 outer_ip_off, inner_ip_off, inner_mac_off; | |
1329 | u32 hdr_info = tpa_info->hdr_info; | |
1330 | bool loopback = false; | |
1331 | ||
1332 | inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); | |
1333 | inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); | |
1334 | outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); | |
1335 | ||
1336 | /* If the packet is an internal loopback packet, the offsets will | |
1337 | * have an extra 4 bytes. | |
1338 | */ | |
1339 | if (inner_mac_off == 4) { | |
1340 | loopback = true; | |
1341 | } else if (inner_mac_off > 4) { | |
1342 | __be16 proto = *((__be16 *)(skb->data + inner_ip_off - | |
1343 | ETH_HLEN - 2)); | |
1344 | ||
1345 | /* We only support inner iPv4/ipv6. If we don't see the | |
1346 | * correct protocol ID, it must be a loopback packet where | |
1347 | * the offsets are off by 4. | |
1348 | */ | |
09a7636a | 1349 | if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6)) |
94758f8d MC |
1350 | loopback = true; |
1351 | } | |
1352 | if (loopback) { | |
1353 | /* internal loopback packet, subtract all offsets by 4 */ | |
1354 | inner_ip_off -= 4; | |
1355 | inner_mac_off -= 4; | |
1356 | outer_ip_off -= 4; | |
1357 | } | |
1358 | ||
1359 | nw_off = inner_ip_off - ETH_HLEN; | |
1360 | skb_set_network_header(skb, nw_off); | |
1361 | if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) { | |
1362 | struct ipv6hdr *iph = ipv6_hdr(skb); | |
1363 | ||
1364 | skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); | |
1365 | len = skb->len - skb_transport_offset(skb); | |
1366 | th = tcp_hdr(skb); | |
1367 | th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); | |
1368 | } else { | |
1369 | struct iphdr *iph = ip_hdr(skb); | |
1370 | ||
1371 | skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); | |
1372 | len = skb->len - skb_transport_offset(skb); | |
1373 | th = tcp_hdr(skb); | |
1374 | th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); | |
1375 | } | |
1376 | ||
1377 | if (inner_mac_off) { /* tunnel */ | |
94758f8d MC |
1378 | __be16 proto = *((__be16 *)(skb->data + outer_ip_off - |
1379 | ETH_HLEN - 2)); | |
1380 | ||
bee5a188 | 1381 | bnxt_gro_tunnel(skb, proto); |
94758f8d MC |
1382 | } |
1383 | #endif | |
1384 | return skb; | |
1385 | } | |
1386 | ||
67912c36 MC |
1387 | static struct sk_buff *bnxt_gro_func_5750x(struct bnxt_tpa_info *tpa_info, |
1388 | int payload_off, int tcp_ts, | |
1389 | struct sk_buff *skb) | |
1390 | { | |
1391 | #ifdef CONFIG_INET | |
1392 | u16 outer_ip_off, inner_ip_off, inner_mac_off; | |
1393 | u32 hdr_info = tpa_info->hdr_info; | |
1394 | int iphdr_len, nw_off; | |
1395 | ||
1396 | inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); | |
1397 | inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); | |
1398 | outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); | |
1399 | ||
1400 | nw_off = inner_ip_off - ETH_HLEN; | |
1401 | skb_set_network_header(skb, nw_off); | |
1402 | iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ? | |
1403 | sizeof(struct ipv6hdr) : sizeof(struct iphdr); | |
1404 | skb_set_transport_header(skb, nw_off + iphdr_len); | |
1405 | ||
1406 | if (inner_mac_off) { /* tunnel */ | |
1407 | __be16 proto = *((__be16 *)(skb->data + outer_ip_off - | |
1408 | ETH_HLEN - 2)); | |
1409 | ||
1410 | bnxt_gro_tunnel(skb, proto); | |
1411 | } | |
1412 | #endif | |
1413 | return skb; | |
1414 | } | |
1415 | ||
c0c050c5 MC |
1416 | #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) |
1417 | #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) | |
1418 | ||
309369c9 MC |
1419 | static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info, |
1420 | int payload_off, int tcp_ts, | |
c0c050c5 MC |
1421 | struct sk_buff *skb) |
1422 | { | |
d1611c3a | 1423 | #ifdef CONFIG_INET |
c0c050c5 | 1424 | struct tcphdr *th; |
719ca811 | 1425 | int len, nw_off, tcp_opt_len = 0; |
27e24189 | 1426 | |
309369c9 | 1427 | if (tcp_ts) |
c0c050c5 MC |
1428 | tcp_opt_len = 12; |
1429 | ||
c0c050c5 MC |
1430 | if (tpa_info->gso_type == SKB_GSO_TCPV4) { |
1431 | struct iphdr *iph; | |
1432 | ||
1433 | nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - | |
1434 | ETH_HLEN; | |
1435 | skb_set_network_header(skb, nw_off); | |
1436 | iph = ip_hdr(skb); | |
1437 | skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); | |
1438 | len = skb->len - skb_transport_offset(skb); | |
1439 | th = tcp_hdr(skb); | |
1440 | th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); | |
1441 | } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { | |
1442 | struct ipv6hdr *iph; | |
1443 | ||
1444 | nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - | |
1445 | ETH_HLEN; | |
1446 | skb_set_network_header(skb, nw_off); | |
1447 | iph = ipv6_hdr(skb); | |
1448 | skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); | |
1449 | len = skb->len - skb_transport_offset(skb); | |
1450 | th = tcp_hdr(skb); | |
1451 | th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); | |
1452 | } else { | |
1453 | dev_kfree_skb_any(skb); | |
1454 | return NULL; | |
1455 | } | |
c0c050c5 | 1456 | |
bee5a188 MC |
1457 | if (nw_off) /* tunnel */ |
1458 | bnxt_gro_tunnel(skb, skb->protocol); | |
c0c050c5 MC |
1459 | #endif |
1460 | return skb; | |
1461 | } | |
1462 | ||
309369c9 MC |
1463 | static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp, |
1464 | struct bnxt_tpa_info *tpa_info, | |
1465 | struct rx_tpa_end_cmp *tpa_end, | |
1466 | struct rx_tpa_end_cmp_ext *tpa_end1, | |
1467 | struct sk_buff *skb) | |
1468 | { | |
1469 | #ifdef CONFIG_INET | |
1470 | int payload_off; | |
1471 | u16 segs; | |
1472 | ||
1473 | segs = TPA_END_TPA_SEGS(tpa_end); | |
1474 | if (segs == 1) | |
1475 | return skb; | |
1476 | ||
1477 | NAPI_GRO_CB(skb)->count = segs; | |
1478 | skb_shinfo(skb)->gso_size = | |
1479 | le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); | |
1480 | skb_shinfo(skb)->gso_type = tpa_info->gso_type; | |
bfcd8d79 MC |
1481 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
1482 | payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1); | |
1483 | else | |
1484 | payload_off = TPA_END_PAYLOAD_OFF(tpa_end); | |
309369c9 | 1485 | skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb); |
5910906c MC |
1486 | if (likely(skb)) |
1487 | tcp_gro_complete(skb); | |
309369c9 MC |
1488 | #endif |
1489 | return skb; | |
1490 | } | |
1491 | ||
ee5c7fb3 SP |
1492 | /* Given the cfa_code of a received packet determine which |
1493 | * netdev (vf-rep or PF) the packet is destined to. | |
1494 | */ | |
1495 | static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code) | |
1496 | { | |
1497 | struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code); | |
1498 | ||
1499 | /* if vf-rep dev is NULL, the must belongs to the PF */ | |
1500 | return dev ? dev : bp->dev; | |
1501 | } | |
1502 | ||
c0c050c5 | 1503 | static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, |
e44758b7 | 1504 | struct bnxt_cp_ring_info *cpr, |
c0c050c5 MC |
1505 | u32 *raw_cons, |
1506 | struct rx_tpa_end_cmp *tpa_end, | |
1507 | struct rx_tpa_end_cmp_ext *tpa_end1, | |
4e5dbbda | 1508 | u8 *event) |
c0c050c5 | 1509 | { |
e44758b7 | 1510 | struct bnxt_napi *bnapi = cpr->bnapi; |
b6ab4b01 | 1511 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
6bb19474 | 1512 | u8 *data_ptr, agg_bufs; |
c0c050c5 MC |
1513 | unsigned int len; |
1514 | struct bnxt_tpa_info *tpa_info; | |
1515 | dma_addr_t mapping; | |
1516 | struct sk_buff *skb; | |
bfcd8d79 | 1517 | u16 idx = 0, agg_id; |
6bb19474 | 1518 | void *data; |
bfcd8d79 | 1519 | bool gro; |
c0c050c5 | 1520 | |
fa7e2812 | 1521 | if (unlikely(bnapi->in_reset)) { |
e44758b7 | 1522 | int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end); |
fa7e2812 MC |
1523 | |
1524 | if (rc < 0) | |
1525 | return ERR_PTR(-EBUSY); | |
1526 | return NULL; | |
1527 | } | |
1528 | ||
bfcd8d79 MC |
1529 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
1530 | agg_id = TPA_END_AGG_ID_P5(tpa_end); | |
ec4d8e7c | 1531 | agg_id = bnxt_lookup_agg_idx(rxr, agg_id); |
bfcd8d79 MC |
1532 | agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1); |
1533 | tpa_info = &rxr->rx_tpa[agg_id]; | |
1534 | if (unlikely(agg_bufs != tpa_info->agg_count)) { | |
1535 | netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n", | |
1536 | agg_bufs, tpa_info->agg_count); | |
1537 | agg_bufs = tpa_info->agg_count; | |
1538 | } | |
1539 | tpa_info->agg_count = 0; | |
1540 | *event |= BNXT_AGG_EVENT; | |
ec4d8e7c | 1541 | bnxt_free_agg_idx(rxr, agg_id); |
bfcd8d79 MC |
1542 | idx = agg_id; |
1543 | gro = !!(bp->flags & BNXT_FLAG_GRO); | |
1544 | } else { | |
1545 | agg_id = TPA_END_AGG_ID(tpa_end); | |
1546 | agg_bufs = TPA_END_AGG_BUFS(tpa_end); | |
1547 | tpa_info = &rxr->rx_tpa[agg_id]; | |
1548 | idx = RING_CMP(*raw_cons); | |
1549 | if (agg_bufs) { | |
1550 | if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) | |
1551 | return ERR_PTR(-EBUSY); | |
1552 | ||
1553 | *event |= BNXT_AGG_EVENT; | |
1554 | idx = NEXT_CMP(idx); | |
1555 | } | |
1556 | gro = !!TPA_END_GRO(tpa_end); | |
1557 | } | |
c0c050c5 | 1558 | data = tpa_info->data; |
6bb19474 MC |
1559 | data_ptr = tpa_info->data_ptr; |
1560 | prefetch(data_ptr); | |
c0c050c5 MC |
1561 | len = tpa_info->len; |
1562 | mapping = tpa_info->mapping; | |
1563 | ||
69c149e2 | 1564 | if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) { |
4a228a3a | 1565 | bnxt_abort_tpa(cpr, idx, agg_bufs); |
69c149e2 MC |
1566 | if (agg_bufs > MAX_SKB_FRAGS) |
1567 | netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", | |
1568 | agg_bufs, (int)MAX_SKB_FRAGS); | |
c0c050c5 MC |
1569 | return NULL; |
1570 | } | |
1571 | ||
1572 | if (len <= bp->rx_copy_thresh) { | |
6bb19474 | 1573 | skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping); |
c0c050c5 | 1574 | if (!skb) { |
4a228a3a | 1575 | bnxt_abort_tpa(cpr, idx, agg_bufs); |
c0c050c5 MC |
1576 | return NULL; |
1577 | } | |
1578 | } else { | |
1579 | u8 *new_data; | |
1580 | dma_addr_t new_mapping; | |
1581 | ||
1582 | new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC); | |
1583 | if (!new_data) { | |
4a228a3a | 1584 | bnxt_abort_tpa(cpr, idx, agg_bufs); |
c0c050c5 MC |
1585 | return NULL; |
1586 | } | |
1587 | ||
1588 | tpa_info->data = new_data; | |
b3dba77c | 1589 | tpa_info->data_ptr = new_data + bp->rx_offset; |
c0c050c5 MC |
1590 | tpa_info->mapping = new_mapping; |
1591 | ||
1592 | skb = build_skb(data, 0); | |
c519fe9a SN |
1593 | dma_unmap_single_attrs(&bp->pdev->dev, mapping, |
1594 | bp->rx_buf_use_size, bp->rx_dir, | |
1595 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
1596 | |
1597 | if (!skb) { | |
1598 | kfree(data); | |
4a228a3a | 1599 | bnxt_abort_tpa(cpr, idx, agg_bufs); |
c0c050c5 MC |
1600 | return NULL; |
1601 | } | |
b3dba77c | 1602 | skb_reserve(skb, bp->rx_offset); |
c0c050c5 MC |
1603 | skb_put(skb, len); |
1604 | } | |
1605 | ||
1606 | if (agg_bufs) { | |
4a228a3a | 1607 | skb = bnxt_rx_pages(bp, cpr, skb, idx, agg_bufs, true); |
c0c050c5 MC |
1608 | if (!skb) { |
1609 | /* Page reuse already handled by bnxt_rx_pages(). */ | |
1610 | return NULL; | |
1611 | } | |
1612 | } | |
ee5c7fb3 SP |
1613 | |
1614 | skb->protocol = | |
1615 | eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code)); | |
c0c050c5 MC |
1616 | |
1617 | if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) | |
1618 | skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); | |
1619 | ||
8852ddb4 MC |
1620 | if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) && |
1621 | (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { | |
c0c050c5 MC |
1622 | u16 vlan_proto = tpa_info->metadata >> |
1623 | RX_CMP_FLAGS2_METADATA_TPID_SFT; | |
ed7bc602 | 1624 | u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK; |
c0c050c5 | 1625 | |
8852ddb4 | 1626 | __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); |
c0c050c5 MC |
1627 | } |
1628 | ||
1629 | skb_checksum_none_assert(skb); | |
1630 | if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { | |
1631 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1632 | skb->csum_level = | |
1633 | (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; | |
1634 | } | |
1635 | ||
bfcd8d79 | 1636 | if (gro) |
309369c9 | 1637 | skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb); |
c0c050c5 MC |
1638 | |
1639 | return skb; | |
1640 | } | |
1641 | ||
8fe88ce7 MC |
1642 | static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, |
1643 | struct rx_agg_cmp *rx_agg) | |
1644 | { | |
1645 | u16 agg_id = TPA_AGG_AGG_ID(rx_agg); | |
1646 | struct bnxt_tpa_info *tpa_info; | |
1647 | ||
ec4d8e7c | 1648 | agg_id = bnxt_lookup_agg_idx(rxr, agg_id); |
8fe88ce7 MC |
1649 | tpa_info = &rxr->rx_tpa[agg_id]; |
1650 | BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS); | |
1651 | tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg; | |
1652 | } | |
1653 | ||
ee5c7fb3 SP |
1654 | static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi, |
1655 | struct sk_buff *skb) | |
1656 | { | |
1657 | if (skb->dev != bp->dev) { | |
1658 | /* this packet belongs to a vf-rep */ | |
1659 | bnxt_vf_rep_rx(bp, skb); | |
1660 | return; | |
1661 | } | |
1662 | skb_record_rx_queue(skb, bnapi->index); | |
1663 | napi_gro_receive(&bnapi->napi, skb); | |
1664 | } | |
1665 | ||
c0c050c5 MC |
1666 | /* returns the following: |
1667 | * 1 - 1 packet successfully received | |
1668 | * 0 - successful TPA_START, packet not completed yet | |
1669 | * -EBUSY - completion ring does not have all the agg buffers yet | |
1670 | * -ENOMEM - packet aborted due to out of memory | |
1671 | * -EIO - packet aborted due to hw error indicated in BD | |
1672 | */ | |
e44758b7 MC |
1673 | static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, |
1674 | u32 *raw_cons, u8 *event) | |
c0c050c5 | 1675 | { |
e44758b7 | 1676 | struct bnxt_napi *bnapi = cpr->bnapi; |
b6ab4b01 | 1677 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
c0c050c5 MC |
1678 | struct net_device *dev = bp->dev; |
1679 | struct rx_cmp *rxcmp; | |
1680 | struct rx_cmp_ext *rxcmp1; | |
1681 | u32 tmp_raw_cons = *raw_cons; | |
ee5c7fb3 | 1682 | u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons); |
c0c050c5 MC |
1683 | struct bnxt_sw_rx_bd *rx_buf; |
1684 | unsigned int len; | |
6bb19474 | 1685 | u8 *data_ptr, agg_bufs, cmp_type; |
c0c050c5 MC |
1686 | dma_addr_t dma_addr; |
1687 | struct sk_buff *skb; | |
6bb19474 | 1688 | void *data; |
c0c050c5 | 1689 | int rc = 0; |
c61fb99c | 1690 | u32 misc; |
c0c050c5 MC |
1691 | |
1692 | rxcmp = (struct rx_cmp *) | |
1693 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
1694 | ||
8fe88ce7 MC |
1695 | cmp_type = RX_CMP_TYPE(rxcmp); |
1696 | ||
1697 | if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) { | |
1698 | bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp); | |
1699 | goto next_rx_no_prod_no_len; | |
1700 | } | |
1701 | ||
c0c050c5 MC |
1702 | tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); |
1703 | cp_cons = RING_CMP(tmp_raw_cons); | |
1704 | rxcmp1 = (struct rx_cmp_ext *) | |
1705 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
1706 | ||
1707 | if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) | |
1708 | return -EBUSY; | |
1709 | ||
c0c050c5 MC |
1710 | prod = rxr->rx_prod; |
1711 | ||
1712 | if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { | |
1713 | bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, | |
1714 | (struct rx_tpa_start_cmp_ext *)rxcmp1); | |
1715 | ||
4e5dbbda | 1716 | *event |= BNXT_RX_EVENT; |
e7e70fa6 | 1717 | goto next_rx_no_prod_no_len; |
c0c050c5 MC |
1718 | |
1719 | } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { | |
e44758b7 | 1720 | skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons, |
c0c050c5 | 1721 | (struct rx_tpa_end_cmp *)rxcmp, |
4e5dbbda | 1722 | (struct rx_tpa_end_cmp_ext *)rxcmp1, event); |
c0c050c5 | 1723 | |
1fac4b2f | 1724 | if (IS_ERR(skb)) |
c0c050c5 MC |
1725 | return -EBUSY; |
1726 | ||
1727 | rc = -ENOMEM; | |
1728 | if (likely(skb)) { | |
ee5c7fb3 | 1729 | bnxt_deliver_skb(bp, bnapi, skb); |
c0c050c5 MC |
1730 | rc = 1; |
1731 | } | |
4e5dbbda | 1732 | *event |= BNXT_RX_EVENT; |
e7e70fa6 | 1733 | goto next_rx_no_prod_no_len; |
c0c050c5 MC |
1734 | } |
1735 | ||
1736 | cons = rxcmp->rx_cmp_opaque; | |
fa7e2812 | 1737 | if (unlikely(cons != rxr->rx_next_cons)) { |
e44758b7 | 1738 | int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp); |
fa7e2812 | 1739 | |
a1b0e4e6 MC |
1740 | netdev_warn(bp->dev, "RX cons %x != expected cons %x\n", |
1741 | cons, rxr->rx_next_cons); | |
fa7e2812 MC |
1742 | bnxt_sched_reset(bp, rxr); |
1743 | return rc1; | |
1744 | } | |
a1b0e4e6 MC |
1745 | rx_buf = &rxr->rx_buf_ring[cons]; |
1746 | data = rx_buf->data; | |
1747 | data_ptr = rx_buf->data_ptr; | |
6bb19474 | 1748 | prefetch(data_ptr); |
c0c050c5 | 1749 | |
c61fb99c MC |
1750 | misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1); |
1751 | agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT; | |
c0c050c5 MC |
1752 | |
1753 | if (agg_bufs) { | |
1754 | if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) | |
1755 | return -EBUSY; | |
1756 | ||
1757 | cp_cons = NEXT_CMP(cp_cons); | |
4e5dbbda | 1758 | *event |= BNXT_AGG_EVENT; |
c0c050c5 | 1759 | } |
4e5dbbda | 1760 | *event |= BNXT_RX_EVENT; |
c0c050c5 MC |
1761 | |
1762 | rx_buf->data = NULL; | |
1763 | if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { | |
8e44e96c MC |
1764 | u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2); |
1765 | ||
c0c050c5 MC |
1766 | bnxt_reuse_rx_data(rxr, cons, data); |
1767 | if (agg_bufs) | |
4a228a3a MC |
1768 | bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs, |
1769 | false); | |
c0c050c5 MC |
1770 | |
1771 | rc = -EIO; | |
8e44e96c | 1772 | if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) { |
19b3751f MC |
1773 | bnapi->cp_ring.rx_buf_errors++; |
1774 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) { | |
1775 | netdev_warn(bp->dev, "RX buffer error %x\n", | |
1776 | rx_err); | |
1777 | bnxt_sched_reset(bp, rxr); | |
1778 | } | |
8e44e96c | 1779 | } |
0b397b17 | 1780 | goto next_rx_no_len; |
c0c050c5 MC |
1781 | } |
1782 | ||
1783 | len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; | |
11cd119d | 1784 | dma_addr = rx_buf->mapping; |
c0c050c5 | 1785 | |
c6d30e83 MC |
1786 | if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) { |
1787 | rc = 1; | |
1788 | goto next_rx; | |
1789 | } | |
1790 | ||
c0c050c5 | 1791 | if (len <= bp->rx_copy_thresh) { |
6bb19474 | 1792 | skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr); |
c0c050c5 MC |
1793 | bnxt_reuse_rx_data(rxr, cons, data); |
1794 | if (!skb) { | |
296d5b54 | 1795 | if (agg_bufs) |
4a228a3a MC |
1796 | bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, |
1797 | agg_bufs, false); | |
c0c050c5 MC |
1798 | rc = -ENOMEM; |
1799 | goto next_rx; | |
1800 | } | |
1801 | } else { | |
c61fb99c MC |
1802 | u32 payload; |
1803 | ||
c6d30e83 MC |
1804 | if (rx_buf->data_ptr == data_ptr) |
1805 | payload = misc & RX_CMP_PAYLOAD_OFFSET; | |
1806 | else | |
1807 | payload = 0; | |
6bb19474 | 1808 | skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr, |
c61fb99c | 1809 | payload | len); |
c0c050c5 MC |
1810 | if (!skb) { |
1811 | rc = -ENOMEM; | |
1812 | goto next_rx; | |
1813 | } | |
1814 | } | |
1815 | ||
1816 | if (agg_bufs) { | |
4a228a3a | 1817 | skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs, false); |
c0c050c5 MC |
1818 | if (!skb) { |
1819 | rc = -ENOMEM; | |
1820 | goto next_rx; | |
1821 | } | |
1822 | } | |
1823 | ||
1824 | if (RX_CMP_HASH_VALID(rxcmp)) { | |
1825 | u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); | |
1826 | enum pkt_hash_types type = PKT_HASH_TYPE_L4; | |
1827 | ||
1828 | /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ | |
1829 | if (hash_type != 1 && hash_type != 3) | |
1830 | type = PKT_HASH_TYPE_L3; | |
1831 | skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); | |
1832 | } | |
1833 | ||
ee5c7fb3 SP |
1834 | cfa_code = RX_CMP_CFA_CODE(rxcmp1); |
1835 | skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code)); | |
c0c050c5 | 1836 | |
8852ddb4 MC |
1837 | if ((rxcmp1->rx_cmp_flags2 & |
1838 | cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) && | |
1839 | (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { | |
c0c050c5 | 1840 | u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); |
ed7bc602 | 1841 | u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK; |
c0c050c5 MC |
1842 | u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT; |
1843 | ||
8852ddb4 | 1844 | __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); |
c0c050c5 MC |
1845 | } |
1846 | ||
1847 | skb_checksum_none_assert(skb); | |
1848 | if (RX_CMP_L4_CS_OK(rxcmp1)) { | |
1849 | if (dev->features & NETIF_F_RXCSUM) { | |
1850 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1851 | skb->csum_level = RX_CMP_ENCAP(rxcmp1); | |
1852 | } | |
1853 | } else { | |
665e350d SB |
1854 | if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { |
1855 | if (dev->features & NETIF_F_RXCSUM) | |
d1981929 | 1856 | bnapi->cp_ring.rx_l4_csum_errors++; |
665e350d | 1857 | } |
c0c050c5 MC |
1858 | } |
1859 | ||
ee5c7fb3 | 1860 | bnxt_deliver_skb(bp, bnapi, skb); |
c0c050c5 MC |
1861 | rc = 1; |
1862 | ||
1863 | next_rx: | |
6a8788f2 AG |
1864 | cpr->rx_packets += 1; |
1865 | cpr->rx_bytes += len; | |
e7e70fa6 | 1866 | |
0b397b17 MC |
1867 | next_rx_no_len: |
1868 | rxr->rx_prod = NEXT_RX(prod); | |
1869 | rxr->rx_next_cons = NEXT_RX(cons); | |
1870 | ||
e7e70fa6 | 1871 | next_rx_no_prod_no_len: |
c0c050c5 MC |
1872 | *raw_cons = tmp_raw_cons; |
1873 | ||
1874 | return rc; | |
1875 | } | |
1876 | ||
2270bc5d MC |
1877 | /* In netpoll mode, if we are using a combined completion ring, we need to |
1878 | * discard the rx packets and recycle the buffers. | |
1879 | */ | |
e44758b7 MC |
1880 | static int bnxt_force_rx_discard(struct bnxt *bp, |
1881 | struct bnxt_cp_ring_info *cpr, | |
2270bc5d MC |
1882 | u32 *raw_cons, u8 *event) |
1883 | { | |
2270bc5d MC |
1884 | u32 tmp_raw_cons = *raw_cons; |
1885 | struct rx_cmp_ext *rxcmp1; | |
1886 | struct rx_cmp *rxcmp; | |
1887 | u16 cp_cons; | |
1888 | u8 cmp_type; | |
1889 | ||
1890 | cp_cons = RING_CMP(tmp_raw_cons); | |
1891 | rxcmp = (struct rx_cmp *) | |
1892 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
1893 | ||
1894 | tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); | |
1895 | cp_cons = RING_CMP(tmp_raw_cons); | |
1896 | rxcmp1 = (struct rx_cmp_ext *) | |
1897 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
1898 | ||
1899 | if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) | |
1900 | return -EBUSY; | |
1901 | ||
1902 | cmp_type = RX_CMP_TYPE(rxcmp); | |
1903 | if (cmp_type == CMP_TYPE_RX_L2_CMP) { | |
1904 | rxcmp1->rx_cmp_cfa_code_errors_v2 |= | |
1905 | cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); | |
1906 | } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { | |
1907 | struct rx_tpa_end_cmp_ext *tpa_end1; | |
1908 | ||
1909 | tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1; | |
1910 | tpa_end1->rx_tpa_end_cmp_errors_v2 |= | |
1911 | cpu_to_le32(RX_TPA_END_CMP_ERRORS); | |
1912 | } | |
e44758b7 | 1913 | return bnxt_rx_pkt(bp, cpr, raw_cons, event); |
2270bc5d MC |
1914 | } |
1915 | ||
7e914027 MC |
1916 | u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx) |
1917 | { | |
1918 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
1919 | u32 reg = fw_health->regs[reg_idx]; | |
1920 | u32 reg_type, reg_off, val = 0; | |
1921 | ||
1922 | reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); | |
1923 | reg_off = BNXT_FW_HEALTH_REG_OFF(reg); | |
1924 | switch (reg_type) { | |
1925 | case BNXT_FW_HEALTH_REG_TYPE_CFG: | |
1926 | pci_read_config_dword(bp->pdev, reg_off, &val); | |
1927 | break; | |
1928 | case BNXT_FW_HEALTH_REG_TYPE_GRC: | |
1929 | reg_off = fw_health->mapped_regs[reg_idx]; | |
1930 | /* fall through */ | |
1931 | case BNXT_FW_HEALTH_REG_TYPE_BAR0: | |
1932 | val = readl(bp->bar0 + reg_off); | |
1933 | break; | |
1934 | case BNXT_FW_HEALTH_REG_TYPE_BAR1: | |
1935 | val = readl(bp->bar1 + reg_off); | |
1936 | break; | |
1937 | } | |
1938 | if (reg_idx == BNXT_FW_RESET_INPROG_REG) | |
1939 | val &= fw_health->fw_reset_inprog_reg_mask; | |
1940 | return val; | |
1941 | } | |
1942 | ||
4bb13abf | 1943 | #define BNXT_GET_EVENT_PORT(data) \ |
87c374de MC |
1944 | ((data) & \ |
1945 | ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK) | |
4bb13abf | 1946 | |
c0c050c5 MC |
1947 | static int bnxt_async_event_process(struct bnxt *bp, |
1948 | struct hwrm_async_event_cmpl *cmpl) | |
1949 | { | |
1950 | u16 event_id = le16_to_cpu(cmpl->event_id); | |
1951 | ||
1952 | /* TODO CHIMP_FW: Define event id's for link change, error etc */ | |
1953 | switch (event_id) { | |
87c374de | 1954 | case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: { |
8cbde117 MC |
1955 | u32 data1 = le32_to_cpu(cmpl->event_data1); |
1956 | struct bnxt_link_info *link_info = &bp->link_info; | |
1957 | ||
1958 | if (BNXT_VF(bp)) | |
1959 | goto async_event_process_exit; | |
a8168b6c MC |
1960 | |
1961 | /* print unsupported speed warning in forced speed mode only */ | |
1962 | if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) && | |
1963 | (data1 & 0x20000)) { | |
8cbde117 MC |
1964 | u16 fw_speed = link_info->force_link_speed; |
1965 | u32 speed = bnxt_fw_to_ethtool_speed(fw_speed); | |
1966 | ||
a8168b6c MC |
1967 | if (speed != SPEED_UNKNOWN) |
1968 | netdev_warn(bp->dev, "Link speed %d no longer supported\n", | |
1969 | speed); | |
8cbde117 | 1970 | } |
286ef9d6 | 1971 | set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event); |
8cbde117 | 1972 | } |
bc171e87 | 1973 | /* fall through */ |
b1613e78 MC |
1974 | case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE: |
1975 | case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE: | |
1976 | set_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, &bp->sp_event); | |
1977 | /* fall through */ | |
87c374de | 1978 | case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: |
c0c050c5 | 1979 | set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); |
19241368 | 1980 | break; |
87c374de | 1981 | case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: |
19241368 | 1982 | set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event); |
c0c050c5 | 1983 | break; |
87c374de | 1984 | case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: { |
4bb13abf MC |
1985 | u32 data1 = le32_to_cpu(cmpl->event_data1); |
1986 | u16 port_id = BNXT_GET_EVENT_PORT(data1); | |
1987 | ||
1988 | if (BNXT_VF(bp)) | |
1989 | break; | |
1990 | ||
1991 | if (bp->pf.port_id != port_id) | |
1992 | break; | |
1993 | ||
4bb13abf MC |
1994 | set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event); |
1995 | break; | |
1996 | } | |
87c374de | 1997 | case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: |
fc0f1929 MC |
1998 | if (BNXT_PF(bp)) |
1999 | goto async_event_process_exit; | |
2000 | set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event); | |
2001 | break; | |
acfb50e4 VV |
2002 | case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: { |
2003 | u32 data1 = le32_to_cpu(cmpl->event_data1); | |
2004 | ||
8280b38e VV |
2005 | if (!bp->fw_health) |
2006 | goto async_event_process_exit; | |
2007 | ||
2151fe08 MC |
2008 | bp->fw_reset_timestamp = jiffies; |
2009 | bp->fw_reset_min_dsecs = cmpl->timestamp_lo; | |
2010 | if (!bp->fw_reset_min_dsecs) | |
2011 | bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS; | |
2012 | bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi); | |
2013 | if (!bp->fw_reset_max_dsecs) | |
2014 | bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS; | |
acfb50e4 VV |
2015 | if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) { |
2016 | netdev_warn(bp->dev, "Firmware fatal reset event received\n"); | |
2017 | set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); | |
2018 | } else { | |
2019 | netdev_warn(bp->dev, "Firmware non-fatal reset event received, max wait time %d msec\n", | |
2020 | bp->fw_reset_max_dsecs * 100); | |
2021 | } | |
2151fe08 MC |
2022 | set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event); |
2023 | break; | |
acfb50e4 | 2024 | } |
7e914027 MC |
2025 | case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: { |
2026 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
2027 | u32 data1 = le32_to_cpu(cmpl->event_data1); | |
2028 | ||
2029 | if (!fw_health) | |
2030 | goto async_event_process_exit; | |
2031 | ||
2032 | fw_health->enabled = EVENT_DATA1_RECOVERY_ENABLED(data1); | |
2033 | fw_health->master = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1); | |
2034 | if (!fw_health->enabled) | |
2035 | break; | |
2036 | ||
2037 | if (netif_msg_drv(bp)) | |
2038 | netdev_info(bp->dev, "Error recovery info: error recovery[%d], master[%d], reset count[0x%x], health status: 0x%x\n", | |
2039 | fw_health->enabled, fw_health->master, | |
2040 | bnxt_fw_health_readl(bp, | |
2041 | BNXT_FW_RESET_CNT_REG), | |
2042 | bnxt_fw_health_readl(bp, | |
2043 | BNXT_FW_HEALTH_REG)); | |
2044 | fw_health->tmr_multiplier = | |
2045 | DIV_ROUND_UP(fw_health->polling_dsecs * HZ, | |
2046 | bp->current_interval * 10); | |
2047 | fw_health->tmr_counter = fw_health->tmr_multiplier; | |
2048 | fw_health->last_fw_heartbeat = | |
2049 | bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); | |
2050 | fw_health->last_fw_reset_cnt = | |
2051 | bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); | |
2052 | goto async_event_process_exit; | |
2053 | } | |
c0c050c5 | 2054 | default: |
19241368 | 2055 | goto async_event_process_exit; |
c0c050c5 | 2056 | } |
c213eae8 | 2057 | bnxt_queue_sp_work(bp); |
19241368 | 2058 | async_event_process_exit: |
a588e458 | 2059 | bnxt_ulp_async_events(bp, cmpl); |
c0c050c5 MC |
2060 | return 0; |
2061 | } | |
2062 | ||
2063 | static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) | |
2064 | { | |
2065 | u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; | |
2066 | struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; | |
2067 | struct hwrm_fwd_req_cmpl *fwd_req_cmpl = | |
2068 | (struct hwrm_fwd_req_cmpl *)txcmp; | |
2069 | ||
2070 | switch (cmpl_type) { | |
2071 | case CMPL_BASE_TYPE_HWRM_DONE: | |
2072 | seq_id = le16_to_cpu(h_cmpl->sequence_id); | |
2073 | if (seq_id == bp->hwrm_intr_seq_id) | |
fc718bb2 | 2074 | bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id; |
c0c050c5 MC |
2075 | else |
2076 | netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id); | |
2077 | break; | |
2078 | ||
2079 | case CMPL_BASE_TYPE_HWRM_FWD_REQ: | |
2080 | vf_id = le16_to_cpu(fwd_req_cmpl->source_id); | |
2081 | ||
2082 | if ((vf_id < bp->pf.first_vf_id) || | |
2083 | (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { | |
2084 | netdev_err(bp->dev, "Msg contains invalid VF id %x\n", | |
2085 | vf_id); | |
2086 | return -EINVAL; | |
2087 | } | |
2088 | ||
2089 | set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); | |
2090 | set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event); | |
c213eae8 | 2091 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
2092 | break; |
2093 | ||
2094 | case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: | |
2095 | bnxt_async_event_process(bp, | |
2096 | (struct hwrm_async_event_cmpl *)txcmp); | |
2097 | ||
2098 | default: | |
2099 | break; | |
2100 | } | |
2101 | ||
2102 | return 0; | |
2103 | } | |
2104 | ||
2105 | static irqreturn_t bnxt_msix(int irq, void *dev_instance) | |
2106 | { | |
2107 | struct bnxt_napi *bnapi = dev_instance; | |
2108 | struct bnxt *bp = bnapi->bp; | |
2109 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2110 | u32 cons = RING_CMP(cpr->cp_raw_cons); | |
2111 | ||
6a8788f2 | 2112 | cpr->event_ctr++; |
c0c050c5 MC |
2113 | prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); |
2114 | napi_schedule(&bnapi->napi); | |
2115 | return IRQ_HANDLED; | |
2116 | } | |
2117 | ||
2118 | static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) | |
2119 | { | |
2120 | u32 raw_cons = cpr->cp_raw_cons; | |
2121 | u16 cons = RING_CMP(raw_cons); | |
2122 | struct tx_cmp *txcmp; | |
2123 | ||
2124 | txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; | |
2125 | ||
2126 | return TX_CMP_VALID(txcmp, raw_cons); | |
2127 | } | |
2128 | ||
c0c050c5 MC |
2129 | static irqreturn_t bnxt_inta(int irq, void *dev_instance) |
2130 | { | |
2131 | struct bnxt_napi *bnapi = dev_instance; | |
2132 | struct bnxt *bp = bnapi->bp; | |
2133 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2134 | u32 cons = RING_CMP(cpr->cp_raw_cons); | |
2135 | u32 int_status; | |
2136 | ||
2137 | prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); | |
2138 | ||
2139 | if (!bnxt_has_work(bp, cpr)) { | |
11809490 | 2140 | int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); |
c0c050c5 MC |
2141 | /* return if erroneous interrupt */ |
2142 | if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) | |
2143 | return IRQ_NONE; | |
2144 | } | |
2145 | ||
2146 | /* disable ring IRQ */ | |
697197e5 | 2147 | BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell); |
c0c050c5 MC |
2148 | |
2149 | /* Return here if interrupt is shared and is disabled. */ | |
2150 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) | |
2151 | return IRQ_HANDLED; | |
2152 | ||
2153 | napi_schedule(&bnapi->napi); | |
2154 | return IRQ_HANDLED; | |
2155 | } | |
2156 | ||
3675b92f MC |
2157 | static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, |
2158 | int budget) | |
c0c050c5 | 2159 | { |
e44758b7 | 2160 | struct bnxt_napi *bnapi = cpr->bnapi; |
c0c050c5 MC |
2161 | u32 raw_cons = cpr->cp_raw_cons; |
2162 | u32 cons; | |
2163 | int tx_pkts = 0; | |
2164 | int rx_pkts = 0; | |
4e5dbbda | 2165 | u8 event = 0; |
c0c050c5 MC |
2166 | struct tx_cmp *txcmp; |
2167 | ||
0fcec985 | 2168 | cpr->has_more_work = 0; |
c0c050c5 MC |
2169 | while (1) { |
2170 | int rc; | |
2171 | ||
2172 | cons = RING_CMP(raw_cons); | |
2173 | txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; | |
2174 | ||
2175 | if (!TX_CMP_VALID(txcmp, raw_cons)) | |
2176 | break; | |
2177 | ||
67a95e20 MC |
2178 | /* The valid test of the entry must be done first before |
2179 | * reading any further. | |
2180 | */ | |
b67daab0 | 2181 | dma_rmb(); |
3675b92f | 2182 | cpr->had_work_done = 1; |
c0c050c5 MC |
2183 | if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { |
2184 | tx_pkts++; | |
2185 | /* return full budget so NAPI will complete. */ | |
73f21c65 | 2186 | if (unlikely(tx_pkts > bp->tx_wake_thresh)) { |
c0c050c5 | 2187 | rx_pkts = budget; |
73f21c65 | 2188 | raw_cons = NEXT_RAW_CMP(raw_cons); |
0fcec985 MC |
2189 | if (budget) |
2190 | cpr->has_more_work = 1; | |
73f21c65 MC |
2191 | break; |
2192 | } | |
c0c050c5 | 2193 | } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { |
2270bc5d | 2194 | if (likely(budget)) |
e44758b7 | 2195 | rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); |
2270bc5d | 2196 | else |
e44758b7 | 2197 | rc = bnxt_force_rx_discard(bp, cpr, &raw_cons, |
2270bc5d | 2198 | &event); |
c0c050c5 MC |
2199 | if (likely(rc >= 0)) |
2200 | rx_pkts += rc; | |
903649e7 MC |
2201 | /* Increment rx_pkts when rc is -ENOMEM to count towards |
2202 | * the NAPI budget. Otherwise, we may potentially loop | |
2203 | * here forever if we consistently cannot allocate | |
2204 | * buffers. | |
2205 | */ | |
2edbdb31 | 2206 | else if (rc == -ENOMEM && budget) |
903649e7 | 2207 | rx_pkts++; |
c0c050c5 MC |
2208 | else if (rc == -EBUSY) /* partial completion */ |
2209 | break; | |
c0c050c5 MC |
2210 | } else if (unlikely((TX_CMP_TYPE(txcmp) == |
2211 | CMPL_BASE_TYPE_HWRM_DONE) || | |
2212 | (TX_CMP_TYPE(txcmp) == | |
2213 | CMPL_BASE_TYPE_HWRM_FWD_REQ) || | |
2214 | (TX_CMP_TYPE(txcmp) == | |
2215 | CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { | |
2216 | bnxt_hwrm_handler(bp, txcmp); | |
2217 | } | |
2218 | raw_cons = NEXT_RAW_CMP(raw_cons); | |
2219 | ||
0fcec985 MC |
2220 | if (rx_pkts && rx_pkts == budget) { |
2221 | cpr->has_more_work = 1; | |
c0c050c5 | 2222 | break; |
0fcec985 | 2223 | } |
c0c050c5 MC |
2224 | } |
2225 | ||
f18c2b77 AG |
2226 | if (event & BNXT_REDIRECT_EVENT) |
2227 | xdp_do_flush_map(); | |
2228 | ||
38413406 MC |
2229 | if (event & BNXT_TX_EVENT) { |
2230 | struct bnxt_tx_ring_info *txr = bnapi->tx_ring; | |
38413406 MC |
2231 | u16 prod = txr->tx_prod; |
2232 | ||
2233 | /* Sync BD data before updating doorbell */ | |
2234 | wmb(); | |
2235 | ||
697197e5 | 2236 | bnxt_db_write_relaxed(bp, &txr->tx_db, prod); |
38413406 MC |
2237 | } |
2238 | ||
c0c050c5 | 2239 | cpr->cp_raw_cons = raw_cons; |
3675b92f MC |
2240 | bnapi->tx_pkts += tx_pkts; |
2241 | bnapi->events |= event; | |
2242 | return rx_pkts; | |
2243 | } | |
c0c050c5 | 2244 | |
3675b92f MC |
2245 | static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi) |
2246 | { | |
2247 | if (bnapi->tx_pkts) { | |
2248 | bnapi->tx_int(bp, bnapi, bnapi->tx_pkts); | |
2249 | bnapi->tx_pkts = 0; | |
2250 | } | |
c0c050c5 | 2251 | |
3675b92f | 2252 | if (bnapi->events & BNXT_RX_EVENT) { |
b6ab4b01 | 2253 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
c0c050c5 | 2254 | |
3675b92f | 2255 | if (bnapi->events & BNXT_AGG_EVENT) |
697197e5 | 2256 | bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); |
e8f267b0 | 2257 | bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); |
c0c050c5 | 2258 | } |
3675b92f MC |
2259 | bnapi->events = 0; |
2260 | } | |
2261 | ||
2262 | static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, | |
2263 | int budget) | |
2264 | { | |
2265 | struct bnxt_napi *bnapi = cpr->bnapi; | |
2266 | int rx_pkts; | |
2267 | ||
2268 | rx_pkts = __bnxt_poll_work(bp, cpr, budget); | |
2269 | ||
2270 | /* ACK completion ring before freeing tx ring and producing new | |
2271 | * buffers in rx/agg rings to prevent overflowing the completion | |
2272 | * ring. | |
2273 | */ | |
2274 | bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons); | |
2275 | ||
2276 | __bnxt_poll_work_done(bp, bnapi); | |
c0c050c5 MC |
2277 | return rx_pkts; |
2278 | } | |
2279 | ||
10bbdaf5 PS |
2280 | static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) |
2281 | { | |
2282 | struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); | |
2283 | struct bnxt *bp = bnapi->bp; | |
2284 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2285 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; | |
2286 | struct tx_cmp *txcmp; | |
2287 | struct rx_cmp_ext *rxcmp1; | |
2288 | u32 cp_cons, tmp_raw_cons; | |
2289 | u32 raw_cons = cpr->cp_raw_cons; | |
2290 | u32 rx_pkts = 0; | |
4e5dbbda | 2291 | u8 event = 0; |
10bbdaf5 PS |
2292 | |
2293 | while (1) { | |
2294 | int rc; | |
2295 | ||
2296 | cp_cons = RING_CMP(raw_cons); | |
2297 | txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
2298 | ||
2299 | if (!TX_CMP_VALID(txcmp, raw_cons)) | |
2300 | break; | |
2301 | ||
2302 | if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { | |
2303 | tmp_raw_cons = NEXT_RAW_CMP(raw_cons); | |
2304 | cp_cons = RING_CMP(tmp_raw_cons); | |
2305 | rxcmp1 = (struct rx_cmp_ext *) | |
2306 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
2307 | ||
2308 | if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) | |
2309 | break; | |
2310 | ||
2311 | /* force an error to recycle the buffer */ | |
2312 | rxcmp1->rx_cmp_cfa_code_errors_v2 |= | |
2313 | cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); | |
2314 | ||
e44758b7 | 2315 | rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); |
2edbdb31 | 2316 | if (likely(rc == -EIO) && budget) |
10bbdaf5 PS |
2317 | rx_pkts++; |
2318 | else if (rc == -EBUSY) /* partial completion */ | |
2319 | break; | |
2320 | } else if (unlikely(TX_CMP_TYPE(txcmp) == | |
2321 | CMPL_BASE_TYPE_HWRM_DONE)) { | |
2322 | bnxt_hwrm_handler(bp, txcmp); | |
2323 | } else { | |
2324 | netdev_err(bp->dev, | |
2325 | "Invalid completion received on special ring\n"); | |
2326 | } | |
2327 | raw_cons = NEXT_RAW_CMP(raw_cons); | |
2328 | ||
2329 | if (rx_pkts == budget) | |
2330 | break; | |
2331 | } | |
2332 | ||
2333 | cpr->cp_raw_cons = raw_cons; | |
697197e5 MC |
2334 | BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons); |
2335 | bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); | |
10bbdaf5 | 2336 | |
434c975a | 2337 | if (event & BNXT_AGG_EVENT) |
697197e5 | 2338 | bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); |
10bbdaf5 PS |
2339 | |
2340 | if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) { | |
6ad20165 | 2341 | napi_complete_done(napi, rx_pkts); |
697197e5 | 2342 | BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); |
10bbdaf5 PS |
2343 | } |
2344 | return rx_pkts; | |
2345 | } | |
2346 | ||
c0c050c5 MC |
2347 | static int bnxt_poll(struct napi_struct *napi, int budget) |
2348 | { | |
2349 | struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); | |
2350 | struct bnxt *bp = bnapi->bp; | |
2351 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2352 | int work_done = 0; | |
2353 | ||
c0c050c5 | 2354 | while (1) { |
e44758b7 | 2355 | work_done += bnxt_poll_work(bp, cpr, budget - work_done); |
c0c050c5 | 2356 | |
73f21c65 MC |
2357 | if (work_done >= budget) { |
2358 | if (!budget) | |
697197e5 | 2359 | BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); |
c0c050c5 | 2360 | break; |
73f21c65 | 2361 | } |
c0c050c5 MC |
2362 | |
2363 | if (!bnxt_has_work(bp, cpr)) { | |
e7b95691 | 2364 | if (napi_complete_done(napi, work_done)) |
697197e5 | 2365 | BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); |
c0c050c5 MC |
2366 | break; |
2367 | } | |
2368 | } | |
6a8788f2 | 2369 | if (bp->flags & BNXT_FLAG_DIM) { |
f06d0ca4 | 2370 | struct dim_sample dim_sample = {}; |
6a8788f2 | 2371 | |
8960b389 TG |
2372 | dim_update_sample(cpr->event_ctr, |
2373 | cpr->rx_packets, | |
2374 | cpr->rx_bytes, | |
2375 | &dim_sample); | |
6a8788f2 AG |
2376 | net_dim(&cpr->dim, dim_sample); |
2377 | } | |
c0c050c5 MC |
2378 | return work_done; |
2379 | } | |
2380 | ||
0fcec985 MC |
2381 | static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) |
2382 | { | |
2383 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2384 | int i, work_done = 0; | |
2385 | ||
2386 | for (i = 0; i < 2; i++) { | |
2387 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; | |
2388 | ||
2389 | if (cpr2) { | |
2390 | work_done += __bnxt_poll_work(bp, cpr2, | |
2391 | budget - work_done); | |
2392 | cpr->has_more_work |= cpr2->has_more_work; | |
2393 | } | |
2394 | } | |
2395 | return work_done; | |
2396 | } | |
2397 | ||
2398 | static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi, | |
2399 | u64 dbr_type, bool all) | |
2400 | { | |
2401 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2402 | int i; | |
2403 | ||
2404 | for (i = 0; i < 2; i++) { | |
2405 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; | |
2406 | struct bnxt_db_info *db; | |
2407 | ||
2408 | if (cpr2 && (all || cpr2->had_work_done)) { | |
2409 | db = &cpr2->cp_db; | |
2410 | writeq(db->db_key64 | dbr_type | | |
2411 | RING_CMP(cpr2->cp_raw_cons), db->doorbell); | |
2412 | cpr2->had_work_done = 0; | |
2413 | } | |
2414 | } | |
2415 | __bnxt_poll_work_done(bp, bnapi); | |
2416 | } | |
2417 | ||
2418 | static int bnxt_poll_p5(struct napi_struct *napi, int budget) | |
2419 | { | |
2420 | struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); | |
2421 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2422 | u32 raw_cons = cpr->cp_raw_cons; | |
2423 | struct bnxt *bp = bnapi->bp; | |
2424 | struct nqe_cn *nqcmp; | |
2425 | int work_done = 0; | |
2426 | u32 cons; | |
2427 | ||
2428 | if (cpr->has_more_work) { | |
2429 | cpr->has_more_work = 0; | |
2430 | work_done = __bnxt_poll_cqs(bp, bnapi, budget); | |
2431 | if (cpr->has_more_work) { | |
2432 | __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, false); | |
2433 | return work_done; | |
2434 | } | |
2435 | __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, true); | |
2436 | if (napi_complete_done(napi, work_done)) | |
2437 | BNXT_DB_NQ_ARM_P5(&cpr->cp_db, cpr->cp_raw_cons); | |
2438 | return work_done; | |
2439 | } | |
2440 | while (1) { | |
2441 | cons = RING_CMP(raw_cons); | |
2442 | nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)]; | |
2443 | ||
2444 | if (!NQ_CMP_VALID(nqcmp, raw_cons)) { | |
2445 | __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, | |
2446 | false); | |
2447 | cpr->cp_raw_cons = raw_cons; | |
2448 | if (napi_complete_done(napi, work_done)) | |
2449 | BNXT_DB_NQ_ARM_P5(&cpr->cp_db, | |
2450 | cpr->cp_raw_cons); | |
2451 | return work_done; | |
2452 | } | |
2453 | ||
2454 | /* The valid test of the entry must be done first before | |
2455 | * reading any further. | |
2456 | */ | |
2457 | dma_rmb(); | |
2458 | ||
2459 | if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) { | |
2460 | u32 idx = le32_to_cpu(nqcmp->cq_handle_low); | |
2461 | struct bnxt_cp_ring_info *cpr2; | |
2462 | ||
2463 | cpr2 = cpr->cp_ring_arr[idx]; | |
2464 | work_done += __bnxt_poll_work(bp, cpr2, | |
2465 | budget - work_done); | |
2466 | cpr->has_more_work = cpr2->has_more_work; | |
2467 | } else { | |
2468 | bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp); | |
2469 | } | |
2470 | raw_cons = NEXT_RAW_CMP(raw_cons); | |
2471 | if (cpr->has_more_work) | |
2472 | break; | |
2473 | } | |
2474 | __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, true); | |
2475 | cpr->cp_raw_cons = raw_cons; | |
2476 | return work_done; | |
2477 | } | |
2478 | ||
c0c050c5 MC |
2479 | static void bnxt_free_tx_skbs(struct bnxt *bp) |
2480 | { | |
2481 | int i, max_idx; | |
2482 | struct pci_dev *pdev = bp->pdev; | |
2483 | ||
b6ab4b01 | 2484 | if (!bp->tx_ring) |
c0c050c5 MC |
2485 | return; |
2486 | ||
2487 | max_idx = bp->tx_nr_pages * TX_DESC_CNT; | |
2488 | for (i = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 2489 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
c0c050c5 MC |
2490 | int j; |
2491 | ||
c0c050c5 MC |
2492 | for (j = 0; j < max_idx;) { |
2493 | struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; | |
f18c2b77 | 2494 | struct sk_buff *skb; |
c0c050c5 MC |
2495 | int k, last; |
2496 | ||
f18c2b77 AG |
2497 | if (i < bp->tx_nr_rings_xdp && |
2498 | tx_buf->action == XDP_REDIRECT) { | |
2499 | dma_unmap_single(&pdev->dev, | |
2500 | dma_unmap_addr(tx_buf, mapping), | |
2501 | dma_unmap_len(tx_buf, len), | |
2502 | PCI_DMA_TODEVICE); | |
2503 | xdp_return_frame(tx_buf->xdpf); | |
2504 | tx_buf->action = 0; | |
2505 | tx_buf->xdpf = NULL; | |
2506 | j++; | |
2507 | continue; | |
2508 | } | |
2509 | ||
2510 | skb = tx_buf->skb; | |
c0c050c5 MC |
2511 | if (!skb) { |
2512 | j++; | |
2513 | continue; | |
2514 | } | |
2515 | ||
2516 | tx_buf->skb = NULL; | |
2517 | ||
2518 | if (tx_buf->is_push) { | |
2519 | dev_kfree_skb(skb); | |
2520 | j += 2; | |
2521 | continue; | |
2522 | } | |
2523 | ||
2524 | dma_unmap_single(&pdev->dev, | |
2525 | dma_unmap_addr(tx_buf, mapping), | |
2526 | skb_headlen(skb), | |
2527 | PCI_DMA_TODEVICE); | |
2528 | ||
2529 | last = tx_buf->nr_frags; | |
2530 | j += 2; | |
d612a579 MC |
2531 | for (k = 0; k < last; k++, j++) { |
2532 | int ring_idx = j & bp->tx_ring_mask; | |
c0c050c5 MC |
2533 | skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; |
2534 | ||
d612a579 | 2535 | tx_buf = &txr->tx_buf_ring[ring_idx]; |
c0c050c5 MC |
2536 | dma_unmap_page( |
2537 | &pdev->dev, | |
2538 | dma_unmap_addr(tx_buf, mapping), | |
2539 | skb_frag_size(frag), PCI_DMA_TODEVICE); | |
2540 | } | |
2541 | dev_kfree_skb(skb); | |
2542 | } | |
2543 | netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); | |
2544 | } | |
2545 | } | |
2546 | ||
2547 | static void bnxt_free_rx_skbs(struct bnxt *bp) | |
2548 | { | |
2549 | int i, max_idx, max_agg_idx; | |
2550 | struct pci_dev *pdev = bp->pdev; | |
2551 | ||
b6ab4b01 | 2552 | if (!bp->rx_ring) |
c0c050c5 MC |
2553 | return; |
2554 | ||
2555 | max_idx = bp->rx_nr_pages * RX_DESC_CNT; | |
2556 | max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; | |
2557 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
b6ab4b01 | 2558 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
ec4d8e7c | 2559 | struct bnxt_tpa_idx_map *map; |
c0c050c5 MC |
2560 | int j; |
2561 | ||
c0c050c5 | 2562 | if (rxr->rx_tpa) { |
79632e9b | 2563 | for (j = 0; j < bp->max_tpa; j++) { |
c0c050c5 MC |
2564 | struct bnxt_tpa_info *tpa_info = |
2565 | &rxr->rx_tpa[j]; | |
2566 | u8 *data = tpa_info->data; | |
2567 | ||
2568 | if (!data) | |
2569 | continue; | |
2570 | ||
c519fe9a SN |
2571 | dma_unmap_single_attrs(&pdev->dev, |
2572 | tpa_info->mapping, | |
2573 | bp->rx_buf_use_size, | |
2574 | bp->rx_dir, | |
2575 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
2576 | |
2577 | tpa_info->data = NULL; | |
2578 | ||
2579 | kfree(data); | |
2580 | } | |
2581 | } | |
2582 | ||
2583 | for (j = 0; j < max_idx; j++) { | |
2584 | struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j]; | |
3ed3a83e | 2585 | dma_addr_t mapping = rx_buf->mapping; |
6bb19474 | 2586 | void *data = rx_buf->data; |
c0c050c5 MC |
2587 | |
2588 | if (!data) | |
2589 | continue; | |
2590 | ||
c0c050c5 MC |
2591 | rx_buf->data = NULL; |
2592 | ||
3ed3a83e MC |
2593 | if (BNXT_RX_PAGE_MODE(bp)) { |
2594 | mapping -= bp->rx_dma_offset; | |
c519fe9a SN |
2595 | dma_unmap_page_attrs(&pdev->dev, mapping, |
2596 | PAGE_SIZE, bp->rx_dir, | |
2597 | DMA_ATTR_WEAK_ORDERING); | |
322b87ca | 2598 | page_pool_recycle_direct(rxr->page_pool, data); |
3ed3a83e | 2599 | } else { |
c519fe9a SN |
2600 | dma_unmap_single_attrs(&pdev->dev, mapping, |
2601 | bp->rx_buf_use_size, | |
2602 | bp->rx_dir, | |
2603 | DMA_ATTR_WEAK_ORDERING); | |
c61fb99c | 2604 | kfree(data); |
3ed3a83e | 2605 | } |
c0c050c5 MC |
2606 | } |
2607 | ||
2608 | for (j = 0; j < max_agg_idx; j++) { | |
2609 | struct bnxt_sw_rx_agg_bd *rx_agg_buf = | |
2610 | &rxr->rx_agg_ring[j]; | |
2611 | struct page *page = rx_agg_buf->page; | |
2612 | ||
2613 | if (!page) | |
2614 | continue; | |
2615 | ||
c519fe9a SN |
2616 | dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping, |
2617 | BNXT_RX_PAGE_SIZE, | |
2618 | PCI_DMA_FROMDEVICE, | |
2619 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
2620 | |
2621 | rx_agg_buf->page = NULL; | |
2622 | __clear_bit(j, rxr->rx_agg_bmap); | |
2623 | ||
2624 | __free_page(page); | |
2625 | } | |
89d0a06c MC |
2626 | if (rxr->rx_page) { |
2627 | __free_page(rxr->rx_page); | |
2628 | rxr->rx_page = NULL; | |
2629 | } | |
ec4d8e7c MC |
2630 | map = rxr->rx_tpa_idx_map; |
2631 | if (map) | |
2632 | memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap)); | |
c0c050c5 MC |
2633 | } |
2634 | } | |
2635 | ||
2636 | static void bnxt_free_skbs(struct bnxt *bp) | |
2637 | { | |
2638 | bnxt_free_tx_skbs(bp); | |
2639 | bnxt_free_rx_skbs(bp); | |
2640 | } | |
2641 | ||
6fe19886 | 2642 | static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) |
c0c050c5 MC |
2643 | { |
2644 | struct pci_dev *pdev = bp->pdev; | |
2645 | int i; | |
2646 | ||
6fe19886 MC |
2647 | for (i = 0; i < rmem->nr_pages; i++) { |
2648 | if (!rmem->pg_arr[i]) | |
c0c050c5 MC |
2649 | continue; |
2650 | ||
6fe19886 MC |
2651 | dma_free_coherent(&pdev->dev, rmem->page_size, |
2652 | rmem->pg_arr[i], rmem->dma_arr[i]); | |
c0c050c5 | 2653 | |
6fe19886 | 2654 | rmem->pg_arr[i] = NULL; |
c0c050c5 | 2655 | } |
6fe19886 | 2656 | if (rmem->pg_tbl) { |
4f49b2b8 MC |
2657 | size_t pg_tbl_size = rmem->nr_pages * 8; |
2658 | ||
2659 | if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) | |
2660 | pg_tbl_size = rmem->page_size; | |
2661 | dma_free_coherent(&pdev->dev, pg_tbl_size, | |
6fe19886 MC |
2662 | rmem->pg_tbl, rmem->pg_tbl_map); |
2663 | rmem->pg_tbl = NULL; | |
c0c050c5 | 2664 | } |
6fe19886 MC |
2665 | if (rmem->vmem_size && *rmem->vmem) { |
2666 | vfree(*rmem->vmem); | |
2667 | *rmem->vmem = NULL; | |
c0c050c5 MC |
2668 | } |
2669 | } | |
2670 | ||
6fe19886 | 2671 | static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) |
c0c050c5 | 2672 | { |
c0c050c5 | 2673 | struct pci_dev *pdev = bp->pdev; |
66cca20a | 2674 | u64 valid_bit = 0; |
6fe19886 | 2675 | int i; |
c0c050c5 | 2676 | |
66cca20a MC |
2677 | if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG)) |
2678 | valid_bit = PTU_PTE_VALID; | |
4f49b2b8 MC |
2679 | if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) { |
2680 | size_t pg_tbl_size = rmem->nr_pages * 8; | |
2681 | ||
2682 | if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) | |
2683 | pg_tbl_size = rmem->page_size; | |
2684 | rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size, | |
6fe19886 | 2685 | &rmem->pg_tbl_map, |
c0c050c5 | 2686 | GFP_KERNEL); |
6fe19886 | 2687 | if (!rmem->pg_tbl) |
c0c050c5 MC |
2688 | return -ENOMEM; |
2689 | } | |
2690 | ||
6fe19886 | 2691 | for (i = 0; i < rmem->nr_pages; i++) { |
66cca20a MC |
2692 | u64 extra_bits = valid_bit; |
2693 | ||
6fe19886 MC |
2694 | rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev, |
2695 | rmem->page_size, | |
2696 | &rmem->dma_arr[i], | |
c0c050c5 | 2697 | GFP_KERNEL); |
6fe19886 | 2698 | if (!rmem->pg_arr[i]) |
c0c050c5 MC |
2699 | return -ENOMEM; |
2700 | ||
3be8136c MC |
2701 | if (rmem->init_val) |
2702 | memset(rmem->pg_arr[i], rmem->init_val, | |
2703 | rmem->page_size); | |
4f49b2b8 | 2704 | if (rmem->nr_pages > 1 || rmem->depth > 0) { |
66cca20a MC |
2705 | if (i == rmem->nr_pages - 2 && |
2706 | (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) | |
2707 | extra_bits |= PTU_PTE_NEXT_TO_LAST; | |
2708 | else if (i == rmem->nr_pages - 1 && | |
2709 | (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) | |
2710 | extra_bits |= PTU_PTE_LAST; | |
2711 | rmem->pg_tbl[i] = | |
2712 | cpu_to_le64(rmem->dma_arr[i] | extra_bits); | |
2713 | } | |
c0c050c5 MC |
2714 | } |
2715 | ||
6fe19886 MC |
2716 | if (rmem->vmem_size) { |
2717 | *rmem->vmem = vzalloc(rmem->vmem_size); | |
2718 | if (!(*rmem->vmem)) | |
c0c050c5 MC |
2719 | return -ENOMEM; |
2720 | } | |
2721 | return 0; | |
2722 | } | |
2723 | ||
4a228a3a MC |
2724 | static void bnxt_free_tpa_info(struct bnxt *bp) |
2725 | { | |
2726 | int i; | |
2727 | ||
2728 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
2729 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; | |
2730 | ||
ec4d8e7c MC |
2731 | kfree(rxr->rx_tpa_idx_map); |
2732 | rxr->rx_tpa_idx_map = NULL; | |
79632e9b MC |
2733 | if (rxr->rx_tpa) { |
2734 | kfree(rxr->rx_tpa[0].agg_arr); | |
2735 | rxr->rx_tpa[0].agg_arr = NULL; | |
2736 | } | |
4a228a3a MC |
2737 | kfree(rxr->rx_tpa); |
2738 | rxr->rx_tpa = NULL; | |
2739 | } | |
2740 | } | |
2741 | ||
2742 | static int bnxt_alloc_tpa_info(struct bnxt *bp) | |
2743 | { | |
79632e9b MC |
2744 | int i, j, total_aggs = 0; |
2745 | ||
2746 | bp->max_tpa = MAX_TPA; | |
2747 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
2748 | if (!bp->max_tpa_v2) | |
2749 | return 0; | |
2750 | bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5); | |
2751 | total_aggs = bp->max_tpa * MAX_SKB_FRAGS; | |
2752 | } | |
4a228a3a MC |
2753 | |
2754 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
2755 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; | |
79632e9b | 2756 | struct rx_agg_cmp *agg; |
4a228a3a | 2757 | |
79632e9b | 2758 | rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info), |
4a228a3a MC |
2759 | GFP_KERNEL); |
2760 | if (!rxr->rx_tpa) | |
2761 | return -ENOMEM; | |
79632e9b MC |
2762 | |
2763 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
2764 | continue; | |
2765 | agg = kcalloc(total_aggs, sizeof(*agg), GFP_KERNEL); | |
2766 | rxr->rx_tpa[0].agg_arr = agg; | |
2767 | if (!agg) | |
2768 | return -ENOMEM; | |
2769 | for (j = 1; j < bp->max_tpa; j++) | |
2770 | rxr->rx_tpa[j].agg_arr = agg + j * MAX_SKB_FRAGS; | |
ec4d8e7c MC |
2771 | rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map), |
2772 | GFP_KERNEL); | |
2773 | if (!rxr->rx_tpa_idx_map) | |
2774 | return -ENOMEM; | |
4a228a3a MC |
2775 | } |
2776 | return 0; | |
2777 | } | |
2778 | ||
c0c050c5 MC |
2779 | static void bnxt_free_rx_rings(struct bnxt *bp) |
2780 | { | |
2781 | int i; | |
2782 | ||
b6ab4b01 | 2783 | if (!bp->rx_ring) |
c0c050c5 MC |
2784 | return; |
2785 | ||
4a228a3a | 2786 | bnxt_free_tpa_info(bp); |
c0c050c5 | 2787 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 2788 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
c0c050c5 MC |
2789 | struct bnxt_ring_struct *ring; |
2790 | ||
c6d30e83 MC |
2791 | if (rxr->xdp_prog) |
2792 | bpf_prog_put(rxr->xdp_prog); | |
2793 | ||
96a8604f JDB |
2794 | if (xdp_rxq_info_is_reg(&rxr->xdp_rxq)) |
2795 | xdp_rxq_info_unreg(&rxr->xdp_rxq); | |
2796 | ||
12479f62 | 2797 | page_pool_destroy(rxr->page_pool); |
322b87ca AG |
2798 | rxr->page_pool = NULL; |
2799 | ||
c0c050c5 MC |
2800 | kfree(rxr->rx_agg_bmap); |
2801 | rxr->rx_agg_bmap = NULL; | |
2802 | ||
2803 | ring = &rxr->rx_ring_struct; | |
6fe19886 | 2804 | bnxt_free_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2805 | |
2806 | ring = &rxr->rx_agg_ring_struct; | |
6fe19886 | 2807 | bnxt_free_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2808 | } |
2809 | } | |
2810 | ||
322b87ca AG |
2811 | static int bnxt_alloc_rx_page_pool(struct bnxt *bp, |
2812 | struct bnxt_rx_ring_info *rxr) | |
2813 | { | |
2814 | struct page_pool_params pp = { 0 }; | |
2815 | ||
2816 | pp.pool_size = bp->rx_ring_size; | |
2817 | pp.nid = dev_to_node(&bp->pdev->dev); | |
2818 | pp.dev = &bp->pdev->dev; | |
2819 | pp.dma_dir = DMA_BIDIRECTIONAL; | |
2820 | ||
2821 | rxr->page_pool = page_pool_create(&pp); | |
2822 | if (IS_ERR(rxr->page_pool)) { | |
2823 | int err = PTR_ERR(rxr->page_pool); | |
2824 | ||
2825 | rxr->page_pool = NULL; | |
2826 | return err; | |
2827 | } | |
2828 | return 0; | |
2829 | } | |
2830 | ||
c0c050c5 MC |
2831 | static int bnxt_alloc_rx_rings(struct bnxt *bp) |
2832 | { | |
4a228a3a | 2833 | int i, rc = 0, agg_rings = 0; |
c0c050c5 | 2834 | |
b6ab4b01 MC |
2835 | if (!bp->rx_ring) |
2836 | return -ENOMEM; | |
2837 | ||
c0c050c5 MC |
2838 | if (bp->flags & BNXT_FLAG_AGG_RINGS) |
2839 | agg_rings = 1; | |
2840 | ||
c0c050c5 | 2841 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 2842 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
c0c050c5 MC |
2843 | struct bnxt_ring_struct *ring; |
2844 | ||
c0c050c5 MC |
2845 | ring = &rxr->rx_ring_struct; |
2846 | ||
322b87ca AG |
2847 | rc = bnxt_alloc_rx_page_pool(bp, rxr); |
2848 | if (rc) | |
2849 | return rc; | |
2850 | ||
96a8604f | 2851 | rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i); |
12479f62 | 2852 | if (rc < 0) |
96a8604f JDB |
2853 | return rc; |
2854 | ||
f18c2b77 | 2855 | rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq, |
322b87ca AG |
2856 | MEM_TYPE_PAGE_POOL, |
2857 | rxr->page_pool); | |
f18c2b77 AG |
2858 | if (rc) { |
2859 | xdp_rxq_info_unreg(&rxr->xdp_rxq); | |
2860 | return rc; | |
2861 | } | |
2862 | ||
6fe19886 | 2863 | rc = bnxt_alloc_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2864 | if (rc) |
2865 | return rc; | |
2866 | ||
2c61d211 | 2867 | ring->grp_idx = i; |
c0c050c5 MC |
2868 | if (agg_rings) { |
2869 | u16 mem_size; | |
2870 | ||
2871 | ring = &rxr->rx_agg_ring_struct; | |
6fe19886 | 2872 | rc = bnxt_alloc_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2873 | if (rc) |
2874 | return rc; | |
2875 | ||
9899bb59 | 2876 | ring->grp_idx = i; |
c0c050c5 MC |
2877 | rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; |
2878 | mem_size = rxr->rx_agg_bmap_size / 8; | |
2879 | rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); | |
2880 | if (!rxr->rx_agg_bmap) | |
2881 | return -ENOMEM; | |
c0c050c5 MC |
2882 | } |
2883 | } | |
4a228a3a MC |
2884 | if (bp->flags & BNXT_FLAG_TPA) |
2885 | rc = bnxt_alloc_tpa_info(bp); | |
2886 | return rc; | |
c0c050c5 MC |
2887 | } |
2888 | ||
2889 | static void bnxt_free_tx_rings(struct bnxt *bp) | |
2890 | { | |
2891 | int i; | |
2892 | struct pci_dev *pdev = bp->pdev; | |
2893 | ||
b6ab4b01 | 2894 | if (!bp->tx_ring) |
c0c050c5 MC |
2895 | return; |
2896 | ||
2897 | for (i = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 2898 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
c0c050c5 MC |
2899 | struct bnxt_ring_struct *ring; |
2900 | ||
c0c050c5 MC |
2901 | if (txr->tx_push) { |
2902 | dma_free_coherent(&pdev->dev, bp->tx_push_size, | |
2903 | txr->tx_push, txr->tx_push_mapping); | |
2904 | txr->tx_push = NULL; | |
2905 | } | |
2906 | ||
2907 | ring = &txr->tx_ring_struct; | |
2908 | ||
6fe19886 | 2909 | bnxt_free_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2910 | } |
2911 | } | |
2912 | ||
2913 | static int bnxt_alloc_tx_rings(struct bnxt *bp) | |
2914 | { | |
2915 | int i, j, rc; | |
2916 | struct pci_dev *pdev = bp->pdev; | |
2917 | ||
2918 | bp->tx_push_size = 0; | |
2919 | if (bp->tx_push_thresh) { | |
2920 | int push_size; | |
2921 | ||
2922 | push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + | |
2923 | bp->tx_push_thresh); | |
2924 | ||
4419dbe6 | 2925 | if (push_size > 256) { |
c0c050c5 MC |
2926 | push_size = 0; |
2927 | bp->tx_push_thresh = 0; | |
2928 | } | |
2929 | ||
2930 | bp->tx_push_size = push_size; | |
2931 | } | |
2932 | ||
2933 | for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 2934 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
c0c050c5 | 2935 | struct bnxt_ring_struct *ring; |
2e8ef77e | 2936 | u8 qidx; |
c0c050c5 | 2937 | |
c0c050c5 MC |
2938 | ring = &txr->tx_ring_struct; |
2939 | ||
6fe19886 | 2940 | rc = bnxt_alloc_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2941 | if (rc) |
2942 | return rc; | |
2943 | ||
9899bb59 | 2944 | ring->grp_idx = txr->bnapi->index; |
c0c050c5 | 2945 | if (bp->tx_push_size) { |
c0c050c5 MC |
2946 | dma_addr_t mapping; |
2947 | ||
2948 | /* One pre-allocated DMA buffer to backup | |
2949 | * TX push operation | |
2950 | */ | |
2951 | txr->tx_push = dma_alloc_coherent(&pdev->dev, | |
2952 | bp->tx_push_size, | |
2953 | &txr->tx_push_mapping, | |
2954 | GFP_KERNEL); | |
2955 | ||
2956 | if (!txr->tx_push) | |
2957 | return -ENOMEM; | |
2958 | ||
c0c050c5 MC |
2959 | mapping = txr->tx_push_mapping + |
2960 | sizeof(struct tx_push_bd); | |
4419dbe6 | 2961 | txr->data_mapping = cpu_to_le64(mapping); |
c0c050c5 | 2962 | } |
2e8ef77e MC |
2963 | qidx = bp->tc_to_qidx[j]; |
2964 | ring->queue_id = bp->q_info[qidx].queue_id; | |
5f449249 MC |
2965 | if (i < bp->tx_nr_rings_xdp) |
2966 | continue; | |
c0c050c5 MC |
2967 | if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) |
2968 | j++; | |
2969 | } | |
2970 | return 0; | |
2971 | } | |
2972 | ||
2973 | static void bnxt_free_cp_rings(struct bnxt *bp) | |
2974 | { | |
2975 | int i; | |
2976 | ||
2977 | if (!bp->bnapi) | |
2978 | return; | |
2979 | ||
2980 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
2981 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
2982 | struct bnxt_cp_ring_info *cpr; | |
2983 | struct bnxt_ring_struct *ring; | |
50e3ab78 | 2984 | int j; |
c0c050c5 MC |
2985 | |
2986 | if (!bnapi) | |
2987 | continue; | |
2988 | ||
2989 | cpr = &bnapi->cp_ring; | |
2990 | ring = &cpr->cp_ring_struct; | |
2991 | ||
6fe19886 | 2992 | bnxt_free_ring(bp, &ring->ring_mem); |
50e3ab78 MC |
2993 | |
2994 | for (j = 0; j < 2; j++) { | |
2995 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; | |
2996 | ||
2997 | if (cpr2) { | |
2998 | ring = &cpr2->cp_ring_struct; | |
2999 | bnxt_free_ring(bp, &ring->ring_mem); | |
3000 | kfree(cpr2); | |
3001 | cpr->cp_ring_arr[j] = NULL; | |
3002 | } | |
3003 | } | |
c0c050c5 MC |
3004 | } |
3005 | } | |
3006 | ||
50e3ab78 MC |
3007 | static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp) |
3008 | { | |
3009 | struct bnxt_ring_mem_info *rmem; | |
3010 | struct bnxt_ring_struct *ring; | |
3011 | struct bnxt_cp_ring_info *cpr; | |
3012 | int rc; | |
3013 | ||
3014 | cpr = kzalloc(sizeof(*cpr), GFP_KERNEL); | |
3015 | if (!cpr) | |
3016 | return NULL; | |
3017 | ||
3018 | ring = &cpr->cp_ring_struct; | |
3019 | rmem = &ring->ring_mem; | |
3020 | rmem->nr_pages = bp->cp_nr_pages; | |
3021 | rmem->page_size = HW_CMPD_RING_SIZE; | |
3022 | rmem->pg_arr = (void **)cpr->cp_desc_ring; | |
3023 | rmem->dma_arr = cpr->cp_desc_mapping; | |
3024 | rmem->flags = BNXT_RMEM_RING_PTE_FLAG; | |
3025 | rc = bnxt_alloc_ring(bp, rmem); | |
3026 | if (rc) { | |
3027 | bnxt_free_ring(bp, rmem); | |
3028 | kfree(cpr); | |
3029 | cpr = NULL; | |
3030 | } | |
3031 | return cpr; | |
3032 | } | |
3033 | ||
c0c050c5 MC |
3034 | static int bnxt_alloc_cp_rings(struct bnxt *bp) |
3035 | { | |
50e3ab78 | 3036 | bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS); |
e5811b8c | 3037 | int i, rc, ulp_base_vec, ulp_msix; |
c0c050c5 | 3038 | |
e5811b8c MC |
3039 | ulp_msix = bnxt_get_ulp_msix_num(bp); |
3040 | ulp_base_vec = bnxt_get_ulp_msix_base(bp); | |
c0c050c5 MC |
3041 | for (i = 0; i < bp->cp_nr_rings; i++) { |
3042 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
3043 | struct bnxt_cp_ring_info *cpr; | |
3044 | struct bnxt_ring_struct *ring; | |
3045 | ||
3046 | if (!bnapi) | |
3047 | continue; | |
3048 | ||
3049 | cpr = &bnapi->cp_ring; | |
50e3ab78 | 3050 | cpr->bnapi = bnapi; |
c0c050c5 MC |
3051 | ring = &cpr->cp_ring_struct; |
3052 | ||
6fe19886 | 3053 | rc = bnxt_alloc_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
3054 | if (rc) |
3055 | return rc; | |
e5811b8c MC |
3056 | |
3057 | if (ulp_msix && i >= ulp_base_vec) | |
3058 | ring->map_idx = i + ulp_msix; | |
3059 | else | |
3060 | ring->map_idx = i; | |
50e3ab78 MC |
3061 | |
3062 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
3063 | continue; | |
3064 | ||
3065 | if (i < bp->rx_nr_rings) { | |
3066 | struct bnxt_cp_ring_info *cpr2 = | |
3067 | bnxt_alloc_cp_sub_ring(bp); | |
3068 | ||
3069 | cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2; | |
3070 | if (!cpr2) | |
3071 | return -ENOMEM; | |
3072 | cpr2->bnapi = bnapi; | |
3073 | } | |
3074 | if ((sh && i < bp->tx_nr_rings) || | |
3075 | (!sh && i >= bp->rx_nr_rings)) { | |
3076 | struct bnxt_cp_ring_info *cpr2 = | |
3077 | bnxt_alloc_cp_sub_ring(bp); | |
3078 | ||
3079 | cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2; | |
3080 | if (!cpr2) | |
3081 | return -ENOMEM; | |
3082 | cpr2->bnapi = bnapi; | |
3083 | } | |
c0c050c5 MC |
3084 | } |
3085 | return 0; | |
3086 | } | |
3087 | ||
3088 | static void bnxt_init_ring_struct(struct bnxt *bp) | |
3089 | { | |
3090 | int i; | |
3091 | ||
3092 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3093 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
6fe19886 | 3094 | struct bnxt_ring_mem_info *rmem; |
c0c050c5 MC |
3095 | struct bnxt_cp_ring_info *cpr; |
3096 | struct bnxt_rx_ring_info *rxr; | |
3097 | struct bnxt_tx_ring_info *txr; | |
3098 | struct bnxt_ring_struct *ring; | |
3099 | ||
3100 | if (!bnapi) | |
3101 | continue; | |
3102 | ||
3103 | cpr = &bnapi->cp_ring; | |
3104 | ring = &cpr->cp_ring_struct; | |
6fe19886 MC |
3105 | rmem = &ring->ring_mem; |
3106 | rmem->nr_pages = bp->cp_nr_pages; | |
3107 | rmem->page_size = HW_CMPD_RING_SIZE; | |
3108 | rmem->pg_arr = (void **)cpr->cp_desc_ring; | |
3109 | rmem->dma_arr = cpr->cp_desc_mapping; | |
3110 | rmem->vmem_size = 0; | |
c0c050c5 | 3111 | |
b6ab4b01 | 3112 | rxr = bnapi->rx_ring; |
3b2b7d9d MC |
3113 | if (!rxr) |
3114 | goto skip_rx; | |
3115 | ||
c0c050c5 | 3116 | ring = &rxr->rx_ring_struct; |
6fe19886 MC |
3117 | rmem = &ring->ring_mem; |
3118 | rmem->nr_pages = bp->rx_nr_pages; | |
3119 | rmem->page_size = HW_RXBD_RING_SIZE; | |
3120 | rmem->pg_arr = (void **)rxr->rx_desc_ring; | |
3121 | rmem->dma_arr = rxr->rx_desc_mapping; | |
3122 | rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; | |
3123 | rmem->vmem = (void **)&rxr->rx_buf_ring; | |
c0c050c5 MC |
3124 | |
3125 | ring = &rxr->rx_agg_ring_struct; | |
6fe19886 MC |
3126 | rmem = &ring->ring_mem; |
3127 | rmem->nr_pages = bp->rx_agg_nr_pages; | |
3128 | rmem->page_size = HW_RXBD_RING_SIZE; | |
3129 | rmem->pg_arr = (void **)rxr->rx_agg_desc_ring; | |
3130 | rmem->dma_arr = rxr->rx_agg_desc_mapping; | |
3131 | rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; | |
3132 | rmem->vmem = (void **)&rxr->rx_agg_ring; | |
c0c050c5 | 3133 | |
3b2b7d9d | 3134 | skip_rx: |
b6ab4b01 | 3135 | txr = bnapi->tx_ring; |
3b2b7d9d MC |
3136 | if (!txr) |
3137 | continue; | |
3138 | ||
c0c050c5 | 3139 | ring = &txr->tx_ring_struct; |
6fe19886 MC |
3140 | rmem = &ring->ring_mem; |
3141 | rmem->nr_pages = bp->tx_nr_pages; | |
3142 | rmem->page_size = HW_RXBD_RING_SIZE; | |
3143 | rmem->pg_arr = (void **)txr->tx_desc_ring; | |
3144 | rmem->dma_arr = txr->tx_desc_mapping; | |
3145 | rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; | |
3146 | rmem->vmem = (void **)&txr->tx_buf_ring; | |
c0c050c5 MC |
3147 | } |
3148 | } | |
3149 | ||
3150 | static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) | |
3151 | { | |
3152 | int i; | |
3153 | u32 prod; | |
3154 | struct rx_bd **rx_buf_ring; | |
3155 | ||
6fe19886 MC |
3156 | rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr; |
3157 | for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) { | |
c0c050c5 MC |
3158 | int j; |
3159 | struct rx_bd *rxbd; | |
3160 | ||
3161 | rxbd = rx_buf_ring[i]; | |
3162 | if (!rxbd) | |
3163 | continue; | |
3164 | ||
3165 | for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { | |
3166 | rxbd->rx_bd_len_flags_type = cpu_to_le32(type); | |
3167 | rxbd->rx_bd_opaque = prod; | |
3168 | } | |
3169 | } | |
3170 | } | |
3171 | ||
3172 | static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) | |
3173 | { | |
3174 | struct net_device *dev = bp->dev; | |
c0c050c5 MC |
3175 | struct bnxt_rx_ring_info *rxr; |
3176 | struct bnxt_ring_struct *ring; | |
3177 | u32 prod, type; | |
3178 | int i; | |
3179 | ||
c0c050c5 MC |
3180 | type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | |
3181 | RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; | |
3182 | ||
3183 | if (NET_IP_ALIGN == 2) | |
3184 | type |= RX_BD_FLAGS_SOP; | |
3185 | ||
b6ab4b01 | 3186 | rxr = &bp->rx_ring[ring_nr]; |
c0c050c5 MC |
3187 | ring = &rxr->rx_ring_struct; |
3188 | bnxt_init_rxbd_pages(ring, type); | |
3189 | ||
c6d30e83 | 3190 | if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) { |
85192dbf AN |
3191 | bpf_prog_add(bp->xdp_prog, 1); |
3192 | rxr->xdp_prog = bp->xdp_prog; | |
c6d30e83 | 3193 | } |
c0c050c5 MC |
3194 | prod = rxr->rx_prod; |
3195 | for (i = 0; i < bp->rx_ring_size; i++) { | |
3196 | if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) { | |
3197 | netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", | |
3198 | ring_nr, i, bp->rx_ring_size); | |
3199 | break; | |
3200 | } | |
3201 | prod = NEXT_RX(prod); | |
3202 | } | |
3203 | rxr->rx_prod = prod; | |
3204 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
3205 | ||
edd0c2cc MC |
3206 | ring = &rxr->rx_agg_ring_struct; |
3207 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
3208 | ||
c0c050c5 MC |
3209 | if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) |
3210 | return 0; | |
3211 | ||
2839f28b | 3212 | type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) | |
c0c050c5 MC |
3213 | RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; |
3214 | ||
3215 | bnxt_init_rxbd_pages(ring, type); | |
3216 | ||
3217 | prod = rxr->rx_agg_prod; | |
3218 | for (i = 0; i < bp->rx_agg_ring_size; i++) { | |
3219 | if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) { | |
3220 | netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", | |
3221 | ring_nr, i, bp->rx_ring_size); | |
3222 | break; | |
3223 | } | |
3224 | prod = NEXT_RX_AGG(prod); | |
3225 | } | |
3226 | rxr->rx_agg_prod = prod; | |
c0c050c5 MC |
3227 | |
3228 | if (bp->flags & BNXT_FLAG_TPA) { | |
3229 | if (rxr->rx_tpa) { | |
3230 | u8 *data; | |
3231 | dma_addr_t mapping; | |
3232 | ||
79632e9b | 3233 | for (i = 0; i < bp->max_tpa; i++) { |
c0c050c5 MC |
3234 | data = __bnxt_alloc_rx_data(bp, &mapping, |
3235 | GFP_KERNEL); | |
3236 | if (!data) | |
3237 | return -ENOMEM; | |
3238 | ||
3239 | rxr->rx_tpa[i].data = data; | |
b3dba77c | 3240 | rxr->rx_tpa[i].data_ptr = data + bp->rx_offset; |
c0c050c5 MC |
3241 | rxr->rx_tpa[i].mapping = mapping; |
3242 | } | |
3243 | } else { | |
3244 | netdev_err(bp->dev, "No resource allocated for LRO/GRO\n"); | |
3245 | return -ENOMEM; | |
3246 | } | |
3247 | } | |
3248 | ||
3249 | return 0; | |
3250 | } | |
3251 | ||
2247925f SP |
3252 | static void bnxt_init_cp_rings(struct bnxt *bp) |
3253 | { | |
3e08b184 | 3254 | int i, j; |
2247925f SP |
3255 | |
3256 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3257 | struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; | |
3258 | struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; | |
3259 | ||
3260 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
6a8788f2 AG |
3261 | cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; |
3262 | cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; | |
3e08b184 MC |
3263 | for (j = 0; j < 2; j++) { |
3264 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; | |
3265 | ||
3266 | if (!cpr2) | |
3267 | continue; | |
3268 | ||
3269 | ring = &cpr2->cp_ring_struct; | |
3270 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
3271 | cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; | |
3272 | cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; | |
3273 | } | |
2247925f SP |
3274 | } |
3275 | } | |
3276 | ||
c0c050c5 MC |
3277 | static int bnxt_init_rx_rings(struct bnxt *bp) |
3278 | { | |
3279 | int i, rc = 0; | |
3280 | ||
c61fb99c | 3281 | if (BNXT_RX_PAGE_MODE(bp)) { |
c6d30e83 MC |
3282 | bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM; |
3283 | bp->rx_dma_offset = XDP_PACKET_HEADROOM; | |
c61fb99c MC |
3284 | } else { |
3285 | bp->rx_offset = BNXT_RX_OFFSET; | |
3286 | bp->rx_dma_offset = BNXT_RX_DMA_OFFSET; | |
3287 | } | |
b3dba77c | 3288 | |
c0c050c5 MC |
3289 | for (i = 0; i < bp->rx_nr_rings; i++) { |
3290 | rc = bnxt_init_one_rx_ring(bp, i); | |
3291 | if (rc) | |
3292 | break; | |
3293 | } | |
3294 | ||
3295 | return rc; | |
3296 | } | |
3297 | ||
3298 | static int bnxt_init_tx_rings(struct bnxt *bp) | |
3299 | { | |
3300 | u16 i; | |
3301 | ||
3302 | bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, | |
3303 | MAX_SKB_FRAGS + 1); | |
3304 | ||
3305 | for (i = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 3306 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
c0c050c5 MC |
3307 | struct bnxt_ring_struct *ring = &txr->tx_ring_struct; |
3308 | ||
3309 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
3310 | } | |
3311 | ||
3312 | return 0; | |
3313 | } | |
3314 | ||
3315 | static void bnxt_free_ring_grps(struct bnxt *bp) | |
3316 | { | |
3317 | kfree(bp->grp_info); | |
3318 | bp->grp_info = NULL; | |
3319 | } | |
3320 | ||
3321 | static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) | |
3322 | { | |
3323 | int i; | |
3324 | ||
3325 | if (irq_re_init) { | |
3326 | bp->grp_info = kcalloc(bp->cp_nr_rings, | |
3327 | sizeof(struct bnxt_ring_grp_info), | |
3328 | GFP_KERNEL); | |
3329 | if (!bp->grp_info) | |
3330 | return -ENOMEM; | |
3331 | } | |
3332 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3333 | if (irq_re_init) | |
3334 | bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; | |
3335 | bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; | |
3336 | bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; | |
3337 | bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; | |
3338 | bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; | |
3339 | } | |
3340 | return 0; | |
3341 | } | |
3342 | ||
3343 | static void bnxt_free_vnics(struct bnxt *bp) | |
3344 | { | |
3345 | kfree(bp->vnic_info); | |
3346 | bp->vnic_info = NULL; | |
3347 | bp->nr_vnics = 0; | |
3348 | } | |
3349 | ||
3350 | static int bnxt_alloc_vnics(struct bnxt *bp) | |
3351 | { | |
3352 | int num_vnics = 1; | |
3353 | ||
3354 | #ifdef CONFIG_RFS_ACCEL | |
9b3d15e6 | 3355 | if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) |
c0c050c5 MC |
3356 | num_vnics += bp->rx_nr_rings; |
3357 | #endif | |
3358 | ||
dc52c6c7 PS |
3359 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) |
3360 | num_vnics++; | |
3361 | ||
c0c050c5 MC |
3362 | bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), |
3363 | GFP_KERNEL); | |
3364 | if (!bp->vnic_info) | |
3365 | return -ENOMEM; | |
3366 | ||
3367 | bp->nr_vnics = num_vnics; | |
3368 | return 0; | |
3369 | } | |
3370 | ||
3371 | static void bnxt_init_vnics(struct bnxt *bp) | |
3372 | { | |
3373 | int i; | |
3374 | ||
3375 | for (i = 0; i < bp->nr_vnics; i++) { | |
3376 | struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; | |
44c6f72a | 3377 | int j; |
c0c050c5 MC |
3378 | |
3379 | vnic->fw_vnic_id = INVALID_HW_RING_ID; | |
44c6f72a MC |
3380 | for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) |
3381 | vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID; | |
3382 | ||
c0c050c5 MC |
3383 | vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; |
3384 | ||
3385 | if (bp->vnic_info[i].rss_hash_key) { | |
3386 | if (i == 0) | |
3387 | prandom_bytes(vnic->rss_hash_key, | |
3388 | HW_HASH_KEY_SIZE); | |
3389 | else | |
3390 | memcpy(vnic->rss_hash_key, | |
3391 | bp->vnic_info[0].rss_hash_key, | |
3392 | HW_HASH_KEY_SIZE); | |
3393 | } | |
3394 | } | |
3395 | } | |
3396 | ||
3397 | static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) | |
3398 | { | |
3399 | int pages; | |
3400 | ||
3401 | pages = ring_size / desc_per_pg; | |
3402 | ||
3403 | if (!pages) | |
3404 | return 1; | |
3405 | ||
3406 | pages++; | |
3407 | ||
3408 | while (pages & (pages - 1)) | |
3409 | pages++; | |
3410 | ||
3411 | return pages; | |
3412 | } | |
3413 | ||
c6d30e83 | 3414 | void bnxt_set_tpa_flags(struct bnxt *bp) |
c0c050c5 MC |
3415 | { |
3416 | bp->flags &= ~BNXT_FLAG_TPA; | |
341138c3 MC |
3417 | if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) |
3418 | return; | |
c0c050c5 MC |
3419 | if (bp->dev->features & NETIF_F_LRO) |
3420 | bp->flags |= BNXT_FLAG_LRO; | |
1054aee8 | 3421 | else if (bp->dev->features & NETIF_F_GRO_HW) |
c0c050c5 MC |
3422 | bp->flags |= BNXT_FLAG_GRO; |
3423 | } | |
3424 | ||
3425 | /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must | |
3426 | * be set on entry. | |
3427 | */ | |
3428 | void bnxt_set_ring_params(struct bnxt *bp) | |
3429 | { | |
3430 | u32 ring_size, rx_size, rx_space; | |
3431 | u32 agg_factor = 0, agg_ring_size = 0; | |
3432 | ||
3433 | /* 8 for CRC and VLAN */ | |
3434 | rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); | |
3435 | ||
3436 | rx_space = rx_size + NET_SKB_PAD + | |
3437 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
3438 | ||
3439 | bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; | |
3440 | ring_size = bp->rx_ring_size; | |
3441 | bp->rx_agg_ring_size = 0; | |
3442 | bp->rx_agg_nr_pages = 0; | |
3443 | ||
3444 | if (bp->flags & BNXT_FLAG_TPA) | |
2839f28b | 3445 | agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE); |
c0c050c5 MC |
3446 | |
3447 | bp->flags &= ~BNXT_FLAG_JUMBO; | |
bdbd1eb5 | 3448 | if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) { |
c0c050c5 MC |
3449 | u32 jumbo_factor; |
3450 | ||
3451 | bp->flags |= BNXT_FLAG_JUMBO; | |
3452 | jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; | |
3453 | if (jumbo_factor > agg_factor) | |
3454 | agg_factor = jumbo_factor; | |
3455 | } | |
3456 | agg_ring_size = ring_size * agg_factor; | |
3457 | ||
3458 | if (agg_ring_size) { | |
3459 | bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, | |
3460 | RX_DESC_CNT); | |
3461 | if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { | |
3462 | u32 tmp = agg_ring_size; | |
3463 | ||
3464 | bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; | |
3465 | agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; | |
3466 | netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", | |
3467 | tmp, agg_ring_size); | |
3468 | } | |
3469 | bp->rx_agg_ring_size = agg_ring_size; | |
3470 | bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; | |
3471 | rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); | |
3472 | rx_space = rx_size + NET_SKB_PAD + | |
3473 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
3474 | } | |
3475 | ||
3476 | bp->rx_buf_use_size = rx_size; | |
3477 | bp->rx_buf_size = rx_space; | |
3478 | ||
3479 | bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); | |
3480 | bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; | |
3481 | ||
3482 | ring_size = bp->tx_ring_size; | |
3483 | bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); | |
3484 | bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; | |
3485 | ||
3486 | ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size; | |
3487 | bp->cp_ring_size = ring_size; | |
3488 | ||
3489 | bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); | |
3490 | if (bp->cp_nr_pages > MAX_CP_PAGES) { | |
3491 | bp->cp_nr_pages = MAX_CP_PAGES; | |
3492 | bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; | |
3493 | netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", | |
3494 | ring_size, bp->cp_ring_size); | |
3495 | } | |
3496 | bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; | |
3497 | bp->cp_ring_mask = bp->cp_bit - 1; | |
3498 | } | |
3499 | ||
96a8604f JDB |
3500 | /* Changing allocation mode of RX rings. |
3501 | * TODO: Update when extending xdp_rxq_info to support allocation modes. | |
3502 | */ | |
c61fb99c | 3503 | int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode) |
6bb19474 | 3504 | { |
c61fb99c MC |
3505 | if (page_mode) { |
3506 | if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU) | |
3507 | return -EOPNOTSUPP; | |
7eb9bb3a MC |
3508 | bp->dev->max_mtu = |
3509 | min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU); | |
c61fb99c MC |
3510 | bp->flags &= ~BNXT_FLAG_AGG_RINGS; |
3511 | bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE; | |
c61fb99c MC |
3512 | bp->rx_dir = DMA_BIDIRECTIONAL; |
3513 | bp->rx_skb_func = bnxt_rx_page_skb; | |
1054aee8 MC |
3514 | /* Disable LRO or GRO_HW */ |
3515 | netdev_update_features(bp->dev); | |
c61fb99c | 3516 | } else { |
7eb9bb3a | 3517 | bp->dev->max_mtu = bp->max_mtu; |
c61fb99c MC |
3518 | bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE; |
3519 | bp->rx_dir = DMA_FROM_DEVICE; | |
3520 | bp->rx_skb_func = bnxt_rx_skb; | |
3521 | } | |
6bb19474 MC |
3522 | return 0; |
3523 | } | |
3524 | ||
c0c050c5 MC |
3525 | static void bnxt_free_vnic_attributes(struct bnxt *bp) |
3526 | { | |
3527 | int i; | |
3528 | struct bnxt_vnic_info *vnic; | |
3529 | struct pci_dev *pdev = bp->pdev; | |
3530 | ||
3531 | if (!bp->vnic_info) | |
3532 | return; | |
3533 | ||
3534 | for (i = 0; i < bp->nr_vnics; i++) { | |
3535 | vnic = &bp->vnic_info[i]; | |
3536 | ||
3537 | kfree(vnic->fw_grp_ids); | |
3538 | vnic->fw_grp_ids = NULL; | |
3539 | ||
3540 | kfree(vnic->uc_list); | |
3541 | vnic->uc_list = NULL; | |
3542 | ||
3543 | if (vnic->mc_list) { | |
3544 | dma_free_coherent(&pdev->dev, vnic->mc_list_size, | |
3545 | vnic->mc_list, vnic->mc_list_mapping); | |
3546 | vnic->mc_list = NULL; | |
3547 | } | |
3548 | ||
3549 | if (vnic->rss_table) { | |
3550 | dma_free_coherent(&pdev->dev, PAGE_SIZE, | |
3551 | vnic->rss_table, | |
3552 | vnic->rss_table_dma_addr); | |
3553 | vnic->rss_table = NULL; | |
3554 | } | |
3555 | ||
3556 | vnic->rss_hash_key = NULL; | |
3557 | vnic->flags = 0; | |
3558 | } | |
3559 | } | |
3560 | ||
3561 | static int bnxt_alloc_vnic_attributes(struct bnxt *bp) | |
3562 | { | |
3563 | int i, rc = 0, size; | |
3564 | struct bnxt_vnic_info *vnic; | |
3565 | struct pci_dev *pdev = bp->pdev; | |
3566 | int max_rings; | |
3567 | ||
3568 | for (i = 0; i < bp->nr_vnics; i++) { | |
3569 | vnic = &bp->vnic_info[i]; | |
3570 | ||
3571 | if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { | |
3572 | int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; | |
3573 | ||
3574 | if (mem_size > 0) { | |
3575 | vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); | |
3576 | if (!vnic->uc_list) { | |
3577 | rc = -ENOMEM; | |
3578 | goto out; | |
3579 | } | |
3580 | } | |
3581 | } | |
3582 | ||
3583 | if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { | |
3584 | vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; | |
3585 | vnic->mc_list = | |
3586 | dma_alloc_coherent(&pdev->dev, | |
3587 | vnic->mc_list_size, | |
3588 | &vnic->mc_list_mapping, | |
3589 | GFP_KERNEL); | |
3590 | if (!vnic->mc_list) { | |
3591 | rc = -ENOMEM; | |
3592 | goto out; | |
3593 | } | |
3594 | } | |
3595 | ||
44c6f72a MC |
3596 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
3597 | goto vnic_skip_grps; | |
3598 | ||
c0c050c5 MC |
3599 | if (vnic->flags & BNXT_VNIC_RSS_FLAG) |
3600 | max_rings = bp->rx_nr_rings; | |
3601 | else | |
3602 | max_rings = 1; | |
3603 | ||
3604 | vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); | |
3605 | if (!vnic->fw_grp_ids) { | |
3606 | rc = -ENOMEM; | |
3607 | goto out; | |
3608 | } | |
44c6f72a | 3609 | vnic_skip_grps: |
ae10ae74 MC |
3610 | if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) && |
3611 | !(vnic->flags & BNXT_VNIC_RSS_FLAG)) | |
3612 | continue; | |
3613 | ||
c0c050c5 MC |
3614 | /* Allocate rss table and hash key */ |
3615 | vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, | |
3616 | &vnic->rss_table_dma_addr, | |
3617 | GFP_KERNEL); | |
3618 | if (!vnic->rss_table) { | |
3619 | rc = -ENOMEM; | |
3620 | goto out; | |
3621 | } | |
3622 | ||
3623 | size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); | |
3624 | ||
3625 | vnic->rss_hash_key = ((void *)vnic->rss_table) + size; | |
3626 | vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; | |
3627 | } | |
3628 | return 0; | |
3629 | ||
3630 | out: | |
3631 | return rc; | |
3632 | } | |
3633 | ||
3634 | static void bnxt_free_hwrm_resources(struct bnxt *bp) | |
3635 | { | |
3636 | struct pci_dev *pdev = bp->pdev; | |
3637 | ||
a2bf74f4 VD |
3638 | if (bp->hwrm_cmd_resp_addr) { |
3639 | dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr, | |
3640 | bp->hwrm_cmd_resp_dma_addr); | |
3641 | bp->hwrm_cmd_resp_addr = NULL; | |
3642 | } | |
760b6d33 VD |
3643 | |
3644 | if (bp->hwrm_cmd_kong_resp_addr) { | |
3645 | dma_free_coherent(&pdev->dev, PAGE_SIZE, | |
3646 | bp->hwrm_cmd_kong_resp_addr, | |
3647 | bp->hwrm_cmd_kong_resp_dma_addr); | |
3648 | bp->hwrm_cmd_kong_resp_addr = NULL; | |
3649 | } | |
3650 | } | |
3651 | ||
3652 | static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp) | |
3653 | { | |
3654 | struct pci_dev *pdev = bp->pdev; | |
3655 | ||
ba642ab7 MC |
3656 | if (bp->hwrm_cmd_kong_resp_addr) |
3657 | return 0; | |
3658 | ||
760b6d33 VD |
3659 | bp->hwrm_cmd_kong_resp_addr = |
3660 | dma_alloc_coherent(&pdev->dev, PAGE_SIZE, | |
3661 | &bp->hwrm_cmd_kong_resp_dma_addr, | |
3662 | GFP_KERNEL); | |
3663 | if (!bp->hwrm_cmd_kong_resp_addr) | |
3664 | return -ENOMEM; | |
3665 | ||
3666 | return 0; | |
c0c050c5 MC |
3667 | } |
3668 | ||
3669 | static int bnxt_alloc_hwrm_resources(struct bnxt *bp) | |
3670 | { | |
3671 | struct pci_dev *pdev = bp->pdev; | |
3672 | ||
3673 | bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, | |
3674 | &bp->hwrm_cmd_resp_dma_addr, | |
3675 | GFP_KERNEL); | |
3676 | if (!bp->hwrm_cmd_resp_addr) | |
3677 | return -ENOMEM; | |
c0c050c5 MC |
3678 | |
3679 | return 0; | |
3680 | } | |
3681 | ||
e605db80 DK |
3682 | static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp) |
3683 | { | |
3684 | if (bp->hwrm_short_cmd_req_addr) { | |
3685 | struct pci_dev *pdev = bp->pdev; | |
3686 | ||
1dfddc41 | 3687 | dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, |
e605db80 DK |
3688 | bp->hwrm_short_cmd_req_addr, |
3689 | bp->hwrm_short_cmd_req_dma_addr); | |
3690 | bp->hwrm_short_cmd_req_addr = NULL; | |
3691 | } | |
3692 | } | |
3693 | ||
3694 | static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp) | |
3695 | { | |
3696 | struct pci_dev *pdev = bp->pdev; | |
3697 | ||
ba642ab7 MC |
3698 | if (bp->hwrm_short_cmd_req_addr) |
3699 | return 0; | |
3700 | ||
e605db80 | 3701 | bp->hwrm_short_cmd_req_addr = |
1dfddc41 | 3702 | dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, |
e605db80 DK |
3703 | &bp->hwrm_short_cmd_req_dma_addr, |
3704 | GFP_KERNEL); | |
3705 | if (!bp->hwrm_short_cmd_req_addr) | |
3706 | return -ENOMEM; | |
3707 | ||
3708 | return 0; | |
3709 | } | |
3710 | ||
fd3ab1c7 | 3711 | static void bnxt_free_port_stats(struct bnxt *bp) |
c0c050c5 | 3712 | { |
c0c050c5 MC |
3713 | struct pci_dev *pdev = bp->pdev; |
3714 | ||
00db3cba VV |
3715 | bp->flags &= ~BNXT_FLAG_PORT_STATS; |
3716 | bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT; | |
3717 | ||
3bdf56c4 MC |
3718 | if (bp->hw_rx_port_stats) { |
3719 | dma_free_coherent(&pdev->dev, bp->hw_port_stats_size, | |
3720 | bp->hw_rx_port_stats, | |
3721 | bp->hw_rx_port_stats_map); | |
3722 | bp->hw_rx_port_stats = NULL; | |
00db3cba VV |
3723 | } |
3724 | ||
36e53349 MC |
3725 | if (bp->hw_tx_port_stats_ext) { |
3726 | dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext), | |
3727 | bp->hw_tx_port_stats_ext, | |
3728 | bp->hw_tx_port_stats_ext_map); | |
3729 | bp->hw_tx_port_stats_ext = NULL; | |
3730 | } | |
3731 | ||
00db3cba VV |
3732 | if (bp->hw_rx_port_stats_ext) { |
3733 | dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), | |
3734 | bp->hw_rx_port_stats_ext, | |
3735 | bp->hw_rx_port_stats_ext_map); | |
3736 | bp->hw_rx_port_stats_ext = NULL; | |
3bdf56c4 | 3737 | } |
55e4398d VV |
3738 | |
3739 | if (bp->hw_pcie_stats) { | |
3740 | dma_free_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), | |
3741 | bp->hw_pcie_stats, bp->hw_pcie_stats_map); | |
3742 | bp->hw_pcie_stats = NULL; | |
3743 | } | |
fd3ab1c7 MC |
3744 | } |
3745 | ||
3746 | static void bnxt_free_ring_stats(struct bnxt *bp) | |
3747 | { | |
3748 | struct pci_dev *pdev = bp->pdev; | |
3749 | int size, i; | |
3bdf56c4 | 3750 | |
c0c050c5 MC |
3751 | if (!bp->bnapi) |
3752 | return; | |
3753 | ||
4e748506 | 3754 | size = bp->hw_ring_stats_size; |
c0c050c5 MC |
3755 | |
3756 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3757 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
3758 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
3759 | ||
3760 | if (cpr->hw_stats) { | |
3761 | dma_free_coherent(&pdev->dev, size, cpr->hw_stats, | |
3762 | cpr->hw_stats_map); | |
3763 | cpr->hw_stats = NULL; | |
3764 | } | |
3765 | } | |
3766 | } | |
3767 | ||
3768 | static int bnxt_alloc_stats(struct bnxt *bp) | |
3769 | { | |
3770 | u32 size, i; | |
3771 | struct pci_dev *pdev = bp->pdev; | |
3772 | ||
4e748506 | 3773 | size = bp->hw_ring_stats_size; |
c0c050c5 MC |
3774 | |
3775 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3776 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
3777 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
3778 | ||
3779 | cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size, | |
3780 | &cpr->hw_stats_map, | |
3781 | GFP_KERNEL); | |
3782 | if (!cpr->hw_stats) | |
3783 | return -ENOMEM; | |
3784 | ||
3785 | cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; | |
3786 | } | |
3bdf56c4 | 3787 | |
a220eabc VV |
3788 | if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700) |
3789 | return 0; | |
fd3ab1c7 | 3790 | |
a220eabc VV |
3791 | if (bp->hw_rx_port_stats) |
3792 | goto alloc_ext_stats; | |
3bdf56c4 | 3793 | |
a220eabc VV |
3794 | bp->hw_port_stats_size = sizeof(struct rx_port_stats) + |
3795 | sizeof(struct tx_port_stats) + 1024; | |
3bdf56c4 | 3796 | |
a220eabc VV |
3797 | bp->hw_rx_port_stats = |
3798 | dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size, | |
3799 | &bp->hw_rx_port_stats_map, | |
3800 | GFP_KERNEL); | |
3801 | if (!bp->hw_rx_port_stats) | |
3802 | return -ENOMEM; | |
3bdf56c4 | 3803 | |
a220eabc VV |
3804 | bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 512; |
3805 | bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map + | |
3806 | sizeof(struct rx_port_stats) + 512; | |
3807 | bp->flags |= BNXT_FLAG_PORT_STATS; | |
00db3cba | 3808 | |
fd3ab1c7 | 3809 | alloc_ext_stats: |
a220eabc VV |
3810 | /* Display extended statistics only if FW supports it */ |
3811 | if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900) | |
6154532f | 3812 | if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) |
00db3cba VV |
3813 | return 0; |
3814 | ||
a220eabc VV |
3815 | if (bp->hw_rx_port_stats_ext) |
3816 | goto alloc_tx_ext_stats; | |
fd3ab1c7 | 3817 | |
a220eabc VV |
3818 | bp->hw_rx_port_stats_ext = |
3819 | dma_alloc_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), | |
3820 | &bp->hw_rx_port_stats_ext_map, GFP_KERNEL); | |
3821 | if (!bp->hw_rx_port_stats_ext) | |
3822 | return 0; | |
00db3cba | 3823 | |
fd3ab1c7 | 3824 | alloc_tx_ext_stats: |
a220eabc | 3825 | if (bp->hw_tx_port_stats_ext) |
55e4398d | 3826 | goto alloc_pcie_stats; |
fd3ab1c7 | 3827 | |
6154532f VV |
3828 | if (bp->hwrm_spec_code >= 0x10902 || |
3829 | (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) { | |
a220eabc VV |
3830 | bp->hw_tx_port_stats_ext = |
3831 | dma_alloc_coherent(&pdev->dev, | |
3832 | sizeof(struct tx_port_stats_ext), | |
3833 | &bp->hw_tx_port_stats_ext_map, | |
3834 | GFP_KERNEL); | |
3bdf56c4 | 3835 | } |
a220eabc | 3836 | bp->flags |= BNXT_FLAG_PORT_STATS_EXT; |
55e4398d VV |
3837 | |
3838 | alloc_pcie_stats: | |
3839 | if (bp->hw_pcie_stats || | |
3840 | !(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) | |
3841 | return 0; | |
3842 | ||
3843 | bp->hw_pcie_stats = | |
3844 | dma_alloc_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), | |
3845 | &bp->hw_pcie_stats_map, GFP_KERNEL); | |
3846 | if (!bp->hw_pcie_stats) | |
3847 | return 0; | |
3848 | ||
3849 | bp->flags |= BNXT_FLAG_PCIE_STATS; | |
c0c050c5 MC |
3850 | return 0; |
3851 | } | |
3852 | ||
3853 | static void bnxt_clear_ring_indices(struct bnxt *bp) | |
3854 | { | |
3855 | int i; | |
3856 | ||
3857 | if (!bp->bnapi) | |
3858 | return; | |
3859 | ||
3860 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3861 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
3862 | struct bnxt_cp_ring_info *cpr; | |
3863 | struct bnxt_rx_ring_info *rxr; | |
3864 | struct bnxt_tx_ring_info *txr; | |
3865 | ||
3866 | if (!bnapi) | |
3867 | continue; | |
3868 | ||
3869 | cpr = &bnapi->cp_ring; | |
3870 | cpr->cp_raw_cons = 0; | |
3871 | ||
b6ab4b01 | 3872 | txr = bnapi->tx_ring; |
3b2b7d9d MC |
3873 | if (txr) { |
3874 | txr->tx_prod = 0; | |
3875 | txr->tx_cons = 0; | |
3876 | } | |
c0c050c5 | 3877 | |
b6ab4b01 | 3878 | rxr = bnapi->rx_ring; |
3b2b7d9d MC |
3879 | if (rxr) { |
3880 | rxr->rx_prod = 0; | |
3881 | rxr->rx_agg_prod = 0; | |
3882 | rxr->rx_sw_agg_prod = 0; | |
376a5b86 | 3883 | rxr->rx_next_cons = 0; |
3b2b7d9d | 3884 | } |
c0c050c5 MC |
3885 | } |
3886 | } | |
3887 | ||
3888 | static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) | |
3889 | { | |
3890 | #ifdef CONFIG_RFS_ACCEL | |
3891 | int i; | |
3892 | ||
3893 | /* Under rtnl_lock and all our NAPIs have been disabled. It's | |
3894 | * safe to delete the hash table. | |
3895 | */ | |
3896 | for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { | |
3897 | struct hlist_head *head; | |
3898 | struct hlist_node *tmp; | |
3899 | struct bnxt_ntuple_filter *fltr; | |
3900 | ||
3901 | head = &bp->ntp_fltr_hash_tbl[i]; | |
3902 | hlist_for_each_entry_safe(fltr, tmp, head, hash) { | |
3903 | hlist_del(&fltr->hash); | |
3904 | kfree(fltr); | |
3905 | } | |
3906 | } | |
3907 | if (irq_reinit) { | |
3908 | kfree(bp->ntp_fltr_bmap); | |
3909 | bp->ntp_fltr_bmap = NULL; | |
3910 | } | |
3911 | bp->ntp_fltr_count = 0; | |
3912 | #endif | |
3913 | } | |
3914 | ||
3915 | static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) | |
3916 | { | |
3917 | #ifdef CONFIG_RFS_ACCEL | |
3918 | int i, rc = 0; | |
3919 | ||
3920 | if (!(bp->flags & BNXT_FLAG_RFS)) | |
3921 | return 0; | |
3922 | ||
3923 | for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) | |
3924 | INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); | |
3925 | ||
3926 | bp->ntp_fltr_count = 0; | |
ac45bd93 DC |
3927 | bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR), |
3928 | sizeof(long), | |
c0c050c5 MC |
3929 | GFP_KERNEL); |
3930 | ||
3931 | if (!bp->ntp_fltr_bmap) | |
3932 | rc = -ENOMEM; | |
3933 | ||
3934 | return rc; | |
3935 | #else | |
3936 | return 0; | |
3937 | #endif | |
3938 | } | |
3939 | ||
3940 | static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) | |
3941 | { | |
3942 | bnxt_free_vnic_attributes(bp); | |
3943 | bnxt_free_tx_rings(bp); | |
3944 | bnxt_free_rx_rings(bp); | |
3945 | bnxt_free_cp_rings(bp); | |
3946 | bnxt_free_ntp_fltrs(bp, irq_re_init); | |
3947 | if (irq_re_init) { | |
fd3ab1c7 | 3948 | bnxt_free_ring_stats(bp); |
c0c050c5 MC |
3949 | bnxt_free_ring_grps(bp); |
3950 | bnxt_free_vnics(bp); | |
a960dec9 MC |
3951 | kfree(bp->tx_ring_map); |
3952 | bp->tx_ring_map = NULL; | |
b6ab4b01 MC |
3953 | kfree(bp->tx_ring); |
3954 | bp->tx_ring = NULL; | |
3955 | kfree(bp->rx_ring); | |
3956 | bp->rx_ring = NULL; | |
c0c050c5 MC |
3957 | kfree(bp->bnapi); |
3958 | bp->bnapi = NULL; | |
3959 | } else { | |
3960 | bnxt_clear_ring_indices(bp); | |
3961 | } | |
3962 | } | |
3963 | ||
3964 | static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) | |
3965 | { | |
01657bcd | 3966 | int i, j, rc, size, arr_size; |
c0c050c5 MC |
3967 | void *bnapi; |
3968 | ||
3969 | if (irq_re_init) { | |
3970 | /* Allocate bnapi mem pointer array and mem block for | |
3971 | * all queues | |
3972 | */ | |
3973 | arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * | |
3974 | bp->cp_nr_rings); | |
3975 | size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); | |
3976 | bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); | |
3977 | if (!bnapi) | |
3978 | return -ENOMEM; | |
3979 | ||
3980 | bp->bnapi = bnapi; | |
3981 | bnapi += arr_size; | |
3982 | for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { | |
3983 | bp->bnapi[i] = bnapi; | |
3984 | bp->bnapi[i]->index = i; | |
3985 | bp->bnapi[i]->bp = bp; | |
e38287b7 MC |
3986 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
3987 | struct bnxt_cp_ring_info *cpr = | |
3988 | &bp->bnapi[i]->cp_ring; | |
3989 | ||
3990 | cpr->cp_ring_struct.ring_mem.flags = | |
3991 | BNXT_RMEM_RING_PTE_FLAG; | |
3992 | } | |
c0c050c5 MC |
3993 | } |
3994 | ||
b6ab4b01 MC |
3995 | bp->rx_ring = kcalloc(bp->rx_nr_rings, |
3996 | sizeof(struct bnxt_rx_ring_info), | |
3997 | GFP_KERNEL); | |
3998 | if (!bp->rx_ring) | |
3999 | return -ENOMEM; | |
4000 | ||
4001 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
e38287b7 MC |
4002 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
4003 | ||
4004 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
4005 | rxr->rx_ring_struct.ring_mem.flags = | |
4006 | BNXT_RMEM_RING_PTE_FLAG; | |
4007 | rxr->rx_agg_ring_struct.ring_mem.flags = | |
4008 | BNXT_RMEM_RING_PTE_FLAG; | |
4009 | } | |
4010 | rxr->bnapi = bp->bnapi[i]; | |
b6ab4b01 MC |
4011 | bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; |
4012 | } | |
4013 | ||
4014 | bp->tx_ring = kcalloc(bp->tx_nr_rings, | |
4015 | sizeof(struct bnxt_tx_ring_info), | |
4016 | GFP_KERNEL); | |
4017 | if (!bp->tx_ring) | |
4018 | return -ENOMEM; | |
4019 | ||
a960dec9 MC |
4020 | bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16), |
4021 | GFP_KERNEL); | |
4022 | ||
4023 | if (!bp->tx_ring_map) | |
4024 | return -ENOMEM; | |
4025 | ||
01657bcd MC |
4026 | if (bp->flags & BNXT_FLAG_SHARED_RINGS) |
4027 | j = 0; | |
4028 | else | |
4029 | j = bp->rx_nr_rings; | |
4030 | ||
4031 | for (i = 0; i < bp->tx_nr_rings; i++, j++) { | |
e38287b7 MC |
4032 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
4033 | ||
4034 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
4035 | txr->tx_ring_struct.ring_mem.flags = | |
4036 | BNXT_RMEM_RING_PTE_FLAG; | |
4037 | txr->bnapi = bp->bnapi[j]; | |
4038 | bp->bnapi[j]->tx_ring = txr; | |
5f449249 | 4039 | bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i; |
38413406 | 4040 | if (i >= bp->tx_nr_rings_xdp) { |
e38287b7 | 4041 | txr->txq_index = i - bp->tx_nr_rings_xdp; |
38413406 MC |
4042 | bp->bnapi[j]->tx_int = bnxt_tx_int; |
4043 | } else { | |
fa3e93e8 | 4044 | bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP; |
38413406 MC |
4045 | bp->bnapi[j]->tx_int = bnxt_tx_int_xdp; |
4046 | } | |
b6ab4b01 MC |
4047 | } |
4048 | ||
c0c050c5 MC |
4049 | rc = bnxt_alloc_stats(bp); |
4050 | if (rc) | |
4051 | goto alloc_mem_err; | |
4052 | ||
4053 | rc = bnxt_alloc_ntp_fltrs(bp); | |
4054 | if (rc) | |
4055 | goto alloc_mem_err; | |
4056 | ||
4057 | rc = bnxt_alloc_vnics(bp); | |
4058 | if (rc) | |
4059 | goto alloc_mem_err; | |
4060 | } | |
4061 | ||
4062 | bnxt_init_ring_struct(bp); | |
4063 | ||
4064 | rc = bnxt_alloc_rx_rings(bp); | |
4065 | if (rc) | |
4066 | goto alloc_mem_err; | |
4067 | ||
4068 | rc = bnxt_alloc_tx_rings(bp); | |
4069 | if (rc) | |
4070 | goto alloc_mem_err; | |
4071 | ||
4072 | rc = bnxt_alloc_cp_rings(bp); | |
4073 | if (rc) | |
4074 | goto alloc_mem_err; | |
4075 | ||
4076 | bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | | |
4077 | BNXT_VNIC_UCAST_FLAG; | |
4078 | rc = bnxt_alloc_vnic_attributes(bp); | |
4079 | if (rc) | |
4080 | goto alloc_mem_err; | |
4081 | return 0; | |
4082 | ||
4083 | alloc_mem_err: | |
4084 | bnxt_free_mem(bp, true); | |
4085 | return rc; | |
4086 | } | |
4087 | ||
9d8bc097 MC |
4088 | static void bnxt_disable_int(struct bnxt *bp) |
4089 | { | |
4090 | int i; | |
4091 | ||
4092 | if (!bp->bnapi) | |
4093 | return; | |
4094 | ||
4095 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
4096 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
4097 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
daf1f1e7 | 4098 | struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; |
9d8bc097 | 4099 | |
daf1f1e7 | 4100 | if (ring->fw_ring_id != INVALID_HW_RING_ID) |
697197e5 | 4101 | bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); |
9d8bc097 MC |
4102 | } |
4103 | } | |
4104 | ||
e5811b8c MC |
4105 | static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n) |
4106 | { | |
4107 | struct bnxt_napi *bnapi = bp->bnapi[n]; | |
4108 | struct bnxt_cp_ring_info *cpr; | |
4109 | ||
4110 | cpr = &bnapi->cp_ring; | |
4111 | return cpr->cp_ring_struct.map_idx; | |
4112 | } | |
4113 | ||
9d8bc097 MC |
4114 | static void bnxt_disable_int_sync(struct bnxt *bp) |
4115 | { | |
4116 | int i; | |
4117 | ||
4118 | atomic_inc(&bp->intr_sem); | |
4119 | ||
4120 | bnxt_disable_int(bp); | |
e5811b8c MC |
4121 | for (i = 0; i < bp->cp_nr_rings; i++) { |
4122 | int map_idx = bnxt_cp_num_to_irq_num(bp, i); | |
4123 | ||
4124 | synchronize_irq(bp->irq_tbl[map_idx].vector); | |
4125 | } | |
9d8bc097 MC |
4126 | } |
4127 | ||
4128 | static void bnxt_enable_int(struct bnxt *bp) | |
4129 | { | |
4130 | int i; | |
4131 | ||
4132 | atomic_set(&bp->intr_sem, 0); | |
4133 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
4134 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
4135 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
4136 | ||
697197e5 | 4137 | bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons); |
9d8bc097 MC |
4138 | } |
4139 | } | |
4140 | ||
c0c050c5 MC |
4141 | void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type, |
4142 | u16 cmpl_ring, u16 target_id) | |
4143 | { | |
a8643e16 | 4144 | struct input *req = request; |
c0c050c5 | 4145 | |
a8643e16 MC |
4146 | req->req_type = cpu_to_le16(req_type); |
4147 | req->cmpl_ring = cpu_to_le16(cmpl_ring); | |
4148 | req->target_id = cpu_to_le16(target_id); | |
760b6d33 VD |
4149 | if (bnxt_kong_hwrm_message(bp, req)) |
4150 | req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); | |
4151 | else | |
4152 | req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr); | |
c0c050c5 MC |
4153 | } |
4154 | ||
d4f1420d MC |
4155 | static int bnxt_hwrm_to_stderr(u32 hwrm_err) |
4156 | { | |
4157 | switch (hwrm_err) { | |
4158 | case HWRM_ERR_CODE_SUCCESS: | |
4159 | return 0; | |
4160 | case HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED: | |
4161 | return -EACCES; | |
4162 | case HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR: | |
4163 | return -ENOSPC; | |
4164 | case HWRM_ERR_CODE_INVALID_PARAMS: | |
4165 | case HWRM_ERR_CODE_INVALID_FLAGS: | |
4166 | case HWRM_ERR_CODE_INVALID_ENABLES: | |
4167 | case HWRM_ERR_CODE_UNSUPPORTED_TLV: | |
4168 | case HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR: | |
4169 | return -EINVAL; | |
4170 | case HWRM_ERR_CODE_NO_BUFFER: | |
4171 | return -ENOMEM; | |
4172 | case HWRM_ERR_CODE_HOT_RESET_PROGRESS: | |
4173 | return -EAGAIN; | |
4174 | case HWRM_ERR_CODE_CMD_NOT_SUPPORTED: | |
4175 | return -EOPNOTSUPP; | |
4176 | default: | |
4177 | return -EIO; | |
4178 | } | |
4179 | } | |
4180 | ||
fbfbc485 MC |
4181 | static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len, |
4182 | int timeout, bool silent) | |
c0c050c5 | 4183 | { |
a11fa2be | 4184 | int i, intr_process, rc, tmo_count; |
a8643e16 | 4185 | struct input *req = msg; |
c0c050c5 | 4186 | u32 *data = msg; |
845adfe4 MC |
4187 | __le32 *resp_len; |
4188 | u8 *valid; | |
c0c050c5 MC |
4189 | u16 cp_ring_id, len = 0; |
4190 | struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr; | |
e605db80 | 4191 | u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN; |
ebd5818c | 4192 | struct hwrm_short_input short_input = {0}; |
2e9ee398 | 4193 | u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER; |
89455017 | 4194 | u8 *resp_addr = (u8 *)bp->hwrm_cmd_resp_addr; |
2e9ee398 | 4195 | u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM; |
760b6d33 | 4196 | u16 dst = BNXT_HWRM_CHNL_CHIMP; |
c0c050c5 | 4197 | |
b4fff207 MC |
4198 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) |
4199 | return -EBUSY; | |
4200 | ||
1dfddc41 MC |
4201 | if (msg_len > BNXT_HWRM_MAX_REQ_LEN) { |
4202 | if (msg_len > bp->hwrm_max_ext_req_len || | |
4203 | !bp->hwrm_short_cmd_req_addr) | |
4204 | return -EINVAL; | |
4205 | } | |
4206 | ||
760b6d33 VD |
4207 | if (bnxt_hwrm_kong_chnl(bp, req)) { |
4208 | dst = BNXT_HWRM_CHNL_KONG; | |
4209 | bar_offset = BNXT_GRCPF_REG_KONG_COMM; | |
4210 | doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER; | |
4211 | resp = bp->hwrm_cmd_kong_resp_addr; | |
4212 | resp_addr = (u8 *)bp->hwrm_cmd_kong_resp_addr; | |
4213 | } | |
4214 | ||
4215 | memset(resp, 0, PAGE_SIZE); | |
4216 | cp_ring_id = le16_to_cpu(req->cmpl_ring); | |
4217 | intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1; | |
4218 | ||
4219 | req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst)); | |
4220 | /* currently supports only one outstanding message */ | |
4221 | if (intr_process) | |
4222 | bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id); | |
4223 | ||
1dfddc41 MC |
4224 | if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || |
4225 | msg_len > BNXT_HWRM_MAX_REQ_LEN) { | |
e605db80 | 4226 | void *short_cmd_req = bp->hwrm_short_cmd_req_addr; |
1dfddc41 MC |
4227 | u16 max_msg_len; |
4228 | ||
4229 | /* Set boundary for maximum extended request length for short | |
4230 | * cmd format. If passed up from device use the max supported | |
4231 | * internal req length. | |
4232 | */ | |
4233 | max_msg_len = bp->hwrm_max_ext_req_len; | |
e605db80 DK |
4234 | |
4235 | memcpy(short_cmd_req, req, msg_len); | |
1dfddc41 MC |
4236 | if (msg_len < max_msg_len) |
4237 | memset(short_cmd_req + msg_len, 0, | |
4238 | max_msg_len - msg_len); | |
e605db80 DK |
4239 | |
4240 | short_input.req_type = req->req_type; | |
4241 | short_input.signature = | |
4242 | cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD); | |
4243 | short_input.size = cpu_to_le16(msg_len); | |
4244 | short_input.req_addr = | |
4245 | cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr); | |
4246 | ||
4247 | data = (u32 *)&short_input; | |
4248 | msg_len = sizeof(short_input); | |
4249 | ||
4250 | /* Sync memory write before updating doorbell */ | |
4251 | wmb(); | |
4252 | ||
4253 | max_req_len = BNXT_HWRM_SHORT_REQ_LEN; | |
4254 | } | |
4255 | ||
c0c050c5 | 4256 | /* Write request msg to hwrm channel */ |
2e9ee398 | 4257 | __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4); |
c0c050c5 | 4258 | |
e605db80 | 4259 | for (i = msg_len; i < max_req_len; i += 4) |
2e9ee398 | 4260 | writel(0, bp->bar0 + bar_offset + i); |
d79979a1 | 4261 | |
c0c050c5 | 4262 | /* Ring channel doorbell */ |
2e9ee398 | 4263 | writel(1, bp->bar0 + doorbell_offset); |
c0c050c5 | 4264 | |
5bedb529 MC |
4265 | if (!pci_is_enabled(bp->pdev)) |
4266 | return 0; | |
4267 | ||
ff4fe81d MC |
4268 | if (!timeout) |
4269 | timeout = DFLT_HWRM_CMD_TIMEOUT; | |
9751e8e7 AG |
4270 | /* convert timeout to usec */ |
4271 | timeout *= 1000; | |
ff4fe81d | 4272 | |
c0c050c5 | 4273 | i = 0; |
9751e8e7 AG |
4274 | /* Short timeout for the first few iterations: |
4275 | * number of loops = number of loops for short timeout + | |
4276 | * number of loops for standard timeout. | |
4277 | */ | |
4278 | tmo_count = HWRM_SHORT_TIMEOUT_COUNTER; | |
4279 | timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER; | |
4280 | tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT); | |
89455017 VD |
4281 | resp_len = (__le32 *)(resp_addr + HWRM_RESP_LEN_OFFSET); |
4282 | ||
c0c050c5 | 4283 | if (intr_process) { |
fc718bb2 VD |
4284 | u16 seq_id = bp->hwrm_intr_seq_id; |
4285 | ||
c0c050c5 | 4286 | /* Wait until hwrm response cmpl interrupt is processed */ |
fc718bb2 | 4287 | while (bp->hwrm_intr_seq_id != (u16)~seq_id && |
a11fa2be | 4288 | i++ < tmo_count) { |
642aebde PC |
4289 | /* Abort the wait for completion if the FW health |
4290 | * check has failed. | |
4291 | */ | |
4292 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) | |
4293 | return -EBUSY; | |
9751e8e7 AG |
4294 | /* on first few passes, just barely sleep */ |
4295 | if (i < HWRM_SHORT_TIMEOUT_COUNTER) | |
4296 | usleep_range(HWRM_SHORT_MIN_TIMEOUT, | |
4297 | HWRM_SHORT_MAX_TIMEOUT); | |
4298 | else | |
4299 | usleep_range(HWRM_MIN_TIMEOUT, | |
4300 | HWRM_MAX_TIMEOUT); | |
c0c050c5 MC |
4301 | } |
4302 | ||
fc718bb2 | 4303 | if (bp->hwrm_intr_seq_id != (u16)~seq_id) { |
5bedb529 MC |
4304 | if (!silent) |
4305 | netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n", | |
4306 | le16_to_cpu(req->req_type)); | |
a935cb7e | 4307 | return -EBUSY; |
c0c050c5 | 4308 | } |
845adfe4 MC |
4309 | len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> |
4310 | HWRM_RESP_LEN_SFT; | |
89455017 | 4311 | valid = resp_addr + len - 1; |
c0c050c5 | 4312 | } else { |
cc559c1a MC |
4313 | int j; |
4314 | ||
c0c050c5 | 4315 | /* Check if response len is updated */ |
a11fa2be | 4316 | for (i = 0; i < tmo_count; i++) { |
642aebde PC |
4317 | /* Abort the wait for completion if the FW health |
4318 | * check has failed. | |
4319 | */ | |
4320 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) | |
4321 | return -EBUSY; | |
c0c050c5 MC |
4322 | len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> |
4323 | HWRM_RESP_LEN_SFT; | |
4324 | if (len) | |
4325 | break; | |
9751e8e7 | 4326 | /* on first few passes, just barely sleep */ |
67681d02 | 4327 | if (i < HWRM_SHORT_TIMEOUT_COUNTER) |
9751e8e7 AG |
4328 | usleep_range(HWRM_SHORT_MIN_TIMEOUT, |
4329 | HWRM_SHORT_MAX_TIMEOUT); | |
4330 | else | |
4331 | usleep_range(HWRM_MIN_TIMEOUT, | |
4332 | HWRM_MAX_TIMEOUT); | |
c0c050c5 MC |
4333 | } |
4334 | ||
a11fa2be | 4335 | if (i >= tmo_count) { |
5bedb529 MC |
4336 | if (!silent) |
4337 | netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n", | |
4338 | HWRM_TOTAL_TIMEOUT(i), | |
4339 | le16_to_cpu(req->req_type), | |
4340 | le16_to_cpu(req->seq_id), len); | |
a935cb7e | 4341 | return -EBUSY; |
c0c050c5 MC |
4342 | } |
4343 | ||
845adfe4 | 4344 | /* Last byte of resp contains valid bit */ |
89455017 | 4345 | valid = resp_addr + len - 1; |
cc559c1a | 4346 | for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) { |
845adfe4 MC |
4347 | /* make sure we read from updated DMA memory */ |
4348 | dma_rmb(); | |
4349 | if (*valid) | |
c0c050c5 | 4350 | break; |
0000b81a | 4351 | usleep_range(1, 5); |
c0c050c5 MC |
4352 | } |
4353 | ||
cc559c1a | 4354 | if (j >= HWRM_VALID_BIT_DELAY_USEC) { |
5bedb529 MC |
4355 | if (!silent) |
4356 | netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n", | |
4357 | HWRM_TOTAL_TIMEOUT(i), | |
4358 | le16_to_cpu(req->req_type), | |
4359 | le16_to_cpu(req->seq_id), len, | |
4360 | *valid); | |
a935cb7e | 4361 | return -EBUSY; |
c0c050c5 MC |
4362 | } |
4363 | } | |
4364 | ||
845adfe4 MC |
4365 | /* Zero valid bit for compatibility. Valid bit in an older spec |
4366 | * may become a new field in a newer spec. We must make sure that | |
4367 | * a new field not implemented by old spec will read zero. | |
4368 | */ | |
4369 | *valid = 0; | |
c0c050c5 | 4370 | rc = le16_to_cpu(resp->error_code); |
fbfbc485 | 4371 | if (rc && !silent) |
c0c050c5 MC |
4372 | netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n", |
4373 | le16_to_cpu(resp->req_type), | |
4374 | le16_to_cpu(resp->seq_id), rc); | |
d4f1420d | 4375 | return bnxt_hwrm_to_stderr(rc); |
fbfbc485 MC |
4376 | } |
4377 | ||
4378 | int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) | |
4379 | { | |
4380 | return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false); | |
c0c050c5 MC |
4381 | } |
4382 | ||
cc72f3b1 MC |
4383 | int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, |
4384 | int timeout) | |
4385 | { | |
4386 | return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); | |
4387 | } | |
4388 | ||
c0c050c5 MC |
4389 | int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) |
4390 | { | |
4391 | int rc; | |
4392 | ||
4393 | mutex_lock(&bp->hwrm_cmd_lock); | |
4394 | rc = _hwrm_send_message(bp, msg, msg_len, timeout); | |
4395 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4396 | return rc; | |
4397 | } | |
4398 | ||
90e20921 MC |
4399 | int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, |
4400 | int timeout) | |
4401 | { | |
4402 | int rc; | |
4403 | ||
4404 | mutex_lock(&bp->hwrm_cmd_lock); | |
4405 | rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); | |
4406 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4407 | return rc; | |
4408 | } | |
4409 | ||
2e882468 VV |
4410 | int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, int bmap_size, |
4411 | bool async_only) | |
c0c050c5 | 4412 | { |
2e882468 | 4413 | struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr; |
c0c050c5 | 4414 | struct hwrm_func_drv_rgtr_input req = {0}; |
25be8623 MC |
4415 | DECLARE_BITMAP(async_events_bmap, 256); |
4416 | u32 *events = (u32 *)async_events_bmap; | |
acfb50e4 | 4417 | u32 flags; |
2e882468 | 4418 | int rc, i; |
a1653b13 MC |
4419 | |
4420 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); | |
4421 | ||
4422 | req.enables = | |
4423 | cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | | |
2e882468 VV |
4424 | FUNC_DRV_RGTR_REQ_ENABLES_VER | |
4425 | FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); | |
a1653b13 | 4426 | |
11f15ed3 | 4427 | req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX); |
8280b38e VV |
4428 | flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE; |
4429 | if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) | |
4430 | flags |= FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT; | |
acfb50e4 | 4431 | if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) |
e633a329 VV |
4432 | flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT | |
4433 | FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT; | |
acfb50e4 | 4434 | req.flags = cpu_to_le32(flags); |
d4f52de0 MC |
4435 | req.ver_maj_8b = DRV_VER_MAJ; |
4436 | req.ver_min_8b = DRV_VER_MIN; | |
4437 | req.ver_upd_8b = DRV_VER_UPD; | |
4438 | req.ver_maj = cpu_to_le16(DRV_VER_MAJ); | |
4439 | req.ver_min = cpu_to_le16(DRV_VER_MIN); | |
4440 | req.ver_upd = cpu_to_le16(DRV_VER_UPD); | |
c0c050c5 MC |
4441 | |
4442 | if (BNXT_PF(bp)) { | |
9b0436c3 | 4443 | u32 data[8]; |
a1653b13 | 4444 | int i; |
c0c050c5 | 4445 | |
9b0436c3 MC |
4446 | memset(data, 0, sizeof(data)); |
4447 | for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) { | |
4448 | u16 cmd = bnxt_vf_req_snif[i]; | |
4449 | unsigned int bit, idx; | |
4450 | ||
4451 | idx = cmd / 32; | |
4452 | bit = cmd % 32; | |
4453 | data[idx] |= 1 << bit; | |
4454 | } | |
c0c050c5 | 4455 | |
de68f5de MC |
4456 | for (i = 0; i < 8; i++) |
4457 | req.vf_req_fwd[i] = cpu_to_le32(data[i]); | |
4458 | ||
c0c050c5 MC |
4459 | req.enables |= |
4460 | cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); | |
4461 | } | |
4462 | ||
abd43a13 VD |
4463 | if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE) |
4464 | req.flags |= cpu_to_le32( | |
4465 | FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE); | |
4466 | ||
2e882468 VV |
4467 | memset(async_events_bmap, 0, sizeof(async_events_bmap)); |
4468 | for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) { | |
4469 | u16 event_id = bnxt_async_events_arr[i]; | |
4470 | ||
4471 | if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY && | |
4472 | !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) | |
4473 | continue; | |
4474 | __set_bit(bnxt_async_events_arr[i], async_events_bmap); | |
4475 | } | |
4476 | if (bmap && bmap_size) { | |
4477 | for (i = 0; i < bmap_size; i++) { | |
4478 | if (test_bit(i, bmap)) | |
4479 | __set_bit(i, async_events_bmap); | |
4480 | } | |
4481 | } | |
4482 | for (i = 0; i < 8; i++) | |
4483 | req.async_event_fwd[i] |= cpu_to_le32(events[i]); | |
4484 | ||
4485 | if (async_only) | |
4486 | req.enables = | |
4487 | cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); | |
4488 | ||
25e1acd6 MC |
4489 | mutex_lock(&bp->hwrm_cmd_lock); |
4490 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
bdb38602 VV |
4491 | if (!rc) { |
4492 | set_bit(BNXT_STATE_DRV_REGISTERED, &bp->state); | |
4493 | if (resp->flags & | |
4494 | cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED)) | |
4495 | bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE; | |
4496 | } | |
25e1acd6 MC |
4497 | mutex_unlock(&bp->hwrm_cmd_lock); |
4498 | return rc; | |
c0c050c5 MC |
4499 | } |
4500 | ||
be58a0da JH |
4501 | static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) |
4502 | { | |
4503 | struct hwrm_func_drv_unrgtr_input req = {0}; | |
4504 | ||
bdb38602 VV |
4505 | if (!test_and_clear_bit(BNXT_STATE_DRV_REGISTERED, &bp->state)) |
4506 | return 0; | |
4507 | ||
be58a0da JH |
4508 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1); |
4509 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4510 | } | |
4511 | ||
c0c050c5 MC |
4512 | static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) |
4513 | { | |
4514 | u32 rc = 0; | |
4515 | struct hwrm_tunnel_dst_port_free_input req = {0}; | |
4516 | ||
4517 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1); | |
4518 | req.tunnel_type = tunnel_type; | |
4519 | ||
4520 | switch (tunnel_type) { | |
4521 | case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: | |
4522 | req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id; | |
4523 | break; | |
4524 | case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: | |
4525 | req.tunnel_dst_port_id = bp->nge_fw_dst_port_id; | |
4526 | break; | |
4527 | default: | |
4528 | break; | |
4529 | } | |
4530 | ||
4531 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4532 | if (rc) | |
4533 | netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", | |
4534 | rc); | |
4535 | return rc; | |
4536 | } | |
4537 | ||
4538 | static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, | |
4539 | u8 tunnel_type) | |
4540 | { | |
4541 | u32 rc = 0; | |
4542 | struct hwrm_tunnel_dst_port_alloc_input req = {0}; | |
4543 | struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
4544 | ||
4545 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1); | |
4546 | ||
4547 | req.tunnel_type = tunnel_type; | |
4548 | req.tunnel_dst_port_val = port; | |
4549 | ||
4550 | mutex_lock(&bp->hwrm_cmd_lock); | |
4551 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4552 | if (rc) { | |
4553 | netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", | |
4554 | rc); | |
4555 | goto err_out; | |
4556 | } | |
4557 | ||
57aac71b CJ |
4558 | switch (tunnel_type) { |
4559 | case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN: | |
c0c050c5 | 4560 | bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id; |
57aac71b CJ |
4561 | break; |
4562 | case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE: | |
c0c050c5 | 4563 | bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id; |
57aac71b CJ |
4564 | break; |
4565 | default: | |
4566 | break; | |
4567 | } | |
4568 | ||
c0c050c5 MC |
4569 | err_out: |
4570 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4571 | return rc; | |
4572 | } | |
4573 | ||
4574 | static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) | |
4575 | { | |
4576 | struct hwrm_cfa_l2_set_rx_mask_input req = {0}; | |
4577 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; | |
4578 | ||
4579 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1); | |
c193554e | 4580 | req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); |
c0c050c5 MC |
4581 | |
4582 | req.num_mc_entries = cpu_to_le32(vnic->mc_list_count); | |
4583 | req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); | |
4584 | req.mask = cpu_to_le32(vnic->rx_mask); | |
4585 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4586 | } | |
4587 | ||
4588 | #ifdef CONFIG_RFS_ACCEL | |
4589 | static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, | |
4590 | struct bnxt_ntuple_filter *fltr) | |
4591 | { | |
4592 | struct hwrm_cfa_ntuple_filter_free_input req = {0}; | |
4593 | ||
4594 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1); | |
4595 | req.ntuple_filter_id = fltr->filter_id; | |
4596 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4597 | } | |
4598 | ||
4599 | #define BNXT_NTP_FLTR_FLAGS \ | |
4600 | (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ | |
4601 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ | |
4602 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ | |
4603 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ | |
4604 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ | |
4605 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ | |
4606 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ | |
4607 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ | |
4608 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ | |
4609 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ | |
4610 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ | |
4611 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ | |
4612 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ | |
c193554e | 4613 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) |
c0c050c5 | 4614 | |
61aad724 MC |
4615 | #define BNXT_NTP_TUNNEL_FLTR_FLAG \ |
4616 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE | |
4617 | ||
c0c050c5 MC |
4618 | static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, |
4619 | struct bnxt_ntuple_filter *fltr) | |
4620 | { | |
c0c050c5 | 4621 | struct hwrm_cfa_ntuple_filter_alloc_input req = {0}; |
5c209fc8 | 4622 | struct hwrm_cfa_ntuple_filter_alloc_output *resp; |
c0c050c5 | 4623 | struct flow_keys *keys = &fltr->fkeys; |
ac33906c | 4624 | struct bnxt_vnic_info *vnic; |
41136ab3 | 4625 | u32 flags = 0; |
5c209fc8 | 4626 | int rc = 0; |
c0c050c5 MC |
4627 | |
4628 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1); | |
a54c4d74 | 4629 | req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx]; |
c0c050c5 | 4630 | |
41136ab3 MC |
4631 | if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) { |
4632 | flags = CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX; | |
4633 | req.dst_id = cpu_to_le16(fltr->rxq); | |
ac33906c MC |
4634 | } else { |
4635 | vnic = &bp->vnic_info[fltr->rxq + 1]; | |
41136ab3 | 4636 | req.dst_id = cpu_to_le16(vnic->fw_vnic_id); |
ac33906c | 4637 | } |
41136ab3 MC |
4638 | req.flags = cpu_to_le32(flags); |
4639 | req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS); | |
c0c050c5 MC |
4640 | |
4641 | req.ethertype = htons(ETH_P_IP); | |
4642 | memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN); | |
c193554e | 4643 | req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; |
c0c050c5 MC |
4644 | req.ip_protocol = keys->basic.ip_proto; |
4645 | ||
dda0e746 MC |
4646 | if (keys->basic.n_proto == htons(ETH_P_IPV6)) { |
4647 | int i; | |
4648 | ||
4649 | req.ethertype = htons(ETH_P_IPV6); | |
4650 | req.ip_addr_type = | |
4651 | CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6; | |
4652 | *(struct in6_addr *)&req.src_ipaddr[0] = | |
4653 | keys->addrs.v6addrs.src; | |
4654 | *(struct in6_addr *)&req.dst_ipaddr[0] = | |
4655 | keys->addrs.v6addrs.dst; | |
4656 | for (i = 0; i < 4; i++) { | |
4657 | req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff); | |
4658 | req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff); | |
4659 | } | |
4660 | } else { | |
4661 | req.src_ipaddr[0] = keys->addrs.v4addrs.src; | |
4662 | req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); | |
4663 | req.dst_ipaddr[0] = keys->addrs.v4addrs.dst; | |
4664 | req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); | |
4665 | } | |
61aad724 MC |
4666 | if (keys->control.flags & FLOW_DIS_ENCAPSULATION) { |
4667 | req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG); | |
4668 | req.tunnel_type = | |
4669 | CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL; | |
4670 | } | |
c0c050c5 MC |
4671 | |
4672 | req.src_port = keys->ports.src; | |
4673 | req.src_port_mask = cpu_to_be16(0xffff); | |
4674 | req.dst_port = keys->ports.dst; | |
4675 | req.dst_port_mask = cpu_to_be16(0xffff); | |
4676 | ||
c0c050c5 MC |
4677 | mutex_lock(&bp->hwrm_cmd_lock); |
4678 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5c209fc8 VD |
4679 | if (!rc) { |
4680 | resp = bnxt_get_hwrm_resp_addr(bp, &req); | |
c0c050c5 | 4681 | fltr->filter_id = resp->ntuple_filter_id; |
5c209fc8 | 4682 | } |
c0c050c5 MC |
4683 | mutex_unlock(&bp->hwrm_cmd_lock); |
4684 | return rc; | |
4685 | } | |
4686 | #endif | |
4687 | ||
4688 | static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, | |
4689 | u8 *mac_addr) | |
4690 | { | |
4691 | u32 rc = 0; | |
4692 | struct hwrm_cfa_l2_filter_alloc_input req = {0}; | |
4693 | struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
4694 | ||
4695 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1); | |
dc52c6c7 PS |
4696 | req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX); |
4697 | if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) | |
4698 | req.flags |= | |
4699 | cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); | |
c193554e | 4700 | req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); |
c0c050c5 MC |
4701 | req.enables = |
4702 | cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | | |
c193554e | 4703 | CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | |
c0c050c5 MC |
4704 | CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); |
4705 | memcpy(req.l2_addr, mac_addr, ETH_ALEN); | |
4706 | req.l2_addr_mask[0] = 0xff; | |
4707 | req.l2_addr_mask[1] = 0xff; | |
4708 | req.l2_addr_mask[2] = 0xff; | |
4709 | req.l2_addr_mask[3] = 0xff; | |
4710 | req.l2_addr_mask[4] = 0xff; | |
4711 | req.l2_addr_mask[5] = 0xff; | |
4712 | ||
4713 | mutex_lock(&bp->hwrm_cmd_lock); | |
4714 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4715 | if (!rc) | |
4716 | bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = | |
4717 | resp->l2_filter_id; | |
4718 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4719 | return rc; | |
4720 | } | |
4721 | ||
4722 | static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) | |
4723 | { | |
4724 | u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ | |
4725 | int rc = 0; | |
4726 | ||
4727 | /* Any associated ntuple filters will also be cleared by firmware. */ | |
4728 | mutex_lock(&bp->hwrm_cmd_lock); | |
4729 | for (i = 0; i < num_of_vnics; i++) { | |
4730 | struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; | |
4731 | ||
4732 | for (j = 0; j < vnic->uc_filter_count; j++) { | |
4733 | struct hwrm_cfa_l2_filter_free_input req = {0}; | |
4734 | ||
4735 | bnxt_hwrm_cmd_hdr_init(bp, &req, | |
4736 | HWRM_CFA_L2_FILTER_FREE, -1, -1); | |
4737 | ||
4738 | req.l2_filter_id = vnic->fw_l2_filter_id[j]; | |
4739 | ||
4740 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
4741 | HWRM_CMD_TIMEOUT); | |
4742 | } | |
4743 | vnic->uc_filter_count = 0; | |
4744 | } | |
4745 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4746 | ||
4747 | return rc; | |
4748 | } | |
4749 | ||
4750 | static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) | |
4751 | { | |
4752 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; | |
79632e9b | 4753 | u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX; |
c0c050c5 MC |
4754 | struct hwrm_vnic_tpa_cfg_input req = {0}; |
4755 | ||
3c4fe80b MC |
4756 | if (vnic->fw_vnic_id == INVALID_HW_RING_ID) |
4757 | return 0; | |
4758 | ||
c0c050c5 MC |
4759 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1); |
4760 | ||
4761 | if (tpa_flags) { | |
4762 | u16 mss = bp->dev->mtu - 40; | |
4763 | u32 nsegs, n, segs = 0, flags; | |
4764 | ||
4765 | flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | | |
4766 | VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | | |
4767 | VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | | |
4768 | VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | | |
4769 | VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; | |
4770 | if (tpa_flags & BNXT_FLAG_GRO) | |
4771 | flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; | |
4772 | ||
4773 | req.flags = cpu_to_le32(flags); | |
4774 | ||
4775 | req.enables = | |
4776 | cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | | |
c193554e MC |
4777 | VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | |
4778 | VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); | |
c0c050c5 MC |
4779 | |
4780 | /* Number of segs are log2 units, and first packet is not | |
4781 | * included as part of this units. | |
4782 | */ | |
2839f28b MC |
4783 | if (mss <= BNXT_RX_PAGE_SIZE) { |
4784 | n = BNXT_RX_PAGE_SIZE / mss; | |
c0c050c5 MC |
4785 | nsegs = (MAX_SKB_FRAGS - 1) * n; |
4786 | } else { | |
2839f28b MC |
4787 | n = mss / BNXT_RX_PAGE_SIZE; |
4788 | if (mss & (BNXT_RX_PAGE_SIZE - 1)) | |
c0c050c5 MC |
4789 | n++; |
4790 | nsegs = (MAX_SKB_FRAGS - n) / n; | |
4791 | } | |
4792 | ||
79632e9b MC |
4793 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
4794 | segs = MAX_TPA_SEGS_P5; | |
4795 | max_aggs = bp->max_tpa; | |
4796 | } else { | |
4797 | segs = ilog2(nsegs); | |
4798 | } | |
c0c050c5 | 4799 | req.max_agg_segs = cpu_to_le16(segs); |
79632e9b | 4800 | req.max_aggs = cpu_to_le16(max_aggs); |
c193554e MC |
4801 | |
4802 | req.min_agg_len = cpu_to_le32(512); | |
c0c050c5 MC |
4803 | } |
4804 | req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); | |
4805 | ||
4806 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4807 | } | |
4808 | ||
2c61d211 MC |
4809 | static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring) |
4810 | { | |
4811 | struct bnxt_ring_grp_info *grp_info; | |
4812 | ||
4813 | grp_info = &bp->grp_info[ring->grp_idx]; | |
4814 | return grp_info->cp_fw_ring_id; | |
4815 | } | |
4816 | ||
4817 | static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) | |
4818 | { | |
4819 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
4820 | struct bnxt_napi *bnapi = rxr->bnapi; | |
4821 | struct bnxt_cp_ring_info *cpr; | |
4822 | ||
4823 | cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL]; | |
4824 | return cpr->cp_ring_struct.fw_ring_id; | |
4825 | } else { | |
4826 | return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct); | |
4827 | } | |
4828 | } | |
4829 | ||
4830 | static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr) | |
4831 | { | |
4832 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
4833 | struct bnxt_napi *bnapi = txr->bnapi; | |
4834 | struct bnxt_cp_ring_info *cpr; | |
4835 | ||
4836 | cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL]; | |
4837 | return cpr->cp_ring_struct.fw_ring_id; | |
4838 | } else { | |
4839 | return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct); | |
4840 | } | |
4841 | } | |
4842 | ||
c0c050c5 MC |
4843 | static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) |
4844 | { | |
4845 | u32 i, j, max_rings; | |
4846 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; | |
4847 | struct hwrm_vnic_rss_cfg_input req = {0}; | |
4848 | ||
7b3af4f7 MC |
4849 | if ((bp->flags & BNXT_FLAG_CHIP_P5) || |
4850 | vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID) | |
c0c050c5 MC |
4851 | return 0; |
4852 | ||
4853 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); | |
4854 | if (set_rss) { | |
87da7f79 | 4855 | req.hash_type = cpu_to_le32(bp->rss_hash_cfg); |
50f011b6 | 4856 | req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; |
dc52c6c7 PS |
4857 | if (vnic->flags & BNXT_VNIC_RSS_FLAG) { |
4858 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) | |
4859 | max_rings = bp->rx_nr_rings - 1; | |
4860 | else | |
4861 | max_rings = bp->rx_nr_rings; | |
4862 | } else { | |
c0c050c5 | 4863 | max_rings = 1; |
dc52c6c7 | 4864 | } |
c0c050c5 MC |
4865 | |
4866 | /* Fill the RSS indirection table with ring group ids */ | |
4867 | for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) { | |
4868 | if (j == max_rings) | |
4869 | j = 0; | |
4870 | vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); | |
4871 | } | |
4872 | ||
4873 | req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); | |
4874 | req.hash_key_tbl_addr = | |
4875 | cpu_to_le64(vnic->rss_hash_key_dma_addr); | |
4876 | } | |
94ce9caa | 4877 | req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); |
c0c050c5 MC |
4878 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
4879 | } | |
4880 | ||
7b3af4f7 MC |
4881 | static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss) |
4882 | { | |
4883 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; | |
4884 | u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings; | |
4885 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; | |
4886 | struct hwrm_vnic_rss_cfg_input req = {0}; | |
4887 | ||
4888 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); | |
4889 | req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); | |
4890 | if (!set_rss) { | |
4891 | hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4892 | return 0; | |
4893 | } | |
4894 | req.hash_type = cpu_to_le32(bp->rss_hash_cfg); | |
4895 | req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; | |
4896 | req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); | |
4897 | req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr); | |
4898 | nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64); | |
4899 | for (i = 0, k = 0; i < nr_ctxs; i++) { | |
4900 | __le16 *ring_tbl = vnic->rss_table; | |
4901 | int rc; | |
4902 | ||
4903 | req.ring_table_pair_index = i; | |
4904 | req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]); | |
4905 | for (j = 0; j < 64; j++) { | |
4906 | u16 ring_id; | |
4907 | ||
4908 | ring_id = rxr->rx_ring_struct.fw_ring_id; | |
4909 | *ring_tbl++ = cpu_to_le16(ring_id); | |
4910 | ring_id = bnxt_cp_ring_for_rx(bp, rxr); | |
4911 | *ring_tbl++ = cpu_to_le16(ring_id); | |
4912 | rxr++; | |
4913 | k++; | |
4914 | if (k == max_rings) { | |
4915 | k = 0; | |
4916 | rxr = &bp->rx_ring[0]; | |
4917 | } | |
4918 | } | |
4919 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4920 | if (rc) | |
d4f1420d | 4921 | return rc; |
7b3af4f7 MC |
4922 | } |
4923 | return 0; | |
4924 | } | |
4925 | ||
c0c050c5 MC |
4926 | static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) |
4927 | { | |
4928 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; | |
4929 | struct hwrm_vnic_plcmodes_cfg_input req = {0}; | |
4930 | ||
4931 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1); | |
4932 | req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT | | |
4933 | VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | | |
4934 | VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); | |
4935 | req.enables = | |
4936 | cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID | | |
4937 | VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); | |
4938 | /* thresholds not implemented in firmware yet */ | |
4939 | req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); | |
4940 | req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh); | |
4941 | req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); | |
4942 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4943 | } | |
4944 | ||
94ce9caa PS |
4945 | static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id, |
4946 | u16 ctx_idx) | |
c0c050c5 MC |
4947 | { |
4948 | struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0}; | |
4949 | ||
4950 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1); | |
4951 | req.rss_cos_lb_ctx_id = | |
94ce9caa | 4952 | cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]); |
c0c050c5 MC |
4953 | |
4954 | hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
94ce9caa | 4955 | bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID; |
c0c050c5 MC |
4956 | } |
4957 | ||
4958 | static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) | |
4959 | { | |
94ce9caa | 4960 | int i, j; |
c0c050c5 MC |
4961 | |
4962 | for (i = 0; i < bp->nr_vnics; i++) { | |
4963 | struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; | |
4964 | ||
94ce9caa PS |
4965 | for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) { |
4966 | if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID) | |
4967 | bnxt_hwrm_vnic_ctx_free_one(bp, i, j); | |
4968 | } | |
c0c050c5 MC |
4969 | } |
4970 | bp->rsscos_nr_ctxs = 0; | |
4971 | } | |
4972 | ||
94ce9caa | 4973 | static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx) |
c0c050c5 MC |
4974 | { |
4975 | int rc; | |
4976 | struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; | |
4977 | struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = | |
4978 | bp->hwrm_cmd_resp_addr; | |
4979 | ||
4980 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1, | |
4981 | -1); | |
4982 | ||
4983 | mutex_lock(&bp->hwrm_cmd_lock); | |
4984 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4985 | if (!rc) | |
94ce9caa | 4986 | bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = |
c0c050c5 MC |
4987 | le16_to_cpu(resp->rss_cos_lb_ctx_id); |
4988 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4989 | ||
4990 | return rc; | |
4991 | } | |
4992 | ||
abe93ad2 MC |
4993 | static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp) |
4994 | { | |
4995 | if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP) | |
4996 | return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE; | |
4997 | return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE; | |
4998 | } | |
4999 | ||
a588e458 | 5000 | int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) |
c0c050c5 | 5001 | { |
b81a90d3 | 5002 | unsigned int ring = 0, grp_idx; |
c0c050c5 MC |
5003 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
5004 | struct hwrm_vnic_cfg_input req = {0}; | |
cf6645f8 | 5005 | u16 def_vlan = 0; |
c0c050c5 MC |
5006 | |
5007 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1); | |
dc52c6c7 | 5008 | |
7b3af4f7 MC |
5009 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5010 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; | |
5011 | ||
5012 | req.default_rx_ring_id = | |
5013 | cpu_to_le16(rxr->rx_ring_struct.fw_ring_id); | |
5014 | req.default_cmpl_ring_id = | |
5015 | cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr)); | |
5016 | req.enables = | |
5017 | cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID | | |
5018 | VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID); | |
5019 | goto vnic_mru; | |
5020 | } | |
dc52c6c7 | 5021 | req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP); |
c0c050c5 | 5022 | /* Only RSS support for now TBD: COS & LB */ |
dc52c6c7 PS |
5023 | if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) { |
5024 | req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); | |
5025 | req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | | |
5026 | VNIC_CFG_REQ_ENABLES_MRU); | |
ae10ae74 MC |
5027 | } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) { |
5028 | req.rss_rule = | |
5029 | cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]); | |
5030 | req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | | |
5031 | VNIC_CFG_REQ_ENABLES_MRU); | |
5032 | req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE); | |
dc52c6c7 PS |
5033 | } else { |
5034 | req.rss_rule = cpu_to_le16(0xffff); | |
5035 | } | |
94ce9caa | 5036 | |
dc52c6c7 PS |
5037 | if (BNXT_CHIP_TYPE_NITRO_A0(bp) && |
5038 | (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) { | |
94ce9caa PS |
5039 | req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]); |
5040 | req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE); | |
5041 | } else { | |
5042 | req.cos_rule = cpu_to_le16(0xffff); | |
5043 | } | |
5044 | ||
c0c050c5 | 5045 | if (vnic->flags & BNXT_VNIC_RSS_FLAG) |
b81a90d3 | 5046 | ring = 0; |
c0c050c5 | 5047 | else if (vnic->flags & BNXT_VNIC_RFS_FLAG) |
b81a90d3 | 5048 | ring = vnic_id - 1; |
76595193 PS |
5049 | else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp)) |
5050 | ring = bp->rx_nr_rings - 1; | |
c0c050c5 | 5051 | |
b81a90d3 | 5052 | grp_idx = bp->rx_ring[ring].bnapi->index; |
c0c050c5 | 5053 | req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); |
c0c050c5 | 5054 | req.lb_rule = cpu_to_le16(0xffff); |
7b3af4f7 | 5055 | vnic_mru: |
c0c050c5 MC |
5056 | req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + |
5057 | VLAN_HLEN); | |
5058 | ||
7b3af4f7 | 5059 | req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); |
cf6645f8 MC |
5060 | #ifdef CONFIG_BNXT_SRIOV |
5061 | if (BNXT_VF(bp)) | |
5062 | def_vlan = bp->vf.vlan; | |
5063 | #endif | |
5064 | if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan) | |
c0c050c5 | 5065 | req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); |
a588e458 | 5066 | if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) |
abe93ad2 | 5067 | req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp)); |
c0c050c5 MC |
5068 | |
5069 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5070 | } | |
5071 | ||
5072 | static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) | |
5073 | { | |
5074 | u32 rc = 0; | |
5075 | ||
5076 | if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { | |
5077 | struct hwrm_vnic_free_input req = {0}; | |
5078 | ||
5079 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1); | |
5080 | req.vnic_id = | |
5081 | cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); | |
5082 | ||
5083 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
c0c050c5 MC |
5084 | bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; |
5085 | } | |
5086 | return rc; | |
5087 | } | |
5088 | ||
5089 | static void bnxt_hwrm_vnic_free(struct bnxt *bp) | |
5090 | { | |
5091 | u16 i; | |
5092 | ||
5093 | for (i = 0; i < bp->nr_vnics; i++) | |
5094 | bnxt_hwrm_vnic_free_one(bp, i); | |
5095 | } | |
5096 | ||
b81a90d3 MC |
5097 | static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, |
5098 | unsigned int start_rx_ring_idx, | |
5099 | unsigned int nr_rings) | |
c0c050c5 | 5100 | { |
b81a90d3 MC |
5101 | int rc = 0; |
5102 | unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; | |
c0c050c5 MC |
5103 | struct hwrm_vnic_alloc_input req = {0}; |
5104 | struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
44c6f72a MC |
5105 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
5106 | ||
5107 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
5108 | goto vnic_no_ring_grps; | |
c0c050c5 MC |
5109 | |
5110 | /* map ring groups to this vnic */ | |
b81a90d3 MC |
5111 | for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { |
5112 | grp_idx = bp->rx_ring[i].bnapi->index; | |
5113 | if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { | |
c0c050c5 | 5114 | netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", |
b81a90d3 | 5115 | j, nr_rings); |
c0c050c5 MC |
5116 | break; |
5117 | } | |
44c6f72a | 5118 | vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id; |
c0c050c5 MC |
5119 | } |
5120 | ||
44c6f72a MC |
5121 | vnic_no_ring_grps: |
5122 | for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++) | |
5123 | vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID; | |
c0c050c5 MC |
5124 | if (vnic_id == 0) |
5125 | req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); | |
5126 | ||
5127 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1); | |
5128 | ||
5129 | mutex_lock(&bp->hwrm_cmd_lock); | |
5130 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5131 | if (!rc) | |
44c6f72a | 5132 | vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id); |
c0c050c5 MC |
5133 | mutex_unlock(&bp->hwrm_cmd_lock); |
5134 | return rc; | |
5135 | } | |
5136 | ||
8fdefd63 MC |
5137 | static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) |
5138 | { | |
5139 | struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
5140 | struct hwrm_vnic_qcaps_input req = {0}; | |
5141 | int rc; | |
5142 | ||
fbbdbc64 | 5143 | bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats); |
ba642ab7 | 5144 | bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP); |
8fdefd63 MC |
5145 | if (bp->hwrm_spec_code < 0x10600) |
5146 | return 0; | |
5147 | ||
5148 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1); | |
5149 | mutex_lock(&bp->hwrm_cmd_lock); | |
5150 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5151 | if (!rc) { | |
abe93ad2 MC |
5152 | u32 flags = le32_to_cpu(resp->flags); |
5153 | ||
41e8d798 MC |
5154 | if (!(bp->flags & BNXT_FLAG_CHIP_P5) && |
5155 | (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)) | |
8fdefd63 | 5156 | bp->flags |= BNXT_FLAG_NEW_RSS_CAP; |
abe93ad2 MC |
5157 | if (flags & |
5158 | VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP) | |
5159 | bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP; | |
79632e9b | 5160 | bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported); |
4e748506 MC |
5161 | if (bp->max_tpa_v2) |
5162 | bp->hw_ring_stats_size = | |
5163 | sizeof(struct ctx_hw_stats_ext); | |
8fdefd63 MC |
5164 | } |
5165 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5166 | return rc; | |
5167 | } | |
5168 | ||
c0c050c5 MC |
5169 | static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) |
5170 | { | |
5171 | u16 i; | |
5172 | u32 rc = 0; | |
5173 | ||
44c6f72a MC |
5174 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
5175 | return 0; | |
5176 | ||
c0c050c5 MC |
5177 | mutex_lock(&bp->hwrm_cmd_lock); |
5178 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
5179 | struct hwrm_ring_grp_alloc_input req = {0}; | |
5180 | struct hwrm_ring_grp_alloc_output *resp = | |
5181 | bp->hwrm_cmd_resp_addr; | |
b81a90d3 | 5182 | unsigned int grp_idx = bp->rx_ring[i].bnapi->index; |
c0c050c5 MC |
5183 | |
5184 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1); | |
5185 | ||
b81a90d3 MC |
5186 | req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); |
5187 | req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); | |
5188 | req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); | |
5189 | req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); | |
c0c050c5 MC |
5190 | |
5191 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
5192 | HWRM_CMD_TIMEOUT); | |
5193 | if (rc) | |
5194 | break; | |
5195 | ||
b81a90d3 MC |
5196 | bp->grp_info[grp_idx].fw_grp_id = |
5197 | le32_to_cpu(resp->ring_group_id); | |
c0c050c5 MC |
5198 | } |
5199 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5200 | return rc; | |
5201 | } | |
5202 | ||
5203 | static int bnxt_hwrm_ring_grp_free(struct bnxt *bp) | |
5204 | { | |
5205 | u16 i; | |
5206 | u32 rc = 0; | |
5207 | struct hwrm_ring_grp_free_input req = {0}; | |
5208 | ||
44c6f72a | 5209 | if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5)) |
c0c050c5 MC |
5210 | return 0; |
5211 | ||
5212 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1); | |
5213 | ||
5214 | mutex_lock(&bp->hwrm_cmd_lock); | |
5215 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
5216 | if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) | |
5217 | continue; | |
5218 | req.ring_group_id = | |
5219 | cpu_to_le32(bp->grp_info[i].fw_grp_id); | |
5220 | ||
5221 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
5222 | HWRM_CMD_TIMEOUT); | |
c0c050c5 MC |
5223 | bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; |
5224 | } | |
5225 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5226 | return rc; | |
5227 | } | |
5228 | ||
5229 | static int hwrm_ring_alloc_send_msg(struct bnxt *bp, | |
5230 | struct bnxt_ring_struct *ring, | |
9899bb59 | 5231 | u32 ring_type, u32 map_index) |
c0c050c5 MC |
5232 | { |
5233 | int rc = 0, err = 0; | |
5234 | struct hwrm_ring_alloc_input req = {0}; | |
5235 | struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
6fe19886 | 5236 | struct bnxt_ring_mem_info *rmem = &ring->ring_mem; |
9899bb59 | 5237 | struct bnxt_ring_grp_info *grp_info; |
c0c050c5 MC |
5238 | u16 ring_id; |
5239 | ||
5240 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1); | |
5241 | ||
5242 | req.enables = 0; | |
6fe19886 MC |
5243 | if (rmem->nr_pages > 1) { |
5244 | req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map); | |
c0c050c5 MC |
5245 | /* Page size is in log2 units */ |
5246 | req.page_size = BNXT_PAGE_SHIFT; | |
5247 | req.page_tbl_depth = 1; | |
5248 | } else { | |
6fe19886 | 5249 | req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]); |
c0c050c5 MC |
5250 | } |
5251 | req.fbo = 0; | |
5252 | /* Association of ring index with doorbell index and MSIX number */ | |
5253 | req.logical_id = cpu_to_le16(map_index); | |
5254 | ||
5255 | switch (ring_type) { | |
2c61d211 MC |
5256 | case HWRM_RING_ALLOC_TX: { |
5257 | struct bnxt_tx_ring_info *txr; | |
5258 | ||
5259 | txr = container_of(ring, struct bnxt_tx_ring_info, | |
5260 | tx_ring_struct); | |
c0c050c5 MC |
5261 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX; |
5262 | /* Association of transmit ring with completion ring */ | |
9899bb59 | 5263 | grp_info = &bp->grp_info[ring->grp_idx]; |
2c61d211 | 5264 | req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr)); |
c0c050c5 | 5265 | req.length = cpu_to_le32(bp->tx_ring_mask + 1); |
9899bb59 | 5266 | req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); |
c0c050c5 MC |
5267 | req.queue_id = cpu_to_le16(ring->queue_id); |
5268 | break; | |
2c61d211 | 5269 | } |
c0c050c5 MC |
5270 | case HWRM_RING_ALLOC_RX: |
5271 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; | |
5272 | req.length = cpu_to_le32(bp->rx_ring_mask + 1); | |
23aefdd7 MC |
5273 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5274 | u16 flags = 0; | |
5275 | ||
5276 | /* Association of rx ring with stats context */ | |
5277 | grp_info = &bp->grp_info[ring->grp_idx]; | |
5278 | req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size); | |
5279 | req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); | |
5280 | req.enables |= cpu_to_le32( | |
5281 | RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); | |
5282 | if (NET_IP_ALIGN == 2) | |
5283 | flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD; | |
5284 | req.flags = cpu_to_le16(flags); | |
5285 | } | |
c0c050c5 MC |
5286 | break; |
5287 | case HWRM_RING_ALLOC_AGG: | |
23aefdd7 MC |
5288 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5289 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG; | |
5290 | /* Association of agg ring with rx ring */ | |
5291 | grp_info = &bp->grp_info[ring->grp_idx]; | |
5292 | req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id); | |
5293 | req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE); | |
5294 | req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); | |
5295 | req.enables |= cpu_to_le32( | |
5296 | RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID | | |
5297 | RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); | |
5298 | } else { | |
5299 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; | |
5300 | } | |
c0c050c5 MC |
5301 | req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1); |
5302 | break; | |
5303 | case HWRM_RING_ALLOC_CMPL: | |
bac9a7e0 | 5304 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL; |
c0c050c5 | 5305 | req.length = cpu_to_le32(bp->cp_ring_mask + 1); |
23aefdd7 MC |
5306 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5307 | /* Association of cp ring with nq */ | |
5308 | grp_info = &bp->grp_info[map_index]; | |
5309 | req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id); | |
5310 | req.cq_handle = cpu_to_le64(ring->handle); | |
5311 | req.enables |= cpu_to_le32( | |
5312 | RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID); | |
5313 | } else if (bp->flags & BNXT_FLAG_USING_MSIX) { | |
5314 | req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; | |
5315 | } | |
5316 | break; | |
5317 | case HWRM_RING_ALLOC_NQ: | |
5318 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ; | |
5319 | req.length = cpu_to_le32(bp->cp_ring_mask + 1); | |
c0c050c5 MC |
5320 | if (bp->flags & BNXT_FLAG_USING_MSIX) |
5321 | req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; | |
5322 | break; | |
5323 | default: | |
5324 | netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", | |
5325 | ring_type); | |
5326 | return -1; | |
5327 | } | |
5328 | ||
5329 | mutex_lock(&bp->hwrm_cmd_lock); | |
5330 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5331 | err = le16_to_cpu(resp->error_code); | |
5332 | ring_id = le16_to_cpu(resp->ring_id); | |
5333 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5334 | ||
5335 | if (rc || err) { | |
2727c888 MC |
5336 | netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n", |
5337 | ring_type, rc, err); | |
5338 | return -EIO; | |
c0c050c5 MC |
5339 | } |
5340 | ring->fw_ring_id = ring_id; | |
5341 | return rc; | |
5342 | } | |
5343 | ||
486b5c22 MC |
5344 | static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx) |
5345 | { | |
5346 | int rc; | |
5347 | ||
5348 | if (BNXT_PF(bp)) { | |
5349 | struct hwrm_func_cfg_input req = {0}; | |
5350 | ||
5351 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); | |
5352 | req.fid = cpu_to_le16(0xffff); | |
5353 | req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR); | |
5354 | req.async_event_cr = cpu_to_le16(idx); | |
5355 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5356 | } else { | |
5357 | struct hwrm_func_vf_cfg_input req = {0}; | |
5358 | ||
5359 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1); | |
5360 | req.enables = | |
5361 | cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR); | |
5362 | req.async_event_cr = cpu_to_le16(idx); | |
5363 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5364 | } | |
5365 | return rc; | |
5366 | } | |
5367 | ||
697197e5 MC |
5368 | static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type, |
5369 | u32 map_idx, u32 xid) | |
5370 | { | |
5371 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
5372 | if (BNXT_PF(bp)) | |
5373 | db->doorbell = bp->bar1 + 0x10000; | |
5374 | else | |
5375 | db->doorbell = bp->bar1 + 0x4000; | |
5376 | switch (ring_type) { | |
5377 | case HWRM_RING_ALLOC_TX: | |
5378 | db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ; | |
5379 | break; | |
5380 | case HWRM_RING_ALLOC_RX: | |
5381 | case HWRM_RING_ALLOC_AGG: | |
5382 | db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ; | |
5383 | break; | |
5384 | case HWRM_RING_ALLOC_CMPL: | |
5385 | db->db_key64 = DBR_PATH_L2; | |
5386 | break; | |
5387 | case HWRM_RING_ALLOC_NQ: | |
5388 | db->db_key64 = DBR_PATH_L2; | |
5389 | break; | |
5390 | } | |
5391 | db->db_key64 |= (u64)xid << DBR_XID_SFT; | |
5392 | } else { | |
5393 | db->doorbell = bp->bar1 + map_idx * 0x80; | |
5394 | switch (ring_type) { | |
5395 | case HWRM_RING_ALLOC_TX: | |
5396 | db->db_key32 = DB_KEY_TX; | |
5397 | break; | |
5398 | case HWRM_RING_ALLOC_RX: | |
5399 | case HWRM_RING_ALLOC_AGG: | |
5400 | db->db_key32 = DB_KEY_RX; | |
5401 | break; | |
5402 | case HWRM_RING_ALLOC_CMPL: | |
5403 | db->db_key32 = DB_KEY_CP; | |
5404 | break; | |
5405 | } | |
5406 | } | |
5407 | } | |
5408 | ||
c0c050c5 MC |
5409 | static int bnxt_hwrm_ring_alloc(struct bnxt *bp) |
5410 | { | |
e8f267b0 | 5411 | bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS); |
c0c050c5 | 5412 | int i, rc = 0; |
697197e5 | 5413 | u32 type; |
c0c050c5 | 5414 | |
23aefdd7 MC |
5415 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
5416 | type = HWRM_RING_ALLOC_NQ; | |
5417 | else | |
5418 | type = HWRM_RING_ALLOC_CMPL; | |
edd0c2cc MC |
5419 | for (i = 0; i < bp->cp_nr_rings; i++) { |
5420 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
5421 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
5422 | struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; | |
9899bb59 | 5423 | u32 map_idx = ring->map_idx; |
5e66e35a | 5424 | unsigned int vector; |
c0c050c5 | 5425 | |
5e66e35a MC |
5426 | vector = bp->irq_tbl[map_idx].vector; |
5427 | disable_irq_nosync(vector); | |
697197e5 | 5428 | rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); |
5e66e35a MC |
5429 | if (rc) { |
5430 | enable_irq(vector); | |
edd0c2cc | 5431 | goto err_out; |
5e66e35a | 5432 | } |
697197e5 MC |
5433 | bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id); |
5434 | bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); | |
5e66e35a | 5435 | enable_irq(vector); |
edd0c2cc | 5436 | bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; |
486b5c22 MC |
5437 | |
5438 | if (!i) { | |
5439 | rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id); | |
5440 | if (rc) | |
5441 | netdev_warn(bp->dev, "Failed to set async event completion ring.\n"); | |
5442 | } | |
c0c050c5 MC |
5443 | } |
5444 | ||
697197e5 | 5445 | type = HWRM_RING_ALLOC_TX; |
edd0c2cc | 5446 | for (i = 0; i < bp->tx_nr_rings; i++) { |
b6ab4b01 | 5447 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
3e08b184 MC |
5448 | struct bnxt_ring_struct *ring; |
5449 | u32 map_idx; | |
c0c050c5 | 5450 | |
3e08b184 MC |
5451 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5452 | struct bnxt_napi *bnapi = txr->bnapi; | |
5453 | struct bnxt_cp_ring_info *cpr, *cpr2; | |
5454 | u32 type2 = HWRM_RING_ALLOC_CMPL; | |
5455 | ||
5456 | cpr = &bnapi->cp_ring; | |
5457 | cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL]; | |
5458 | ring = &cpr2->cp_ring_struct; | |
5459 | ring->handle = BNXT_TX_HDL; | |
5460 | map_idx = bnapi->index; | |
5461 | rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); | |
5462 | if (rc) | |
5463 | goto err_out; | |
5464 | bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, | |
5465 | ring->fw_ring_id); | |
5466 | bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); | |
5467 | } | |
5468 | ring = &txr->tx_ring_struct; | |
5469 | map_idx = i; | |
697197e5 | 5470 | rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); |
edd0c2cc MC |
5471 | if (rc) |
5472 | goto err_out; | |
697197e5 | 5473 | bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id); |
c0c050c5 MC |
5474 | } |
5475 | ||
697197e5 | 5476 | type = HWRM_RING_ALLOC_RX; |
edd0c2cc | 5477 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 5478 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
edd0c2cc | 5479 | struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; |
3e08b184 MC |
5480 | struct bnxt_napi *bnapi = rxr->bnapi; |
5481 | u32 map_idx = bnapi->index; | |
c0c050c5 | 5482 | |
697197e5 | 5483 | rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); |
edd0c2cc MC |
5484 | if (rc) |
5485 | goto err_out; | |
697197e5 | 5486 | bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id); |
e8f267b0 MC |
5487 | /* If we have agg rings, post agg buffers first. */ |
5488 | if (!agg_rings) | |
5489 | bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); | |
b81a90d3 | 5490 | bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; |
3e08b184 MC |
5491 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5492 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
5493 | u32 type2 = HWRM_RING_ALLOC_CMPL; | |
5494 | struct bnxt_cp_ring_info *cpr2; | |
5495 | ||
5496 | cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL]; | |
5497 | ring = &cpr2->cp_ring_struct; | |
5498 | ring->handle = BNXT_RX_HDL; | |
5499 | rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); | |
5500 | if (rc) | |
5501 | goto err_out; | |
5502 | bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, | |
5503 | ring->fw_ring_id); | |
5504 | bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); | |
5505 | } | |
c0c050c5 MC |
5506 | } |
5507 | ||
e8f267b0 | 5508 | if (agg_rings) { |
697197e5 | 5509 | type = HWRM_RING_ALLOC_AGG; |
c0c050c5 | 5510 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 5511 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
c0c050c5 MC |
5512 | struct bnxt_ring_struct *ring = |
5513 | &rxr->rx_agg_ring_struct; | |
9899bb59 | 5514 | u32 grp_idx = ring->grp_idx; |
b81a90d3 | 5515 | u32 map_idx = grp_idx + bp->rx_nr_rings; |
c0c050c5 | 5516 | |
697197e5 | 5517 | rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); |
c0c050c5 MC |
5518 | if (rc) |
5519 | goto err_out; | |
5520 | ||
697197e5 MC |
5521 | bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx, |
5522 | ring->fw_ring_id); | |
5523 | bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); | |
e8f267b0 | 5524 | bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); |
b81a90d3 | 5525 | bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; |
c0c050c5 MC |
5526 | } |
5527 | } | |
5528 | err_out: | |
5529 | return rc; | |
5530 | } | |
5531 | ||
5532 | static int hwrm_ring_free_send_msg(struct bnxt *bp, | |
5533 | struct bnxt_ring_struct *ring, | |
5534 | u32 ring_type, int cmpl_ring_id) | |
5535 | { | |
5536 | int rc; | |
5537 | struct hwrm_ring_free_input req = {0}; | |
5538 | struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr; | |
5539 | u16 error_code; | |
5540 | ||
b4fff207 MC |
5541 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) |
5542 | return 0; | |
5543 | ||
74608fc9 | 5544 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1); |
c0c050c5 MC |
5545 | req.ring_type = ring_type; |
5546 | req.ring_id = cpu_to_le16(ring->fw_ring_id); | |
5547 | ||
5548 | mutex_lock(&bp->hwrm_cmd_lock); | |
5549 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5550 | error_code = le16_to_cpu(resp->error_code); | |
5551 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5552 | ||
5553 | if (rc || error_code) { | |
2727c888 MC |
5554 | netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n", |
5555 | ring_type, rc, error_code); | |
5556 | return -EIO; | |
c0c050c5 MC |
5557 | } |
5558 | return 0; | |
5559 | } | |
5560 | ||
edd0c2cc | 5561 | static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) |
c0c050c5 | 5562 | { |
23aefdd7 | 5563 | u32 type; |
edd0c2cc | 5564 | int i; |
c0c050c5 MC |
5565 | |
5566 | if (!bp->bnapi) | |
edd0c2cc | 5567 | return; |
c0c050c5 | 5568 | |
edd0c2cc | 5569 | for (i = 0; i < bp->tx_nr_rings; i++) { |
b6ab4b01 | 5570 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
edd0c2cc | 5571 | struct bnxt_ring_struct *ring = &txr->tx_ring_struct; |
edd0c2cc MC |
5572 | |
5573 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
1f83391b MC |
5574 | u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr); |
5575 | ||
edd0c2cc MC |
5576 | hwrm_ring_free_send_msg(bp, ring, |
5577 | RING_FREE_REQ_RING_TYPE_TX, | |
5578 | close_path ? cmpl_ring_id : | |
5579 | INVALID_HW_RING_ID); | |
5580 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
c0c050c5 MC |
5581 | } |
5582 | } | |
5583 | ||
edd0c2cc | 5584 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 5585 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
edd0c2cc | 5586 | struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; |
b81a90d3 | 5587 | u32 grp_idx = rxr->bnapi->index; |
edd0c2cc MC |
5588 | |
5589 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
1f83391b MC |
5590 | u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); |
5591 | ||
edd0c2cc MC |
5592 | hwrm_ring_free_send_msg(bp, ring, |
5593 | RING_FREE_REQ_RING_TYPE_RX, | |
5594 | close_path ? cmpl_ring_id : | |
5595 | INVALID_HW_RING_ID); | |
5596 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
b81a90d3 MC |
5597 | bp->grp_info[grp_idx].rx_fw_ring_id = |
5598 | INVALID_HW_RING_ID; | |
c0c050c5 MC |
5599 | } |
5600 | } | |
5601 | ||
23aefdd7 MC |
5602 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
5603 | type = RING_FREE_REQ_RING_TYPE_RX_AGG; | |
5604 | else | |
5605 | type = RING_FREE_REQ_RING_TYPE_RX; | |
edd0c2cc | 5606 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 5607 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
edd0c2cc | 5608 | struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; |
b81a90d3 | 5609 | u32 grp_idx = rxr->bnapi->index; |
edd0c2cc MC |
5610 | |
5611 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
1f83391b MC |
5612 | u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); |
5613 | ||
23aefdd7 | 5614 | hwrm_ring_free_send_msg(bp, ring, type, |
edd0c2cc MC |
5615 | close_path ? cmpl_ring_id : |
5616 | INVALID_HW_RING_ID); | |
5617 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
b81a90d3 MC |
5618 | bp->grp_info[grp_idx].agg_fw_ring_id = |
5619 | INVALID_HW_RING_ID; | |
c0c050c5 MC |
5620 | } |
5621 | } | |
5622 | ||
9d8bc097 MC |
5623 | /* The completion rings are about to be freed. After that the |
5624 | * IRQ doorbell will not work anymore. So we need to disable | |
5625 | * IRQ here. | |
5626 | */ | |
5627 | bnxt_disable_int_sync(bp); | |
5628 | ||
23aefdd7 MC |
5629 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
5630 | type = RING_FREE_REQ_RING_TYPE_NQ; | |
5631 | else | |
5632 | type = RING_FREE_REQ_RING_TYPE_L2_CMPL; | |
edd0c2cc MC |
5633 | for (i = 0; i < bp->cp_nr_rings; i++) { |
5634 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
5635 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
3e08b184 MC |
5636 | struct bnxt_ring_struct *ring; |
5637 | int j; | |
edd0c2cc | 5638 | |
3e08b184 MC |
5639 | for (j = 0; j < 2; j++) { |
5640 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; | |
5641 | ||
5642 | if (cpr2) { | |
5643 | ring = &cpr2->cp_ring_struct; | |
5644 | if (ring->fw_ring_id == INVALID_HW_RING_ID) | |
5645 | continue; | |
5646 | hwrm_ring_free_send_msg(bp, ring, | |
5647 | RING_FREE_REQ_RING_TYPE_L2_CMPL, | |
5648 | INVALID_HW_RING_ID); | |
5649 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
5650 | } | |
5651 | } | |
5652 | ring = &cpr->cp_ring_struct; | |
edd0c2cc | 5653 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { |
23aefdd7 | 5654 | hwrm_ring_free_send_msg(bp, ring, type, |
edd0c2cc MC |
5655 | INVALID_HW_RING_ID); |
5656 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
5657 | bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; | |
c0c050c5 MC |
5658 | } |
5659 | } | |
c0c050c5 MC |
5660 | } |
5661 | ||
41e8d798 MC |
5662 | static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, |
5663 | bool shared); | |
5664 | ||
674f50a5 MC |
5665 | static int bnxt_hwrm_get_rings(struct bnxt *bp) |
5666 | { | |
5667 | struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
5668 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
5669 | struct hwrm_func_qcfg_input req = {0}; | |
5670 | int rc; | |
5671 | ||
5672 | if (bp->hwrm_spec_code < 0x10601) | |
5673 | return 0; | |
5674 | ||
5675 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); | |
5676 | req.fid = cpu_to_le16(0xffff); | |
5677 | mutex_lock(&bp->hwrm_cmd_lock); | |
5678 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5679 | if (rc) { | |
5680 | mutex_unlock(&bp->hwrm_cmd_lock); | |
d4f1420d | 5681 | return rc; |
674f50a5 MC |
5682 | } |
5683 | ||
5684 | hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings); | |
f1ca94de | 5685 | if (BNXT_NEW_RM(bp)) { |
674f50a5 MC |
5686 | u16 cp, stats; |
5687 | ||
5688 | hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings); | |
5689 | hw_resc->resv_hw_ring_grps = | |
5690 | le32_to_cpu(resp->alloc_hw_ring_grps); | |
5691 | hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics); | |
5692 | cp = le16_to_cpu(resp->alloc_cmpl_rings); | |
5693 | stats = le16_to_cpu(resp->alloc_stat_ctx); | |
75720e63 | 5694 | hw_resc->resv_irqs = cp; |
41e8d798 MC |
5695 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5696 | int rx = hw_resc->resv_rx_rings; | |
5697 | int tx = hw_resc->resv_tx_rings; | |
5698 | ||
5699 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
5700 | rx >>= 1; | |
5701 | if (cp < (rx + tx)) { | |
5702 | bnxt_trim_rings(bp, &rx, &tx, cp, false); | |
5703 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
5704 | rx <<= 1; | |
5705 | hw_resc->resv_rx_rings = rx; | |
5706 | hw_resc->resv_tx_rings = tx; | |
5707 | } | |
75720e63 | 5708 | hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix); |
41e8d798 MC |
5709 | hw_resc->resv_hw_ring_grps = rx; |
5710 | } | |
674f50a5 | 5711 | hw_resc->resv_cp_rings = cp; |
780baad4 | 5712 | hw_resc->resv_stat_ctxs = stats; |
674f50a5 MC |
5713 | } |
5714 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5715 | return 0; | |
5716 | } | |
5717 | ||
391be5c2 MC |
5718 | /* Caller must hold bp->hwrm_cmd_lock */ |
5719 | int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings) | |
5720 | { | |
5721 | struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
5722 | struct hwrm_func_qcfg_input req = {0}; | |
5723 | int rc; | |
5724 | ||
5725 | if (bp->hwrm_spec_code < 0x10601) | |
5726 | return 0; | |
5727 | ||
5728 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); | |
5729 | req.fid = cpu_to_le16(fid); | |
5730 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5731 | if (!rc) | |
5732 | *tx_rings = le16_to_cpu(resp->alloc_tx_rings); | |
5733 | ||
5734 | return rc; | |
5735 | } | |
5736 | ||
41e8d798 MC |
5737 | static bool bnxt_rfs_supported(struct bnxt *bp); |
5738 | ||
4ed50ef4 MC |
5739 | static void |
5740 | __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req, | |
5741 | int tx_rings, int rx_rings, int ring_grps, | |
780baad4 | 5742 | int cp_rings, int stats, int vnics) |
391be5c2 | 5743 | { |
674f50a5 | 5744 | u32 enables = 0; |
391be5c2 | 5745 | |
4ed50ef4 MC |
5746 | bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1); |
5747 | req->fid = cpu_to_le16(0xffff); | |
674f50a5 | 5748 | enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; |
4ed50ef4 | 5749 | req->num_tx_rings = cpu_to_le16(tx_rings); |
f1ca94de | 5750 | if (BNXT_NEW_RM(bp)) { |
674f50a5 | 5751 | enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0; |
3f93cd3f | 5752 | enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; |
41e8d798 MC |
5753 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5754 | enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0; | |
5755 | enables |= tx_rings + ring_grps ? | |
3f93cd3f | 5756 | FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; |
41e8d798 MC |
5757 | enables |= rx_rings ? |
5758 | FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; | |
5759 | } else { | |
5760 | enables |= cp_rings ? | |
3f93cd3f | 5761 | FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; |
41e8d798 MC |
5762 | enables |= ring_grps ? |
5763 | FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS | | |
5764 | FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; | |
5765 | } | |
dbe80d44 | 5766 | enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0; |
674f50a5 | 5767 | |
4ed50ef4 | 5768 | req->num_rx_rings = cpu_to_le16(rx_rings); |
41e8d798 MC |
5769 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5770 | req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); | |
5771 | req->num_msix = cpu_to_le16(cp_rings); | |
5772 | req->num_rsscos_ctxs = | |
5773 | cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); | |
5774 | } else { | |
5775 | req->num_cmpl_rings = cpu_to_le16(cp_rings); | |
5776 | req->num_hw_ring_grps = cpu_to_le16(ring_grps); | |
5777 | req->num_rsscos_ctxs = cpu_to_le16(1); | |
5778 | if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) && | |
5779 | bnxt_rfs_supported(bp)) | |
5780 | req->num_rsscos_ctxs = | |
5781 | cpu_to_le16(ring_grps + 1); | |
5782 | } | |
780baad4 | 5783 | req->num_stat_ctxs = cpu_to_le16(stats); |
4ed50ef4 | 5784 | req->num_vnics = cpu_to_le16(vnics); |
674f50a5 | 5785 | } |
4ed50ef4 MC |
5786 | req->enables = cpu_to_le32(enables); |
5787 | } | |
5788 | ||
5789 | static void | |
5790 | __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, | |
5791 | struct hwrm_func_vf_cfg_input *req, int tx_rings, | |
5792 | int rx_rings, int ring_grps, int cp_rings, | |
780baad4 | 5793 | int stats, int vnics) |
4ed50ef4 MC |
5794 | { |
5795 | u32 enables = 0; | |
5796 | ||
5797 | bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1); | |
5798 | enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; | |
41e8d798 MC |
5799 | enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS | |
5800 | FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; | |
3f93cd3f | 5801 | enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; |
41e8d798 MC |
5802 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5803 | enables |= tx_rings + ring_grps ? | |
3f93cd3f | 5804 | FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; |
41e8d798 MC |
5805 | } else { |
5806 | enables |= cp_rings ? | |
3f93cd3f | 5807 | FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; |
41e8d798 MC |
5808 | enables |= ring_grps ? |
5809 | FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0; | |
5810 | } | |
4ed50ef4 | 5811 | enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0; |
41e8d798 | 5812 | enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS; |
4ed50ef4 | 5813 | |
41e8d798 | 5814 | req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX); |
4ed50ef4 MC |
5815 | req->num_tx_rings = cpu_to_le16(tx_rings); |
5816 | req->num_rx_rings = cpu_to_le16(rx_rings); | |
41e8d798 MC |
5817 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5818 | req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); | |
5819 | req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); | |
5820 | } else { | |
5821 | req->num_cmpl_rings = cpu_to_le16(cp_rings); | |
5822 | req->num_hw_ring_grps = cpu_to_le16(ring_grps); | |
5823 | req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX); | |
5824 | } | |
780baad4 | 5825 | req->num_stat_ctxs = cpu_to_le16(stats); |
4ed50ef4 MC |
5826 | req->num_vnics = cpu_to_le16(vnics); |
5827 | ||
5828 | req->enables = cpu_to_le32(enables); | |
5829 | } | |
5830 | ||
5831 | static int | |
5832 | bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, | |
780baad4 | 5833 | int ring_grps, int cp_rings, int stats, int vnics) |
4ed50ef4 MC |
5834 | { |
5835 | struct hwrm_func_cfg_input req = {0}; | |
5836 | int rc; | |
5837 | ||
5838 | __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, | |
780baad4 | 5839 | cp_rings, stats, vnics); |
4ed50ef4 | 5840 | if (!req.enables) |
391be5c2 MC |
5841 | return 0; |
5842 | ||
674f50a5 MC |
5843 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
5844 | if (rc) | |
d4f1420d | 5845 | return rc; |
674f50a5 MC |
5846 | |
5847 | if (bp->hwrm_spec_code < 0x10601) | |
5848 | bp->hw_resc.resv_tx_rings = tx_rings; | |
5849 | ||
5850 | rc = bnxt_hwrm_get_rings(bp); | |
5851 | return rc; | |
5852 | } | |
5853 | ||
5854 | static int | |
5855 | bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, | |
780baad4 | 5856 | int ring_grps, int cp_rings, int stats, int vnics) |
674f50a5 MC |
5857 | { |
5858 | struct hwrm_func_vf_cfg_input req = {0}; | |
674f50a5 MC |
5859 | int rc; |
5860 | ||
f1ca94de | 5861 | if (!BNXT_NEW_RM(bp)) { |
674f50a5 | 5862 | bp->hw_resc.resv_tx_rings = tx_rings; |
391be5c2 | 5863 | return 0; |
674f50a5 | 5864 | } |
391be5c2 | 5865 | |
4ed50ef4 | 5866 | __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, |
780baad4 | 5867 | cp_rings, stats, vnics); |
391be5c2 | 5868 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
674f50a5 | 5869 | if (rc) |
d4f1420d | 5870 | return rc; |
674f50a5 MC |
5871 | |
5872 | rc = bnxt_hwrm_get_rings(bp); | |
5873 | return rc; | |
5874 | } | |
5875 | ||
5876 | static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp, | |
780baad4 | 5877 | int cp, int stat, int vnic) |
674f50a5 MC |
5878 | { |
5879 | if (BNXT_PF(bp)) | |
780baad4 VV |
5880 | return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat, |
5881 | vnic); | |
674f50a5 | 5882 | else |
780baad4 VV |
5883 | return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat, |
5884 | vnic); | |
674f50a5 MC |
5885 | } |
5886 | ||
b16b6891 | 5887 | int bnxt_nq_rings_in_use(struct bnxt *bp) |
08654eb2 MC |
5888 | { |
5889 | int cp = bp->cp_nr_rings; | |
5890 | int ulp_msix, ulp_base; | |
5891 | ||
5892 | ulp_msix = bnxt_get_ulp_msix_num(bp); | |
5893 | if (ulp_msix) { | |
5894 | ulp_base = bnxt_get_ulp_msix_base(bp); | |
5895 | cp += ulp_msix; | |
5896 | if ((ulp_base + ulp_msix) > cp) | |
5897 | cp = ulp_base + ulp_msix; | |
5898 | } | |
5899 | return cp; | |
5900 | } | |
5901 | ||
c0b8cda0 MC |
5902 | static int bnxt_cp_rings_in_use(struct bnxt *bp) |
5903 | { | |
5904 | int cp; | |
5905 | ||
5906 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
5907 | return bnxt_nq_rings_in_use(bp); | |
5908 | ||
5909 | cp = bp->tx_nr_rings + bp->rx_nr_rings; | |
5910 | return cp; | |
5911 | } | |
5912 | ||
780baad4 VV |
5913 | static int bnxt_get_func_stat_ctxs(struct bnxt *bp) |
5914 | { | |
d77b1ad8 MC |
5915 | int ulp_stat = bnxt_get_ulp_stat_ctxs(bp); |
5916 | int cp = bp->cp_nr_rings; | |
5917 | ||
5918 | if (!ulp_stat) | |
5919 | return cp; | |
5920 | ||
5921 | if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp)) | |
5922 | return bnxt_get_ulp_msix_base(bp) + ulp_stat; | |
5923 | ||
5924 | return cp + ulp_stat; | |
780baad4 VV |
5925 | } |
5926 | ||
4e41dc5d MC |
5927 | static bool bnxt_need_reserve_rings(struct bnxt *bp) |
5928 | { | |
5929 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
fbcfc8e4 | 5930 | int cp = bnxt_cp_rings_in_use(bp); |
c0b8cda0 | 5931 | int nq = bnxt_nq_rings_in_use(bp); |
780baad4 | 5932 | int rx = bp->rx_nr_rings, stat; |
4e41dc5d MC |
5933 | int vnic = 1, grp = rx; |
5934 | ||
5935 | if (bp->hwrm_spec_code < 0x10601) | |
5936 | return false; | |
5937 | ||
5938 | if (hw_resc->resv_tx_rings != bp->tx_nr_rings) | |
5939 | return true; | |
5940 | ||
41e8d798 | 5941 | if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) |
4e41dc5d MC |
5942 | vnic = rx + 1; |
5943 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
5944 | rx <<= 1; | |
780baad4 | 5945 | stat = bnxt_get_func_stat_ctxs(bp); |
f1ca94de | 5946 | if (BNXT_NEW_RM(bp) && |
4e41dc5d | 5947 | (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp || |
01989c6b | 5948 | hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat || |
41e8d798 MC |
5949 | (hw_resc->resv_hw_ring_grps != grp && |
5950 | !(bp->flags & BNXT_FLAG_CHIP_P5)))) | |
4e41dc5d | 5951 | return true; |
01989c6b MC |
5952 | if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) && |
5953 | hw_resc->resv_irqs != nq) | |
5954 | return true; | |
4e41dc5d MC |
5955 | return false; |
5956 | } | |
5957 | ||
674f50a5 MC |
5958 | static int __bnxt_reserve_rings(struct bnxt *bp) |
5959 | { | |
5960 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
c0b8cda0 | 5961 | int cp = bnxt_nq_rings_in_use(bp); |
674f50a5 MC |
5962 | int tx = bp->tx_nr_rings; |
5963 | int rx = bp->rx_nr_rings; | |
674f50a5 | 5964 | int grp, rx_rings, rc; |
780baad4 | 5965 | int vnic = 1, stat; |
674f50a5 | 5966 | bool sh = false; |
674f50a5 | 5967 | |
4e41dc5d | 5968 | if (!bnxt_need_reserve_rings(bp)) |
674f50a5 MC |
5969 | return 0; |
5970 | ||
5971 | if (bp->flags & BNXT_FLAG_SHARED_RINGS) | |
5972 | sh = true; | |
41e8d798 | 5973 | if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) |
674f50a5 MC |
5974 | vnic = rx + 1; |
5975 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
5976 | rx <<= 1; | |
674f50a5 | 5977 | grp = bp->rx_nr_rings; |
780baad4 | 5978 | stat = bnxt_get_func_stat_ctxs(bp); |
674f50a5 | 5979 | |
780baad4 | 5980 | rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic); |
391be5c2 MC |
5981 | if (rc) |
5982 | return rc; | |
5983 | ||
674f50a5 | 5984 | tx = hw_resc->resv_tx_rings; |
f1ca94de | 5985 | if (BNXT_NEW_RM(bp)) { |
674f50a5 | 5986 | rx = hw_resc->resv_rx_rings; |
c0b8cda0 | 5987 | cp = hw_resc->resv_irqs; |
674f50a5 MC |
5988 | grp = hw_resc->resv_hw_ring_grps; |
5989 | vnic = hw_resc->resv_vnics; | |
780baad4 | 5990 | stat = hw_resc->resv_stat_ctxs; |
674f50a5 MC |
5991 | } |
5992 | ||
5993 | rx_rings = rx; | |
5994 | if (bp->flags & BNXT_FLAG_AGG_RINGS) { | |
5995 | if (rx >= 2) { | |
5996 | rx_rings = rx >> 1; | |
5997 | } else { | |
5998 | if (netif_running(bp->dev)) | |
5999 | return -ENOMEM; | |
6000 | ||
6001 | bp->flags &= ~BNXT_FLAG_AGG_RINGS; | |
6002 | bp->flags |= BNXT_FLAG_NO_AGG_RINGS; | |
6003 | bp->dev->hw_features &= ~NETIF_F_LRO; | |
6004 | bp->dev->features &= ~NETIF_F_LRO; | |
6005 | bnxt_set_ring_params(bp); | |
6006 | } | |
6007 | } | |
6008 | rx_rings = min_t(int, rx_rings, grp); | |
780baad4 VV |
6009 | cp = min_t(int, cp, bp->cp_nr_rings); |
6010 | if (stat > bnxt_get_ulp_stat_ctxs(bp)) | |
6011 | stat -= bnxt_get_ulp_stat_ctxs(bp); | |
6012 | cp = min_t(int, cp, stat); | |
674f50a5 MC |
6013 | rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh); |
6014 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
6015 | rx = rx_rings << 1; | |
6016 | cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings; | |
6017 | bp->tx_nr_rings = tx; | |
6018 | bp->rx_nr_rings = rx_rings; | |
6019 | bp->cp_nr_rings = cp; | |
6020 | ||
780baad4 | 6021 | if (!tx || !rx || !cp || !grp || !vnic || !stat) |
674f50a5 MC |
6022 | return -ENOMEM; |
6023 | ||
391be5c2 MC |
6024 | return rc; |
6025 | } | |
6026 | ||
8f23d638 | 6027 | static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, |
780baad4 VV |
6028 | int ring_grps, int cp_rings, int stats, |
6029 | int vnics) | |
98fdbe73 | 6030 | { |
8f23d638 | 6031 | struct hwrm_func_vf_cfg_input req = {0}; |
6fc2ffdf | 6032 | u32 flags; |
98fdbe73 MC |
6033 | int rc; |
6034 | ||
f1ca94de | 6035 | if (!BNXT_NEW_RM(bp)) |
98fdbe73 MC |
6036 | return 0; |
6037 | ||
6fc2ffdf | 6038 | __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, |
780baad4 | 6039 | cp_rings, stats, vnics); |
8f23d638 MC |
6040 | flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST | |
6041 | FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST | | |
6042 | FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | | |
8f23d638 | 6043 | FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | |
41e8d798 MC |
6044 | FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST | |
6045 | FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST; | |
6046 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
6047 | flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; | |
8f23d638 MC |
6048 | |
6049 | req.flags = cpu_to_le32(flags); | |
8f23d638 | 6050 | rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
d4f1420d | 6051 | return rc; |
8f23d638 MC |
6052 | } |
6053 | ||
6054 | static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, | |
780baad4 VV |
6055 | int ring_grps, int cp_rings, int stats, |
6056 | int vnics) | |
8f23d638 MC |
6057 | { |
6058 | struct hwrm_func_cfg_input req = {0}; | |
6fc2ffdf | 6059 | u32 flags; |
8f23d638 | 6060 | int rc; |
98fdbe73 | 6061 | |
6fc2ffdf | 6062 | __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, |
780baad4 | 6063 | cp_rings, stats, vnics); |
8f23d638 | 6064 | flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST; |
41e8d798 | 6065 | if (BNXT_NEW_RM(bp)) { |
8f23d638 MC |
6066 | flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST | |
6067 | FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | | |
8f23d638 MC |
6068 | FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | |
6069 | FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST; | |
41e8d798 | 6070 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
0b815023 MC |
6071 | flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST | |
6072 | FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST; | |
41e8d798 MC |
6073 | else |
6074 | flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; | |
6075 | } | |
6fc2ffdf | 6076 | |
8f23d638 | 6077 | req.flags = cpu_to_le32(flags); |
98fdbe73 | 6078 | rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
d4f1420d | 6079 | return rc; |
98fdbe73 MC |
6080 | } |
6081 | ||
8f23d638 | 6082 | static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings, |
780baad4 VV |
6083 | int ring_grps, int cp_rings, int stats, |
6084 | int vnics) | |
8f23d638 MC |
6085 | { |
6086 | if (bp->hwrm_spec_code < 0x10801) | |
6087 | return 0; | |
6088 | ||
6089 | if (BNXT_PF(bp)) | |
6090 | return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings, | |
780baad4 VV |
6091 | ring_grps, cp_rings, stats, |
6092 | vnics); | |
8f23d638 MC |
6093 | |
6094 | return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps, | |
780baad4 | 6095 | cp_rings, stats, vnics); |
8f23d638 MC |
6096 | } |
6097 | ||
74706afa MC |
6098 | static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp) |
6099 | { | |
6100 | struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
6101 | struct bnxt_coal_cap *coal_cap = &bp->coal_cap; | |
6102 | struct hwrm_ring_aggint_qcaps_input req = {0}; | |
6103 | int rc; | |
6104 | ||
6105 | coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS; | |
6106 | coal_cap->num_cmpl_dma_aggr_max = 63; | |
6107 | coal_cap->num_cmpl_dma_aggr_during_int_max = 63; | |
6108 | coal_cap->cmpl_aggr_dma_tmr_max = 65535; | |
6109 | coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535; | |
6110 | coal_cap->int_lat_tmr_min_max = 65535; | |
6111 | coal_cap->int_lat_tmr_max_max = 65535; | |
6112 | coal_cap->num_cmpl_aggr_int_max = 65535; | |
6113 | coal_cap->timer_units = 80; | |
6114 | ||
6115 | if (bp->hwrm_spec_code < 0x10902) | |
6116 | return; | |
6117 | ||
6118 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1); | |
6119 | mutex_lock(&bp->hwrm_cmd_lock); | |
6120 | rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
6121 | if (!rc) { | |
6122 | coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params); | |
58590c8d | 6123 | coal_cap->nq_params = le32_to_cpu(resp->nq_params); |
74706afa MC |
6124 | coal_cap->num_cmpl_dma_aggr_max = |
6125 | le16_to_cpu(resp->num_cmpl_dma_aggr_max); | |
6126 | coal_cap->num_cmpl_dma_aggr_during_int_max = | |
6127 | le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max); | |
6128 | coal_cap->cmpl_aggr_dma_tmr_max = | |
6129 | le16_to_cpu(resp->cmpl_aggr_dma_tmr_max); | |
6130 | coal_cap->cmpl_aggr_dma_tmr_during_int_max = | |
6131 | le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max); | |
6132 | coal_cap->int_lat_tmr_min_max = | |
6133 | le16_to_cpu(resp->int_lat_tmr_min_max); | |
6134 | coal_cap->int_lat_tmr_max_max = | |
6135 | le16_to_cpu(resp->int_lat_tmr_max_max); | |
6136 | coal_cap->num_cmpl_aggr_int_max = | |
6137 | le16_to_cpu(resp->num_cmpl_aggr_int_max); | |
6138 | coal_cap->timer_units = le16_to_cpu(resp->timer_units); | |
6139 | } | |
6140 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6141 | } | |
6142 | ||
6143 | static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec) | |
6144 | { | |
6145 | struct bnxt_coal_cap *coal_cap = &bp->coal_cap; | |
6146 | ||
6147 | return usec * 1000 / coal_cap->timer_units; | |
6148 | } | |
6149 | ||
6150 | static void bnxt_hwrm_set_coal_params(struct bnxt *bp, | |
6151 | struct bnxt_coal *hw_coal, | |
bb053f52 MC |
6152 | struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req) |
6153 | { | |
74706afa MC |
6154 | struct bnxt_coal_cap *coal_cap = &bp->coal_cap; |
6155 | u32 cmpl_params = coal_cap->cmpl_params; | |
6156 | u16 val, tmr, max, flags = 0; | |
f8503969 MC |
6157 | |
6158 | max = hw_coal->bufs_per_record * 128; | |
6159 | if (hw_coal->budget) | |
6160 | max = hw_coal->bufs_per_record * hw_coal->budget; | |
74706afa | 6161 | max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max); |
f8503969 MC |
6162 | |
6163 | val = clamp_t(u16, hw_coal->coal_bufs, 1, max); | |
6164 | req->num_cmpl_aggr_int = cpu_to_le16(val); | |
b153cbc5 | 6165 | |
74706afa | 6166 | val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max); |
f8503969 MC |
6167 | req->num_cmpl_dma_aggr = cpu_to_le16(val); |
6168 | ||
74706afa MC |
6169 | val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, |
6170 | coal_cap->num_cmpl_dma_aggr_during_int_max); | |
f8503969 MC |
6171 | req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val); |
6172 | ||
74706afa MC |
6173 | tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks); |
6174 | tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max); | |
f8503969 MC |
6175 | req->int_lat_tmr_max = cpu_to_le16(tmr); |
6176 | ||
6177 | /* min timer set to 1/2 of interrupt timer */ | |
74706afa MC |
6178 | if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) { |
6179 | val = tmr / 2; | |
6180 | val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max); | |
6181 | req->int_lat_tmr_min = cpu_to_le16(val); | |
6182 | req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); | |
6183 | } | |
f8503969 MC |
6184 | |
6185 | /* buf timer set to 1/4 of interrupt timer */ | |
74706afa | 6186 | val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max); |
f8503969 MC |
6187 | req->cmpl_aggr_dma_tmr = cpu_to_le16(val); |
6188 | ||
74706afa MC |
6189 | if (cmpl_params & |
6190 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) { | |
6191 | tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq); | |
6192 | val = clamp_t(u16, tmr, 1, | |
6193 | coal_cap->cmpl_aggr_dma_tmr_during_int_max); | |
6adc4601 | 6194 | req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val); |
74706afa MC |
6195 | req->enables |= |
6196 | cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE); | |
6197 | } | |
f8503969 | 6198 | |
74706afa MC |
6199 | if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET) |
6200 | flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; | |
6201 | if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) && | |
6202 | hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh) | |
f8503969 | 6203 | flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; |
bb053f52 | 6204 | req->flags = cpu_to_le16(flags); |
74706afa | 6205 | req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES); |
bb053f52 MC |
6206 | } |
6207 | ||
58590c8d MC |
6208 | /* Caller holds bp->hwrm_cmd_lock */ |
6209 | static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi, | |
6210 | struct bnxt_coal *hw_coal) | |
6211 | { | |
6212 | struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0}; | |
6213 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
6214 | struct bnxt_coal_cap *coal_cap = &bp->coal_cap; | |
6215 | u32 nq_params = coal_cap->nq_params; | |
6216 | u16 tmr; | |
6217 | ||
6218 | if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN)) | |
6219 | return 0; | |
6220 | ||
6221 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, | |
6222 | -1, -1); | |
6223 | req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id); | |
6224 | req.flags = | |
6225 | cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ); | |
6226 | ||
6227 | tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2; | |
6228 | tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max); | |
6229 | req.int_lat_tmr_min = cpu_to_le16(tmr); | |
6230 | req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); | |
6231 | return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
6232 | } | |
6233 | ||
6a8788f2 AG |
6234 | int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi) |
6235 | { | |
6236 | struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}; | |
6237 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
6238 | struct bnxt_coal coal; | |
6a8788f2 AG |
6239 | |
6240 | /* Tick values in micro seconds. | |
6241 | * 1 coal_buf x bufs_per_record = 1 completion record. | |
6242 | */ | |
6243 | memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal)); | |
6244 | ||
6245 | coal.coal_ticks = cpr->rx_ring_coal.coal_ticks; | |
6246 | coal.coal_bufs = cpr->rx_ring_coal.coal_bufs; | |
6247 | ||
6248 | if (!bnapi->rx_ring) | |
6249 | return -ENODEV; | |
6250 | ||
6251 | bnxt_hwrm_cmd_hdr_init(bp, &req_rx, | |
6252 | HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); | |
6253 | ||
74706afa | 6254 | bnxt_hwrm_set_coal_params(bp, &coal, &req_rx); |
6a8788f2 | 6255 | |
2c61d211 | 6256 | req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring)); |
6a8788f2 AG |
6257 | |
6258 | return hwrm_send_message(bp, &req_rx, sizeof(req_rx), | |
6259 | HWRM_CMD_TIMEOUT); | |
6260 | } | |
6261 | ||
c0c050c5 MC |
6262 | int bnxt_hwrm_set_coal(struct bnxt *bp) |
6263 | { | |
6264 | int i, rc = 0; | |
dfc9c94a MC |
6265 | struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}, |
6266 | req_tx = {0}, *req; | |
c0c050c5 | 6267 | |
dfc9c94a MC |
6268 | bnxt_hwrm_cmd_hdr_init(bp, &req_rx, |
6269 | HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); | |
6270 | bnxt_hwrm_cmd_hdr_init(bp, &req_tx, | |
6271 | HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); | |
c0c050c5 | 6272 | |
74706afa MC |
6273 | bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx); |
6274 | bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx); | |
c0c050c5 MC |
6275 | |
6276 | mutex_lock(&bp->hwrm_cmd_lock); | |
6277 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
dfc9c94a | 6278 | struct bnxt_napi *bnapi = bp->bnapi[i]; |
58590c8d | 6279 | struct bnxt_coal *hw_coal; |
2c61d211 | 6280 | u16 ring_id; |
c0c050c5 | 6281 | |
dfc9c94a | 6282 | req = &req_rx; |
2c61d211 MC |
6283 | if (!bnapi->rx_ring) { |
6284 | ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); | |
dfc9c94a | 6285 | req = &req_tx; |
2c61d211 MC |
6286 | } else { |
6287 | ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring); | |
6288 | } | |
6289 | req->ring_id = cpu_to_le16(ring_id); | |
dfc9c94a MC |
6290 | |
6291 | rc = _hwrm_send_message(bp, req, sizeof(*req), | |
c0c050c5 MC |
6292 | HWRM_CMD_TIMEOUT); |
6293 | if (rc) | |
6294 | break; | |
58590c8d MC |
6295 | |
6296 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
6297 | continue; | |
6298 | ||
6299 | if (bnapi->rx_ring && bnapi->tx_ring) { | |
6300 | req = &req_tx; | |
6301 | ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); | |
6302 | req->ring_id = cpu_to_le16(ring_id); | |
6303 | rc = _hwrm_send_message(bp, req, sizeof(*req), | |
6304 | HWRM_CMD_TIMEOUT); | |
6305 | if (rc) | |
6306 | break; | |
6307 | } | |
6308 | if (bnapi->rx_ring) | |
6309 | hw_coal = &bp->rx_coal; | |
6310 | else | |
6311 | hw_coal = &bp->tx_coal; | |
6312 | __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal); | |
c0c050c5 MC |
6313 | } |
6314 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6315 | return rc; | |
6316 | } | |
6317 | ||
6318 | static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp) | |
6319 | { | |
6320 | int rc = 0, i; | |
6321 | struct hwrm_stat_ctx_free_input req = {0}; | |
6322 | ||
6323 | if (!bp->bnapi) | |
6324 | return 0; | |
6325 | ||
3e8060fa PS |
6326 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) |
6327 | return 0; | |
6328 | ||
c0c050c5 MC |
6329 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1); |
6330 | ||
6331 | mutex_lock(&bp->hwrm_cmd_lock); | |
6332 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
6333 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
6334 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
6335 | ||
6336 | if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { | |
6337 | req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); | |
6338 | ||
6339 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
6340 | HWRM_CMD_TIMEOUT); | |
c0c050c5 MC |
6341 | |
6342 | cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; | |
6343 | } | |
6344 | } | |
6345 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6346 | return rc; | |
6347 | } | |
6348 | ||
6349 | static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) | |
6350 | { | |
6351 | int rc = 0, i; | |
6352 | struct hwrm_stat_ctx_alloc_input req = {0}; | |
6353 | struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
6354 | ||
3e8060fa PS |
6355 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) |
6356 | return 0; | |
6357 | ||
c0c050c5 MC |
6358 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1); |
6359 | ||
4e748506 | 6360 | req.stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size); |
51f30785 | 6361 | req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000); |
c0c050c5 MC |
6362 | |
6363 | mutex_lock(&bp->hwrm_cmd_lock); | |
6364 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
6365 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
6366 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
6367 | ||
6368 | req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map); | |
6369 | ||
6370 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
6371 | HWRM_CMD_TIMEOUT); | |
6372 | if (rc) | |
6373 | break; | |
6374 | ||
6375 | cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); | |
6376 | ||
6377 | bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; | |
6378 | } | |
6379 | mutex_unlock(&bp->hwrm_cmd_lock); | |
89aa8445 | 6380 | return rc; |
c0c050c5 MC |
6381 | } |
6382 | ||
cf6645f8 MC |
6383 | static int bnxt_hwrm_func_qcfg(struct bnxt *bp) |
6384 | { | |
6385 | struct hwrm_func_qcfg_input req = {0}; | |
567b2abe | 6386 | struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; |
9315edca | 6387 | u16 flags; |
cf6645f8 MC |
6388 | int rc; |
6389 | ||
6390 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); | |
6391 | req.fid = cpu_to_le16(0xffff); | |
6392 | mutex_lock(&bp->hwrm_cmd_lock); | |
6393 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
6394 | if (rc) | |
6395 | goto func_qcfg_exit; | |
6396 | ||
6397 | #ifdef CONFIG_BNXT_SRIOV | |
6398 | if (BNXT_VF(bp)) { | |
cf6645f8 MC |
6399 | struct bnxt_vf_info *vf = &bp->vf; |
6400 | ||
6401 | vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK; | |
230d1f0d MC |
6402 | } else { |
6403 | bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs); | |
cf6645f8 MC |
6404 | } |
6405 | #endif | |
9315edca MC |
6406 | flags = le16_to_cpu(resp->flags); |
6407 | if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED | | |
6408 | FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) { | |
97381a18 | 6409 | bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT; |
9315edca | 6410 | if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED) |
97381a18 | 6411 | bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT; |
9315edca MC |
6412 | } |
6413 | if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)) | |
6414 | bp->flags |= BNXT_FLAG_MULTI_HOST; | |
bc39f885 | 6415 | |
567b2abe SB |
6416 | switch (resp->port_partition_type) { |
6417 | case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0: | |
6418 | case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5: | |
6419 | case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0: | |
6420 | bp->port_partition_type = resp->port_partition_type; | |
6421 | break; | |
6422 | } | |
32e8239c MC |
6423 | if (bp->hwrm_spec_code < 0x10707 || |
6424 | resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB) | |
6425 | bp->br_mode = BRIDGE_MODE_VEB; | |
6426 | else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA) | |
6427 | bp->br_mode = BRIDGE_MODE_VEPA; | |
6428 | else | |
6429 | bp->br_mode = BRIDGE_MODE_UNDEF; | |
cf6645f8 | 6430 | |
7eb9bb3a MC |
6431 | bp->max_mtu = le16_to_cpu(resp->max_mtu_configured); |
6432 | if (!bp->max_mtu) | |
6433 | bp->max_mtu = BNXT_MAX_MTU; | |
6434 | ||
cf6645f8 MC |
6435 | func_qcfg_exit: |
6436 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6437 | return rc; | |
6438 | } | |
6439 | ||
98f04cf0 MC |
6440 | static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp) |
6441 | { | |
6442 | struct hwrm_func_backing_store_qcaps_input req = {0}; | |
6443 | struct hwrm_func_backing_store_qcaps_output *resp = | |
6444 | bp->hwrm_cmd_resp_addr; | |
6445 | int rc; | |
6446 | ||
6447 | if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx) | |
6448 | return 0; | |
6449 | ||
6450 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1); | |
6451 | mutex_lock(&bp->hwrm_cmd_lock); | |
6452 | rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
6453 | if (!rc) { | |
6454 | struct bnxt_ctx_pg_info *ctx_pg; | |
6455 | struct bnxt_ctx_mem_info *ctx; | |
6456 | int i; | |
6457 | ||
6458 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); | |
6459 | if (!ctx) { | |
6460 | rc = -ENOMEM; | |
6461 | goto ctx_err; | |
6462 | } | |
6463 | ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL); | |
6464 | if (!ctx_pg) { | |
6465 | kfree(ctx); | |
6466 | rc = -ENOMEM; | |
6467 | goto ctx_err; | |
6468 | } | |
6469 | for (i = 0; i < bp->max_q + 1; i++, ctx_pg++) | |
6470 | ctx->tqm_mem[i] = ctx_pg; | |
6471 | ||
6472 | bp->ctx = ctx; | |
6473 | ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries); | |
6474 | ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries); | |
6475 | ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries); | |
6476 | ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size); | |
6477 | ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries); | |
6478 | ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries); | |
6479 | ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size); | |
6480 | ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries); | |
6481 | ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries); | |
6482 | ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size); | |
6483 | ctx->vnic_max_vnic_entries = | |
6484 | le16_to_cpu(resp->vnic_max_vnic_entries); | |
6485 | ctx->vnic_max_ring_table_entries = | |
6486 | le16_to_cpu(resp->vnic_max_ring_table_entries); | |
6487 | ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size); | |
6488 | ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries); | |
6489 | ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size); | |
6490 | ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size); | |
6491 | ctx->tqm_min_entries_per_ring = | |
6492 | le32_to_cpu(resp->tqm_min_entries_per_ring); | |
6493 | ctx->tqm_max_entries_per_ring = | |
6494 | le32_to_cpu(resp->tqm_max_entries_per_ring); | |
6495 | ctx->tqm_entries_multiple = resp->tqm_entries_multiple; | |
6496 | if (!ctx->tqm_entries_multiple) | |
6497 | ctx->tqm_entries_multiple = 1; | |
6498 | ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries); | |
6499 | ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size); | |
53579e37 DS |
6500 | ctx->mrav_num_entries_units = |
6501 | le16_to_cpu(resp->mrav_num_entries_units); | |
98f04cf0 MC |
6502 | ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size); |
6503 | ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries); | |
3be8136c | 6504 | ctx->ctx_kind_initializer = resp->ctx_kind_initializer; |
98f04cf0 MC |
6505 | } else { |
6506 | rc = 0; | |
6507 | } | |
6508 | ctx_err: | |
6509 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6510 | return rc; | |
6511 | } | |
6512 | ||
1b9394e5 MC |
6513 | static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr, |
6514 | __le64 *pg_dir) | |
6515 | { | |
6516 | u8 pg_size = 0; | |
6517 | ||
6518 | if (BNXT_PAGE_SHIFT == 13) | |
6519 | pg_size = 1 << 4; | |
6520 | else if (BNXT_PAGE_SIZE == 16) | |
6521 | pg_size = 2 << 4; | |
6522 | ||
6523 | *pg_attr = pg_size; | |
08fe9d18 MC |
6524 | if (rmem->depth >= 1) { |
6525 | if (rmem->depth == 2) | |
6526 | *pg_attr |= 2; | |
6527 | else | |
6528 | *pg_attr |= 1; | |
1b9394e5 MC |
6529 | *pg_dir = cpu_to_le64(rmem->pg_tbl_map); |
6530 | } else { | |
6531 | *pg_dir = cpu_to_le64(rmem->dma_arr[0]); | |
6532 | } | |
6533 | } | |
6534 | ||
6535 | #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \ | |
6536 | (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \ | |
6537 | FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \ | |
6538 | FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \ | |
6539 | FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \ | |
6540 | FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) | |
6541 | ||
6542 | static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables) | |
6543 | { | |
6544 | struct hwrm_func_backing_store_cfg_input req = {0}; | |
6545 | struct bnxt_ctx_mem_info *ctx = bp->ctx; | |
6546 | struct bnxt_ctx_pg_info *ctx_pg; | |
6547 | __le32 *num_entries; | |
6548 | __le64 *pg_dir; | |
53579e37 | 6549 | u32 flags = 0; |
1b9394e5 MC |
6550 | u8 *pg_attr; |
6551 | int i, rc; | |
6552 | u32 ena; | |
6553 | ||
6554 | if (!ctx) | |
6555 | return 0; | |
6556 | ||
6557 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1); | |
6558 | req.enables = cpu_to_le32(enables); | |
6559 | ||
6560 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) { | |
6561 | ctx_pg = &ctx->qp_mem; | |
6562 | req.qp_num_entries = cpu_to_le32(ctx_pg->entries); | |
6563 | req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries); | |
6564 | req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries); | |
6565 | req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size); | |
6566 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6567 | &req.qpc_pg_size_qpc_lvl, | |
6568 | &req.qpc_page_dir); | |
6569 | } | |
6570 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) { | |
6571 | ctx_pg = &ctx->srq_mem; | |
6572 | req.srq_num_entries = cpu_to_le32(ctx_pg->entries); | |
6573 | req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries); | |
6574 | req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size); | |
6575 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6576 | &req.srq_pg_size_srq_lvl, | |
6577 | &req.srq_page_dir); | |
6578 | } | |
6579 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) { | |
6580 | ctx_pg = &ctx->cq_mem; | |
6581 | req.cq_num_entries = cpu_to_le32(ctx_pg->entries); | |
6582 | req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries); | |
6583 | req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size); | |
6584 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl, | |
6585 | &req.cq_page_dir); | |
6586 | } | |
6587 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) { | |
6588 | ctx_pg = &ctx->vnic_mem; | |
6589 | req.vnic_num_vnic_entries = | |
6590 | cpu_to_le16(ctx->vnic_max_vnic_entries); | |
6591 | req.vnic_num_ring_table_entries = | |
6592 | cpu_to_le16(ctx->vnic_max_ring_table_entries); | |
6593 | req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size); | |
6594 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6595 | &req.vnic_pg_size_vnic_lvl, | |
6596 | &req.vnic_page_dir); | |
6597 | } | |
6598 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) { | |
6599 | ctx_pg = &ctx->stat_mem; | |
6600 | req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries); | |
6601 | req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size); | |
6602 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6603 | &req.stat_pg_size_stat_lvl, | |
6604 | &req.stat_page_dir); | |
6605 | } | |
cf6daed0 MC |
6606 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) { |
6607 | ctx_pg = &ctx->mrav_mem; | |
6608 | req.mrav_num_entries = cpu_to_le32(ctx_pg->entries); | |
53579e37 DS |
6609 | if (ctx->mrav_num_entries_units) |
6610 | flags |= | |
6611 | FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT; | |
cf6daed0 MC |
6612 | req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size); |
6613 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6614 | &req.mrav_pg_size_mrav_lvl, | |
6615 | &req.mrav_page_dir); | |
6616 | } | |
6617 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) { | |
6618 | ctx_pg = &ctx->tim_mem; | |
6619 | req.tim_num_entries = cpu_to_le32(ctx_pg->entries); | |
6620 | req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size); | |
6621 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6622 | &req.tim_pg_size_tim_lvl, | |
6623 | &req.tim_page_dir); | |
6624 | } | |
1b9394e5 MC |
6625 | for (i = 0, num_entries = &req.tqm_sp_num_entries, |
6626 | pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl, | |
6627 | pg_dir = &req.tqm_sp_page_dir, | |
6628 | ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP; | |
6629 | i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) { | |
6630 | if (!(enables & ena)) | |
6631 | continue; | |
6632 | ||
6633 | req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size); | |
6634 | ctx_pg = ctx->tqm_mem[i]; | |
6635 | *num_entries = cpu_to_le32(ctx_pg->entries); | |
6636 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir); | |
6637 | } | |
53579e37 | 6638 | req.flags = cpu_to_le32(flags); |
1b9394e5 | 6639 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
1b9394e5 MC |
6640 | return rc; |
6641 | } | |
6642 | ||
98f04cf0 | 6643 | static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, |
08fe9d18 | 6644 | struct bnxt_ctx_pg_info *ctx_pg) |
98f04cf0 MC |
6645 | { |
6646 | struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; | |
6647 | ||
98f04cf0 MC |
6648 | rmem->page_size = BNXT_PAGE_SIZE; |
6649 | rmem->pg_arr = ctx_pg->ctx_pg_arr; | |
6650 | rmem->dma_arr = ctx_pg->ctx_dma_arr; | |
1b9394e5 | 6651 | rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; |
08fe9d18 MC |
6652 | if (rmem->depth >= 1) |
6653 | rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG; | |
98f04cf0 MC |
6654 | return bnxt_alloc_ring(bp, rmem); |
6655 | } | |
6656 | ||
08fe9d18 MC |
6657 | static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp, |
6658 | struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size, | |
3be8136c | 6659 | u8 depth, bool use_init_val) |
08fe9d18 MC |
6660 | { |
6661 | struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; | |
6662 | int rc; | |
6663 | ||
6664 | if (!mem_size) | |
6665 | return 0; | |
6666 | ||
6667 | ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); | |
6668 | if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) { | |
6669 | ctx_pg->nr_pages = 0; | |
6670 | return -EINVAL; | |
6671 | } | |
6672 | if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) { | |
6673 | int nr_tbls, i; | |
6674 | ||
6675 | rmem->depth = 2; | |
6676 | ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg), | |
6677 | GFP_KERNEL); | |
6678 | if (!ctx_pg->ctx_pg_tbl) | |
6679 | return -ENOMEM; | |
6680 | nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES); | |
6681 | rmem->nr_pages = nr_tbls; | |
6682 | rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); | |
6683 | if (rc) | |
6684 | return rc; | |
6685 | for (i = 0; i < nr_tbls; i++) { | |
6686 | struct bnxt_ctx_pg_info *pg_tbl; | |
6687 | ||
6688 | pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL); | |
6689 | if (!pg_tbl) | |
6690 | return -ENOMEM; | |
6691 | ctx_pg->ctx_pg_tbl[i] = pg_tbl; | |
6692 | rmem = &pg_tbl->ring_mem; | |
6693 | rmem->pg_tbl = ctx_pg->ctx_pg_arr[i]; | |
6694 | rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i]; | |
6695 | rmem->depth = 1; | |
6696 | rmem->nr_pages = MAX_CTX_PAGES; | |
3be8136c MC |
6697 | if (use_init_val) |
6698 | rmem->init_val = bp->ctx->ctx_kind_initializer; | |
6ef982de MC |
6699 | if (i == (nr_tbls - 1)) { |
6700 | int rem = ctx_pg->nr_pages % MAX_CTX_PAGES; | |
6701 | ||
6702 | if (rem) | |
6703 | rmem->nr_pages = rem; | |
6704 | } | |
08fe9d18 MC |
6705 | rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl); |
6706 | if (rc) | |
6707 | break; | |
6708 | } | |
6709 | } else { | |
6710 | rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); | |
6711 | if (rmem->nr_pages > 1 || depth) | |
6712 | rmem->depth = 1; | |
3be8136c MC |
6713 | if (use_init_val) |
6714 | rmem->init_val = bp->ctx->ctx_kind_initializer; | |
08fe9d18 MC |
6715 | rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); |
6716 | } | |
6717 | return rc; | |
6718 | } | |
6719 | ||
6720 | static void bnxt_free_ctx_pg_tbls(struct bnxt *bp, | |
6721 | struct bnxt_ctx_pg_info *ctx_pg) | |
6722 | { | |
6723 | struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; | |
6724 | ||
6725 | if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES || | |
6726 | ctx_pg->ctx_pg_tbl) { | |
6727 | int i, nr_tbls = rmem->nr_pages; | |
6728 | ||
6729 | for (i = 0; i < nr_tbls; i++) { | |
6730 | struct bnxt_ctx_pg_info *pg_tbl; | |
6731 | struct bnxt_ring_mem_info *rmem2; | |
6732 | ||
6733 | pg_tbl = ctx_pg->ctx_pg_tbl[i]; | |
6734 | if (!pg_tbl) | |
6735 | continue; | |
6736 | rmem2 = &pg_tbl->ring_mem; | |
6737 | bnxt_free_ring(bp, rmem2); | |
6738 | ctx_pg->ctx_pg_arr[i] = NULL; | |
6739 | kfree(pg_tbl); | |
6740 | ctx_pg->ctx_pg_tbl[i] = NULL; | |
6741 | } | |
6742 | kfree(ctx_pg->ctx_pg_tbl); | |
6743 | ctx_pg->ctx_pg_tbl = NULL; | |
6744 | } | |
6745 | bnxt_free_ring(bp, rmem); | |
6746 | ctx_pg->nr_pages = 0; | |
6747 | } | |
6748 | ||
98f04cf0 MC |
6749 | static void bnxt_free_ctx_mem(struct bnxt *bp) |
6750 | { | |
6751 | struct bnxt_ctx_mem_info *ctx = bp->ctx; | |
6752 | int i; | |
6753 | ||
6754 | if (!ctx) | |
6755 | return; | |
6756 | ||
6757 | if (ctx->tqm_mem[0]) { | |
6758 | for (i = 0; i < bp->max_q + 1; i++) | |
08fe9d18 | 6759 | bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]); |
98f04cf0 MC |
6760 | kfree(ctx->tqm_mem[0]); |
6761 | ctx->tqm_mem[0] = NULL; | |
6762 | } | |
6763 | ||
cf6daed0 MC |
6764 | bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem); |
6765 | bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem); | |
08fe9d18 MC |
6766 | bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem); |
6767 | bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem); | |
6768 | bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem); | |
6769 | bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem); | |
6770 | bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem); | |
98f04cf0 MC |
6771 | ctx->flags &= ~BNXT_CTX_FLAG_INITED; |
6772 | } | |
6773 | ||
6774 | static int bnxt_alloc_ctx_mem(struct bnxt *bp) | |
6775 | { | |
6776 | struct bnxt_ctx_pg_info *ctx_pg; | |
6777 | struct bnxt_ctx_mem_info *ctx; | |
1b9394e5 | 6778 | u32 mem_size, ena, entries; |
53579e37 | 6779 | u32 num_mr, num_ah; |
cf6daed0 MC |
6780 | u32 extra_srqs = 0; |
6781 | u32 extra_qps = 0; | |
6782 | u8 pg_lvl = 1; | |
98f04cf0 MC |
6783 | int i, rc; |
6784 | ||
6785 | rc = bnxt_hwrm_func_backing_store_qcaps(bp); | |
6786 | if (rc) { | |
6787 | netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n", | |
6788 | rc); | |
6789 | return rc; | |
6790 | } | |
6791 | ctx = bp->ctx; | |
6792 | if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) | |
6793 | return 0; | |
6794 | ||
d629522e | 6795 | if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) { |
cf6daed0 MC |
6796 | pg_lvl = 2; |
6797 | extra_qps = 65536; | |
6798 | extra_srqs = 8192; | |
6799 | } | |
6800 | ||
98f04cf0 | 6801 | ctx_pg = &ctx->qp_mem; |
cf6daed0 MC |
6802 | ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries + |
6803 | extra_qps; | |
98f04cf0 | 6804 | mem_size = ctx->qp_entry_size * ctx_pg->entries; |
3be8136c | 6805 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); |
98f04cf0 MC |
6806 | if (rc) |
6807 | return rc; | |
6808 | ||
6809 | ctx_pg = &ctx->srq_mem; | |
cf6daed0 | 6810 | ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs; |
98f04cf0 | 6811 | mem_size = ctx->srq_entry_size * ctx_pg->entries; |
3be8136c | 6812 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); |
98f04cf0 MC |
6813 | if (rc) |
6814 | return rc; | |
6815 | ||
6816 | ctx_pg = &ctx->cq_mem; | |
cf6daed0 | 6817 | ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2; |
98f04cf0 | 6818 | mem_size = ctx->cq_entry_size * ctx_pg->entries; |
3be8136c | 6819 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); |
98f04cf0 MC |
6820 | if (rc) |
6821 | return rc; | |
6822 | ||
6823 | ctx_pg = &ctx->vnic_mem; | |
6824 | ctx_pg->entries = ctx->vnic_max_vnic_entries + | |
6825 | ctx->vnic_max_ring_table_entries; | |
6826 | mem_size = ctx->vnic_entry_size * ctx_pg->entries; | |
3be8136c | 6827 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true); |
98f04cf0 MC |
6828 | if (rc) |
6829 | return rc; | |
6830 | ||
6831 | ctx_pg = &ctx->stat_mem; | |
6832 | ctx_pg->entries = ctx->stat_max_entries; | |
6833 | mem_size = ctx->stat_entry_size * ctx_pg->entries; | |
3be8136c | 6834 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true); |
98f04cf0 MC |
6835 | if (rc) |
6836 | return rc; | |
6837 | ||
cf6daed0 MC |
6838 | ena = 0; |
6839 | if (!(bp->flags & BNXT_FLAG_ROCE_CAP)) | |
6840 | goto skip_rdma; | |
6841 | ||
6842 | ctx_pg = &ctx->mrav_mem; | |
53579e37 DS |
6843 | /* 128K extra is needed to accommodate static AH context |
6844 | * allocation by f/w. | |
6845 | */ | |
6846 | num_mr = 1024 * 256; | |
6847 | num_ah = 1024 * 128; | |
6848 | ctx_pg->entries = num_mr + num_ah; | |
cf6daed0 | 6849 | mem_size = ctx->mrav_entry_size * ctx_pg->entries; |
3be8136c | 6850 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, true); |
cf6daed0 MC |
6851 | if (rc) |
6852 | return rc; | |
6853 | ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV; | |
53579e37 DS |
6854 | if (ctx->mrav_num_entries_units) |
6855 | ctx_pg->entries = | |
6856 | ((num_mr / ctx->mrav_num_entries_units) << 16) | | |
6857 | (num_ah / ctx->mrav_num_entries_units); | |
cf6daed0 MC |
6858 | |
6859 | ctx_pg = &ctx->tim_mem; | |
6860 | ctx_pg->entries = ctx->qp_mem.entries; | |
6861 | mem_size = ctx->tim_entry_size * ctx_pg->entries; | |
3be8136c | 6862 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false); |
cf6daed0 MC |
6863 | if (rc) |
6864 | return rc; | |
6865 | ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM; | |
6866 | ||
6867 | skip_rdma: | |
6868 | entries = ctx->qp_max_l2_entries + extra_qps; | |
98f04cf0 MC |
6869 | entries = roundup(entries, ctx->tqm_entries_multiple); |
6870 | entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring, | |
6871 | ctx->tqm_max_entries_per_ring); | |
cf6daed0 | 6872 | for (i = 0; i < bp->max_q + 1; i++) { |
98f04cf0 MC |
6873 | ctx_pg = ctx->tqm_mem[i]; |
6874 | ctx_pg->entries = entries; | |
6875 | mem_size = ctx->tqm_entry_size * entries; | |
3be8136c | 6876 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false); |
98f04cf0 MC |
6877 | if (rc) |
6878 | return rc; | |
1b9394e5 | 6879 | ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i; |
98f04cf0 | 6880 | } |
1b9394e5 MC |
6881 | ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES; |
6882 | rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); | |
6883 | if (rc) | |
6884 | netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n", | |
6885 | rc); | |
6886 | else | |
6887 | ctx->flags |= BNXT_CTX_FLAG_INITED; | |
6888 | ||
98f04cf0 MC |
6889 | return 0; |
6890 | } | |
6891 | ||
db4723b3 | 6892 | int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all) |
be0dd9c4 MC |
6893 | { |
6894 | struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
6895 | struct hwrm_func_resource_qcaps_input req = {0}; | |
6896 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
6897 | int rc; | |
6898 | ||
6899 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1); | |
6900 | req.fid = cpu_to_le16(0xffff); | |
6901 | ||
6902 | mutex_lock(&bp->hwrm_cmd_lock); | |
351cbde9 JT |
6903 | rc = _hwrm_send_message_silent(bp, &req, sizeof(req), |
6904 | HWRM_CMD_TIMEOUT); | |
d4f1420d | 6905 | if (rc) |
be0dd9c4 | 6906 | goto hwrm_func_resc_qcaps_exit; |
be0dd9c4 | 6907 | |
db4723b3 MC |
6908 | hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs); |
6909 | if (!all) | |
6910 | goto hwrm_func_resc_qcaps_exit; | |
6911 | ||
be0dd9c4 MC |
6912 | hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx); |
6913 | hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); | |
6914 | hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings); | |
6915 | hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); | |
6916 | hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings); | |
6917 | hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); | |
6918 | hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings); | |
6919 | hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); | |
6920 | hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps); | |
6921 | hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps); | |
6922 | hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs); | |
6923 | hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); | |
6924 | hw_resc->min_vnics = le16_to_cpu(resp->min_vnics); | |
6925 | hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); | |
6926 | hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx); | |
6927 | hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); | |
6928 | ||
9c1fabdf MC |
6929 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
6930 | u16 max_msix = le16_to_cpu(resp->max_msix); | |
6931 | ||
f7588cd8 | 6932 | hw_resc->max_nqs = max_msix; |
9c1fabdf MC |
6933 | hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings; |
6934 | } | |
6935 | ||
4673d664 MC |
6936 | if (BNXT_PF(bp)) { |
6937 | struct bnxt_pf_info *pf = &bp->pf; | |
6938 | ||
6939 | pf->vf_resv_strategy = | |
6940 | le16_to_cpu(resp->vf_reservation_strategy); | |
bf82736d | 6941 | if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC) |
4673d664 MC |
6942 | pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL; |
6943 | } | |
be0dd9c4 MC |
6944 | hwrm_func_resc_qcaps_exit: |
6945 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6946 | return rc; | |
6947 | } | |
6948 | ||
6949 | static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) | |
c0c050c5 MC |
6950 | { |
6951 | int rc = 0; | |
6952 | struct hwrm_func_qcaps_input req = {0}; | |
6953 | struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
6a4f2947 MC |
6954 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; |
6955 | u32 flags; | |
c0c050c5 MC |
6956 | |
6957 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1); | |
6958 | req.fid = cpu_to_le16(0xffff); | |
6959 | ||
6960 | mutex_lock(&bp->hwrm_cmd_lock); | |
6961 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
6962 | if (rc) | |
6963 | goto hwrm_func_qcaps_exit; | |
6964 | ||
6a4f2947 MC |
6965 | flags = le32_to_cpu(resp->flags); |
6966 | if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED) | |
e4060d30 | 6967 | bp->flags |= BNXT_FLAG_ROCEV1_CAP; |
6a4f2947 | 6968 | if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED) |
e4060d30 | 6969 | bp->flags |= BNXT_FLAG_ROCEV2_CAP; |
55e4398d VV |
6970 | if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED) |
6971 | bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED; | |
0a3f4e4f VV |
6972 | if (flags & FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE) |
6973 | bp->fw_cap |= BNXT_FW_CAP_HOT_RESET; | |
6154532f VV |
6974 | if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED) |
6975 | bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED; | |
07f83d72 MC |
6976 | if (flags & FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE) |
6977 | bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY; | |
4037eb71 VV |
6978 | if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD) |
6979 | bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD; | |
e4060d30 | 6980 | |
7cc5a20e | 6981 | bp->tx_push_thresh = 0; |
6a4f2947 | 6982 | if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) |
7cc5a20e MC |
6983 | bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; |
6984 | ||
6a4f2947 MC |
6985 | hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); |
6986 | hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); | |
6987 | hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); | |
6988 | hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); | |
6989 | hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); | |
6990 | if (!hw_resc->max_hw_ring_grps) | |
6991 | hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings; | |
6992 | hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); | |
6993 | hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); | |
6994 | hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); | |
6995 | ||
c0c050c5 MC |
6996 | if (BNXT_PF(bp)) { |
6997 | struct bnxt_pf_info *pf = &bp->pf; | |
6998 | ||
6999 | pf->fw_fid = le16_to_cpu(resp->fid); | |
7000 | pf->port_id = le16_to_cpu(resp->port_id); | |
11f15ed3 | 7001 | memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN); |
c0c050c5 MC |
7002 | pf->first_vf_id = le16_to_cpu(resp->first_vf_id); |
7003 | pf->max_vfs = le16_to_cpu(resp->max_vfs); | |
7004 | pf->max_encap_records = le32_to_cpu(resp->max_encap_records); | |
7005 | pf->max_decap_records = le32_to_cpu(resp->max_decap_records); | |
7006 | pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); | |
7007 | pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); | |
7008 | pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); | |
7009 | pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); | |
ba642ab7 | 7010 | bp->flags &= ~BNXT_FLAG_WOL_CAP; |
6a4f2947 | 7011 | if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED) |
c1ef146a | 7012 | bp->flags |= BNXT_FLAG_WOL_CAP; |
c0c050c5 | 7013 | } else { |
379a80a1 | 7014 | #ifdef CONFIG_BNXT_SRIOV |
c0c050c5 MC |
7015 | struct bnxt_vf_info *vf = &bp->vf; |
7016 | ||
7017 | vf->fw_fid = le16_to_cpu(resp->fid); | |
7cc5a20e | 7018 | memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN); |
379a80a1 | 7019 | #endif |
c0c050c5 MC |
7020 | } |
7021 | ||
c0c050c5 MC |
7022 | hwrm_func_qcaps_exit: |
7023 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7024 | return rc; | |
7025 | } | |
7026 | ||
804fba4e MC |
7027 | static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp); |
7028 | ||
be0dd9c4 MC |
7029 | static int bnxt_hwrm_func_qcaps(struct bnxt *bp) |
7030 | { | |
7031 | int rc; | |
7032 | ||
7033 | rc = __bnxt_hwrm_func_qcaps(bp); | |
7034 | if (rc) | |
7035 | return rc; | |
804fba4e MC |
7036 | rc = bnxt_hwrm_queue_qportcfg(bp); |
7037 | if (rc) { | |
7038 | netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc); | |
7039 | return rc; | |
7040 | } | |
be0dd9c4 | 7041 | if (bp->hwrm_spec_code >= 0x10803) { |
98f04cf0 MC |
7042 | rc = bnxt_alloc_ctx_mem(bp); |
7043 | if (rc) | |
7044 | return rc; | |
db4723b3 | 7045 | rc = bnxt_hwrm_func_resc_qcaps(bp, true); |
be0dd9c4 | 7046 | if (!rc) |
97381a18 | 7047 | bp->fw_cap |= BNXT_FW_CAP_NEW_RM; |
be0dd9c4 MC |
7048 | } |
7049 | return 0; | |
7050 | } | |
7051 | ||
e969ae5b MC |
7052 | static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp) |
7053 | { | |
7054 | struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0}; | |
7055 | struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp; | |
7056 | int rc = 0; | |
7057 | u32 flags; | |
7058 | ||
7059 | if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW)) | |
7060 | return 0; | |
7061 | ||
7062 | resp = bp->hwrm_cmd_resp_addr; | |
7063 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1); | |
7064 | ||
7065 | mutex_lock(&bp->hwrm_cmd_lock); | |
7066 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7067 | if (rc) | |
7068 | goto hwrm_cfa_adv_qcaps_exit; | |
7069 | ||
7070 | flags = le32_to_cpu(resp->flags); | |
7071 | if (flags & | |
41136ab3 MC |
7072 | CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED) |
7073 | bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2; | |
e969ae5b MC |
7074 | |
7075 | hwrm_cfa_adv_qcaps_exit: | |
7076 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7077 | return rc; | |
7078 | } | |
7079 | ||
9ffbd677 MC |
7080 | static int bnxt_map_fw_health_regs(struct bnxt *bp) |
7081 | { | |
7082 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
7083 | u32 reg_base = 0xffffffff; | |
7084 | int i; | |
7085 | ||
7086 | /* Only pre-map the monitoring GRC registers using window 3 */ | |
7087 | for (i = 0; i < 4; i++) { | |
7088 | u32 reg = fw_health->regs[i]; | |
7089 | ||
7090 | if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC) | |
7091 | continue; | |
7092 | if (reg_base == 0xffffffff) | |
7093 | reg_base = reg & BNXT_GRC_BASE_MASK; | |
7094 | if ((reg & BNXT_GRC_BASE_MASK) != reg_base) | |
7095 | return -ERANGE; | |
7096 | fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_BASE + | |
7097 | (reg & BNXT_GRC_OFFSET_MASK); | |
7098 | } | |
7099 | if (reg_base == 0xffffffff) | |
7100 | return 0; | |
7101 | ||
7102 | writel(reg_base, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + | |
7103 | BNXT_FW_HEALTH_WIN_MAP_OFF); | |
7104 | return 0; | |
7105 | } | |
7106 | ||
07f83d72 MC |
7107 | static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp) |
7108 | { | |
7109 | struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
7110 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
7111 | struct hwrm_error_recovery_qcfg_input req = {0}; | |
7112 | int rc, i; | |
7113 | ||
7114 | if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) | |
7115 | return 0; | |
7116 | ||
7117 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_ERROR_RECOVERY_QCFG, -1, -1); | |
7118 | mutex_lock(&bp->hwrm_cmd_lock); | |
7119 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7120 | if (rc) | |
7121 | goto err_recovery_out; | |
07f83d72 MC |
7122 | fw_health->flags = le32_to_cpu(resp->flags); |
7123 | if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) && | |
7124 | !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) { | |
7125 | rc = -EINVAL; | |
7126 | goto err_recovery_out; | |
7127 | } | |
7128 | fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq); | |
7129 | fw_health->master_func_wait_dsecs = | |
7130 | le32_to_cpu(resp->master_func_wait_period); | |
7131 | fw_health->normal_func_wait_dsecs = | |
7132 | le32_to_cpu(resp->normal_func_wait_period); | |
7133 | fw_health->post_reset_wait_dsecs = | |
7134 | le32_to_cpu(resp->master_func_wait_period_after_reset); | |
7135 | fw_health->post_reset_max_wait_dsecs = | |
7136 | le32_to_cpu(resp->max_bailout_time_after_reset); | |
7137 | fw_health->regs[BNXT_FW_HEALTH_REG] = | |
7138 | le32_to_cpu(resp->fw_health_status_reg); | |
7139 | fw_health->regs[BNXT_FW_HEARTBEAT_REG] = | |
7140 | le32_to_cpu(resp->fw_heartbeat_reg); | |
7141 | fw_health->regs[BNXT_FW_RESET_CNT_REG] = | |
7142 | le32_to_cpu(resp->fw_reset_cnt_reg); | |
7143 | fw_health->regs[BNXT_FW_RESET_INPROG_REG] = | |
7144 | le32_to_cpu(resp->reset_inprogress_reg); | |
7145 | fw_health->fw_reset_inprog_reg_mask = | |
7146 | le32_to_cpu(resp->reset_inprogress_reg_mask); | |
7147 | fw_health->fw_reset_seq_cnt = resp->reg_array_cnt; | |
7148 | if (fw_health->fw_reset_seq_cnt >= 16) { | |
7149 | rc = -EINVAL; | |
7150 | goto err_recovery_out; | |
7151 | } | |
7152 | for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) { | |
7153 | fw_health->fw_reset_seq_regs[i] = | |
7154 | le32_to_cpu(resp->reset_reg[i]); | |
7155 | fw_health->fw_reset_seq_vals[i] = | |
7156 | le32_to_cpu(resp->reset_reg_val[i]); | |
7157 | fw_health->fw_reset_seq_delay_msec[i] = | |
7158 | resp->delay_after_reset[i]; | |
7159 | } | |
7160 | err_recovery_out: | |
7161 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9ffbd677 MC |
7162 | if (!rc) |
7163 | rc = bnxt_map_fw_health_regs(bp); | |
07f83d72 MC |
7164 | if (rc) |
7165 | bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; | |
7166 | return rc; | |
7167 | } | |
7168 | ||
c0c050c5 MC |
7169 | static int bnxt_hwrm_func_reset(struct bnxt *bp) |
7170 | { | |
7171 | struct hwrm_func_reset_input req = {0}; | |
7172 | ||
7173 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1); | |
7174 | req.enables = 0; | |
7175 | ||
7176 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT); | |
7177 | } | |
7178 | ||
7179 | static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) | |
7180 | { | |
7181 | int rc = 0; | |
7182 | struct hwrm_queue_qportcfg_input req = {0}; | |
7183 | struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
aabfc016 MC |
7184 | u8 i, j, *qptr; |
7185 | bool no_rdma; | |
c0c050c5 MC |
7186 | |
7187 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1); | |
7188 | ||
7189 | mutex_lock(&bp->hwrm_cmd_lock); | |
7190 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7191 | if (rc) | |
7192 | goto qportcfg_exit; | |
7193 | ||
7194 | if (!resp->max_configurable_queues) { | |
7195 | rc = -EINVAL; | |
7196 | goto qportcfg_exit; | |
7197 | } | |
7198 | bp->max_tc = resp->max_configurable_queues; | |
87c374de | 7199 | bp->max_lltc = resp->max_configurable_lossless_queues; |
c0c050c5 MC |
7200 | if (bp->max_tc > BNXT_MAX_QUEUE) |
7201 | bp->max_tc = BNXT_MAX_QUEUE; | |
7202 | ||
aabfc016 MC |
7203 | no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP); |
7204 | qptr = &resp->queue_id0; | |
7205 | for (i = 0, j = 0; i < bp->max_tc; i++) { | |
98f04cf0 MC |
7206 | bp->q_info[j].queue_id = *qptr; |
7207 | bp->q_ids[i] = *qptr++; | |
aabfc016 MC |
7208 | bp->q_info[j].queue_profile = *qptr++; |
7209 | bp->tc_to_qidx[j] = j; | |
7210 | if (!BNXT_CNPQ(bp->q_info[j].queue_profile) || | |
7211 | (no_rdma && BNXT_PF(bp))) | |
7212 | j++; | |
7213 | } | |
98f04cf0 | 7214 | bp->max_q = bp->max_tc; |
aabfc016 MC |
7215 | bp->max_tc = max_t(u8, j, 1); |
7216 | ||
441cabbb MC |
7217 | if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) |
7218 | bp->max_tc = 1; | |
7219 | ||
87c374de MC |
7220 | if (bp->max_lltc > bp->max_tc) |
7221 | bp->max_lltc = bp->max_tc; | |
7222 | ||
c0c050c5 MC |
7223 | qportcfg_exit: |
7224 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7225 | return rc; | |
7226 | } | |
7227 | ||
ba642ab7 | 7228 | static int __bnxt_hwrm_ver_get(struct bnxt *bp, bool silent) |
c0c050c5 | 7229 | { |
c0c050c5 | 7230 | struct hwrm_ver_get_input req = {0}; |
ba642ab7 | 7231 | int rc; |
c0c050c5 MC |
7232 | |
7233 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1); | |
7234 | req.hwrm_intf_maj = HWRM_VERSION_MAJOR; | |
7235 | req.hwrm_intf_min = HWRM_VERSION_MINOR; | |
7236 | req.hwrm_intf_upd = HWRM_VERSION_UPDATE; | |
ba642ab7 MC |
7237 | |
7238 | rc = bnxt_hwrm_do_send_msg(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT, | |
7239 | silent); | |
7240 | return rc; | |
7241 | } | |
7242 | ||
7243 | static int bnxt_hwrm_ver_get(struct bnxt *bp) | |
7244 | { | |
7245 | struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr; | |
7246 | u32 dev_caps_cfg; | |
7247 | int rc; | |
7248 | ||
7249 | bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN; | |
c0c050c5 | 7250 | mutex_lock(&bp->hwrm_cmd_lock); |
ba642ab7 | 7251 | rc = __bnxt_hwrm_ver_get(bp, false); |
c0c050c5 MC |
7252 | if (rc) |
7253 | goto hwrm_ver_get_exit; | |
7254 | ||
7255 | memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); | |
7256 | ||
894aa69a MC |
7257 | bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 | |
7258 | resp->hwrm_intf_min_8b << 8 | | |
7259 | resp->hwrm_intf_upd_8b; | |
7260 | if (resp->hwrm_intf_maj_8b < 1) { | |
c193554e | 7261 | netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", |
894aa69a MC |
7262 | resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, |
7263 | resp->hwrm_intf_upd_8b); | |
c193554e | 7264 | netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); |
c0c050c5 | 7265 | } |
431aa1eb | 7266 | snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d", |
894aa69a MC |
7267 | resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b, |
7268 | resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b); | |
c0c050c5 | 7269 | |
691aa620 VV |
7270 | if (strlen(resp->active_pkg_name)) { |
7271 | int fw_ver_len = strlen(bp->fw_ver_str); | |
7272 | ||
7273 | snprintf(bp->fw_ver_str + fw_ver_len, | |
7274 | FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s", | |
7275 | resp->active_pkg_name); | |
7276 | bp->fw_cap |= BNXT_FW_CAP_PKG_VER; | |
7277 | } | |
7278 | ||
ff4fe81d MC |
7279 | bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout); |
7280 | if (!bp->hwrm_cmd_timeout) | |
7281 | bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; | |
7282 | ||
1dfddc41 | 7283 | if (resp->hwrm_intf_maj_8b >= 1) { |
e6ef2699 | 7284 | bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len); |
1dfddc41 MC |
7285 | bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len); |
7286 | } | |
7287 | if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN) | |
7288 | bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN; | |
e6ef2699 | 7289 | |
659c805c | 7290 | bp->chip_num = le16_to_cpu(resp->chip_num); |
3e8060fa PS |
7291 | if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev && |
7292 | !resp->chip_metal) | |
7293 | bp->flags |= BNXT_FLAG_CHIP_NITRO_A0; | |
659c805c | 7294 | |
e605db80 DK |
7295 | dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg); |
7296 | if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && | |
7297 | (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) | |
97381a18 | 7298 | bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD; |
e605db80 | 7299 | |
760b6d33 VD |
7300 | if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) |
7301 | bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL; | |
7302 | ||
abd43a13 VD |
7303 | if (dev_caps_cfg & |
7304 | VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED) | |
7305 | bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE; | |
7306 | ||
2a516444 MC |
7307 | if (dev_caps_cfg & |
7308 | VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED) | |
7309 | bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF; | |
7310 | ||
e969ae5b MC |
7311 | if (dev_caps_cfg & |
7312 | VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) | |
7313 | bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW; | |
7314 | ||
c0c050c5 MC |
7315 | hwrm_ver_get_exit: |
7316 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7317 | return rc; | |
7318 | } | |
7319 | ||
5ac67d8b RS |
7320 | int bnxt_hwrm_fw_set_time(struct bnxt *bp) |
7321 | { | |
7322 | struct hwrm_fw_set_time_input req = {0}; | |
7dfaa7bc AB |
7323 | struct tm tm; |
7324 | time64_t now = ktime_get_real_seconds(); | |
5ac67d8b | 7325 | |
ca2c39e2 MC |
7326 | if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) || |
7327 | bp->hwrm_spec_code < 0x10400) | |
5ac67d8b RS |
7328 | return -EOPNOTSUPP; |
7329 | ||
7dfaa7bc | 7330 | time64_to_tm(now, 0, &tm); |
5ac67d8b RS |
7331 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1); |
7332 | req.year = cpu_to_le16(1900 + tm.tm_year); | |
7333 | req.month = 1 + tm.tm_mon; | |
7334 | req.day = tm.tm_mday; | |
7335 | req.hour = tm.tm_hour; | |
7336 | req.minute = tm.tm_min; | |
7337 | req.second = tm.tm_sec; | |
7338 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7339 | } | |
7340 | ||
3bdf56c4 MC |
7341 | static int bnxt_hwrm_port_qstats(struct bnxt *bp) |
7342 | { | |
7343 | int rc; | |
7344 | struct bnxt_pf_info *pf = &bp->pf; | |
7345 | struct hwrm_port_qstats_input req = {0}; | |
7346 | ||
7347 | if (!(bp->flags & BNXT_FLAG_PORT_STATS)) | |
7348 | return 0; | |
7349 | ||
7350 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1); | |
7351 | req.port_id = cpu_to_le16(pf->port_id); | |
7352 | req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map); | |
7353 | req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map); | |
7354 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7355 | return rc; | |
7356 | } | |
7357 | ||
00db3cba VV |
7358 | static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp) |
7359 | { | |
36e53349 | 7360 | struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr; |
e37fed79 | 7361 | struct hwrm_queue_pri2cos_qcfg_input req2 = {0}; |
00db3cba VV |
7362 | struct hwrm_port_qstats_ext_input req = {0}; |
7363 | struct bnxt_pf_info *pf = &bp->pf; | |
ad361adf | 7364 | u32 tx_stat_size; |
36e53349 | 7365 | int rc; |
00db3cba VV |
7366 | |
7367 | if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) | |
7368 | return 0; | |
7369 | ||
7370 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1); | |
7371 | req.port_id = cpu_to_le16(pf->port_id); | |
7372 | req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext)); | |
7373 | req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map); | |
ad361adf MC |
7374 | tx_stat_size = bp->hw_tx_port_stats_ext ? |
7375 | sizeof(*bp->hw_tx_port_stats_ext) : 0; | |
7376 | req.tx_stat_size = cpu_to_le16(tx_stat_size); | |
36e53349 MC |
7377 | req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map); |
7378 | mutex_lock(&bp->hwrm_cmd_lock); | |
7379 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7380 | if (!rc) { | |
7381 | bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8; | |
ad361adf MC |
7382 | bp->fw_tx_stats_ext_size = tx_stat_size ? |
7383 | le16_to_cpu(resp->tx_stat_size) / 8 : 0; | |
36e53349 MC |
7384 | } else { |
7385 | bp->fw_rx_stats_ext_size = 0; | |
7386 | bp->fw_tx_stats_ext_size = 0; | |
7387 | } | |
e37fed79 MC |
7388 | if (bp->fw_tx_stats_ext_size <= |
7389 | offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) { | |
7390 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7391 | bp->pri2cos_valid = 0; | |
7392 | return rc; | |
7393 | } | |
7394 | ||
7395 | bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1); | |
7396 | req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN); | |
7397 | ||
7398 | rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT); | |
7399 | if (!rc) { | |
7400 | struct hwrm_queue_pri2cos_qcfg_output *resp2; | |
7401 | u8 *pri2cos; | |
7402 | int i, j; | |
7403 | ||
7404 | resp2 = bp->hwrm_cmd_resp_addr; | |
7405 | pri2cos = &resp2->pri0_cos_queue_id; | |
7406 | for (i = 0; i < 8; i++) { | |
7407 | u8 queue_id = pri2cos[i]; | |
7408 | ||
7409 | for (j = 0; j < bp->max_q; j++) { | |
7410 | if (bp->q_ids[j] == queue_id) | |
7411 | bp->pri2cos[i] = j; | |
7412 | } | |
7413 | } | |
7414 | bp->pri2cos_valid = 1; | |
7415 | } | |
36e53349 MC |
7416 | mutex_unlock(&bp->hwrm_cmd_lock); |
7417 | return rc; | |
00db3cba VV |
7418 | } |
7419 | ||
55e4398d VV |
7420 | static int bnxt_hwrm_pcie_qstats(struct bnxt *bp) |
7421 | { | |
7422 | struct hwrm_pcie_qstats_input req = {0}; | |
7423 | ||
7424 | if (!(bp->flags & BNXT_FLAG_PCIE_STATS)) | |
7425 | return 0; | |
7426 | ||
7427 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1); | |
7428 | req.pcie_stat_size = cpu_to_le16(sizeof(struct pcie_ctx_hw_stats)); | |
7429 | req.pcie_stat_host_addr = cpu_to_le64(bp->hw_pcie_stats_map); | |
7430 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7431 | } | |
7432 | ||
c0c050c5 MC |
7433 | static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) |
7434 | { | |
7435 | if (bp->vxlan_port_cnt) { | |
7436 | bnxt_hwrm_tunnel_dst_port_free( | |
7437 | bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); | |
7438 | } | |
7439 | bp->vxlan_port_cnt = 0; | |
7440 | if (bp->nge_port_cnt) { | |
7441 | bnxt_hwrm_tunnel_dst_port_free( | |
7442 | bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); | |
7443 | } | |
7444 | bp->nge_port_cnt = 0; | |
7445 | } | |
7446 | ||
7447 | static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) | |
7448 | { | |
7449 | int rc, i; | |
7450 | u32 tpa_flags = 0; | |
7451 | ||
7452 | if (set_tpa) | |
7453 | tpa_flags = bp->flags & BNXT_FLAG_TPA; | |
b4fff207 MC |
7454 | else if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) |
7455 | return 0; | |
c0c050c5 MC |
7456 | for (i = 0; i < bp->nr_vnics; i++) { |
7457 | rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); | |
7458 | if (rc) { | |
7459 | netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", | |
23e12c89 | 7460 | i, rc); |
c0c050c5 MC |
7461 | return rc; |
7462 | } | |
7463 | } | |
7464 | return 0; | |
7465 | } | |
7466 | ||
7467 | static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) | |
7468 | { | |
7469 | int i; | |
7470 | ||
7471 | for (i = 0; i < bp->nr_vnics; i++) | |
7472 | bnxt_hwrm_vnic_set_rss(bp, i, false); | |
7473 | } | |
7474 | ||
a46ecb11 | 7475 | static void bnxt_clear_vnic(struct bnxt *bp) |
c0c050c5 | 7476 | { |
a46ecb11 MC |
7477 | if (!bp->vnic_info) |
7478 | return; | |
7479 | ||
7480 | bnxt_hwrm_clear_vnic_filter(bp); | |
7481 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) { | |
c0c050c5 MC |
7482 | /* clear all RSS setting before free vnic ctx */ |
7483 | bnxt_hwrm_clear_vnic_rss(bp); | |
7484 | bnxt_hwrm_vnic_ctx_free(bp); | |
c0c050c5 | 7485 | } |
a46ecb11 MC |
7486 | /* before free the vnic, undo the vnic tpa settings */ |
7487 | if (bp->flags & BNXT_FLAG_TPA) | |
7488 | bnxt_set_tpa(bp, false); | |
7489 | bnxt_hwrm_vnic_free(bp); | |
7490 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
7491 | bnxt_hwrm_vnic_ctx_free(bp); | |
7492 | } | |
7493 | ||
7494 | static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, | |
7495 | bool irq_re_init) | |
7496 | { | |
7497 | bnxt_clear_vnic(bp); | |
c0c050c5 MC |
7498 | bnxt_hwrm_ring_free(bp, close_path); |
7499 | bnxt_hwrm_ring_grp_free(bp); | |
7500 | if (irq_re_init) { | |
7501 | bnxt_hwrm_stat_ctx_free(bp); | |
7502 | bnxt_hwrm_free_tunnel_ports(bp); | |
7503 | } | |
7504 | } | |
7505 | ||
39d8ba2e MC |
7506 | static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode) |
7507 | { | |
7508 | struct hwrm_func_cfg_input req = {0}; | |
7509 | int rc; | |
7510 | ||
7511 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); | |
7512 | req.fid = cpu_to_le16(0xffff); | |
7513 | req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE); | |
7514 | if (br_mode == BRIDGE_MODE_VEB) | |
7515 | req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB; | |
7516 | else if (br_mode == BRIDGE_MODE_VEPA) | |
7517 | req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA; | |
7518 | else | |
7519 | return -EINVAL; | |
7520 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
39d8ba2e MC |
7521 | return rc; |
7522 | } | |
7523 | ||
c3480a60 MC |
7524 | static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size) |
7525 | { | |
7526 | struct hwrm_func_cfg_input req = {0}; | |
7527 | int rc; | |
7528 | ||
7529 | if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803) | |
7530 | return 0; | |
7531 | ||
7532 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); | |
7533 | req.fid = cpu_to_le16(0xffff); | |
7534 | req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE); | |
d4f52de0 | 7535 | req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64; |
c3480a60 | 7536 | if (size == 128) |
d4f52de0 | 7537 | req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128; |
c3480a60 MC |
7538 | |
7539 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
c3480a60 MC |
7540 | return rc; |
7541 | } | |
7542 | ||
7b3af4f7 | 7543 | static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) |
c0c050c5 | 7544 | { |
ae10ae74 | 7545 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
c0c050c5 MC |
7546 | int rc; |
7547 | ||
ae10ae74 MC |
7548 | if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) |
7549 | goto skip_rss_ctx; | |
7550 | ||
c0c050c5 | 7551 | /* allocate context for vnic */ |
94ce9caa | 7552 | rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0); |
c0c050c5 MC |
7553 | if (rc) { |
7554 | netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", | |
7555 | vnic_id, rc); | |
7556 | goto vnic_setup_err; | |
7557 | } | |
7558 | bp->rsscos_nr_ctxs++; | |
7559 | ||
94ce9caa PS |
7560 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { |
7561 | rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1); | |
7562 | if (rc) { | |
7563 | netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n", | |
7564 | vnic_id, rc); | |
7565 | goto vnic_setup_err; | |
7566 | } | |
7567 | bp->rsscos_nr_ctxs++; | |
7568 | } | |
7569 | ||
ae10ae74 | 7570 | skip_rss_ctx: |
c0c050c5 MC |
7571 | /* configure default vnic, ring grp */ |
7572 | rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); | |
7573 | if (rc) { | |
7574 | netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", | |
7575 | vnic_id, rc); | |
7576 | goto vnic_setup_err; | |
7577 | } | |
7578 | ||
7579 | /* Enable RSS hashing on vnic */ | |
7580 | rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); | |
7581 | if (rc) { | |
7582 | netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", | |
7583 | vnic_id, rc); | |
7584 | goto vnic_setup_err; | |
7585 | } | |
7586 | ||
7587 | if (bp->flags & BNXT_FLAG_AGG_RINGS) { | |
7588 | rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); | |
7589 | if (rc) { | |
7590 | netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", | |
7591 | vnic_id, rc); | |
7592 | } | |
7593 | } | |
7594 | ||
7595 | vnic_setup_err: | |
7596 | return rc; | |
7597 | } | |
7598 | ||
7b3af4f7 MC |
7599 | static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id) |
7600 | { | |
7601 | int rc, i, nr_ctxs; | |
7602 | ||
7603 | nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64); | |
7604 | for (i = 0; i < nr_ctxs; i++) { | |
7605 | rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i); | |
7606 | if (rc) { | |
7607 | netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n", | |
7608 | vnic_id, i, rc); | |
7609 | break; | |
7610 | } | |
7611 | bp->rsscos_nr_ctxs++; | |
7612 | } | |
7613 | if (i < nr_ctxs) | |
7614 | return -ENOMEM; | |
7615 | ||
7616 | rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true); | |
7617 | if (rc) { | |
7618 | netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n", | |
7619 | vnic_id, rc); | |
7620 | return rc; | |
7621 | } | |
7622 | rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); | |
7623 | if (rc) { | |
7624 | netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", | |
7625 | vnic_id, rc); | |
7626 | return rc; | |
7627 | } | |
7628 | if (bp->flags & BNXT_FLAG_AGG_RINGS) { | |
7629 | rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); | |
7630 | if (rc) { | |
7631 | netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", | |
7632 | vnic_id, rc); | |
7633 | } | |
7634 | } | |
7635 | return rc; | |
7636 | } | |
7637 | ||
7638 | static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) | |
7639 | { | |
7640 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
7641 | return __bnxt_setup_vnic_p5(bp, vnic_id); | |
7642 | else | |
7643 | return __bnxt_setup_vnic(bp, vnic_id); | |
7644 | } | |
7645 | ||
c0c050c5 MC |
7646 | static int bnxt_alloc_rfs_vnics(struct bnxt *bp) |
7647 | { | |
7648 | #ifdef CONFIG_RFS_ACCEL | |
7649 | int i, rc = 0; | |
7650 | ||
9b3d15e6 MC |
7651 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
7652 | return 0; | |
7653 | ||
c0c050c5 | 7654 | for (i = 0; i < bp->rx_nr_rings; i++) { |
ae10ae74 | 7655 | struct bnxt_vnic_info *vnic; |
c0c050c5 MC |
7656 | u16 vnic_id = i + 1; |
7657 | u16 ring_id = i; | |
7658 | ||
7659 | if (vnic_id >= bp->nr_vnics) | |
7660 | break; | |
7661 | ||
ae10ae74 MC |
7662 | vnic = &bp->vnic_info[vnic_id]; |
7663 | vnic->flags |= BNXT_VNIC_RFS_FLAG; | |
7664 | if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) | |
7665 | vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG; | |
b81a90d3 | 7666 | rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); |
c0c050c5 MC |
7667 | if (rc) { |
7668 | netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", | |
7669 | vnic_id, rc); | |
7670 | break; | |
7671 | } | |
7672 | rc = bnxt_setup_vnic(bp, vnic_id); | |
7673 | if (rc) | |
7674 | break; | |
7675 | } | |
7676 | return rc; | |
7677 | #else | |
7678 | return 0; | |
7679 | #endif | |
7680 | } | |
7681 | ||
17c71ac3 MC |
7682 | /* Allow PF and VF with default VLAN to be in promiscuous mode */ |
7683 | static bool bnxt_promisc_ok(struct bnxt *bp) | |
7684 | { | |
7685 | #ifdef CONFIG_BNXT_SRIOV | |
7686 | if (BNXT_VF(bp) && !bp->vf.vlan) | |
7687 | return false; | |
7688 | #endif | |
7689 | return true; | |
7690 | } | |
7691 | ||
dc52c6c7 PS |
7692 | static int bnxt_setup_nitroa0_vnic(struct bnxt *bp) |
7693 | { | |
7694 | unsigned int rc = 0; | |
7695 | ||
7696 | rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1); | |
7697 | if (rc) { | |
7698 | netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", | |
7699 | rc); | |
7700 | return rc; | |
7701 | } | |
7702 | ||
7703 | rc = bnxt_hwrm_vnic_cfg(bp, 1); | |
7704 | if (rc) { | |
7705 | netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", | |
7706 | rc); | |
7707 | return rc; | |
7708 | } | |
7709 | return rc; | |
7710 | } | |
7711 | ||
b664f008 | 7712 | static int bnxt_cfg_rx_mode(struct bnxt *); |
7d2837dd | 7713 | static bool bnxt_mc_list_updated(struct bnxt *, u32 *); |
b664f008 | 7714 | |
c0c050c5 MC |
7715 | static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) |
7716 | { | |
7d2837dd | 7717 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; |
c0c050c5 | 7718 | int rc = 0; |
76595193 | 7719 | unsigned int rx_nr_rings = bp->rx_nr_rings; |
c0c050c5 MC |
7720 | |
7721 | if (irq_re_init) { | |
7722 | rc = bnxt_hwrm_stat_ctx_alloc(bp); | |
7723 | if (rc) { | |
7724 | netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", | |
7725 | rc); | |
7726 | goto err_out; | |
7727 | } | |
7728 | } | |
7729 | ||
7730 | rc = bnxt_hwrm_ring_alloc(bp); | |
7731 | if (rc) { | |
7732 | netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); | |
7733 | goto err_out; | |
7734 | } | |
7735 | ||
7736 | rc = bnxt_hwrm_ring_grp_alloc(bp); | |
7737 | if (rc) { | |
7738 | netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); | |
7739 | goto err_out; | |
7740 | } | |
7741 | ||
76595193 PS |
7742 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) |
7743 | rx_nr_rings--; | |
7744 | ||
c0c050c5 | 7745 | /* default vnic 0 */ |
76595193 | 7746 | rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings); |
c0c050c5 MC |
7747 | if (rc) { |
7748 | netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); | |
7749 | goto err_out; | |
7750 | } | |
7751 | ||
7752 | rc = bnxt_setup_vnic(bp, 0); | |
7753 | if (rc) | |
7754 | goto err_out; | |
7755 | ||
7756 | if (bp->flags & BNXT_FLAG_RFS) { | |
7757 | rc = bnxt_alloc_rfs_vnics(bp); | |
7758 | if (rc) | |
7759 | goto err_out; | |
7760 | } | |
7761 | ||
7762 | if (bp->flags & BNXT_FLAG_TPA) { | |
7763 | rc = bnxt_set_tpa(bp, true); | |
7764 | if (rc) | |
7765 | goto err_out; | |
7766 | } | |
7767 | ||
7768 | if (BNXT_VF(bp)) | |
7769 | bnxt_update_vf_mac(bp); | |
7770 | ||
7771 | /* Filter for default vnic 0 */ | |
7772 | rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); | |
7773 | if (rc) { | |
7774 | netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); | |
7775 | goto err_out; | |
7776 | } | |
7d2837dd | 7777 | vnic->uc_filter_count = 1; |
c0c050c5 | 7778 | |
30e33848 MC |
7779 | vnic->rx_mask = 0; |
7780 | if (bp->dev->flags & IFF_BROADCAST) | |
7781 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; | |
c0c050c5 | 7782 | |
17c71ac3 | 7783 | if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) |
7d2837dd MC |
7784 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; |
7785 | ||
7786 | if (bp->dev->flags & IFF_ALLMULTI) { | |
7787 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; | |
7788 | vnic->mc_list_count = 0; | |
7789 | } else { | |
7790 | u32 mask = 0; | |
7791 | ||
7792 | bnxt_mc_list_updated(bp, &mask); | |
7793 | vnic->rx_mask |= mask; | |
7794 | } | |
c0c050c5 | 7795 | |
b664f008 MC |
7796 | rc = bnxt_cfg_rx_mode(bp); |
7797 | if (rc) | |
c0c050c5 | 7798 | goto err_out; |
c0c050c5 MC |
7799 | |
7800 | rc = bnxt_hwrm_set_coal(bp); | |
7801 | if (rc) | |
7802 | netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", | |
dc52c6c7 PS |
7803 | rc); |
7804 | ||
7805 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { | |
7806 | rc = bnxt_setup_nitroa0_vnic(bp); | |
7807 | if (rc) | |
7808 | netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n", | |
7809 | rc); | |
7810 | } | |
c0c050c5 | 7811 | |
cf6645f8 MC |
7812 | if (BNXT_VF(bp)) { |
7813 | bnxt_hwrm_func_qcfg(bp); | |
7814 | netdev_update_features(bp->dev); | |
7815 | } | |
7816 | ||
c0c050c5 MC |
7817 | return 0; |
7818 | ||
7819 | err_out: | |
7820 | bnxt_hwrm_resource_free(bp, 0, true); | |
7821 | ||
7822 | return rc; | |
7823 | } | |
7824 | ||
7825 | static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) | |
7826 | { | |
7827 | bnxt_hwrm_resource_free(bp, 1, irq_re_init); | |
7828 | return 0; | |
7829 | } | |
7830 | ||
7831 | static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) | |
7832 | { | |
2247925f | 7833 | bnxt_init_cp_rings(bp); |
c0c050c5 MC |
7834 | bnxt_init_rx_rings(bp); |
7835 | bnxt_init_tx_rings(bp); | |
7836 | bnxt_init_ring_grps(bp, irq_re_init); | |
7837 | bnxt_init_vnics(bp); | |
7838 | ||
7839 | return bnxt_init_chip(bp, irq_re_init); | |
7840 | } | |
7841 | ||
c0c050c5 MC |
7842 | static int bnxt_set_real_num_queues(struct bnxt *bp) |
7843 | { | |
7844 | int rc; | |
7845 | struct net_device *dev = bp->dev; | |
7846 | ||
5f449249 MC |
7847 | rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings - |
7848 | bp->tx_nr_rings_xdp); | |
c0c050c5 MC |
7849 | if (rc) |
7850 | return rc; | |
7851 | ||
7852 | rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); | |
7853 | if (rc) | |
7854 | return rc; | |
7855 | ||
7856 | #ifdef CONFIG_RFS_ACCEL | |
45019a18 | 7857 | if (bp->flags & BNXT_FLAG_RFS) |
c0c050c5 | 7858 | dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); |
c0c050c5 MC |
7859 | #endif |
7860 | ||
7861 | return rc; | |
7862 | } | |
7863 | ||
6e6c5a57 MC |
7864 | static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, |
7865 | bool shared) | |
7866 | { | |
7867 | int _rx = *rx, _tx = *tx; | |
7868 | ||
7869 | if (shared) { | |
7870 | *rx = min_t(int, _rx, max); | |
7871 | *tx = min_t(int, _tx, max); | |
7872 | } else { | |
7873 | if (max < 2) | |
7874 | return -ENOMEM; | |
7875 | ||
7876 | while (_rx + _tx > max) { | |
7877 | if (_rx > _tx && _rx > 1) | |
7878 | _rx--; | |
7879 | else if (_tx > 1) | |
7880 | _tx--; | |
7881 | } | |
7882 | *rx = _rx; | |
7883 | *tx = _tx; | |
7884 | } | |
7885 | return 0; | |
7886 | } | |
7887 | ||
7809592d MC |
7888 | static void bnxt_setup_msix(struct bnxt *bp) |
7889 | { | |
7890 | const int len = sizeof(bp->irq_tbl[0].name); | |
7891 | struct net_device *dev = bp->dev; | |
7892 | int tcs, i; | |
7893 | ||
7894 | tcs = netdev_get_num_tc(dev); | |
7895 | if (tcs > 1) { | |
d1e7925e | 7896 | int i, off, count; |
7809592d | 7897 | |
d1e7925e MC |
7898 | for (i = 0; i < tcs; i++) { |
7899 | count = bp->tx_nr_rings_per_tc; | |
7900 | off = i * count; | |
7901 | netdev_set_tc_queue(dev, i, count, off); | |
7809592d MC |
7902 | } |
7903 | } | |
7904 | ||
7905 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
e5811b8c | 7906 | int map_idx = bnxt_cp_num_to_irq_num(bp, i); |
7809592d MC |
7907 | char *attr; |
7908 | ||
7909 | if (bp->flags & BNXT_FLAG_SHARED_RINGS) | |
7910 | attr = "TxRx"; | |
7911 | else if (i < bp->rx_nr_rings) | |
7912 | attr = "rx"; | |
7913 | else | |
7914 | attr = "tx"; | |
7915 | ||
e5811b8c MC |
7916 | snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name, |
7917 | attr, i); | |
7918 | bp->irq_tbl[map_idx].handler = bnxt_msix; | |
7809592d MC |
7919 | } |
7920 | } | |
7921 | ||
7922 | static void bnxt_setup_inta(struct bnxt *bp) | |
7923 | { | |
7924 | const int len = sizeof(bp->irq_tbl[0].name); | |
7925 | ||
7926 | if (netdev_get_num_tc(bp->dev)) | |
7927 | netdev_reset_tc(bp->dev); | |
7928 | ||
7929 | snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx", | |
7930 | 0); | |
7931 | bp->irq_tbl[0].handler = bnxt_inta; | |
7932 | } | |
7933 | ||
7934 | static int bnxt_setup_int_mode(struct bnxt *bp) | |
7935 | { | |
7936 | int rc; | |
7937 | ||
7938 | if (bp->flags & BNXT_FLAG_USING_MSIX) | |
7939 | bnxt_setup_msix(bp); | |
7940 | else | |
7941 | bnxt_setup_inta(bp); | |
7942 | ||
7943 | rc = bnxt_set_real_num_queues(bp); | |
7944 | return rc; | |
7945 | } | |
7946 | ||
b7429954 | 7947 | #ifdef CONFIG_RFS_ACCEL |
8079e8f1 MC |
7948 | static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp) |
7949 | { | |
6a4f2947 | 7950 | return bp->hw_resc.max_rsscos_ctxs; |
8079e8f1 MC |
7951 | } |
7952 | ||
7953 | static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp) | |
7954 | { | |
6a4f2947 | 7955 | return bp->hw_resc.max_vnics; |
8079e8f1 | 7956 | } |
b7429954 | 7957 | #endif |
8079e8f1 | 7958 | |
e4060d30 MC |
7959 | unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp) |
7960 | { | |
6a4f2947 | 7961 | return bp->hw_resc.max_stat_ctxs; |
e4060d30 MC |
7962 | } |
7963 | ||
7964 | unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp) | |
7965 | { | |
6a4f2947 | 7966 | return bp->hw_resc.max_cp_rings; |
e4060d30 MC |
7967 | } |
7968 | ||
e916b081 | 7969 | static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp) |
a588e458 | 7970 | { |
c0b8cda0 MC |
7971 | unsigned int cp = bp->hw_resc.max_cp_rings; |
7972 | ||
7973 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
7974 | cp -= bnxt_get_ulp_msix_num(bp); | |
7975 | ||
7976 | return cp; | |
a588e458 MC |
7977 | } |
7978 | ||
ad95c27b | 7979 | static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp) |
7809592d | 7980 | { |
6a4f2947 MC |
7981 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; |
7982 | ||
f7588cd8 MC |
7983 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
7984 | return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs); | |
7985 | ||
6a4f2947 | 7986 | return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings); |
7809592d MC |
7987 | } |
7988 | ||
30f52947 | 7989 | static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs) |
33c2657e | 7990 | { |
6a4f2947 | 7991 | bp->hw_resc.max_irqs = max_irqs; |
33c2657e MC |
7992 | } |
7993 | ||
e916b081 MC |
7994 | unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp) |
7995 | { | |
7996 | unsigned int cp; | |
7997 | ||
7998 | cp = bnxt_get_max_func_cp_rings_for_en(bp); | |
7999 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
8000 | return cp - bp->rx_nr_rings - bp->tx_nr_rings; | |
8001 | else | |
8002 | return cp - bp->cp_nr_rings; | |
8003 | } | |
8004 | ||
c027c6b4 VV |
8005 | unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp) |
8006 | { | |
d77b1ad8 | 8007 | return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp); |
c027c6b4 VV |
8008 | } |
8009 | ||
fbcfc8e4 MC |
8010 | int bnxt_get_avail_msix(struct bnxt *bp, int num) |
8011 | { | |
8012 | int max_cp = bnxt_get_max_func_cp_rings(bp); | |
8013 | int max_irq = bnxt_get_max_func_irqs(bp); | |
8014 | int total_req = bp->cp_nr_rings + num; | |
8015 | int max_idx, avail_msix; | |
8016 | ||
75720e63 MC |
8017 | max_idx = bp->total_irqs; |
8018 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
8019 | max_idx = min_t(int, bp->total_irqs, max_cp); | |
fbcfc8e4 | 8020 | avail_msix = max_idx - bp->cp_nr_rings; |
f1ca94de | 8021 | if (!BNXT_NEW_RM(bp) || avail_msix >= num) |
fbcfc8e4 MC |
8022 | return avail_msix; |
8023 | ||
8024 | if (max_irq < total_req) { | |
8025 | num = max_irq - bp->cp_nr_rings; | |
8026 | if (num <= 0) | |
8027 | return 0; | |
8028 | } | |
8029 | return num; | |
8030 | } | |
8031 | ||
08654eb2 MC |
8032 | static int bnxt_get_num_msix(struct bnxt *bp) |
8033 | { | |
f1ca94de | 8034 | if (!BNXT_NEW_RM(bp)) |
08654eb2 MC |
8035 | return bnxt_get_max_func_irqs(bp); |
8036 | ||
c0b8cda0 | 8037 | return bnxt_nq_rings_in_use(bp); |
08654eb2 MC |
8038 | } |
8039 | ||
7809592d | 8040 | static int bnxt_init_msix(struct bnxt *bp) |
c0c050c5 | 8041 | { |
fbcfc8e4 | 8042 | int i, total_vecs, max, rc = 0, min = 1, ulp_msix; |
7809592d | 8043 | struct msix_entry *msix_ent; |
c0c050c5 | 8044 | |
08654eb2 MC |
8045 | total_vecs = bnxt_get_num_msix(bp); |
8046 | max = bnxt_get_max_func_irqs(bp); | |
8047 | if (total_vecs > max) | |
8048 | total_vecs = max; | |
8049 | ||
2773dfb2 MC |
8050 | if (!total_vecs) |
8051 | return 0; | |
8052 | ||
c0c050c5 MC |
8053 | msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); |
8054 | if (!msix_ent) | |
8055 | return -ENOMEM; | |
8056 | ||
8057 | for (i = 0; i < total_vecs; i++) { | |
8058 | msix_ent[i].entry = i; | |
8059 | msix_ent[i].vector = 0; | |
8060 | } | |
8061 | ||
01657bcd MC |
8062 | if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) |
8063 | min = 2; | |
8064 | ||
8065 | total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); | |
fbcfc8e4 MC |
8066 | ulp_msix = bnxt_get_ulp_msix_num(bp); |
8067 | if (total_vecs < 0 || total_vecs < ulp_msix) { | |
c0c050c5 MC |
8068 | rc = -ENODEV; |
8069 | goto msix_setup_exit; | |
8070 | } | |
8071 | ||
8072 | bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); | |
8073 | if (bp->irq_tbl) { | |
7809592d MC |
8074 | for (i = 0; i < total_vecs; i++) |
8075 | bp->irq_tbl[i].vector = msix_ent[i].vector; | |
c0c050c5 | 8076 | |
7809592d | 8077 | bp->total_irqs = total_vecs; |
c0c050c5 | 8078 | /* Trim rings based upon num of vectors allocated */ |
6e6c5a57 | 8079 | rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, |
fbcfc8e4 | 8080 | total_vecs - ulp_msix, min == 1); |
6e6c5a57 MC |
8081 | if (rc) |
8082 | goto msix_setup_exit; | |
8083 | ||
7809592d MC |
8084 | bp->cp_nr_rings = (min == 1) ? |
8085 | max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : | |
8086 | bp->tx_nr_rings + bp->rx_nr_rings; | |
c0c050c5 | 8087 | |
c0c050c5 MC |
8088 | } else { |
8089 | rc = -ENOMEM; | |
8090 | goto msix_setup_exit; | |
8091 | } | |
8092 | bp->flags |= BNXT_FLAG_USING_MSIX; | |
8093 | kfree(msix_ent); | |
8094 | return 0; | |
8095 | ||
8096 | msix_setup_exit: | |
7809592d MC |
8097 | netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc); |
8098 | kfree(bp->irq_tbl); | |
8099 | bp->irq_tbl = NULL; | |
c0c050c5 MC |
8100 | pci_disable_msix(bp->pdev); |
8101 | kfree(msix_ent); | |
8102 | return rc; | |
8103 | } | |
8104 | ||
7809592d | 8105 | static int bnxt_init_inta(struct bnxt *bp) |
c0c050c5 | 8106 | { |
c0c050c5 | 8107 | bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL); |
7809592d MC |
8108 | if (!bp->irq_tbl) |
8109 | return -ENOMEM; | |
8110 | ||
8111 | bp->total_irqs = 1; | |
c0c050c5 MC |
8112 | bp->rx_nr_rings = 1; |
8113 | bp->tx_nr_rings = 1; | |
8114 | bp->cp_nr_rings = 1; | |
01657bcd | 8115 | bp->flags |= BNXT_FLAG_SHARED_RINGS; |
c0c050c5 | 8116 | bp->irq_tbl[0].vector = bp->pdev->irq; |
7809592d | 8117 | return 0; |
c0c050c5 MC |
8118 | } |
8119 | ||
7809592d | 8120 | static int bnxt_init_int_mode(struct bnxt *bp) |
c0c050c5 MC |
8121 | { |
8122 | int rc = 0; | |
8123 | ||
8124 | if (bp->flags & BNXT_FLAG_MSIX_CAP) | |
7809592d | 8125 | rc = bnxt_init_msix(bp); |
c0c050c5 | 8126 | |
1fa72e29 | 8127 | if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) { |
c0c050c5 | 8128 | /* fallback to INTA */ |
7809592d | 8129 | rc = bnxt_init_inta(bp); |
c0c050c5 MC |
8130 | } |
8131 | return rc; | |
8132 | } | |
8133 | ||
7809592d MC |
8134 | static void bnxt_clear_int_mode(struct bnxt *bp) |
8135 | { | |
8136 | if (bp->flags & BNXT_FLAG_USING_MSIX) | |
8137 | pci_disable_msix(bp->pdev); | |
8138 | ||
8139 | kfree(bp->irq_tbl); | |
8140 | bp->irq_tbl = NULL; | |
8141 | bp->flags &= ~BNXT_FLAG_USING_MSIX; | |
8142 | } | |
8143 | ||
1b3f0b75 | 8144 | int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init) |
674f50a5 | 8145 | { |
674f50a5 | 8146 | int tcs = netdev_get_num_tc(bp->dev); |
1b3f0b75 | 8147 | bool irq_cleared = false; |
674f50a5 MC |
8148 | int rc; |
8149 | ||
8150 | if (!bnxt_need_reserve_rings(bp)) | |
8151 | return 0; | |
8152 | ||
1b3f0b75 MC |
8153 | if (irq_re_init && BNXT_NEW_RM(bp) && |
8154 | bnxt_get_num_msix(bp) != bp->total_irqs) { | |
ec86f14e | 8155 | bnxt_ulp_irq_stop(bp); |
674f50a5 | 8156 | bnxt_clear_int_mode(bp); |
1b3f0b75 | 8157 | irq_cleared = true; |
36d65be9 MC |
8158 | } |
8159 | rc = __bnxt_reserve_rings(bp); | |
1b3f0b75 | 8160 | if (irq_cleared) { |
36d65be9 MC |
8161 | if (!rc) |
8162 | rc = bnxt_init_int_mode(bp); | |
ec86f14e | 8163 | bnxt_ulp_irq_restart(bp, rc); |
36d65be9 MC |
8164 | } |
8165 | if (rc) { | |
8166 | netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc); | |
8167 | return rc; | |
674f50a5 MC |
8168 | } |
8169 | if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) { | |
8170 | netdev_err(bp->dev, "tx ring reservation failure\n"); | |
8171 | netdev_reset_tc(bp->dev); | |
8172 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; | |
8173 | return -ENOMEM; | |
8174 | } | |
674f50a5 MC |
8175 | return 0; |
8176 | } | |
8177 | ||
c0c050c5 MC |
8178 | static void bnxt_free_irq(struct bnxt *bp) |
8179 | { | |
8180 | struct bnxt_irq *irq; | |
8181 | int i; | |
8182 | ||
8183 | #ifdef CONFIG_RFS_ACCEL | |
8184 | free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); | |
8185 | bp->dev->rx_cpu_rmap = NULL; | |
8186 | #endif | |
cb98526b | 8187 | if (!bp->irq_tbl || !bp->bnapi) |
c0c050c5 MC |
8188 | return; |
8189 | ||
8190 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
e5811b8c MC |
8191 | int map_idx = bnxt_cp_num_to_irq_num(bp, i); |
8192 | ||
8193 | irq = &bp->irq_tbl[map_idx]; | |
56f0fd80 VV |
8194 | if (irq->requested) { |
8195 | if (irq->have_cpumask) { | |
8196 | irq_set_affinity_hint(irq->vector, NULL); | |
8197 | free_cpumask_var(irq->cpu_mask); | |
8198 | irq->have_cpumask = 0; | |
8199 | } | |
c0c050c5 | 8200 | free_irq(irq->vector, bp->bnapi[i]); |
56f0fd80 VV |
8201 | } |
8202 | ||
c0c050c5 MC |
8203 | irq->requested = 0; |
8204 | } | |
c0c050c5 MC |
8205 | } |
8206 | ||
8207 | static int bnxt_request_irq(struct bnxt *bp) | |
8208 | { | |
b81a90d3 | 8209 | int i, j, rc = 0; |
c0c050c5 MC |
8210 | unsigned long flags = 0; |
8211 | #ifdef CONFIG_RFS_ACCEL | |
e5811b8c | 8212 | struct cpu_rmap *rmap; |
c0c050c5 MC |
8213 | #endif |
8214 | ||
e5811b8c MC |
8215 | rc = bnxt_setup_int_mode(bp); |
8216 | if (rc) { | |
8217 | netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", | |
8218 | rc); | |
8219 | return rc; | |
8220 | } | |
8221 | #ifdef CONFIG_RFS_ACCEL | |
8222 | rmap = bp->dev->rx_cpu_rmap; | |
8223 | #endif | |
c0c050c5 MC |
8224 | if (!(bp->flags & BNXT_FLAG_USING_MSIX)) |
8225 | flags = IRQF_SHARED; | |
8226 | ||
b81a90d3 | 8227 | for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { |
e5811b8c MC |
8228 | int map_idx = bnxt_cp_num_to_irq_num(bp, i); |
8229 | struct bnxt_irq *irq = &bp->irq_tbl[map_idx]; | |
8230 | ||
c0c050c5 | 8231 | #ifdef CONFIG_RFS_ACCEL |
b81a90d3 | 8232 | if (rmap && bp->bnapi[i]->rx_ring) { |
c0c050c5 MC |
8233 | rc = irq_cpu_rmap_add(rmap, irq->vector); |
8234 | if (rc) | |
8235 | netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", | |
b81a90d3 MC |
8236 | j); |
8237 | j++; | |
c0c050c5 MC |
8238 | } |
8239 | #endif | |
8240 | rc = request_irq(irq->vector, irq->handler, flags, irq->name, | |
8241 | bp->bnapi[i]); | |
8242 | if (rc) | |
8243 | break; | |
8244 | ||
8245 | irq->requested = 1; | |
56f0fd80 VV |
8246 | |
8247 | if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) { | |
8248 | int numa_node = dev_to_node(&bp->pdev->dev); | |
8249 | ||
8250 | irq->have_cpumask = 1; | |
8251 | cpumask_set_cpu(cpumask_local_spread(i, numa_node), | |
8252 | irq->cpu_mask); | |
8253 | rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask); | |
8254 | if (rc) { | |
8255 | netdev_warn(bp->dev, | |
8256 | "Set affinity failed, IRQ = %d\n", | |
8257 | irq->vector); | |
8258 | break; | |
8259 | } | |
8260 | } | |
c0c050c5 MC |
8261 | } |
8262 | return rc; | |
8263 | } | |
8264 | ||
8265 | static void bnxt_del_napi(struct bnxt *bp) | |
8266 | { | |
8267 | int i; | |
8268 | ||
8269 | if (!bp->bnapi) | |
8270 | return; | |
8271 | ||
8272 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
8273 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
8274 | ||
8275 | napi_hash_del(&bnapi->napi); | |
8276 | netif_napi_del(&bnapi->napi); | |
8277 | } | |
e5f6f564 ED |
8278 | /* We called napi_hash_del() before netif_napi_del(), we need |
8279 | * to respect an RCU grace period before freeing napi structures. | |
8280 | */ | |
8281 | synchronize_net(); | |
c0c050c5 MC |
8282 | } |
8283 | ||
8284 | static void bnxt_init_napi(struct bnxt *bp) | |
8285 | { | |
8286 | int i; | |
10bbdaf5 | 8287 | unsigned int cp_nr_rings = bp->cp_nr_rings; |
c0c050c5 MC |
8288 | struct bnxt_napi *bnapi; |
8289 | ||
8290 | if (bp->flags & BNXT_FLAG_USING_MSIX) { | |
0fcec985 MC |
8291 | int (*poll_fn)(struct napi_struct *, int) = bnxt_poll; |
8292 | ||
8293 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
8294 | poll_fn = bnxt_poll_p5; | |
8295 | else if (BNXT_CHIP_TYPE_NITRO_A0(bp)) | |
10bbdaf5 PS |
8296 | cp_nr_rings--; |
8297 | for (i = 0; i < cp_nr_rings; i++) { | |
c0c050c5 | 8298 | bnapi = bp->bnapi[i]; |
0fcec985 | 8299 | netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64); |
c0c050c5 | 8300 | } |
10bbdaf5 PS |
8301 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { |
8302 | bnapi = bp->bnapi[cp_nr_rings]; | |
8303 | netif_napi_add(bp->dev, &bnapi->napi, | |
8304 | bnxt_poll_nitroa0, 64); | |
10bbdaf5 | 8305 | } |
c0c050c5 MC |
8306 | } else { |
8307 | bnapi = bp->bnapi[0]; | |
8308 | netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64); | |
c0c050c5 MC |
8309 | } |
8310 | } | |
8311 | ||
8312 | static void bnxt_disable_napi(struct bnxt *bp) | |
8313 | { | |
8314 | int i; | |
8315 | ||
8316 | if (!bp->bnapi) | |
8317 | return; | |
8318 | ||
0bc0b97f AG |
8319 | for (i = 0; i < bp->cp_nr_rings; i++) { |
8320 | struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; | |
8321 | ||
8322 | if (bp->bnapi[i]->rx_ring) | |
8323 | cancel_work_sync(&cpr->dim.work); | |
8324 | ||
c0c050c5 | 8325 | napi_disable(&bp->bnapi[i]->napi); |
0bc0b97f | 8326 | } |
c0c050c5 MC |
8327 | } |
8328 | ||
8329 | static void bnxt_enable_napi(struct bnxt *bp) | |
8330 | { | |
8331 | int i; | |
8332 | ||
8333 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
6a8788f2 | 8334 | struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; |
fa7e2812 | 8335 | bp->bnapi[i]->in_reset = false; |
6a8788f2 AG |
8336 | |
8337 | if (bp->bnapi[i]->rx_ring) { | |
8338 | INIT_WORK(&cpr->dim.work, bnxt_dim_work); | |
c002bd52 | 8339 | cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; |
6a8788f2 | 8340 | } |
c0c050c5 MC |
8341 | napi_enable(&bp->bnapi[i]->napi); |
8342 | } | |
8343 | } | |
8344 | ||
7df4ae9f | 8345 | void bnxt_tx_disable(struct bnxt *bp) |
c0c050c5 MC |
8346 | { |
8347 | int i; | |
c0c050c5 | 8348 | struct bnxt_tx_ring_info *txr; |
c0c050c5 | 8349 | |
b6ab4b01 | 8350 | if (bp->tx_ring) { |
c0c050c5 | 8351 | for (i = 0; i < bp->tx_nr_rings; i++) { |
b6ab4b01 | 8352 | txr = &bp->tx_ring[i]; |
c0c050c5 | 8353 | txr->dev_state = BNXT_DEV_STATE_CLOSING; |
c0c050c5 MC |
8354 | } |
8355 | } | |
8356 | /* Stop all TX queues */ | |
8357 | netif_tx_disable(bp->dev); | |
8358 | netif_carrier_off(bp->dev); | |
8359 | } | |
8360 | ||
7df4ae9f | 8361 | void bnxt_tx_enable(struct bnxt *bp) |
c0c050c5 MC |
8362 | { |
8363 | int i; | |
c0c050c5 | 8364 | struct bnxt_tx_ring_info *txr; |
c0c050c5 MC |
8365 | |
8366 | for (i = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 8367 | txr = &bp->tx_ring[i]; |
c0c050c5 MC |
8368 | txr->dev_state = 0; |
8369 | } | |
8370 | netif_tx_wake_all_queues(bp->dev); | |
8371 | if (bp->link_info.link_up) | |
8372 | netif_carrier_on(bp->dev); | |
8373 | } | |
8374 | ||
8375 | static void bnxt_report_link(struct bnxt *bp) | |
8376 | { | |
8377 | if (bp->link_info.link_up) { | |
8378 | const char *duplex; | |
8379 | const char *flow_ctrl; | |
38a21b34 DK |
8380 | u32 speed; |
8381 | u16 fec; | |
c0c050c5 MC |
8382 | |
8383 | netif_carrier_on(bp->dev); | |
8384 | if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) | |
8385 | duplex = "full"; | |
8386 | else | |
8387 | duplex = "half"; | |
8388 | if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) | |
8389 | flow_ctrl = "ON - receive & transmit"; | |
8390 | else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) | |
8391 | flow_ctrl = "ON - transmit"; | |
8392 | else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) | |
8393 | flow_ctrl = "ON - receive"; | |
8394 | else | |
8395 | flow_ctrl = "none"; | |
8396 | speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); | |
38a21b34 | 8397 | netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n", |
c0c050c5 | 8398 | speed, duplex, flow_ctrl); |
170ce013 MC |
8399 | if (bp->flags & BNXT_FLAG_EEE_CAP) |
8400 | netdev_info(bp->dev, "EEE is %s\n", | |
8401 | bp->eee.eee_active ? "active" : | |
8402 | "not active"); | |
e70c752f MC |
8403 | fec = bp->link_info.fec_cfg; |
8404 | if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED)) | |
8405 | netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n", | |
8406 | (fec & BNXT_FEC_AUTONEG) ? "on" : "off", | |
8407 | (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" : | |
8408 | (fec & BNXT_FEC_ENC_RS) ? "RS" : "None"); | |
c0c050c5 MC |
8409 | } else { |
8410 | netif_carrier_off(bp->dev); | |
8411 | netdev_err(bp->dev, "NIC Link is Down\n"); | |
8412 | } | |
8413 | } | |
8414 | ||
170ce013 MC |
8415 | static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) |
8416 | { | |
8417 | int rc = 0; | |
8418 | struct hwrm_port_phy_qcaps_input req = {0}; | |
8419 | struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
93ed8117 | 8420 | struct bnxt_link_info *link_info = &bp->link_info; |
170ce013 | 8421 | |
ba642ab7 MC |
8422 | bp->flags &= ~BNXT_FLAG_EEE_CAP; |
8423 | if (bp->test_info) | |
8a60efd1 MC |
8424 | bp->test_info->flags &= ~(BNXT_TEST_FL_EXT_LPBK | |
8425 | BNXT_TEST_FL_AN_PHY_LPBK); | |
170ce013 MC |
8426 | if (bp->hwrm_spec_code < 0x10201) |
8427 | return 0; | |
8428 | ||
8429 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); | |
8430 | ||
8431 | mutex_lock(&bp->hwrm_cmd_lock); | |
8432 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8433 | if (rc) | |
8434 | goto hwrm_phy_qcaps_exit; | |
8435 | ||
acb20054 | 8436 | if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) { |
170ce013 MC |
8437 | struct ethtool_eee *eee = &bp->eee; |
8438 | u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode); | |
8439 | ||
8440 | bp->flags |= BNXT_FLAG_EEE_CAP; | |
8441 | eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); | |
8442 | bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) & | |
8443 | PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK; | |
8444 | bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) & | |
8445 | PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK; | |
8446 | } | |
55fd0cf3 MC |
8447 | if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) { |
8448 | if (bp->test_info) | |
8449 | bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK; | |
8450 | } | |
8a60efd1 MC |
8451 | if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED) { |
8452 | if (bp->test_info) | |
8453 | bp->test_info->flags |= BNXT_TEST_FL_AN_PHY_LPBK; | |
8454 | } | |
c7e457f4 MC |
8455 | if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED) { |
8456 | if (BNXT_PF(bp)) | |
8457 | bp->fw_cap |= BNXT_FW_CAP_SHARED_PORT_CFG; | |
8458 | } | |
520ad89a MC |
8459 | if (resp->supported_speeds_auto_mode) |
8460 | link_info->support_auto_speeds = | |
8461 | le16_to_cpu(resp->supported_speeds_auto_mode); | |
170ce013 | 8462 | |
d5430d31 MC |
8463 | bp->port_count = resp->port_cnt; |
8464 | ||
170ce013 MC |
8465 | hwrm_phy_qcaps_exit: |
8466 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8467 | return rc; | |
8468 | } | |
8469 | ||
c0c050c5 MC |
8470 | static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) |
8471 | { | |
8472 | int rc = 0; | |
8473 | struct bnxt_link_info *link_info = &bp->link_info; | |
8474 | struct hwrm_port_phy_qcfg_input req = {0}; | |
8475 | struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
8476 | u8 link_up = link_info->link_up; | |
286ef9d6 | 8477 | u16 diff; |
c0c050c5 MC |
8478 | |
8479 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1); | |
8480 | ||
8481 | mutex_lock(&bp->hwrm_cmd_lock); | |
8482 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8483 | if (rc) { | |
8484 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8485 | return rc; | |
8486 | } | |
8487 | ||
8488 | memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); | |
8489 | link_info->phy_link_status = resp->link; | |
acb20054 MC |
8490 | link_info->duplex = resp->duplex_cfg; |
8491 | if (bp->hwrm_spec_code >= 0x10800) | |
8492 | link_info->duplex = resp->duplex_state; | |
c0c050c5 MC |
8493 | link_info->pause = resp->pause; |
8494 | link_info->auto_mode = resp->auto_mode; | |
8495 | link_info->auto_pause_setting = resp->auto_pause; | |
3277360e | 8496 | link_info->lp_pause = resp->link_partner_adv_pause; |
c0c050c5 | 8497 | link_info->force_pause_setting = resp->force_pause; |
acb20054 | 8498 | link_info->duplex_setting = resp->duplex_cfg; |
c0c050c5 MC |
8499 | if (link_info->phy_link_status == BNXT_LINK_LINK) |
8500 | link_info->link_speed = le16_to_cpu(resp->link_speed); | |
8501 | else | |
8502 | link_info->link_speed = 0; | |
8503 | link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); | |
c0c050c5 MC |
8504 | link_info->support_speeds = le16_to_cpu(resp->support_speeds); |
8505 | link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); | |
3277360e MC |
8506 | link_info->lp_auto_link_speeds = |
8507 | le16_to_cpu(resp->link_partner_adv_speeds); | |
c0c050c5 MC |
8508 | link_info->preemphasis = le32_to_cpu(resp->preemphasis); |
8509 | link_info->phy_ver[0] = resp->phy_maj; | |
8510 | link_info->phy_ver[1] = resp->phy_min; | |
8511 | link_info->phy_ver[2] = resp->phy_bld; | |
8512 | link_info->media_type = resp->media_type; | |
03efbec0 | 8513 | link_info->phy_type = resp->phy_type; |
11f15ed3 | 8514 | link_info->transceiver = resp->xcvr_pkg_type; |
170ce013 MC |
8515 | link_info->phy_addr = resp->eee_config_phy_addr & |
8516 | PORT_PHY_QCFG_RESP_PHY_ADDR_MASK; | |
42ee18fe | 8517 | link_info->module_status = resp->module_status; |
170ce013 MC |
8518 | |
8519 | if (bp->flags & BNXT_FLAG_EEE_CAP) { | |
8520 | struct ethtool_eee *eee = &bp->eee; | |
8521 | u16 fw_speeds; | |
8522 | ||
8523 | eee->eee_active = 0; | |
8524 | if (resp->eee_config_phy_addr & | |
8525 | PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) { | |
8526 | eee->eee_active = 1; | |
8527 | fw_speeds = le16_to_cpu( | |
8528 | resp->link_partner_adv_eee_link_speed_mask); | |
8529 | eee->lp_advertised = | |
8530 | _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); | |
8531 | } | |
8532 | ||
8533 | /* Pull initial EEE config */ | |
8534 | if (!chng_link_state) { | |
8535 | if (resp->eee_config_phy_addr & | |
8536 | PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED) | |
8537 | eee->eee_enabled = 1; | |
c0c050c5 | 8538 | |
170ce013 MC |
8539 | fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask); |
8540 | eee->advertised = | |
8541 | _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); | |
8542 | ||
8543 | if (resp->eee_config_phy_addr & | |
8544 | PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) { | |
8545 | __le32 tmr; | |
8546 | ||
8547 | eee->tx_lpi_enabled = 1; | |
8548 | tmr = resp->xcvr_identifier_type_tx_lpi_timer; | |
8549 | eee->tx_lpi_timer = le32_to_cpu(tmr) & | |
8550 | PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK; | |
8551 | } | |
8552 | } | |
8553 | } | |
e70c752f MC |
8554 | |
8555 | link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED; | |
8556 | if (bp->hwrm_spec_code >= 0x10504) | |
8557 | link_info->fec_cfg = le16_to_cpu(resp->fec_cfg); | |
8558 | ||
c0c050c5 MC |
8559 | /* TODO: need to add more logic to report VF link */ |
8560 | if (chng_link_state) { | |
8561 | if (link_info->phy_link_status == BNXT_LINK_LINK) | |
8562 | link_info->link_up = 1; | |
8563 | else | |
8564 | link_info->link_up = 0; | |
8565 | if (link_up != link_info->link_up) | |
8566 | bnxt_report_link(bp); | |
8567 | } else { | |
8568 | /* alwasy link down if not require to update link state */ | |
8569 | link_info->link_up = 0; | |
8570 | } | |
8571 | mutex_unlock(&bp->hwrm_cmd_lock); | |
286ef9d6 | 8572 | |
c7e457f4 | 8573 | if (!BNXT_PHY_CFG_ABLE(bp)) |
dac04907 MC |
8574 | return 0; |
8575 | ||
286ef9d6 MC |
8576 | diff = link_info->support_auto_speeds ^ link_info->advertising; |
8577 | if ((link_info->support_auto_speeds | diff) != | |
8578 | link_info->support_auto_speeds) { | |
8579 | /* An advertised speed is no longer supported, so we need to | |
0eaa24b9 MC |
8580 | * update the advertisement settings. Caller holds RTNL |
8581 | * so we can modify link settings. | |
286ef9d6 | 8582 | */ |
286ef9d6 | 8583 | link_info->advertising = link_info->support_auto_speeds; |
0eaa24b9 | 8584 | if (link_info->autoneg & BNXT_AUTONEG_SPEED) |
286ef9d6 | 8585 | bnxt_hwrm_set_link_setting(bp, true, false); |
286ef9d6 | 8586 | } |
c0c050c5 MC |
8587 | return 0; |
8588 | } | |
8589 | ||
10289bec MC |
8590 | static void bnxt_get_port_module_status(struct bnxt *bp) |
8591 | { | |
8592 | struct bnxt_link_info *link_info = &bp->link_info; | |
8593 | struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; | |
8594 | u8 module_status; | |
8595 | ||
8596 | if (bnxt_update_link(bp, true)) | |
8597 | return; | |
8598 | ||
8599 | module_status = link_info->module_status; | |
8600 | switch (module_status) { | |
8601 | case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX: | |
8602 | case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: | |
8603 | case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG: | |
8604 | netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n", | |
8605 | bp->pf.port_id); | |
8606 | if (bp->hwrm_spec_code >= 0x10201) { | |
8607 | netdev_warn(bp->dev, "Module part number %s\n", | |
8608 | resp->phy_vendor_partnumber); | |
8609 | } | |
8610 | if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX) | |
8611 | netdev_warn(bp->dev, "TX is disabled\n"); | |
8612 | if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN) | |
8613 | netdev_warn(bp->dev, "SFP+ module is shutdown\n"); | |
8614 | } | |
8615 | } | |
8616 | ||
c0c050c5 MC |
8617 | static void |
8618 | bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) | |
8619 | { | |
8620 | if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { | |
c9ee9516 MC |
8621 | if (bp->hwrm_spec_code >= 0x10201) |
8622 | req->auto_pause = | |
8623 | PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; | |
c0c050c5 MC |
8624 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) |
8625 | req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; | |
8626 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) | |
49b5c7a1 | 8627 | req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX; |
c0c050c5 MC |
8628 | req->enables |= |
8629 | cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); | |
8630 | } else { | |
8631 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) | |
8632 | req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; | |
8633 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) | |
8634 | req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; | |
8635 | req->enables |= | |
8636 | cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); | |
c9ee9516 MC |
8637 | if (bp->hwrm_spec_code >= 0x10201) { |
8638 | req->auto_pause = req->force_pause; | |
8639 | req->enables |= cpu_to_le32( | |
8640 | PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); | |
8641 | } | |
c0c050c5 MC |
8642 | } |
8643 | } | |
8644 | ||
8645 | static void bnxt_hwrm_set_link_common(struct bnxt *bp, | |
8646 | struct hwrm_port_phy_cfg_input *req) | |
8647 | { | |
8648 | u8 autoneg = bp->link_info.autoneg; | |
8649 | u16 fw_link_speed = bp->link_info.req_link_speed; | |
68515a18 | 8650 | u16 advertising = bp->link_info.advertising; |
c0c050c5 MC |
8651 | |
8652 | if (autoneg & BNXT_AUTONEG_SPEED) { | |
8653 | req->auto_mode |= | |
11f15ed3 | 8654 | PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK; |
c0c050c5 MC |
8655 | |
8656 | req->enables |= cpu_to_le32( | |
8657 | PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); | |
8658 | req->auto_link_speed_mask = cpu_to_le16(advertising); | |
8659 | ||
8660 | req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); | |
8661 | req->flags |= | |
8662 | cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); | |
8663 | } else { | |
8664 | req->force_link_speed = cpu_to_le16(fw_link_speed); | |
8665 | req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); | |
8666 | } | |
8667 | ||
c0c050c5 MC |
8668 | /* tell chimp that the setting takes effect immediately */ |
8669 | req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); | |
8670 | } | |
8671 | ||
8672 | int bnxt_hwrm_set_pause(struct bnxt *bp) | |
8673 | { | |
8674 | struct hwrm_port_phy_cfg_input req = {0}; | |
8675 | int rc; | |
8676 | ||
8677 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); | |
8678 | bnxt_hwrm_set_pause_common(bp, &req); | |
8679 | ||
8680 | if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || | |
8681 | bp->link_info.force_link_chng) | |
8682 | bnxt_hwrm_set_link_common(bp, &req); | |
8683 | ||
8684 | mutex_lock(&bp->hwrm_cmd_lock); | |
8685 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8686 | if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { | |
8687 | /* since changing of pause setting doesn't trigger any link | |
8688 | * change event, the driver needs to update the current pause | |
8689 | * result upon successfully return of the phy_cfg command | |
8690 | */ | |
8691 | bp->link_info.pause = | |
8692 | bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; | |
8693 | bp->link_info.auto_pause_setting = 0; | |
8694 | if (!bp->link_info.force_link_chng) | |
8695 | bnxt_report_link(bp); | |
8696 | } | |
8697 | bp->link_info.force_link_chng = false; | |
8698 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8699 | return rc; | |
8700 | } | |
8701 | ||
939f7f0c MC |
8702 | static void bnxt_hwrm_set_eee(struct bnxt *bp, |
8703 | struct hwrm_port_phy_cfg_input *req) | |
8704 | { | |
8705 | struct ethtool_eee *eee = &bp->eee; | |
8706 | ||
8707 | if (eee->eee_enabled) { | |
8708 | u16 eee_speeds; | |
8709 | u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE; | |
8710 | ||
8711 | if (eee->tx_lpi_enabled) | |
8712 | flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE; | |
8713 | else | |
8714 | flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE; | |
8715 | ||
8716 | req->flags |= cpu_to_le32(flags); | |
8717 | eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); | |
8718 | req->eee_link_speed_mask = cpu_to_le16(eee_speeds); | |
8719 | req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer); | |
8720 | } else { | |
8721 | req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE); | |
8722 | } | |
8723 | } | |
8724 | ||
8725 | int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee) | |
c0c050c5 MC |
8726 | { |
8727 | struct hwrm_port_phy_cfg_input req = {0}; | |
8728 | ||
8729 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); | |
8730 | if (set_pause) | |
8731 | bnxt_hwrm_set_pause_common(bp, &req); | |
8732 | ||
8733 | bnxt_hwrm_set_link_common(bp, &req); | |
939f7f0c MC |
8734 | |
8735 | if (set_eee) | |
8736 | bnxt_hwrm_set_eee(bp, &req); | |
c0c050c5 MC |
8737 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
8738 | } | |
8739 | ||
33f7d55f MC |
8740 | static int bnxt_hwrm_shutdown_link(struct bnxt *bp) |
8741 | { | |
8742 | struct hwrm_port_phy_cfg_input req = {0}; | |
8743 | ||
567b2abe | 8744 | if (!BNXT_SINGLE_PF(bp)) |
33f7d55f MC |
8745 | return 0; |
8746 | ||
8747 | if (pci_num_vf(bp->pdev)) | |
8748 | return 0; | |
8749 | ||
8750 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); | |
16d663a6 | 8751 | req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN); |
33f7d55f MC |
8752 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
8753 | } | |
8754 | ||
ec5d31e3 MC |
8755 | static int bnxt_fw_init_one(struct bnxt *bp); |
8756 | ||
25e1acd6 MC |
8757 | static int bnxt_hwrm_if_change(struct bnxt *bp, bool up) |
8758 | { | |
8759 | struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr; | |
8760 | struct hwrm_func_drv_if_change_input req = {0}; | |
ec5d31e3 MC |
8761 | bool resc_reinit = false, fw_reset = false; |
8762 | u32 flags = 0; | |
25e1acd6 MC |
8763 | int rc; |
8764 | ||
8765 | if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE)) | |
8766 | return 0; | |
8767 | ||
8768 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1); | |
8769 | if (up) | |
8770 | req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP); | |
8771 | mutex_lock(&bp->hwrm_cmd_lock); | |
8772 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
ec5d31e3 MC |
8773 | if (!rc) |
8774 | flags = le32_to_cpu(resp->flags); | |
25e1acd6 | 8775 | mutex_unlock(&bp->hwrm_cmd_lock); |
ec5d31e3 MC |
8776 | if (rc) |
8777 | return rc; | |
25e1acd6 | 8778 | |
ec5d31e3 MC |
8779 | if (!up) |
8780 | return 0; | |
25e1acd6 | 8781 | |
ec5d31e3 MC |
8782 | if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE) |
8783 | resc_reinit = true; | |
8784 | if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE) | |
8785 | fw_reset = true; | |
8786 | ||
3bc7d4a3 MC |
8787 | if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) { |
8788 | netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n"); | |
8789 | return -ENODEV; | |
8790 | } | |
ec5d31e3 MC |
8791 | if (resc_reinit || fw_reset) { |
8792 | if (fw_reset) { | |
f3a6d206 VV |
8793 | if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) |
8794 | bnxt_ulp_stop(bp); | |
325f85f3 MC |
8795 | bnxt_free_ctx_mem(bp); |
8796 | kfree(bp->ctx); | |
8797 | bp->ctx = NULL; | |
ec5d31e3 MC |
8798 | rc = bnxt_fw_init_one(bp); |
8799 | if (rc) { | |
8800 | set_bit(BNXT_STATE_ABORT_ERR, &bp->state); | |
8801 | return rc; | |
8802 | } | |
8803 | bnxt_clear_int_mode(bp); | |
8804 | rc = bnxt_init_int_mode(bp); | |
8805 | if (rc) { | |
8806 | netdev_err(bp->dev, "init int mode failed\n"); | |
8807 | return rc; | |
8808 | } | |
8809 | set_bit(BNXT_STATE_FW_RESET_DET, &bp->state); | |
8810 | } | |
8811 | if (BNXT_NEW_RM(bp)) { | |
8812 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
8813 | ||
8814 | rc = bnxt_hwrm_func_resc_qcaps(bp, true); | |
8815 | hw_resc->resv_cp_rings = 0; | |
8816 | hw_resc->resv_stat_ctxs = 0; | |
8817 | hw_resc->resv_irqs = 0; | |
8818 | hw_resc->resv_tx_rings = 0; | |
8819 | hw_resc->resv_rx_rings = 0; | |
8820 | hw_resc->resv_hw_ring_grps = 0; | |
8821 | hw_resc->resv_vnics = 0; | |
8822 | if (!fw_reset) { | |
8823 | bp->tx_nr_rings = 0; | |
8824 | bp->rx_nr_rings = 0; | |
8825 | } | |
8826 | } | |
25e1acd6 | 8827 | } |
ec5d31e3 | 8828 | return 0; |
25e1acd6 MC |
8829 | } |
8830 | ||
5ad2cbee MC |
8831 | static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) |
8832 | { | |
8833 | struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
8834 | struct hwrm_port_led_qcaps_input req = {0}; | |
8835 | struct bnxt_pf_info *pf = &bp->pf; | |
8836 | int rc; | |
8837 | ||
ba642ab7 | 8838 | bp->num_leds = 0; |
5ad2cbee MC |
8839 | if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601) |
8840 | return 0; | |
8841 | ||
8842 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1); | |
8843 | req.port_id = cpu_to_le16(pf->port_id); | |
8844 | mutex_lock(&bp->hwrm_cmd_lock); | |
8845 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8846 | if (rc) { | |
8847 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8848 | return rc; | |
8849 | } | |
8850 | if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) { | |
8851 | int i; | |
8852 | ||
8853 | bp->num_leds = resp->num_leds; | |
8854 | memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) * | |
8855 | bp->num_leds); | |
8856 | for (i = 0; i < bp->num_leds; i++) { | |
8857 | struct bnxt_led_info *led = &bp->leds[i]; | |
8858 | __le16 caps = led->led_state_caps; | |
8859 | ||
8860 | if (!led->led_group_id || | |
8861 | !BNXT_LED_ALT_BLINK_CAP(caps)) { | |
8862 | bp->num_leds = 0; | |
8863 | break; | |
8864 | } | |
8865 | } | |
8866 | } | |
8867 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8868 | return 0; | |
8869 | } | |
8870 | ||
5282db6c MC |
8871 | int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp) |
8872 | { | |
8873 | struct hwrm_wol_filter_alloc_input req = {0}; | |
8874 | struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
8875 | int rc; | |
8876 | ||
8877 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1); | |
8878 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
8879 | req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT; | |
8880 | req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS); | |
8881 | memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN); | |
8882 | mutex_lock(&bp->hwrm_cmd_lock); | |
8883 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8884 | if (!rc) | |
8885 | bp->wol_filter_id = resp->wol_filter_id; | |
8886 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8887 | return rc; | |
8888 | } | |
8889 | ||
8890 | int bnxt_hwrm_free_wol_fltr(struct bnxt *bp) | |
8891 | { | |
8892 | struct hwrm_wol_filter_free_input req = {0}; | |
8893 | int rc; | |
8894 | ||
8895 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1); | |
8896 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
8897 | req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID); | |
8898 | req.wol_filter_id = bp->wol_filter_id; | |
8899 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8900 | return rc; | |
8901 | } | |
8902 | ||
c1ef146a MC |
8903 | static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle) |
8904 | { | |
8905 | struct hwrm_wol_filter_qcfg_input req = {0}; | |
8906 | struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
8907 | u16 next_handle = 0; | |
8908 | int rc; | |
8909 | ||
8910 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1); | |
8911 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
8912 | req.handle = cpu_to_le16(handle); | |
8913 | mutex_lock(&bp->hwrm_cmd_lock); | |
8914 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8915 | if (!rc) { | |
8916 | next_handle = le16_to_cpu(resp->next_handle); | |
8917 | if (next_handle != 0) { | |
8918 | if (resp->wol_type == | |
8919 | WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) { | |
8920 | bp->wol = 1; | |
8921 | bp->wol_filter_id = resp->wol_filter_id; | |
8922 | } | |
8923 | } | |
8924 | } | |
8925 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8926 | return next_handle; | |
8927 | } | |
8928 | ||
8929 | static void bnxt_get_wol_settings(struct bnxt *bp) | |
8930 | { | |
8931 | u16 handle = 0; | |
8932 | ||
ba642ab7 | 8933 | bp->wol = 0; |
c1ef146a MC |
8934 | if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP)) |
8935 | return; | |
8936 | ||
8937 | do { | |
8938 | handle = bnxt_hwrm_get_wol_fltrs(bp, handle); | |
8939 | } while (handle && handle != 0xffff); | |
8940 | } | |
8941 | ||
cde49a42 VV |
8942 | #ifdef CONFIG_BNXT_HWMON |
8943 | static ssize_t bnxt_show_temp(struct device *dev, | |
8944 | struct device_attribute *devattr, char *buf) | |
8945 | { | |
8946 | struct hwrm_temp_monitor_query_input req = {0}; | |
8947 | struct hwrm_temp_monitor_query_output *resp; | |
8948 | struct bnxt *bp = dev_get_drvdata(dev); | |
8949 | u32 temp = 0; | |
8950 | ||
8951 | resp = bp->hwrm_cmd_resp_addr; | |
8952 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1); | |
8953 | mutex_lock(&bp->hwrm_cmd_lock); | |
8954 | if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT)) | |
8955 | temp = resp->temp * 1000; /* display millidegree */ | |
8956 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8957 | ||
8958 | return sprintf(buf, "%u\n", temp); | |
8959 | } | |
8960 | static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0); | |
8961 | ||
8962 | static struct attribute *bnxt_attrs[] = { | |
8963 | &sensor_dev_attr_temp1_input.dev_attr.attr, | |
8964 | NULL | |
8965 | }; | |
8966 | ATTRIBUTE_GROUPS(bnxt); | |
8967 | ||
8968 | static void bnxt_hwmon_close(struct bnxt *bp) | |
8969 | { | |
8970 | if (bp->hwmon_dev) { | |
8971 | hwmon_device_unregister(bp->hwmon_dev); | |
8972 | bp->hwmon_dev = NULL; | |
8973 | } | |
8974 | } | |
8975 | ||
8976 | static void bnxt_hwmon_open(struct bnxt *bp) | |
8977 | { | |
8978 | struct pci_dev *pdev = bp->pdev; | |
8979 | ||
ba642ab7 MC |
8980 | if (bp->hwmon_dev) |
8981 | return; | |
8982 | ||
cde49a42 VV |
8983 | bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, |
8984 | DRV_MODULE_NAME, bp, | |
8985 | bnxt_groups); | |
8986 | if (IS_ERR(bp->hwmon_dev)) { | |
8987 | bp->hwmon_dev = NULL; | |
8988 | dev_warn(&pdev->dev, "Cannot register hwmon device\n"); | |
8989 | } | |
8990 | } | |
8991 | #else | |
8992 | static void bnxt_hwmon_close(struct bnxt *bp) | |
8993 | { | |
8994 | } | |
8995 | ||
8996 | static void bnxt_hwmon_open(struct bnxt *bp) | |
8997 | { | |
8998 | } | |
8999 | #endif | |
9000 | ||
939f7f0c MC |
9001 | static bool bnxt_eee_config_ok(struct bnxt *bp) |
9002 | { | |
9003 | struct ethtool_eee *eee = &bp->eee; | |
9004 | struct bnxt_link_info *link_info = &bp->link_info; | |
9005 | ||
9006 | if (!(bp->flags & BNXT_FLAG_EEE_CAP)) | |
9007 | return true; | |
9008 | ||
9009 | if (eee->eee_enabled) { | |
9010 | u32 advertising = | |
9011 | _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); | |
9012 | ||
9013 | if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { | |
9014 | eee->eee_enabled = 0; | |
9015 | return false; | |
9016 | } | |
9017 | if (eee->advertised & ~advertising) { | |
9018 | eee->advertised = advertising & eee->supported; | |
9019 | return false; | |
9020 | } | |
9021 | } | |
9022 | return true; | |
9023 | } | |
9024 | ||
c0c050c5 MC |
9025 | static int bnxt_update_phy_setting(struct bnxt *bp) |
9026 | { | |
9027 | int rc; | |
9028 | bool update_link = false; | |
9029 | bool update_pause = false; | |
939f7f0c | 9030 | bool update_eee = false; |
c0c050c5 MC |
9031 | struct bnxt_link_info *link_info = &bp->link_info; |
9032 | ||
9033 | rc = bnxt_update_link(bp, true); | |
9034 | if (rc) { | |
9035 | netdev_err(bp->dev, "failed to update link (rc: %x)\n", | |
9036 | rc); | |
9037 | return rc; | |
9038 | } | |
33dac24a MC |
9039 | if (!BNXT_SINGLE_PF(bp)) |
9040 | return 0; | |
9041 | ||
c0c050c5 | 9042 | if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && |
c9ee9516 MC |
9043 | (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) != |
9044 | link_info->req_flow_ctrl) | |
c0c050c5 MC |
9045 | update_pause = true; |
9046 | if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && | |
9047 | link_info->force_pause_setting != link_info->req_flow_ctrl) | |
9048 | update_pause = true; | |
c0c050c5 MC |
9049 | if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { |
9050 | if (BNXT_AUTO_MODE(link_info->auto_mode)) | |
9051 | update_link = true; | |
9052 | if (link_info->req_link_speed != link_info->force_link_speed) | |
9053 | update_link = true; | |
de73018f MC |
9054 | if (link_info->req_duplex != link_info->duplex_setting) |
9055 | update_link = true; | |
c0c050c5 MC |
9056 | } else { |
9057 | if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) | |
9058 | update_link = true; | |
9059 | if (link_info->advertising != link_info->auto_link_speeds) | |
9060 | update_link = true; | |
c0c050c5 MC |
9061 | } |
9062 | ||
16d663a6 MC |
9063 | /* The last close may have shutdown the link, so need to call |
9064 | * PHY_CFG to bring it back up. | |
9065 | */ | |
83d8f5e9 | 9066 | if (!bp->link_info.link_up) |
16d663a6 MC |
9067 | update_link = true; |
9068 | ||
939f7f0c MC |
9069 | if (!bnxt_eee_config_ok(bp)) |
9070 | update_eee = true; | |
9071 | ||
c0c050c5 | 9072 | if (update_link) |
939f7f0c | 9073 | rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee); |
c0c050c5 MC |
9074 | else if (update_pause) |
9075 | rc = bnxt_hwrm_set_pause(bp); | |
9076 | if (rc) { | |
9077 | netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", | |
9078 | rc); | |
9079 | return rc; | |
9080 | } | |
9081 | ||
9082 | return rc; | |
9083 | } | |
9084 | ||
11809490 JH |
9085 | /* Common routine to pre-map certain register block to different GRC window. |
9086 | * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows | |
9087 | * in PF and 3 windows in VF that can be customized to map in different | |
9088 | * register blocks. | |
9089 | */ | |
9090 | static void bnxt_preset_reg_win(struct bnxt *bp) | |
9091 | { | |
9092 | if (BNXT_PF(bp)) { | |
9093 | /* CAG registers map to GRC window #4 */ | |
9094 | writel(BNXT_CAG_REG_BASE, | |
9095 | bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); | |
9096 | } | |
9097 | } | |
9098 | ||
47558acd MC |
9099 | static int bnxt_init_dflt_ring_mode(struct bnxt *bp); |
9100 | ||
c0c050c5 MC |
9101 | static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) |
9102 | { | |
9103 | int rc = 0; | |
9104 | ||
11809490 | 9105 | bnxt_preset_reg_win(bp); |
c0c050c5 MC |
9106 | netif_carrier_off(bp->dev); |
9107 | if (irq_re_init) { | |
47558acd MC |
9108 | /* Reserve rings now if none were reserved at driver probe. */ |
9109 | rc = bnxt_init_dflt_ring_mode(bp); | |
9110 | if (rc) { | |
9111 | netdev_err(bp->dev, "Failed to reserve default rings at open\n"); | |
9112 | return rc; | |
9113 | } | |
c0c050c5 | 9114 | } |
1b3f0b75 | 9115 | rc = bnxt_reserve_rings(bp, irq_re_init); |
41e8d798 MC |
9116 | if (rc) |
9117 | return rc; | |
c0c050c5 MC |
9118 | if ((bp->flags & BNXT_FLAG_RFS) && |
9119 | !(bp->flags & BNXT_FLAG_USING_MSIX)) { | |
9120 | /* disable RFS if falling back to INTA */ | |
9121 | bp->dev->hw_features &= ~NETIF_F_NTUPLE; | |
9122 | bp->flags &= ~BNXT_FLAG_RFS; | |
9123 | } | |
9124 | ||
9125 | rc = bnxt_alloc_mem(bp, irq_re_init); | |
9126 | if (rc) { | |
9127 | netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); | |
9128 | goto open_err_free_mem; | |
9129 | } | |
9130 | ||
9131 | if (irq_re_init) { | |
9132 | bnxt_init_napi(bp); | |
9133 | rc = bnxt_request_irq(bp); | |
9134 | if (rc) { | |
9135 | netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); | |
c58387ab | 9136 | goto open_err_irq; |
c0c050c5 MC |
9137 | } |
9138 | } | |
9139 | ||
9140 | bnxt_enable_napi(bp); | |
cabfb09d | 9141 | bnxt_debug_dev_init(bp); |
c0c050c5 MC |
9142 | |
9143 | rc = bnxt_init_nic(bp, irq_re_init); | |
9144 | if (rc) { | |
9145 | netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); | |
9146 | goto open_err; | |
9147 | } | |
9148 | ||
9149 | if (link_re_init) { | |
e2dc9b6e | 9150 | mutex_lock(&bp->link_lock); |
c0c050c5 | 9151 | rc = bnxt_update_phy_setting(bp); |
e2dc9b6e | 9152 | mutex_unlock(&bp->link_lock); |
a1ef4a79 | 9153 | if (rc) { |
ba41d46f | 9154 | netdev_warn(bp->dev, "failed to update phy settings\n"); |
a1ef4a79 MC |
9155 | if (BNXT_SINGLE_PF(bp)) { |
9156 | bp->link_info.phy_retry = true; | |
9157 | bp->link_info.phy_retry_expires = | |
9158 | jiffies + 5 * HZ; | |
9159 | } | |
9160 | } | |
c0c050c5 MC |
9161 | } |
9162 | ||
7cdd5fc3 | 9163 | if (irq_re_init) |
ad51b8e9 | 9164 | udp_tunnel_get_rx_info(bp->dev); |
c0c050c5 | 9165 | |
caefe526 | 9166 | set_bit(BNXT_STATE_OPEN, &bp->state); |
c0c050c5 MC |
9167 | bnxt_enable_int(bp); |
9168 | /* Enable TX queues */ | |
9169 | bnxt_tx_enable(bp); | |
9170 | mod_timer(&bp->timer, jiffies + bp->current_interval); | |
10289bec MC |
9171 | /* Poll link status and check for SFP+ module status */ |
9172 | bnxt_get_port_module_status(bp); | |
c0c050c5 | 9173 | |
ee5c7fb3 SP |
9174 | /* VF-reps may need to be re-opened after the PF is re-opened */ |
9175 | if (BNXT_PF(bp)) | |
9176 | bnxt_vf_reps_open(bp); | |
c0c050c5 MC |
9177 | return 0; |
9178 | ||
9179 | open_err: | |
cabfb09d | 9180 | bnxt_debug_dev_exit(bp); |
c0c050c5 | 9181 | bnxt_disable_napi(bp); |
c58387ab VG |
9182 | |
9183 | open_err_irq: | |
c0c050c5 MC |
9184 | bnxt_del_napi(bp); |
9185 | ||
9186 | open_err_free_mem: | |
9187 | bnxt_free_skbs(bp); | |
9188 | bnxt_free_irq(bp); | |
9189 | bnxt_free_mem(bp, true); | |
9190 | return rc; | |
9191 | } | |
9192 | ||
9193 | /* rtnl_lock held */ | |
9194 | int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) | |
9195 | { | |
9196 | int rc = 0; | |
9197 | ||
9198 | rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); | |
9199 | if (rc) { | |
9200 | netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); | |
9201 | dev_close(bp->dev); | |
9202 | } | |
9203 | return rc; | |
9204 | } | |
9205 | ||
f7dc1ea6 MC |
9206 | /* rtnl_lock held, open the NIC half way by allocating all resources, but |
9207 | * NAPI, IRQ, and TX are not enabled. This is mainly used for offline | |
9208 | * self tests. | |
9209 | */ | |
9210 | int bnxt_half_open_nic(struct bnxt *bp) | |
9211 | { | |
9212 | int rc = 0; | |
9213 | ||
9214 | rc = bnxt_alloc_mem(bp, false); | |
9215 | if (rc) { | |
9216 | netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); | |
9217 | goto half_open_err; | |
9218 | } | |
9219 | rc = bnxt_init_nic(bp, false); | |
9220 | if (rc) { | |
9221 | netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); | |
9222 | goto half_open_err; | |
9223 | } | |
9224 | return 0; | |
9225 | ||
9226 | half_open_err: | |
9227 | bnxt_free_skbs(bp); | |
9228 | bnxt_free_mem(bp, false); | |
9229 | dev_close(bp->dev); | |
9230 | return rc; | |
9231 | } | |
9232 | ||
9233 | /* rtnl_lock held, this call can only be made after a previous successful | |
9234 | * call to bnxt_half_open_nic(). | |
9235 | */ | |
9236 | void bnxt_half_close_nic(struct bnxt *bp) | |
9237 | { | |
9238 | bnxt_hwrm_resource_free(bp, false, false); | |
9239 | bnxt_free_skbs(bp); | |
9240 | bnxt_free_mem(bp, false); | |
9241 | } | |
9242 | ||
c0c050c5 MC |
9243 | static int bnxt_open(struct net_device *dev) |
9244 | { | |
9245 | struct bnxt *bp = netdev_priv(dev); | |
25e1acd6 | 9246 | int rc; |
c0c050c5 | 9247 | |
ec5d31e3 MC |
9248 | if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) { |
9249 | netdev_err(bp->dev, "A previous firmware reset did not complete, aborting\n"); | |
9250 | return -ENODEV; | |
9251 | } | |
9252 | ||
9253 | rc = bnxt_hwrm_if_change(bp, true); | |
25e1acd6 | 9254 | if (rc) |
ec5d31e3 MC |
9255 | return rc; |
9256 | rc = __bnxt_open_nic(bp, true, true); | |
9257 | if (rc) { | |
25e1acd6 | 9258 | bnxt_hwrm_if_change(bp, false); |
ec5d31e3 | 9259 | } else { |
f3a6d206 VV |
9260 | if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) { |
9261 | if (BNXT_PF(bp)) { | |
9262 | struct bnxt_pf_info *pf = &bp->pf; | |
9263 | int n = pf->active_vfs; | |
cde49a42 | 9264 | |
f3a6d206 VV |
9265 | if (n) |
9266 | bnxt_cfg_hw_sriov(bp, &n, true); | |
9267 | } | |
9268 | if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) | |
9269 | bnxt_ulp_start(bp, 0); | |
ec5d31e3 MC |
9270 | } |
9271 | bnxt_hwmon_open(bp); | |
9272 | } | |
cde49a42 | 9273 | |
25e1acd6 | 9274 | return rc; |
c0c050c5 MC |
9275 | } |
9276 | ||
f9b76ebd MC |
9277 | static bool bnxt_drv_busy(struct bnxt *bp) |
9278 | { | |
9279 | return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) || | |
9280 | test_bit(BNXT_STATE_READ_STATS, &bp->state)); | |
9281 | } | |
9282 | ||
b8875ca3 MC |
9283 | static void bnxt_get_ring_stats(struct bnxt *bp, |
9284 | struct rtnl_link_stats64 *stats); | |
9285 | ||
86e953db MC |
9286 | static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init, |
9287 | bool link_re_init) | |
c0c050c5 | 9288 | { |
ee5c7fb3 SP |
9289 | /* Close the VF-reps before closing PF */ |
9290 | if (BNXT_PF(bp)) | |
9291 | bnxt_vf_reps_close(bp); | |
86e953db | 9292 | |
c0c050c5 MC |
9293 | /* Change device state to avoid TX queue wake up's */ |
9294 | bnxt_tx_disable(bp); | |
9295 | ||
caefe526 | 9296 | clear_bit(BNXT_STATE_OPEN, &bp->state); |
4cebdcec | 9297 | smp_mb__after_atomic(); |
f9b76ebd | 9298 | while (bnxt_drv_busy(bp)) |
4cebdcec | 9299 | msleep(20); |
c0c050c5 | 9300 | |
9d8bc097 | 9301 | /* Flush rings and and disable interrupts */ |
c0c050c5 MC |
9302 | bnxt_shutdown_nic(bp, irq_re_init); |
9303 | ||
9304 | /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ | |
9305 | ||
cabfb09d | 9306 | bnxt_debug_dev_exit(bp); |
c0c050c5 | 9307 | bnxt_disable_napi(bp); |
c0c050c5 | 9308 | del_timer_sync(&bp->timer); |
3bc7d4a3 MC |
9309 | if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && |
9310 | pci_is_enabled(bp->pdev)) | |
9311 | pci_disable_device(bp->pdev); | |
9312 | ||
c0c050c5 MC |
9313 | bnxt_free_skbs(bp); |
9314 | ||
b8875ca3 MC |
9315 | /* Save ring stats before shutdown */ |
9316 | if (bp->bnapi) | |
9317 | bnxt_get_ring_stats(bp, &bp->net_stats_prev); | |
c0c050c5 MC |
9318 | if (irq_re_init) { |
9319 | bnxt_free_irq(bp); | |
9320 | bnxt_del_napi(bp); | |
9321 | } | |
9322 | bnxt_free_mem(bp, irq_re_init); | |
86e953db MC |
9323 | } |
9324 | ||
9325 | int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) | |
9326 | { | |
9327 | int rc = 0; | |
9328 | ||
3bc7d4a3 MC |
9329 | if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { |
9330 | /* If we get here, it means firmware reset is in progress | |
9331 | * while we are trying to close. We can safely proceed with | |
9332 | * the close because we are holding rtnl_lock(). Some firmware | |
9333 | * messages may fail as we proceed to close. We set the | |
9334 | * ABORT_ERR flag here so that the FW reset thread will later | |
9335 | * abort when it gets the rtnl_lock() and sees the flag. | |
9336 | */ | |
9337 | netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n"); | |
9338 | set_bit(BNXT_STATE_ABORT_ERR, &bp->state); | |
9339 | } | |
9340 | ||
86e953db MC |
9341 | #ifdef CONFIG_BNXT_SRIOV |
9342 | if (bp->sriov_cfg) { | |
9343 | rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, | |
9344 | !bp->sriov_cfg, | |
9345 | BNXT_SRIOV_CFG_WAIT_TMO); | |
9346 | if (rc) | |
9347 | netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); | |
9348 | } | |
9349 | #endif | |
9350 | __bnxt_close_nic(bp, irq_re_init, link_re_init); | |
c0c050c5 MC |
9351 | return rc; |
9352 | } | |
9353 | ||
9354 | static int bnxt_close(struct net_device *dev) | |
9355 | { | |
9356 | struct bnxt *bp = netdev_priv(dev); | |
9357 | ||
cde49a42 | 9358 | bnxt_hwmon_close(bp); |
c0c050c5 | 9359 | bnxt_close_nic(bp, true, true); |
33f7d55f | 9360 | bnxt_hwrm_shutdown_link(bp); |
25e1acd6 | 9361 | bnxt_hwrm_if_change(bp, false); |
c0c050c5 MC |
9362 | return 0; |
9363 | } | |
9364 | ||
0ca12be9 VV |
9365 | static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg, |
9366 | u16 *val) | |
9367 | { | |
9368 | struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr; | |
9369 | struct hwrm_port_phy_mdio_read_input req = {0}; | |
9370 | int rc; | |
9371 | ||
9372 | if (bp->hwrm_spec_code < 0x10a00) | |
9373 | return -EOPNOTSUPP; | |
9374 | ||
9375 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1); | |
9376 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
9377 | req.phy_addr = phy_addr; | |
9378 | req.reg_addr = cpu_to_le16(reg & 0x1f); | |
2730214d | 9379 | if (mdio_phy_id_is_c45(phy_addr)) { |
0ca12be9 VV |
9380 | req.cl45_mdio = 1; |
9381 | req.phy_addr = mdio_phy_id_prtad(phy_addr); | |
9382 | req.dev_addr = mdio_phy_id_devad(phy_addr); | |
9383 | req.reg_addr = cpu_to_le16(reg); | |
9384 | } | |
9385 | ||
9386 | mutex_lock(&bp->hwrm_cmd_lock); | |
9387 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
9388 | if (!rc) | |
9389 | *val = le16_to_cpu(resp->reg_data); | |
9390 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9391 | return rc; | |
9392 | } | |
9393 | ||
9394 | static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg, | |
9395 | u16 val) | |
9396 | { | |
9397 | struct hwrm_port_phy_mdio_write_input req = {0}; | |
9398 | ||
9399 | if (bp->hwrm_spec_code < 0x10a00) | |
9400 | return -EOPNOTSUPP; | |
9401 | ||
9402 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1); | |
9403 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
9404 | req.phy_addr = phy_addr; | |
9405 | req.reg_addr = cpu_to_le16(reg & 0x1f); | |
2730214d | 9406 | if (mdio_phy_id_is_c45(phy_addr)) { |
0ca12be9 VV |
9407 | req.cl45_mdio = 1; |
9408 | req.phy_addr = mdio_phy_id_prtad(phy_addr); | |
9409 | req.dev_addr = mdio_phy_id_devad(phy_addr); | |
9410 | req.reg_addr = cpu_to_le16(reg); | |
9411 | } | |
9412 | req.reg_data = cpu_to_le16(val); | |
9413 | ||
9414 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
9415 | } | |
9416 | ||
c0c050c5 MC |
9417 | /* rtnl_lock held */ |
9418 | static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
9419 | { | |
0ca12be9 VV |
9420 | struct mii_ioctl_data *mdio = if_mii(ifr); |
9421 | struct bnxt *bp = netdev_priv(dev); | |
9422 | int rc; | |
9423 | ||
c0c050c5 MC |
9424 | switch (cmd) { |
9425 | case SIOCGMIIPHY: | |
0ca12be9 VV |
9426 | mdio->phy_id = bp->link_info.phy_addr; |
9427 | ||
c0c050c5 MC |
9428 | /* fallthru */ |
9429 | case SIOCGMIIREG: { | |
0ca12be9 VV |
9430 | u16 mii_regval = 0; |
9431 | ||
c0c050c5 MC |
9432 | if (!netif_running(dev)) |
9433 | return -EAGAIN; | |
9434 | ||
0ca12be9 VV |
9435 | rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num, |
9436 | &mii_regval); | |
9437 | mdio->val_out = mii_regval; | |
9438 | return rc; | |
c0c050c5 MC |
9439 | } |
9440 | ||
9441 | case SIOCSMIIREG: | |
9442 | if (!netif_running(dev)) | |
9443 | return -EAGAIN; | |
9444 | ||
0ca12be9 VV |
9445 | return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num, |
9446 | mdio->val_in); | |
c0c050c5 MC |
9447 | |
9448 | default: | |
9449 | /* do nothing */ | |
9450 | break; | |
9451 | } | |
9452 | return -EOPNOTSUPP; | |
9453 | } | |
9454 | ||
b8875ca3 MC |
9455 | static void bnxt_get_ring_stats(struct bnxt *bp, |
9456 | struct rtnl_link_stats64 *stats) | |
c0c050c5 | 9457 | { |
b8875ca3 | 9458 | int i; |
c0c050c5 | 9459 | |
c0c050c5 | 9460 | |
c0c050c5 MC |
9461 | for (i = 0; i < bp->cp_nr_rings; i++) { |
9462 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
9463 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
9464 | struct ctx_hw_stats *hw_stats = cpr->hw_stats; | |
9465 | ||
9466 | stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts); | |
9467 | stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts); | |
9468 | stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts); | |
9469 | ||
9470 | stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts); | |
9471 | stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts); | |
9472 | stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts); | |
9473 | ||
9474 | stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes); | |
9475 | stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes); | |
9476 | stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes); | |
9477 | ||
9478 | stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes); | |
9479 | stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes); | |
9480 | stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes); | |
9481 | ||
9482 | stats->rx_missed_errors += | |
9483 | le64_to_cpu(hw_stats->rx_discard_pkts); | |
9484 | ||
9485 | stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts); | |
9486 | ||
c0c050c5 MC |
9487 | stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts); |
9488 | } | |
b8875ca3 MC |
9489 | } |
9490 | ||
9491 | static void bnxt_add_prev_stats(struct bnxt *bp, | |
9492 | struct rtnl_link_stats64 *stats) | |
9493 | { | |
9494 | struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev; | |
9495 | ||
9496 | stats->rx_packets += prev_stats->rx_packets; | |
9497 | stats->tx_packets += prev_stats->tx_packets; | |
9498 | stats->rx_bytes += prev_stats->rx_bytes; | |
9499 | stats->tx_bytes += prev_stats->tx_bytes; | |
9500 | stats->rx_missed_errors += prev_stats->rx_missed_errors; | |
9501 | stats->multicast += prev_stats->multicast; | |
9502 | stats->tx_dropped += prev_stats->tx_dropped; | |
9503 | } | |
9504 | ||
9505 | static void | |
9506 | bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) | |
9507 | { | |
9508 | struct bnxt *bp = netdev_priv(dev); | |
9509 | ||
9510 | set_bit(BNXT_STATE_READ_STATS, &bp->state); | |
9511 | /* Make sure bnxt_close_nic() sees that we are reading stats before | |
9512 | * we check the BNXT_STATE_OPEN flag. | |
9513 | */ | |
9514 | smp_mb__after_atomic(); | |
9515 | if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { | |
9516 | clear_bit(BNXT_STATE_READ_STATS, &bp->state); | |
9517 | *stats = bp->net_stats_prev; | |
9518 | return; | |
9519 | } | |
9520 | ||
9521 | bnxt_get_ring_stats(bp, stats); | |
9522 | bnxt_add_prev_stats(bp, stats); | |
c0c050c5 | 9523 | |
9947f83f MC |
9524 | if (bp->flags & BNXT_FLAG_PORT_STATS) { |
9525 | struct rx_port_stats *rx = bp->hw_rx_port_stats; | |
9526 | struct tx_port_stats *tx = bp->hw_tx_port_stats; | |
9527 | ||
9528 | stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames); | |
9529 | stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames); | |
9530 | stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) + | |
9531 | le64_to_cpu(rx->rx_ovrsz_frames) + | |
9532 | le64_to_cpu(rx->rx_runt_frames); | |
9533 | stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) + | |
9534 | le64_to_cpu(rx->rx_jbr_frames); | |
9535 | stats->collisions = le64_to_cpu(tx->tx_total_collisions); | |
9536 | stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns); | |
9537 | stats->tx_errors = le64_to_cpu(tx->tx_err); | |
9538 | } | |
f9b76ebd | 9539 | clear_bit(BNXT_STATE_READ_STATS, &bp->state); |
c0c050c5 MC |
9540 | } |
9541 | ||
9542 | static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) | |
9543 | { | |
9544 | struct net_device *dev = bp->dev; | |
9545 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; | |
9546 | struct netdev_hw_addr *ha; | |
9547 | u8 *haddr; | |
9548 | int mc_count = 0; | |
9549 | bool update = false; | |
9550 | int off = 0; | |
9551 | ||
9552 | netdev_for_each_mc_addr(ha, dev) { | |
9553 | if (mc_count >= BNXT_MAX_MC_ADDRS) { | |
9554 | *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; | |
9555 | vnic->mc_list_count = 0; | |
9556 | return false; | |
9557 | } | |
9558 | haddr = ha->addr; | |
9559 | if (!ether_addr_equal(haddr, vnic->mc_list + off)) { | |
9560 | memcpy(vnic->mc_list + off, haddr, ETH_ALEN); | |
9561 | update = true; | |
9562 | } | |
9563 | off += ETH_ALEN; | |
9564 | mc_count++; | |
9565 | } | |
9566 | if (mc_count) | |
9567 | *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; | |
9568 | ||
9569 | if (mc_count != vnic->mc_list_count) { | |
9570 | vnic->mc_list_count = mc_count; | |
9571 | update = true; | |
9572 | } | |
9573 | return update; | |
9574 | } | |
9575 | ||
9576 | static bool bnxt_uc_list_updated(struct bnxt *bp) | |
9577 | { | |
9578 | struct net_device *dev = bp->dev; | |
9579 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; | |
9580 | struct netdev_hw_addr *ha; | |
9581 | int off = 0; | |
9582 | ||
9583 | if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) | |
9584 | return true; | |
9585 | ||
9586 | netdev_for_each_uc_addr(ha, dev) { | |
9587 | if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) | |
9588 | return true; | |
9589 | ||
9590 | off += ETH_ALEN; | |
9591 | } | |
9592 | return false; | |
9593 | } | |
9594 | ||
9595 | static void bnxt_set_rx_mode(struct net_device *dev) | |
9596 | { | |
9597 | struct bnxt *bp = netdev_priv(dev); | |
268d0895 | 9598 | struct bnxt_vnic_info *vnic; |
c0c050c5 MC |
9599 | bool mc_update = false; |
9600 | bool uc_update; | |
268d0895 | 9601 | u32 mask; |
c0c050c5 | 9602 | |
268d0895 | 9603 | if (!test_bit(BNXT_STATE_OPEN, &bp->state)) |
c0c050c5 MC |
9604 | return; |
9605 | ||
268d0895 MC |
9606 | vnic = &bp->vnic_info[0]; |
9607 | mask = vnic->rx_mask; | |
c0c050c5 MC |
9608 | mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | |
9609 | CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | | |
30e33848 MC |
9610 | CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST | |
9611 | CFA_L2_SET_RX_MASK_REQ_MASK_BCAST); | |
c0c050c5 | 9612 | |
17c71ac3 | 9613 | if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) |
c0c050c5 MC |
9614 | mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; |
9615 | ||
9616 | uc_update = bnxt_uc_list_updated(bp); | |
9617 | ||
30e33848 MC |
9618 | if (dev->flags & IFF_BROADCAST) |
9619 | mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; | |
c0c050c5 MC |
9620 | if (dev->flags & IFF_ALLMULTI) { |
9621 | mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; | |
9622 | vnic->mc_list_count = 0; | |
9623 | } else { | |
9624 | mc_update = bnxt_mc_list_updated(bp, &mask); | |
9625 | } | |
9626 | ||
9627 | if (mask != vnic->rx_mask || uc_update || mc_update) { | |
9628 | vnic->rx_mask = mask; | |
9629 | ||
9630 | set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); | |
c213eae8 | 9631 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
9632 | } |
9633 | } | |
9634 | ||
b664f008 | 9635 | static int bnxt_cfg_rx_mode(struct bnxt *bp) |
c0c050c5 MC |
9636 | { |
9637 | struct net_device *dev = bp->dev; | |
9638 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; | |
9639 | struct netdev_hw_addr *ha; | |
9640 | int i, off = 0, rc; | |
9641 | bool uc_update; | |
9642 | ||
9643 | netif_addr_lock_bh(dev); | |
9644 | uc_update = bnxt_uc_list_updated(bp); | |
9645 | netif_addr_unlock_bh(dev); | |
9646 | ||
9647 | if (!uc_update) | |
9648 | goto skip_uc; | |
9649 | ||
9650 | mutex_lock(&bp->hwrm_cmd_lock); | |
9651 | for (i = 1; i < vnic->uc_filter_count; i++) { | |
9652 | struct hwrm_cfa_l2_filter_free_input req = {0}; | |
9653 | ||
9654 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1, | |
9655 | -1); | |
9656 | ||
9657 | req.l2_filter_id = vnic->fw_l2_filter_id[i]; | |
9658 | ||
9659 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
9660 | HWRM_CMD_TIMEOUT); | |
9661 | } | |
9662 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9663 | ||
9664 | vnic->uc_filter_count = 1; | |
9665 | ||
9666 | netif_addr_lock_bh(dev); | |
9667 | if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { | |
9668 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; | |
9669 | } else { | |
9670 | netdev_for_each_uc_addr(ha, dev) { | |
9671 | memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); | |
9672 | off += ETH_ALEN; | |
9673 | vnic->uc_filter_count++; | |
9674 | } | |
9675 | } | |
9676 | netif_addr_unlock_bh(dev); | |
9677 | ||
9678 | for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { | |
9679 | rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); | |
9680 | if (rc) { | |
9681 | netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", | |
9682 | rc); | |
9683 | vnic->uc_filter_count = i; | |
b664f008 | 9684 | return rc; |
c0c050c5 MC |
9685 | } |
9686 | } | |
9687 | ||
9688 | skip_uc: | |
9689 | rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); | |
b4e30e8e MC |
9690 | if (rc && vnic->mc_list_count) { |
9691 | netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n", | |
9692 | rc); | |
9693 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; | |
9694 | vnic->mc_list_count = 0; | |
9695 | rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); | |
9696 | } | |
c0c050c5 | 9697 | if (rc) |
b4e30e8e | 9698 | netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n", |
c0c050c5 | 9699 | rc); |
b664f008 MC |
9700 | |
9701 | return rc; | |
c0c050c5 MC |
9702 | } |
9703 | ||
2773dfb2 MC |
9704 | static bool bnxt_can_reserve_rings(struct bnxt *bp) |
9705 | { | |
9706 | #ifdef CONFIG_BNXT_SRIOV | |
f1ca94de | 9707 | if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) { |
2773dfb2 MC |
9708 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; |
9709 | ||
9710 | /* No minimum rings were provisioned by the PF. Don't | |
9711 | * reserve rings by default when device is down. | |
9712 | */ | |
9713 | if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings) | |
9714 | return true; | |
9715 | ||
9716 | if (!netif_running(bp->dev)) | |
9717 | return false; | |
9718 | } | |
9719 | #endif | |
9720 | return true; | |
9721 | } | |
9722 | ||
8079e8f1 MC |
9723 | /* If the chip and firmware supports RFS */ |
9724 | static bool bnxt_rfs_supported(struct bnxt *bp) | |
9725 | { | |
e969ae5b | 9726 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
41136ab3 | 9727 | if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) |
e969ae5b | 9728 | return true; |
41e8d798 | 9729 | return false; |
e969ae5b | 9730 | } |
8079e8f1 MC |
9731 | if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) |
9732 | return true; | |
ae10ae74 MC |
9733 | if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) |
9734 | return true; | |
8079e8f1 MC |
9735 | return false; |
9736 | } | |
9737 | ||
9738 | /* If runtime conditions support RFS */ | |
2bcfa6f6 MC |
9739 | static bool bnxt_rfs_capable(struct bnxt *bp) |
9740 | { | |
9741 | #ifdef CONFIG_RFS_ACCEL | |
8079e8f1 | 9742 | int vnics, max_vnics, max_rss_ctxs; |
2bcfa6f6 | 9743 | |
41e8d798 | 9744 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
ac33906c | 9745 | return bnxt_rfs_supported(bp); |
2773dfb2 | 9746 | if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp)) |
2bcfa6f6 MC |
9747 | return false; |
9748 | ||
9749 | vnics = 1 + bp->rx_nr_rings; | |
8079e8f1 MC |
9750 | max_vnics = bnxt_get_max_func_vnics(bp); |
9751 | max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp); | |
ae10ae74 MC |
9752 | |
9753 | /* RSS contexts not a limiting factor */ | |
9754 | if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) | |
9755 | max_rss_ctxs = max_vnics; | |
8079e8f1 | 9756 | if (vnics > max_vnics || vnics > max_rss_ctxs) { |
6a1eef5b MC |
9757 | if (bp->rx_nr_rings > 1) |
9758 | netdev_warn(bp->dev, | |
9759 | "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n", | |
9760 | min(max_rss_ctxs - 1, max_vnics - 1)); | |
2bcfa6f6 | 9761 | return false; |
a2304909 | 9762 | } |
2bcfa6f6 | 9763 | |
f1ca94de | 9764 | if (!BNXT_NEW_RM(bp)) |
6a1eef5b MC |
9765 | return true; |
9766 | ||
9767 | if (vnics == bp->hw_resc.resv_vnics) | |
9768 | return true; | |
9769 | ||
780baad4 | 9770 | bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics); |
6a1eef5b MC |
9771 | if (vnics <= bp->hw_resc.resv_vnics) |
9772 | return true; | |
9773 | ||
9774 | netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n"); | |
780baad4 | 9775 | bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1); |
6a1eef5b | 9776 | return false; |
2bcfa6f6 MC |
9777 | #else |
9778 | return false; | |
9779 | #endif | |
9780 | } | |
9781 | ||
c0c050c5 MC |
9782 | static netdev_features_t bnxt_fix_features(struct net_device *dev, |
9783 | netdev_features_t features) | |
9784 | { | |
2bcfa6f6 MC |
9785 | struct bnxt *bp = netdev_priv(dev); |
9786 | ||
a2304909 | 9787 | if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp)) |
2bcfa6f6 | 9788 | features &= ~NETIF_F_NTUPLE; |
5a9f6b23 | 9789 | |
1054aee8 MC |
9790 | if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) |
9791 | features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); | |
9792 | ||
9793 | if (!(features & NETIF_F_GRO)) | |
9794 | features &= ~NETIF_F_GRO_HW; | |
9795 | ||
9796 | if (features & NETIF_F_GRO_HW) | |
9797 | features &= ~NETIF_F_LRO; | |
9798 | ||
5a9f6b23 MC |
9799 | /* Both CTAG and STAG VLAN accelaration on the RX side have to be |
9800 | * turned on or off together. | |
9801 | */ | |
9802 | if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) != | |
9803 | (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) { | |
9804 | if (dev->features & NETIF_F_HW_VLAN_CTAG_RX) | |
9805 | features &= ~(NETIF_F_HW_VLAN_CTAG_RX | | |
9806 | NETIF_F_HW_VLAN_STAG_RX); | |
9807 | else | |
9808 | features |= NETIF_F_HW_VLAN_CTAG_RX | | |
9809 | NETIF_F_HW_VLAN_STAG_RX; | |
9810 | } | |
cf6645f8 MC |
9811 | #ifdef CONFIG_BNXT_SRIOV |
9812 | if (BNXT_VF(bp)) { | |
9813 | if (bp->vf.vlan) { | |
9814 | features &= ~(NETIF_F_HW_VLAN_CTAG_RX | | |
9815 | NETIF_F_HW_VLAN_STAG_RX); | |
9816 | } | |
9817 | } | |
9818 | #endif | |
c0c050c5 MC |
9819 | return features; |
9820 | } | |
9821 | ||
9822 | static int bnxt_set_features(struct net_device *dev, netdev_features_t features) | |
9823 | { | |
9824 | struct bnxt *bp = netdev_priv(dev); | |
9825 | u32 flags = bp->flags; | |
9826 | u32 changes; | |
9827 | int rc = 0; | |
9828 | bool re_init = false; | |
9829 | bool update_tpa = false; | |
9830 | ||
9831 | flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; | |
1054aee8 | 9832 | if (features & NETIF_F_GRO_HW) |
c0c050c5 | 9833 | flags |= BNXT_FLAG_GRO; |
1054aee8 | 9834 | else if (features & NETIF_F_LRO) |
c0c050c5 MC |
9835 | flags |= BNXT_FLAG_LRO; |
9836 | ||
bdbd1eb5 MC |
9837 | if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) |
9838 | flags &= ~BNXT_FLAG_TPA; | |
9839 | ||
c0c050c5 MC |
9840 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
9841 | flags |= BNXT_FLAG_STRIP_VLAN; | |
9842 | ||
9843 | if (features & NETIF_F_NTUPLE) | |
9844 | flags |= BNXT_FLAG_RFS; | |
9845 | ||
9846 | changes = flags ^ bp->flags; | |
9847 | if (changes & BNXT_FLAG_TPA) { | |
9848 | update_tpa = true; | |
9849 | if ((bp->flags & BNXT_FLAG_TPA) == 0 || | |
f45b7b78 MC |
9850 | (flags & BNXT_FLAG_TPA) == 0 || |
9851 | (bp->flags & BNXT_FLAG_CHIP_P5)) | |
c0c050c5 MC |
9852 | re_init = true; |
9853 | } | |
9854 | ||
9855 | if (changes & ~BNXT_FLAG_TPA) | |
9856 | re_init = true; | |
9857 | ||
9858 | if (flags != bp->flags) { | |
9859 | u32 old_flags = bp->flags; | |
9860 | ||
2bcfa6f6 | 9861 | if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { |
f45b7b78 | 9862 | bp->flags = flags; |
c0c050c5 MC |
9863 | if (update_tpa) |
9864 | bnxt_set_ring_params(bp); | |
9865 | return rc; | |
9866 | } | |
9867 | ||
9868 | if (re_init) { | |
9869 | bnxt_close_nic(bp, false, false); | |
f45b7b78 | 9870 | bp->flags = flags; |
c0c050c5 MC |
9871 | if (update_tpa) |
9872 | bnxt_set_ring_params(bp); | |
9873 | ||
9874 | return bnxt_open_nic(bp, false, false); | |
9875 | } | |
9876 | if (update_tpa) { | |
f45b7b78 | 9877 | bp->flags = flags; |
c0c050c5 MC |
9878 | rc = bnxt_set_tpa(bp, |
9879 | (flags & BNXT_FLAG_TPA) ? | |
9880 | true : false); | |
9881 | if (rc) | |
9882 | bp->flags = old_flags; | |
9883 | } | |
9884 | } | |
9885 | return rc; | |
9886 | } | |
9887 | ||
ffd77621 MC |
9888 | static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type, |
9889 | u32 ring_id, u32 *prod, u32 *cons) | |
9890 | { | |
9891 | struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr; | |
9892 | struct hwrm_dbg_ring_info_get_input req = {0}; | |
9893 | int rc; | |
9894 | ||
9895 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1); | |
9896 | req.ring_type = ring_type; | |
9897 | req.fw_ring_id = cpu_to_le32(ring_id); | |
9898 | mutex_lock(&bp->hwrm_cmd_lock); | |
9899 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
9900 | if (!rc) { | |
9901 | *prod = le32_to_cpu(resp->producer_index); | |
9902 | *cons = le32_to_cpu(resp->consumer_index); | |
9903 | } | |
9904 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9905 | return rc; | |
9906 | } | |
9907 | ||
9f554590 MC |
9908 | static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) |
9909 | { | |
b6ab4b01 | 9910 | struct bnxt_tx_ring_info *txr = bnapi->tx_ring; |
9f554590 MC |
9911 | int i = bnapi->index; |
9912 | ||
3b2b7d9d MC |
9913 | if (!txr) |
9914 | return; | |
9915 | ||
9f554590 MC |
9916 | netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", |
9917 | i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, | |
9918 | txr->tx_cons); | |
9919 | } | |
9920 | ||
9921 | static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) | |
9922 | { | |
b6ab4b01 | 9923 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
9f554590 MC |
9924 | int i = bnapi->index; |
9925 | ||
3b2b7d9d MC |
9926 | if (!rxr) |
9927 | return; | |
9928 | ||
9f554590 MC |
9929 | netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", |
9930 | i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, | |
9931 | rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, | |
9932 | rxr->rx_sw_agg_prod); | |
9933 | } | |
9934 | ||
9935 | static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) | |
9936 | { | |
9937 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
9938 | int i = bnapi->index; | |
9939 | ||
9940 | netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", | |
9941 | i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); | |
9942 | } | |
9943 | ||
c0c050c5 MC |
9944 | static void bnxt_dbg_dump_states(struct bnxt *bp) |
9945 | { | |
9946 | int i; | |
9947 | struct bnxt_napi *bnapi; | |
c0c050c5 MC |
9948 | |
9949 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
9950 | bnapi = bp->bnapi[i]; | |
c0c050c5 | 9951 | if (netif_msg_drv(bp)) { |
9f554590 MC |
9952 | bnxt_dump_tx_sw_state(bnapi); |
9953 | bnxt_dump_rx_sw_state(bnapi); | |
9954 | bnxt_dump_cp_sw_state(bnapi); | |
c0c050c5 MC |
9955 | } |
9956 | } | |
9957 | } | |
9958 | ||
6988bd92 | 9959 | static void bnxt_reset_task(struct bnxt *bp, bool silent) |
c0c050c5 | 9960 | { |
6988bd92 MC |
9961 | if (!silent) |
9962 | bnxt_dbg_dump_states(bp); | |
028de140 | 9963 | if (netif_running(bp->dev)) { |
b386cd36 MC |
9964 | int rc; |
9965 | ||
aa46dfff VV |
9966 | if (silent) { |
9967 | bnxt_close_nic(bp, false, false); | |
9968 | bnxt_open_nic(bp, false, false); | |
9969 | } else { | |
b386cd36 | 9970 | bnxt_ulp_stop(bp); |
aa46dfff VV |
9971 | bnxt_close_nic(bp, true, false); |
9972 | rc = bnxt_open_nic(bp, true, false); | |
9973 | bnxt_ulp_start(bp, rc); | |
9974 | } | |
028de140 | 9975 | } |
c0c050c5 MC |
9976 | } |
9977 | ||
0290bd29 | 9978 | static void bnxt_tx_timeout(struct net_device *dev, unsigned int txqueue) |
c0c050c5 MC |
9979 | { |
9980 | struct bnxt *bp = netdev_priv(dev); | |
9981 | ||
9982 | netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); | |
9983 | set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); | |
c213eae8 | 9984 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
9985 | } |
9986 | ||
acfb50e4 VV |
9987 | static void bnxt_fw_health_check(struct bnxt *bp) |
9988 | { | |
9989 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
9990 | u32 val; | |
9991 | ||
0797c10d | 9992 | if (!fw_health->enabled || test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) |
acfb50e4 VV |
9993 | return; |
9994 | ||
9995 | if (fw_health->tmr_counter) { | |
9996 | fw_health->tmr_counter--; | |
9997 | return; | |
9998 | } | |
9999 | ||
10000 | val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); | |
10001 | if (val == fw_health->last_fw_heartbeat) | |
10002 | goto fw_reset; | |
10003 | ||
10004 | fw_health->last_fw_heartbeat = val; | |
10005 | ||
10006 | val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); | |
10007 | if (val != fw_health->last_fw_reset_cnt) | |
10008 | goto fw_reset; | |
10009 | ||
10010 | fw_health->tmr_counter = fw_health->tmr_multiplier; | |
10011 | return; | |
10012 | ||
10013 | fw_reset: | |
10014 | set_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event); | |
10015 | bnxt_queue_sp_work(bp); | |
10016 | } | |
10017 | ||
e99e88a9 | 10018 | static void bnxt_timer(struct timer_list *t) |
c0c050c5 | 10019 | { |
e99e88a9 | 10020 | struct bnxt *bp = from_timer(bp, t, timer); |
c0c050c5 MC |
10021 | struct net_device *dev = bp->dev; |
10022 | ||
10023 | if (!netif_running(dev)) | |
10024 | return; | |
10025 | ||
10026 | if (atomic_read(&bp->intr_sem) != 0) | |
10027 | goto bnxt_restart_timer; | |
10028 | ||
acfb50e4 VV |
10029 | if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) |
10030 | bnxt_fw_health_check(bp); | |
10031 | ||
adcc331e MC |
10032 | if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) && |
10033 | bp->stats_coal_ticks) { | |
3bdf56c4 | 10034 | set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event); |
c213eae8 | 10035 | bnxt_queue_sp_work(bp); |
3bdf56c4 | 10036 | } |
5a84acbe SP |
10037 | |
10038 | if (bnxt_tc_flower_enabled(bp)) { | |
10039 | set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event); | |
10040 | bnxt_queue_sp_work(bp); | |
10041 | } | |
a1ef4a79 | 10042 | |
87d67f59 PC |
10043 | #ifdef CONFIG_RFS_ACCEL |
10044 | if ((bp->flags & BNXT_FLAG_RFS) && bp->ntp_fltr_count) { | |
10045 | set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); | |
10046 | bnxt_queue_sp_work(bp); | |
10047 | } | |
10048 | #endif /*CONFIG_RFS_ACCEL*/ | |
10049 | ||
a1ef4a79 MC |
10050 | if (bp->link_info.phy_retry) { |
10051 | if (time_after(jiffies, bp->link_info.phy_retry_expires)) { | |
acda6180 | 10052 | bp->link_info.phy_retry = false; |
a1ef4a79 MC |
10053 | netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n"); |
10054 | } else { | |
10055 | set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event); | |
10056 | bnxt_queue_sp_work(bp); | |
10057 | } | |
10058 | } | |
ffd77621 MC |
10059 | |
10060 | if ((bp->flags & BNXT_FLAG_CHIP_P5) && netif_carrier_ok(dev)) { | |
10061 | set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event); | |
10062 | bnxt_queue_sp_work(bp); | |
10063 | } | |
c0c050c5 MC |
10064 | bnxt_restart_timer: |
10065 | mod_timer(&bp->timer, jiffies + bp->current_interval); | |
10066 | } | |
10067 | ||
a551ee94 | 10068 | static void bnxt_rtnl_lock_sp(struct bnxt *bp) |
6988bd92 | 10069 | { |
a551ee94 MC |
10070 | /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK |
10071 | * set. If the device is being closed, bnxt_close() may be holding | |
6988bd92 MC |
10072 | * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we |
10073 | * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). | |
10074 | */ | |
10075 | clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); | |
10076 | rtnl_lock(); | |
a551ee94 MC |
10077 | } |
10078 | ||
10079 | static void bnxt_rtnl_unlock_sp(struct bnxt *bp) | |
10080 | { | |
6988bd92 MC |
10081 | set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); |
10082 | rtnl_unlock(); | |
10083 | } | |
10084 | ||
a551ee94 MC |
10085 | /* Only called from bnxt_sp_task() */ |
10086 | static void bnxt_reset(struct bnxt *bp, bool silent) | |
10087 | { | |
10088 | bnxt_rtnl_lock_sp(bp); | |
10089 | if (test_bit(BNXT_STATE_OPEN, &bp->state)) | |
10090 | bnxt_reset_task(bp, silent); | |
10091 | bnxt_rtnl_unlock_sp(bp); | |
10092 | } | |
10093 | ||
230d1f0d MC |
10094 | static void bnxt_fw_reset_close(struct bnxt *bp) |
10095 | { | |
f3a6d206 | 10096 | bnxt_ulp_stop(bp); |
230d1f0d | 10097 | __bnxt_close_nic(bp, true, false); |
230d1f0d MC |
10098 | bnxt_clear_int_mode(bp); |
10099 | bnxt_hwrm_func_drv_unrgtr(bp); | |
10100 | bnxt_free_ctx_mem(bp); | |
10101 | kfree(bp->ctx); | |
10102 | bp->ctx = NULL; | |
10103 | } | |
10104 | ||
acfb50e4 VV |
10105 | static bool is_bnxt_fw_ok(struct bnxt *bp) |
10106 | { | |
10107 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
10108 | bool no_heartbeat = false, has_reset = false; | |
10109 | u32 val; | |
10110 | ||
10111 | val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); | |
10112 | if (val == fw_health->last_fw_heartbeat) | |
10113 | no_heartbeat = true; | |
10114 | ||
10115 | val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); | |
10116 | if (val != fw_health->last_fw_reset_cnt) | |
10117 | has_reset = true; | |
10118 | ||
10119 | if (!no_heartbeat && has_reset) | |
10120 | return true; | |
10121 | ||
10122 | return false; | |
10123 | } | |
10124 | ||
d1db9e16 MC |
10125 | /* rtnl_lock is acquired before calling this function */ |
10126 | static void bnxt_force_fw_reset(struct bnxt *bp) | |
10127 | { | |
10128 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
10129 | u32 wait_dsecs; | |
10130 | ||
10131 | if (!test_bit(BNXT_STATE_OPEN, &bp->state) || | |
10132 | test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) | |
10133 | return; | |
10134 | ||
10135 | set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
10136 | bnxt_fw_reset_close(bp); | |
10137 | wait_dsecs = fw_health->master_func_wait_dsecs; | |
10138 | if (fw_health->master) { | |
10139 | if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) | |
10140 | wait_dsecs = 0; | |
10141 | bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; | |
10142 | } else { | |
10143 | bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10; | |
10144 | wait_dsecs = fw_health->normal_func_wait_dsecs; | |
10145 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
10146 | } | |
4037eb71 VV |
10147 | |
10148 | bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs; | |
d1db9e16 MC |
10149 | bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs; |
10150 | bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); | |
10151 | } | |
10152 | ||
10153 | void bnxt_fw_exception(struct bnxt *bp) | |
10154 | { | |
a2b31e27 | 10155 | netdev_warn(bp->dev, "Detected firmware fatal condition, initiating reset\n"); |
d1db9e16 MC |
10156 | set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); |
10157 | bnxt_rtnl_lock_sp(bp); | |
10158 | bnxt_force_fw_reset(bp); | |
10159 | bnxt_rtnl_unlock_sp(bp); | |
10160 | } | |
10161 | ||
e72cb7d6 MC |
10162 | /* Returns the number of registered VFs, or 1 if VF configuration is pending, or |
10163 | * < 0 on error. | |
10164 | */ | |
10165 | static int bnxt_get_registered_vfs(struct bnxt *bp) | |
230d1f0d | 10166 | { |
e72cb7d6 | 10167 | #ifdef CONFIG_BNXT_SRIOV |
230d1f0d MC |
10168 | int rc; |
10169 | ||
e72cb7d6 MC |
10170 | if (!BNXT_PF(bp)) |
10171 | return 0; | |
10172 | ||
10173 | rc = bnxt_hwrm_func_qcfg(bp); | |
10174 | if (rc) { | |
10175 | netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc); | |
10176 | return rc; | |
10177 | } | |
10178 | if (bp->pf.registered_vfs) | |
10179 | return bp->pf.registered_vfs; | |
10180 | if (bp->sriov_cfg) | |
10181 | return 1; | |
10182 | #endif | |
10183 | return 0; | |
10184 | } | |
10185 | ||
10186 | void bnxt_fw_reset(struct bnxt *bp) | |
10187 | { | |
230d1f0d MC |
10188 | bnxt_rtnl_lock_sp(bp); |
10189 | if (test_bit(BNXT_STATE_OPEN, &bp->state) && | |
10190 | !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { | |
4037eb71 | 10191 | int n = 0, tmo; |
e72cb7d6 | 10192 | |
230d1f0d | 10193 | set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); |
e72cb7d6 MC |
10194 | if (bp->pf.active_vfs && |
10195 | !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) | |
10196 | n = bnxt_get_registered_vfs(bp); | |
10197 | if (n < 0) { | |
10198 | netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n", | |
10199 | n); | |
10200 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
10201 | dev_close(bp->dev); | |
10202 | goto fw_reset_exit; | |
10203 | } else if (n > 0) { | |
10204 | u16 vf_tmo_dsecs = n * 10; | |
10205 | ||
10206 | if (bp->fw_reset_max_dsecs < vf_tmo_dsecs) | |
10207 | bp->fw_reset_max_dsecs = vf_tmo_dsecs; | |
10208 | bp->fw_reset_state = | |
10209 | BNXT_FW_RESET_STATE_POLL_VF; | |
10210 | bnxt_queue_fw_reset_work(bp, HZ / 10); | |
10211 | goto fw_reset_exit; | |
230d1f0d MC |
10212 | } |
10213 | bnxt_fw_reset_close(bp); | |
4037eb71 VV |
10214 | if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { |
10215 | bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; | |
10216 | tmo = HZ / 10; | |
10217 | } else { | |
10218 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
10219 | tmo = bp->fw_reset_min_dsecs * HZ / 10; | |
10220 | } | |
10221 | bnxt_queue_fw_reset_work(bp, tmo); | |
230d1f0d MC |
10222 | } |
10223 | fw_reset_exit: | |
10224 | bnxt_rtnl_unlock_sp(bp); | |
10225 | } | |
10226 | ||
ffd77621 MC |
10227 | static void bnxt_chk_missed_irq(struct bnxt *bp) |
10228 | { | |
10229 | int i; | |
10230 | ||
10231 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
10232 | return; | |
10233 | ||
10234 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
10235 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
10236 | struct bnxt_cp_ring_info *cpr; | |
10237 | u32 fw_ring_id; | |
10238 | int j; | |
10239 | ||
10240 | if (!bnapi) | |
10241 | continue; | |
10242 | ||
10243 | cpr = &bnapi->cp_ring; | |
10244 | for (j = 0; j < 2; j++) { | |
10245 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; | |
10246 | u32 val[2]; | |
10247 | ||
10248 | if (!cpr2 || cpr2->has_more_work || | |
10249 | !bnxt_has_work(bp, cpr2)) | |
10250 | continue; | |
10251 | ||
10252 | if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) { | |
10253 | cpr2->last_cp_raw_cons = cpr2->cp_raw_cons; | |
10254 | continue; | |
10255 | } | |
10256 | fw_ring_id = cpr2->cp_ring_struct.fw_ring_id; | |
10257 | bnxt_dbg_hwrm_ring_info_get(bp, | |
10258 | DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL, | |
10259 | fw_ring_id, &val[0], &val[1]); | |
83eb5c5c | 10260 | cpr->missed_irqs++; |
ffd77621 MC |
10261 | } |
10262 | } | |
10263 | } | |
10264 | ||
c0c050c5 MC |
10265 | static void bnxt_cfg_ntp_filters(struct bnxt *); |
10266 | ||
8119e49b MC |
10267 | static void bnxt_init_ethtool_link_settings(struct bnxt *bp) |
10268 | { | |
10269 | struct bnxt_link_info *link_info = &bp->link_info; | |
10270 | ||
10271 | if (BNXT_AUTO_MODE(link_info->auto_mode)) { | |
10272 | link_info->autoneg = BNXT_AUTONEG_SPEED; | |
10273 | if (bp->hwrm_spec_code >= 0x10201) { | |
10274 | if (link_info->auto_pause_setting & | |
10275 | PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE) | |
10276 | link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; | |
10277 | } else { | |
10278 | link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; | |
10279 | } | |
10280 | link_info->advertising = link_info->auto_link_speeds; | |
10281 | } else { | |
10282 | link_info->req_link_speed = link_info->force_link_speed; | |
10283 | link_info->req_duplex = link_info->duplex_setting; | |
10284 | } | |
10285 | if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) | |
10286 | link_info->req_flow_ctrl = | |
10287 | link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH; | |
10288 | else | |
10289 | link_info->req_flow_ctrl = link_info->force_pause_setting; | |
10290 | } | |
10291 | ||
c0c050c5 MC |
10292 | static void bnxt_sp_task(struct work_struct *work) |
10293 | { | |
10294 | struct bnxt *bp = container_of(work, struct bnxt, sp_task); | |
c0c050c5 | 10295 | |
4cebdcec MC |
10296 | set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); |
10297 | smp_mb__after_atomic(); | |
10298 | if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { | |
10299 | clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); | |
c0c050c5 | 10300 | return; |
4cebdcec | 10301 | } |
c0c050c5 MC |
10302 | |
10303 | if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) | |
10304 | bnxt_cfg_rx_mode(bp); | |
10305 | ||
10306 | if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) | |
10307 | bnxt_cfg_ntp_filters(bp); | |
c0c050c5 MC |
10308 | if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) |
10309 | bnxt_hwrm_exec_fwd_req(bp); | |
10310 | if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) { | |
10311 | bnxt_hwrm_tunnel_dst_port_alloc( | |
10312 | bp, bp->vxlan_port, | |
10313 | TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); | |
10314 | } | |
10315 | if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) { | |
10316 | bnxt_hwrm_tunnel_dst_port_free( | |
10317 | bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); | |
10318 | } | |
7cdd5fc3 AD |
10319 | if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) { |
10320 | bnxt_hwrm_tunnel_dst_port_alloc( | |
10321 | bp, bp->nge_port, | |
10322 | TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); | |
10323 | } | |
10324 | if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) { | |
10325 | bnxt_hwrm_tunnel_dst_port_free( | |
10326 | bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); | |
10327 | } | |
00db3cba | 10328 | if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) { |
3bdf56c4 | 10329 | bnxt_hwrm_port_qstats(bp); |
00db3cba | 10330 | bnxt_hwrm_port_qstats_ext(bp); |
55e4398d | 10331 | bnxt_hwrm_pcie_qstats(bp); |
00db3cba | 10332 | } |
3bdf56c4 | 10333 | |
0eaa24b9 | 10334 | if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { |
e2dc9b6e | 10335 | int rc; |
0eaa24b9 | 10336 | |
e2dc9b6e | 10337 | mutex_lock(&bp->link_lock); |
0eaa24b9 MC |
10338 | if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, |
10339 | &bp->sp_event)) | |
10340 | bnxt_hwrm_phy_qcaps(bp); | |
10341 | ||
b1613e78 MC |
10342 | if (test_and_clear_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, |
10343 | &bp->sp_event)) | |
10344 | bnxt_init_ethtool_link_settings(bp); | |
10345 | ||
e2dc9b6e MC |
10346 | rc = bnxt_update_link(bp, true); |
10347 | mutex_unlock(&bp->link_lock); | |
0eaa24b9 MC |
10348 | if (rc) |
10349 | netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", | |
10350 | rc); | |
10351 | } | |
a1ef4a79 MC |
10352 | if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) { |
10353 | int rc; | |
10354 | ||
10355 | mutex_lock(&bp->link_lock); | |
10356 | rc = bnxt_update_phy_setting(bp); | |
10357 | mutex_unlock(&bp->link_lock); | |
10358 | if (rc) { | |
10359 | netdev_warn(bp->dev, "update phy settings retry failed\n"); | |
10360 | } else { | |
10361 | bp->link_info.phy_retry = false; | |
10362 | netdev_info(bp->dev, "update phy settings retry succeeded\n"); | |
10363 | } | |
10364 | } | |
90c694bb | 10365 | if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) { |
e2dc9b6e MC |
10366 | mutex_lock(&bp->link_lock); |
10367 | bnxt_get_port_module_status(bp); | |
10368 | mutex_unlock(&bp->link_lock); | |
90c694bb | 10369 | } |
5a84acbe SP |
10370 | |
10371 | if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event)) | |
10372 | bnxt_tc_flow_stats_work(bp); | |
10373 | ||
ffd77621 MC |
10374 | if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event)) |
10375 | bnxt_chk_missed_irq(bp); | |
10376 | ||
e2dc9b6e MC |
10377 | /* These functions below will clear BNXT_STATE_IN_SP_TASK. They |
10378 | * must be the last functions to be called before exiting. | |
10379 | */ | |
6988bd92 MC |
10380 | if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) |
10381 | bnxt_reset(bp, false); | |
4cebdcec | 10382 | |
fc0f1929 MC |
10383 | if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event)) |
10384 | bnxt_reset(bp, true); | |
10385 | ||
657a33c8 VV |
10386 | if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event)) |
10387 | bnxt_devlink_health_report(bp, BNXT_FW_RESET_NOTIFY_SP_EVENT); | |
10388 | ||
acfb50e4 VV |
10389 | if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) { |
10390 | if (!is_bnxt_fw_ok(bp)) | |
10391 | bnxt_devlink_health_report(bp, | |
10392 | BNXT_FW_EXCEPTION_SP_EVENT); | |
10393 | } | |
10394 | ||
4cebdcec MC |
10395 | smp_mb__before_atomic(); |
10396 | clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); | |
c0c050c5 MC |
10397 | } |
10398 | ||
d1e7925e | 10399 | /* Under rtnl_lock */ |
98fdbe73 MC |
10400 | int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, |
10401 | int tx_xdp) | |
d1e7925e MC |
10402 | { |
10403 | int max_rx, max_tx, tx_sets = 1; | |
780baad4 | 10404 | int tx_rings_needed, stats; |
8f23d638 | 10405 | int rx_rings = rx; |
6fc2ffdf | 10406 | int cp, vnics, rc; |
d1e7925e | 10407 | |
d1e7925e MC |
10408 | if (tcs) |
10409 | tx_sets = tcs; | |
10410 | ||
10411 | rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh); | |
10412 | if (rc) | |
10413 | return rc; | |
10414 | ||
10415 | if (max_rx < rx) | |
10416 | return -ENOMEM; | |
10417 | ||
5f449249 | 10418 | tx_rings_needed = tx * tx_sets + tx_xdp; |
d1e7925e MC |
10419 | if (max_tx < tx_rings_needed) |
10420 | return -ENOMEM; | |
10421 | ||
6fc2ffdf | 10422 | vnics = 1; |
9b3d15e6 | 10423 | if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) |
6fc2ffdf EW |
10424 | vnics += rx_rings; |
10425 | ||
8f23d638 MC |
10426 | if (bp->flags & BNXT_FLAG_AGG_RINGS) |
10427 | rx_rings <<= 1; | |
10428 | cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx; | |
780baad4 VV |
10429 | stats = cp; |
10430 | if (BNXT_NEW_RM(bp)) { | |
11c3ec7b | 10431 | cp += bnxt_get_ulp_msix_num(bp); |
780baad4 VV |
10432 | stats += bnxt_get_ulp_stat_ctxs(bp); |
10433 | } | |
6fc2ffdf | 10434 | return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp, |
780baad4 | 10435 | stats, vnics); |
d1e7925e MC |
10436 | } |
10437 | ||
17086399 SP |
10438 | static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev) |
10439 | { | |
10440 | if (bp->bar2) { | |
10441 | pci_iounmap(pdev, bp->bar2); | |
10442 | bp->bar2 = NULL; | |
10443 | } | |
10444 | ||
10445 | if (bp->bar1) { | |
10446 | pci_iounmap(pdev, bp->bar1); | |
10447 | bp->bar1 = NULL; | |
10448 | } | |
10449 | ||
10450 | if (bp->bar0) { | |
10451 | pci_iounmap(pdev, bp->bar0); | |
10452 | bp->bar0 = NULL; | |
10453 | } | |
10454 | } | |
10455 | ||
10456 | static void bnxt_cleanup_pci(struct bnxt *bp) | |
10457 | { | |
10458 | bnxt_unmap_bars(bp, bp->pdev); | |
10459 | pci_release_regions(bp->pdev); | |
f6824308 VV |
10460 | if (pci_is_enabled(bp->pdev)) |
10461 | pci_disable_device(bp->pdev); | |
17086399 SP |
10462 | } |
10463 | ||
18775aa8 MC |
10464 | static void bnxt_init_dflt_coal(struct bnxt *bp) |
10465 | { | |
10466 | struct bnxt_coal *coal; | |
10467 | ||
10468 | /* Tick values in micro seconds. | |
10469 | * 1 coal_buf x bufs_per_record = 1 completion record. | |
10470 | */ | |
10471 | coal = &bp->rx_coal; | |
0c2ff8d7 | 10472 | coal->coal_ticks = 10; |
18775aa8 MC |
10473 | coal->coal_bufs = 30; |
10474 | coal->coal_ticks_irq = 1; | |
10475 | coal->coal_bufs_irq = 2; | |
05abe4dd | 10476 | coal->idle_thresh = 50; |
18775aa8 MC |
10477 | coal->bufs_per_record = 2; |
10478 | coal->budget = 64; /* NAPI budget */ | |
10479 | ||
10480 | coal = &bp->tx_coal; | |
10481 | coal->coal_ticks = 28; | |
10482 | coal->coal_bufs = 30; | |
10483 | coal->coal_ticks_irq = 2; | |
10484 | coal->coal_bufs_irq = 2; | |
10485 | coal->bufs_per_record = 1; | |
10486 | ||
10487 | bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS; | |
10488 | } | |
10489 | ||
8280b38e VV |
10490 | static void bnxt_alloc_fw_health(struct bnxt *bp) |
10491 | { | |
10492 | if (bp->fw_health) | |
10493 | return; | |
10494 | ||
10495 | if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) && | |
10496 | !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) | |
10497 | return; | |
10498 | ||
10499 | bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL); | |
10500 | if (!bp->fw_health) { | |
10501 | netdev_warn(bp->dev, "Failed to allocate fw_health\n"); | |
10502 | bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET; | |
10503 | bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; | |
10504 | } | |
10505 | } | |
10506 | ||
7c380918 MC |
10507 | static int bnxt_fw_init_one_p1(struct bnxt *bp) |
10508 | { | |
10509 | int rc; | |
10510 | ||
10511 | bp->fw_cap = 0; | |
10512 | rc = bnxt_hwrm_ver_get(bp); | |
10513 | if (rc) | |
10514 | return rc; | |
10515 | ||
10516 | if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) { | |
10517 | rc = bnxt_alloc_kong_hwrm_resources(bp); | |
10518 | if (rc) | |
10519 | bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL; | |
10520 | } | |
10521 | ||
10522 | if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || | |
10523 | bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) { | |
10524 | rc = bnxt_alloc_hwrm_short_cmd_req(bp); | |
10525 | if (rc) | |
10526 | return rc; | |
10527 | } | |
10528 | rc = bnxt_hwrm_func_reset(bp); | |
10529 | if (rc) | |
10530 | return -ENODEV; | |
10531 | ||
10532 | bnxt_hwrm_fw_set_time(bp); | |
10533 | return 0; | |
10534 | } | |
10535 | ||
10536 | static int bnxt_fw_init_one_p2(struct bnxt *bp) | |
10537 | { | |
10538 | int rc; | |
10539 | ||
10540 | /* Get the MAX capabilities for this function */ | |
10541 | rc = bnxt_hwrm_func_qcaps(bp); | |
10542 | if (rc) { | |
10543 | netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", | |
10544 | rc); | |
10545 | return -ENODEV; | |
10546 | } | |
10547 | ||
10548 | rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp); | |
10549 | if (rc) | |
10550 | netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n", | |
10551 | rc); | |
10552 | ||
8280b38e | 10553 | bnxt_alloc_fw_health(bp); |
07f83d72 MC |
10554 | rc = bnxt_hwrm_error_recovery_qcfg(bp); |
10555 | if (rc) | |
10556 | netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n", | |
10557 | rc); | |
10558 | ||
2e882468 | 10559 | rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false); |
7c380918 MC |
10560 | if (rc) |
10561 | return -ENODEV; | |
10562 | ||
10563 | bnxt_hwrm_func_qcfg(bp); | |
10564 | bnxt_hwrm_vnic_qcaps(bp); | |
10565 | bnxt_hwrm_port_led_qcaps(bp); | |
10566 | bnxt_ethtool_init(bp); | |
10567 | bnxt_dcb_init(bp); | |
10568 | return 0; | |
10569 | } | |
10570 | ||
ba642ab7 MC |
10571 | static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp) |
10572 | { | |
10573 | bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP; | |
10574 | bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 | | |
10575 | VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 | | |
10576 | VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | | |
10577 | VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; | |
c66c06c5 | 10578 | if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) { |
ba642ab7 MC |
10579 | bp->flags |= BNXT_FLAG_UDP_RSS_CAP; |
10580 | bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 | | |
10581 | VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; | |
10582 | } | |
10583 | } | |
10584 | ||
10585 | static void bnxt_set_dflt_rfs(struct bnxt *bp) | |
10586 | { | |
10587 | struct net_device *dev = bp->dev; | |
10588 | ||
10589 | dev->hw_features &= ~NETIF_F_NTUPLE; | |
10590 | dev->features &= ~NETIF_F_NTUPLE; | |
10591 | bp->flags &= ~BNXT_FLAG_RFS; | |
10592 | if (bnxt_rfs_supported(bp)) { | |
10593 | dev->hw_features |= NETIF_F_NTUPLE; | |
10594 | if (bnxt_rfs_capable(bp)) { | |
10595 | bp->flags |= BNXT_FLAG_RFS; | |
10596 | dev->features |= NETIF_F_NTUPLE; | |
10597 | } | |
10598 | } | |
10599 | } | |
10600 | ||
10601 | static void bnxt_fw_init_one_p3(struct bnxt *bp) | |
10602 | { | |
10603 | struct pci_dev *pdev = bp->pdev; | |
10604 | ||
10605 | bnxt_set_dflt_rss_hash_type(bp); | |
10606 | bnxt_set_dflt_rfs(bp); | |
10607 | ||
10608 | bnxt_get_wol_settings(bp); | |
10609 | if (bp->flags & BNXT_FLAG_WOL_CAP) | |
10610 | device_set_wakeup_enable(&pdev->dev, bp->wol); | |
10611 | else | |
10612 | device_set_wakeup_capable(&pdev->dev, false); | |
10613 | ||
10614 | bnxt_hwrm_set_cache_line_size(bp, cache_line_size()); | |
10615 | bnxt_hwrm_coal_params_qcaps(bp); | |
10616 | } | |
10617 | ||
ec5d31e3 MC |
10618 | static int bnxt_fw_init_one(struct bnxt *bp) |
10619 | { | |
10620 | int rc; | |
10621 | ||
10622 | rc = bnxt_fw_init_one_p1(bp); | |
10623 | if (rc) { | |
10624 | netdev_err(bp->dev, "Firmware init phase 1 failed\n"); | |
10625 | return rc; | |
10626 | } | |
10627 | rc = bnxt_fw_init_one_p2(bp); | |
10628 | if (rc) { | |
10629 | netdev_err(bp->dev, "Firmware init phase 2 failed\n"); | |
10630 | return rc; | |
10631 | } | |
10632 | rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false); | |
10633 | if (rc) | |
10634 | return rc; | |
937f188c VV |
10635 | |
10636 | /* In case fw capabilities have changed, destroy the unneeded | |
10637 | * reporters and create newly capable ones. | |
10638 | */ | |
10639 | bnxt_dl_fw_reporters_destroy(bp, false); | |
10640 | bnxt_dl_fw_reporters_create(bp); | |
ec5d31e3 MC |
10641 | bnxt_fw_init_one_p3(bp); |
10642 | return 0; | |
10643 | } | |
10644 | ||
cbb51067 MC |
10645 | static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx) |
10646 | { | |
10647 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
10648 | u32 reg = fw_health->fw_reset_seq_regs[reg_idx]; | |
10649 | u32 val = fw_health->fw_reset_seq_vals[reg_idx]; | |
10650 | u32 reg_type, reg_off, delay_msecs; | |
10651 | ||
10652 | delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx]; | |
10653 | reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); | |
10654 | reg_off = BNXT_FW_HEALTH_REG_OFF(reg); | |
10655 | switch (reg_type) { | |
10656 | case BNXT_FW_HEALTH_REG_TYPE_CFG: | |
10657 | pci_write_config_dword(bp->pdev, reg_off, val); | |
10658 | break; | |
10659 | case BNXT_FW_HEALTH_REG_TYPE_GRC: | |
10660 | writel(reg_off & BNXT_GRC_BASE_MASK, | |
10661 | bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); | |
10662 | reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000; | |
10663 | /* fall through */ | |
10664 | case BNXT_FW_HEALTH_REG_TYPE_BAR0: | |
10665 | writel(val, bp->bar0 + reg_off); | |
10666 | break; | |
10667 | case BNXT_FW_HEALTH_REG_TYPE_BAR1: | |
10668 | writel(val, bp->bar1 + reg_off); | |
10669 | break; | |
10670 | } | |
10671 | if (delay_msecs) { | |
10672 | pci_read_config_dword(bp->pdev, 0, &val); | |
10673 | msleep(delay_msecs); | |
10674 | } | |
10675 | } | |
10676 | ||
10677 | static void bnxt_reset_all(struct bnxt *bp) | |
10678 | { | |
10679 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
e07ab202 VV |
10680 | int i, rc; |
10681 | ||
10682 | if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { | |
10683 | #ifdef CONFIG_TEE_BNXT_FW | |
10684 | rc = tee_bnxt_fw_load(); | |
10685 | if (rc) | |
10686 | netdev_err(bp->dev, "Unable to reset FW rc=%d\n", rc); | |
10687 | bp->fw_reset_timestamp = jiffies; | |
10688 | #endif | |
10689 | return; | |
10690 | } | |
cbb51067 MC |
10691 | |
10692 | if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) { | |
10693 | for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) | |
10694 | bnxt_fw_reset_writel(bp, i); | |
10695 | } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) { | |
10696 | struct hwrm_fw_reset_input req = {0}; | |
cbb51067 MC |
10697 | |
10698 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1); | |
10699 | req.resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); | |
10700 | req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP; | |
10701 | req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP; | |
10702 | req.flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; | |
10703 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
10704 | if (rc) | |
10705 | netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc); | |
10706 | } | |
10707 | bp->fw_reset_timestamp = jiffies; | |
10708 | } | |
10709 | ||
230d1f0d MC |
10710 | static void bnxt_fw_reset_task(struct work_struct *work) |
10711 | { | |
10712 | struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work); | |
10713 | int rc; | |
10714 | ||
10715 | if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { | |
10716 | netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n"); | |
10717 | return; | |
10718 | } | |
10719 | ||
10720 | switch (bp->fw_reset_state) { | |
e72cb7d6 MC |
10721 | case BNXT_FW_RESET_STATE_POLL_VF: { |
10722 | int n = bnxt_get_registered_vfs(bp); | |
4037eb71 | 10723 | int tmo; |
e72cb7d6 MC |
10724 | |
10725 | if (n < 0) { | |
230d1f0d | 10726 | netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n", |
e72cb7d6 | 10727 | n, jiffies_to_msecs(jiffies - |
230d1f0d MC |
10728 | bp->fw_reset_timestamp)); |
10729 | goto fw_reset_abort; | |
e72cb7d6 | 10730 | } else if (n > 0) { |
230d1f0d MC |
10731 | if (time_after(jiffies, bp->fw_reset_timestamp + |
10732 | (bp->fw_reset_max_dsecs * HZ / 10))) { | |
10733 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
10734 | bp->fw_reset_state = 0; | |
e72cb7d6 MC |
10735 | netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n", |
10736 | n); | |
230d1f0d MC |
10737 | return; |
10738 | } | |
10739 | bnxt_queue_fw_reset_work(bp, HZ / 10); | |
10740 | return; | |
10741 | } | |
10742 | bp->fw_reset_timestamp = jiffies; | |
10743 | rtnl_lock(); | |
10744 | bnxt_fw_reset_close(bp); | |
4037eb71 VV |
10745 | if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { |
10746 | bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; | |
10747 | tmo = HZ / 10; | |
10748 | } else { | |
10749 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
10750 | tmo = bp->fw_reset_min_dsecs * HZ / 10; | |
10751 | } | |
230d1f0d | 10752 | rtnl_unlock(); |
4037eb71 | 10753 | bnxt_queue_fw_reset_work(bp, tmo); |
230d1f0d | 10754 | return; |
e72cb7d6 | 10755 | } |
4037eb71 VV |
10756 | case BNXT_FW_RESET_STATE_POLL_FW_DOWN: { |
10757 | u32 val; | |
10758 | ||
10759 | val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); | |
10760 | if (!(val & BNXT_FW_STATUS_SHUTDOWN) && | |
10761 | !time_after(jiffies, bp->fw_reset_timestamp + | |
10762 | (bp->fw_reset_max_dsecs * HZ / 10))) { | |
10763 | bnxt_queue_fw_reset_work(bp, HZ / 5); | |
10764 | return; | |
10765 | } | |
10766 | ||
10767 | if (!bp->fw_health->master) { | |
10768 | u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs; | |
10769 | ||
10770 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
10771 | bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); | |
10772 | return; | |
10773 | } | |
10774 | bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; | |
10775 | } | |
10776 | /* fall through */ | |
c6a9e7aa | 10777 | case BNXT_FW_RESET_STATE_RESET_FW: |
cbb51067 MC |
10778 | bnxt_reset_all(bp); |
10779 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
c6a9e7aa | 10780 | bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10); |
cbb51067 | 10781 | return; |
230d1f0d | 10782 | case BNXT_FW_RESET_STATE_ENABLE_DEV: |
0797c10d | 10783 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) { |
d1db9e16 MC |
10784 | u32 val; |
10785 | ||
10786 | val = bnxt_fw_health_readl(bp, | |
10787 | BNXT_FW_RESET_INPROG_REG); | |
10788 | if (val) | |
10789 | netdev_warn(bp->dev, "FW reset inprog %x after min wait time.\n", | |
10790 | val); | |
10791 | } | |
b4fff207 | 10792 | clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); |
230d1f0d MC |
10793 | if (pci_enable_device(bp->pdev)) { |
10794 | netdev_err(bp->dev, "Cannot re-enable PCI device\n"); | |
10795 | goto fw_reset_abort; | |
10796 | } | |
10797 | pci_set_master(bp->pdev); | |
10798 | bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW; | |
10799 | /* fall through */ | |
10800 | case BNXT_FW_RESET_STATE_POLL_FW: | |
10801 | bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT; | |
10802 | rc = __bnxt_hwrm_ver_get(bp, true); | |
10803 | if (rc) { | |
10804 | if (time_after(jiffies, bp->fw_reset_timestamp + | |
10805 | (bp->fw_reset_max_dsecs * HZ / 10))) { | |
10806 | netdev_err(bp->dev, "Firmware reset aborted\n"); | |
10807 | goto fw_reset_abort; | |
10808 | } | |
10809 | bnxt_queue_fw_reset_work(bp, HZ / 5); | |
10810 | return; | |
10811 | } | |
10812 | bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; | |
10813 | bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING; | |
10814 | /* fall through */ | |
10815 | case BNXT_FW_RESET_STATE_OPENING: | |
10816 | while (!rtnl_trylock()) { | |
10817 | bnxt_queue_fw_reset_work(bp, HZ / 10); | |
10818 | return; | |
10819 | } | |
10820 | rc = bnxt_open(bp->dev); | |
10821 | if (rc) { | |
10822 | netdev_err(bp->dev, "bnxt_open_nic() failed\n"); | |
10823 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
10824 | dev_close(bp->dev); | |
10825 | } | |
230d1f0d MC |
10826 | |
10827 | bp->fw_reset_state = 0; | |
10828 | /* Make sure fw_reset_state is 0 before clearing the flag */ | |
10829 | smp_mb__before_atomic(); | |
10830 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
f3a6d206 | 10831 | bnxt_ulp_start(bp, rc); |
737d7a6c | 10832 | bnxt_dl_health_recovery_done(bp); |
e4e38237 | 10833 | bnxt_dl_health_status_update(bp, true); |
f3a6d206 | 10834 | rtnl_unlock(); |
230d1f0d MC |
10835 | break; |
10836 | } | |
10837 | return; | |
10838 | ||
10839 | fw_reset_abort: | |
10840 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
e4e38237 VV |
10841 | if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF) |
10842 | bnxt_dl_health_status_update(bp, false); | |
230d1f0d MC |
10843 | bp->fw_reset_state = 0; |
10844 | rtnl_lock(); | |
10845 | dev_close(bp->dev); | |
10846 | rtnl_unlock(); | |
10847 | } | |
10848 | ||
c0c050c5 MC |
10849 | static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) |
10850 | { | |
10851 | int rc; | |
10852 | struct bnxt *bp = netdev_priv(dev); | |
10853 | ||
10854 | SET_NETDEV_DEV(dev, &pdev->dev); | |
10855 | ||
10856 | /* enable device (incl. PCI PM wakeup), and bus-mastering */ | |
10857 | rc = pci_enable_device(pdev); | |
10858 | if (rc) { | |
10859 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); | |
10860 | goto init_err; | |
10861 | } | |
10862 | ||
10863 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
10864 | dev_err(&pdev->dev, | |
10865 | "Cannot find PCI device base address, aborting\n"); | |
10866 | rc = -ENODEV; | |
10867 | goto init_err_disable; | |
10868 | } | |
10869 | ||
10870 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
10871 | if (rc) { | |
10872 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); | |
10873 | goto init_err_disable; | |
10874 | } | |
10875 | ||
10876 | if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && | |
10877 | dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { | |
10878 | dev_err(&pdev->dev, "System does not support DMA, aborting\n"); | |
10879 | goto init_err_disable; | |
10880 | } | |
10881 | ||
10882 | pci_set_master(pdev); | |
10883 | ||
10884 | bp->dev = dev; | |
10885 | bp->pdev = pdev; | |
10886 | ||
10887 | bp->bar0 = pci_ioremap_bar(pdev, 0); | |
10888 | if (!bp->bar0) { | |
10889 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); | |
10890 | rc = -ENOMEM; | |
10891 | goto init_err_release; | |
10892 | } | |
10893 | ||
10894 | bp->bar1 = pci_ioremap_bar(pdev, 2); | |
10895 | if (!bp->bar1) { | |
10896 | dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n"); | |
10897 | rc = -ENOMEM; | |
10898 | goto init_err_release; | |
10899 | } | |
10900 | ||
10901 | bp->bar2 = pci_ioremap_bar(pdev, 4); | |
10902 | if (!bp->bar2) { | |
10903 | dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); | |
10904 | rc = -ENOMEM; | |
10905 | goto init_err_release; | |
10906 | } | |
10907 | ||
6316ea6d SB |
10908 | pci_enable_pcie_error_reporting(pdev); |
10909 | ||
c0c050c5 | 10910 | INIT_WORK(&bp->sp_task, bnxt_sp_task); |
230d1f0d | 10911 | INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task); |
c0c050c5 MC |
10912 | |
10913 | spin_lock_init(&bp->ntp_fltr_lock); | |
697197e5 MC |
10914 | #if BITS_PER_LONG == 32 |
10915 | spin_lock_init(&bp->db_lock); | |
10916 | #endif | |
c0c050c5 MC |
10917 | |
10918 | bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; | |
10919 | bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; | |
10920 | ||
18775aa8 | 10921 | bnxt_init_dflt_coal(bp); |
51f30785 | 10922 | |
e99e88a9 | 10923 | timer_setup(&bp->timer, bnxt_timer, 0); |
c0c050c5 MC |
10924 | bp->current_interval = BNXT_TIMER_INTERVAL; |
10925 | ||
caefe526 | 10926 | clear_bit(BNXT_STATE_OPEN, &bp->state); |
c0c050c5 MC |
10927 | return 0; |
10928 | ||
10929 | init_err_release: | |
17086399 | 10930 | bnxt_unmap_bars(bp, pdev); |
c0c050c5 MC |
10931 | pci_release_regions(pdev); |
10932 | ||
10933 | init_err_disable: | |
10934 | pci_disable_device(pdev); | |
10935 | ||
10936 | init_err: | |
10937 | return rc; | |
10938 | } | |
10939 | ||
10940 | /* rtnl_lock held */ | |
10941 | static int bnxt_change_mac_addr(struct net_device *dev, void *p) | |
10942 | { | |
10943 | struct sockaddr *addr = p; | |
1fc2cfd0 JH |
10944 | struct bnxt *bp = netdev_priv(dev); |
10945 | int rc = 0; | |
c0c050c5 MC |
10946 | |
10947 | if (!is_valid_ether_addr(addr->sa_data)) | |
10948 | return -EADDRNOTAVAIL; | |
10949 | ||
c1a7bdff MC |
10950 | if (ether_addr_equal(addr->sa_data, dev->dev_addr)) |
10951 | return 0; | |
10952 | ||
28ea334b | 10953 | rc = bnxt_approve_mac(bp, addr->sa_data, true); |
84c33dd3 MC |
10954 | if (rc) |
10955 | return rc; | |
bdd4347b | 10956 | |
c0c050c5 | 10957 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
1fc2cfd0 JH |
10958 | if (netif_running(dev)) { |
10959 | bnxt_close_nic(bp, false, false); | |
10960 | rc = bnxt_open_nic(bp, false, false); | |
10961 | } | |
c0c050c5 | 10962 | |
1fc2cfd0 | 10963 | return rc; |
c0c050c5 MC |
10964 | } |
10965 | ||
10966 | /* rtnl_lock held */ | |
10967 | static int bnxt_change_mtu(struct net_device *dev, int new_mtu) | |
10968 | { | |
10969 | struct bnxt *bp = netdev_priv(dev); | |
10970 | ||
c0c050c5 MC |
10971 | if (netif_running(dev)) |
10972 | bnxt_close_nic(bp, false, false); | |
10973 | ||
10974 | dev->mtu = new_mtu; | |
10975 | bnxt_set_ring_params(bp); | |
10976 | ||
10977 | if (netif_running(dev)) | |
10978 | return bnxt_open_nic(bp, false, false); | |
10979 | ||
10980 | return 0; | |
10981 | } | |
10982 | ||
c5e3deb8 | 10983 | int bnxt_setup_mq_tc(struct net_device *dev, u8 tc) |
c0c050c5 MC |
10984 | { |
10985 | struct bnxt *bp = netdev_priv(dev); | |
3ffb6a39 | 10986 | bool sh = false; |
d1e7925e | 10987 | int rc; |
16e5cc64 | 10988 | |
c0c050c5 | 10989 | if (tc > bp->max_tc) { |
b451c8b6 | 10990 | netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n", |
c0c050c5 MC |
10991 | tc, bp->max_tc); |
10992 | return -EINVAL; | |
10993 | } | |
10994 | ||
10995 | if (netdev_get_num_tc(dev) == tc) | |
10996 | return 0; | |
10997 | ||
3ffb6a39 MC |
10998 | if (bp->flags & BNXT_FLAG_SHARED_RINGS) |
10999 | sh = true; | |
11000 | ||
98fdbe73 MC |
11001 | rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings, |
11002 | sh, tc, bp->tx_nr_rings_xdp); | |
d1e7925e MC |
11003 | if (rc) |
11004 | return rc; | |
c0c050c5 MC |
11005 | |
11006 | /* Needs to close the device and do hw resource re-allocations */ | |
11007 | if (netif_running(bp->dev)) | |
11008 | bnxt_close_nic(bp, true, false); | |
11009 | ||
11010 | if (tc) { | |
11011 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; | |
11012 | netdev_set_num_tc(dev, tc); | |
11013 | } else { | |
11014 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc; | |
11015 | netdev_reset_tc(dev); | |
11016 | } | |
87e9b377 | 11017 | bp->tx_nr_rings += bp->tx_nr_rings_xdp; |
3ffb6a39 MC |
11018 | bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : |
11019 | bp->tx_nr_rings + bp->rx_nr_rings; | |
c0c050c5 MC |
11020 | |
11021 | if (netif_running(bp->dev)) | |
11022 | return bnxt_open_nic(bp, true, false); | |
11023 | ||
11024 | return 0; | |
11025 | } | |
11026 | ||
9e0fd15d JP |
11027 | static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data, |
11028 | void *cb_priv) | |
c5e3deb8 | 11029 | { |
9e0fd15d | 11030 | struct bnxt *bp = cb_priv; |
de4784ca | 11031 | |
312324f1 JK |
11032 | if (!bnxt_tc_flower_enabled(bp) || |
11033 | !tc_cls_can_offload_and_chain0(bp->dev, type_data)) | |
38cf0426 | 11034 | return -EOPNOTSUPP; |
c5e3deb8 | 11035 | |
9e0fd15d JP |
11036 | switch (type) { |
11037 | case TC_SETUP_CLSFLOWER: | |
11038 | return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data); | |
11039 | default: | |
11040 | return -EOPNOTSUPP; | |
11041 | } | |
11042 | } | |
11043 | ||
627c89d0 | 11044 | LIST_HEAD(bnxt_block_cb_list); |
955bcb6e | 11045 | |
2ae7408f SP |
11046 | static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type, |
11047 | void *type_data) | |
11048 | { | |
4e95bc26 PNA |
11049 | struct bnxt *bp = netdev_priv(dev); |
11050 | ||
2ae7408f | 11051 | switch (type) { |
9e0fd15d | 11052 | case TC_SETUP_BLOCK: |
955bcb6e PNA |
11053 | return flow_block_cb_setup_simple(type_data, |
11054 | &bnxt_block_cb_list, | |
4e95bc26 PNA |
11055 | bnxt_setup_tc_block_cb, |
11056 | bp, bp, true); | |
575ed7d3 | 11057 | case TC_SETUP_QDISC_MQPRIO: { |
2ae7408f SP |
11058 | struct tc_mqprio_qopt *mqprio = type_data; |
11059 | ||
11060 | mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; | |
56f36acd | 11061 | |
2ae7408f SP |
11062 | return bnxt_setup_mq_tc(dev, mqprio->num_tc); |
11063 | } | |
11064 | default: | |
11065 | return -EOPNOTSUPP; | |
11066 | } | |
c5e3deb8 MC |
11067 | } |
11068 | ||
c0c050c5 MC |
11069 | #ifdef CONFIG_RFS_ACCEL |
11070 | static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, | |
11071 | struct bnxt_ntuple_filter *f2) | |
11072 | { | |
11073 | struct flow_keys *keys1 = &f1->fkeys; | |
11074 | struct flow_keys *keys2 = &f2->fkeys; | |
11075 | ||
6fc7caa8 MC |
11076 | if (keys1->basic.n_proto != keys2->basic.n_proto || |
11077 | keys1->basic.ip_proto != keys2->basic.ip_proto) | |
11078 | return false; | |
11079 | ||
11080 | if (keys1->basic.n_proto == htons(ETH_P_IP)) { | |
11081 | if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src || | |
11082 | keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst) | |
11083 | return false; | |
11084 | } else { | |
11085 | if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src, | |
11086 | sizeof(keys1->addrs.v6addrs.src)) || | |
11087 | memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst, | |
11088 | sizeof(keys1->addrs.v6addrs.dst))) | |
11089 | return false; | |
11090 | } | |
11091 | ||
11092 | if (keys1->ports.ports == keys2->ports.ports && | |
61aad724 | 11093 | keys1->control.flags == keys2->control.flags && |
a54c4d74 MC |
11094 | ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) && |
11095 | ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr)) | |
c0c050c5 MC |
11096 | return true; |
11097 | ||
11098 | return false; | |
11099 | } | |
11100 | ||
11101 | static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, | |
11102 | u16 rxq_index, u32 flow_id) | |
11103 | { | |
11104 | struct bnxt *bp = netdev_priv(dev); | |
11105 | struct bnxt_ntuple_filter *fltr, *new_fltr; | |
11106 | struct flow_keys *fkeys; | |
11107 | struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); | |
a54c4d74 | 11108 | int rc = 0, idx, bit_id, l2_idx = 0; |
c0c050c5 | 11109 | struct hlist_head *head; |
f47d0e19 | 11110 | u32 flags; |
c0c050c5 | 11111 | |
a54c4d74 MC |
11112 | if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) { |
11113 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; | |
11114 | int off = 0, j; | |
11115 | ||
11116 | netif_addr_lock_bh(dev); | |
11117 | for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) { | |
11118 | if (ether_addr_equal(eth->h_dest, | |
11119 | vnic->uc_list + off)) { | |
11120 | l2_idx = j + 1; | |
11121 | break; | |
11122 | } | |
11123 | } | |
11124 | netif_addr_unlock_bh(dev); | |
11125 | if (!l2_idx) | |
11126 | return -EINVAL; | |
11127 | } | |
c0c050c5 MC |
11128 | new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); |
11129 | if (!new_fltr) | |
11130 | return -ENOMEM; | |
11131 | ||
11132 | fkeys = &new_fltr->fkeys; | |
11133 | if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { | |
11134 | rc = -EPROTONOSUPPORT; | |
11135 | goto err_free; | |
11136 | } | |
11137 | ||
dda0e746 MC |
11138 | if ((fkeys->basic.n_proto != htons(ETH_P_IP) && |
11139 | fkeys->basic.n_proto != htons(ETH_P_IPV6)) || | |
c0c050c5 MC |
11140 | ((fkeys->basic.ip_proto != IPPROTO_TCP) && |
11141 | (fkeys->basic.ip_proto != IPPROTO_UDP))) { | |
11142 | rc = -EPROTONOSUPPORT; | |
11143 | goto err_free; | |
11144 | } | |
dda0e746 MC |
11145 | if (fkeys->basic.n_proto == htons(ETH_P_IPV6) && |
11146 | bp->hwrm_spec_code < 0x10601) { | |
11147 | rc = -EPROTONOSUPPORT; | |
11148 | goto err_free; | |
11149 | } | |
f47d0e19 MC |
11150 | flags = fkeys->control.flags; |
11151 | if (((flags & FLOW_DIS_ENCAPSULATION) && | |
11152 | bp->hwrm_spec_code < 0x10601) || (flags & FLOW_DIS_IS_FRAGMENT)) { | |
61aad724 MC |
11153 | rc = -EPROTONOSUPPORT; |
11154 | goto err_free; | |
11155 | } | |
c0c050c5 | 11156 | |
a54c4d74 | 11157 | memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN); |
c0c050c5 MC |
11158 | memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); |
11159 | ||
11160 | idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; | |
11161 | head = &bp->ntp_fltr_hash_tbl[idx]; | |
11162 | rcu_read_lock(); | |
11163 | hlist_for_each_entry_rcu(fltr, head, hash) { | |
11164 | if (bnxt_fltr_match(fltr, new_fltr)) { | |
11165 | rcu_read_unlock(); | |
11166 | rc = 0; | |
11167 | goto err_free; | |
11168 | } | |
11169 | } | |
11170 | rcu_read_unlock(); | |
11171 | ||
11172 | spin_lock_bh(&bp->ntp_fltr_lock); | |
84e86b98 MC |
11173 | bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, |
11174 | BNXT_NTP_FLTR_MAX_FLTR, 0); | |
11175 | if (bit_id < 0) { | |
c0c050c5 MC |
11176 | spin_unlock_bh(&bp->ntp_fltr_lock); |
11177 | rc = -ENOMEM; | |
11178 | goto err_free; | |
11179 | } | |
11180 | ||
84e86b98 | 11181 | new_fltr->sw_id = (u16)bit_id; |
c0c050c5 | 11182 | new_fltr->flow_id = flow_id; |
a54c4d74 | 11183 | new_fltr->l2_fltr_idx = l2_idx; |
c0c050c5 MC |
11184 | new_fltr->rxq = rxq_index; |
11185 | hlist_add_head_rcu(&new_fltr->hash, head); | |
11186 | bp->ntp_fltr_count++; | |
11187 | spin_unlock_bh(&bp->ntp_fltr_lock); | |
11188 | ||
11189 | set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); | |
c213eae8 | 11190 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
11191 | |
11192 | return new_fltr->sw_id; | |
11193 | ||
11194 | err_free: | |
11195 | kfree(new_fltr); | |
11196 | return rc; | |
11197 | } | |
11198 | ||
11199 | static void bnxt_cfg_ntp_filters(struct bnxt *bp) | |
11200 | { | |
11201 | int i; | |
11202 | ||
11203 | for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { | |
11204 | struct hlist_head *head; | |
11205 | struct hlist_node *tmp; | |
11206 | struct bnxt_ntuple_filter *fltr; | |
11207 | int rc; | |
11208 | ||
11209 | head = &bp->ntp_fltr_hash_tbl[i]; | |
11210 | hlist_for_each_entry_safe(fltr, tmp, head, hash) { | |
11211 | bool del = false; | |
11212 | ||
11213 | if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { | |
11214 | if (rps_may_expire_flow(bp->dev, fltr->rxq, | |
11215 | fltr->flow_id, | |
11216 | fltr->sw_id)) { | |
11217 | bnxt_hwrm_cfa_ntuple_filter_free(bp, | |
11218 | fltr); | |
11219 | del = true; | |
11220 | } | |
11221 | } else { | |
11222 | rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, | |
11223 | fltr); | |
11224 | if (rc) | |
11225 | del = true; | |
11226 | else | |
11227 | set_bit(BNXT_FLTR_VALID, &fltr->state); | |
11228 | } | |
11229 | ||
11230 | if (del) { | |
11231 | spin_lock_bh(&bp->ntp_fltr_lock); | |
11232 | hlist_del_rcu(&fltr->hash); | |
11233 | bp->ntp_fltr_count--; | |
11234 | spin_unlock_bh(&bp->ntp_fltr_lock); | |
11235 | synchronize_rcu(); | |
11236 | clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); | |
11237 | kfree(fltr); | |
11238 | } | |
11239 | } | |
11240 | } | |
19241368 JH |
11241 | if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event)) |
11242 | netdev_info(bp->dev, "Receive PF driver unload event!"); | |
c0c050c5 MC |
11243 | } |
11244 | ||
11245 | #else | |
11246 | ||
11247 | static void bnxt_cfg_ntp_filters(struct bnxt *bp) | |
11248 | { | |
11249 | } | |
11250 | ||
11251 | #endif /* CONFIG_RFS_ACCEL */ | |
11252 | ||
ad51b8e9 AD |
11253 | static void bnxt_udp_tunnel_add(struct net_device *dev, |
11254 | struct udp_tunnel_info *ti) | |
c0c050c5 MC |
11255 | { |
11256 | struct bnxt *bp = netdev_priv(dev); | |
11257 | ||
ad51b8e9 | 11258 | if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) |
c0c050c5 MC |
11259 | return; |
11260 | ||
ad51b8e9 | 11261 | if (!netif_running(dev)) |
c0c050c5 MC |
11262 | return; |
11263 | ||
ad51b8e9 AD |
11264 | switch (ti->type) { |
11265 | case UDP_TUNNEL_TYPE_VXLAN: | |
11266 | if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port) | |
11267 | return; | |
c0c050c5 | 11268 | |
ad51b8e9 AD |
11269 | bp->vxlan_port_cnt++; |
11270 | if (bp->vxlan_port_cnt == 1) { | |
11271 | bp->vxlan_port = ti->port; | |
11272 | set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event); | |
c213eae8 | 11273 | bnxt_queue_sp_work(bp); |
ad51b8e9 AD |
11274 | } |
11275 | break; | |
7cdd5fc3 AD |
11276 | case UDP_TUNNEL_TYPE_GENEVE: |
11277 | if (bp->nge_port_cnt && bp->nge_port != ti->port) | |
11278 | return; | |
11279 | ||
11280 | bp->nge_port_cnt++; | |
11281 | if (bp->nge_port_cnt == 1) { | |
11282 | bp->nge_port = ti->port; | |
11283 | set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event); | |
11284 | } | |
11285 | break; | |
ad51b8e9 AD |
11286 | default: |
11287 | return; | |
c0c050c5 | 11288 | } |
ad51b8e9 | 11289 | |
c213eae8 | 11290 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
11291 | } |
11292 | ||
ad51b8e9 AD |
11293 | static void bnxt_udp_tunnel_del(struct net_device *dev, |
11294 | struct udp_tunnel_info *ti) | |
c0c050c5 MC |
11295 | { |
11296 | struct bnxt *bp = netdev_priv(dev); | |
11297 | ||
ad51b8e9 | 11298 | if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) |
c0c050c5 MC |
11299 | return; |
11300 | ||
ad51b8e9 | 11301 | if (!netif_running(dev)) |
c0c050c5 MC |
11302 | return; |
11303 | ||
ad51b8e9 AD |
11304 | switch (ti->type) { |
11305 | case UDP_TUNNEL_TYPE_VXLAN: | |
11306 | if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port) | |
11307 | return; | |
c0c050c5 MC |
11308 | bp->vxlan_port_cnt--; |
11309 | ||
ad51b8e9 AD |
11310 | if (bp->vxlan_port_cnt != 0) |
11311 | return; | |
11312 | ||
11313 | set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event); | |
11314 | break; | |
7cdd5fc3 AD |
11315 | case UDP_TUNNEL_TYPE_GENEVE: |
11316 | if (!bp->nge_port_cnt || bp->nge_port != ti->port) | |
11317 | return; | |
11318 | bp->nge_port_cnt--; | |
11319 | ||
11320 | if (bp->nge_port_cnt != 0) | |
11321 | return; | |
11322 | ||
11323 | set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event); | |
11324 | break; | |
ad51b8e9 AD |
11325 | default: |
11326 | return; | |
c0c050c5 | 11327 | } |
ad51b8e9 | 11328 | |
c213eae8 | 11329 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
11330 | } |
11331 | ||
39d8ba2e MC |
11332 | static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, |
11333 | struct net_device *dev, u32 filter_mask, | |
11334 | int nlflags) | |
11335 | { | |
11336 | struct bnxt *bp = netdev_priv(dev); | |
11337 | ||
11338 | return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0, | |
11339 | nlflags, filter_mask, NULL); | |
11340 | } | |
11341 | ||
11342 | static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, | |
2fd527b7 | 11343 | u16 flags, struct netlink_ext_ack *extack) |
39d8ba2e MC |
11344 | { |
11345 | struct bnxt *bp = netdev_priv(dev); | |
11346 | struct nlattr *attr, *br_spec; | |
11347 | int rem, rc = 0; | |
11348 | ||
11349 | if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp)) | |
11350 | return -EOPNOTSUPP; | |
11351 | ||
11352 | br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); | |
11353 | if (!br_spec) | |
11354 | return -EINVAL; | |
11355 | ||
11356 | nla_for_each_nested(attr, br_spec, rem) { | |
11357 | u16 mode; | |
11358 | ||
11359 | if (nla_type(attr) != IFLA_BRIDGE_MODE) | |
11360 | continue; | |
11361 | ||
11362 | if (nla_len(attr) < sizeof(mode)) | |
11363 | return -EINVAL; | |
11364 | ||
11365 | mode = nla_get_u16(attr); | |
11366 | if (mode == bp->br_mode) | |
11367 | break; | |
11368 | ||
11369 | rc = bnxt_hwrm_set_br_mode(bp, mode); | |
11370 | if (!rc) | |
11371 | bp->br_mode = mode; | |
11372 | break; | |
11373 | } | |
11374 | return rc; | |
11375 | } | |
11376 | ||
52d5254a FF |
11377 | int bnxt_get_port_parent_id(struct net_device *dev, |
11378 | struct netdev_phys_item_id *ppid) | |
c124a62f | 11379 | { |
52d5254a FF |
11380 | struct bnxt *bp = netdev_priv(dev); |
11381 | ||
c124a62f SP |
11382 | if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV) |
11383 | return -EOPNOTSUPP; | |
11384 | ||
11385 | /* The PF and it's VF-reps only support the switchdev framework */ | |
d061b241 | 11386 | if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_DSN_VALID)) |
c124a62f SP |
11387 | return -EOPNOTSUPP; |
11388 | ||
52d5254a FF |
11389 | ppid->id_len = sizeof(bp->switch_id); |
11390 | memcpy(ppid->id, bp->switch_id, ppid->id_len); | |
c124a62f | 11391 | |
52d5254a | 11392 | return 0; |
c124a62f SP |
11393 | } |
11394 | ||
c9c49a65 JP |
11395 | static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev) |
11396 | { | |
11397 | struct bnxt *bp = netdev_priv(dev); | |
11398 | ||
11399 | return &bp->dl_port; | |
11400 | } | |
11401 | ||
c0c050c5 MC |
11402 | static const struct net_device_ops bnxt_netdev_ops = { |
11403 | .ndo_open = bnxt_open, | |
11404 | .ndo_start_xmit = bnxt_start_xmit, | |
11405 | .ndo_stop = bnxt_close, | |
11406 | .ndo_get_stats64 = bnxt_get_stats64, | |
11407 | .ndo_set_rx_mode = bnxt_set_rx_mode, | |
11408 | .ndo_do_ioctl = bnxt_ioctl, | |
11409 | .ndo_validate_addr = eth_validate_addr, | |
11410 | .ndo_set_mac_address = bnxt_change_mac_addr, | |
11411 | .ndo_change_mtu = bnxt_change_mtu, | |
11412 | .ndo_fix_features = bnxt_fix_features, | |
11413 | .ndo_set_features = bnxt_set_features, | |
11414 | .ndo_tx_timeout = bnxt_tx_timeout, | |
11415 | #ifdef CONFIG_BNXT_SRIOV | |
11416 | .ndo_get_vf_config = bnxt_get_vf_config, | |
11417 | .ndo_set_vf_mac = bnxt_set_vf_mac, | |
11418 | .ndo_set_vf_vlan = bnxt_set_vf_vlan, | |
11419 | .ndo_set_vf_rate = bnxt_set_vf_bw, | |
11420 | .ndo_set_vf_link_state = bnxt_set_vf_link_state, | |
11421 | .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, | |
746df139 | 11422 | .ndo_set_vf_trust = bnxt_set_vf_trust, |
c0c050c5 MC |
11423 | #endif |
11424 | .ndo_setup_tc = bnxt_setup_tc, | |
11425 | #ifdef CONFIG_RFS_ACCEL | |
11426 | .ndo_rx_flow_steer = bnxt_rx_flow_steer, | |
11427 | #endif | |
ad51b8e9 AD |
11428 | .ndo_udp_tunnel_add = bnxt_udp_tunnel_add, |
11429 | .ndo_udp_tunnel_del = bnxt_udp_tunnel_del, | |
f4e63525 | 11430 | .ndo_bpf = bnxt_xdp, |
f18c2b77 | 11431 | .ndo_xdp_xmit = bnxt_xdp_xmit, |
39d8ba2e MC |
11432 | .ndo_bridge_getlink = bnxt_bridge_getlink, |
11433 | .ndo_bridge_setlink = bnxt_bridge_setlink, | |
c9c49a65 | 11434 | .ndo_get_devlink_port = bnxt_get_devlink_port, |
c0c050c5 MC |
11435 | }; |
11436 | ||
11437 | static void bnxt_remove_one(struct pci_dev *pdev) | |
11438 | { | |
11439 | struct net_device *dev = pci_get_drvdata(pdev); | |
11440 | struct bnxt *bp = netdev_priv(dev); | |
11441 | ||
7e334fc8 | 11442 | if (BNXT_PF(bp)) |
c0c050c5 MC |
11443 | bnxt_sriov_disable(bp); |
11444 | ||
7e334fc8 VV |
11445 | bnxt_dl_fw_reporters_destroy(bp, true); |
11446 | bnxt_dl_unregister(bp); | |
6316ea6d | 11447 | pci_disable_pcie_error_reporting(pdev); |
c0c050c5 | 11448 | unregister_netdev(dev); |
2ae7408f | 11449 | bnxt_shutdown_tc(bp); |
c213eae8 | 11450 | bnxt_cancel_sp_work(bp); |
c0c050c5 MC |
11451 | bp->sp_event = 0; |
11452 | ||
7809592d | 11453 | bnxt_clear_int_mode(bp); |
be58a0da | 11454 | bnxt_hwrm_func_drv_unrgtr(bp); |
c0c050c5 | 11455 | bnxt_free_hwrm_resources(bp); |
e605db80 | 11456 | bnxt_free_hwrm_short_cmd_req(bp); |
eb513658 | 11457 | bnxt_ethtool_free(bp); |
7df4ae9f | 11458 | bnxt_dcb_free(bp); |
a588e458 MC |
11459 | kfree(bp->edev); |
11460 | bp->edev = NULL; | |
8280b38e VV |
11461 | kfree(bp->fw_health); |
11462 | bp->fw_health = NULL; | |
c20dc142 | 11463 | bnxt_cleanup_pci(bp); |
98f04cf0 MC |
11464 | bnxt_free_ctx_mem(bp); |
11465 | kfree(bp->ctx); | |
11466 | bp->ctx = NULL; | |
fd3ab1c7 | 11467 | bnxt_free_port_stats(bp); |
c0c050c5 | 11468 | free_netdev(dev); |
c0c050c5 MC |
11469 | } |
11470 | ||
ba642ab7 | 11471 | static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt) |
c0c050c5 MC |
11472 | { |
11473 | int rc = 0; | |
11474 | struct bnxt_link_info *link_info = &bp->link_info; | |
c0c050c5 | 11475 | |
170ce013 MC |
11476 | rc = bnxt_hwrm_phy_qcaps(bp); |
11477 | if (rc) { | |
11478 | netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n", | |
11479 | rc); | |
11480 | return rc; | |
11481 | } | |
43a5107d MC |
11482 | if (!fw_dflt) |
11483 | return 0; | |
11484 | ||
c0c050c5 MC |
11485 | rc = bnxt_update_link(bp, false); |
11486 | if (rc) { | |
11487 | netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", | |
11488 | rc); | |
11489 | return rc; | |
11490 | } | |
11491 | ||
93ed8117 MC |
11492 | /* Older firmware does not have supported_auto_speeds, so assume |
11493 | * that all supported speeds can be autonegotiated. | |
11494 | */ | |
11495 | if (link_info->auto_link_speeds && !link_info->support_auto_speeds) | |
11496 | link_info->support_auto_speeds = link_info->support_speeds; | |
11497 | ||
8119e49b | 11498 | bnxt_init_ethtool_link_settings(bp); |
ba642ab7 | 11499 | return 0; |
c0c050c5 MC |
11500 | } |
11501 | ||
11502 | static int bnxt_get_max_irq(struct pci_dev *pdev) | |
11503 | { | |
11504 | u16 ctrl; | |
11505 | ||
11506 | if (!pdev->msix_cap) | |
11507 | return 1; | |
11508 | ||
11509 | pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); | |
11510 | return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; | |
11511 | } | |
11512 | ||
6e6c5a57 MC |
11513 | static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, |
11514 | int *max_cp) | |
c0c050c5 | 11515 | { |
6a4f2947 | 11516 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; |
e30fbc33 | 11517 | int max_ring_grps = 0, max_irq; |
c0c050c5 | 11518 | |
6a4f2947 MC |
11519 | *max_tx = hw_resc->max_tx_rings; |
11520 | *max_rx = hw_resc->max_rx_rings; | |
e30fbc33 MC |
11521 | *max_cp = bnxt_get_max_func_cp_rings_for_en(bp); |
11522 | max_irq = min_t(int, bnxt_get_max_func_irqs(bp) - | |
11523 | bnxt_get_ulp_msix_num(bp), | |
c027c6b4 | 11524 | hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp)); |
e30fbc33 MC |
11525 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) |
11526 | *max_cp = min_t(int, *max_cp, max_irq); | |
6a4f2947 | 11527 | max_ring_grps = hw_resc->max_hw_ring_grps; |
76595193 PS |
11528 | if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) { |
11529 | *max_cp -= 1; | |
11530 | *max_rx -= 2; | |
11531 | } | |
c0c050c5 MC |
11532 | if (bp->flags & BNXT_FLAG_AGG_RINGS) |
11533 | *max_rx >>= 1; | |
e30fbc33 MC |
11534 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
11535 | bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false); | |
11536 | /* On P5 chips, max_cp output param should be available NQs */ | |
11537 | *max_cp = max_irq; | |
11538 | } | |
b72d4a68 | 11539 | *max_rx = min_t(int, *max_rx, max_ring_grps); |
6e6c5a57 MC |
11540 | } |
11541 | ||
11542 | int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) | |
11543 | { | |
11544 | int rx, tx, cp; | |
11545 | ||
11546 | _bnxt_get_max_rings(bp, &rx, &tx, &cp); | |
78f058a4 MC |
11547 | *max_rx = rx; |
11548 | *max_tx = tx; | |
6e6c5a57 MC |
11549 | if (!rx || !tx || !cp) |
11550 | return -ENOMEM; | |
11551 | ||
6e6c5a57 MC |
11552 | return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); |
11553 | } | |
11554 | ||
e4060d30 MC |
11555 | static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx, |
11556 | bool shared) | |
11557 | { | |
11558 | int rc; | |
11559 | ||
11560 | rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); | |
bdbd1eb5 MC |
11561 | if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) { |
11562 | /* Not enough rings, try disabling agg rings. */ | |
11563 | bp->flags &= ~BNXT_FLAG_AGG_RINGS; | |
11564 | rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); | |
07f4fde5 MC |
11565 | if (rc) { |
11566 | /* set BNXT_FLAG_AGG_RINGS back for consistency */ | |
11567 | bp->flags |= BNXT_FLAG_AGG_RINGS; | |
bdbd1eb5 | 11568 | return rc; |
07f4fde5 | 11569 | } |
bdbd1eb5 | 11570 | bp->flags |= BNXT_FLAG_NO_AGG_RINGS; |
1054aee8 MC |
11571 | bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); |
11572 | bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); | |
bdbd1eb5 MC |
11573 | bnxt_set_ring_params(bp); |
11574 | } | |
e4060d30 MC |
11575 | |
11576 | if (bp->flags & BNXT_FLAG_ROCE_CAP) { | |
11577 | int max_cp, max_stat, max_irq; | |
11578 | ||
11579 | /* Reserve minimum resources for RoCE */ | |
11580 | max_cp = bnxt_get_max_func_cp_rings(bp); | |
11581 | max_stat = bnxt_get_max_func_stat_ctxs(bp); | |
11582 | max_irq = bnxt_get_max_func_irqs(bp); | |
11583 | if (max_cp <= BNXT_MIN_ROCE_CP_RINGS || | |
11584 | max_irq <= BNXT_MIN_ROCE_CP_RINGS || | |
11585 | max_stat <= BNXT_MIN_ROCE_STAT_CTXS) | |
11586 | return 0; | |
11587 | ||
11588 | max_cp -= BNXT_MIN_ROCE_CP_RINGS; | |
11589 | max_irq -= BNXT_MIN_ROCE_CP_RINGS; | |
11590 | max_stat -= BNXT_MIN_ROCE_STAT_CTXS; | |
11591 | max_cp = min_t(int, max_cp, max_irq); | |
11592 | max_cp = min_t(int, max_cp, max_stat); | |
11593 | rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared); | |
11594 | if (rc) | |
11595 | rc = 0; | |
11596 | } | |
11597 | return rc; | |
11598 | } | |
11599 | ||
58ea801a MC |
11600 | /* In initial default shared ring setting, each shared ring must have a |
11601 | * RX/TX ring pair. | |
11602 | */ | |
11603 | static void bnxt_trim_dflt_sh_rings(struct bnxt *bp) | |
11604 | { | |
11605 | bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings); | |
11606 | bp->rx_nr_rings = bp->cp_nr_rings; | |
11607 | bp->tx_nr_rings_per_tc = bp->cp_nr_rings; | |
11608 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc; | |
11609 | } | |
11610 | ||
702c221c | 11611 | static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh) |
6e6c5a57 MC |
11612 | { |
11613 | int dflt_rings, max_rx_rings, max_tx_rings, rc; | |
6e6c5a57 | 11614 | |
2773dfb2 MC |
11615 | if (!bnxt_can_reserve_rings(bp)) |
11616 | return 0; | |
11617 | ||
6e6c5a57 MC |
11618 | if (sh) |
11619 | bp->flags |= BNXT_FLAG_SHARED_RINGS; | |
d629522e | 11620 | dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues(); |
1d3ef13d MC |
11621 | /* Reduce default rings on multi-port cards so that total default |
11622 | * rings do not exceed CPU count. | |
11623 | */ | |
11624 | if (bp->port_count > 1) { | |
11625 | int max_rings = | |
11626 | max_t(int, num_online_cpus() / bp->port_count, 1); | |
11627 | ||
11628 | dflt_rings = min_t(int, dflt_rings, max_rings); | |
11629 | } | |
e4060d30 | 11630 | rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh); |
6e6c5a57 MC |
11631 | if (rc) |
11632 | return rc; | |
11633 | bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); | |
11634 | bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); | |
58ea801a MC |
11635 | if (sh) |
11636 | bnxt_trim_dflt_sh_rings(bp); | |
11637 | else | |
11638 | bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings; | |
11639 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc; | |
391be5c2 | 11640 | |
674f50a5 | 11641 | rc = __bnxt_reserve_rings(bp); |
391be5c2 MC |
11642 | if (rc) |
11643 | netdev_warn(bp->dev, "Unable to reserve tx rings\n"); | |
58ea801a MC |
11644 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; |
11645 | if (sh) | |
11646 | bnxt_trim_dflt_sh_rings(bp); | |
391be5c2 | 11647 | |
674f50a5 MC |
11648 | /* Rings may have been trimmed, re-reserve the trimmed rings. */ |
11649 | if (bnxt_need_reserve_rings(bp)) { | |
11650 | rc = __bnxt_reserve_rings(bp); | |
11651 | if (rc) | |
11652 | netdev_warn(bp->dev, "2nd rings reservation failed.\n"); | |
11653 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; | |
11654 | } | |
76595193 PS |
11655 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { |
11656 | bp->rx_nr_rings++; | |
11657 | bp->cp_nr_rings++; | |
11658 | } | |
6e6c5a57 | 11659 | return rc; |
c0c050c5 MC |
11660 | } |
11661 | ||
47558acd MC |
11662 | static int bnxt_init_dflt_ring_mode(struct bnxt *bp) |
11663 | { | |
11664 | int rc; | |
11665 | ||
11666 | if (bp->tx_nr_rings) | |
11667 | return 0; | |
11668 | ||
6b95c3e9 MC |
11669 | bnxt_ulp_irq_stop(bp); |
11670 | bnxt_clear_int_mode(bp); | |
47558acd MC |
11671 | rc = bnxt_set_dflt_rings(bp, true); |
11672 | if (rc) { | |
11673 | netdev_err(bp->dev, "Not enough rings available.\n"); | |
6b95c3e9 | 11674 | goto init_dflt_ring_err; |
47558acd MC |
11675 | } |
11676 | rc = bnxt_init_int_mode(bp); | |
11677 | if (rc) | |
6b95c3e9 MC |
11678 | goto init_dflt_ring_err; |
11679 | ||
47558acd MC |
11680 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; |
11681 | if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) { | |
11682 | bp->flags |= BNXT_FLAG_RFS; | |
11683 | bp->dev->features |= NETIF_F_NTUPLE; | |
11684 | } | |
6b95c3e9 MC |
11685 | init_dflt_ring_err: |
11686 | bnxt_ulp_irq_restart(bp, rc); | |
11687 | return rc; | |
47558acd MC |
11688 | } |
11689 | ||
80fcaf46 | 11690 | int bnxt_restore_pf_fw_resources(struct bnxt *bp) |
7b08f661 | 11691 | { |
80fcaf46 MC |
11692 | int rc; |
11693 | ||
7b08f661 MC |
11694 | ASSERT_RTNL(); |
11695 | bnxt_hwrm_func_qcaps(bp); | |
1a037782 VD |
11696 | |
11697 | if (netif_running(bp->dev)) | |
11698 | __bnxt_close_nic(bp, true, false); | |
11699 | ||
ec86f14e | 11700 | bnxt_ulp_irq_stop(bp); |
80fcaf46 MC |
11701 | bnxt_clear_int_mode(bp); |
11702 | rc = bnxt_init_int_mode(bp); | |
ec86f14e | 11703 | bnxt_ulp_irq_restart(bp, rc); |
1a037782 VD |
11704 | |
11705 | if (netif_running(bp->dev)) { | |
11706 | if (rc) | |
11707 | dev_close(bp->dev); | |
11708 | else | |
11709 | rc = bnxt_open_nic(bp, true, false); | |
11710 | } | |
11711 | ||
80fcaf46 | 11712 | return rc; |
7b08f661 MC |
11713 | } |
11714 | ||
a22a6ac2 MC |
11715 | static int bnxt_init_mac_addr(struct bnxt *bp) |
11716 | { | |
11717 | int rc = 0; | |
11718 | ||
11719 | if (BNXT_PF(bp)) { | |
11720 | memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN); | |
11721 | } else { | |
11722 | #ifdef CONFIG_BNXT_SRIOV | |
11723 | struct bnxt_vf_info *vf = &bp->vf; | |
28ea334b | 11724 | bool strict_approval = true; |
a22a6ac2 MC |
11725 | |
11726 | if (is_valid_ether_addr(vf->mac_addr)) { | |
91cdda40 | 11727 | /* overwrite netdev dev_addr with admin VF MAC */ |
a22a6ac2 | 11728 | memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN); |
28ea334b MC |
11729 | /* Older PF driver or firmware may not approve this |
11730 | * correctly. | |
11731 | */ | |
11732 | strict_approval = false; | |
a22a6ac2 MC |
11733 | } else { |
11734 | eth_hw_addr_random(bp->dev); | |
a22a6ac2 | 11735 | } |
28ea334b | 11736 | rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval); |
a22a6ac2 MC |
11737 | #endif |
11738 | } | |
11739 | return rc; | |
11740 | } | |
11741 | ||
03213a99 JP |
11742 | static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[]) |
11743 | { | |
11744 | struct pci_dev *pdev = bp->pdev; | |
11745 | int pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DSN); | |
11746 | u32 dw; | |
11747 | ||
11748 | if (!pos) { | |
11749 | netdev_info(bp->dev, "Unable do read adapter's DSN"); | |
11750 | return -EOPNOTSUPP; | |
11751 | } | |
11752 | ||
11753 | /* DSN (two dw) is at an offset of 4 from the cap pos */ | |
11754 | pos += 4; | |
11755 | pci_read_config_dword(pdev, pos, &dw); | |
11756 | put_unaligned_le32(dw, &dsn[0]); | |
11757 | pci_read_config_dword(pdev, pos + 4, &dw); | |
11758 | put_unaligned_le32(dw, &dsn[4]); | |
d061b241 | 11759 | bp->flags |= BNXT_FLAG_DSN_VALID; |
03213a99 JP |
11760 | return 0; |
11761 | } | |
11762 | ||
c0c050c5 MC |
11763 | static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
11764 | { | |
11765 | static int version_printed; | |
11766 | struct net_device *dev; | |
11767 | struct bnxt *bp; | |
6e6c5a57 | 11768 | int rc, max_irqs; |
c0c050c5 | 11769 | |
4e00338a | 11770 | if (pci_is_bridge(pdev)) |
fa853dda PS |
11771 | return -ENODEV; |
11772 | ||
c0c050c5 MC |
11773 | if (version_printed++ == 0) |
11774 | pr_info("%s", version); | |
11775 | ||
11776 | max_irqs = bnxt_get_max_irq(pdev); | |
11777 | dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); | |
11778 | if (!dev) | |
11779 | return -ENOMEM; | |
11780 | ||
11781 | bp = netdev_priv(dev); | |
9c1fabdf | 11782 | bnxt_set_max_func_irqs(bp, max_irqs); |
c0c050c5 MC |
11783 | |
11784 | if (bnxt_vf_pciid(ent->driver_data)) | |
11785 | bp->flags |= BNXT_FLAG_VF; | |
11786 | ||
2bcfa6f6 | 11787 | if (pdev->msix_cap) |
c0c050c5 | 11788 | bp->flags |= BNXT_FLAG_MSIX_CAP; |
c0c050c5 MC |
11789 | |
11790 | rc = bnxt_init_board(pdev, dev); | |
11791 | if (rc < 0) | |
11792 | goto init_err_free; | |
11793 | ||
11794 | dev->netdev_ops = &bnxt_netdev_ops; | |
11795 | dev->watchdog_timeo = BNXT_TX_TIMEOUT; | |
11796 | dev->ethtool_ops = &bnxt_ethtool_ops; | |
c0c050c5 MC |
11797 | pci_set_drvdata(pdev, dev); |
11798 | ||
3e8060fa PS |
11799 | rc = bnxt_alloc_hwrm_resources(bp); |
11800 | if (rc) | |
17086399 | 11801 | goto init_err_pci_clean; |
3e8060fa PS |
11802 | |
11803 | mutex_init(&bp->hwrm_cmd_lock); | |
ba642ab7 | 11804 | mutex_init(&bp->link_lock); |
7c380918 MC |
11805 | |
11806 | rc = bnxt_fw_init_one_p1(bp); | |
3e8060fa | 11807 | if (rc) |
17086399 | 11808 | goto init_err_pci_clean; |
3e8060fa | 11809 | |
e38287b7 MC |
11810 | if (BNXT_CHIP_P5(bp)) |
11811 | bp->flags |= BNXT_FLAG_CHIP_P5; | |
11812 | ||
7c380918 | 11813 | rc = bnxt_fw_init_one_p2(bp); |
3c2217a6 MC |
11814 | if (rc) |
11815 | goto init_err_pci_clean; | |
11816 | ||
c0c050c5 MC |
11817 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | |
11818 | NETIF_F_TSO | NETIF_F_TSO6 | | |
11819 | NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | | |
7e13318d | 11820 | NETIF_F_GSO_IPXIP4 | |
152971ee AD |
11821 | NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | |
11822 | NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH | | |
3e8060fa PS |
11823 | NETIF_F_RXCSUM | NETIF_F_GRO; |
11824 | ||
e38287b7 | 11825 | if (BNXT_SUPPORTS_TPA(bp)) |
3e8060fa | 11826 | dev->hw_features |= NETIF_F_LRO; |
c0c050c5 | 11827 | |
c0c050c5 MC |
11828 | dev->hw_enc_features = |
11829 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | | |
11830 | NETIF_F_TSO | NETIF_F_TSO6 | | |
11831 | NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | | |
152971ee | 11832 | NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | |
7e13318d | 11833 | NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL; |
152971ee AD |
11834 | dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM | |
11835 | NETIF_F_GSO_GRE_CSUM; | |
c0c050c5 MC |
11836 | dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; |
11837 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | | |
11838 | NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX; | |
e38287b7 | 11839 | if (BNXT_SUPPORTS_TPA(bp)) |
1054aee8 | 11840 | dev->hw_features |= NETIF_F_GRO_HW; |
c0c050c5 | 11841 | dev->features |= dev->hw_features | NETIF_F_HIGHDMA; |
1054aee8 MC |
11842 | if (dev->features & NETIF_F_GRO_HW) |
11843 | dev->features &= ~NETIF_F_LRO; | |
c0c050c5 MC |
11844 | dev->priv_flags |= IFF_UNICAST_FLT; |
11845 | ||
11846 | #ifdef CONFIG_BNXT_SRIOV | |
11847 | init_waitqueue_head(&bp->sriov_cfg_wait); | |
4ab0c6a8 | 11848 | mutex_init(&bp->sriov_lock); |
c0c050c5 | 11849 | #endif |
e38287b7 MC |
11850 | if (BNXT_SUPPORTS_TPA(bp)) { |
11851 | bp->gro_func = bnxt_gro_func_5730x; | |
67912c36 | 11852 | if (BNXT_CHIP_P4(bp)) |
e38287b7 | 11853 | bp->gro_func = bnxt_gro_func_5731x; |
67912c36 MC |
11854 | else if (BNXT_CHIP_P5(bp)) |
11855 | bp->gro_func = bnxt_gro_func_5750x; | |
e38287b7 MC |
11856 | } |
11857 | if (!BNXT_CHIP_P4_PLUS(bp)) | |
434c975a | 11858 | bp->flags |= BNXT_FLAG_DOUBLE_DB; |
309369c9 | 11859 | |
a588e458 MC |
11860 | bp->ulp_probe = bnxt_ulp_probe; |
11861 | ||
a22a6ac2 MC |
11862 | rc = bnxt_init_mac_addr(bp); |
11863 | if (rc) { | |
11864 | dev_err(&pdev->dev, "Unable to initialize mac address.\n"); | |
11865 | rc = -EADDRNOTAVAIL; | |
11866 | goto init_err_pci_clean; | |
11867 | } | |
c0c050c5 | 11868 | |
2e9217d1 VV |
11869 | if (BNXT_PF(bp)) { |
11870 | /* Read the adapter's DSN to use as the eswitch switch_id */ | |
d061b241 | 11871 | bnxt_pcie_dsn_get(bp, bp->switch_id); |
2e9217d1 | 11872 | } |
567b2abe | 11873 | |
7eb9bb3a MC |
11874 | /* MTU range: 60 - FW defined max */ |
11875 | dev->min_mtu = ETH_ZLEN; | |
11876 | dev->max_mtu = bp->max_mtu; | |
11877 | ||
ba642ab7 | 11878 | rc = bnxt_probe_phy(bp, true); |
d5430d31 MC |
11879 | if (rc) |
11880 | goto init_err_pci_clean; | |
11881 | ||
c61fb99c | 11882 | bnxt_set_rx_skb_mode(bp, false); |
c0c050c5 MC |
11883 | bnxt_set_tpa_flags(bp); |
11884 | bnxt_set_ring_params(bp); | |
702c221c | 11885 | rc = bnxt_set_dflt_rings(bp, true); |
bdbd1eb5 MC |
11886 | if (rc) { |
11887 | netdev_err(bp->dev, "Not enough rings available.\n"); | |
11888 | rc = -ENOMEM; | |
17086399 | 11889 | goto init_err_pci_clean; |
bdbd1eb5 | 11890 | } |
c0c050c5 | 11891 | |
ba642ab7 | 11892 | bnxt_fw_init_one_p3(bp); |
2bcfa6f6 | 11893 | |
c0c050c5 MC |
11894 | if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX) |
11895 | bp->flags |= BNXT_FLAG_STRIP_VLAN; | |
11896 | ||
7809592d | 11897 | rc = bnxt_init_int_mode(bp); |
c0c050c5 | 11898 | if (rc) |
17086399 | 11899 | goto init_err_pci_clean; |
c0c050c5 | 11900 | |
832aed16 MC |
11901 | /* No TC has been set yet and rings may have been trimmed due to |
11902 | * limited MSIX, so we re-initialize the TX rings per TC. | |
11903 | */ | |
11904 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; | |
11905 | ||
c213eae8 MC |
11906 | if (BNXT_PF(bp)) { |
11907 | if (!bnxt_pf_wq) { | |
11908 | bnxt_pf_wq = | |
11909 | create_singlethread_workqueue("bnxt_pf_wq"); | |
11910 | if (!bnxt_pf_wq) { | |
11911 | dev_err(&pdev->dev, "Unable to create workqueue.\n"); | |
11912 | goto init_err_pci_clean; | |
11913 | } | |
11914 | } | |
2ae7408f | 11915 | bnxt_init_tc(bp); |
c213eae8 | 11916 | } |
2ae7408f | 11917 | |
7809592d MC |
11918 | rc = register_netdev(dev); |
11919 | if (rc) | |
2ae7408f | 11920 | goto init_err_cleanup_tc; |
7809592d | 11921 | |
7e334fc8 VV |
11922 | bnxt_dl_register(bp); |
11923 | bnxt_dl_fw_reporters_create(bp); | |
4ab0c6a8 | 11924 | |
c0c050c5 MC |
11925 | netdev_info(dev, "%s found at mem %lx, node addr %pM\n", |
11926 | board_info[ent->driver_data].name, | |
11927 | (long)pci_resource_start(pdev, 0), dev->dev_addr); | |
af125b75 | 11928 | pcie_print_link_status(pdev); |
90c4f788 | 11929 | |
c0c050c5 MC |
11930 | return 0; |
11931 | ||
2ae7408f SP |
11932 | init_err_cleanup_tc: |
11933 | bnxt_shutdown_tc(bp); | |
7809592d MC |
11934 | bnxt_clear_int_mode(bp); |
11935 | ||
17086399 | 11936 | init_err_pci_clean: |
bdb38602 | 11937 | bnxt_hwrm_func_drv_unrgtr(bp); |
f9099d61 | 11938 | bnxt_free_hwrm_short_cmd_req(bp); |
a2bf74f4 | 11939 | bnxt_free_hwrm_resources(bp); |
98f04cf0 MC |
11940 | bnxt_free_ctx_mem(bp); |
11941 | kfree(bp->ctx); | |
11942 | bp->ctx = NULL; | |
07f83d72 MC |
11943 | kfree(bp->fw_health); |
11944 | bp->fw_health = NULL; | |
17086399 | 11945 | bnxt_cleanup_pci(bp); |
c0c050c5 MC |
11946 | |
11947 | init_err_free: | |
11948 | free_netdev(dev); | |
11949 | return rc; | |
11950 | } | |
11951 | ||
d196ece7 MC |
11952 | static void bnxt_shutdown(struct pci_dev *pdev) |
11953 | { | |
11954 | struct net_device *dev = pci_get_drvdata(pdev); | |
11955 | struct bnxt *bp; | |
11956 | ||
11957 | if (!dev) | |
11958 | return; | |
11959 | ||
11960 | rtnl_lock(); | |
11961 | bp = netdev_priv(dev); | |
11962 | if (!bp) | |
11963 | goto shutdown_exit; | |
11964 | ||
11965 | if (netif_running(dev)) | |
11966 | dev_close(dev); | |
11967 | ||
a7f3f939 RJ |
11968 | bnxt_ulp_shutdown(bp); |
11969 | ||
d196ece7 MC |
11970 | if (system_state == SYSTEM_POWER_OFF) { |
11971 | bnxt_clear_int_mode(bp); | |
c20dc142 | 11972 | pci_disable_device(pdev); |
d196ece7 MC |
11973 | pci_wake_from_d3(pdev, bp->wol); |
11974 | pci_set_power_state(pdev, PCI_D3hot); | |
11975 | } | |
11976 | ||
11977 | shutdown_exit: | |
11978 | rtnl_unlock(); | |
11979 | } | |
11980 | ||
f65a2044 MC |
11981 | #ifdef CONFIG_PM_SLEEP |
11982 | static int bnxt_suspend(struct device *device) | |
11983 | { | |
f521eaa9 | 11984 | struct net_device *dev = dev_get_drvdata(device); |
f65a2044 MC |
11985 | struct bnxt *bp = netdev_priv(dev); |
11986 | int rc = 0; | |
11987 | ||
11988 | rtnl_lock(); | |
6a68749d | 11989 | bnxt_ulp_stop(bp); |
f65a2044 MC |
11990 | if (netif_running(dev)) { |
11991 | netif_device_detach(dev); | |
11992 | rc = bnxt_close(dev); | |
11993 | } | |
11994 | bnxt_hwrm_func_drv_unrgtr(bp); | |
ef02af8c | 11995 | pci_disable_device(bp->pdev); |
f9b69d7f VV |
11996 | bnxt_free_ctx_mem(bp); |
11997 | kfree(bp->ctx); | |
11998 | bp->ctx = NULL; | |
f65a2044 MC |
11999 | rtnl_unlock(); |
12000 | return rc; | |
12001 | } | |
12002 | ||
12003 | static int bnxt_resume(struct device *device) | |
12004 | { | |
f521eaa9 | 12005 | struct net_device *dev = dev_get_drvdata(device); |
f65a2044 MC |
12006 | struct bnxt *bp = netdev_priv(dev); |
12007 | int rc = 0; | |
12008 | ||
12009 | rtnl_lock(); | |
ef02af8c MC |
12010 | rc = pci_enable_device(bp->pdev); |
12011 | if (rc) { | |
12012 | netdev_err(dev, "Cannot re-enable PCI device during resume, err = %d\n", | |
12013 | rc); | |
12014 | goto resume_exit; | |
12015 | } | |
12016 | pci_set_master(bp->pdev); | |
f92335d8 | 12017 | if (bnxt_hwrm_ver_get(bp)) { |
f65a2044 MC |
12018 | rc = -ENODEV; |
12019 | goto resume_exit; | |
12020 | } | |
12021 | rc = bnxt_hwrm_func_reset(bp); | |
12022 | if (rc) { | |
12023 | rc = -EBUSY; | |
12024 | goto resume_exit; | |
12025 | } | |
f92335d8 | 12026 | |
f9b69d7f VV |
12027 | if (bnxt_hwrm_queue_qportcfg(bp)) { |
12028 | rc = -ENODEV; | |
12029 | goto resume_exit; | |
12030 | } | |
12031 | ||
12032 | if (bp->hwrm_spec_code >= 0x10803) { | |
12033 | if (bnxt_alloc_ctx_mem(bp)) { | |
12034 | rc = -ENODEV; | |
12035 | goto resume_exit; | |
12036 | } | |
12037 | } | |
f92335d8 VV |
12038 | if (BNXT_NEW_RM(bp)) |
12039 | bnxt_hwrm_func_resc_qcaps(bp, false); | |
12040 | ||
12041 | if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) { | |
12042 | rc = -ENODEV; | |
12043 | goto resume_exit; | |
12044 | } | |
12045 | ||
f65a2044 MC |
12046 | bnxt_get_wol_settings(bp); |
12047 | if (netif_running(dev)) { | |
12048 | rc = bnxt_open(dev); | |
12049 | if (!rc) | |
12050 | netif_device_attach(dev); | |
12051 | } | |
12052 | ||
12053 | resume_exit: | |
6a68749d | 12054 | bnxt_ulp_start(bp, rc); |
f65a2044 MC |
12055 | rtnl_unlock(); |
12056 | return rc; | |
12057 | } | |
12058 | ||
12059 | static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume); | |
12060 | #define BNXT_PM_OPS (&bnxt_pm_ops) | |
12061 | ||
12062 | #else | |
12063 | ||
12064 | #define BNXT_PM_OPS NULL | |
12065 | ||
12066 | #endif /* CONFIG_PM_SLEEP */ | |
12067 | ||
6316ea6d SB |
12068 | /** |
12069 | * bnxt_io_error_detected - called when PCI error is detected | |
12070 | * @pdev: Pointer to PCI device | |
12071 | * @state: The current pci connection state | |
12072 | * | |
12073 | * This function is called after a PCI bus error affecting | |
12074 | * this device has been detected. | |
12075 | */ | |
12076 | static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev, | |
12077 | pci_channel_state_t state) | |
12078 | { | |
12079 | struct net_device *netdev = pci_get_drvdata(pdev); | |
a588e458 | 12080 | struct bnxt *bp = netdev_priv(netdev); |
6316ea6d SB |
12081 | |
12082 | netdev_info(netdev, "PCI I/O error detected\n"); | |
12083 | ||
12084 | rtnl_lock(); | |
12085 | netif_device_detach(netdev); | |
12086 | ||
a588e458 MC |
12087 | bnxt_ulp_stop(bp); |
12088 | ||
6316ea6d SB |
12089 | if (state == pci_channel_io_perm_failure) { |
12090 | rtnl_unlock(); | |
12091 | return PCI_ERS_RESULT_DISCONNECT; | |
12092 | } | |
12093 | ||
12094 | if (netif_running(netdev)) | |
12095 | bnxt_close(netdev); | |
12096 | ||
12097 | pci_disable_device(pdev); | |
12098 | rtnl_unlock(); | |
12099 | ||
12100 | /* Request a slot slot reset. */ | |
12101 | return PCI_ERS_RESULT_NEED_RESET; | |
12102 | } | |
12103 | ||
12104 | /** | |
12105 | * bnxt_io_slot_reset - called after the pci bus has been reset. | |
12106 | * @pdev: Pointer to PCI device | |
12107 | * | |
12108 | * Restart the card from scratch, as if from a cold-boot. | |
12109 | * At this point, the card has exprienced a hard reset, | |
12110 | * followed by fixups by BIOS, and has its config space | |
12111 | * set up identically to what it was at cold boot. | |
12112 | */ | |
12113 | static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) | |
12114 | { | |
12115 | struct net_device *netdev = pci_get_drvdata(pdev); | |
12116 | struct bnxt *bp = netdev_priv(netdev); | |
12117 | int err = 0; | |
12118 | pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; | |
12119 | ||
12120 | netdev_info(bp->dev, "PCI Slot Reset\n"); | |
12121 | ||
12122 | rtnl_lock(); | |
12123 | ||
12124 | if (pci_enable_device(pdev)) { | |
12125 | dev_err(&pdev->dev, | |
12126 | "Cannot re-enable PCI device after reset.\n"); | |
12127 | } else { | |
12128 | pci_set_master(pdev); | |
12129 | ||
aa8ed021 MC |
12130 | err = bnxt_hwrm_func_reset(bp); |
12131 | if (!err && netif_running(netdev)) | |
6316ea6d SB |
12132 | err = bnxt_open(netdev); |
12133 | ||
aa46dfff | 12134 | if (!err) |
6316ea6d | 12135 | result = PCI_ERS_RESULT_RECOVERED; |
aa46dfff | 12136 | bnxt_ulp_start(bp, err); |
6316ea6d SB |
12137 | } |
12138 | ||
12139 | if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev)) | |
12140 | dev_close(netdev); | |
12141 | ||
12142 | rtnl_unlock(); | |
12143 | ||
6316ea6d SB |
12144 | return PCI_ERS_RESULT_RECOVERED; |
12145 | } | |
12146 | ||
12147 | /** | |
12148 | * bnxt_io_resume - called when traffic can start flowing again. | |
12149 | * @pdev: Pointer to PCI device | |
12150 | * | |
12151 | * This callback is called when the error recovery driver tells | |
12152 | * us that its OK to resume normal operation. | |
12153 | */ | |
12154 | static void bnxt_io_resume(struct pci_dev *pdev) | |
12155 | { | |
12156 | struct net_device *netdev = pci_get_drvdata(pdev); | |
12157 | ||
12158 | rtnl_lock(); | |
12159 | ||
12160 | netif_device_attach(netdev); | |
12161 | ||
12162 | rtnl_unlock(); | |
12163 | } | |
12164 | ||
12165 | static const struct pci_error_handlers bnxt_err_handler = { | |
12166 | .error_detected = bnxt_io_error_detected, | |
12167 | .slot_reset = bnxt_io_slot_reset, | |
12168 | .resume = bnxt_io_resume | |
12169 | }; | |
12170 | ||
c0c050c5 MC |
12171 | static struct pci_driver bnxt_pci_driver = { |
12172 | .name = DRV_MODULE_NAME, | |
12173 | .id_table = bnxt_pci_tbl, | |
12174 | .probe = bnxt_init_one, | |
12175 | .remove = bnxt_remove_one, | |
d196ece7 | 12176 | .shutdown = bnxt_shutdown, |
f65a2044 | 12177 | .driver.pm = BNXT_PM_OPS, |
6316ea6d | 12178 | .err_handler = &bnxt_err_handler, |
c0c050c5 MC |
12179 | #if defined(CONFIG_BNXT_SRIOV) |
12180 | .sriov_configure = bnxt_sriov_configure, | |
12181 | #endif | |
12182 | }; | |
12183 | ||
c213eae8 MC |
12184 | static int __init bnxt_init(void) |
12185 | { | |
cabfb09d | 12186 | bnxt_debug_init(); |
c213eae8 MC |
12187 | return pci_register_driver(&bnxt_pci_driver); |
12188 | } | |
12189 | ||
12190 | static void __exit bnxt_exit(void) | |
12191 | { | |
12192 | pci_unregister_driver(&bnxt_pci_driver); | |
12193 | if (bnxt_pf_wq) | |
12194 | destroy_workqueue(bnxt_pf_wq); | |
cabfb09d | 12195 | bnxt_debug_exit(); |
c213eae8 MC |
12196 | } |
12197 | ||
12198 | module_init(bnxt_init); | |
12199 | module_exit(bnxt_exit); |