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Commit | Line | Data |
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c0c050c5 MC |
1 | /* Broadcom NetXtreme-C/E network driver. |
2 | * | |
11f15ed3 | 3 | * Copyright (c) 2014-2016 Broadcom Corporation |
c6cc32a2 | 4 | * Copyright (c) 2016-2019 Broadcom Limited |
c0c050c5 MC |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | ||
13 | #include <linux/stringify.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/timer.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/ioport.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/vmalloc.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/etherdevice.h> | |
24 | #include <linux/skbuff.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/bitops.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/irq.h> | |
29 | #include <linux/delay.h> | |
30 | #include <asm/byteorder.h> | |
31 | #include <asm/page.h> | |
32 | #include <linux/time.h> | |
33 | #include <linux/mii.h> | |
0ca12be9 | 34 | #include <linux/mdio.h> |
c0c050c5 MC |
35 | #include <linux/if.h> |
36 | #include <linux/if_vlan.h> | |
32e8239c | 37 | #include <linux/if_bridge.h> |
5ac67d8b | 38 | #include <linux/rtc.h> |
c6d30e83 | 39 | #include <linux/bpf.h> |
c0c050c5 MC |
40 | #include <net/ip.h> |
41 | #include <net/tcp.h> | |
42 | #include <net/udp.h> | |
43 | #include <net/checksum.h> | |
44 | #include <net/ip6_checksum.h> | |
ad51b8e9 | 45 | #include <net/udp_tunnel.h> |
c0c050c5 MC |
46 | #include <linux/workqueue.h> |
47 | #include <linux/prefetch.h> | |
48 | #include <linux/cache.h> | |
49 | #include <linux/log2.h> | |
50 | #include <linux/aer.h> | |
51 | #include <linux/bitmap.h> | |
52 | #include <linux/cpu_rmap.h> | |
56f0fd80 | 53 | #include <linux/cpumask.h> |
2ae7408f | 54 | #include <net/pkt_cls.h> |
cde49a42 VV |
55 | #include <linux/hwmon.h> |
56 | #include <linux/hwmon-sysfs.h> | |
322b87ca | 57 | #include <net/page_pool.h> |
c0c050c5 MC |
58 | |
59 | #include "bnxt_hsi.h" | |
60 | #include "bnxt.h" | |
a588e458 | 61 | #include "bnxt_ulp.h" |
c0c050c5 MC |
62 | #include "bnxt_sriov.h" |
63 | #include "bnxt_ethtool.h" | |
7df4ae9f | 64 | #include "bnxt_dcb.h" |
c6d30e83 | 65 | #include "bnxt_xdp.h" |
4ab0c6a8 | 66 | #include "bnxt_vfr.h" |
2ae7408f | 67 | #include "bnxt_tc.h" |
3c467bf3 | 68 | #include "bnxt_devlink.h" |
cabfb09d | 69 | #include "bnxt_debugfs.h" |
c0c050c5 MC |
70 | |
71 | #define BNXT_TX_TIMEOUT (5 * HZ) | |
72 | ||
c0c050c5 MC |
73 | MODULE_LICENSE("GPL"); |
74 | MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); | |
c0c050c5 MC |
75 | |
76 | #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) | |
77 | #define BNXT_RX_DMA_OFFSET NET_SKB_PAD | |
78 | #define BNXT_RX_COPY_THRESH 256 | |
79 | ||
4419dbe6 | 80 | #define BNXT_TX_PUSH_THRESH 164 |
c0c050c5 MC |
81 | |
82 | enum board_idx { | |
fbc9a523 | 83 | BCM57301, |
c0c050c5 MC |
84 | BCM57302, |
85 | BCM57304, | |
1f681688 | 86 | BCM57417_NPAR, |
fa853dda | 87 | BCM58700, |
b24eb6ae MC |
88 | BCM57311, |
89 | BCM57312, | |
fbc9a523 | 90 | BCM57402, |
c0c050c5 MC |
91 | BCM57404, |
92 | BCM57406, | |
1f681688 MC |
93 | BCM57402_NPAR, |
94 | BCM57407, | |
b24eb6ae MC |
95 | BCM57412, |
96 | BCM57414, | |
97 | BCM57416, | |
98 | BCM57417, | |
1f681688 | 99 | BCM57412_NPAR, |
5049e33b | 100 | BCM57314, |
1f681688 MC |
101 | BCM57417_SFP, |
102 | BCM57416_SFP, | |
103 | BCM57404_NPAR, | |
104 | BCM57406_NPAR, | |
105 | BCM57407_SFP, | |
adbc8305 | 106 | BCM57407_NPAR, |
1f681688 MC |
107 | BCM57414_NPAR, |
108 | BCM57416_NPAR, | |
32b40798 DK |
109 | BCM57452, |
110 | BCM57454, | |
92abef36 | 111 | BCM5745x_NPAR, |
1ab968d2 | 112 | BCM57508, |
c6cc32a2 | 113 | BCM57504, |
51fec80d | 114 | BCM57502, |
49c98421 MC |
115 | BCM57508_NPAR, |
116 | BCM57504_NPAR, | |
117 | BCM57502_NPAR, | |
4a58139b | 118 | BCM58802, |
8ed693b7 | 119 | BCM58804, |
4a58139b | 120 | BCM58808, |
adbc8305 MC |
121 | NETXTREME_E_VF, |
122 | NETXTREME_C_VF, | |
618784e3 | 123 | NETXTREME_S_VF, |
b16b6891 | 124 | NETXTREME_E_P5_VF, |
c0c050c5 MC |
125 | }; |
126 | ||
127 | /* indexed by enum above */ | |
128 | static const struct { | |
129 | char *name; | |
130 | } board_info[] = { | |
27573a7d SB |
131 | [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" }, |
132 | [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" }, | |
133 | [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, | |
134 | [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" }, | |
135 | [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" }, | |
136 | [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" }, | |
137 | [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" }, | |
138 | [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" }, | |
139 | [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" }, | |
140 | [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" }, | |
141 | [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" }, | |
142 | [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" }, | |
143 | [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" }, | |
144 | [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" }, | |
145 | [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" }, | |
146 | [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" }, | |
147 | [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" }, | |
148 | [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, | |
149 | [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" }, | |
150 | [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" }, | |
151 | [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" }, | |
152 | [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" }, | |
153 | [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" }, | |
154 | [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" }, | |
155 | [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" }, | |
156 | [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" }, | |
157 | [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" }, | |
158 | [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, | |
92abef36 | 159 | [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" }, |
1ab968d2 | 160 | [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, |
c6cc32a2 | 161 | [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, |
51fec80d | 162 | [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" }, |
49c98421 MC |
163 | [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" }, |
164 | [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" }, | |
165 | [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" }, | |
27573a7d | 166 | [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" }, |
8ed693b7 | 167 | [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, |
27573a7d SB |
168 | [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, |
169 | [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" }, | |
170 | [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" }, | |
618784e3 | 171 | [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" }, |
b16b6891 | 172 | [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" }, |
c0c050c5 MC |
173 | }; |
174 | ||
175 | static const struct pci_device_id bnxt_pci_tbl[] = { | |
92abef36 VV |
176 | { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR }, |
177 | { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR }, | |
4a58139b | 178 | { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 }, |
adbc8305 | 179 | { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR }, |
fbc9a523 | 180 | { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, |
c0c050c5 MC |
181 | { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, |
182 | { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, | |
1f681688 | 183 | { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR }, |
fa853dda | 184 | { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 }, |
b24eb6ae MC |
185 | { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 }, |
186 | { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 }, | |
fbc9a523 | 187 | { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, |
c0c050c5 MC |
188 | { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, |
189 | { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, | |
1f681688 MC |
190 | { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR }, |
191 | { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 }, | |
b24eb6ae MC |
192 | { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 }, |
193 | { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 }, | |
194 | { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 }, | |
195 | { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 }, | |
1f681688 | 196 | { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR }, |
5049e33b | 197 | { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 }, |
1f681688 MC |
198 | { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP }, |
199 | { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP }, | |
200 | { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR }, | |
201 | { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR }, | |
202 | { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP }, | |
adbc8305 MC |
203 | { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR }, |
204 | { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR }, | |
1f681688 | 205 | { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR }, |
adbc8305 | 206 | { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR }, |
1f681688 | 207 | { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR }, |
adbc8305 | 208 | { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR }, |
4a58139b | 209 | { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 }, |
32b40798 | 210 | { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 }, |
1ab968d2 | 211 | { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 }, |
c6cc32a2 | 212 | { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 }, |
51fec80d | 213 | { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 }, |
49c98421 MC |
214 | { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57508_NPAR }, |
215 | { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR }, | |
216 | { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57502_NPAR }, | |
217 | { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57508_NPAR }, | |
218 | { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR }, | |
219 | { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57502_NPAR }, | |
4a58139b | 220 | { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 }, |
8ed693b7 | 221 | { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 }, |
c0c050c5 | 222 | #ifdef CONFIG_BNXT_SRIOV |
c7ef35eb DK |
223 | { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF }, |
224 | { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF }, | |
adbc8305 MC |
225 | { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF }, |
226 | { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF }, | |
227 | { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF }, | |
228 | { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF }, | |
229 | { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF }, | |
230 | { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF }, | |
51fec80d | 231 | { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF }, |
b16b6891 | 232 | { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF }, |
618784e3 | 233 | { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF }, |
c0c050c5 MC |
234 | #endif |
235 | { 0 } | |
236 | }; | |
237 | ||
238 | MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); | |
239 | ||
240 | static const u16 bnxt_vf_req_snif[] = { | |
241 | HWRM_FUNC_CFG, | |
91cdda40 | 242 | HWRM_FUNC_VF_CFG, |
c0c050c5 MC |
243 | HWRM_PORT_PHY_QCFG, |
244 | HWRM_CFA_L2_FILTER_ALLOC, | |
245 | }; | |
246 | ||
25be8623 | 247 | static const u16 bnxt_async_events_arr[] = { |
87c374de | 248 | ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, |
b1613e78 | 249 | ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE, |
87c374de MC |
250 | ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD, |
251 | ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED, | |
252 | ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE, | |
253 | ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, | |
b1613e78 | 254 | ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE, |
2151fe08 | 255 | ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY, |
7e914027 | 256 | ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY, |
25be8623 MC |
257 | }; |
258 | ||
c213eae8 MC |
259 | static struct workqueue_struct *bnxt_pf_wq; |
260 | ||
c0c050c5 MC |
261 | static bool bnxt_vf_pciid(enum board_idx idx) |
262 | { | |
618784e3 | 263 | return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF || |
b16b6891 | 264 | idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF); |
c0c050c5 MC |
265 | } |
266 | ||
267 | #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) | |
268 | #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) | |
269 | #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) | |
270 | ||
c0c050c5 MC |
271 | #define BNXT_CP_DB_IRQ_DIS(db) \ |
272 | writel(DB_CP_IRQ_DIS_FLAGS, db) | |
273 | ||
697197e5 MC |
274 | #define BNXT_DB_CQ(db, idx) \ |
275 | writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell) | |
276 | ||
277 | #define BNXT_DB_NQ_P5(db, idx) \ | |
278 | writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell) | |
279 | ||
280 | #define BNXT_DB_CQ_ARM(db, idx) \ | |
281 | writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell) | |
282 | ||
283 | #define BNXT_DB_NQ_ARM_P5(db, idx) \ | |
284 | writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell) | |
285 | ||
286 | static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) | |
287 | { | |
288 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
289 | BNXT_DB_NQ_P5(db, idx); | |
290 | else | |
291 | BNXT_DB_CQ(db, idx); | |
292 | } | |
293 | ||
294 | static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) | |
295 | { | |
296 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
297 | BNXT_DB_NQ_ARM_P5(db, idx); | |
298 | else | |
299 | BNXT_DB_CQ_ARM(db, idx); | |
300 | } | |
301 | ||
302 | static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) | |
303 | { | |
304 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
305 | writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx), | |
306 | db->doorbell); | |
307 | else | |
308 | BNXT_DB_CQ(db, idx); | |
309 | } | |
310 | ||
38413406 | 311 | const u16 bnxt_lhint_arr[] = { |
c0c050c5 MC |
312 | TX_BD_FLAGS_LHINT_512_AND_SMALLER, |
313 | TX_BD_FLAGS_LHINT_512_TO_1023, | |
314 | TX_BD_FLAGS_LHINT_1024_TO_2047, | |
315 | TX_BD_FLAGS_LHINT_1024_TO_2047, | |
316 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
317 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
318 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
319 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
320 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
321 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
322 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
323 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
324 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
325 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
326 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
327 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
328 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
329 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
330 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
331 | }; | |
332 | ||
ee5c7fb3 SP |
333 | static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb) |
334 | { | |
335 | struct metadata_dst *md_dst = skb_metadata_dst(skb); | |
336 | ||
337 | if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX) | |
338 | return 0; | |
339 | ||
340 | return md_dst->u.port_info.port_id; | |
341 | } | |
342 | ||
c0c050c5 MC |
343 | static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) |
344 | { | |
345 | struct bnxt *bp = netdev_priv(dev); | |
346 | struct tx_bd *txbd; | |
347 | struct tx_bd_ext *txbd1; | |
348 | struct netdev_queue *txq; | |
349 | int i; | |
350 | dma_addr_t mapping; | |
351 | unsigned int length, pad = 0; | |
352 | u32 len, free_size, vlan_tag_flags, cfa_action, flags; | |
353 | u16 prod, last_frag; | |
354 | struct pci_dev *pdev = bp->pdev; | |
c0c050c5 MC |
355 | struct bnxt_tx_ring_info *txr; |
356 | struct bnxt_sw_tx_bd *tx_buf; | |
357 | ||
358 | i = skb_get_queue_mapping(skb); | |
359 | if (unlikely(i >= bp->tx_nr_rings)) { | |
360 | dev_kfree_skb_any(skb); | |
361 | return NETDEV_TX_OK; | |
362 | } | |
363 | ||
c0c050c5 | 364 | txq = netdev_get_tx_queue(dev, i); |
a960dec9 | 365 | txr = &bp->tx_ring[bp->tx_ring_map[i]]; |
c0c050c5 MC |
366 | prod = txr->tx_prod; |
367 | ||
368 | free_size = bnxt_tx_avail(bp, txr); | |
369 | if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { | |
370 | netif_tx_stop_queue(txq); | |
371 | return NETDEV_TX_BUSY; | |
372 | } | |
373 | ||
374 | length = skb->len; | |
375 | len = skb_headlen(skb); | |
376 | last_frag = skb_shinfo(skb)->nr_frags; | |
377 | ||
378 | txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; | |
379 | ||
380 | txbd->tx_bd_opaque = prod; | |
381 | ||
382 | tx_buf = &txr->tx_buf_ring[prod]; | |
383 | tx_buf->skb = skb; | |
384 | tx_buf->nr_frags = last_frag; | |
385 | ||
386 | vlan_tag_flags = 0; | |
ee5c7fb3 | 387 | cfa_action = bnxt_xmit_get_cfa_action(skb); |
c0c050c5 MC |
388 | if (skb_vlan_tag_present(skb)) { |
389 | vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | | |
390 | skb_vlan_tag_get(skb); | |
391 | /* Currently supports 8021Q, 8021AD vlan offloads | |
392 | * QINQ1, QINQ2, QINQ3 vlan headers are deprecated | |
393 | */ | |
394 | if (skb->vlan_proto == htons(ETH_P_8021Q)) | |
395 | vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; | |
396 | } | |
397 | ||
398 | if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) { | |
4419dbe6 MC |
399 | struct tx_push_buffer *tx_push_buf = txr->tx_push; |
400 | struct tx_push_bd *tx_push = &tx_push_buf->push_bd; | |
401 | struct tx_bd_ext *tx_push1 = &tx_push->txbd2; | |
697197e5 | 402 | void __iomem *db = txr->tx_db.doorbell; |
4419dbe6 MC |
403 | void *pdata = tx_push_buf->data; |
404 | u64 *end; | |
405 | int j, push_len; | |
c0c050c5 MC |
406 | |
407 | /* Set COAL_NOW to be ready quickly for the next push */ | |
408 | tx_push->tx_bd_len_flags_type = | |
409 | cpu_to_le32((length << TX_BD_LEN_SHIFT) | | |
410 | TX_BD_TYPE_LONG_TX_BD | | |
411 | TX_BD_FLAGS_LHINT_512_AND_SMALLER | | |
412 | TX_BD_FLAGS_COAL_NOW | | |
413 | TX_BD_FLAGS_PACKET_END | | |
414 | (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); | |
415 | ||
416 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
417 | tx_push1->tx_bd_hsize_lflags = | |
418 | cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); | |
419 | else | |
420 | tx_push1->tx_bd_hsize_lflags = 0; | |
421 | ||
422 | tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); | |
ee5c7fb3 SP |
423 | tx_push1->tx_bd_cfa_action = |
424 | cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); | |
c0c050c5 | 425 | |
fbb0fa8b MC |
426 | end = pdata + length; |
427 | end = PTR_ALIGN(end, 8) - 1; | |
4419dbe6 MC |
428 | *end = 0; |
429 | ||
c0c050c5 MC |
430 | skb_copy_from_linear_data(skb, pdata, len); |
431 | pdata += len; | |
432 | for (j = 0; j < last_frag; j++) { | |
433 | skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; | |
434 | void *fptr; | |
435 | ||
436 | fptr = skb_frag_address_safe(frag); | |
437 | if (!fptr) | |
438 | goto normal_tx; | |
439 | ||
440 | memcpy(pdata, fptr, skb_frag_size(frag)); | |
441 | pdata += skb_frag_size(frag); | |
442 | } | |
443 | ||
4419dbe6 MC |
444 | txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type; |
445 | txbd->tx_bd_haddr = txr->data_mapping; | |
c0c050c5 MC |
446 | prod = NEXT_TX(prod); |
447 | txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; | |
448 | memcpy(txbd, tx_push1, sizeof(*txbd)); | |
449 | prod = NEXT_TX(prod); | |
4419dbe6 | 450 | tx_push->doorbell = |
c0c050c5 MC |
451 | cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); |
452 | txr->tx_prod = prod; | |
453 | ||
b9a8460a | 454 | tx_buf->is_push = 1; |
c0c050c5 | 455 | netdev_tx_sent_queue(txq, skb->len); |
b9a8460a | 456 | wmb(); /* Sync is_push and byte queue before pushing data */ |
c0c050c5 | 457 | |
4419dbe6 MC |
458 | push_len = (length + sizeof(*tx_push) + 7) / 8; |
459 | if (push_len > 16) { | |
697197e5 MC |
460 | __iowrite64_copy(db, tx_push_buf, 16); |
461 | __iowrite32_copy(db + 4, tx_push_buf + 1, | |
9d13744b | 462 | (push_len - 16) << 1); |
4419dbe6 | 463 | } else { |
697197e5 | 464 | __iowrite64_copy(db, tx_push_buf, push_len); |
4419dbe6 | 465 | } |
c0c050c5 | 466 | |
c0c050c5 MC |
467 | goto tx_done; |
468 | } | |
469 | ||
470 | normal_tx: | |
471 | if (length < BNXT_MIN_PKT_SIZE) { | |
472 | pad = BNXT_MIN_PKT_SIZE - length; | |
473 | if (skb_pad(skb, pad)) { | |
474 | /* SKB already freed. */ | |
475 | tx_buf->skb = NULL; | |
476 | return NETDEV_TX_OK; | |
477 | } | |
478 | length = BNXT_MIN_PKT_SIZE; | |
479 | } | |
480 | ||
481 | mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); | |
482 | ||
483 | if (unlikely(dma_mapping_error(&pdev->dev, mapping))) { | |
484 | dev_kfree_skb_any(skb); | |
485 | tx_buf->skb = NULL; | |
486 | return NETDEV_TX_OK; | |
487 | } | |
488 | ||
489 | dma_unmap_addr_set(tx_buf, mapping, mapping); | |
490 | flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | | |
491 | ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); | |
492 | ||
493 | txbd->tx_bd_haddr = cpu_to_le64(mapping); | |
494 | ||
495 | prod = NEXT_TX(prod); | |
496 | txbd1 = (struct tx_bd_ext *) | |
497 | &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; | |
498 | ||
499 | txbd1->tx_bd_hsize_lflags = 0; | |
500 | if (skb_is_gso(skb)) { | |
501 | u32 hdr_len; | |
502 | ||
503 | if (skb->encapsulation) | |
504 | hdr_len = skb_inner_network_offset(skb) + | |
505 | skb_inner_network_header_len(skb) + | |
506 | inner_tcp_hdrlen(skb); | |
507 | else | |
508 | hdr_len = skb_transport_offset(skb) + | |
509 | tcp_hdrlen(skb); | |
510 | ||
511 | txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO | | |
512 | TX_BD_FLAGS_T_IPID | | |
513 | (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); | |
514 | length = skb_shinfo(skb)->gso_size; | |
515 | txbd1->tx_bd_mss = cpu_to_le32(length); | |
516 | length += hdr_len; | |
517 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
518 | txbd1->tx_bd_hsize_lflags = | |
519 | cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); | |
520 | txbd1->tx_bd_mss = 0; | |
521 | } | |
522 | ||
523 | length >>= 9; | |
2b3c6885 MC |
524 | if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) { |
525 | dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n", | |
526 | skb->len); | |
527 | i = 0; | |
528 | goto tx_dma_error; | |
529 | } | |
c0c050c5 MC |
530 | flags |= bnxt_lhint_arr[length]; |
531 | txbd->tx_bd_len_flags_type = cpu_to_le32(flags); | |
532 | ||
533 | txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); | |
ee5c7fb3 SP |
534 | txbd1->tx_bd_cfa_action = |
535 | cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); | |
c0c050c5 MC |
536 | for (i = 0; i < last_frag; i++) { |
537 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
538 | ||
539 | prod = NEXT_TX(prod); | |
540 | txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; | |
541 | ||
542 | len = skb_frag_size(frag); | |
543 | mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, | |
544 | DMA_TO_DEVICE); | |
545 | ||
546 | if (unlikely(dma_mapping_error(&pdev->dev, mapping))) | |
547 | goto tx_dma_error; | |
548 | ||
549 | tx_buf = &txr->tx_buf_ring[prod]; | |
550 | dma_unmap_addr_set(tx_buf, mapping, mapping); | |
551 | ||
552 | txbd->tx_bd_haddr = cpu_to_le64(mapping); | |
553 | ||
554 | flags = len << TX_BD_LEN_SHIFT; | |
555 | txbd->tx_bd_len_flags_type = cpu_to_le32(flags); | |
556 | } | |
557 | ||
558 | flags &= ~TX_BD_LEN; | |
559 | txbd->tx_bd_len_flags_type = | |
560 | cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | | |
561 | TX_BD_FLAGS_PACKET_END); | |
562 | ||
563 | netdev_tx_sent_queue(txq, skb->len); | |
564 | ||
565 | /* Sync BD data before updating doorbell */ | |
566 | wmb(); | |
567 | ||
568 | prod = NEXT_TX(prod); | |
569 | txr->tx_prod = prod; | |
570 | ||
6b16f9ee | 571 | if (!netdev_xmit_more() || netif_xmit_stopped(txq)) |
697197e5 | 572 | bnxt_db_write(bp, &txr->tx_db, prod); |
c0c050c5 MC |
573 | |
574 | tx_done: | |
575 | ||
c0c050c5 | 576 | if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { |
6b16f9ee | 577 | if (netdev_xmit_more() && !tx_buf->is_push) |
697197e5 | 578 | bnxt_db_write(bp, &txr->tx_db, prod); |
4d172f21 | 579 | |
c0c050c5 MC |
580 | netif_tx_stop_queue(txq); |
581 | ||
582 | /* netif_tx_stop_queue() must be done before checking | |
583 | * tx index in bnxt_tx_avail() below, because in | |
584 | * bnxt_tx_int(), we update tx index before checking for | |
585 | * netif_tx_queue_stopped(). | |
586 | */ | |
587 | smp_mb(); | |
588 | if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) | |
589 | netif_tx_wake_queue(txq); | |
590 | } | |
591 | return NETDEV_TX_OK; | |
592 | ||
593 | tx_dma_error: | |
594 | last_frag = i; | |
595 | ||
596 | /* start back at beginning and unmap skb */ | |
597 | prod = txr->tx_prod; | |
598 | tx_buf = &txr->tx_buf_ring[prod]; | |
599 | tx_buf->skb = NULL; | |
600 | dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), | |
601 | skb_headlen(skb), PCI_DMA_TODEVICE); | |
602 | prod = NEXT_TX(prod); | |
603 | ||
604 | /* unmap remaining mapped pages */ | |
605 | for (i = 0; i < last_frag; i++) { | |
606 | prod = NEXT_TX(prod); | |
607 | tx_buf = &txr->tx_buf_ring[prod]; | |
608 | dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), | |
609 | skb_frag_size(&skb_shinfo(skb)->frags[i]), | |
610 | PCI_DMA_TODEVICE); | |
611 | } | |
612 | ||
613 | dev_kfree_skb_any(skb); | |
614 | return NETDEV_TX_OK; | |
615 | } | |
616 | ||
617 | static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) | |
618 | { | |
b6ab4b01 | 619 | struct bnxt_tx_ring_info *txr = bnapi->tx_ring; |
a960dec9 | 620 | struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index); |
c0c050c5 MC |
621 | u16 cons = txr->tx_cons; |
622 | struct pci_dev *pdev = bp->pdev; | |
623 | int i; | |
624 | unsigned int tx_bytes = 0; | |
625 | ||
626 | for (i = 0; i < nr_pkts; i++) { | |
627 | struct bnxt_sw_tx_bd *tx_buf; | |
628 | struct sk_buff *skb; | |
629 | int j, last; | |
630 | ||
631 | tx_buf = &txr->tx_buf_ring[cons]; | |
632 | cons = NEXT_TX(cons); | |
633 | skb = tx_buf->skb; | |
634 | tx_buf->skb = NULL; | |
635 | ||
636 | if (tx_buf->is_push) { | |
637 | tx_buf->is_push = 0; | |
638 | goto next_tx_int; | |
639 | } | |
640 | ||
641 | dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), | |
642 | skb_headlen(skb), PCI_DMA_TODEVICE); | |
643 | last = tx_buf->nr_frags; | |
644 | ||
645 | for (j = 0; j < last; j++) { | |
646 | cons = NEXT_TX(cons); | |
647 | tx_buf = &txr->tx_buf_ring[cons]; | |
648 | dma_unmap_page( | |
649 | &pdev->dev, | |
650 | dma_unmap_addr(tx_buf, mapping), | |
651 | skb_frag_size(&skb_shinfo(skb)->frags[j]), | |
652 | PCI_DMA_TODEVICE); | |
653 | } | |
654 | ||
655 | next_tx_int: | |
656 | cons = NEXT_TX(cons); | |
657 | ||
658 | tx_bytes += skb->len; | |
659 | dev_kfree_skb_any(skb); | |
660 | } | |
661 | ||
662 | netdev_tx_completed_queue(txq, nr_pkts, tx_bytes); | |
663 | txr->tx_cons = cons; | |
664 | ||
665 | /* Need to make the tx_cons update visible to bnxt_start_xmit() | |
666 | * before checking for netif_tx_queue_stopped(). Without the | |
667 | * memory barrier, there is a small possibility that bnxt_start_xmit() | |
668 | * will miss it and cause the queue to be stopped forever. | |
669 | */ | |
670 | smp_mb(); | |
671 | ||
672 | if (unlikely(netif_tx_queue_stopped(txq)) && | |
673 | (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) { | |
674 | __netif_tx_lock(txq, smp_processor_id()); | |
675 | if (netif_tx_queue_stopped(txq) && | |
676 | bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh && | |
677 | txr->dev_state != BNXT_DEV_STATE_CLOSING) | |
678 | netif_tx_wake_queue(txq); | |
679 | __netif_tx_unlock(txq); | |
680 | } | |
681 | } | |
682 | ||
c61fb99c | 683 | static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping, |
322b87ca | 684 | struct bnxt_rx_ring_info *rxr, |
c61fb99c MC |
685 | gfp_t gfp) |
686 | { | |
687 | struct device *dev = &bp->pdev->dev; | |
688 | struct page *page; | |
689 | ||
322b87ca | 690 | page = page_pool_dev_alloc_pages(rxr->page_pool); |
c61fb99c MC |
691 | if (!page) |
692 | return NULL; | |
693 | ||
c519fe9a SN |
694 | *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir, |
695 | DMA_ATTR_WEAK_ORDERING); | |
c61fb99c | 696 | if (dma_mapping_error(dev, *mapping)) { |
322b87ca | 697 | page_pool_recycle_direct(rxr->page_pool, page); |
c61fb99c MC |
698 | return NULL; |
699 | } | |
700 | *mapping += bp->rx_dma_offset; | |
701 | return page; | |
702 | } | |
703 | ||
c0c050c5 MC |
704 | static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping, |
705 | gfp_t gfp) | |
706 | { | |
707 | u8 *data; | |
708 | struct pci_dev *pdev = bp->pdev; | |
709 | ||
710 | data = kmalloc(bp->rx_buf_size, gfp); | |
711 | if (!data) | |
712 | return NULL; | |
713 | ||
c519fe9a SN |
714 | *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset, |
715 | bp->rx_buf_use_size, bp->rx_dir, | |
716 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
717 | |
718 | if (dma_mapping_error(&pdev->dev, *mapping)) { | |
719 | kfree(data); | |
720 | data = NULL; | |
721 | } | |
722 | return data; | |
723 | } | |
724 | ||
38413406 MC |
725 | int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, |
726 | u16 prod, gfp_t gfp) | |
c0c050c5 MC |
727 | { |
728 | struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
729 | struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; | |
c0c050c5 MC |
730 | dma_addr_t mapping; |
731 | ||
c61fb99c | 732 | if (BNXT_RX_PAGE_MODE(bp)) { |
322b87ca AG |
733 | struct page *page = |
734 | __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp); | |
c0c050c5 | 735 | |
c61fb99c MC |
736 | if (!page) |
737 | return -ENOMEM; | |
738 | ||
739 | rx_buf->data = page; | |
740 | rx_buf->data_ptr = page_address(page) + bp->rx_offset; | |
741 | } else { | |
742 | u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp); | |
743 | ||
744 | if (!data) | |
745 | return -ENOMEM; | |
746 | ||
747 | rx_buf->data = data; | |
748 | rx_buf->data_ptr = data + bp->rx_offset; | |
749 | } | |
11cd119d | 750 | rx_buf->mapping = mapping; |
c0c050c5 MC |
751 | |
752 | rxbd->rx_bd_haddr = cpu_to_le64(mapping); | |
c0c050c5 MC |
753 | return 0; |
754 | } | |
755 | ||
c6d30e83 | 756 | void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data) |
c0c050c5 MC |
757 | { |
758 | u16 prod = rxr->rx_prod; | |
759 | struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; | |
760 | struct rx_bd *cons_bd, *prod_bd; | |
761 | ||
762 | prod_rx_buf = &rxr->rx_buf_ring[prod]; | |
763 | cons_rx_buf = &rxr->rx_buf_ring[cons]; | |
764 | ||
765 | prod_rx_buf->data = data; | |
6bb19474 | 766 | prod_rx_buf->data_ptr = cons_rx_buf->data_ptr; |
c0c050c5 | 767 | |
11cd119d | 768 | prod_rx_buf->mapping = cons_rx_buf->mapping; |
c0c050c5 MC |
769 | |
770 | prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
771 | cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; | |
772 | ||
773 | prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; | |
774 | } | |
775 | ||
776 | static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) | |
777 | { | |
778 | u16 next, max = rxr->rx_agg_bmap_size; | |
779 | ||
780 | next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); | |
781 | if (next >= max) | |
782 | next = find_first_zero_bit(rxr->rx_agg_bmap, max); | |
783 | return next; | |
784 | } | |
785 | ||
786 | static inline int bnxt_alloc_rx_page(struct bnxt *bp, | |
787 | struct bnxt_rx_ring_info *rxr, | |
788 | u16 prod, gfp_t gfp) | |
789 | { | |
790 | struct rx_bd *rxbd = | |
791 | &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
792 | struct bnxt_sw_rx_agg_bd *rx_agg_buf; | |
793 | struct pci_dev *pdev = bp->pdev; | |
794 | struct page *page; | |
795 | dma_addr_t mapping; | |
796 | u16 sw_prod = rxr->rx_sw_agg_prod; | |
89d0a06c | 797 | unsigned int offset = 0; |
c0c050c5 | 798 | |
89d0a06c MC |
799 | if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) { |
800 | page = rxr->rx_page; | |
801 | if (!page) { | |
802 | page = alloc_page(gfp); | |
803 | if (!page) | |
804 | return -ENOMEM; | |
805 | rxr->rx_page = page; | |
806 | rxr->rx_page_offset = 0; | |
807 | } | |
808 | offset = rxr->rx_page_offset; | |
809 | rxr->rx_page_offset += BNXT_RX_PAGE_SIZE; | |
810 | if (rxr->rx_page_offset == PAGE_SIZE) | |
811 | rxr->rx_page = NULL; | |
812 | else | |
813 | get_page(page); | |
814 | } else { | |
815 | page = alloc_page(gfp); | |
816 | if (!page) | |
817 | return -ENOMEM; | |
818 | } | |
c0c050c5 | 819 | |
c519fe9a SN |
820 | mapping = dma_map_page_attrs(&pdev->dev, page, offset, |
821 | BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE, | |
822 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
823 | if (dma_mapping_error(&pdev->dev, mapping)) { |
824 | __free_page(page); | |
825 | return -EIO; | |
826 | } | |
827 | ||
828 | if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) | |
829 | sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); | |
830 | ||
831 | __set_bit(sw_prod, rxr->rx_agg_bmap); | |
832 | rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; | |
833 | rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); | |
834 | ||
835 | rx_agg_buf->page = page; | |
89d0a06c | 836 | rx_agg_buf->offset = offset; |
c0c050c5 MC |
837 | rx_agg_buf->mapping = mapping; |
838 | rxbd->rx_bd_haddr = cpu_to_le64(mapping); | |
839 | rxbd->rx_bd_opaque = sw_prod; | |
840 | return 0; | |
841 | } | |
842 | ||
4a228a3a MC |
843 | static struct rx_agg_cmp *bnxt_get_agg(struct bnxt *bp, |
844 | struct bnxt_cp_ring_info *cpr, | |
845 | u16 cp_cons, u16 curr) | |
846 | { | |
847 | struct rx_agg_cmp *agg; | |
848 | ||
849 | cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr)); | |
850 | agg = (struct rx_agg_cmp *) | |
851 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
852 | return agg; | |
853 | } | |
854 | ||
bfcd8d79 MC |
855 | static struct rx_agg_cmp *bnxt_get_tpa_agg_p5(struct bnxt *bp, |
856 | struct bnxt_rx_ring_info *rxr, | |
857 | u16 agg_id, u16 curr) | |
858 | { | |
859 | struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id]; | |
860 | ||
861 | return &tpa_info->agg_arr[curr]; | |
862 | } | |
863 | ||
4a228a3a MC |
864 | static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx, |
865 | u16 start, u32 agg_bufs, bool tpa) | |
c0c050c5 | 866 | { |
e44758b7 | 867 | struct bnxt_napi *bnapi = cpr->bnapi; |
c0c050c5 | 868 | struct bnxt *bp = bnapi->bp; |
b6ab4b01 | 869 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
c0c050c5 MC |
870 | u16 prod = rxr->rx_agg_prod; |
871 | u16 sw_prod = rxr->rx_sw_agg_prod; | |
bfcd8d79 | 872 | bool p5_tpa = false; |
c0c050c5 MC |
873 | u32 i; |
874 | ||
bfcd8d79 MC |
875 | if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) |
876 | p5_tpa = true; | |
877 | ||
c0c050c5 MC |
878 | for (i = 0; i < agg_bufs; i++) { |
879 | u16 cons; | |
880 | struct rx_agg_cmp *agg; | |
881 | struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; | |
882 | struct rx_bd *prod_bd; | |
883 | struct page *page; | |
884 | ||
bfcd8d79 MC |
885 | if (p5_tpa) |
886 | agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i); | |
887 | else | |
888 | agg = bnxt_get_agg(bp, cpr, idx, start + i); | |
c0c050c5 MC |
889 | cons = agg->rx_agg_cmp_opaque; |
890 | __clear_bit(cons, rxr->rx_agg_bmap); | |
891 | ||
892 | if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) | |
893 | sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); | |
894 | ||
895 | __set_bit(sw_prod, rxr->rx_agg_bmap); | |
896 | prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; | |
897 | cons_rx_buf = &rxr->rx_agg_ring[cons]; | |
898 | ||
899 | /* It is possible for sw_prod to be equal to cons, so | |
900 | * set cons_rx_buf->page to NULL first. | |
901 | */ | |
902 | page = cons_rx_buf->page; | |
903 | cons_rx_buf->page = NULL; | |
904 | prod_rx_buf->page = page; | |
89d0a06c | 905 | prod_rx_buf->offset = cons_rx_buf->offset; |
c0c050c5 MC |
906 | |
907 | prod_rx_buf->mapping = cons_rx_buf->mapping; | |
908 | ||
909 | prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
910 | ||
911 | prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); | |
912 | prod_bd->rx_bd_opaque = sw_prod; | |
913 | ||
914 | prod = NEXT_RX_AGG(prod); | |
915 | sw_prod = NEXT_RX_AGG(sw_prod); | |
c0c050c5 MC |
916 | } |
917 | rxr->rx_agg_prod = prod; | |
918 | rxr->rx_sw_agg_prod = sw_prod; | |
919 | } | |
920 | ||
c61fb99c MC |
921 | static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp, |
922 | struct bnxt_rx_ring_info *rxr, | |
923 | u16 cons, void *data, u8 *data_ptr, | |
924 | dma_addr_t dma_addr, | |
925 | unsigned int offset_and_len) | |
926 | { | |
927 | unsigned int payload = offset_and_len >> 16; | |
928 | unsigned int len = offset_and_len & 0xffff; | |
d7840976 | 929 | skb_frag_t *frag; |
c61fb99c MC |
930 | struct page *page = data; |
931 | u16 prod = rxr->rx_prod; | |
932 | struct sk_buff *skb; | |
933 | int off, err; | |
934 | ||
935 | err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); | |
936 | if (unlikely(err)) { | |
937 | bnxt_reuse_rx_data(rxr, cons, data); | |
938 | return NULL; | |
939 | } | |
940 | dma_addr -= bp->rx_dma_offset; | |
c519fe9a SN |
941 | dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir, |
942 | DMA_ATTR_WEAK_ORDERING); | |
3071c517 | 943 | page_pool_release_page(rxr->page_pool, page); |
c61fb99c MC |
944 | |
945 | if (unlikely(!payload)) | |
c43f1255 | 946 | payload = eth_get_headlen(bp->dev, data_ptr, len); |
c61fb99c MC |
947 | |
948 | skb = napi_alloc_skb(&rxr->bnapi->napi, payload); | |
949 | if (!skb) { | |
950 | __free_page(page); | |
951 | return NULL; | |
952 | } | |
953 | ||
954 | off = (void *)data_ptr - page_address(page); | |
955 | skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE); | |
956 | memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN, | |
957 | payload + NET_IP_ALIGN); | |
958 | ||
959 | frag = &skb_shinfo(skb)->frags[0]; | |
960 | skb_frag_size_sub(frag, payload); | |
b54c9d5b | 961 | skb_frag_off_add(frag, payload); |
c61fb99c MC |
962 | skb->data_len -= payload; |
963 | skb->tail += payload; | |
964 | ||
965 | return skb; | |
966 | } | |
967 | ||
c0c050c5 MC |
968 | static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, |
969 | struct bnxt_rx_ring_info *rxr, u16 cons, | |
6bb19474 MC |
970 | void *data, u8 *data_ptr, |
971 | dma_addr_t dma_addr, | |
972 | unsigned int offset_and_len) | |
c0c050c5 | 973 | { |
6bb19474 | 974 | u16 prod = rxr->rx_prod; |
c0c050c5 | 975 | struct sk_buff *skb; |
6bb19474 | 976 | int err; |
c0c050c5 MC |
977 | |
978 | err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); | |
979 | if (unlikely(err)) { | |
980 | bnxt_reuse_rx_data(rxr, cons, data); | |
981 | return NULL; | |
982 | } | |
983 | ||
984 | skb = build_skb(data, 0); | |
c519fe9a SN |
985 | dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, |
986 | bp->rx_dir, DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
987 | if (!skb) { |
988 | kfree(data); | |
989 | return NULL; | |
990 | } | |
991 | ||
b3dba77c | 992 | skb_reserve(skb, bp->rx_offset); |
6bb19474 | 993 | skb_put(skb, offset_and_len & 0xffff); |
c0c050c5 MC |
994 | return skb; |
995 | } | |
996 | ||
e44758b7 MC |
997 | static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, |
998 | struct bnxt_cp_ring_info *cpr, | |
4a228a3a MC |
999 | struct sk_buff *skb, u16 idx, |
1000 | u32 agg_bufs, bool tpa) | |
c0c050c5 | 1001 | { |
e44758b7 | 1002 | struct bnxt_napi *bnapi = cpr->bnapi; |
c0c050c5 | 1003 | struct pci_dev *pdev = bp->pdev; |
b6ab4b01 | 1004 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
c0c050c5 | 1005 | u16 prod = rxr->rx_agg_prod; |
bfcd8d79 | 1006 | bool p5_tpa = false; |
c0c050c5 MC |
1007 | u32 i; |
1008 | ||
bfcd8d79 MC |
1009 | if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) |
1010 | p5_tpa = true; | |
1011 | ||
c0c050c5 MC |
1012 | for (i = 0; i < agg_bufs; i++) { |
1013 | u16 cons, frag_len; | |
1014 | struct rx_agg_cmp *agg; | |
1015 | struct bnxt_sw_rx_agg_bd *cons_rx_buf; | |
1016 | struct page *page; | |
1017 | dma_addr_t mapping; | |
1018 | ||
bfcd8d79 MC |
1019 | if (p5_tpa) |
1020 | agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i); | |
1021 | else | |
1022 | agg = bnxt_get_agg(bp, cpr, idx, i); | |
c0c050c5 MC |
1023 | cons = agg->rx_agg_cmp_opaque; |
1024 | frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & | |
1025 | RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; | |
1026 | ||
1027 | cons_rx_buf = &rxr->rx_agg_ring[cons]; | |
89d0a06c MC |
1028 | skb_fill_page_desc(skb, i, cons_rx_buf->page, |
1029 | cons_rx_buf->offset, frag_len); | |
c0c050c5 MC |
1030 | __clear_bit(cons, rxr->rx_agg_bmap); |
1031 | ||
1032 | /* It is possible for bnxt_alloc_rx_page() to allocate | |
1033 | * a sw_prod index that equals the cons index, so we | |
1034 | * need to clear the cons entry now. | |
1035 | */ | |
11cd119d | 1036 | mapping = cons_rx_buf->mapping; |
c0c050c5 MC |
1037 | page = cons_rx_buf->page; |
1038 | cons_rx_buf->page = NULL; | |
1039 | ||
1040 | if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { | |
1041 | struct skb_shared_info *shinfo; | |
1042 | unsigned int nr_frags; | |
1043 | ||
1044 | shinfo = skb_shinfo(skb); | |
1045 | nr_frags = --shinfo->nr_frags; | |
1046 | __skb_frag_set_page(&shinfo->frags[nr_frags], NULL); | |
1047 | ||
1048 | dev_kfree_skb(skb); | |
1049 | ||
1050 | cons_rx_buf->page = page; | |
1051 | ||
1052 | /* Update prod since possibly some pages have been | |
1053 | * allocated already. | |
1054 | */ | |
1055 | rxr->rx_agg_prod = prod; | |
4a228a3a | 1056 | bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa); |
c0c050c5 MC |
1057 | return NULL; |
1058 | } | |
1059 | ||
c519fe9a SN |
1060 | dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE, |
1061 | PCI_DMA_FROMDEVICE, | |
1062 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
1063 | |
1064 | skb->data_len += frag_len; | |
1065 | skb->len += frag_len; | |
1066 | skb->truesize += PAGE_SIZE; | |
1067 | ||
1068 | prod = NEXT_RX_AGG(prod); | |
c0c050c5 MC |
1069 | } |
1070 | rxr->rx_agg_prod = prod; | |
1071 | return skb; | |
1072 | } | |
1073 | ||
1074 | static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, | |
1075 | u8 agg_bufs, u32 *raw_cons) | |
1076 | { | |
1077 | u16 last; | |
1078 | struct rx_agg_cmp *agg; | |
1079 | ||
1080 | *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); | |
1081 | last = RING_CMP(*raw_cons); | |
1082 | agg = (struct rx_agg_cmp *) | |
1083 | &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; | |
1084 | return RX_AGG_CMP_VALID(agg, *raw_cons); | |
1085 | } | |
1086 | ||
1087 | static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, | |
1088 | unsigned int len, | |
1089 | dma_addr_t mapping) | |
1090 | { | |
1091 | struct bnxt *bp = bnapi->bp; | |
1092 | struct pci_dev *pdev = bp->pdev; | |
1093 | struct sk_buff *skb; | |
1094 | ||
1095 | skb = napi_alloc_skb(&bnapi->napi, len); | |
1096 | if (!skb) | |
1097 | return NULL; | |
1098 | ||
745fc05c MC |
1099 | dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh, |
1100 | bp->rx_dir); | |
c0c050c5 | 1101 | |
6bb19474 MC |
1102 | memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN, |
1103 | len + NET_IP_ALIGN); | |
c0c050c5 | 1104 | |
745fc05c MC |
1105 | dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh, |
1106 | bp->rx_dir); | |
c0c050c5 MC |
1107 | |
1108 | skb_put(skb, len); | |
1109 | return skb; | |
1110 | } | |
1111 | ||
e44758b7 | 1112 | static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, |
fa7e2812 MC |
1113 | u32 *raw_cons, void *cmp) |
1114 | { | |
fa7e2812 MC |
1115 | struct rx_cmp *rxcmp = cmp; |
1116 | u32 tmp_raw_cons = *raw_cons; | |
1117 | u8 cmp_type, agg_bufs = 0; | |
1118 | ||
1119 | cmp_type = RX_CMP_TYPE(rxcmp); | |
1120 | ||
1121 | if (cmp_type == CMP_TYPE_RX_L2_CMP) { | |
1122 | agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & | |
1123 | RX_CMP_AGG_BUFS) >> | |
1124 | RX_CMP_AGG_BUFS_SHIFT; | |
1125 | } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { | |
1126 | struct rx_tpa_end_cmp *tpa_end = cmp; | |
1127 | ||
bfcd8d79 MC |
1128 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
1129 | return 0; | |
1130 | ||
4a228a3a | 1131 | agg_bufs = TPA_END_AGG_BUFS(tpa_end); |
fa7e2812 MC |
1132 | } |
1133 | ||
1134 | if (agg_bufs) { | |
1135 | if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) | |
1136 | return -EBUSY; | |
1137 | } | |
1138 | *raw_cons = tmp_raw_cons; | |
1139 | return 0; | |
1140 | } | |
1141 | ||
230d1f0d MC |
1142 | static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay) |
1143 | { | |
b148bb23 MC |
1144 | if (!(test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))) |
1145 | return; | |
1146 | ||
230d1f0d MC |
1147 | if (BNXT_PF(bp)) |
1148 | queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay); | |
1149 | else | |
1150 | schedule_delayed_work(&bp->fw_reset_task, delay); | |
1151 | } | |
1152 | ||
c213eae8 MC |
1153 | static void bnxt_queue_sp_work(struct bnxt *bp) |
1154 | { | |
1155 | if (BNXT_PF(bp)) | |
1156 | queue_work(bnxt_pf_wq, &bp->sp_task); | |
1157 | else | |
1158 | schedule_work(&bp->sp_task); | |
1159 | } | |
1160 | ||
1161 | static void bnxt_cancel_sp_work(struct bnxt *bp) | |
1162 | { | |
b148bb23 | 1163 | if (BNXT_PF(bp)) { |
c213eae8 | 1164 | flush_workqueue(bnxt_pf_wq); |
b148bb23 | 1165 | } else { |
c213eae8 | 1166 | cancel_work_sync(&bp->sp_task); |
b148bb23 MC |
1167 | cancel_delayed_work_sync(&bp->fw_reset_task); |
1168 | } | |
c213eae8 MC |
1169 | } |
1170 | ||
fa7e2812 MC |
1171 | static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) |
1172 | { | |
1173 | if (!rxr->bnapi->in_reset) { | |
1174 | rxr->bnapi->in_reset = true; | |
1175 | set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); | |
c213eae8 | 1176 | bnxt_queue_sp_work(bp); |
fa7e2812 MC |
1177 | } |
1178 | rxr->rx_next_cons = 0xffff; | |
1179 | } | |
1180 | ||
ec4d8e7c MC |
1181 | static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) |
1182 | { | |
1183 | struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; | |
1184 | u16 idx = agg_id & MAX_TPA_P5_MASK; | |
1185 | ||
1186 | if (test_bit(idx, map->agg_idx_bmap)) | |
1187 | idx = find_first_zero_bit(map->agg_idx_bmap, | |
1188 | BNXT_AGG_IDX_BMAP_SIZE); | |
1189 | __set_bit(idx, map->agg_idx_bmap); | |
1190 | map->agg_id_tbl[agg_id] = idx; | |
1191 | return idx; | |
1192 | } | |
1193 | ||
1194 | static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) | |
1195 | { | |
1196 | struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; | |
1197 | ||
1198 | __clear_bit(idx, map->agg_idx_bmap); | |
1199 | } | |
1200 | ||
1201 | static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) | |
1202 | { | |
1203 | struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; | |
1204 | ||
1205 | return map->agg_id_tbl[agg_id]; | |
1206 | } | |
1207 | ||
c0c050c5 MC |
1208 | static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, |
1209 | struct rx_tpa_start_cmp *tpa_start, | |
1210 | struct rx_tpa_start_cmp_ext *tpa_start1) | |
1211 | { | |
c0c050c5 | 1212 | struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; |
bfcd8d79 MC |
1213 | struct bnxt_tpa_info *tpa_info; |
1214 | u16 cons, prod, agg_id; | |
c0c050c5 MC |
1215 | struct rx_bd *prod_bd; |
1216 | dma_addr_t mapping; | |
1217 | ||
ec4d8e7c | 1218 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
bfcd8d79 | 1219 | agg_id = TPA_START_AGG_ID_P5(tpa_start); |
ec4d8e7c MC |
1220 | agg_id = bnxt_alloc_agg_idx(rxr, agg_id); |
1221 | } else { | |
bfcd8d79 | 1222 | agg_id = TPA_START_AGG_ID(tpa_start); |
ec4d8e7c | 1223 | } |
c0c050c5 MC |
1224 | cons = tpa_start->rx_tpa_start_cmp_opaque; |
1225 | prod = rxr->rx_prod; | |
1226 | cons_rx_buf = &rxr->rx_buf_ring[cons]; | |
1227 | prod_rx_buf = &rxr->rx_buf_ring[prod]; | |
1228 | tpa_info = &rxr->rx_tpa[agg_id]; | |
1229 | ||
bfcd8d79 MC |
1230 | if (unlikely(cons != rxr->rx_next_cons || |
1231 | TPA_START_ERROR(tpa_start))) { | |
1232 | netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n", | |
1233 | cons, rxr->rx_next_cons, | |
1234 | TPA_START_ERROR_CODE(tpa_start1)); | |
fa7e2812 MC |
1235 | bnxt_sched_reset(bp, rxr); |
1236 | return; | |
1237 | } | |
ee5c7fb3 SP |
1238 | /* Store cfa_code in tpa_info to use in tpa_end |
1239 | * completion processing. | |
1240 | */ | |
1241 | tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1); | |
c0c050c5 | 1242 | prod_rx_buf->data = tpa_info->data; |
6bb19474 | 1243 | prod_rx_buf->data_ptr = tpa_info->data_ptr; |
c0c050c5 MC |
1244 | |
1245 | mapping = tpa_info->mapping; | |
11cd119d | 1246 | prod_rx_buf->mapping = mapping; |
c0c050c5 MC |
1247 | |
1248 | prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
1249 | ||
1250 | prod_bd->rx_bd_haddr = cpu_to_le64(mapping); | |
1251 | ||
1252 | tpa_info->data = cons_rx_buf->data; | |
6bb19474 | 1253 | tpa_info->data_ptr = cons_rx_buf->data_ptr; |
c0c050c5 | 1254 | cons_rx_buf->data = NULL; |
11cd119d | 1255 | tpa_info->mapping = cons_rx_buf->mapping; |
c0c050c5 MC |
1256 | |
1257 | tpa_info->len = | |
1258 | le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> | |
1259 | RX_TPA_START_CMP_LEN_SHIFT; | |
1260 | if (likely(TPA_START_HASH_VALID(tpa_start))) { | |
1261 | u32 hash_type = TPA_START_HASH_TYPE(tpa_start); | |
1262 | ||
1263 | tpa_info->hash_type = PKT_HASH_TYPE_L4; | |
1264 | tpa_info->gso_type = SKB_GSO_TCPV4; | |
1265 | /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ | |
50f011b6 | 1266 | if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1)) |
c0c050c5 MC |
1267 | tpa_info->gso_type = SKB_GSO_TCPV6; |
1268 | tpa_info->rss_hash = | |
1269 | le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); | |
1270 | } else { | |
1271 | tpa_info->hash_type = PKT_HASH_TYPE_NONE; | |
1272 | tpa_info->gso_type = 0; | |
1273 | if (netif_msg_rx_err(bp)) | |
1274 | netdev_warn(bp->dev, "TPA packet without valid hash\n"); | |
1275 | } | |
1276 | tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); | |
1277 | tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); | |
94758f8d | 1278 | tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info); |
bfcd8d79 | 1279 | tpa_info->agg_count = 0; |
c0c050c5 MC |
1280 | |
1281 | rxr->rx_prod = NEXT_RX(prod); | |
1282 | cons = NEXT_RX(cons); | |
376a5b86 | 1283 | rxr->rx_next_cons = NEXT_RX(cons); |
c0c050c5 MC |
1284 | cons_rx_buf = &rxr->rx_buf_ring[cons]; |
1285 | ||
1286 | bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); | |
1287 | rxr->rx_prod = NEXT_RX(rxr->rx_prod); | |
1288 | cons_rx_buf->data = NULL; | |
1289 | } | |
1290 | ||
4a228a3a | 1291 | static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs) |
c0c050c5 MC |
1292 | { |
1293 | if (agg_bufs) | |
4a228a3a | 1294 | bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true); |
c0c050c5 MC |
1295 | } |
1296 | ||
bee5a188 MC |
1297 | #ifdef CONFIG_INET |
1298 | static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto) | |
1299 | { | |
1300 | struct udphdr *uh = NULL; | |
1301 | ||
1302 | if (ip_proto == htons(ETH_P_IP)) { | |
1303 | struct iphdr *iph = (struct iphdr *)skb->data; | |
1304 | ||
1305 | if (iph->protocol == IPPROTO_UDP) | |
1306 | uh = (struct udphdr *)(iph + 1); | |
1307 | } else { | |
1308 | struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; | |
1309 | ||
1310 | if (iph->nexthdr == IPPROTO_UDP) | |
1311 | uh = (struct udphdr *)(iph + 1); | |
1312 | } | |
1313 | if (uh) { | |
1314 | if (uh->check) | |
1315 | skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM; | |
1316 | else | |
1317 | skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; | |
1318 | } | |
1319 | } | |
1320 | #endif | |
1321 | ||
94758f8d MC |
1322 | static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info, |
1323 | int payload_off, int tcp_ts, | |
1324 | struct sk_buff *skb) | |
1325 | { | |
1326 | #ifdef CONFIG_INET | |
1327 | struct tcphdr *th; | |
1328 | int len, nw_off; | |
1329 | u16 outer_ip_off, inner_ip_off, inner_mac_off; | |
1330 | u32 hdr_info = tpa_info->hdr_info; | |
1331 | bool loopback = false; | |
1332 | ||
1333 | inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); | |
1334 | inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); | |
1335 | outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); | |
1336 | ||
1337 | /* If the packet is an internal loopback packet, the offsets will | |
1338 | * have an extra 4 bytes. | |
1339 | */ | |
1340 | if (inner_mac_off == 4) { | |
1341 | loopback = true; | |
1342 | } else if (inner_mac_off > 4) { | |
1343 | __be16 proto = *((__be16 *)(skb->data + inner_ip_off - | |
1344 | ETH_HLEN - 2)); | |
1345 | ||
1346 | /* We only support inner iPv4/ipv6. If we don't see the | |
1347 | * correct protocol ID, it must be a loopback packet where | |
1348 | * the offsets are off by 4. | |
1349 | */ | |
09a7636a | 1350 | if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6)) |
94758f8d MC |
1351 | loopback = true; |
1352 | } | |
1353 | if (loopback) { | |
1354 | /* internal loopback packet, subtract all offsets by 4 */ | |
1355 | inner_ip_off -= 4; | |
1356 | inner_mac_off -= 4; | |
1357 | outer_ip_off -= 4; | |
1358 | } | |
1359 | ||
1360 | nw_off = inner_ip_off - ETH_HLEN; | |
1361 | skb_set_network_header(skb, nw_off); | |
1362 | if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) { | |
1363 | struct ipv6hdr *iph = ipv6_hdr(skb); | |
1364 | ||
1365 | skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); | |
1366 | len = skb->len - skb_transport_offset(skb); | |
1367 | th = tcp_hdr(skb); | |
1368 | th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); | |
1369 | } else { | |
1370 | struct iphdr *iph = ip_hdr(skb); | |
1371 | ||
1372 | skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); | |
1373 | len = skb->len - skb_transport_offset(skb); | |
1374 | th = tcp_hdr(skb); | |
1375 | th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); | |
1376 | } | |
1377 | ||
1378 | if (inner_mac_off) { /* tunnel */ | |
94758f8d MC |
1379 | __be16 proto = *((__be16 *)(skb->data + outer_ip_off - |
1380 | ETH_HLEN - 2)); | |
1381 | ||
bee5a188 | 1382 | bnxt_gro_tunnel(skb, proto); |
94758f8d MC |
1383 | } |
1384 | #endif | |
1385 | return skb; | |
1386 | } | |
1387 | ||
67912c36 MC |
1388 | static struct sk_buff *bnxt_gro_func_5750x(struct bnxt_tpa_info *tpa_info, |
1389 | int payload_off, int tcp_ts, | |
1390 | struct sk_buff *skb) | |
1391 | { | |
1392 | #ifdef CONFIG_INET | |
1393 | u16 outer_ip_off, inner_ip_off, inner_mac_off; | |
1394 | u32 hdr_info = tpa_info->hdr_info; | |
1395 | int iphdr_len, nw_off; | |
1396 | ||
1397 | inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); | |
1398 | inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); | |
1399 | outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); | |
1400 | ||
1401 | nw_off = inner_ip_off - ETH_HLEN; | |
1402 | skb_set_network_header(skb, nw_off); | |
1403 | iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ? | |
1404 | sizeof(struct ipv6hdr) : sizeof(struct iphdr); | |
1405 | skb_set_transport_header(skb, nw_off + iphdr_len); | |
1406 | ||
1407 | if (inner_mac_off) { /* tunnel */ | |
1408 | __be16 proto = *((__be16 *)(skb->data + outer_ip_off - | |
1409 | ETH_HLEN - 2)); | |
1410 | ||
1411 | bnxt_gro_tunnel(skb, proto); | |
1412 | } | |
1413 | #endif | |
1414 | return skb; | |
1415 | } | |
1416 | ||
c0c050c5 MC |
1417 | #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) |
1418 | #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) | |
1419 | ||
309369c9 MC |
1420 | static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info, |
1421 | int payload_off, int tcp_ts, | |
c0c050c5 MC |
1422 | struct sk_buff *skb) |
1423 | { | |
d1611c3a | 1424 | #ifdef CONFIG_INET |
c0c050c5 | 1425 | struct tcphdr *th; |
719ca811 | 1426 | int len, nw_off, tcp_opt_len = 0; |
27e24189 | 1427 | |
309369c9 | 1428 | if (tcp_ts) |
c0c050c5 MC |
1429 | tcp_opt_len = 12; |
1430 | ||
c0c050c5 MC |
1431 | if (tpa_info->gso_type == SKB_GSO_TCPV4) { |
1432 | struct iphdr *iph; | |
1433 | ||
1434 | nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - | |
1435 | ETH_HLEN; | |
1436 | skb_set_network_header(skb, nw_off); | |
1437 | iph = ip_hdr(skb); | |
1438 | skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); | |
1439 | len = skb->len - skb_transport_offset(skb); | |
1440 | th = tcp_hdr(skb); | |
1441 | th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); | |
1442 | } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { | |
1443 | struct ipv6hdr *iph; | |
1444 | ||
1445 | nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - | |
1446 | ETH_HLEN; | |
1447 | skb_set_network_header(skb, nw_off); | |
1448 | iph = ipv6_hdr(skb); | |
1449 | skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); | |
1450 | len = skb->len - skb_transport_offset(skb); | |
1451 | th = tcp_hdr(skb); | |
1452 | th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); | |
1453 | } else { | |
1454 | dev_kfree_skb_any(skb); | |
1455 | return NULL; | |
1456 | } | |
c0c050c5 | 1457 | |
bee5a188 MC |
1458 | if (nw_off) /* tunnel */ |
1459 | bnxt_gro_tunnel(skb, skb->protocol); | |
c0c050c5 MC |
1460 | #endif |
1461 | return skb; | |
1462 | } | |
1463 | ||
309369c9 MC |
1464 | static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp, |
1465 | struct bnxt_tpa_info *tpa_info, | |
1466 | struct rx_tpa_end_cmp *tpa_end, | |
1467 | struct rx_tpa_end_cmp_ext *tpa_end1, | |
1468 | struct sk_buff *skb) | |
1469 | { | |
1470 | #ifdef CONFIG_INET | |
1471 | int payload_off; | |
1472 | u16 segs; | |
1473 | ||
1474 | segs = TPA_END_TPA_SEGS(tpa_end); | |
1475 | if (segs == 1) | |
1476 | return skb; | |
1477 | ||
1478 | NAPI_GRO_CB(skb)->count = segs; | |
1479 | skb_shinfo(skb)->gso_size = | |
1480 | le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); | |
1481 | skb_shinfo(skb)->gso_type = tpa_info->gso_type; | |
bfcd8d79 MC |
1482 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
1483 | payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1); | |
1484 | else | |
1485 | payload_off = TPA_END_PAYLOAD_OFF(tpa_end); | |
309369c9 | 1486 | skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb); |
5910906c MC |
1487 | if (likely(skb)) |
1488 | tcp_gro_complete(skb); | |
309369c9 MC |
1489 | #endif |
1490 | return skb; | |
1491 | } | |
1492 | ||
ee5c7fb3 SP |
1493 | /* Given the cfa_code of a received packet determine which |
1494 | * netdev (vf-rep or PF) the packet is destined to. | |
1495 | */ | |
1496 | static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code) | |
1497 | { | |
1498 | struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code); | |
1499 | ||
1500 | /* if vf-rep dev is NULL, the must belongs to the PF */ | |
1501 | return dev ? dev : bp->dev; | |
1502 | } | |
1503 | ||
c0c050c5 | 1504 | static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, |
e44758b7 | 1505 | struct bnxt_cp_ring_info *cpr, |
c0c050c5 MC |
1506 | u32 *raw_cons, |
1507 | struct rx_tpa_end_cmp *tpa_end, | |
1508 | struct rx_tpa_end_cmp_ext *tpa_end1, | |
4e5dbbda | 1509 | u8 *event) |
c0c050c5 | 1510 | { |
e44758b7 | 1511 | struct bnxt_napi *bnapi = cpr->bnapi; |
b6ab4b01 | 1512 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
6bb19474 | 1513 | u8 *data_ptr, agg_bufs; |
c0c050c5 MC |
1514 | unsigned int len; |
1515 | struct bnxt_tpa_info *tpa_info; | |
1516 | dma_addr_t mapping; | |
1517 | struct sk_buff *skb; | |
bfcd8d79 | 1518 | u16 idx = 0, agg_id; |
6bb19474 | 1519 | void *data; |
bfcd8d79 | 1520 | bool gro; |
c0c050c5 | 1521 | |
fa7e2812 | 1522 | if (unlikely(bnapi->in_reset)) { |
e44758b7 | 1523 | int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end); |
fa7e2812 MC |
1524 | |
1525 | if (rc < 0) | |
1526 | return ERR_PTR(-EBUSY); | |
1527 | return NULL; | |
1528 | } | |
1529 | ||
bfcd8d79 MC |
1530 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
1531 | agg_id = TPA_END_AGG_ID_P5(tpa_end); | |
ec4d8e7c | 1532 | agg_id = bnxt_lookup_agg_idx(rxr, agg_id); |
bfcd8d79 MC |
1533 | agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1); |
1534 | tpa_info = &rxr->rx_tpa[agg_id]; | |
1535 | if (unlikely(agg_bufs != tpa_info->agg_count)) { | |
1536 | netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n", | |
1537 | agg_bufs, tpa_info->agg_count); | |
1538 | agg_bufs = tpa_info->agg_count; | |
1539 | } | |
1540 | tpa_info->agg_count = 0; | |
1541 | *event |= BNXT_AGG_EVENT; | |
ec4d8e7c | 1542 | bnxt_free_agg_idx(rxr, agg_id); |
bfcd8d79 MC |
1543 | idx = agg_id; |
1544 | gro = !!(bp->flags & BNXT_FLAG_GRO); | |
1545 | } else { | |
1546 | agg_id = TPA_END_AGG_ID(tpa_end); | |
1547 | agg_bufs = TPA_END_AGG_BUFS(tpa_end); | |
1548 | tpa_info = &rxr->rx_tpa[agg_id]; | |
1549 | idx = RING_CMP(*raw_cons); | |
1550 | if (agg_bufs) { | |
1551 | if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) | |
1552 | return ERR_PTR(-EBUSY); | |
1553 | ||
1554 | *event |= BNXT_AGG_EVENT; | |
1555 | idx = NEXT_CMP(idx); | |
1556 | } | |
1557 | gro = !!TPA_END_GRO(tpa_end); | |
1558 | } | |
c0c050c5 | 1559 | data = tpa_info->data; |
6bb19474 MC |
1560 | data_ptr = tpa_info->data_ptr; |
1561 | prefetch(data_ptr); | |
c0c050c5 MC |
1562 | len = tpa_info->len; |
1563 | mapping = tpa_info->mapping; | |
1564 | ||
69c149e2 | 1565 | if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) { |
4a228a3a | 1566 | bnxt_abort_tpa(cpr, idx, agg_bufs); |
69c149e2 MC |
1567 | if (agg_bufs > MAX_SKB_FRAGS) |
1568 | netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", | |
1569 | agg_bufs, (int)MAX_SKB_FRAGS); | |
c0c050c5 MC |
1570 | return NULL; |
1571 | } | |
1572 | ||
1573 | if (len <= bp->rx_copy_thresh) { | |
6bb19474 | 1574 | skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping); |
c0c050c5 | 1575 | if (!skb) { |
4a228a3a | 1576 | bnxt_abort_tpa(cpr, idx, agg_bufs); |
c0c050c5 MC |
1577 | return NULL; |
1578 | } | |
1579 | } else { | |
1580 | u8 *new_data; | |
1581 | dma_addr_t new_mapping; | |
1582 | ||
1583 | new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC); | |
1584 | if (!new_data) { | |
4a228a3a | 1585 | bnxt_abort_tpa(cpr, idx, agg_bufs); |
c0c050c5 MC |
1586 | return NULL; |
1587 | } | |
1588 | ||
1589 | tpa_info->data = new_data; | |
b3dba77c | 1590 | tpa_info->data_ptr = new_data + bp->rx_offset; |
c0c050c5 MC |
1591 | tpa_info->mapping = new_mapping; |
1592 | ||
1593 | skb = build_skb(data, 0); | |
c519fe9a SN |
1594 | dma_unmap_single_attrs(&bp->pdev->dev, mapping, |
1595 | bp->rx_buf_use_size, bp->rx_dir, | |
1596 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
1597 | |
1598 | if (!skb) { | |
1599 | kfree(data); | |
4a228a3a | 1600 | bnxt_abort_tpa(cpr, idx, agg_bufs); |
c0c050c5 MC |
1601 | return NULL; |
1602 | } | |
b3dba77c | 1603 | skb_reserve(skb, bp->rx_offset); |
c0c050c5 MC |
1604 | skb_put(skb, len); |
1605 | } | |
1606 | ||
1607 | if (agg_bufs) { | |
4a228a3a | 1608 | skb = bnxt_rx_pages(bp, cpr, skb, idx, agg_bufs, true); |
c0c050c5 MC |
1609 | if (!skb) { |
1610 | /* Page reuse already handled by bnxt_rx_pages(). */ | |
1611 | return NULL; | |
1612 | } | |
1613 | } | |
ee5c7fb3 SP |
1614 | |
1615 | skb->protocol = | |
1616 | eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code)); | |
c0c050c5 MC |
1617 | |
1618 | if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) | |
1619 | skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); | |
1620 | ||
8852ddb4 | 1621 | if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) && |
a196e96b | 1622 | (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) { |
c0c050c5 MC |
1623 | u16 vlan_proto = tpa_info->metadata >> |
1624 | RX_CMP_FLAGS2_METADATA_TPID_SFT; | |
ed7bc602 | 1625 | u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK; |
c0c050c5 | 1626 | |
8852ddb4 | 1627 | __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); |
c0c050c5 MC |
1628 | } |
1629 | ||
1630 | skb_checksum_none_assert(skb); | |
1631 | if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { | |
1632 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1633 | skb->csum_level = | |
1634 | (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; | |
1635 | } | |
1636 | ||
bfcd8d79 | 1637 | if (gro) |
309369c9 | 1638 | skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb); |
c0c050c5 MC |
1639 | |
1640 | return skb; | |
1641 | } | |
1642 | ||
8fe88ce7 MC |
1643 | static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, |
1644 | struct rx_agg_cmp *rx_agg) | |
1645 | { | |
1646 | u16 agg_id = TPA_AGG_AGG_ID(rx_agg); | |
1647 | struct bnxt_tpa_info *tpa_info; | |
1648 | ||
ec4d8e7c | 1649 | agg_id = bnxt_lookup_agg_idx(rxr, agg_id); |
8fe88ce7 MC |
1650 | tpa_info = &rxr->rx_tpa[agg_id]; |
1651 | BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS); | |
1652 | tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg; | |
1653 | } | |
1654 | ||
ee5c7fb3 SP |
1655 | static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi, |
1656 | struct sk_buff *skb) | |
1657 | { | |
1658 | if (skb->dev != bp->dev) { | |
1659 | /* this packet belongs to a vf-rep */ | |
1660 | bnxt_vf_rep_rx(bp, skb); | |
1661 | return; | |
1662 | } | |
1663 | skb_record_rx_queue(skb, bnapi->index); | |
1664 | napi_gro_receive(&bnapi->napi, skb); | |
1665 | } | |
1666 | ||
c0c050c5 MC |
1667 | /* returns the following: |
1668 | * 1 - 1 packet successfully received | |
1669 | * 0 - successful TPA_START, packet not completed yet | |
1670 | * -EBUSY - completion ring does not have all the agg buffers yet | |
1671 | * -ENOMEM - packet aborted due to out of memory | |
1672 | * -EIO - packet aborted due to hw error indicated in BD | |
1673 | */ | |
e44758b7 MC |
1674 | static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, |
1675 | u32 *raw_cons, u8 *event) | |
c0c050c5 | 1676 | { |
e44758b7 | 1677 | struct bnxt_napi *bnapi = cpr->bnapi; |
b6ab4b01 | 1678 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
c0c050c5 MC |
1679 | struct net_device *dev = bp->dev; |
1680 | struct rx_cmp *rxcmp; | |
1681 | struct rx_cmp_ext *rxcmp1; | |
1682 | u32 tmp_raw_cons = *raw_cons; | |
ee5c7fb3 | 1683 | u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons); |
c0c050c5 MC |
1684 | struct bnxt_sw_rx_bd *rx_buf; |
1685 | unsigned int len; | |
6bb19474 | 1686 | u8 *data_ptr, agg_bufs, cmp_type; |
c0c050c5 MC |
1687 | dma_addr_t dma_addr; |
1688 | struct sk_buff *skb; | |
6bb19474 | 1689 | void *data; |
c0c050c5 | 1690 | int rc = 0; |
c61fb99c | 1691 | u32 misc; |
c0c050c5 MC |
1692 | |
1693 | rxcmp = (struct rx_cmp *) | |
1694 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
1695 | ||
8fe88ce7 MC |
1696 | cmp_type = RX_CMP_TYPE(rxcmp); |
1697 | ||
1698 | if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) { | |
1699 | bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp); | |
1700 | goto next_rx_no_prod_no_len; | |
1701 | } | |
1702 | ||
c0c050c5 MC |
1703 | tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); |
1704 | cp_cons = RING_CMP(tmp_raw_cons); | |
1705 | rxcmp1 = (struct rx_cmp_ext *) | |
1706 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
1707 | ||
1708 | if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) | |
1709 | return -EBUSY; | |
1710 | ||
c0c050c5 MC |
1711 | prod = rxr->rx_prod; |
1712 | ||
1713 | if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { | |
1714 | bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, | |
1715 | (struct rx_tpa_start_cmp_ext *)rxcmp1); | |
1716 | ||
4e5dbbda | 1717 | *event |= BNXT_RX_EVENT; |
e7e70fa6 | 1718 | goto next_rx_no_prod_no_len; |
c0c050c5 MC |
1719 | |
1720 | } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { | |
e44758b7 | 1721 | skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons, |
c0c050c5 | 1722 | (struct rx_tpa_end_cmp *)rxcmp, |
4e5dbbda | 1723 | (struct rx_tpa_end_cmp_ext *)rxcmp1, event); |
c0c050c5 | 1724 | |
1fac4b2f | 1725 | if (IS_ERR(skb)) |
c0c050c5 MC |
1726 | return -EBUSY; |
1727 | ||
1728 | rc = -ENOMEM; | |
1729 | if (likely(skb)) { | |
ee5c7fb3 | 1730 | bnxt_deliver_skb(bp, bnapi, skb); |
c0c050c5 MC |
1731 | rc = 1; |
1732 | } | |
4e5dbbda | 1733 | *event |= BNXT_RX_EVENT; |
e7e70fa6 | 1734 | goto next_rx_no_prod_no_len; |
c0c050c5 MC |
1735 | } |
1736 | ||
1737 | cons = rxcmp->rx_cmp_opaque; | |
fa7e2812 | 1738 | if (unlikely(cons != rxr->rx_next_cons)) { |
e44758b7 | 1739 | int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp); |
fa7e2812 | 1740 | |
a1b0e4e6 MC |
1741 | netdev_warn(bp->dev, "RX cons %x != expected cons %x\n", |
1742 | cons, rxr->rx_next_cons); | |
fa7e2812 MC |
1743 | bnxt_sched_reset(bp, rxr); |
1744 | return rc1; | |
1745 | } | |
a1b0e4e6 MC |
1746 | rx_buf = &rxr->rx_buf_ring[cons]; |
1747 | data = rx_buf->data; | |
1748 | data_ptr = rx_buf->data_ptr; | |
6bb19474 | 1749 | prefetch(data_ptr); |
c0c050c5 | 1750 | |
c61fb99c MC |
1751 | misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1); |
1752 | agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT; | |
c0c050c5 MC |
1753 | |
1754 | if (agg_bufs) { | |
1755 | if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) | |
1756 | return -EBUSY; | |
1757 | ||
1758 | cp_cons = NEXT_CMP(cp_cons); | |
4e5dbbda | 1759 | *event |= BNXT_AGG_EVENT; |
c0c050c5 | 1760 | } |
4e5dbbda | 1761 | *event |= BNXT_RX_EVENT; |
c0c050c5 MC |
1762 | |
1763 | rx_buf->data = NULL; | |
1764 | if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { | |
8e44e96c MC |
1765 | u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2); |
1766 | ||
c0c050c5 MC |
1767 | bnxt_reuse_rx_data(rxr, cons, data); |
1768 | if (agg_bufs) | |
4a228a3a MC |
1769 | bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs, |
1770 | false); | |
c0c050c5 MC |
1771 | |
1772 | rc = -EIO; | |
8e44e96c | 1773 | if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) { |
9d8b5f05 | 1774 | bnapi->cp_ring.sw_stats.rx.rx_buf_errors++; |
19b3751f MC |
1775 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) { |
1776 | netdev_warn(bp->dev, "RX buffer error %x\n", | |
1777 | rx_err); | |
1778 | bnxt_sched_reset(bp, rxr); | |
1779 | } | |
8e44e96c | 1780 | } |
0b397b17 | 1781 | goto next_rx_no_len; |
c0c050c5 MC |
1782 | } |
1783 | ||
1784 | len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; | |
11cd119d | 1785 | dma_addr = rx_buf->mapping; |
c0c050c5 | 1786 | |
c6d30e83 MC |
1787 | if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) { |
1788 | rc = 1; | |
1789 | goto next_rx; | |
1790 | } | |
1791 | ||
c0c050c5 | 1792 | if (len <= bp->rx_copy_thresh) { |
6bb19474 | 1793 | skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr); |
c0c050c5 MC |
1794 | bnxt_reuse_rx_data(rxr, cons, data); |
1795 | if (!skb) { | |
296d5b54 | 1796 | if (agg_bufs) |
4a228a3a MC |
1797 | bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, |
1798 | agg_bufs, false); | |
c0c050c5 MC |
1799 | rc = -ENOMEM; |
1800 | goto next_rx; | |
1801 | } | |
1802 | } else { | |
c61fb99c MC |
1803 | u32 payload; |
1804 | ||
c6d30e83 MC |
1805 | if (rx_buf->data_ptr == data_ptr) |
1806 | payload = misc & RX_CMP_PAYLOAD_OFFSET; | |
1807 | else | |
1808 | payload = 0; | |
6bb19474 | 1809 | skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr, |
c61fb99c | 1810 | payload | len); |
c0c050c5 MC |
1811 | if (!skb) { |
1812 | rc = -ENOMEM; | |
1813 | goto next_rx; | |
1814 | } | |
1815 | } | |
1816 | ||
1817 | if (agg_bufs) { | |
4a228a3a | 1818 | skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs, false); |
c0c050c5 MC |
1819 | if (!skb) { |
1820 | rc = -ENOMEM; | |
1821 | goto next_rx; | |
1822 | } | |
1823 | } | |
1824 | ||
1825 | if (RX_CMP_HASH_VALID(rxcmp)) { | |
1826 | u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); | |
1827 | enum pkt_hash_types type = PKT_HASH_TYPE_L4; | |
1828 | ||
1829 | /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ | |
1830 | if (hash_type != 1 && hash_type != 3) | |
1831 | type = PKT_HASH_TYPE_L3; | |
1832 | skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); | |
1833 | } | |
1834 | ||
ee5c7fb3 SP |
1835 | cfa_code = RX_CMP_CFA_CODE(rxcmp1); |
1836 | skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code)); | |
c0c050c5 | 1837 | |
8852ddb4 MC |
1838 | if ((rxcmp1->rx_cmp_flags2 & |
1839 | cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) && | |
a196e96b | 1840 | (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) { |
c0c050c5 | 1841 | u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); |
ed7bc602 | 1842 | u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK; |
c0c050c5 MC |
1843 | u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT; |
1844 | ||
8852ddb4 | 1845 | __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); |
c0c050c5 MC |
1846 | } |
1847 | ||
1848 | skb_checksum_none_assert(skb); | |
1849 | if (RX_CMP_L4_CS_OK(rxcmp1)) { | |
1850 | if (dev->features & NETIF_F_RXCSUM) { | |
1851 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1852 | skb->csum_level = RX_CMP_ENCAP(rxcmp1); | |
1853 | } | |
1854 | } else { | |
665e350d SB |
1855 | if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { |
1856 | if (dev->features & NETIF_F_RXCSUM) | |
9d8b5f05 | 1857 | bnapi->cp_ring.sw_stats.rx.rx_l4_csum_errors++; |
665e350d | 1858 | } |
c0c050c5 MC |
1859 | } |
1860 | ||
ee5c7fb3 | 1861 | bnxt_deliver_skb(bp, bnapi, skb); |
c0c050c5 MC |
1862 | rc = 1; |
1863 | ||
1864 | next_rx: | |
6a8788f2 AG |
1865 | cpr->rx_packets += 1; |
1866 | cpr->rx_bytes += len; | |
e7e70fa6 | 1867 | |
0b397b17 MC |
1868 | next_rx_no_len: |
1869 | rxr->rx_prod = NEXT_RX(prod); | |
1870 | rxr->rx_next_cons = NEXT_RX(cons); | |
1871 | ||
e7e70fa6 | 1872 | next_rx_no_prod_no_len: |
c0c050c5 MC |
1873 | *raw_cons = tmp_raw_cons; |
1874 | ||
1875 | return rc; | |
1876 | } | |
1877 | ||
2270bc5d MC |
1878 | /* In netpoll mode, if we are using a combined completion ring, we need to |
1879 | * discard the rx packets and recycle the buffers. | |
1880 | */ | |
e44758b7 MC |
1881 | static int bnxt_force_rx_discard(struct bnxt *bp, |
1882 | struct bnxt_cp_ring_info *cpr, | |
2270bc5d MC |
1883 | u32 *raw_cons, u8 *event) |
1884 | { | |
2270bc5d MC |
1885 | u32 tmp_raw_cons = *raw_cons; |
1886 | struct rx_cmp_ext *rxcmp1; | |
1887 | struct rx_cmp *rxcmp; | |
1888 | u16 cp_cons; | |
1889 | u8 cmp_type; | |
1890 | ||
1891 | cp_cons = RING_CMP(tmp_raw_cons); | |
1892 | rxcmp = (struct rx_cmp *) | |
1893 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
1894 | ||
1895 | tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); | |
1896 | cp_cons = RING_CMP(tmp_raw_cons); | |
1897 | rxcmp1 = (struct rx_cmp_ext *) | |
1898 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
1899 | ||
1900 | if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) | |
1901 | return -EBUSY; | |
1902 | ||
1903 | cmp_type = RX_CMP_TYPE(rxcmp); | |
1904 | if (cmp_type == CMP_TYPE_RX_L2_CMP) { | |
1905 | rxcmp1->rx_cmp_cfa_code_errors_v2 |= | |
1906 | cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); | |
1907 | } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { | |
1908 | struct rx_tpa_end_cmp_ext *tpa_end1; | |
1909 | ||
1910 | tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1; | |
1911 | tpa_end1->rx_tpa_end_cmp_errors_v2 |= | |
1912 | cpu_to_le32(RX_TPA_END_CMP_ERRORS); | |
1913 | } | |
e44758b7 | 1914 | return bnxt_rx_pkt(bp, cpr, raw_cons, event); |
2270bc5d MC |
1915 | } |
1916 | ||
7e914027 MC |
1917 | u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx) |
1918 | { | |
1919 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
1920 | u32 reg = fw_health->regs[reg_idx]; | |
1921 | u32 reg_type, reg_off, val = 0; | |
1922 | ||
1923 | reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); | |
1924 | reg_off = BNXT_FW_HEALTH_REG_OFF(reg); | |
1925 | switch (reg_type) { | |
1926 | case BNXT_FW_HEALTH_REG_TYPE_CFG: | |
1927 | pci_read_config_dword(bp->pdev, reg_off, &val); | |
1928 | break; | |
1929 | case BNXT_FW_HEALTH_REG_TYPE_GRC: | |
1930 | reg_off = fw_health->mapped_regs[reg_idx]; | |
1931 | /* fall through */ | |
1932 | case BNXT_FW_HEALTH_REG_TYPE_BAR0: | |
1933 | val = readl(bp->bar0 + reg_off); | |
1934 | break; | |
1935 | case BNXT_FW_HEALTH_REG_TYPE_BAR1: | |
1936 | val = readl(bp->bar1 + reg_off); | |
1937 | break; | |
1938 | } | |
1939 | if (reg_idx == BNXT_FW_RESET_INPROG_REG) | |
1940 | val &= fw_health->fw_reset_inprog_reg_mask; | |
1941 | return val; | |
1942 | } | |
1943 | ||
4bb13abf | 1944 | #define BNXT_GET_EVENT_PORT(data) \ |
87c374de MC |
1945 | ((data) & \ |
1946 | ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK) | |
4bb13abf | 1947 | |
c0c050c5 MC |
1948 | static int bnxt_async_event_process(struct bnxt *bp, |
1949 | struct hwrm_async_event_cmpl *cmpl) | |
1950 | { | |
1951 | u16 event_id = le16_to_cpu(cmpl->event_id); | |
1952 | ||
1953 | /* TODO CHIMP_FW: Define event id's for link change, error etc */ | |
1954 | switch (event_id) { | |
87c374de | 1955 | case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: { |
8cbde117 MC |
1956 | u32 data1 = le32_to_cpu(cmpl->event_data1); |
1957 | struct bnxt_link_info *link_info = &bp->link_info; | |
1958 | ||
1959 | if (BNXT_VF(bp)) | |
1960 | goto async_event_process_exit; | |
a8168b6c MC |
1961 | |
1962 | /* print unsupported speed warning in forced speed mode only */ | |
1963 | if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) && | |
1964 | (data1 & 0x20000)) { | |
8cbde117 MC |
1965 | u16 fw_speed = link_info->force_link_speed; |
1966 | u32 speed = bnxt_fw_to_ethtool_speed(fw_speed); | |
1967 | ||
a8168b6c MC |
1968 | if (speed != SPEED_UNKNOWN) |
1969 | netdev_warn(bp->dev, "Link speed %d no longer supported\n", | |
1970 | speed); | |
8cbde117 | 1971 | } |
286ef9d6 | 1972 | set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event); |
8cbde117 | 1973 | } |
bc171e87 | 1974 | /* fall through */ |
b1613e78 MC |
1975 | case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE: |
1976 | case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE: | |
1977 | set_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, &bp->sp_event); | |
1978 | /* fall through */ | |
87c374de | 1979 | case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: |
c0c050c5 | 1980 | set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); |
19241368 | 1981 | break; |
87c374de | 1982 | case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: |
19241368 | 1983 | set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event); |
c0c050c5 | 1984 | break; |
87c374de | 1985 | case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: { |
4bb13abf MC |
1986 | u32 data1 = le32_to_cpu(cmpl->event_data1); |
1987 | u16 port_id = BNXT_GET_EVENT_PORT(data1); | |
1988 | ||
1989 | if (BNXT_VF(bp)) | |
1990 | break; | |
1991 | ||
1992 | if (bp->pf.port_id != port_id) | |
1993 | break; | |
1994 | ||
4bb13abf MC |
1995 | set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event); |
1996 | break; | |
1997 | } | |
87c374de | 1998 | case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: |
fc0f1929 MC |
1999 | if (BNXT_PF(bp)) |
2000 | goto async_event_process_exit; | |
2001 | set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event); | |
2002 | break; | |
acfb50e4 VV |
2003 | case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: { |
2004 | u32 data1 = le32_to_cpu(cmpl->event_data1); | |
2005 | ||
8280b38e VV |
2006 | if (!bp->fw_health) |
2007 | goto async_event_process_exit; | |
2008 | ||
2151fe08 MC |
2009 | bp->fw_reset_timestamp = jiffies; |
2010 | bp->fw_reset_min_dsecs = cmpl->timestamp_lo; | |
2011 | if (!bp->fw_reset_min_dsecs) | |
2012 | bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS; | |
2013 | bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi); | |
2014 | if (!bp->fw_reset_max_dsecs) | |
2015 | bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS; | |
acfb50e4 VV |
2016 | if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) { |
2017 | netdev_warn(bp->dev, "Firmware fatal reset event received\n"); | |
2018 | set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); | |
2019 | } else { | |
2020 | netdev_warn(bp->dev, "Firmware non-fatal reset event received, max wait time %d msec\n", | |
2021 | bp->fw_reset_max_dsecs * 100); | |
2022 | } | |
2151fe08 MC |
2023 | set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event); |
2024 | break; | |
acfb50e4 | 2025 | } |
7e914027 MC |
2026 | case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: { |
2027 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
2028 | u32 data1 = le32_to_cpu(cmpl->event_data1); | |
2029 | ||
2030 | if (!fw_health) | |
2031 | goto async_event_process_exit; | |
2032 | ||
2033 | fw_health->enabled = EVENT_DATA1_RECOVERY_ENABLED(data1); | |
2034 | fw_health->master = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1); | |
2035 | if (!fw_health->enabled) | |
2036 | break; | |
2037 | ||
2038 | if (netif_msg_drv(bp)) | |
2039 | netdev_info(bp->dev, "Error recovery info: error recovery[%d], master[%d], reset count[0x%x], health status: 0x%x\n", | |
2040 | fw_health->enabled, fw_health->master, | |
2041 | bnxt_fw_health_readl(bp, | |
2042 | BNXT_FW_RESET_CNT_REG), | |
2043 | bnxt_fw_health_readl(bp, | |
2044 | BNXT_FW_HEALTH_REG)); | |
2045 | fw_health->tmr_multiplier = | |
2046 | DIV_ROUND_UP(fw_health->polling_dsecs * HZ, | |
2047 | bp->current_interval * 10); | |
2048 | fw_health->tmr_counter = fw_health->tmr_multiplier; | |
2049 | fw_health->last_fw_heartbeat = | |
2050 | bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); | |
2051 | fw_health->last_fw_reset_cnt = | |
2052 | bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); | |
2053 | goto async_event_process_exit; | |
2054 | } | |
c0c050c5 | 2055 | default: |
19241368 | 2056 | goto async_event_process_exit; |
c0c050c5 | 2057 | } |
c213eae8 | 2058 | bnxt_queue_sp_work(bp); |
19241368 | 2059 | async_event_process_exit: |
a588e458 | 2060 | bnxt_ulp_async_events(bp, cmpl); |
c0c050c5 MC |
2061 | return 0; |
2062 | } | |
2063 | ||
2064 | static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) | |
2065 | { | |
2066 | u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; | |
2067 | struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; | |
2068 | struct hwrm_fwd_req_cmpl *fwd_req_cmpl = | |
2069 | (struct hwrm_fwd_req_cmpl *)txcmp; | |
2070 | ||
2071 | switch (cmpl_type) { | |
2072 | case CMPL_BASE_TYPE_HWRM_DONE: | |
2073 | seq_id = le16_to_cpu(h_cmpl->sequence_id); | |
2074 | if (seq_id == bp->hwrm_intr_seq_id) | |
fc718bb2 | 2075 | bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id; |
c0c050c5 MC |
2076 | else |
2077 | netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id); | |
2078 | break; | |
2079 | ||
2080 | case CMPL_BASE_TYPE_HWRM_FWD_REQ: | |
2081 | vf_id = le16_to_cpu(fwd_req_cmpl->source_id); | |
2082 | ||
2083 | if ((vf_id < bp->pf.first_vf_id) || | |
2084 | (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { | |
2085 | netdev_err(bp->dev, "Msg contains invalid VF id %x\n", | |
2086 | vf_id); | |
2087 | return -EINVAL; | |
2088 | } | |
2089 | ||
2090 | set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); | |
2091 | set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event); | |
c213eae8 | 2092 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
2093 | break; |
2094 | ||
2095 | case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: | |
2096 | bnxt_async_event_process(bp, | |
2097 | (struct hwrm_async_event_cmpl *)txcmp); | |
2098 | ||
2099 | default: | |
2100 | break; | |
2101 | } | |
2102 | ||
2103 | return 0; | |
2104 | } | |
2105 | ||
2106 | static irqreturn_t bnxt_msix(int irq, void *dev_instance) | |
2107 | { | |
2108 | struct bnxt_napi *bnapi = dev_instance; | |
2109 | struct bnxt *bp = bnapi->bp; | |
2110 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2111 | u32 cons = RING_CMP(cpr->cp_raw_cons); | |
2112 | ||
6a8788f2 | 2113 | cpr->event_ctr++; |
c0c050c5 MC |
2114 | prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); |
2115 | napi_schedule(&bnapi->napi); | |
2116 | return IRQ_HANDLED; | |
2117 | } | |
2118 | ||
2119 | static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) | |
2120 | { | |
2121 | u32 raw_cons = cpr->cp_raw_cons; | |
2122 | u16 cons = RING_CMP(raw_cons); | |
2123 | struct tx_cmp *txcmp; | |
2124 | ||
2125 | txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; | |
2126 | ||
2127 | return TX_CMP_VALID(txcmp, raw_cons); | |
2128 | } | |
2129 | ||
c0c050c5 MC |
2130 | static irqreturn_t bnxt_inta(int irq, void *dev_instance) |
2131 | { | |
2132 | struct bnxt_napi *bnapi = dev_instance; | |
2133 | struct bnxt *bp = bnapi->bp; | |
2134 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2135 | u32 cons = RING_CMP(cpr->cp_raw_cons); | |
2136 | u32 int_status; | |
2137 | ||
2138 | prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); | |
2139 | ||
2140 | if (!bnxt_has_work(bp, cpr)) { | |
11809490 | 2141 | int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); |
c0c050c5 MC |
2142 | /* return if erroneous interrupt */ |
2143 | if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) | |
2144 | return IRQ_NONE; | |
2145 | } | |
2146 | ||
2147 | /* disable ring IRQ */ | |
697197e5 | 2148 | BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell); |
c0c050c5 MC |
2149 | |
2150 | /* Return here if interrupt is shared and is disabled. */ | |
2151 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) | |
2152 | return IRQ_HANDLED; | |
2153 | ||
2154 | napi_schedule(&bnapi->napi); | |
2155 | return IRQ_HANDLED; | |
2156 | } | |
2157 | ||
3675b92f MC |
2158 | static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, |
2159 | int budget) | |
c0c050c5 | 2160 | { |
e44758b7 | 2161 | struct bnxt_napi *bnapi = cpr->bnapi; |
c0c050c5 MC |
2162 | u32 raw_cons = cpr->cp_raw_cons; |
2163 | u32 cons; | |
2164 | int tx_pkts = 0; | |
2165 | int rx_pkts = 0; | |
4e5dbbda | 2166 | u8 event = 0; |
c0c050c5 MC |
2167 | struct tx_cmp *txcmp; |
2168 | ||
0fcec985 | 2169 | cpr->has_more_work = 0; |
340ac85e | 2170 | cpr->had_work_done = 1; |
c0c050c5 MC |
2171 | while (1) { |
2172 | int rc; | |
2173 | ||
2174 | cons = RING_CMP(raw_cons); | |
2175 | txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; | |
2176 | ||
2177 | if (!TX_CMP_VALID(txcmp, raw_cons)) | |
2178 | break; | |
2179 | ||
67a95e20 MC |
2180 | /* The valid test of the entry must be done first before |
2181 | * reading any further. | |
2182 | */ | |
b67daab0 | 2183 | dma_rmb(); |
c0c050c5 MC |
2184 | if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { |
2185 | tx_pkts++; | |
2186 | /* return full budget so NAPI will complete. */ | |
73f21c65 | 2187 | if (unlikely(tx_pkts > bp->tx_wake_thresh)) { |
c0c050c5 | 2188 | rx_pkts = budget; |
73f21c65 | 2189 | raw_cons = NEXT_RAW_CMP(raw_cons); |
0fcec985 MC |
2190 | if (budget) |
2191 | cpr->has_more_work = 1; | |
73f21c65 MC |
2192 | break; |
2193 | } | |
c0c050c5 | 2194 | } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { |
2270bc5d | 2195 | if (likely(budget)) |
e44758b7 | 2196 | rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); |
2270bc5d | 2197 | else |
e44758b7 | 2198 | rc = bnxt_force_rx_discard(bp, cpr, &raw_cons, |
2270bc5d | 2199 | &event); |
c0c050c5 MC |
2200 | if (likely(rc >= 0)) |
2201 | rx_pkts += rc; | |
903649e7 MC |
2202 | /* Increment rx_pkts when rc is -ENOMEM to count towards |
2203 | * the NAPI budget. Otherwise, we may potentially loop | |
2204 | * here forever if we consistently cannot allocate | |
2205 | * buffers. | |
2206 | */ | |
2edbdb31 | 2207 | else if (rc == -ENOMEM && budget) |
903649e7 | 2208 | rx_pkts++; |
c0c050c5 MC |
2209 | else if (rc == -EBUSY) /* partial completion */ |
2210 | break; | |
c0c050c5 MC |
2211 | } else if (unlikely((TX_CMP_TYPE(txcmp) == |
2212 | CMPL_BASE_TYPE_HWRM_DONE) || | |
2213 | (TX_CMP_TYPE(txcmp) == | |
2214 | CMPL_BASE_TYPE_HWRM_FWD_REQ) || | |
2215 | (TX_CMP_TYPE(txcmp) == | |
2216 | CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { | |
2217 | bnxt_hwrm_handler(bp, txcmp); | |
2218 | } | |
2219 | raw_cons = NEXT_RAW_CMP(raw_cons); | |
2220 | ||
0fcec985 MC |
2221 | if (rx_pkts && rx_pkts == budget) { |
2222 | cpr->has_more_work = 1; | |
c0c050c5 | 2223 | break; |
0fcec985 | 2224 | } |
c0c050c5 MC |
2225 | } |
2226 | ||
f18c2b77 AG |
2227 | if (event & BNXT_REDIRECT_EVENT) |
2228 | xdp_do_flush_map(); | |
2229 | ||
38413406 MC |
2230 | if (event & BNXT_TX_EVENT) { |
2231 | struct bnxt_tx_ring_info *txr = bnapi->tx_ring; | |
38413406 MC |
2232 | u16 prod = txr->tx_prod; |
2233 | ||
2234 | /* Sync BD data before updating doorbell */ | |
2235 | wmb(); | |
2236 | ||
697197e5 | 2237 | bnxt_db_write_relaxed(bp, &txr->tx_db, prod); |
38413406 MC |
2238 | } |
2239 | ||
c0c050c5 | 2240 | cpr->cp_raw_cons = raw_cons; |
3675b92f MC |
2241 | bnapi->tx_pkts += tx_pkts; |
2242 | bnapi->events |= event; | |
2243 | return rx_pkts; | |
2244 | } | |
c0c050c5 | 2245 | |
3675b92f MC |
2246 | static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi) |
2247 | { | |
2248 | if (bnapi->tx_pkts) { | |
2249 | bnapi->tx_int(bp, bnapi, bnapi->tx_pkts); | |
2250 | bnapi->tx_pkts = 0; | |
2251 | } | |
c0c050c5 | 2252 | |
3675b92f | 2253 | if (bnapi->events & BNXT_RX_EVENT) { |
b6ab4b01 | 2254 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
c0c050c5 | 2255 | |
3675b92f | 2256 | if (bnapi->events & BNXT_AGG_EVENT) |
697197e5 | 2257 | bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); |
e8f267b0 | 2258 | bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); |
c0c050c5 | 2259 | } |
3675b92f MC |
2260 | bnapi->events = 0; |
2261 | } | |
2262 | ||
2263 | static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, | |
2264 | int budget) | |
2265 | { | |
2266 | struct bnxt_napi *bnapi = cpr->bnapi; | |
2267 | int rx_pkts; | |
2268 | ||
2269 | rx_pkts = __bnxt_poll_work(bp, cpr, budget); | |
2270 | ||
2271 | /* ACK completion ring before freeing tx ring and producing new | |
2272 | * buffers in rx/agg rings to prevent overflowing the completion | |
2273 | * ring. | |
2274 | */ | |
2275 | bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons); | |
2276 | ||
2277 | __bnxt_poll_work_done(bp, bnapi); | |
c0c050c5 MC |
2278 | return rx_pkts; |
2279 | } | |
2280 | ||
10bbdaf5 PS |
2281 | static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) |
2282 | { | |
2283 | struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); | |
2284 | struct bnxt *bp = bnapi->bp; | |
2285 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2286 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; | |
2287 | struct tx_cmp *txcmp; | |
2288 | struct rx_cmp_ext *rxcmp1; | |
2289 | u32 cp_cons, tmp_raw_cons; | |
2290 | u32 raw_cons = cpr->cp_raw_cons; | |
2291 | u32 rx_pkts = 0; | |
4e5dbbda | 2292 | u8 event = 0; |
10bbdaf5 PS |
2293 | |
2294 | while (1) { | |
2295 | int rc; | |
2296 | ||
2297 | cp_cons = RING_CMP(raw_cons); | |
2298 | txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
2299 | ||
2300 | if (!TX_CMP_VALID(txcmp, raw_cons)) | |
2301 | break; | |
2302 | ||
2303 | if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { | |
2304 | tmp_raw_cons = NEXT_RAW_CMP(raw_cons); | |
2305 | cp_cons = RING_CMP(tmp_raw_cons); | |
2306 | rxcmp1 = (struct rx_cmp_ext *) | |
2307 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
2308 | ||
2309 | if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) | |
2310 | break; | |
2311 | ||
2312 | /* force an error to recycle the buffer */ | |
2313 | rxcmp1->rx_cmp_cfa_code_errors_v2 |= | |
2314 | cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); | |
2315 | ||
e44758b7 | 2316 | rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); |
2edbdb31 | 2317 | if (likely(rc == -EIO) && budget) |
10bbdaf5 PS |
2318 | rx_pkts++; |
2319 | else if (rc == -EBUSY) /* partial completion */ | |
2320 | break; | |
2321 | } else if (unlikely(TX_CMP_TYPE(txcmp) == | |
2322 | CMPL_BASE_TYPE_HWRM_DONE)) { | |
2323 | bnxt_hwrm_handler(bp, txcmp); | |
2324 | } else { | |
2325 | netdev_err(bp->dev, | |
2326 | "Invalid completion received on special ring\n"); | |
2327 | } | |
2328 | raw_cons = NEXT_RAW_CMP(raw_cons); | |
2329 | ||
2330 | if (rx_pkts == budget) | |
2331 | break; | |
2332 | } | |
2333 | ||
2334 | cpr->cp_raw_cons = raw_cons; | |
697197e5 MC |
2335 | BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons); |
2336 | bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); | |
10bbdaf5 | 2337 | |
434c975a | 2338 | if (event & BNXT_AGG_EVENT) |
697197e5 | 2339 | bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); |
10bbdaf5 PS |
2340 | |
2341 | if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) { | |
6ad20165 | 2342 | napi_complete_done(napi, rx_pkts); |
697197e5 | 2343 | BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); |
10bbdaf5 PS |
2344 | } |
2345 | return rx_pkts; | |
2346 | } | |
2347 | ||
c0c050c5 MC |
2348 | static int bnxt_poll(struct napi_struct *napi, int budget) |
2349 | { | |
2350 | struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); | |
2351 | struct bnxt *bp = bnapi->bp; | |
2352 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2353 | int work_done = 0; | |
2354 | ||
c0c050c5 | 2355 | while (1) { |
e44758b7 | 2356 | work_done += bnxt_poll_work(bp, cpr, budget - work_done); |
c0c050c5 | 2357 | |
73f21c65 MC |
2358 | if (work_done >= budget) { |
2359 | if (!budget) | |
697197e5 | 2360 | BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); |
c0c050c5 | 2361 | break; |
73f21c65 | 2362 | } |
c0c050c5 MC |
2363 | |
2364 | if (!bnxt_has_work(bp, cpr)) { | |
e7b95691 | 2365 | if (napi_complete_done(napi, work_done)) |
697197e5 | 2366 | BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); |
c0c050c5 MC |
2367 | break; |
2368 | } | |
2369 | } | |
6a8788f2 | 2370 | if (bp->flags & BNXT_FLAG_DIM) { |
f06d0ca4 | 2371 | struct dim_sample dim_sample = {}; |
6a8788f2 | 2372 | |
8960b389 TG |
2373 | dim_update_sample(cpr->event_ctr, |
2374 | cpr->rx_packets, | |
2375 | cpr->rx_bytes, | |
2376 | &dim_sample); | |
6a8788f2 AG |
2377 | net_dim(&cpr->dim, dim_sample); |
2378 | } | |
c0c050c5 MC |
2379 | return work_done; |
2380 | } | |
2381 | ||
0fcec985 MC |
2382 | static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) |
2383 | { | |
2384 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2385 | int i, work_done = 0; | |
2386 | ||
2387 | for (i = 0; i < 2; i++) { | |
2388 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; | |
2389 | ||
2390 | if (cpr2) { | |
2391 | work_done += __bnxt_poll_work(bp, cpr2, | |
2392 | budget - work_done); | |
2393 | cpr->has_more_work |= cpr2->has_more_work; | |
2394 | } | |
2395 | } | |
2396 | return work_done; | |
2397 | } | |
2398 | ||
2399 | static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi, | |
340ac85e | 2400 | u64 dbr_type) |
0fcec985 MC |
2401 | { |
2402 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2403 | int i; | |
2404 | ||
2405 | for (i = 0; i < 2; i++) { | |
2406 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; | |
2407 | struct bnxt_db_info *db; | |
2408 | ||
340ac85e | 2409 | if (cpr2 && cpr2->had_work_done) { |
0fcec985 MC |
2410 | db = &cpr2->cp_db; |
2411 | writeq(db->db_key64 | dbr_type | | |
2412 | RING_CMP(cpr2->cp_raw_cons), db->doorbell); | |
2413 | cpr2->had_work_done = 0; | |
2414 | } | |
2415 | } | |
2416 | __bnxt_poll_work_done(bp, bnapi); | |
2417 | } | |
2418 | ||
2419 | static int bnxt_poll_p5(struct napi_struct *napi, int budget) | |
2420 | { | |
2421 | struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); | |
2422 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2423 | u32 raw_cons = cpr->cp_raw_cons; | |
2424 | struct bnxt *bp = bnapi->bp; | |
2425 | struct nqe_cn *nqcmp; | |
2426 | int work_done = 0; | |
2427 | u32 cons; | |
2428 | ||
2429 | if (cpr->has_more_work) { | |
2430 | cpr->has_more_work = 0; | |
2431 | work_done = __bnxt_poll_cqs(bp, bnapi, budget); | |
0fcec985 MC |
2432 | } |
2433 | while (1) { | |
2434 | cons = RING_CMP(raw_cons); | |
2435 | nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)]; | |
2436 | ||
2437 | if (!NQ_CMP_VALID(nqcmp, raw_cons)) { | |
54a9062f MC |
2438 | if (cpr->has_more_work) |
2439 | break; | |
2440 | ||
340ac85e | 2441 | __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL); |
0fcec985 MC |
2442 | cpr->cp_raw_cons = raw_cons; |
2443 | if (napi_complete_done(napi, work_done)) | |
2444 | BNXT_DB_NQ_ARM_P5(&cpr->cp_db, | |
2445 | cpr->cp_raw_cons); | |
2446 | return work_done; | |
2447 | } | |
2448 | ||
2449 | /* The valid test of the entry must be done first before | |
2450 | * reading any further. | |
2451 | */ | |
2452 | dma_rmb(); | |
2453 | ||
2454 | if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) { | |
2455 | u32 idx = le32_to_cpu(nqcmp->cq_handle_low); | |
2456 | struct bnxt_cp_ring_info *cpr2; | |
2457 | ||
2458 | cpr2 = cpr->cp_ring_arr[idx]; | |
2459 | work_done += __bnxt_poll_work(bp, cpr2, | |
2460 | budget - work_done); | |
54a9062f | 2461 | cpr->has_more_work |= cpr2->has_more_work; |
0fcec985 MC |
2462 | } else { |
2463 | bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp); | |
2464 | } | |
2465 | raw_cons = NEXT_RAW_CMP(raw_cons); | |
0fcec985 | 2466 | } |
340ac85e | 2467 | __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ); |
389a877a MC |
2468 | if (raw_cons != cpr->cp_raw_cons) { |
2469 | cpr->cp_raw_cons = raw_cons; | |
2470 | BNXT_DB_NQ_P5(&cpr->cp_db, raw_cons); | |
2471 | } | |
0fcec985 MC |
2472 | return work_done; |
2473 | } | |
2474 | ||
c0c050c5 MC |
2475 | static void bnxt_free_tx_skbs(struct bnxt *bp) |
2476 | { | |
2477 | int i, max_idx; | |
2478 | struct pci_dev *pdev = bp->pdev; | |
2479 | ||
b6ab4b01 | 2480 | if (!bp->tx_ring) |
c0c050c5 MC |
2481 | return; |
2482 | ||
2483 | max_idx = bp->tx_nr_pages * TX_DESC_CNT; | |
2484 | for (i = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 2485 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
c0c050c5 MC |
2486 | int j; |
2487 | ||
c0c050c5 MC |
2488 | for (j = 0; j < max_idx;) { |
2489 | struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; | |
f18c2b77 | 2490 | struct sk_buff *skb; |
c0c050c5 MC |
2491 | int k, last; |
2492 | ||
f18c2b77 AG |
2493 | if (i < bp->tx_nr_rings_xdp && |
2494 | tx_buf->action == XDP_REDIRECT) { | |
2495 | dma_unmap_single(&pdev->dev, | |
2496 | dma_unmap_addr(tx_buf, mapping), | |
2497 | dma_unmap_len(tx_buf, len), | |
2498 | PCI_DMA_TODEVICE); | |
2499 | xdp_return_frame(tx_buf->xdpf); | |
2500 | tx_buf->action = 0; | |
2501 | tx_buf->xdpf = NULL; | |
2502 | j++; | |
2503 | continue; | |
2504 | } | |
2505 | ||
2506 | skb = tx_buf->skb; | |
c0c050c5 MC |
2507 | if (!skb) { |
2508 | j++; | |
2509 | continue; | |
2510 | } | |
2511 | ||
2512 | tx_buf->skb = NULL; | |
2513 | ||
2514 | if (tx_buf->is_push) { | |
2515 | dev_kfree_skb(skb); | |
2516 | j += 2; | |
2517 | continue; | |
2518 | } | |
2519 | ||
2520 | dma_unmap_single(&pdev->dev, | |
2521 | dma_unmap_addr(tx_buf, mapping), | |
2522 | skb_headlen(skb), | |
2523 | PCI_DMA_TODEVICE); | |
2524 | ||
2525 | last = tx_buf->nr_frags; | |
2526 | j += 2; | |
d612a579 MC |
2527 | for (k = 0; k < last; k++, j++) { |
2528 | int ring_idx = j & bp->tx_ring_mask; | |
c0c050c5 MC |
2529 | skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; |
2530 | ||
d612a579 | 2531 | tx_buf = &txr->tx_buf_ring[ring_idx]; |
c0c050c5 MC |
2532 | dma_unmap_page( |
2533 | &pdev->dev, | |
2534 | dma_unmap_addr(tx_buf, mapping), | |
2535 | skb_frag_size(frag), PCI_DMA_TODEVICE); | |
2536 | } | |
2537 | dev_kfree_skb(skb); | |
2538 | } | |
2539 | netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); | |
2540 | } | |
2541 | } | |
2542 | ||
2543 | static void bnxt_free_rx_skbs(struct bnxt *bp) | |
2544 | { | |
2545 | int i, max_idx, max_agg_idx; | |
2546 | struct pci_dev *pdev = bp->pdev; | |
2547 | ||
b6ab4b01 | 2548 | if (!bp->rx_ring) |
c0c050c5 MC |
2549 | return; |
2550 | ||
2551 | max_idx = bp->rx_nr_pages * RX_DESC_CNT; | |
2552 | max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; | |
2553 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
b6ab4b01 | 2554 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
ec4d8e7c | 2555 | struct bnxt_tpa_idx_map *map; |
c0c050c5 MC |
2556 | int j; |
2557 | ||
c0c050c5 | 2558 | if (rxr->rx_tpa) { |
79632e9b | 2559 | for (j = 0; j < bp->max_tpa; j++) { |
c0c050c5 MC |
2560 | struct bnxt_tpa_info *tpa_info = |
2561 | &rxr->rx_tpa[j]; | |
2562 | u8 *data = tpa_info->data; | |
2563 | ||
2564 | if (!data) | |
2565 | continue; | |
2566 | ||
c519fe9a SN |
2567 | dma_unmap_single_attrs(&pdev->dev, |
2568 | tpa_info->mapping, | |
2569 | bp->rx_buf_use_size, | |
2570 | bp->rx_dir, | |
2571 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
2572 | |
2573 | tpa_info->data = NULL; | |
2574 | ||
2575 | kfree(data); | |
2576 | } | |
2577 | } | |
2578 | ||
2579 | for (j = 0; j < max_idx; j++) { | |
2580 | struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j]; | |
3ed3a83e | 2581 | dma_addr_t mapping = rx_buf->mapping; |
6bb19474 | 2582 | void *data = rx_buf->data; |
c0c050c5 MC |
2583 | |
2584 | if (!data) | |
2585 | continue; | |
2586 | ||
c0c050c5 MC |
2587 | rx_buf->data = NULL; |
2588 | ||
3ed3a83e MC |
2589 | if (BNXT_RX_PAGE_MODE(bp)) { |
2590 | mapping -= bp->rx_dma_offset; | |
c519fe9a SN |
2591 | dma_unmap_page_attrs(&pdev->dev, mapping, |
2592 | PAGE_SIZE, bp->rx_dir, | |
2593 | DMA_ATTR_WEAK_ORDERING); | |
322b87ca | 2594 | page_pool_recycle_direct(rxr->page_pool, data); |
3ed3a83e | 2595 | } else { |
c519fe9a SN |
2596 | dma_unmap_single_attrs(&pdev->dev, mapping, |
2597 | bp->rx_buf_use_size, | |
2598 | bp->rx_dir, | |
2599 | DMA_ATTR_WEAK_ORDERING); | |
c61fb99c | 2600 | kfree(data); |
3ed3a83e | 2601 | } |
c0c050c5 MC |
2602 | } |
2603 | ||
2604 | for (j = 0; j < max_agg_idx; j++) { | |
2605 | struct bnxt_sw_rx_agg_bd *rx_agg_buf = | |
2606 | &rxr->rx_agg_ring[j]; | |
2607 | struct page *page = rx_agg_buf->page; | |
2608 | ||
2609 | if (!page) | |
2610 | continue; | |
2611 | ||
c519fe9a SN |
2612 | dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping, |
2613 | BNXT_RX_PAGE_SIZE, | |
2614 | PCI_DMA_FROMDEVICE, | |
2615 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
2616 | |
2617 | rx_agg_buf->page = NULL; | |
2618 | __clear_bit(j, rxr->rx_agg_bmap); | |
2619 | ||
2620 | __free_page(page); | |
2621 | } | |
89d0a06c MC |
2622 | if (rxr->rx_page) { |
2623 | __free_page(rxr->rx_page); | |
2624 | rxr->rx_page = NULL; | |
2625 | } | |
ec4d8e7c MC |
2626 | map = rxr->rx_tpa_idx_map; |
2627 | if (map) | |
2628 | memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap)); | |
c0c050c5 MC |
2629 | } |
2630 | } | |
2631 | ||
2632 | static void bnxt_free_skbs(struct bnxt *bp) | |
2633 | { | |
2634 | bnxt_free_tx_skbs(bp); | |
2635 | bnxt_free_rx_skbs(bp); | |
2636 | } | |
2637 | ||
6fe19886 | 2638 | static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) |
c0c050c5 MC |
2639 | { |
2640 | struct pci_dev *pdev = bp->pdev; | |
2641 | int i; | |
2642 | ||
6fe19886 MC |
2643 | for (i = 0; i < rmem->nr_pages; i++) { |
2644 | if (!rmem->pg_arr[i]) | |
c0c050c5 MC |
2645 | continue; |
2646 | ||
6fe19886 MC |
2647 | dma_free_coherent(&pdev->dev, rmem->page_size, |
2648 | rmem->pg_arr[i], rmem->dma_arr[i]); | |
c0c050c5 | 2649 | |
6fe19886 | 2650 | rmem->pg_arr[i] = NULL; |
c0c050c5 | 2651 | } |
6fe19886 | 2652 | if (rmem->pg_tbl) { |
4f49b2b8 MC |
2653 | size_t pg_tbl_size = rmem->nr_pages * 8; |
2654 | ||
2655 | if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) | |
2656 | pg_tbl_size = rmem->page_size; | |
2657 | dma_free_coherent(&pdev->dev, pg_tbl_size, | |
6fe19886 MC |
2658 | rmem->pg_tbl, rmem->pg_tbl_map); |
2659 | rmem->pg_tbl = NULL; | |
c0c050c5 | 2660 | } |
6fe19886 MC |
2661 | if (rmem->vmem_size && *rmem->vmem) { |
2662 | vfree(*rmem->vmem); | |
2663 | *rmem->vmem = NULL; | |
c0c050c5 MC |
2664 | } |
2665 | } | |
2666 | ||
6fe19886 | 2667 | static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) |
c0c050c5 | 2668 | { |
c0c050c5 | 2669 | struct pci_dev *pdev = bp->pdev; |
66cca20a | 2670 | u64 valid_bit = 0; |
6fe19886 | 2671 | int i; |
c0c050c5 | 2672 | |
66cca20a MC |
2673 | if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG)) |
2674 | valid_bit = PTU_PTE_VALID; | |
4f49b2b8 MC |
2675 | if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) { |
2676 | size_t pg_tbl_size = rmem->nr_pages * 8; | |
2677 | ||
2678 | if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) | |
2679 | pg_tbl_size = rmem->page_size; | |
2680 | rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size, | |
6fe19886 | 2681 | &rmem->pg_tbl_map, |
c0c050c5 | 2682 | GFP_KERNEL); |
6fe19886 | 2683 | if (!rmem->pg_tbl) |
c0c050c5 MC |
2684 | return -ENOMEM; |
2685 | } | |
2686 | ||
6fe19886 | 2687 | for (i = 0; i < rmem->nr_pages; i++) { |
66cca20a MC |
2688 | u64 extra_bits = valid_bit; |
2689 | ||
6fe19886 MC |
2690 | rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev, |
2691 | rmem->page_size, | |
2692 | &rmem->dma_arr[i], | |
c0c050c5 | 2693 | GFP_KERNEL); |
6fe19886 | 2694 | if (!rmem->pg_arr[i]) |
c0c050c5 MC |
2695 | return -ENOMEM; |
2696 | ||
3be8136c MC |
2697 | if (rmem->init_val) |
2698 | memset(rmem->pg_arr[i], rmem->init_val, | |
2699 | rmem->page_size); | |
4f49b2b8 | 2700 | if (rmem->nr_pages > 1 || rmem->depth > 0) { |
66cca20a MC |
2701 | if (i == rmem->nr_pages - 2 && |
2702 | (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) | |
2703 | extra_bits |= PTU_PTE_NEXT_TO_LAST; | |
2704 | else if (i == rmem->nr_pages - 1 && | |
2705 | (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) | |
2706 | extra_bits |= PTU_PTE_LAST; | |
2707 | rmem->pg_tbl[i] = | |
2708 | cpu_to_le64(rmem->dma_arr[i] | extra_bits); | |
2709 | } | |
c0c050c5 MC |
2710 | } |
2711 | ||
6fe19886 MC |
2712 | if (rmem->vmem_size) { |
2713 | *rmem->vmem = vzalloc(rmem->vmem_size); | |
2714 | if (!(*rmem->vmem)) | |
c0c050c5 MC |
2715 | return -ENOMEM; |
2716 | } | |
2717 | return 0; | |
2718 | } | |
2719 | ||
4a228a3a MC |
2720 | static void bnxt_free_tpa_info(struct bnxt *bp) |
2721 | { | |
2722 | int i; | |
2723 | ||
2724 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
2725 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; | |
2726 | ||
ec4d8e7c MC |
2727 | kfree(rxr->rx_tpa_idx_map); |
2728 | rxr->rx_tpa_idx_map = NULL; | |
79632e9b MC |
2729 | if (rxr->rx_tpa) { |
2730 | kfree(rxr->rx_tpa[0].agg_arr); | |
2731 | rxr->rx_tpa[0].agg_arr = NULL; | |
2732 | } | |
4a228a3a MC |
2733 | kfree(rxr->rx_tpa); |
2734 | rxr->rx_tpa = NULL; | |
2735 | } | |
2736 | } | |
2737 | ||
2738 | static int bnxt_alloc_tpa_info(struct bnxt *bp) | |
2739 | { | |
79632e9b MC |
2740 | int i, j, total_aggs = 0; |
2741 | ||
2742 | bp->max_tpa = MAX_TPA; | |
2743 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
2744 | if (!bp->max_tpa_v2) | |
2745 | return 0; | |
2746 | bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5); | |
2747 | total_aggs = bp->max_tpa * MAX_SKB_FRAGS; | |
2748 | } | |
4a228a3a MC |
2749 | |
2750 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
2751 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; | |
79632e9b | 2752 | struct rx_agg_cmp *agg; |
4a228a3a | 2753 | |
79632e9b | 2754 | rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info), |
4a228a3a MC |
2755 | GFP_KERNEL); |
2756 | if (!rxr->rx_tpa) | |
2757 | return -ENOMEM; | |
79632e9b MC |
2758 | |
2759 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
2760 | continue; | |
2761 | agg = kcalloc(total_aggs, sizeof(*agg), GFP_KERNEL); | |
2762 | rxr->rx_tpa[0].agg_arr = agg; | |
2763 | if (!agg) | |
2764 | return -ENOMEM; | |
2765 | for (j = 1; j < bp->max_tpa; j++) | |
2766 | rxr->rx_tpa[j].agg_arr = agg + j * MAX_SKB_FRAGS; | |
ec4d8e7c MC |
2767 | rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map), |
2768 | GFP_KERNEL); | |
2769 | if (!rxr->rx_tpa_idx_map) | |
2770 | return -ENOMEM; | |
4a228a3a MC |
2771 | } |
2772 | return 0; | |
2773 | } | |
2774 | ||
c0c050c5 MC |
2775 | static void bnxt_free_rx_rings(struct bnxt *bp) |
2776 | { | |
2777 | int i; | |
2778 | ||
b6ab4b01 | 2779 | if (!bp->rx_ring) |
c0c050c5 MC |
2780 | return; |
2781 | ||
4a228a3a | 2782 | bnxt_free_tpa_info(bp); |
c0c050c5 | 2783 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 2784 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
c0c050c5 MC |
2785 | struct bnxt_ring_struct *ring; |
2786 | ||
c6d30e83 MC |
2787 | if (rxr->xdp_prog) |
2788 | bpf_prog_put(rxr->xdp_prog); | |
2789 | ||
96a8604f JDB |
2790 | if (xdp_rxq_info_is_reg(&rxr->xdp_rxq)) |
2791 | xdp_rxq_info_unreg(&rxr->xdp_rxq); | |
2792 | ||
12479f62 | 2793 | page_pool_destroy(rxr->page_pool); |
322b87ca AG |
2794 | rxr->page_pool = NULL; |
2795 | ||
c0c050c5 MC |
2796 | kfree(rxr->rx_agg_bmap); |
2797 | rxr->rx_agg_bmap = NULL; | |
2798 | ||
2799 | ring = &rxr->rx_ring_struct; | |
6fe19886 | 2800 | bnxt_free_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2801 | |
2802 | ring = &rxr->rx_agg_ring_struct; | |
6fe19886 | 2803 | bnxt_free_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2804 | } |
2805 | } | |
2806 | ||
322b87ca AG |
2807 | static int bnxt_alloc_rx_page_pool(struct bnxt *bp, |
2808 | struct bnxt_rx_ring_info *rxr) | |
2809 | { | |
2810 | struct page_pool_params pp = { 0 }; | |
2811 | ||
2812 | pp.pool_size = bp->rx_ring_size; | |
2813 | pp.nid = dev_to_node(&bp->pdev->dev); | |
2814 | pp.dev = &bp->pdev->dev; | |
2815 | pp.dma_dir = DMA_BIDIRECTIONAL; | |
2816 | ||
2817 | rxr->page_pool = page_pool_create(&pp); | |
2818 | if (IS_ERR(rxr->page_pool)) { | |
2819 | int err = PTR_ERR(rxr->page_pool); | |
2820 | ||
2821 | rxr->page_pool = NULL; | |
2822 | return err; | |
2823 | } | |
2824 | return 0; | |
2825 | } | |
2826 | ||
c0c050c5 MC |
2827 | static int bnxt_alloc_rx_rings(struct bnxt *bp) |
2828 | { | |
4a228a3a | 2829 | int i, rc = 0, agg_rings = 0; |
c0c050c5 | 2830 | |
b6ab4b01 MC |
2831 | if (!bp->rx_ring) |
2832 | return -ENOMEM; | |
2833 | ||
c0c050c5 MC |
2834 | if (bp->flags & BNXT_FLAG_AGG_RINGS) |
2835 | agg_rings = 1; | |
2836 | ||
c0c050c5 | 2837 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 2838 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
c0c050c5 MC |
2839 | struct bnxt_ring_struct *ring; |
2840 | ||
c0c050c5 MC |
2841 | ring = &rxr->rx_ring_struct; |
2842 | ||
322b87ca AG |
2843 | rc = bnxt_alloc_rx_page_pool(bp, rxr); |
2844 | if (rc) | |
2845 | return rc; | |
2846 | ||
96a8604f | 2847 | rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i); |
12479f62 | 2848 | if (rc < 0) |
96a8604f JDB |
2849 | return rc; |
2850 | ||
f18c2b77 | 2851 | rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq, |
322b87ca AG |
2852 | MEM_TYPE_PAGE_POOL, |
2853 | rxr->page_pool); | |
f18c2b77 AG |
2854 | if (rc) { |
2855 | xdp_rxq_info_unreg(&rxr->xdp_rxq); | |
2856 | return rc; | |
2857 | } | |
2858 | ||
6fe19886 | 2859 | rc = bnxt_alloc_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2860 | if (rc) |
2861 | return rc; | |
2862 | ||
2c61d211 | 2863 | ring->grp_idx = i; |
c0c050c5 MC |
2864 | if (agg_rings) { |
2865 | u16 mem_size; | |
2866 | ||
2867 | ring = &rxr->rx_agg_ring_struct; | |
6fe19886 | 2868 | rc = bnxt_alloc_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2869 | if (rc) |
2870 | return rc; | |
2871 | ||
9899bb59 | 2872 | ring->grp_idx = i; |
c0c050c5 MC |
2873 | rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; |
2874 | mem_size = rxr->rx_agg_bmap_size / 8; | |
2875 | rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); | |
2876 | if (!rxr->rx_agg_bmap) | |
2877 | return -ENOMEM; | |
c0c050c5 MC |
2878 | } |
2879 | } | |
4a228a3a MC |
2880 | if (bp->flags & BNXT_FLAG_TPA) |
2881 | rc = bnxt_alloc_tpa_info(bp); | |
2882 | return rc; | |
c0c050c5 MC |
2883 | } |
2884 | ||
2885 | static void bnxt_free_tx_rings(struct bnxt *bp) | |
2886 | { | |
2887 | int i; | |
2888 | struct pci_dev *pdev = bp->pdev; | |
2889 | ||
b6ab4b01 | 2890 | if (!bp->tx_ring) |
c0c050c5 MC |
2891 | return; |
2892 | ||
2893 | for (i = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 2894 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
c0c050c5 MC |
2895 | struct bnxt_ring_struct *ring; |
2896 | ||
c0c050c5 MC |
2897 | if (txr->tx_push) { |
2898 | dma_free_coherent(&pdev->dev, bp->tx_push_size, | |
2899 | txr->tx_push, txr->tx_push_mapping); | |
2900 | txr->tx_push = NULL; | |
2901 | } | |
2902 | ||
2903 | ring = &txr->tx_ring_struct; | |
2904 | ||
6fe19886 | 2905 | bnxt_free_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2906 | } |
2907 | } | |
2908 | ||
2909 | static int bnxt_alloc_tx_rings(struct bnxt *bp) | |
2910 | { | |
2911 | int i, j, rc; | |
2912 | struct pci_dev *pdev = bp->pdev; | |
2913 | ||
2914 | bp->tx_push_size = 0; | |
2915 | if (bp->tx_push_thresh) { | |
2916 | int push_size; | |
2917 | ||
2918 | push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + | |
2919 | bp->tx_push_thresh); | |
2920 | ||
4419dbe6 | 2921 | if (push_size > 256) { |
c0c050c5 MC |
2922 | push_size = 0; |
2923 | bp->tx_push_thresh = 0; | |
2924 | } | |
2925 | ||
2926 | bp->tx_push_size = push_size; | |
2927 | } | |
2928 | ||
2929 | for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 2930 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
c0c050c5 | 2931 | struct bnxt_ring_struct *ring; |
2e8ef77e | 2932 | u8 qidx; |
c0c050c5 | 2933 | |
c0c050c5 MC |
2934 | ring = &txr->tx_ring_struct; |
2935 | ||
6fe19886 | 2936 | rc = bnxt_alloc_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2937 | if (rc) |
2938 | return rc; | |
2939 | ||
9899bb59 | 2940 | ring->grp_idx = txr->bnapi->index; |
c0c050c5 | 2941 | if (bp->tx_push_size) { |
c0c050c5 MC |
2942 | dma_addr_t mapping; |
2943 | ||
2944 | /* One pre-allocated DMA buffer to backup | |
2945 | * TX push operation | |
2946 | */ | |
2947 | txr->tx_push = dma_alloc_coherent(&pdev->dev, | |
2948 | bp->tx_push_size, | |
2949 | &txr->tx_push_mapping, | |
2950 | GFP_KERNEL); | |
2951 | ||
2952 | if (!txr->tx_push) | |
2953 | return -ENOMEM; | |
2954 | ||
c0c050c5 MC |
2955 | mapping = txr->tx_push_mapping + |
2956 | sizeof(struct tx_push_bd); | |
4419dbe6 | 2957 | txr->data_mapping = cpu_to_le64(mapping); |
c0c050c5 | 2958 | } |
2e8ef77e MC |
2959 | qidx = bp->tc_to_qidx[j]; |
2960 | ring->queue_id = bp->q_info[qidx].queue_id; | |
5f449249 MC |
2961 | if (i < bp->tx_nr_rings_xdp) |
2962 | continue; | |
c0c050c5 MC |
2963 | if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) |
2964 | j++; | |
2965 | } | |
2966 | return 0; | |
2967 | } | |
2968 | ||
2969 | static void bnxt_free_cp_rings(struct bnxt *bp) | |
2970 | { | |
2971 | int i; | |
2972 | ||
2973 | if (!bp->bnapi) | |
2974 | return; | |
2975 | ||
2976 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
2977 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
2978 | struct bnxt_cp_ring_info *cpr; | |
2979 | struct bnxt_ring_struct *ring; | |
50e3ab78 | 2980 | int j; |
c0c050c5 MC |
2981 | |
2982 | if (!bnapi) | |
2983 | continue; | |
2984 | ||
2985 | cpr = &bnapi->cp_ring; | |
2986 | ring = &cpr->cp_ring_struct; | |
2987 | ||
6fe19886 | 2988 | bnxt_free_ring(bp, &ring->ring_mem); |
50e3ab78 MC |
2989 | |
2990 | for (j = 0; j < 2; j++) { | |
2991 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; | |
2992 | ||
2993 | if (cpr2) { | |
2994 | ring = &cpr2->cp_ring_struct; | |
2995 | bnxt_free_ring(bp, &ring->ring_mem); | |
2996 | kfree(cpr2); | |
2997 | cpr->cp_ring_arr[j] = NULL; | |
2998 | } | |
2999 | } | |
c0c050c5 MC |
3000 | } |
3001 | } | |
3002 | ||
50e3ab78 MC |
3003 | static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp) |
3004 | { | |
3005 | struct bnxt_ring_mem_info *rmem; | |
3006 | struct bnxt_ring_struct *ring; | |
3007 | struct bnxt_cp_ring_info *cpr; | |
3008 | int rc; | |
3009 | ||
3010 | cpr = kzalloc(sizeof(*cpr), GFP_KERNEL); | |
3011 | if (!cpr) | |
3012 | return NULL; | |
3013 | ||
3014 | ring = &cpr->cp_ring_struct; | |
3015 | rmem = &ring->ring_mem; | |
3016 | rmem->nr_pages = bp->cp_nr_pages; | |
3017 | rmem->page_size = HW_CMPD_RING_SIZE; | |
3018 | rmem->pg_arr = (void **)cpr->cp_desc_ring; | |
3019 | rmem->dma_arr = cpr->cp_desc_mapping; | |
3020 | rmem->flags = BNXT_RMEM_RING_PTE_FLAG; | |
3021 | rc = bnxt_alloc_ring(bp, rmem); | |
3022 | if (rc) { | |
3023 | bnxt_free_ring(bp, rmem); | |
3024 | kfree(cpr); | |
3025 | cpr = NULL; | |
3026 | } | |
3027 | return cpr; | |
3028 | } | |
3029 | ||
c0c050c5 MC |
3030 | static int bnxt_alloc_cp_rings(struct bnxt *bp) |
3031 | { | |
50e3ab78 | 3032 | bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS); |
e5811b8c | 3033 | int i, rc, ulp_base_vec, ulp_msix; |
c0c050c5 | 3034 | |
e5811b8c MC |
3035 | ulp_msix = bnxt_get_ulp_msix_num(bp); |
3036 | ulp_base_vec = bnxt_get_ulp_msix_base(bp); | |
c0c050c5 MC |
3037 | for (i = 0; i < bp->cp_nr_rings; i++) { |
3038 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
3039 | struct bnxt_cp_ring_info *cpr; | |
3040 | struct bnxt_ring_struct *ring; | |
3041 | ||
3042 | if (!bnapi) | |
3043 | continue; | |
3044 | ||
3045 | cpr = &bnapi->cp_ring; | |
50e3ab78 | 3046 | cpr->bnapi = bnapi; |
c0c050c5 MC |
3047 | ring = &cpr->cp_ring_struct; |
3048 | ||
6fe19886 | 3049 | rc = bnxt_alloc_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
3050 | if (rc) |
3051 | return rc; | |
e5811b8c MC |
3052 | |
3053 | if (ulp_msix && i >= ulp_base_vec) | |
3054 | ring->map_idx = i + ulp_msix; | |
3055 | else | |
3056 | ring->map_idx = i; | |
50e3ab78 MC |
3057 | |
3058 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
3059 | continue; | |
3060 | ||
3061 | if (i < bp->rx_nr_rings) { | |
3062 | struct bnxt_cp_ring_info *cpr2 = | |
3063 | bnxt_alloc_cp_sub_ring(bp); | |
3064 | ||
3065 | cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2; | |
3066 | if (!cpr2) | |
3067 | return -ENOMEM; | |
3068 | cpr2->bnapi = bnapi; | |
3069 | } | |
3070 | if ((sh && i < bp->tx_nr_rings) || | |
3071 | (!sh && i >= bp->rx_nr_rings)) { | |
3072 | struct bnxt_cp_ring_info *cpr2 = | |
3073 | bnxt_alloc_cp_sub_ring(bp); | |
3074 | ||
3075 | cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2; | |
3076 | if (!cpr2) | |
3077 | return -ENOMEM; | |
3078 | cpr2->bnapi = bnapi; | |
3079 | } | |
c0c050c5 MC |
3080 | } |
3081 | return 0; | |
3082 | } | |
3083 | ||
3084 | static void bnxt_init_ring_struct(struct bnxt *bp) | |
3085 | { | |
3086 | int i; | |
3087 | ||
3088 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3089 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
6fe19886 | 3090 | struct bnxt_ring_mem_info *rmem; |
c0c050c5 MC |
3091 | struct bnxt_cp_ring_info *cpr; |
3092 | struct bnxt_rx_ring_info *rxr; | |
3093 | struct bnxt_tx_ring_info *txr; | |
3094 | struct bnxt_ring_struct *ring; | |
3095 | ||
3096 | if (!bnapi) | |
3097 | continue; | |
3098 | ||
3099 | cpr = &bnapi->cp_ring; | |
3100 | ring = &cpr->cp_ring_struct; | |
6fe19886 MC |
3101 | rmem = &ring->ring_mem; |
3102 | rmem->nr_pages = bp->cp_nr_pages; | |
3103 | rmem->page_size = HW_CMPD_RING_SIZE; | |
3104 | rmem->pg_arr = (void **)cpr->cp_desc_ring; | |
3105 | rmem->dma_arr = cpr->cp_desc_mapping; | |
3106 | rmem->vmem_size = 0; | |
c0c050c5 | 3107 | |
b6ab4b01 | 3108 | rxr = bnapi->rx_ring; |
3b2b7d9d MC |
3109 | if (!rxr) |
3110 | goto skip_rx; | |
3111 | ||
c0c050c5 | 3112 | ring = &rxr->rx_ring_struct; |
6fe19886 MC |
3113 | rmem = &ring->ring_mem; |
3114 | rmem->nr_pages = bp->rx_nr_pages; | |
3115 | rmem->page_size = HW_RXBD_RING_SIZE; | |
3116 | rmem->pg_arr = (void **)rxr->rx_desc_ring; | |
3117 | rmem->dma_arr = rxr->rx_desc_mapping; | |
3118 | rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; | |
3119 | rmem->vmem = (void **)&rxr->rx_buf_ring; | |
c0c050c5 MC |
3120 | |
3121 | ring = &rxr->rx_agg_ring_struct; | |
6fe19886 MC |
3122 | rmem = &ring->ring_mem; |
3123 | rmem->nr_pages = bp->rx_agg_nr_pages; | |
3124 | rmem->page_size = HW_RXBD_RING_SIZE; | |
3125 | rmem->pg_arr = (void **)rxr->rx_agg_desc_ring; | |
3126 | rmem->dma_arr = rxr->rx_agg_desc_mapping; | |
3127 | rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; | |
3128 | rmem->vmem = (void **)&rxr->rx_agg_ring; | |
c0c050c5 | 3129 | |
3b2b7d9d | 3130 | skip_rx: |
b6ab4b01 | 3131 | txr = bnapi->tx_ring; |
3b2b7d9d MC |
3132 | if (!txr) |
3133 | continue; | |
3134 | ||
c0c050c5 | 3135 | ring = &txr->tx_ring_struct; |
6fe19886 MC |
3136 | rmem = &ring->ring_mem; |
3137 | rmem->nr_pages = bp->tx_nr_pages; | |
3138 | rmem->page_size = HW_RXBD_RING_SIZE; | |
3139 | rmem->pg_arr = (void **)txr->tx_desc_ring; | |
3140 | rmem->dma_arr = txr->tx_desc_mapping; | |
3141 | rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; | |
3142 | rmem->vmem = (void **)&txr->tx_buf_ring; | |
c0c050c5 MC |
3143 | } |
3144 | } | |
3145 | ||
3146 | static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) | |
3147 | { | |
3148 | int i; | |
3149 | u32 prod; | |
3150 | struct rx_bd **rx_buf_ring; | |
3151 | ||
6fe19886 MC |
3152 | rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr; |
3153 | for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) { | |
c0c050c5 MC |
3154 | int j; |
3155 | struct rx_bd *rxbd; | |
3156 | ||
3157 | rxbd = rx_buf_ring[i]; | |
3158 | if (!rxbd) | |
3159 | continue; | |
3160 | ||
3161 | for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { | |
3162 | rxbd->rx_bd_len_flags_type = cpu_to_le32(type); | |
3163 | rxbd->rx_bd_opaque = prod; | |
3164 | } | |
3165 | } | |
3166 | } | |
3167 | ||
3168 | static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) | |
3169 | { | |
3170 | struct net_device *dev = bp->dev; | |
c0c050c5 MC |
3171 | struct bnxt_rx_ring_info *rxr; |
3172 | struct bnxt_ring_struct *ring; | |
3173 | u32 prod, type; | |
3174 | int i; | |
3175 | ||
c0c050c5 MC |
3176 | type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | |
3177 | RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; | |
3178 | ||
3179 | if (NET_IP_ALIGN == 2) | |
3180 | type |= RX_BD_FLAGS_SOP; | |
3181 | ||
b6ab4b01 | 3182 | rxr = &bp->rx_ring[ring_nr]; |
c0c050c5 MC |
3183 | ring = &rxr->rx_ring_struct; |
3184 | bnxt_init_rxbd_pages(ring, type); | |
3185 | ||
c6d30e83 | 3186 | if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) { |
85192dbf AN |
3187 | bpf_prog_add(bp->xdp_prog, 1); |
3188 | rxr->xdp_prog = bp->xdp_prog; | |
c6d30e83 | 3189 | } |
c0c050c5 MC |
3190 | prod = rxr->rx_prod; |
3191 | for (i = 0; i < bp->rx_ring_size; i++) { | |
3192 | if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) { | |
3193 | netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", | |
3194 | ring_nr, i, bp->rx_ring_size); | |
3195 | break; | |
3196 | } | |
3197 | prod = NEXT_RX(prod); | |
3198 | } | |
3199 | rxr->rx_prod = prod; | |
3200 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
3201 | ||
edd0c2cc MC |
3202 | ring = &rxr->rx_agg_ring_struct; |
3203 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
3204 | ||
c0c050c5 MC |
3205 | if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) |
3206 | return 0; | |
3207 | ||
2839f28b | 3208 | type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) | |
c0c050c5 MC |
3209 | RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; |
3210 | ||
3211 | bnxt_init_rxbd_pages(ring, type); | |
3212 | ||
3213 | prod = rxr->rx_agg_prod; | |
3214 | for (i = 0; i < bp->rx_agg_ring_size; i++) { | |
3215 | if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) { | |
3216 | netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", | |
3217 | ring_nr, i, bp->rx_ring_size); | |
3218 | break; | |
3219 | } | |
3220 | prod = NEXT_RX_AGG(prod); | |
3221 | } | |
3222 | rxr->rx_agg_prod = prod; | |
c0c050c5 MC |
3223 | |
3224 | if (bp->flags & BNXT_FLAG_TPA) { | |
3225 | if (rxr->rx_tpa) { | |
3226 | u8 *data; | |
3227 | dma_addr_t mapping; | |
3228 | ||
79632e9b | 3229 | for (i = 0; i < bp->max_tpa; i++) { |
c0c050c5 MC |
3230 | data = __bnxt_alloc_rx_data(bp, &mapping, |
3231 | GFP_KERNEL); | |
3232 | if (!data) | |
3233 | return -ENOMEM; | |
3234 | ||
3235 | rxr->rx_tpa[i].data = data; | |
b3dba77c | 3236 | rxr->rx_tpa[i].data_ptr = data + bp->rx_offset; |
c0c050c5 MC |
3237 | rxr->rx_tpa[i].mapping = mapping; |
3238 | } | |
3239 | } else { | |
3240 | netdev_err(bp->dev, "No resource allocated for LRO/GRO\n"); | |
3241 | return -ENOMEM; | |
3242 | } | |
3243 | } | |
3244 | ||
3245 | return 0; | |
3246 | } | |
3247 | ||
2247925f SP |
3248 | static void bnxt_init_cp_rings(struct bnxt *bp) |
3249 | { | |
3e08b184 | 3250 | int i, j; |
2247925f SP |
3251 | |
3252 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3253 | struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; | |
3254 | struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; | |
3255 | ||
3256 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
6a8788f2 AG |
3257 | cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; |
3258 | cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; | |
3e08b184 MC |
3259 | for (j = 0; j < 2; j++) { |
3260 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; | |
3261 | ||
3262 | if (!cpr2) | |
3263 | continue; | |
3264 | ||
3265 | ring = &cpr2->cp_ring_struct; | |
3266 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
3267 | cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; | |
3268 | cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; | |
3269 | } | |
2247925f SP |
3270 | } |
3271 | } | |
3272 | ||
c0c050c5 MC |
3273 | static int bnxt_init_rx_rings(struct bnxt *bp) |
3274 | { | |
3275 | int i, rc = 0; | |
3276 | ||
c61fb99c | 3277 | if (BNXT_RX_PAGE_MODE(bp)) { |
c6d30e83 MC |
3278 | bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM; |
3279 | bp->rx_dma_offset = XDP_PACKET_HEADROOM; | |
c61fb99c MC |
3280 | } else { |
3281 | bp->rx_offset = BNXT_RX_OFFSET; | |
3282 | bp->rx_dma_offset = BNXT_RX_DMA_OFFSET; | |
3283 | } | |
b3dba77c | 3284 | |
c0c050c5 MC |
3285 | for (i = 0; i < bp->rx_nr_rings; i++) { |
3286 | rc = bnxt_init_one_rx_ring(bp, i); | |
3287 | if (rc) | |
3288 | break; | |
3289 | } | |
3290 | ||
3291 | return rc; | |
3292 | } | |
3293 | ||
3294 | static int bnxt_init_tx_rings(struct bnxt *bp) | |
3295 | { | |
3296 | u16 i; | |
3297 | ||
3298 | bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, | |
3299 | MAX_SKB_FRAGS + 1); | |
3300 | ||
3301 | for (i = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 3302 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
c0c050c5 MC |
3303 | struct bnxt_ring_struct *ring = &txr->tx_ring_struct; |
3304 | ||
3305 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
3306 | } | |
3307 | ||
3308 | return 0; | |
3309 | } | |
3310 | ||
3311 | static void bnxt_free_ring_grps(struct bnxt *bp) | |
3312 | { | |
3313 | kfree(bp->grp_info); | |
3314 | bp->grp_info = NULL; | |
3315 | } | |
3316 | ||
3317 | static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) | |
3318 | { | |
3319 | int i; | |
3320 | ||
3321 | if (irq_re_init) { | |
3322 | bp->grp_info = kcalloc(bp->cp_nr_rings, | |
3323 | sizeof(struct bnxt_ring_grp_info), | |
3324 | GFP_KERNEL); | |
3325 | if (!bp->grp_info) | |
3326 | return -ENOMEM; | |
3327 | } | |
3328 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3329 | if (irq_re_init) | |
3330 | bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; | |
3331 | bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; | |
3332 | bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; | |
3333 | bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; | |
3334 | bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; | |
3335 | } | |
3336 | return 0; | |
3337 | } | |
3338 | ||
3339 | static void bnxt_free_vnics(struct bnxt *bp) | |
3340 | { | |
3341 | kfree(bp->vnic_info); | |
3342 | bp->vnic_info = NULL; | |
3343 | bp->nr_vnics = 0; | |
3344 | } | |
3345 | ||
3346 | static int bnxt_alloc_vnics(struct bnxt *bp) | |
3347 | { | |
3348 | int num_vnics = 1; | |
3349 | ||
3350 | #ifdef CONFIG_RFS_ACCEL | |
9b3d15e6 | 3351 | if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) |
c0c050c5 MC |
3352 | num_vnics += bp->rx_nr_rings; |
3353 | #endif | |
3354 | ||
dc52c6c7 PS |
3355 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) |
3356 | num_vnics++; | |
3357 | ||
c0c050c5 MC |
3358 | bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), |
3359 | GFP_KERNEL); | |
3360 | if (!bp->vnic_info) | |
3361 | return -ENOMEM; | |
3362 | ||
3363 | bp->nr_vnics = num_vnics; | |
3364 | return 0; | |
3365 | } | |
3366 | ||
3367 | static void bnxt_init_vnics(struct bnxt *bp) | |
3368 | { | |
3369 | int i; | |
3370 | ||
3371 | for (i = 0; i < bp->nr_vnics; i++) { | |
3372 | struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; | |
44c6f72a | 3373 | int j; |
c0c050c5 MC |
3374 | |
3375 | vnic->fw_vnic_id = INVALID_HW_RING_ID; | |
44c6f72a MC |
3376 | for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) |
3377 | vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID; | |
3378 | ||
c0c050c5 MC |
3379 | vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; |
3380 | ||
3381 | if (bp->vnic_info[i].rss_hash_key) { | |
3382 | if (i == 0) | |
3383 | prandom_bytes(vnic->rss_hash_key, | |
3384 | HW_HASH_KEY_SIZE); | |
3385 | else | |
3386 | memcpy(vnic->rss_hash_key, | |
3387 | bp->vnic_info[0].rss_hash_key, | |
3388 | HW_HASH_KEY_SIZE); | |
3389 | } | |
3390 | } | |
3391 | } | |
3392 | ||
3393 | static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) | |
3394 | { | |
3395 | int pages; | |
3396 | ||
3397 | pages = ring_size / desc_per_pg; | |
3398 | ||
3399 | if (!pages) | |
3400 | return 1; | |
3401 | ||
3402 | pages++; | |
3403 | ||
3404 | while (pages & (pages - 1)) | |
3405 | pages++; | |
3406 | ||
3407 | return pages; | |
3408 | } | |
3409 | ||
c6d30e83 | 3410 | void bnxt_set_tpa_flags(struct bnxt *bp) |
c0c050c5 MC |
3411 | { |
3412 | bp->flags &= ~BNXT_FLAG_TPA; | |
341138c3 MC |
3413 | if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) |
3414 | return; | |
c0c050c5 MC |
3415 | if (bp->dev->features & NETIF_F_LRO) |
3416 | bp->flags |= BNXT_FLAG_LRO; | |
1054aee8 | 3417 | else if (bp->dev->features & NETIF_F_GRO_HW) |
c0c050c5 MC |
3418 | bp->flags |= BNXT_FLAG_GRO; |
3419 | } | |
3420 | ||
3421 | /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must | |
3422 | * be set on entry. | |
3423 | */ | |
3424 | void bnxt_set_ring_params(struct bnxt *bp) | |
3425 | { | |
27640ce6 | 3426 | u32 ring_size, rx_size, rx_space, max_rx_cmpl; |
c0c050c5 MC |
3427 | u32 agg_factor = 0, agg_ring_size = 0; |
3428 | ||
3429 | /* 8 for CRC and VLAN */ | |
3430 | rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); | |
3431 | ||
3432 | rx_space = rx_size + NET_SKB_PAD + | |
3433 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
3434 | ||
3435 | bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; | |
3436 | ring_size = bp->rx_ring_size; | |
3437 | bp->rx_agg_ring_size = 0; | |
3438 | bp->rx_agg_nr_pages = 0; | |
3439 | ||
3440 | if (bp->flags & BNXT_FLAG_TPA) | |
2839f28b | 3441 | agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE); |
c0c050c5 MC |
3442 | |
3443 | bp->flags &= ~BNXT_FLAG_JUMBO; | |
bdbd1eb5 | 3444 | if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) { |
c0c050c5 MC |
3445 | u32 jumbo_factor; |
3446 | ||
3447 | bp->flags |= BNXT_FLAG_JUMBO; | |
3448 | jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; | |
3449 | if (jumbo_factor > agg_factor) | |
3450 | agg_factor = jumbo_factor; | |
3451 | } | |
3452 | agg_ring_size = ring_size * agg_factor; | |
3453 | ||
3454 | if (agg_ring_size) { | |
3455 | bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, | |
3456 | RX_DESC_CNT); | |
3457 | if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { | |
3458 | u32 tmp = agg_ring_size; | |
3459 | ||
3460 | bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; | |
3461 | agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; | |
3462 | netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", | |
3463 | tmp, agg_ring_size); | |
3464 | } | |
3465 | bp->rx_agg_ring_size = agg_ring_size; | |
3466 | bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; | |
3467 | rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); | |
3468 | rx_space = rx_size + NET_SKB_PAD + | |
3469 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
3470 | } | |
3471 | ||
3472 | bp->rx_buf_use_size = rx_size; | |
3473 | bp->rx_buf_size = rx_space; | |
3474 | ||
3475 | bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); | |
3476 | bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; | |
3477 | ||
3478 | ring_size = bp->tx_ring_size; | |
3479 | bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); | |
3480 | bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; | |
3481 | ||
27640ce6 MC |
3482 | max_rx_cmpl = bp->rx_ring_size; |
3483 | /* MAX TPA needs to be added because TPA_START completions are | |
3484 | * immediately recycled, so the TPA completions are not bound by | |
3485 | * the RX ring size. | |
3486 | */ | |
3487 | if (bp->flags & BNXT_FLAG_TPA) | |
3488 | max_rx_cmpl += bp->max_tpa; | |
3489 | /* RX and TPA completions are 32-byte, all others are 16-byte */ | |
3490 | ring_size = max_rx_cmpl * 2 + agg_ring_size + bp->tx_ring_size; | |
c0c050c5 MC |
3491 | bp->cp_ring_size = ring_size; |
3492 | ||
3493 | bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); | |
3494 | if (bp->cp_nr_pages > MAX_CP_PAGES) { | |
3495 | bp->cp_nr_pages = MAX_CP_PAGES; | |
3496 | bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; | |
3497 | netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", | |
3498 | ring_size, bp->cp_ring_size); | |
3499 | } | |
3500 | bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; | |
3501 | bp->cp_ring_mask = bp->cp_bit - 1; | |
3502 | } | |
3503 | ||
96a8604f JDB |
3504 | /* Changing allocation mode of RX rings. |
3505 | * TODO: Update when extending xdp_rxq_info to support allocation modes. | |
3506 | */ | |
c61fb99c | 3507 | int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode) |
6bb19474 | 3508 | { |
c61fb99c MC |
3509 | if (page_mode) { |
3510 | if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU) | |
3511 | return -EOPNOTSUPP; | |
7eb9bb3a MC |
3512 | bp->dev->max_mtu = |
3513 | min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU); | |
c61fb99c MC |
3514 | bp->flags &= ~BNXT_FLAG_AGG_RINGS; |
3515 | bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE; | |
c61fb99c MC |
3516 | bp->rx_dir = DMA_BIDIRECTIONAL; |
3517 | bp->rx_skb_func = bnxt_rx_page_skb; | |
1054aee8 MC |
3518 | /* Disable LRO or GRO_HW */ |
3519 | netdev_update_features(bp->dev); | |
c61fb99c | 3520 | } else { |
7eb9bb3a | 3521 | bp->dev->max_mtu = bp->max_mtu; |
c61fb99c MC |
3522 | bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE; |
3523 | bp->rx_dir = DMA_FROM_DEVICE; | |
3524 | bp->rx_skb_func = bnxt_rx_skb; | |
3525 | } | |
6bb19474 MC |
3526 | return 0; |
3527 | } | |
3528 | ||
c0c050c5 MC |
3529 | static void bnxt_free_vnic_attributes(struct bnxt *bp) |
3530 | { | |
3531 | int i; | |
3532 | struct bnxt_vnic_info *vnic; | |
3533 | struct pci_dev *pdev = bp->pdev; | |
3534 | ||
3535 | if (!bp->vnic_info) | |
3536 | return; | |
3537 | ||
3538 | for (i = 0; i < bp->nr_vnics; i++) { | |
3539 | vnic = &bp->vnic_info[i]; | |
3540 | ||
3541 | kfree(vnic->fw_grp_ids); | |
3542 | vnic->fw_grp_ids = NULL; | |
3543 | ||
3544 | kfree(vnic->uc_list); | |
3545 | vnic->uc_list = NULL; | |
3546 | ||
3547 | if (vnic->mc_list) { | |
3548 | dma_free_coherent(&pdev->dev, vnic->mc_list_size, | |
3549 | vnic->mc_list, vnic->mc_list_mapping); | |
3550 | vnic->mc_list = NULL; | |
3551 | } | |
3552 | ||
3553 | if (vnic->rss_table) { | |
34370d24 | 3554 | dma_free_coherent(&pdev->dev, vnic->rss_table_size, |
c0c050c5 MC |
3555 | vnic->rss_table, |
3556 | vnic->rss_table_dma_addr); | |
3557 | vnic->rss_table = NULL; | |
3558 | } | |
3559 | ||
3560 | vnic->rss_hash_key = NULL; | |
3561 | vnic->flags = 0; | |
3562 | } | |
3563 | } | |
3564 | ||
3565 | static int bnxt_alloc_vnic_attributes(struct bnxt *bp) | |
3566 | { | |
3567 | int i, rc = 0, size; | |
3568 | struct bnxt_vnic_info *vnic; | |
3569 | struct pci_dev *pdev = bp->pdev; | |
3570 | int max_rings; | |
3571 | ||
3572 | for (i = 0; i < bp->nr_vnics; i++) { | |
3573 | vnic = &bp->vnic_info[i]; | |
3574 | ||
3575 | if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { | |
3576 | int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; | |
3577 | ||
3578 | if (mem_size > 0) { | |
3579 | vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); | |
3580 | if (!vnic->uc_list) { | |
3581 | rc = -ENOMEM; | |
3582 | goto out; | |
3583 | } | |
3584 | } | |
3585 | } | |
3586 | ||
3587 | if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { | |
3588 | vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; | |
3589 | vnic->mc_list = | |
3590 | dma_alloc_coherent(&pdev->dev, | |
3591 | vnic->mc_list_size, | |
3592 | &vnic->mc_list_mapping, | |
3593 | GFP_KERNEL); | |
3594 | if (!vnic->mc_list) { | |
3595 | rc = -ENOMEM; | |
3596 | goto out; | |
3597 | } | |
3598 | } | |
3599 | ||
44c6f72a MC |
3600 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
3601 | goto vnic_skip_grps; | |
3602 | ||
c0c050c5 MC |
3603 | if (vnic->flags & BNXT_VNIC_RSS_FLAG) |
3604 | max_rings = bp->rx_nr_rings; | |
3605 | else | |
3606 | max_rings = 1; | |
3607 | ||
3608 | vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); | |
3609 | if (!vnic->fw_grp_ids) { | |
3610 | rc = -ENOMEM; | |
3611 | goto out; | |
3612 | } | |
44c6f72a | 3613 | vnic_skip_grps: |
ae10ae74 MC |
3614 | if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) && |
3615 | !(vnic->flags & BNXT_VNIC_RSS_FLAG)) | |
3616 | continue; | |
3617 | ||
c0c050c5 | 3618 | /* Allocate rss table and hash key */ |
34370d24 MC |
3619 | size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); |
3620 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
3621 | size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5); | |
3622 | ||
3623 | vnic->rss_table_size = size + HW_HASH_KEY_SIZE; | |
3624 | vnic->rss_table = dma_alloc_coherent(&pdev->dev, | |
3625 | vnic->rss_table_size, | |
c0c050c5 MC |
3626 | &vnic->rss_table_dma_addr, |
3627 | GFP_KERNEL); | |
3628 | if (!vnic->rss_table) { | |
3629 | rc = -ENOMEM; | |
3630 | goto out; | |
3631 | } | |
3632 | ||
c0c050c5 MC |
3633 | vnic->rss_hash_key = ((void *)vnic->rss_table) + size; |
3634 | vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; | |
3635 | } | |
3636 | return 0; | |
3637 | ||
3638 | out: | |
3639 | return rc; | |
3640 | } | |
3641 | ||
3642 | static void bnxt_free_hwrm_resources(struct bnxt *bp) | |
3643 | { | |
3644 | struct pci_dev *pdev = bp->pdev; | |
3645 | ||
a2bf74f4 VD |
3646 | if (bp->hwrm_cmd_resp_addr) { |
3647 | dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr, | |
3648 | bp->hwrm_cmd_resp_dma_addr); | |
3649 | bp->hwrm_cmd_resp_addr = NULL; | |
3650 | } | |
760b6d33 VD |
3651 | |
3652 | if (bp->hwrm_cmd_kong_resp_addr) { | |
3653 | dma_free_coherent(&pdev->dev, PAGE_SIZE, | |
3654 | bp->hwrm_cmd_kong_resp_addr, | |
3655 | bp->hwrm_cmd_kong_resp_dma_addr); | |
3656 | bp->hwrm_cmd_kong_resp_addr = NULL; | |
3657 | } | |
3658 | } | |
3659 | ||
3660 | static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp) | |
3661 | { | |
3662 | struct pci_dev *pdev = bp->pdev; | |
3663 | ||
ba642ab7 MC |
3664 | if (bp->hwrm_cmd_kong_resp_addr) |
3665 | return 0; | |
3666 | ||
760b6d33 VD |
3667 | bp->hwrm_cmd_kong_resp_addr = |
3668 | dma_alloc_coherent(&pdev->dev, PAGE_SIZE, | |
3669 | &bp->hwrm_cmd_kong_resp_dma_addr, | |
3670 | GFP_KERNEL); | |
3671 | if (!bp->hwrm_cmd_kong_resp_addr) | |
3672 | return -ENOMEM; | |
3673 | ||
3674 | return 0; | |
c0c050c5 MC |
3675 | } |
3676 | ||
3677 | static int bnxt_alloc_hwrm_resources(struct bnxt *bp) | |
3678 | { | |
3679 | struct pci_dev *pdev = bp->pdev; | |
3680 | ||
3681 | bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, | |
3682 | &bp->hwrm_cmd_resp_dma_addr, | |
3683 | GFP_KERNEL); | |
3684 | if (!bp->hwrm_cmd_resp_addr) | |
3685 | return -ENOMEM; | |
c0c050c5 MC |
3686 | |
3687 | return 0; | |
3688 | } | |
3689 | ||
e605db80 DK |
3690 | static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp) |
3691 | { | |
3692 | if (bp->hwrm_short_cmd_req_addr) { | |
3693 | struct pci_dev *pdev = bp->pdev; | |
3694 | ||
1dfddc41 | 3695 | dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, |
e605db80 DK |
3696 | bp->hwrm_short_cmd_req_addr, |
3697 | bp->hwrm_short_cmd_req_dma_addr); | |
3698 | bp->hwrm_short_cmd_req_addr = NULL; | |
3699 | } | |
3700 | } | |
3701 | ||
3702 | static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp) | |
3703 | { | |
3704 | struct pci_dev *pdev = bp->pdev; | |
3705 | ||
ba642ab7 MC |
3706 | if (bp->hwrm_short_cmd_req_addr) |
3707 | return 0; | |
3708 | ||
e605db80 | 3709 | bp->hwrm_short_cmd_req_addr = |
1dfddc41 | 3710 | dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, |
e605db80 DK |
3711 | &bp->hwrm_short_cmd_req_dma_addr, |
3712 | GFP_KERNEL); | |
3713 | if (!bp->hwrm_short_cmd_req_addr) | |
3714 | return -ENOMEM; | |
3715 | ||
3716 | return 0; | |
3717 | } | |
3718 | ||
177a6cde | 3719 | static void bnxt_free_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats) |
c0c050c5 | 3720 | { |
a37120b2 MC |
3721 | kfree(stats->hw_masks); |
3722 | stats->hw_masks = NULL; | |
3723 | kfree(stats->sw_stats); | |
3724 | stats->sw_stats = NULL; | |
177a6cde MC |
3725 | if (stats->hw_stats) { |
3726 | dma_free_coherent(&bp->pdev->dev, stats->len, stats->hw_stats, | |
3727 | stats->hw_stats_map); | |
3728 | stats->hw_stats = NULL; | |
3729 | } | |
3730 | } | |
c0c050c5 | 3731 | |
a37120b2 MC |
3732 | static int bnxt_alloc_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats, |
3733 | bool alloc_masks) | |
177a6cde MC |
3734 | { |
3735 | stats->hw_stats = dma_alloc_coherent(&bp->pdev->dev, stats->len, | |
3736 | &stats->hw_stats_map, GFP_KERNEL); | |
3737 | if (!stats->hw_stats) | |
3738 | return -ENOMEM; | |
00db3cba | 3739 | |
a37120b2 MC |
3740 | stats->sw_stats = kzalloc(stats->len, GFP_KERNEL); |
3741 | if (!stats->sw_stats) | |
3742 | goto stats_mem_err; | |
3743 | ||
3744 | if (alloc_masks) { | |
3745 | stats->hw_masks = kzalloc(stats->len, GFP_KERNEL); | |
3746 | if (!stats->hw_masks) | |
3747 | goto stats_mem_err; | |
3748 | } | |
177a6cde | 3749 | return 0; |
a37120b2 MC |
3750 | |
3751 | stats_mem_err: | |
3752 | bnxt_free_stats_mem(bp, stats); | |
3753 | return -ENOMEM; | |
177a6cde | 3754 | } |
00db3cba | 3755 | |
d752d053 MC |
3756 | static void bnxt_fill_masks(u64 *mask_arr, u64 mask, int count) |
3757 | { | |
3758 | int i; | |
3759 | ||
3760 | for (i = 0; i < count; i++) | |
3761 | mask_arr[i] = mask; | |
3762 | } | |
3763 | ||
3764 | static void bnxt_copy_hw_masks(u64 *mask_arr, __le64 *hw_mask_arr, int count) | |
3765 | { | |
3766 | int i; | |
3767 | ||
3768 | for (i = 0; i < count; i++) | |
3769 | mask_arr[i] = le64_to_cpu(hw_mask_arr[i]); | |
3770 | } | |
3771 | ||
3772 | static int bnxt_hwrm_func_qstat_ext(struct bnxt *bp, | |
3773 | struct bnxt_stats_mem *stats) | |
3774 | { | |
3775 | struct hwrm_func_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr; | |
3776 | struct hwrm_func_qstats_ext_input req = {0}; | |
3777 | __le64 *hw_masks; | |
3778 | int rc; | |
3779 | ||
3780 | if (!(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED) || | |
3781 | !(bp->flags & BNXT_FLAG_CHIP_P5)) | |
3782 | return -EOPNOTSUPP; | |
3783 | ||
3784 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QSTATS_EXT, -1, -1); | |
3785 | req.flags = FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK; | |
3786 | mutex_lock(&bp->hwrm_cmd_lock); | |
3787 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
3788 | if (rc) | |
3789 | goto qstat_exit; | |
3790 | ||
3791 | hw_masks = &resp->rx_ucast_pkts; | |
3792 | bnxt_copy_hw_masks(stats->hw_masks, hw_masks, stats->len / 8); | |
3793 | ||
3794 | qstat_exit: | |
3795 | mutex_unlock(&bp->hwrm_cmd_lock); | |
3796 | return rc; | |
3797 | } | |
3798 | ||
531d1d26 MC |
3799 | static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags); |
3800 | static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags); | |
3801 | ||
d752d053 MC |
3802 | static void bnxt_init_stats(struct bnxt *bp) |
3803 | { | |
3804 | struct bnxt_napi *bnapi = bp->bnapi[0]; | |
3805 | struct bnxt_cp_ring_info *cpr; | |
3806 | struct bnxt_stats_mem *stats; | |
531d1d26 MC |
3807 | __le64 *rx_stats, *tx_stats; |
3808 | int rc, rx_count, tx_count; | |
3809 | u64 *rx_masks, *tx_masks; | |
d752d053 | 3810 | u64 mask; |
531d1d26 | 3811 | u8 flags; |
d752d053 MC |
3812 | |
3813 | cpr = &bnapi->cp_ring; | |
3814 | stats = &cpr->stats; | |
3815 | rc = bnxt_hwrm_func_qstat_ext(bp, stats); | |
3816 | if (rc) { | |
3817 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
3818 | mask = (1ULL << 48) - 1; | |
3819 | else | |
3820 | mask = -1ULL; | |
3821 | bnxt_fill_masks(stats->hw_masks, mask, stats->len / 8); | |
3822 | } | |
531d1d26 MC |
3823 | if (bp->flags & BNXT_FLAG_PORT_STATS) { |
3824 | stats = &bp->port_stats; | |
3825 | rx_stats = stats->hw_stats; | |
3826 | rx_masks = stats->hw_masks; | |
3827 | rx_count = sizeof(struct rx_port_stats) / 8; | |
3828 | tx_stats = rx_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; | |
3829 | tx_masks = rx_masks + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; | |
3830 | tx_count = sizeof(struct tx_port_stats) / 8; | |
3831 | ||
3832 | flags = PORT_QSTATS_REQ_FLAGS_COUNTER_MASK; | |
3833 | rc = bnxt_hwrm_port_qstats(bp, flags); | |
3834 | if (rc) { | |
3835 | mask = (1ULL << 40) - 1; | |
3836 | ||
3837 | bnxt_fill_masks(rx_masks, mask, rx_count); | |
3838 | bnxt_fill_masks(tx_masks, mask, tx_count); | |
3839 | } else { | |
3840 | bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count); | |
3841 | bnxt_copy_hw_masks(tx_masks, tx_stats, tx_count); | |
3842 | bnxt_hwrm_port_qstats(bp, 0); | |
3843 | } | |
3844 | } | |
3845 | if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { | |
3846 | stats = &bp->rx_port_stats_ext; | |
3847 | rx_stats = stats->hw_stats; | |
3848 | rx_masks = stats->hw_masks; | |
3849 | rx_count = sizeof(struct rx_port_stats_ext) / 8; | |
3850 | stats = &bp->tx_port_stats_ext; | |
3851 | tx_stats = stats->hw_stats; | |
3852 | tx_masks = stats->hw_masks; | |
3853 | tx_count = sizeof(struct tx_port_stats_ext) / 8; | |
3854 | ||
3855 | flags = FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK; | |
3856 | rc = bnxt_hwrm_port_qstats_ext(bp, flags); | |
3857 | if (rc) { | |
3858 | mask = (1ULL << 40) - 1; | |
3859 | ||
3860 | bnxt_fill_masks(rx_masks, mask, rx_count); | |
3861 | if (tx_stats) | |
3862 | bnxt_fill_masks(tx_masks, mask, tx_count); | |
3863 | } else { | |
3864 | bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count); | |
3865 | if (tx_stats) | |
3866 | bnxt_copy_hw_masks(tx_masks, tx_stats, | |
3867 | tx_count); | |
3868 | bnxt_hwrm_port_qstats_ext(bp, 0); | |
3869 | } | |
3870 | } | |
d752d053 MC |
3871 | } |
3872 | ||
177a6cde MC |
3873 | static void bnxt_free_port_stats(struct bnxt *bp) |
3874 | { | |
3875 | bp->flags &= ~BNXT_FLAG_PORT_STATS; | |
3876 | bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT; | |
36e53349 | 3877 | |
177a6cde MC |
3878 | bnxt_free_stats_mem(bp, &bp->port_stats); |
3879 | bnxt_free_stats_mem(bp, &bp->rx_port_stats_ext); | |
3880 | bnxt_free_stats_mem(bp, &bp->tx_port_stats_ext); | |
fd3ab1c7 MC |
3881 | } |
3882 | ||
3883 | static void bnxt_free_ring_stats(struct bnxt *bp) | |
3884 | { | |
177a6cde | 3885 | int i; |
3bdf56c4 | 3886 | |
c0c050c5 MC |
3887 | if (!bp->bnapi) |
3888 | return; | |
3889 | ||
c0c050c5 MC |
3890 | for (i = 0; i < bp->cp_nr_rings; i++) { |
3891 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
3892 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
3893 | ||
177a6cde | 3894 | bnxt_free_stats_mem(bp, &cpr->stats); |
c0c050c5 MC |
3895 | } |
3896 | } | |
3897 | ||
3898 | static int bnxt_alloc_stats(struct bnxt *bp) | |
3899 | { | |
3900 | u32 size, i; | |
177a6cde | 3901 | int rc; |
c0c050c5 | 3902 | |
4e748506 | 3903 | size = bp->hw_ring_stats_size; |
c0c050c5 MC |
3904 | |
3905 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3906 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
3907 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
3908 | ||
177a6cde | 3909 | cpr->stats.len = size; |
a37120b2 | 3910 | rc = bnxt_alloc_stats_mem(bp, &cpr->stats, !i); |
177a6cde MC |
3911 | if (rc) |
3912 | return rc; | |
c0c050c5 MC |
3913 | |
3914 | cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; | |
3915 | } | |
3bdf56c4 | 3916 | |
a220eabc VV |
3917 | if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700) |
3918 | return 0; | |
fd3ab1c7 | 3919 | |
177a6cde | 3920 | if (bp->port_stats.hw_stats) |
a220eabc | 3921 | goto alloc_ext_stats; |
3bdf56c4 | 3922 | |
177a6cde | 3923 | bp->port_stats.len = BNXT_PORT_STATS_SIZE; |
a37120b2 | 3924 | rc = bnxt_alloc_stats_mem(bp, &bp->port_stats, true); |
177a6cde MC |
3925 | if (rc) |
3926 | return rc; | |
3bdf56c4 | 3927 | |
a220eabc | 3928 | bp->flags |= BNXT_FLAG_PORT_STATS; |
00db3cba | 3929 | |
fd3ab1c7 | 3930 | alloc_ext_stats: |
a220eabc VV |
3931 | /* Display extended statistics only if FW supports it */ |
3932 | if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900) | |
6154532f | 3933 | if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) |
00db3cba VV |
3934 | return 0; |
3935 | ||
177a6cde | 3936 | if (bp->rx_port_stats_ext.hw_stats) |
a220eabc | 3937 | goto alloc_tx_ext_stats; |
fd3ab1c7 | 3938 | |
177a6cde | 3939 | bp->rx_port_stats_ext.len = sizeof(struct rx_port_stats_ext); |
a37120b2 | 3940 | rc = bnxt_alloc_stats_mem(bp, &bp->rx_port_stats_ext, true); |
177a6cde MC |
3941 | /* Extended stats are optional */ |
3942 | if (rc) | |
a220eabc | 3943 | return 0; |
00db3cba | 3944 | |
fd3ab1c7 | 3945 | alloc_tx_ext_stats: |
177a6cde | 3946 | if (bp->tx_port_stats_ext.hw_stats) |
dfe64de9 | 3947 | return 0; |
fd3ab1c7 | 3948 | |
6154532f VV |
3949 | if (bp->hwrm_spec_code >= 0x10902 || |
3950 | (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) { | |
177a6cde | 3951 | bp->tx_port_stats_ext.len = sizeof(struct tx_port_stats_ext); |
a37120b2 | 3952 | rc = bnxt_alloc_stats_mem(bp, &bp->tx_port_stats_ext, true); |
177a6cde MC |
3953 | /* Extended stats are optional */ |
3954 | if (rc) | |
3955 | return 0; | |
3bdf56c4 | 3956 | } |
a220eabc | 3957 | bp->flags |= BNXT_FLAG_PORT_STATS_EXT; |
c0c050c5 MC |
3958 | return 0; |
3959 | } | |
3960 | ||
3961 | static void bnxt_clear_ring_indices(struct bnxt *bp) | |
3962 | { | |
3963 | int i; | |
3964 | ||
3965 | if (!bp->bnapi) | |
3966 | return; | |
3967 | ||
3968 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3969 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
3970 | struct bnxt_cp_ring_info *cpr; | |
3971 | struct bnxt_rx_ring_info *rxr; | |
3972 | struct bnxt_tx_ring_info *txr; | |
3973 | ||
3974 | if (!bnapi) | |
3975 | continue; | |
3976 | ||
3977 | cpr = &bnapi->cp_ring; | |
3978 | cpr->cp_raw_cons = 0; | |
3979 | ||
b6ab4b01 | 3980 | txr = bnapi->tx_ring; |
3b2b7d9d MC |
3981 | if (txr) { |
3982 | txr->tx_prod = 0; | |
3983 | txr->tx_cons = 0; | |
3984 | } | |
c0c050c5 | 3985 | |
b6ab4b01 | 3986 | rxr = bnapi->rx_ring; |
3b2b7d9d MC |
3987 | if (rxr) { |
3988 | rxr->rx_prod = 0; | |
3989 | rxr->rx_agg_prod = 0; | |
3990 | rxr->rx_sw_agg_prod = 0; | |
376a5b86 | 3991 | rxr->rx_next_cons = 0; |
3b2b7d9d | 3992 | } |
c0c050c5 MC |
3993 | } |
3994 | } | |
3995 | ||
3996 | static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) | |
3997 | { | |
3998 | #ifdef CONFIG_RFS_ACCEL | |
3999 | int i; | |
4000 | ||
4001 | /* Under rtnl_lock and all our NAPIs have been disabled. It's | |
4002 | * safe to delete the hash table. | |
4003 | */ | |
4004 | for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { | |
4005 | struct hlist_head *head; | |
4006 | struct hlist_node *tmp; | |
4007 | struct bnxt_ntuple_filter *fltr; | |
4008 | ||
4009 | head = &bp->ntp_fltr_hash_tbl[i]; | |
4010 | hlist_for_each_entry_safe(fltr, tmp, head, hash) { | |
4011 | hlist_del(&fltr->hash); | |
4012 | kfree(fltr); | |
4013 | } | |
4014 | } | |
4015 | if (irq_reinit) { | |
4016 | kfree(bp->ntp_fltr_bmap); | |
4017 | bp->ntp_fltr_bmap = NULL; | |
4018 | } | |
4019 | bp->ntp_fltr_count = 0; | |
4020 | #endif | |
4021 | } | |
4022 | ||
4023 | static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) | |
4024 | { | |
4025 | #ifdef CONFIG_RFS_ACCEL | |
4026 | int i, rc = 0; | |
4027 | ||
4028 | if (!(bp->flags & BNXT_FLAG_RFS)) | |
4029 | return 0; | |
4030 | ||
4031 | for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) | |
4032 | INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); | |
4033 | ||
4034 | bp->ntp_fltr_count = 0; | |
ac45bd93 DC |
4035 | bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR), |
4036 | sizeof(long), | |
c0c050c5 MC |
4037 | GFP_KERNEL); |
4038 | ||
4039 | if (!bp->ntp_fltr_bmap) | |
4040 | rc = -ENOMEM; | |
4041 | ||
4042 | return rc; | |
4043 | #else | |
4044 | return 0; | |
4045 | #endif | |
4046 | } | |
4047 | ||
4048 | static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) | |
4049 | { | |
4050 | bnxt_free_vnic_attributes(bp); | |
4051 | bnxt_free_tx_rings(bp); | |
4052 | bnxt_free_rx_rings(bp); | |
4053 | bnxt_free_cp_rings(bp); | |
4054 | bnxt_free_ntp_fltrs(bp, irq_re_init); | |
4055 | if (irq_re_init) { | |
fd3ab1c7 | 4056 | bnxt_free_ring_stats(bp); |
fea6b333 MC |
4057 | if (!(bp->fw_cap & BNXT_FW_CAP_PORT_STATS_NO_RESET)) |
4058 | bnxt_free_port_stats(bp); | |
c0c050c5 MC |
4059 | bnxt_free_ring_grps(bp); |
4060 | bnxt_free_vnics(bp); | |
a960dec9 MC |
4061 | kfree(bp->tx_ring_map); |
4062 | bp->tx_ring_map = NULL; | |
b6ab4b01 MC |
4063 | kfree(bp->tx_ring); |
4064 | bp->tx_ring = NULL; | |
4065 | kfree(bp->rx_ring); | |
4066 | bp->rx_ring = NULL; | |
c0c050c5 MC |
4067 | kfree(bp->bnapi); |
4068 | bp->bnapi = NULL; | |
4069 | } else { | |
4070 | bnxt_clear_ring_indices(bp); | |
4071 | } | |
4072 | } | |
4073 | ||
4074 | static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) | |
4075 | { | |
01657bcd | 4076 | int i, j, rc, size, arr_size; |
c0c050c5 MC |
4077 | void *bnapi; |
4078 | ||
4079 | if (irq_re_init) { | |
4080 | /* Allocate bnapi mem pointer array and mem block for | |
4081 | * all queues | |
4082 | */ | |
4083 | arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * | |
4084 | bp->cp_nr_rings); | |
4085 | size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); | |
4086 | bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); | |
4087 | if (!bnapi) | |
4088 | return -ENOMEM; | |
4089 | ||
4090 | bp->bnapi = bnapi; | |
4091 | bnapi += arr_size; | |
4092 | for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { | |
4093 | bp->bnapi[i] = bnapi; | |
4094 | bp->bnapi[i]->index = i; | |
4095 | bp->bnapi[i]->bp = bp; | |
e38287b7 MC |
4096 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
4097 | struct bnxt_cp_ring_info *cpr = | |
4098 | &bp->bnapi[i]->cp_ring; | |
4099 | ||
4100 | cpr->cp_ring_struct.ring_mem.flags = | |
4101 | BNXT_RMEM_RING_PTE_FLAG; | |
4102 | } | |
c0c050c5 MC |
4103 | } |
4104 | ||
b6ab4b01 MC |
4105 | bp->rx_ring = kcalloc(bp->rx_nr_rings, |
4106 | sizeof(struct bnxt_rx_ring_info), | |
4107 | GFP_KERNEL); | |
4108 | if (!bp->rx_ring) | |
4109 | return -ENOMEM; | |
4110 | ||
4111 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
e38287b7 MC |
4112 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
4113 | ||
4114 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
4115 | rxr->rx_ring_struct.ring_mem.flags = | |
4116 | BNXT_RMEM_RING_PTE_FLAG; | |
4117 | rxr->rx_agg_ring_struct.ring_mem.flags = | |
4118 | BNXT_RMEM_RING_PTE_FLAG; | |
4119 | } | |
4120 | rxr->bnapi = bp->bnapi[i]; | |
b6ab4b01 MC |
4121 | bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; |
4122 | } | |
4123 | ||
4124 | bp->tx_ring = kcalloc(bp->tx_nr_rings, | |
4125 | sizeof(struct bnxt_tx_ring_info), | |
4126 | GFP_KERNEL); | |
4127 | if (!bp->tx_ring) | |
4128 | return -ENOMEM; | |
4129 | ||
a960dec9 MC |
4130 | bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16), |
4131 | GFP_KERNEL); | |
4132 | ||
4133 | if (!bp->tx_ring_map) | |
4134 | return -ENOMEM; | |
4135 | ||
01657bcd MC |
4136 | if (bp->flags & BNXT_FLAG_SHARED_RINGS) |
4137 | j = 0; | |
4138 | else | |
4139 | j = bp->rx_nr_rings; | |
4140 | ||
4141 | for (i = 0; i < bp->tx_nr_rings; i++, j++) { | |
e38287b7 MC |
4142 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
4143 | ||
4144 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
4145 | txr->tx_ring_struct.ring_mem.flags = | |
4146 | BNXT_RMEM_RING_PTE_FLAG; | |
4147 | txr->bnapi = bp->bnapi[j]; | |
4148 | bp->bnapi[j]->tx_ring = txr; | |
5f449249 | 4149 | bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i; |
38413406 | 4150 | if (i >= bp->tx_nr_rings_xdp) { |
e38287b7 | 4151 | txr->txq_index = i - bp->tx_nr_rings_xdp; |
38413406 MC |
4152 | bp->bnapi[j]->tx_int = bnxt_tx_int; |
4153 | } else { | |
fa3e93e8 | 4154 | bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP; |
38413406 MC |
4155 | bp->bnapi[j]->tx_int = bnxt_tx_int_xdp; |
4156 | } | |
b6ab4b01 MC |
4157 | } |
4158 | ||
c0c050c5 MC |
4159 | rc = bnxt_alloc_stats(bp); |
4160 | if (rc) | |
4161 | goto alloc_mem_err; | |
d752d053 | 4162 | bnxt_init_stats(bp); |
c0c050c5 MC |
4163 | |
4164 | rc = bnxt_alloc_ntp_fltrs(bp); | |
4165 | if (rc) | |
4166 | goto alloc_mem_err; | |
4167 | ||
4168 | rc = bnxt_alloc_vnics(bp); | |
4169 | if (rc) | |
4170 | goto alloc_mem_err; | |
4171 | } | |
4172 | ||
4173 | bnxt_init_ring_struct(bp); | |
4174 | ||
4175 | rc = bnxt_alloc_rx_rings(bp); | |
4176 | if (rc) | |
4177 | goto alloc_mem_err; | |
4178 | ||
4179 | rc = bnxt_alloc_tx_rings(bp); | |
4180 | if (rc) | |
4181 | goto alloc_mem_err; | |
4182 | ||
4183 | rc = bnxt_alloc_cp_rings(bp); | |
4184 | if (rc) | |
4185 | goto alloc_mem_err; | |
4186 | ||
4187 | bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | | |
4188 | BNXT_VNIC_UCAST_FLAG; | |
4189 | rc = bnxt_alloc_vnic_attributes(bp); | |
4190 | if (rc) | |
4191 | goto alloc_mem_err; | |
4192 | return 0; | |
4193 | ||
4194 | alloc_mem_err: | |
4195 | bnxt_free_mem(bp, true); | |
4196 | return rc; | |
4197 | } | |
4198 | ||
9d8bc097 MC |
4199 | static void bnxt_disable_int(struct bnxt *bp) |
4200 | { | |
4201 | int i; | |
4202 | ||
4203 | if (!bp->bnapi) | |
4204 | return; | |
4205 | ||
4206 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
4207 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
4208 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
daf1f1e7 | 4209 | struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; |
9d8bc097 | 4210 | |
daf1f1e7 | 4211 | if (ring->fw_ring_id != INVALID_HW_RING_ID) |
697197e5 | 4212 | bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); |
9d8bc097 MC |
4213 | } |
4214 | } | |
4215 | ||
e5811b8c MC |
4216 | static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n) |
4217 | { | |
4218 | struct bnxt_napi *bnapi = bp->bnapi[n]; | |
4219 | struct bnxt_cp_ring_info *cpr; | |
4220 | ||
4221 | cpr = &bnapi->cp_ring; | |
4222 | return cpr->cp_ring_struct.map_idx; | |
4223 | } | |
4224 | ||
9d8bc097 MC |
4225 | static void bnxt_disable_int_sync(struct bnxt *bp) |
4226 | { | |
4227 | int i; | |
4228 | ||
4229 | atomic_inc(&bp->intr_sem); | |
4230 | ||
4231 | bnxt_disable_int(bp); | |
e5811b8c MC |
4232 | for (i = 0; i < bp->cp_nr_rings; i++) { |
4233 | int map_idx = bnxt_cp_num_to_irq_num(bp, i); | |
4234 | ||
4235 | synchronize_irq(bp->irq_tbl[map_idx].vector); | |
4236 | } | |
9d8bc097 MC |
4237 | } |
4238 | ||
4239 | static void bnxt_enable_int(struct bnxt *bp) | |
4240 | { | |
4241 | int i; | |
4242 | ||
4243 | atomic_set(&bp->intr_sem, 0); | |
4244 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
4245 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
4246 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
4247 | ||
697197e5 | 4248 | bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons); |
9d8bc097 MC |
4249 | } |
4250 | } | |
4251 | ||
c0c050c5 MC |
4252 | void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type, |
4253 | u16 cmpl_ring, u16 target_id) | |
4254 | { | |
a8643e16 | 4255 | struct input *req = request; |
c0c050c5 | 4256 | |
a8643e16 MC |
4257 | req->req_type = cpu_to_le16(req_type); |
4258 | req->cmpl_ring = cpu_to_le16(cmpl_ring); | |
4259 | req->target_id = cpu_to_le16(target_id); | |
760b6d33 VD |
4260 | if (bnxt_kong_hwrm_message(bp, req)) |
4261 | req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); | |
4262 | else | |
4263 | req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr); | |
c0c050c5 MC |
4264 | } |
4265 | ||
d4f1420d MC |
4266 | static int bnxt_hwrm_to_stderr(u32 hwrm_err) |
4267 | { | |
4268 | switch (hwrm_err) { | |
4269 | case HWRM_ERR_CODE_SUCCESS: | |
4270 | return 0; | |
4271 | case HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED: | |
4272 | return -EACCES; | |
4273 | case HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR: | |
4274 | return -ENOSPC; | |
4275 | case HWRM_ERR_CODE_INVALID_PARAMS: | |
4276 | case HWRM_ERR_CODE_INVALID_FLAGS: | |
4277 | case HWRM_ERR_CODE_INVALID_ENABLES: | |
4278 | case HWRM_ERR_CODE_UNSUPPORTED_TLV: | |
4279 | case HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR: | |
4280 | return -EINVAL; | |
4281 | case HWRM_ERR_CODE_NO_BUFFER: | |
4282 | return -ENOMEM; | |
4283 | case HWRM_ERR_CODE_HOT_RESET_PROGRESS: | |
3a707bed | 4284 | case HWRM_ERR_CODE_BUSY: |
d4f1420d MC |
4285 | return -EAGAIN; |
4286 | case HWRM_ERR_CODE_CMD_NOT_SUPPORTED: | |
4287 | return -EOPNOTSUPP; | |
4288 | default: | |
4289 | return -EIO; | |
4290 | } | |
4291 | } | |
4292 | ||
fbfbc485 MC |
4293 | static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len, |
4294 | int timeout, bool silent) | |
c0c050c5 | 4295 | { |
a11fa2be | 4296 | int i, intr_process, rc, tmo_count; |
a8643e16 | 4297 | struct input *req = msg; |
c0c050c5 | 4298 | u32 *data = msg; |
845adfe4 | 4299 | u8 *valid; |
c0c050c5 MC |
4300 | u16 cp_ring_id, len = 0; |
4301 | struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr; | |
e605db80 | 4302 | u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN; |
ebd5818c | 4303 | struct hwrm_short_input short_input = {0}; |
2e9ee398 VD |
4304 | u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER; |
4305 | u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM; | |
760b6d33 | 4306 | u16 dst = BNXT_HWRM_CHNL_CHIMP; |
c0c050c5 | 4307 | |
b4fff207 MC |
4308 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) |
4309 | return -EBUSY; | |
4310 | ||
1dfddc41 MC |
4311 | if (msg_len > BNXT_HWRM_MAX_REQ_LEN) { |
4312 | if (msg_len > bp->hwrm_max_ext_req_len || | |
4313 | !bp->hwrm_short_cmd_req_addr) | |
4314 | return -EINVAL; | |
4315 | } | |
4316 | ||
760b6d33 VD |
4317 | if (bnxt_hwrm_kong_chnl(bp, req)) { |
4318 | dst = BNXT_HWRM_CHNL_KONG; | |
4319 | bar_offset = BNXT_GRCPF_REG_KONG_COMM; | |
4320 | doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER; | |
4321 | resp = bp->hwrm_cmd_kong_resp_addr; | |
760b6d33 VD |
4322 | } |
4323 | ||
4324 | memset(resp, 0, PAGE_SIZE); | |
4325 | cp_ring_id = le16_to_cpu(req->cmpl_ring); | |
4326 | intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1; | |
4327 | ||
4328 | req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst)); | |
4329 | /* currently supports only one outstanding message */ | |
4330 | if (intr_process) | |
4331 | bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id); | |
4332 | ||
1dfddc41 MC |
4333 | if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || |
4334 | msg_len > BNXT_HWRM_MAX_REQ_LEN) { | |
e605db80 | 4335 | void *short_cmd_req = bp->hwrm_short_cmd_req_addr; |
1dfddc41 MC |
4336 | u16 max_msg_len; |
4337 | ||
4338 | /* Set boundary for maximum extended request length for short | |
4339 | * cmd format. If passed up from device use the max supported | |
4340 | * internal req length. | |
4341 | */ | |
4342 | max_msg_len = bp->hwrm_max_ext_req_len; | |
e605db80 DK |
4343 | |
4344 | memcpy(short_cmd_req, req, msg_len); | |
1dfddc41 MC |
4345 | if (msg_len < max_msg_len) |
4346 | memset(short_cmd_req + msg_len, 0, | |
4347 | max_msg_len - msg_len); | |
e605db80 DK |
4348 | |
4349 | short_input.req_type = req->req_type; | |
4350 | short_input.signature = | |
4351 | cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD); | |
4352 | short_input.size = cpu_to_le16(msg_len); | |
4353 | short_input.req_addr = | |
4354 | cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr); | |
4355 | ||
4356 | data = (u32 *)&short_input; | |
4357 | msg_len = sizeof(short_input); | |
4358 | ||
4359 | /* Sync memory write before updating doorbell */ | |
4360 | wmb(); | |
4361 | ||
4362 | max_req_len = BNXT_HWRM_SHORT_REQ_LEN; | |
4363 | } | |
4364 | ||
c0c050c5 | 4365 | /* Write request msg to hwrm channel */ |
2e9ee398 | 4366 | __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4); |
c0c050c5 | 4367 | |
e605db80 | 4368 | for (i = msg_len; i < max_req_len; i += 4) |
2e9ee398 | 4369 | writel(0, bp->bar0 + bar_offset + i); |
d79979a1 | 4370 | |
c0c050c5 | 4371 | /* Ring channel doorbell */ |
2e9ee398 | 4372 | writel(1, bp->bar0 + doorbell_offset); |
c0c050c5 | 4373 | |
5bedb529 MC |
4374 | if (!pci_is_enabled(bp->pdev)) |
4375 | return 0; | |
4376 | ||
ff4fe81d MC |
4377 | if (!timeout) |
4378 | timeout = DFLT_HWRM_CMD_TIMEOUT; | |
9751e8e7 AG |
4379 | /* convert timeout to usec */ |
4380 | timeout *= 1000; | |
ff4fe81d | 4381 | |
c0c050c5 | 4382 | i = 0; |
9751e8e7 AG |
4383 | /* Short timeout for the first few iterations: |
4384 | * number of loops = number of loops for short timeout + | |
4385 | * number of loops for standard timeout. | |
4386 | */ | |
4387 | tmo_count = HWRM_SHORT_TIMEOUT_COUNTER; | |
4388 | timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER; | |
4389 | tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT); | |
89455017 | 4390 | |
c0c050c5 | 4391 | if (intr_process) { |
fc718bb2 VD |
4392 | u16 seq_id = bp->hwrm_intr_seq_id; |
4393 | ||
c0c050c5 | 4394 | /* Wait until hwrm response cmpl interrupt is processed */ |
fc718bb2 | 4395 | while (bp->hwrm_intr_seq_id != (u16)~seq_id && |
a11fa2be | 4396 | i++ < tmo_count) { |
642aebde PC |
4397 | /* Abort the wait for completion if the FW health |
4398 | * check has failed. | |
4399 | */ | |
4400 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) | |
4401 | return -EBUSY; | |
9751e8e7 AG |
4402 | /* on first few passes, just barely sleep */ |
4403 | if (i < HWRM_SHORT_TIMEOUT_COUNTER) | |
4404 | usleep_range(HWRM_SHORT_MIN_TIMEOUT, | |
4405 | HWRM_SHORT_MAX_TIMEOUT); | |
4406 | else | |
4407 | usleep_range(HWRM_MIN_TIMEOUT, | |
4408 | HWRM_MAX_TIMEOUT); | |
c0c050c5 MC |
4409 | } |
4410 | ||
fc718bb2 | 4411 | if (bp->hwrm_intr_seq_id != (u16)~seq_id) { |
5bedb529 MC |
4412 | if (!silent) |
4413 | netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n", | |
4414 | le16_to_cpu(req->req_type)); | |
a935cb7e | 4415 | return -EBUSY; |
c0c050c5 | 4416 | } |
2a5a8800 EP |
4417 | len = le16_to_cpu(resp->resp_len); |
4418 | valid = ((u8 *)resp) + len - 1; | |
c0c050c5 | 4419 | } else { |
cc559c1a MC |
4420 | int j; |
4421 | ||
c0c050c5 | 4422 | /* Check if response len is updated */ |
a11fa2be | 4423 | for (i = 0; i < tmo_count; i++) { |
642aebde PC |
4424 | /* Abort the wait for completion if the FW health |
4425 | * check has failed. | |
4426 | */ | |
4427 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) | |
4428 | return -EBUSY; | |
2a5a8800 | 4429 | len = le16_to_cpu(resp->resp_len); |
c0c050c5 MC |
4430 | if (len) |
4431 | break; | |
9751e8e7 | 4432 | /* on first few passes, just barely sleep */ |
67681d02 | 4433 | if (i < HWRM_SHORT_TIMEOUT_COUNTER) |
9751e8e7 AG |
4434 | usleep_range(HWRM_SHORT_MIN_TIMEOUT, |
4435 | HWRM_SHORT_MAX_TIMEOUT); | |
4436 | else | |
4437 | usleep_range(HWRM_MIN_TIMEOUT, | |
4438 | HWRM_MAX_TIMEOUT); | |
c0c050c5 MC |
4439 | } |
4440 | ||
a11fa2be | 4441 | if (i >= tmo_count) { |
5bedb529 MC |
4442 | if (!silent) |
4443 | netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n", | |
4444 | HWRM_TOTAL_TIMEOUT(i), | |
4445 | le16_to_cpu(req->req_type), | |
4446 | le16_to_cpu(req->seq_id), len); | |
a935cb7e | 4447 | return -EBUSY; |
c0c050c5 MC |
4448 | } |
4449 | ||
845adfe4 | 4450 | /* Last byte of resp contains valid bit */ |
2a5a8800 | 4451 | valid = ((u8 *)resp) + len - 1; |
cc559c1a | 4452 | for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) { |
845adfe4 MC |
4453 | /* make sure we read from updated DMA memory */ |
4454 | dma_rmb(); | |
4455 | if (*valid) | |
c0c050c5 | 4456 | break; |
0000b81a | 4457 | usleep_range(1, 5); |
c0c050c5 MC |
4458 | } |
4459 | ||
cc559c1a | 4460 | if (j >= HWRM_VALID_BIT_DELAY_USEC) { |
5bedb529 MC |
4461 | if (!silent) |
4462 | netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n", | |
4463 | HWRM_TOTAL_TIMEOUT(i), | |
4464 | le16_to_cpu(req->req_type), | |
4465 | le16_to_cpu(req->seq_id), len, | |
4466 | *valid); | |
a935cb7e | 4467 | return -EBUSY; |
c0c050c5 MC |
4468 | } |
4469 | } | |
4470 | ||
845adfe4 MC |
4471 | /* Zero valid bit for compatibility. Valid bit in an older spec |
4472 | * may become a new field in a newer spec. We must make sure that | |
4473 | * a new field not implemented by old spec will read zero. | |
4474 | */ | |
4475 | *valid = 0; | |
c0c050c5 | 4476 | rc = le16_to_cpu(resp->error_code); |
fbfbc485 | 4477 | if (rc && !silent) |
c0c050c5 MC |
4478 | netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n", |
4479 | le16_to_cpu(resp->req_type), | |
4480 | le16_to_cpu(resp->seq_id), rc); | |
d4f1420d | 4481 | return bnxt_hwrm_to_stderr(rc); |
fbfbc485 MC |
4482 | } |
4483 | ||
4484 | int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) | |
4485 | { | |
4486 | return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false); | |
c0c050c5 MC |
4487 | } |
4488 | ||
cc72f3b1 MC |
4489 | int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, |
4490 | int timeout) | |
4491 | { | |
4492 | return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); | |
4493 | } | |
4494 | ||
c0c050c5 MC |
4495 | int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) |
4496 | { | |
4497 | int rc; | |
4498 | ||
4499 | mutex_lock(&bp->hwrm_cmd_lock); | |
4500 | rc = _hwrm_send_message(bp, msg, msg_len, timeout); | |
4501 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4502 | return rc; | |
4503 | } | |
4504 | ||
90e20921 MC |
4505 | int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, |
4506 | int timeout) | |
4507 | { | |
4508 | int rc; | |
4509 | ||
4510 | mutex_lock(&bp->hwrm_cmd_lock); | |
4511 | rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); | |
4512 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4513 | return rc; | |
4514 | } | |
4515 | ||
2e882468 VV |
4516 | int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, int bmap_size, |
4517 | bool async_only) | |
c0c050c5 | 4518 | { |
2e882468 | 4519 | struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr; |
c0c050c5 | 4520 | struct hwrm_func_drv_rgtr_input req = {0}; |
25be8623 MC |
4521 | DECLARE_BITMAP(async_events_bmap, 256); |
4522 | u32 *events = (u32 *)async_events_bmap; | |
acfb50e4 | 4523 | u32 flags; |
2e882468 | 4524 | int rc, i; |
a1653b13 MC |
4525 | |
4526 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); | |
4527 | ||
4528 | req.enables = | |
4529 | cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | | |
2e882468 VV |
4530 | FUNC_DRV_RGTR_REQ_ENABLES_VER | |
4531 | FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); | |
a1653b13 | 4532 | |
11f15ed3 | 4533 | req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX); |
8280b38e VV |
4534 | flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE; |
4535 | if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) | |
4536 | flags |= FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT; | |
acfb50e4 | 4537 | if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) |
e633a329 VV |
4538 | flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT | |
4539 | FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT; | |
acfb50e4 | 4540 | req.flags = cpu_to_le32(flags); |
d4f52de0 MC |
4541 | req.ver_maj_8b = DRV_VER_MAJ; |
4542 | req.ver_min_8b = DRV_VER_MIN; | |
4543 | req.ver_upd_8b = DRV_VER_UPD; | |
4544 | req.ver_maj = cpu_to_le16(DRV_VER_MAJ); | |
4545 | req.ver_min = cpu_to_le16(DRV_VER_MIN); | |
4546 | req.ver_upd = cpu_to_le16(DRV_VER_UPD); | |
c0c050c5 MC |
4547 | |
4548 | if (BNXT_PF(bp)) { | |
9b0436c3 | 4549 | u32 data[8]; |
a1653b13 | 4550 | int i; |
c0c050c5 | 4551 | |
9b0436c3 MC |
4552 | memset(data, 0, sizeof(data)); |
4553 | for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) { | |
4554 | u16 cmd = bnxt_vf_req_snif[i]; | |
4555 | unsigned int bit, idx; | |
4556 | ||
4557 | idx = cmd / 32; | |
4558 | bit = cmd % 32; | |
4559 | data[idx] |= 1 << bit; | |
4560 | } | |
c0c050c5 | 4561 | |
de68f5de MC |
4562 | for (i = 0; i < 8; i++) |
4563 | req.vf_req_fwd[i] = cpu_to_le32(data[i]); | |
4564 | ||
c0c050c5 MC |
4565 | req.enables |= |
4566 | cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); | |
4567 | } | |
4568 | ||
abd43a13 VD |
4569 | if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE) |
4570 | req.flags |= cpu_to_le32( | |
4571 | FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE); | |
4572 | ||
2e882468 VV |
4573 | memset(async_events_bmap, 0, sizeof(async_events_bmap)); |
4574 | for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) { | |
4575 | u16 event_id = bnxt_async_events_arr[i]; | |
4576 | ||
4577 | if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY && | |
4578 | !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) | |
4579 | continue; | |
4580 | __set_bit(bnxt_async_events_arr[i], async_events_bmap); | |
4581 | } | |
4582 | if (bmap && bmap_size) { | |
4583 | for (i = 0; i < bmap_size; i++) { | |
4584 | if (test_bit(i, bmap)) | |
4585 | __set_bit(i, async_events_bmap); | |
4586 | } | |
4587 | } | |
4588 | for (i = 0; i < 8; i++) | |
4589 | req.async_event_fwd[i] |= cpu_to_le32(events[i]); | |
4590 | ||
4591 | if (async_only) | |
4592 | req.enables = | |
4593 | cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); | |
4594 | ||
25e1acd6 MC |
4595 | mutex_lock(&bp->hwrm_cmd_lock); |
4596 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
bdb38602 VV |
4597 | if (!rc) { |
4598 | set_bit(BNXT_STATE_DRV_REGISTERED, &bp->state); | |
4599 | if (resp->flags & | |
4600 | cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED)) | |
4601 | bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE; | |
4602 | } | |
25e1acd6 MC |
4603 | mutex_unlock(&bp->hwrm_cmd_lock); |
4604 | return rc; | |
c0c050c5 MC |
4605 | } |
4606 | ||
be58a0da JH |
4607 | static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) |
4608 | { | |
4609 | struct hwrm_func_drv_unrgtr_input req = {0}; | |
4610 | ||
bdb38602 VV |
4611 | if (!test_and_clear_bit(BNXT_STATE_DRV_REGISTERED, &bp->state)) |
4612 | return 0; | |
4613 | ||
be58a0da JH |
4614 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1); |
4615 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4616 | } | |
4617 | ||
c0c050c5 MC |
4618 | static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) |
4619 | { | |
4620 | u32 rc = 0; | |
4621 | struct hwrm_tunnel_dst_port_free_input req = {0}; | |
4622 | ||
4623 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1); | |
4624 | req.tunnel_type = tunnel_type; | |
4625 | ||
4626 | switch (tunnel_type) { | |
4627 | case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: | |
442a35a5 JK |
4628 | req.tunnel_dst_port_id = cpu_to_le16(bp->vxlan_fw_dst_port_id); |
4629 | bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID; | |
c0c050c5 MC |
4630 | break; |
4631 | case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: | |
442a35a5 JK |
4632 | req.tunnel_dst_port_id = cpu_to_le16(bp->nge_fw_dst_port_id); |
4633 | bp->nge_fw_dst_port_id = INVALID_HW_RING_ID; | |
c0c050c5 MC |
4634 | break; |
4635 | default: | |
4636 | break; | |
4637 | } | |
4638 | ||
4639 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4640 | if (rc) | |
4641 | netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", | |
4642 | rc); | |
4643 | return rc; | |
4644 | } | |
4645 | ||
4646 | static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, | |
4647 | u8 tunnel_type) | |
4648 | { | |
4649 | u32 rc = 0; | |
4650 | struct hwrm_tunnel_dst_port_alloc_input req = {0}; | |
4651 | struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
4652 | ||
4653 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1); | |
4654 | ||
4655 | req.tunnel_type = tunnel_type; | |
4656 | req.tunnel_dst_port_val = port; | |
4657 | ||
4658 | mutex_lock(&bp->hwrm_cmd_lock); | |
4659 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4660 | if (rc) { | |
4661 | netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", | |
4662 | rc); | |
4663 | goto err_out; | |
4664 | } | |
4665 | ||
57aac71b CJ |
4666 | switch (tunnel_type) { |
4667 | case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN: | |
442a35a5 JK |
4668 | bp->vxlan_fw_dst_port_id = |
4669 | le16_to_cpu(resp->tunnel_dst_port_id); | |
57aac71b CJ |
4670 | break; |
4671 | case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE: | |
442a35a5 | 4672 | bp->nge_fw_dst_port_id = le16_to_cpu(resp->tunnel_dst_port_id); |
57aac71b CJ |
4673 | break; |
4674 | default: | |
4675 | break; | |
4676 | } | |
4677 | ||
c0c050c5 MC |
4678 | err_out: |
4679 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4680 | return rc; | |
4681 | } | |
4682 | ||
4683 | static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) | |
4684 | { | |
4685 | struct hwrm_cfa_l2_set_rx_mask_input req = {0}; | |
4686 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; | |
4687 | ||
4688 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1); | |
c193554e | 4689 | req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); |
c0c050c5 MC |
4690 | |
4691 | req.num_mc_entries = cpu_to_le32(vnic->mc_list_count); | |
4692 | req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); | |
4693 | req.mask = cpu_to_le32(vnic->rx_mask); | |
4694 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4695 | } | |
4696 | ||
4697 | #ifdef CONFIG_RFS_ACCEL | |
4698 | static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, | |
4699 | struct bnxt_ntuple_filter *fltr) | |
4700 | { | |
4701 | struct hwrm_cfa_ntuple_filter_free_input req = {0}; | |
4702 | ||
4703 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1); | |
4704 | req.ntuple_filter_id = fltr->filter_id; | |
4705 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4706 | } | |
4707 | ||
4708 | #define BNXT_NTP_FLTR_FLAGS \ | |
4709 | (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ | |
4710 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ | |
4711 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ | |
4712 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ | |
4713 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ | |
4714 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ | |
4715 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ | |
4716 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ | |
4717 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ | |
4718 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ | |
4719 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ | |
4720 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ | |
4721 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ | |
c193554e | 4722 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) |
c0c050c5 | 4723 | |
61aad724 MC |
4724 | #define BNXT_NTP_TUNNEL_FLTR_FLAG \ |
4725 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE | |
4726 | ||
c0c050c5 MC |
4727 | static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, |
4728 | struct bnxt_ntuple_filter *fltr) | |
4729 | { | |
c0c050c5 | 4730 | struct hwrm_cfa_ntuple_filter_alloc_input req = {0}; |
5c209fc8 | 4731 | struct hwrm_cfa_ntuple_filter_alloc_output *resp; |
c0c050c5 | 4732 | struct flow_keys *keys = &fltr->fkeys; |
ac33906c | 4733 | struct bnxt_vnic_info *vnic; |
41136ab3 | 4734 | u32 flags = 0; |
5c209fc8 | 4735 | int rc = 0; |
c0c050c5 MC |
4736 | |
4737 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1); | |
a54c4d74 | 4738 | req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx]; |
c0c050c5 | 4739 | |
41136ab3 MC |
4740 | if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) { |
4741 | flags = CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX; | |
4742 | req.dst_id = cpu_to_le16(fltr->rxq); | |
ac33906c MC |
4743 | } else { |
4744 | vnic = &bp->vnic_info[fltr->rxq + 1]; | |
41136ab3 | 4745 | req.dst_id = cpu_to_le16(vnic->fw_vnic_id); |
ac33906c | 4746 | } |
41136ab3 MC |
4747 | req.flags = cpu_to_le32(flags); |
4748 | req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS); | |
c0c050c5 MC |
4749 | |
4750 | req.ethertype = htons(ETH_P_IP); | |
4751 | memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN); | |
c193554e | 4752 | req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; |
c0c050c5 MC |
4753 | req.ip_protocol = keys->basic.ip_proto; |
4754 | ||
dda0e746 MC |
4755 | if (keys->basic.n_proto == htons(ETH_P_IPV6)) { |
4756 | int i; | |
4757 | ||
4758 | req.ethertype = htons(ETH_P_IPV6); | |
4759 | req.ip_addr_type = | |
4760 | CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6; | |
4761 | *(struct in6_addr *)&req.src_ipaddr[0] = | |
4762 | keys->addrs.v6addrs.src; | |
4763 | *(struct in6_addr *)&req.dst_ipaddr[0] = | |
4764 | keys->addrs.v6addrs.dst; | |
4765 | for (i = 0; i < 4; i++) { | |
4766 | req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff); | |
4767 | req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff); | |
4768 | } | |
4769 | } else { | |
4770 | req.src_ipaddr[0] = keys->addrs.v4addrs.src; | |
4771 | req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); | |
4772 | req.dst_ipaddr[0] = keys->addrs.v4addrs.dst; | |
4773 | req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); | |
4774 | } | |
61aad724 MC |
4775 | if (keys->control.flags & FLOW_DIS_ENCAPSULATION) { |
4776 | req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG); | |
4777 | req.tunnel_type = | |
4778 | CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL; | |
4779 | } | |
c0c050c5 MC |
4780 | |
4781 | req.src_port = keys->ports.src; | |
4782 | req.src_port_mask = cpu_to_be16(0xffff); | |
4783 | req.dst_port = keys->ports.dst; | |
4784 | req.dst_port_mask = cpu_to_be16(0xffff); | |
4785 | ||
c0c050c5 MC |
4786 | mutex_lock(&bp->hwrm_cmd_lock); |
4787 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5c209fc8 VD |
4788 | if (!rc) { |
4789 | resp = bnxt_get_hwrm_resp_addr(bp, &req); | |
c0c050c5 | 4790 | fltr->filter_id = resp->ntuple_filter_id; |
5c209fc8 | 4791 | } |
c0c050c5 MC |
4792 | mutex_unlock(&bp->hwrm_cmd_lock); |
4793 | return rc; | |
4794 | } | |
4795 | #endif | |
4796 | ||
4797 | static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, | |
4798 | u8 *mac_addr) | |
4799 | { | |
4800 | u32 rc = 0; | |
4801 | struct hwrm_cfa_l2_filter_alloc_input req = {0}; | |
4802 | struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
4803 | ||
4804 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1); | |
dc52c6c7 PS |
4805 | req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX); |
4806 | if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) | |
4807 | req.flags |= | |
4808 | cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); | |
c193554e | 4809 | req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); |
c0c050c5 MC |
4810 | req.enables = |
4811 | cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | | |
c193554e | 4812 | CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | |
c0c050c5 MC |
4813 | CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); |
4814 | memcpy(req.l2_addr, mac_addr, ETH_ALEN); | |
4815 | req.l2_addr_mask[0] = 0xff; | |
4816 | req.l2_addr_mask[1] = 0xff; | |
4817 | req.l2_addr_mask[2] = 0xff; | |
4818 | req.l2_addr_mask[3] = 0xff; | |
4819 | req.l2_addr_mask[4] = 0xff; | |
4820 | req.l2_addr_mask[5] = 0xff; | |
4821 | ||
4822 | mutex_lock(&bp->hwrm_cmd_lock); | |
4823 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4824 | if (!rc) | |
4825 | bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = | |
4826 | resp->l2_filter_id; | |
4827 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4828 | return rc; | |
4829 | } | |
4830 | ||
4831 | static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) | |
4832 | { | |
4833 | u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ | |
4834 | int rc = 0; | |
4835 | ||
4836 | /* Any associated ntuple filters will also be cleared by firmware. */ | |
4837 | mutex_lock(&bp->hwrm_cmd_lock); | |
4838 | for (i = 0; i < num_of_vnics; i++) { | |
4839 | struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; | |
4840 | ||
4841 | for (j = 0; j < vnic->uc_filter_count; j++) { | |
4842 | struct hwrm_cfa_l2_filter_free_input req = {0}; | |
4843 | ||
4844 | bnxt_hwrm_cmd_hdr_init(bp, &req, | |
4845 | HWRM_CFA_L2_FILTER_FREE, -1, -1); | |
4846 | ||
4847 | req.l2_filter_id = vnic->fw_l2_filter_id[j]; | |
4848 | ||
4849 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
4850 | HWRM_CMD_TIMEOUT); | |
4851 | } | |
4852 | vnic->uc_filter_count = 0; | |
4853 | } | |
4854 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4855 | ||
4856 | return rc; | |
4857 | } | |
4858 | ||
4859 | static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) | |
4860 | { | |
4861 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; | |
79632e9b | 4862 | u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX; |
c0c050c5 MC |
4863 | struct hwrm_vnic_tpa_cfg_input req = {0}; |
4864 | ||
3c4fe80b MC |
4865 | if (vnic->fw_vnic_id == INVALID_HW_RING_ID) |
4866 | return 0; | |
4867 | ||
c0c050c5 MC |
4868 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1); |
4869 | ||
4870 | if (tpa_flags) { | |
4871 | u16 mss = bp->dev->mtu - 40; | |
4872 | u32 nsegs, n, segs = 0, flags; | |
4873 | ||
4874 | flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | | |
4875 | VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | | |
4876 | VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | | |
4877 | VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | | |
4878 | VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; | |
4879 | if (tpa_flags & BNXT_FLAG_GRO) | |
4880 | flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; | |
4881 | ||
4882 | req.flags = cpu_to_le32(flags); | |
4883 | ||
4884 | req.enables = | |
4885 | cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | | |
c193554e MC |
4886 | VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | |
4887 | VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); | |
c0c050c5 MC |
4888 | |
4889 | /* Number of segs are log2 units, and first packet is not | |
4890 | * included as part of this units. | |
4891 | */ | |
2839f28b MC |
4892 | if (mss <= BNXT_RX_PAGE_SIZE) { |
4893 | n = BNXT_RX_PAGE_SIZE / mss; | |
c0c050c5 MC |
4894 | nsegs = (MAX_SKB_FRAGS - 1) * n; |
4895 | } else { | |
2839f28b MC |
4896 | n = mss / BNXT_RX_PAGE_SIZE; |
4897 | if (mss & (BNXT_RX_PAGE_SIZE - 1)) | |
c0c050c5 MC |
4898 | n++; |
4899 | nsegs = (MAX_SKB_FRAGS - n) / n; | |
4900 | } | |
4901 | ||
79632e9b MC |
4902 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
4903 | segs = MAX_TPA_SEGS_P5; | |
4904 | max_aggs = bp->max_tpa; | |
4905 | } else { | |
4906 | segs = ilog2(nsegs); | |
4907 | } | |
c0c050c5 | 4908 | req.max_agg_segs = cpu_to_le16(segs); |
79632e9b | 4909 | req.max_aggs = cpu_to_le16(max_aggs); |
c193554e MC |
4910 | |
4911 | req.min_agg_len = cpu_to_le32(512); | |
c0c050c5 MC |
4912 | } |
4913 | req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); | |
4914 | ||
4915 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4916 | } | |
4917 | ||
2c61d211 MC |
4918 | static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring) |
4919 | { | |
4920 | struct bnxt_ring_grp_info *grp_info; | |
4921 | ||
4922 | grp_info = &bp->grp_info[ring->grp_idx]; | |
4923 | return grp_info->cp_fw_ring_id; | |
4924 | } | |
4925 | ||
4926 | static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) | |
4927 | { | |
4928 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
4929 | struct bnxt_napi *bnapi = rxr->bnapi; | |
4930 | struct bnxt_cp_ring_info *cpr; | |
4931 | ||
4932 | cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL]; | |
4933 | return cpr->cp_ring_struct.fw_ring_id; | |
4934 | } else { | |
4935 | return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct); | |
4936 | } | |
4937 | } | |
4938 | ||
4939 | static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr) | |
4940 | { | |
4941 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
4942 | struct bnxt_napi *bnapi = txr->bnapi; | |
4943 | struct bnxt_cp_ring_info *cpr; | |
4944 | ||
4945 | cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL]; | |
4946 | return cpr->cp_ring_struct.fw_ring_id; | |
4947 | } else { | |
4948 | return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct); | |
4949 | } | |
4950 | } | |
4951 | ||
1667cbf6 MC |
4952 | static int bnxt_alloc_rss_indir_tbl(struct bnxt *bp) |
4953 | { | |
4954 | int entries; | |
4955 | ||
4956 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
4957 | entries = BNXT_MAX_RSS_TABLE_ENTRIES_P5; | |
4958 | else | |
4959 | entries = HW_HASH_INDEX_SIZE; | |
4960 | ||
4961 | bp->rss_indir_tbl_entries = entries; | |
4962 | bp->rss_indir_tbl = kmalloc_array(entries, sizeof(*bp->rss_indir_tbl), | |
4963 | GFP_KERNEL); | |
4964 | if (!bp->rss_indir_tbl) | |
4965 | return -ENOMEM; | |
4966 | return 0; | |
4967 | } | |
4968 | ||
4969 | static void bnxt_set_dflt_rss_indir_tbl(struct bnxt *bp) | |
4970 | { | |
4971 | u16 max_rings, max_entries, pad, i; | |
4972 | ||
4973 | if (!bp->rx_nr_rings) | |
4974 | return; | |
4975 | ||
4976 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) | |
4977 | max_rings = bp->rx_nr_rings - 1; | |
4978 | else | |
4979 | max_rings = bp->rx_nr_rings; | |
4980 | ||
4981 | max_entries = bnxt_get_rxfh_indir_size(bp->dev); | |
4982 | ||
4983 | for (i = 0; i < max_entries; i++) | |
4984 | bp->rss_indir_tbl[i] = ethtool_rxfh_indir_default(i, max_rings); | |
4985 | ||
4986 | pad = bp->rss_indir_tbl_entries - max_entries; | |
4987 | if (pad) | |
4988 | memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16)); | |
4989 | } | |
4990 | ||
bd3191b5 MC |
4991 | static u16 bnxt_get_max_rss_ring(struct bnxt *bp) |
4992 | { | |
4993 | u16 i, tbl_size, max_ring = 0; | |
4994 | ||
4995 | if (!bp->rss_indir_tbl) | |
4996 | return 0; | |
4997 | ||
4998 | tbl_size = bnxt_get_rxfh_indir_size(bp->dev); | |
4999 | for (i = 0; i < tbl_size; i++) | |
5000 | max_ring = max(max_ring, bp->rss_indir_tbl[i]); | |
5001 | return max_ring; | |
5002 | } | |
5003 | ||
f9f6a3fb MC |
5004 | int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings) |
5005 | { | |
5006 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
5007 | return DIV_ROUND_UP(rx_rings, BNXT_RSS_TABLE_ENTRIES_P5); | |
5008 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) | |
5009 | return 2; | |
5010 | return 1; | |
5011 | } | |
5012 | ||
f33a305d MC |
5013 | static void __bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic) |
5014 | { | |
5015 | bool no_rss = !(vnic->flags & BNXT_VNIC_RSS_FLAG); | |
5016 | u16 i, j; | |
5017 | ||
5018 | /* Fill the RSS indirection table with ring group ids */ | |
5019 | for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++) { | |
5020 | if (!no_rss) | |
5021 | j = bp->rss_indir_tbl[i]; | |
5022 | vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); | |
5023 | } | |
5024 | } | |
5025 | ||
5026 | static void __bnxt_fill_hw_rss_tbl_p5(struct bnxt *bp, | |
5027 | struct bnxt_vnic_info *vnic) | |
5028 | { | |
5029 | __le16 *ring_tbl = vnic->rss_table; | |
5030 | struct bnxt_rx_ring_info *rxr; | |
5031 | u16 tbl_size, i; | |
5032 | ||
5033 | tbl_size = bnxt_get_rxfh_indir_size(bp->dev); | |
5034 | ||
5035 | for (i = 0; i < tbl_size; i++) { | |
5036 | u16 ring_id, j; | |
5037 | ||
5038 | j = bp->rss_indir_tbl[i]; | |
5039 | rxr = &bp->rx_ring[j]; | |
5040 | ||
5041 | ring_id = rxr->rx_ring_struct.fw_ring_id; | |
5042 | *ring_tbl++ = cpu_to_le16(ring_id); | |
5043 | ring_id = bnxt_cp_ring_for_rx(bp, rxr); | |
5044 | *ring_tbl++ = cpu_to_le16(ring_id); | |
5045 | } | |
5046 | } | |
5047 | ||
5048 | static void bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic) | |
5049 | { | |
5050 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
5051 | __bnxt_fill_hw_rss_tbl_p5(bp, vnic); | |
5052 | else | |
5053 | __bnxt_fill_hw_rss_tbl(bp, vnic); | |
5054 | } | |
5055 | ||
c0c050c5 MC |
5056 | static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) |
5057 | { | |
c0c050c5 MC |
5058 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
5059 | struct hwrm_vnic_rss_cfg_input req = {0}; | |
5060 | ||
7b3af4f7 MC |
5061 | if ((bp->flags & BNXT_FLAG_CHIP_P5) || |
5062 | vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID) | |
c0c050c5 MC |
5063 | return 0; |
5064 | ||
5065 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); | |
5066 | if (set_rss) { | |
f33a305d | 5067 | bnxt_fill_hw_rss_tbl(bp, vnic); |
87da7f79 | 5068 | req.hash_type = cpu_to_le32(bp->rss_hash_cfg); |
50f011b6 | 5069 | req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; |
c0c050c5 MC |
5070 | req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); |
5071 | req.hash_key_tbl_addr = | |
5072 | cpu_to_le64(vnic->rss_hash_key_dma_addr); | |
5073 | } | |
94ce9caa | 5074 | req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); |
c0c050c5 MC |
5075 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
5076 | } | |
5077 | ||
7b3af4f7 MC |
5078 | static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss) |
5079 | { | |
5080 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; | |
7b3af4f7 | 5081 | struct hwrm_vnic_rss_cfg_input req = {0}; |
f33a305d MC |
5082 | dma_addr_t ring_tbl_map; |
5083 | u32 i, nr_ctxs; | |
7b3af4f7 MC |
5084 | |
5085 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); | |
5086 | req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); | |
5087 | if (!set_rss) { | |
5088 | hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5089 | return 0; | |
5090 | } | |
f33a305d | 5091 | bnxt_fill_hw_rss_tbl(bp, vnic); |
7b3af4f7 MC |
5092 | req.hash_type = cpu_to_le32(bp->rss_hash_cfg); |
5093 | req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; | |
7b3af4f7 | 5094 | req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr); |
f33a305d | 5095 | ring_tbl_map = vnic->rss_table_dma_addr; |
f9f6a3fb | 5096 | nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings); |
f33a305d | 5097 | for (i = 0; i < nr_ctxs; ring_tbl_map += BNXT_RSS_TABLE_SIZE_P5, i++) { |
7b3af4f7 MC |
5098 | int rc; |
5099 | ||
f33a305d | 5100 | req.ring_grp_tbl_addr = cpu_to_le64(ring_tbl_map); |
7b3af4f7 MC |
5101 | req.ring_table_pair_index = i; |
5102 | req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]); | |
7b3af4f7 MC |
5103 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
5104 | if (rc) | |
d4f1420d | 5105 | return rc; |
7b3af4f7 MC |
5106 | } |
5107 | return 0; | |
5108 | } | |
5109 | ||
c0c050c5 MC |
5110 | static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) |
5111 | { | |
5112 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; | |
5113 | struct hwrm_vnic_plcmodes_cfg_input req = {0}; | |
5114 | ||
5115 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1); | |
5116 | req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT | | |
5117 | VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | | |
5118 | VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); | |
5119 | req.enables = | |
5120 | cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID | | |
5121 | VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); | |
5122 | /* thresholds not implemented in firmware yet */ | |
5123 | req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); | |
5124 | req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh); | |
5125 | req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); | |
5126 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5127 | } | |
5128 | ||
94ce9caa PS |
5129 | static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id, |
5130 | u16 ctx_idx) | |
c0c050c5 MC |
5131 | { |
5132 | struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0}; | |
5133 | ||
5134 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1); | |
5135 | req.rss_cos_lb_ctx_id = | |
94ce9caa | 5136 | cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]); |
c0c050c5 MC |
5137 | |
5138 | hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
94ce9caa | 5139 | bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID; |
c0c050c5 MC |
5140 | } |
5141 | ||
5142 | static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) | |
5143 | { | |
94ce9caa | 5144 | int i, j; |
c0c050c5 MC |
5145 | |
5146 | for (i = 0; i < bp->nr_vnics; i++) { | |
5147 | struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; | |
5148 | ||
94ce9caa PS |
5149 | for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) { |
5150 | if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID) | |
5151 | bnxt_hwrm_vnic_ctx_free_one(bp, i, j); | |
5152 | } | |
c0c050c5 MC |
5153 | } |
5154 | bp->rsscos_nr_ctxs = 0; | |
5155 | } | |
5156 | ||
94ce9caa | 5157 | static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx) |
c0c050c5 MC |
5158 | { |
5159 | int rc; | |
5160 | struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; | |
5161 | struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = | |
5162 | bp->hwrm_cmd_resp_addr; | |
5163 | ||
5164 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1, | |
5165 | -1); | |
5166 | ||
5167 | mutex_lock(&bp->hwrm_cmd_lock); | |
5168 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5169 | if (!rc) | |
94ce9caa | 5170 | bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = |
c0c050c5 MC |
5171 | le16_to_cpu(resp->rss_cos_lb_ctx_id); |
5172 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5173 | ||
5174 | return rc; | |
5175 | } | |
5176 | ||
abe93ad2 MC |
5177 | static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp) |
5178 | { | |
5179 | if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP) | |
5180 | return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE; | |
5181 | return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE; | |
5182 | } | |
5183 | ||
a588e458 | 5184 | int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) |
c0c050c5 | 5185 | { |
b81a90d3 | 5186 | unsigned int ring = 0, grp_idx; |
c0c050c5 MC |
5187 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
5188 | struct hwrm_vnic_cfg_input req = {0}; | |
cf6645f8 | 5189 | u16 def_vlan = 0; |
c0c050c5 MC |
5190 | |
5191 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1); | |
dc52c6c7 | 5192 | |
7b3af4f7 MC |
5193 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5194 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; | |
5195 | ||
5196 | req.default_rx_ring_id = | |
5197 | cpu_to_le16(rxr->rx_ring_struct.fw_ring_id); | |
5198 | req.default_cmpl_ring_id = | |
5199 | cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr)); | |
5200 | req.enables = | |
5201 | cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID | | |
5202 | VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID); | |
5203 | goto vnic_mru; | |
5204 | } | |
dc52c6c7 | 5205 | req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP); |
c0c050c5 | 5206 | /* Only RSS support for now TBD: COS & LB */ |
dc52c6c7 PS |
5207 | if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) { |
5208 | req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); | |
5209 | req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | | |
5210 | VNIC_CFG_REQ_ENABLES_MRU); | |
ae10ae74 MC |
5211 | } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) { |
5212 | req.rss_rule = | |
5213 | cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]); | |
5214 | req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | | |
5215 | VNIC_CFG_REQ_ENABLES_MRU); | |
5216 | req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE); | |
dc52c6c7 PS |
5217 | } else { |
5218 | req.rss_rule = cpu_to_le16(0xffff); | |
5219 | } | |
94ce9caa | 5220 | |
dc52c6c7 PS |
5221 | if (BNXT_CHIP_TYPE_NITRO_A0(bp) && |
5222 | (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) { | |
94ce9caa PS |
5223 | req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]); |
5224 | req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE); | |
5225 | } else { | |
5226 | req.cos_rule = cpu_to_le16(0xffff); | |
5227 | } | |
5228 | ||
c0c050c5 | 5229 | if (vnic->flags & BNXT_VNIC_RSS_FLAG) |
b81a90d3 | 5230 | ring = 0; |
c0c050c5 | 5231 | else if (vnic->flags & BNXT_VNIC_RFS_FLAG) |
b81a90d3 | 5232 | ring = vnic_id - 1; |
76595193 PS |
5233 | else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp)) |
5234 | ring = bp->rx_nr_rings - 1; | |
c0c050c5 | 5235 | |
b81a90d3 | 5236 | grp_idx = bp->rx_ring[ring].bnapi->index; |
c0c050c5 | 5237 | req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); |
c0c050c5 | 5238 | req.lb_rule = cpu_to_le16(0xffff); |
7b3af4f7 | 5239 | vnic_mru: |
d0b82c54 | 5240 | req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + VLAN_HLEN); |
c0c050c5 | 5241 | |
7b3af4f7 | 5242 | req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); |
cf6645f8 MC |
5243 | #ifdef CONFIG_BNXT_SRIOV |
5244 | if (BNXT_VF(bp)) | |
5245 | def_vlan = bp->vf.vlan; | |
5246 | #endif | |
5247 | if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan) | |
c0c050c5 | 5248 | req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); |
a588e458 | 5249 | if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) |
abe93ad2 | 5250 | req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp)); |
c0c050c5 MC |
5251 | |
5252 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5253 | } | |
5254 | ||
3d061591 | 5255 | static void bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) |
c0c050c5 | 5256 | { |
c0c050c5 MC |
5257 | if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { |
5258 | struct hwrm_vnic_free_input req = {0}; | |
5259 | ||
5260 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1); | |
5261 | req.vnic_id = | |
5262 | cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); | |
5263 | ||
3d061591 | 5264 | hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
c0c050c5 MC |
5265 | bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; |
5266 | } | |
c0c050c5 MC |
5267 | } |
5268 | ||
5269 | static void bnxt_hwrm_vnic_free(struct bnxt *bp) | |
5270 | { | |
5271 | u16 i; | |
5272 | ||
5273 | for (i = 0; i < bp->nr_vnics; i++) | |
5274 | bnxt_hwrm_vnic_free_one(bp, i); | |
5275 | } | |
5276 | ||
b81a90d3 MC |
5277 | static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, |
5278 | unsigned int start_rx_ring_idx, | |
5279 | unsigned int nr_rings) | |
c0c050c5 | 5280 | { |
b81a90d3 MC |
5281 | int rc = 0; |
5282 | unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; | |
c0c050c5 MC |
5283 | struct hwrm_vnic_alloc_input req = {0}; |
5284 | struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
44c6f72a MC |
5285 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
5286 | ||
5287 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
5288 | goto vnic_no_ring_grps; | |
c0c050c5 MC |
5289 | |
5290 | /* map ring groups to this vnic */ | |
b81a90d3 MC |
5291 | for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { |
5292 | grp_idx = bp->rx_ring[i].bnapi->index; | |
5293 | if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { | |
c0c050c5 | 5294 | netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", |
b81a90d3 | 5295 | j, nr_rings); |
c0c050c5 MC |
5296 | break; |
5297 | } | |
44c6f72a | 5298 | vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id; |
c0c050c5 MC |
5299 | } |
5300 | ||
44c6f72a MC |
5301 | vnic_no_ring_grps: |
5302 | for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++) | |
5303 | vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID; | |
c0c050c5 MC |
5304 | if (vnic_id == 0) |
5305 | req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); | |
5306 | ||
5307 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1); | |
5308 | ||
5309 | mutex_lock(&bp->hwrm_cmd_lock); | |
5310 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5311 | if (!rc) | |
44c6f72a | 5312 | vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id); |
c0c050c5 MC |
5313 | mutex_unlock(&bp->hwrm_cmd_lock); |
5314 | return rc; | |
5315 | } | |
5316 | ||
8fdefd63 MC |
5317 | static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) |
5318 | { | |
5319 | struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
5320 | struct hwrm_vnic_qcaps_input req = {0}; | |
5321 | int rc; | |
5322 | ||
fbbdbc64 | 5323 | bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats); |
ba642ab7 | 5324 | bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP); |
8fdefd63 MC |
5325 | if (bp->hwrm_spec_code < 0x10600) |
5326 | return 0; | |
5327 | ||
5328 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1); | |
5329 | mutex_lock(&bp->hwrm_cmd_lock); | |
5330 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5331 | if (!rc) { | |
abe93ad2 MC |
5332 | u32 flags = le32_to_cpu(resp->flags); |
5333 | ||
41e8d798 MC |
5334 | if (!(bp->flags & BNXT_FLAG_CHIP_P5) && |
5335 | (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)) | |
8fdefd63 | 5336 | bp->flags |= BNXT_FLAG_NEW_RSS_CAP; |
abe93ad2 MC |
5337 | if (flags & |
5338 | VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP) | |
5339 | bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP; | |
1da63ddd EP |
5340 | |
5341 | /* Older P5 fw before EXT_HW_STATS support did not set | |
5342 | * VLAN_STRIP_CAP properly. | |
5343 | */ | |
5344 | if ((flags & VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP) || | |
5345 | ((bp->flags & BNXT_FLAG_CHIP_P5) && | |
5346 | !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))) | |
5347 | bp->fw_cap |= BNXT_FW_CAP_VLAN_RX_STRIP; | |
79632e9b | 5348 | bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported); |
4e748506 MC |
5349 | if (bp->max_tpa_v2) |
5350 | bp->hw_ring_stats_size = | |
5351 | sizeof(struct ctx_hw_stats_ext); | |
8fdefd63 MC |
5352 | } |
5353 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5354 | return rc; | |
5355 | } | |
5356 | ||
c0c050c5 MC |
5357 | static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) |
5358 | { | |
5359 | u16 i; | |
5360 | u32 rc = 0; | |
5361 | ||
44c6f72a MC |
5362 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
5363 | return 0; | |
5364 | ||
c0c050c5 MC |
5365 | mutex_lock(&bp->hwrm_cmd_lock); |
5366 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
5367 | struct hwrm_ring_grp_alloc_input req = {0}; | |
5368 | struct hwrm_ring_grp_alloc_output *resp = | |
5369 | bp->hwrm_cmd_resp_addr; | |
b81a90d3 | 5370 | unsigned int grp_idx = bp->rx_ring[i].bnapi->index; |
c0c050c5 MC |
5371 | |
5372 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1); | |
5373 | ||
b81a90d3 MC |
5374 | req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); |
5375 | req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); | |
5376 | req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); | |
5377 | req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); | |
c0c050c5 MC |
5378 | |
5379 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
5380 | HWRM_CMD_TIMEOUT); | |
5381 | if (rc) | |
5382 | break; | |
5383 | ||
b81a90d3 MC |
5384 | bp->grp_info[grp_idx].fw_grp_id = |
5385 | le32_to_cpu(resp->ring_group_id); | |
c0c050c5 MC |
5386 | } |
5387 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5388 | return rc; | |
5389 | } | |
5390 | ||
3d061591 | 5391 | static void bnxt_hwrm_ring_grp_free(struct bnxt *bp) |
c0c050c5 MC |
5392 | { |
5393 | u16 i; | |
c0c050c5 MC |
5394 | struct hwrm_ring_grp_free_input req = {0}; |
5395 | ||
44c6f72a | 5396 | if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5)) |
3d061591 | 5397 | return; |
c0c050c5 MC |
5398 | |
5399 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1); | |
5400 | ||
5401 | mutex_lock(&bp->hwrm_cmd_lock); | |
5402 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
5403 | if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) | |
5404 | continue; | |
5405 | req.ring_group_id = | |
5406 | cpu_to_le32(bp->grp_info[i].fw_grp_id); | |
5407 | ||
3d061591 | 5408 | _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
c0c050c5 MC |
5409 | bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; |
5410 | } | |
5411 | mutex_unlock(&bp->hwrm_cmd_lock); | |
c0c050c5 MC |
5412 | } |
5413 | ||
5414 | static int hwrm_ring_alloc_send_msg(struct bnxt *bp, | |
5415 | struct bnxt_ring_struct *ring, | |
9899bb59 | 5416 | u32 ring_type, u32 map_index) |
c0c050c5 MC |
5417 | { |
5418 | int rc = 0, err = 0; | |
5419 | struct hwrm_ring_alloc_input req = {0}; | |
5420 | struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
6fe19886 | 5421 | struct bnxt_ring_mem_info *rmem = &ring->ring_mem; |
9899bb59 | 5422 | struct bnxt_ring_grp_info *grp_info; |
c0c050c5 MC |
5423 | u16 ring_id; |
5424 | ||
5425 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1); | |
5426 | ||
5427 | req.enables = 0; | |
6fe19886 MC |
5428 | if (rmem->nr_pages > 1) { |
5429 | req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map); | |
c0c050c5 MC |
5430 | /* Page size is in log2 units */ |
5431 | req.page_size = BNXT_PAGE_SHIFT; | |
5432 | req.page_tbl_depth = 1; | |
5433 | } else { | |
6fe19886 | 5434 | req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]); |
c0c050c5 MC |
5435 | } |
5436 | req.fbo = 0; | |
5437 | /* Association of ring index with doorbell index and MSIX number */ | |
5438 | req.logical_id = cpu_to_le16(map_index); | |
5439 | ||
5440 | switch (ring_type) { | |
2c61d211 MC |
5441 | case HWRM_RING_ALLOC_TX: { |
5442 | struct bnxt_tx_ring_info *txr; | |
5443 | ||
5444 | txr = container_of(ring, struct bnxt_tx_ring_info, | |
5445 | tx_ring_struct); | |
c0c050c5 MC |
5446 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX; |
5447 | /* Association of transmit ring with completion ring */ | |
9899bb59 | 5448 | grp_info = &bp->grp_info[ring->grp_idx]; |
2c61d211 | 5449 | req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr)); |
c0c050c5 | 5450 | req.length = cpu_to_le32(bp->tx_ring_mask + 1); |
9899bb59 | 5451 | req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); |
c0c050c5 MC |
5452 | req.queue_id = cpu_to_le16(ring->queue_id); |
5453 | break; | |
2c61d211 | 5454 | } |
c0c050c5 MC |
5455 | case HWRM_RING_ALLOC_RX: |
5456 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; | |
5457 | req.length = cpu_to_le32(bp->rx_ring_mask + 1); | |
23aefdd7 MC |
5458 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5459 | u16 flags = 0; | |
5460 | ||
5461 | /* Association of rx ring with stats context */ | |
5462 | grp_info = &bp->grp_info[ring->grp_idx]; | |
5463 | req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size); | |
5464 | req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); | |
5465 | req.enables |= cpu_to_le32( | |
5466 | RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); | |
5467 | if (NET_IP_ALIGN == 2) | |
5468 | flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD; | |
5469 | req.flags = cpu_to_le16(flags); | |
5470 | } | |
c0c050c5 MC |
5471 | break; |
5472 | case HWRM_RING_ALLOC_AGG: | |
23aefdd7 MC |
5473 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5474 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG; | |
5475 | /* Association of agg ring with rx ring */ | |
5476 | grp_info = &bp->grp_info[ring->grp_idx]; | |
5477 | req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id); | |
5478 | req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE); | |
5479 | req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); | |
5480 | req.enables |= cpu_to_le32( | |
5481 | RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID | | |
5482 | RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); | |
5483 | } else { | |
5484 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; | |
5485 | } | |
c0c050c5 MC |
5486 | req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1); |
5487 | break; | |
5488 | case HWRM_RING_ALLOC_CMPL: | |
bac9a7e0 | 5489 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL; |
c0c050c5 | 5490 | req.length = cpu_to_le32(bp->cp_ring_mask + 1); |
23aefdd7 MC |
5491 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5492 | /* Association of cp ring with nq */ | |
5493 | grp_info = &bp->grp_info[map_index]; | |
5494 | req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id); | |
5495 | req.cq_handle = cpu_to_le64(ring->handle); | |
5496 | req.enables |= cpu_to_le32( | |
5497 | RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID); | |
5498 | } else if (bp->flags & BNXT_FLAG_USING_MSIX) { | |
5499 | req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; | |
5500 | } | |
5501 | break; | |
5502 | case HWRM_RING_ALLOC_NQ: | |
5503 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ; | |
5504 | req.length = cpu_to_le32(bp->cp_ring_mask + 1); | |
c0c050c5 MC |
5505 | if (bp->flags & BNXT_FLAG_USING_MSIX) |
5506 | req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; | |
5507 | break; | |
5508 | default: | |
5509 | netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", | |
5510 | ring_type); | |
5511 | return -1; | |
5512 | } | |
5513 | ||
5514 | mutex_lock(&bp->hwrm_cmd_lock); | |
5515 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5516 | err = le16_to_cpu(resp->error_code); | |
5517 | ring_id = le16_to_cpu(resp->ring_id); | |
5518 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5519 | ||
5520 | if (rc || err) { | |
2727c888 MC |
5521 | netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n", |
5522 | ring_type, rc, err); | |
5523 | return -EIO; | |
c0c050c5 MC |
5524 | } |
5525 | ring->fw_ring_id = ring_id; | |
5526 | return rc; | |
5527 | } | |
5528 | ||
486b5c22 MC |
5529 | static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx) |
5530 | { | |
5531 | int rc; | |
5532 | ||
5533 | if (BNXT_PF(bp)) { | |
5534 | struct hwrm_func_cfg_input req = {0}; | |
5535 | ||
5536 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); | |
5537 | req.fid = cpu_to_le16(0xffff); | |
5538 | req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR); | |
5539 | req.async_event_cr = cpu_to_le16(idx); | |
5540 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5541 | } else { | |
5542 | struct hwrm_func_vf_cfg_input req = {0}; | |
5543 | ||
5544 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1); | |
5545 | req.enables = | |
5546 | cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR); | |
5547 | req.async_event_cr = cpu_to_le16(idx); | |
5548 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5549 | } | |
5550 | return rc; | |
5551 | } | |
5552 | ||
697197e5 MC |
5553 | static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type, |
5554 | u32 map_idx, u32 xid) | |
5555 | { | |
5556 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
5557 | if (BNXT_PF(bp)) | |
ebdf73dc | 5558 | db->doorbell = bp->bar1 + DB_PF_OFFSET_P5; |
697197e5 | 5559 | else |
ebdf73dc | 5560 | db->doorbell = bp->bar1 + DB_VF_OFFSET_P5; |
697197e5 MC |
5561 | switch (ring_type) { |
5562 | case HWRM_RING_ALLOC_TX: | |
5563 | db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ; | |
5564 | break; | |
5565 | case HWRM_RING_ALLOC_RX: | |
5566 | case HWRM_RING_ALLOC_AGG: | |
5567 | db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ; | |
5568 | break; | |
5569 | case HWRM_RING_ALLOC_CMPL: | |
5570 | db->db_key64 = DBR_PATH_L2; | |
5571 | break; | |
5572 | case HWRM_RING_ALLOC_NQ: | |
5573 | db->db_key64 = DBR_PATH_L2; | |
5574 | break; | |
5575 | } | |
5576 | db->db_key64 |= (u64)xid << DBR_XID_SFT; | |
5577 | } else { | |
5578 | db->doorbell = bp->bar1 + map_idx * 0x80; | |
5579 | switch (ring_type) { | |
5580 | case HWRM_RING_ALLOC_TX: | |
5581 | db->db_key32 = DB_KEY_TX; | |
5582 | break; | |
5583 | case HWRM_RING_ALLOC_RX: | |
5584 | case HWRM_RING_ALLOC_AGG: | |
5585 | db->db_key32 = DB_KEY_RX; | |
5586 | break; | |
5587 | case HWRM_RING_ALLOC_CMPL: | |
5588 | db->db_key32 = DB_KEY_CP; | |
5589 | break; | |
5590 | } | |
5591 | } | |
5592 | } | |
5593 | ||
c0c050c5 MC |
5594 | static int bnxt_hwrm_ring_alloc(struct bnxt *bp) |
5595 | { | |
e8f267b0 | 5596 | bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS); |
c0c050c5 | 5597 | int i, rc = 0; |
697197e5 | 5598 | u32 type; |
c0c050c5 | 5599 | |
23aefdd7 MC |
5600 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
5601 | type = HWRM_RING_ALLOC_NQ; | |
5602 | else | |
5603 | type = HWRM_RING_ALLOC_CMPL; | |
edd0c2cc MC |
5604 | for (i = 0; i < bp->cp_nr_rings; i++) { |
5605 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
5606 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
5607 | struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; | |
9899bb59 | 5608 | u32 map_idx = ring->map_idx; |
5e66e35a | 5609 | unsigned int vector; |
c0c050c5 | 5610 | |
5e66e35a MC |
5611 | vector = bp->irq_tbl[map_idx].vector; |
5612 | disable_irq_nosync(vector); | |
697197e5 | 5613 | rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); |
5e66e35a MC |
5614 | if (rc) { |
5615 | enable_irq(vector); | |
edd0c2cc | 5616 | goto err_out; |
5e66e35a | 5617 | } |
697197e5 MC |
5618 | bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id); |
5619 | bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); | |
5e66e35a | 5620 | enable_irq(vector); |
edd0c2cc | 5621 | bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; |
486b5c22 MC |
5622 | |
5623 | if (!i) { | |
5624 | rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id); | |
5625 | if (rc) | |
5626 | netdev_warn(bp->dev, "Failed to set async event completion ring.\n"); | |
5627 | } | |
c0c050c5 MC |
5628 | } |
5629 | ||
697197e5 | 5630 | type = HWRM_RING_ALLOC_TX; |
edd0c2cc | 5631 | for (i = 0; i < bp->tx_nr_rings; i++) { |
b6ab4b01 | 5632 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
3e08b184 MC |
5633 | struct bnxt_ring_struct *ring; |
5634 | u32 map_idx; | |
c0c050c5 | 5635 | |
3e08b184 MC |
5636 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5637 | struct bnxt_napi *bnapi = txr->bnapi; | |
5638 | struct bnxt_cp_ring_info *cpr, *cpr2; | |
5639 | u32 type2 = HWRM_RING_ALLOC_CMPL; | |
5640 | ||
5641 | cpr = &bnapi->cp_ring; | |
5642 | cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL]; | |
5643 | ring = &cpr2->cp_ring_struct; | |
5644 | ring->handle = BNXT_TX_HDL; | |
5645 | map_idx = bnapi->index; | |
5646 | rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); | |
5647 | if (rc) | |
5648 | goto err_out; | |
5649 | bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, | |
5650 | ring->fw_ring_id); | |
5651 | bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); | |
5652 | } | |
5653 | ring = &txr->tx_ring_struct; | |
5654 | map_idx = i; | |
697197e5 | 5655 | rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); |
edd0c2cc MC |
5656 | if (rc) |
5657 | goto err_out; | |
697197e5 | 5658 | bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id); |
c0c050c5 MC |
5659 | } |
5660 | ||
697197e5 | 5661 | type = HWRM_RING_ALLOC_RX; |
edd0c2cc | 5662 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 5663 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
edd0c2cc | 5664 | struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; |
3e08b184 MC |
5665 | struct bnxt_napi *bnapi = rxr->bnapi; |
5666 | u32 map_idx = bnapi->index; | |
c0c050c5 | 5667 | |
697197e5 | 5668 | rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); |
edd0c2cc MC |
5669 | if (rc) |
5670 | goto err_out; | |
697197e5 | 5671 | bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id); |
e8f267b0 MC |
5672 | /* If we have agg rings, post agg buffers first. */ |
5673 | if (!agg_rings) | |
5674 | bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); | |
b81a90d3 | 5675 | bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; |
3e08b184 MC |
5676 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5677 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
5678 | u32 type2 = HWRM_RING_ALLOC_CMPL; | |
5679 | struct bnxt_cp_ring_info *cpr2; | |
5680 | ||
5681 | cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL]; | |
5682 | ring = &cpr2->cp_ring_struct; | |
5683 | ring->handle = BNXT_RX_HDL; | |
5684 | rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); | |
5685 | if (rc) | |
5686 | goto err_out; | |
5687 | bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, | |
5688 | ring->fw_ring_id); | |
5689 | bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); | |
5690 | } | |
c0c050c5 MC |
5691 | } |
5692 | ||
e8f267b0 | 5693 | if (agg_rings) { |
697197e5 | 5694 | type = HWRM_RING_ALLOC_AGG; |
c0c050c5 | 5695 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 5696 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
c0c050c5 MC |
5697 | struct bnxt_ring_struct *ring = |
5698 | &rxr->rx_agg_ring_struct; | |
9899bb59 | 5699 | u32 grp_idx = ring->grp_idx; |
b81a90d3 | 5700 | u32 map_idx = grp_idx + bp->rx_nr_rings; |
c0c050c5 | 5701 | |
697197e5 | 5702 | rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); |
c0c050c5 MC |
5703 | if (rc) |
5704 | goto err_out; | |
5705 | ||
697197e5 MC |
5706 | bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx, |
5707 | ring->fw_ring_id); | |
5708 | bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); | |
e8f267b0 | 5709 | bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); |
b81a90d3 | 5710 | bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; |
c0c050c5 MC |
5711 | } |
5712 | } | |
5713 | err_out: | |
5714 | return rc; | |
5715 | } | |
5716 | ||
5717 | static int hwrm_ring_free_send_msg(struct bnxt *bp, | |
5718 | struct bnxt_ring_struct *ring, | |
5719 | u32 ring_type, int cmpl_ring_id) | |
5720 | { | |
5721 | int rc; | |
5722 | struct hwrm_ring_free_input req = {0}; | |
5723 | struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr; | |
5724 | u16 error_code; | |
5725 | ||
b4fff207 MC |
5726 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) |
5727 | return 0; | |
5728 | ||
74608fc9 | 5729 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1); |
c0c050c5 MC |
5730 | req.ring_type = ring_type; |
5731 | req.ring_id = cpu_to_le16(ring->fw_ring_id); | |
5732 | ||
5733 | mutex_lock(&bp->hwrm_cmd_lock); | |
5734 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5735 | error_code = le16_to_cpu(resp->error_code); | |
5736 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5737 | ||
5738 | if (rc || error_code) { | |
2727c888 MC |
5739 | netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n", |
5740 | ring_type, rc, error_code); | |
5741 | return -EIO; | |
c0c050c5 MC |
5742 | } |
5743 | return 0; | |
5744 | } | |
5745 | ||
edd0c2cc | 5746 | static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) |
c0c050c5 | 5747 | { |
23aefdd7 | 5748 | u32 type; |
edd0c2cc | 5749 | int i; |
c0c050c5 MC |
5750 | |
5751 | if (!bp->bnapi) | |
edd0c2cc | 5752 | return; |
c0c050c5 | 5753 | |
edd0c2cc | 5754 | for (i = 0; i < bp->tx_nr_rings; i++) { |
b6ab4b01 | 5755 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
edd0c2cc | 5756 | struct bnxt_ring_struct *ring = &txr->tx_ring_struct; |
edd0c2cc MC |
5757 | |
5758 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
1f83391b MC |
5759 | u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr); |
5760 | ||
edd0c2cc MC |
5761 | hwrm_ring_free_send_msg(bp, ring, |
5762 | RING_FREE_REQ_RING_TYPE_TX, | |
5763 | close_path ? cmpl_ring_id : | |
5764 | INVALID_HW_RING_ID); | |
5765 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
c0c050c5 MC |
5766 | } |
5767 | } | |
5768 | ||
edd0c2cc | 5769 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 5770 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
edd0c2cc | 5771 | struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; |
b81a90d3 | 5772 | u32 grp_idx = rxr->bnapi->index; |
edd0c2cc MC |
5773 | |
5774 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
1f83391b MC |
5775 | u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); |
5776 | ||
edd0c2cc MC |
5777 | hwrm_ring_free_send_msg(bp, ring, |
5778 | RING_FREE_REQ_RING_TYPE_RX, | |
5779 | close_path ? cmpl_ring_id : | |
5780 | INVALID_HW_RING_ID); | |
5781 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
b81a90d3 MC |
5782 | bp->grp_info[grp_idx].rx_fw_ring_id = |
5783 | INVALID_HW_RING_ID; | |
c0c050c5 MC |
5784 | } |
5785 | } | |
5786 | ||
23aefdd7 MC |
5787 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
5788 | type = RING_FREE_REQ_RING_TYPE_RX_AGG; | |
5789 | else | |
5790 | type = RING_FREE_REQ_RING_TYPE_RX; | |
edd0c2cc | 5791 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 5792 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
edd0c2cc | 5793 | struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; |
b81a90d3 | 5794 | u32 grp_idx = rxr->bnapi->index; |
edd0c2cc MC |
5795 | |
5796 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
1f83391b MC |
5797 | u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); |
5798 | ||
23aefdd7 | 5799 | hwrm_ring_free_send_msg(bp, ring, type, |
edd0c2cc MC |
5800 | close_path ? cmpl_ring_id : |
5801 | INVALID_HW_RING_ID); | |
5802 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
b81a90d3 MC |
5803 | bp->grp_info[grp_idx].agg_fw_ring_id = |
5804 | INVALID_HW_RING_ID; | |
c0c050c5 MC |
5805 | } |
5806 | } | |
5807 | ||
9d8bc097 MC |
5808 | /* The completion rings are about to be freed. After that the |
5809 | * IRQ doorbell will not work anymore. So we need to disable | |
5810 | * IRQ here. | |
5811 | */ | |
5812 | bnxt_disable_int_sync(bp); | |
5813 | ||
23aefdd7 MC |
5814 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
5815 | type = RING_FREE_REQ_RING_TYPE_NQ; | |
5816 | else | |
5817 | type = RING_FREE_REQ_RING_TYPE_L2_CMPL; | |
edd0c2cc MC |
5818 | for (i = 0; i < bp->cp_nr_rings; i++) { |
5819 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
5820 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
3e08b184 MC |
5821 | struct bnxt_ring_struct *ring; |
5822 | int j; | |
edd0c2cc | 5823 | |
3e08b184 MC |
5824 | for (j = 0; j < 2; j++) { |
5825 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; | |
5826 | ||
5827 | if (cpr2) { | |
5828 | ring = &cpr2->cp_ring_struct; | |
5829 | if (ring->fw_ring_id == INVALID_HW_RING_ID) | |
5830 | continue; | |
5831 | hwrm_ring_free_send_msg(bp, ring, | |
5832 | RING_FREE_REQ_RING_TYPE_L2_CMPL, | |
5833 | INVALID_HW_RING_ID); | |
5834 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
5835 | } | |
5836 | } | |
5837 | ring = &cpr->cp_ring_struct; | |
edd0c2cc | 5838 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { |
23aefdd7 | 5839 | hwrm_ring_free_send_msg(bp, ring, type, |
edd0c2cc MC |
5840 | INVALID_HW_RING_ID); |
5841 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
5842 | bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; | |
c0c050c5 MC |
5843 | } |
5844 | } | |
c0c050c5 MC |
5845 | } |
5846 | ||
41e8d798 MC |
5847 | static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, |
5848 | bool shared); | |
5849 | ||
674f50a5 MC |
5850 | static int bnxt_hwrm_get_rings(struct bnxt *bp) |
5851 | { | |
5852 | struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
5853 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
5854 | struct hwrm_func_qcfg_input req = {0}; | |
5855 | int rc; | |
5856 | ||
5857 | if (bp->hwrm_spec_code < 0x10601) | |
5858 | return 0; | |
5859 | ||
5860 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); | |
5861 | req.fid = cpu_to_le16(0xffff); | |
5862 | mutex_lock(&bp->hwrm_cmd_lock); | |
5863 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5864 | if (rc) { | |
5865 | mutex_unlock(&bp->hwrm_cmd_lock); | |
d4f1420d | 5866 | return rc; |
674f50a5 MC |
5867 | } |
5868 | ||
5869 | hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings); | |
f1ca94de | 5870 | if (BNXT_NEW_RM(bp)) { |
674f50a5 MC |
5871 | u16 cp, stats; |
5872 | ||
5873 | hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings); | |
5874 | hw_resc->resv_hw_ring_grps = | |
5875 | le32_to_cpu(resp->alloc_hw_ring_grps); | |
5876 | hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics); | |
5877 | cp = le16_to_cpu(resp->alloc_cmpl_rings); | |
5878 | stats = le16_to_cpu(resp->alloc_stat_ctx); | |
75720e63 | 5879 | hw_resc->resv_irqs = cp; |
41e8d798 MC |
5880 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5881 | int rx = hw_resc->resv_rx_rings; | |
5882 | int tx = hw_resc->resv_tx_rings; | |
5883 | ||
5884 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
5885 | rx >>= 1; | |
5886 | if (cp < (rx + tx)) { | |
5887 | bnxt_trim_rings(bp, &rx, &tx, cp, false); | |
5888 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
5889 | rx <<= 1; | |
5890 | hw_resc->resv_rx_rings = rx; | |
5891 | hw_resc->resv_tx_rings = tx; | |
5892 | } | |
75720e63 | 5893 | hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix); |
41e8d798 MC |
5894 | hw_resc->resv_hw_ring_grps = rx; |
5895 | } | |
674f50a5 | 5896 | hw_resc->resv_cp_rings = cp; |
780baad4 | 5897 | hw_resc->resv_stat_ctxs = stats; |
674f50a5 MC |
5898 | } |
5899 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5900 | return 0; | |
5901 | } | |
5902 | ||
391be5c2 MC |
5903 | /* Caller must hold bp->hwrm_cmd_lock */ |
5904 | int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings) | |
5905 | { | |
5906 | struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
5907 | struct hwrm_func_qcfg_input req = {0}; | |
5908 | int rc; | |
5909 | ||
5910 | if (bp->hwrm_spec_code < 0x10601) | |
5911 | return 0; | |
5912 | ||
5913 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); | |
5914 | req.fid = cpu_to_le16(fid); | |
5915 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5916 | if (!rc) | |
5917 | *tx_rings = le16_to_cpu(resp->alloc_tx_rings); | |
5918 | ||
5919 | return rc; | |
5920 | } | |
5921 | ||
41e8d798 MC |
5922 | static bool bnxt_rfs_supported(struct bnxt *bp); |
5923 | ||
4ed50ef4 MC |
5924 | static void |
5925 | __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req, | |
5926 | int tx_rings, int rx_rings, int ring_grps, | |
780baad4 | 5927 | int cp_rings, int stats, int vnics) |
391be5c2 | 5928 | { |
674f50a5 | 5929 | u32 enables = 0; |
391be5c2 | 5930 | |
4ed50ef4 MC |
5931 | bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1); |
5932 | req->fid = cpu_to_le16(0xffff); | |
674f50a5 | 5933 | enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; |
4ed50ef4 | 5934 | req->num_tx_rings = cpu_to_le16(tx_rings); |
f1ca94de | 5935 | if (BNXT_NEW_RM(bp)) { |
674f50a5 | 5936 | enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0; |
3f93cd3f | 5937 | enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; |
41e8d798 MC |
5938 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5939 | enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0; | |
5940 | enables |= tx_rings + ring_grps ? | |
3f93cd3f | 5941 | FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; |
41e8d798 MC |
5942 | enables |= rx_rings ? |
5943 | FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; | |
5944 | } else { | |
5945 | enables |= cp_rings ? | |
3f93cd3f | 5946 | FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; |
41e8d798 MC |
5947 | enables |= ring_grps ? |
5948 | FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS | | |
5949 | FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; | |
5950 | } | |
dbe80d44 | 5951 | enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0; |
674f50a5 | 5952 | |
4ed50ef4 | 5953 | req->num_rx_rings = cpu_to_le16(rx_rings); |
41e8d798 MC |
5954 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5955 | req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); | |
5956 | req->num_msix = cpu_to_le16(cp_rings); | |
5957 | req->num_rsscos_ctxs = | |
5958 | cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); | |
5959 | } else { | |
5960 | req->num_cmpl_rings = cpu_to_le16(cp_rings); | |
5961 | req->num_hw_ring_grps = cpu_to_le16(ring_grps); | |
5962 | req->num_rsscos_ctxs = cpu_to_le16(1); | |
5963 | if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) && | |
5964 | bnxt_rfs_supported(bp)) | |
5965 | req->num_rsscos_ctxs = | |
5966 | cpu_to_le16(ring_grps + 1); | |
5967 | } | |
780baad4 | 5968 | req->num_stat_ctxs = cpu_to_le16(stats); |
4ed50ef4 | 5969 | req->num_vnics = cpu_to_le16(vnics); |
674f50a5 | 5970 | } |
4ed50ef4 MC |
5971 | req->enables = cpu_to_le32(enables); |
5972 | } | |
5973 | ||
5974 | static void | |
5975 | __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, | |
5976 | struct hwrm_func_vf_cfg_input *req, int tx_rings, | |
5977 | int rx_rings, int ring_grps, int cp_rings, | |
780baad4 | 5978 | int stats, int vnics) |
4ed50ef4 MC |
5979 | { |
5980 | u32 enables = 0; | |
5981 | ||
5982 | bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1); | |
5983 | enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; | |
41e8d798 MC |
5984 | enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS | |
5985 | FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; | |
3f93cd3f | 5986 | enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; |
41e8d798 MC |
5987 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5988 | enables |= tx_rings + ring_grps ? | |
3f93cd3f | 5989 | FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; |
41e8d798 MC |
5990 | } else { |
5991 | enables |= cp_rings ? | |
3f93cd3f | 5992 | FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; |
41e8d798 MC |
5993 | enables |= ring_grps ? |
5994 | FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0; | |
5995 | } | |
4ed50ef4 | 5996 | enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0; |
41e8d798 | 5997 | enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS; |
4ed50ef4 | 5998 | |
41e8d798 | 5999 | req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX); |
4ed50ef4 MC |
6000 | req->num_tx_rings = cpu_to_le16(tx_rings); |
6001 | req->num_rx_rings = cpu_to_le16(rx_rings); | |
41e8d798 MC |
6002 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
6003 | req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); | |
6004 | req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); | |
6005 | } else { | |
6006 | req->num_cmpl_rings = cpu_to_le16(cp_rings); | |
6007 | req->num_hw_ring_grps = cpu_to_le16(ring_grps); | |
6008 | req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX); | |
6009 | } | |
780baad4 | 6010 | req->num_stat_ctxs = cpu_to_le16(stats); |
4ed50ef4 MC |
6011 | req->num_vnics = cpu_to_le16(vnics); |
6012 | ||
6013 | req->enables = cpu_to_le32(enables); | |
6014 | } | |
6015 | ||
6016 | static int | |
6017 | bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, | |
780baad4 | 6018 | int ring_grps, int cp_rings, int stats, int vnics) |
4ed50ef4 MC |
6019 | { |
6020 | struct hwrm_func_cfg_input req = {0}; | |
6021 | int rc; | |
6022 | ||
6023 | __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, | |
780baad4 | 6024 | cp_rings, stats, vnics); |
4ed50ef4 | 6025 | if (!req.enables) |
391be5c2 MC |
6026 | return 0; |
6027 | ||
674f50a5 MC |
6028 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
6029 | if (rc) | |
d4f1420d | 6030 | return rc; |
674f50a5 MC |
6031 | |
6032 | if (bp->hwrm_spec_code < 0x10601) | |
6033 | bp->hw_resc.resv_tx_rings = tx_rings; | |
6034 | ||
9f90445c | 6035 | return bnxt_hwrm_get_rings(bp); |
674f50a5 MC |
6036 | } |
6037 | ||
6038 | static int | |
6039 | bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, | |
780baad4 | 6040 | int ring_grps, int cp_rings, int stats, int vnics) |
674f50a5 MC |
6041 | { |
6042 | struct hwrm_func_vf_cfg_input req = {0}; | |
674f50a5 MC |
6043 | int rc; |
6044 | ||
f1ca94de | 6045 | if (!BNXT_NEW_RM(bp)) { |
674f50a5 | 6046 | bp->hw_resc.resv_tx_rings = tx_rings; |
391be5c2 | 6047 | return 0; |
674f50a5 | 6048 | } |
391be5c2 | 6049 | |
4ed50ef4 | 6050 | __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, |
780baad4 | 6051 | cp_rings, stats, vnics); |
391be5c2 | 6052 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
674f50a5 | 6053 | if (rc) |
d4f1420d | 6054 | return rc; |
674f50a5 | 6055 | |
9f90445c | 6056 | return bnxt_hwrm_get_rings(bp); |
674f50a5 MC |
6057 | } |
6058 | ||
6059 | static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp, | |
780baad4 | 6060 | int cp, int stat, int vnic) |
674f50a5 MC |
6061 | { |
6062 | if (BNXT_PF(bp)) | |
780baad4 VV |
6063 | return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat, |
6064 | vnic); | |
674f50a5 | 6065 | else |
780baad4 VV |
6066 | return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat, |
6067 | vnic); | |
674f50a5 MC |
6068 | } |
6069 | ||
b16b6891 | 6070 | int bnxt_nq_rings_in_use(struct bnxt *bp) |
08654eb2 MC |
6071 | { |
6072 | int cp = bp->cp_nr_rings; | |
6073 | int ulp_msix, ulp_base; | |
6074 | ||
6075 | ulp_msix = bnxt_get_ulp_msix_num(bp); | |
6076 | if (ulp_msix) { | |
6077 | ulp_base = bnxt_get_ulp_msix_base(bp); | |
6078 | cp += ulp_msix; | |
6079 | if ((ulp_base + ulp_msix) > cp) | |
6080 | cp = ulp_base + ulp_msix; | |
6081 | } | |
6082 | return cp; | |
6083 | } | |
6084 | ||
c0b8cda0 MC |
6085 | static int bnxt_cp_rings_in_use(struct bnxt *bp) |
6086 | { | |
6087 | int cp; | |
6088 | ||
6089 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
6090 | return bnxt_nq_rings_in_use(bp); | |
6091 | ||
6092 | cp = bp->tx_nr_rings + bp->rx_nr_rings; | |
6093 | return cp; | |
6094 | } | |
6095 | ||
780baad4 VV |
6096 | static int bnxt_get_func_stat_ctxs(struct bnxt *bp) |
6097 | { | |
d77b1ad8 MC |
6098 | int ulp_stat = bnxt_get_ulp_stat_ctxs(bp); |
6099 | int cp = bp->cp_nr_rings; | |
6100 | ||
6101 | if (!ulp_stat) | |
6102 | return cp; | |
6103 | ||
6104 | if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp)) | |
6105 | return bnxt_get_ulp_msix_base(bp) + ulp_stat; | |
6106 | ||
6107 | return cp + ulp_stat; | |
780baad4 VV |
6108 | } |
6109 | ||
4e41dc5d MC |
6110 | static bool bnxt_need_reserve_rings(struct bnxt *bp) |
6111 | { | |
6112 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
fbcfc8e4 | 6113 | int cp = bnxt_cp_rings_in_use(bp); |
c0b8cda0 | 6114 | int nq = bnxt_nq_rings_in_use(bp); |
780baad4 | 6115 | int rx = bp->rx_nr_rings, stat; |
4e41dc5d MC |
6116 | int vnic = 1, grp = rx; |
6117 | ||
6118 | if (bp->hwrm_spec_code < 0x10601) | |
6119 | return false; | |
6120 | ||
6121 | if (hw_resc->resv_tx_rings != bp->tx_nr_rings) | |
6122 | return true; | |
6123 | ||
41e8d798 | 6124 | if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) |
4e41dc5d MC |
6125 | vnic = rx + 1; |
6126 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
6127 | rx <<= 1; | |
780baad4 | 6128 | stat = bnxt_get_func_stat_ctxs(bp); |
f1ca94de | 6129 | if (BNXT_NEW_RM(bp) && |
4e41dc5d | 6130 | (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp || |
01989c6b | 6131 | hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat || |
41e8d798 MC |
6132 | (hw_resc->resv_hw_ring_grps != grp && |
6133 | !(bp->flags & BNXT_FLAG_CHIP_P5)))) | |
4e41dc5d | 6134 | return true; |
01989c6b MC |
6135 | if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) && |
6136 | hw_resc->resv_irqs != nq) | |
6137 | return true; | |
4e41dc5d MC |
6138 | return false; |
6139 | } | |
6140 | ||
674f50a5 MC |
6141 | static int __bnxt_reserve_rings(struct bnxt *bp) |
6142 | { | |
6143 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
c0b8cda0 | 6144 | int cp = bnxt_nq_rings_in_use(bp); |
674f50a5 MC |
6145 | int tx = bp->tx_nr_rings; |
6146 | int rx = bp->rx_nr_rings; | |
674f50a5 | 6147 | int grp, rx_rings, rc; |
780baad4 | 6148 | int vnic = 1, stat; |
674f50a5 | 6149 | bool sh = false; |
674f50a5 | 6150 | |
4e41dc5d | 6151 | if (!bnxt_need_reserve_rings(bp)) |
674f50a5 MC |
6152 | return 0; |
6153 | ||
6154 | if (bp->flags & BNXT_FLAG_SHARED_RINGS) | |
6155 | sh = true; | |
41e8d798 | 6156 | if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) |
674f50a5 MC |
6157 | vnic = rx + 1; |
6158 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
6159 | rx <<= 1; | |
674f50a5 | 6160 | grp = bp->rx_nr_rings; |
780baad4 | 6161 | stat = bnxt_get_func_stat_ctxs(bp); |
674f50a5 | 6162 | |
780baad4 | 6163 | rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic); |
391be5c2 MC |
6164 | if (rc) |
6165 | return rc; | |
6166 | ||
674f50a5 | 6167 | tx = hw_resc->resv_tx_rings; |
f1ca94de | 6168 | if (BNXT_NEW_RM(bp)) { |
674f50a5 | 6169 | rx = hw_resc->resv_rx_rings; |
c0b8cda0 | 6170 | cp = hw_resc->resv_irqs; |
674f50a5 MC |
6171 | grp = hw_resc->resv_hw_ring_grps; |
6172 | vnic = hw_resc->resv_vnics; | |
780baad4 | 6173 | stat = hw_resc->resv_stat_ctxs; |
674f50a5 MC |
6174 | } |
6175 | ||
6176 | rx_rings = rx; | |
6177 | if (bp->flags & BNXT_FLAG_AGG_RINGS) { | |
6178 | if (rx >= 2) { | |
6179 | rx_rings = rx >> 1; | |
6180 | } else { | |
6181 | if (netif_running(bp->dev)) | |
6182 | return -ENOMEM; | |
6183 | ||
6184 | bp->flags &= ~BNXT_FLAG_AGG_RINGS; | |
6185 | bp->flags |= BNXT_FLAG_NO_AGG_RINGS; | |
6186 | bp->dev->hw_features &= ~NETIF_F_LRO; | |
6187 | bp->dev->features &= ~NETIF_F_LRO; | |
6188 | bnxt_set_ring_params(bp); | |
6189 | } | |
6190 | } | |
6191 | rx_rings = min_t(int, rx_rings, grp); | |
780baad4 VV |
6192 | cp = min_t(int, cp, bp->cp_nr_rings); |
6193 | if (stat > bnxt_get_ulp_stat_ctxs(bp)) | |
6194 | stat -= bnxt_get_ulp_stat_ctxs(bp); | |
6195 | cp = min_t(int, cp, stat); | |
674f50a5 MC |
6196 | rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh); |
6197 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
6198 | rx = rx_rings << 1; | |
6199 | cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings; | |
6200 | bp->tx_nr_rings = tx; | |
bd3191b5 MC |
6201 | |
6202 | /* If we cannot reserve all the RX rings, reset the RSS map only | |
6203 | * if absolutely necessary | |
6204 | */ | |
6205 | if (rx_rings != bp->rx_nr_rings) { | |
6206 | netdev_warn(bp->dev, "Able to reserve only %d out of %d requested RX rings\n", | |
6207 | rx_rings, bp->rx_nr_rings); | |
6208 | if ((bp->dev->priv_flags & IFF_RXFH_CONFIGURED) && | |
6209 | (bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) != | |
6210 | bnxt_get_nr_rss_ctxs(bp, rx_rings) || | |
6211 | bnxt_get_max_rss_ring(bp) >= rx_rings)) { | |
6212 | netdev_warn(bp->dev, "RSS table entries reverting to default\n"); | |
6213 | bp->dev->priv_flags &= ~IFF_RXFH_CONFIGURED; | |
6214 | } | |
6215 | } | |
674f50a5 MC |
6216 | bp->rx_nr_rings = rx_rings; |
6217 | bp->cp_nr_rings = cp; | |
6218 | ||
780baad4 | 6219 | if (!tx || !rx || !cp || !grp || !vnic || !stat) |
674f50a5 MC |
6220 | return -ENOMEM; |
6221 | ||
391be5c2 MC |
6222 | return rc; |
6223 | } | |
6224 | ||
8f23d638 | 6225 | static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, |
780baad4 VV |
6226 | int ring_grps, int cp_rings, int stats, |
6227 | int vnics) | |
98fdbe73 | 6228 | { |
8f23d638 | 6229 | struct hwrm_func_vf_cfg_input req = {0}; |
6fc2ffdf | 6230 | u32 flags; |
98fdbe73 | 6231 | |
f1ca94de | 6232 | if (!BNXT_NEW_RM(bp)) |
98fdbe73 MC |
6233 | return 0; |
6234 | ||
6fc2ffdf | 6235 | __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, |
780baad4 | 6236 | cp_rings, stats, vnics); |
8f23d638 MC |
6237 | flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST | |
6238 | FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST | | |
6239 | FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | | |
8f23d638 | 6240 | FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | |
41e8d798 MC |
6241 | FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST | |
6242 | FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST; | |
6243 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
6244 | flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; | |
8f23d638 MC |
6245 | |
6246 | req.flags = cpu_to_le32(flags); | |
9f90445c VV |
6247 | return hwrm_send_message_silent(bp, &req, sizeof(req), |
6248 | HWRM_CMD_TIMEOUT); | |
8f23d638 MC |
6249 | } |
6250 | ||
6251 | static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, | |
780baad4 VV |
6252 | int ring_grps, int cp_rings, int stats, |
6253 | int vnics) | |
8f23d638 MC |
6254 | { |
6255 | struct hwrm_func_cfg_input req = {0}; | |
6fc2ffdf | 6256 | u32 flags; |
98fdbe73 | 6257 | |
6fc2ffdf | 6258 | __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, |
780baad4 | 6259 | cp_rings, stats, vnics); |
8f23d638 | 6260 | flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST; |
41e8d798 | 6261 | if (BNXT_NEW_RM(bp)) { |
8f23d638 MC |
6262 | flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST | |
6263 | FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | | |
8f23d638 MC |
6264 | FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | |
6265 | FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST; | |
41e8d798 | 6266 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
0b815023 MC |
6267 | flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST | |
6268 | FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST; | |
41e8d798 MC |
6269 | else |
6270 | flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; | |
6271 | } | |
6fc2ffdf | 6272 | |
8f23d638 | 6273 | req.flags = cpu_to_le32(flags); |
9f90445c VV |
6274 | return hwrm_send_message_silent(bp, &req, sizeof(req), |
6275 | HWRM_CMD_TIMEOUT); | |
98fdbe73 MC |
6276 | } |
6277 | ||
8f23d638 | 6278 | static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings, |
780baad4 VV |
6279 | int ring_grps, int cp_rings, int stats, |
6280 | int vnics) | |
8f23d638 MC |
6281 | { |
6282 | if (bp->hwrm_spec_code < 0x10801) | |
6283 | return 0; | |
6284 | ||
6285 | if (BNXT_PF(bp)) | |
6286 | return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings, | |
780baad4 VV |
6287 | ring_grps, cp_rings, stats, |
6288 | vnics); | |
8f23d638 MC |
6289 | |
6290 | return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps, | |
780baad4 | 6291 | cp_rings, stats, vnics); |
8f23d638 MC |
6292 | } |
6293 | ||
74706afa MC |
6294 | static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp) |
6295 | { | |
6296 | struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
6297 | struct bnxt_coal_cap *coal_cap = &bp->coal_cap; | |
6298 | struct hwrm_ring_aggint_qcaps_input req = {0}; | |
6299 | int rc; | |
6300 | ||
6301 | coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS; | |
6302 | coal_cap->num_cmpl_dma_aggr_max = 63; | |
6303 | coal_cap->num_cmpl_dma_aggr_during_int_max = 63; | |
6304 | coal_cap->cmpl_aggr_dma_tmr_max = 65535; | |
6305 | coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535; | |
6306 | coal_cap->int_lat_tmr_min_max = 65535; | |
6307 | coal_cap->int_lat_tmr_max_max = 65535; | |
6308 | coal_cap->num_cmpl_aggr_int_max = 65535; | |
6309 | coal_cap->timer_units = 80; | |
6310 | ||
6311 | if (bp->hwrm_spec_code < 0x10902) | |
6312 | return; | |
6313 | ||
6314 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1); | |
6315 | mutex_lock(&bp->hwrm_cmd_lock); | |
6316 | rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
6317 | if (!rc) { | |
6318 | coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params); | |
58590c8d | 6319 | coal_cap->nq_params = le32_to_cpu(resp->nq_params); |
74706afa MC |
6320 | coal_cap->num_cmpl_dma_aggr_max = |
6321 | le16_to_cpu(resp->num_cmpl_dma_aggr_max); | |
6322 | coal_cap->num_cmpl_dma_aggr_during_int_max = | |
6323 | le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max); | |
6324 | coal_cap->cmpl_aggr_dma_tmr_max = | |
6325 | le16_to_cpu(resp->cmpl_aggr_dma_tmr_max); | |
6326 | coal_cap->cmpl_aggr_dma_tmr_during_int_max = | |
6327 | le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max); | |
6328 | coal_cap->int_lat_tmr_min_max = | |
6329 | le16_to_cpu(resp->int_lat_tmr_min_max); | |
6330 | coal_cap->int_lat_tmr_max_max = | |
6331 | le16_to_cpu(resp->int_lat_tmr_max_max); | |
6332 | coal_cap->num_cmpl_aggr_int_max = | |
6333 | le16_to_cpu(resp->num_cmpl_aggr_int_max); | |
6334 | coal_cap->timer_units = le16_to_cpu(resp->timer_units); | |
6335 | } | |
6336 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6337 | } | |
6338 | ||
6339 | static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec) | |
6340 | { | |
6341 | struct bnxt_coal_cap *coal_cap = &bp->coal_cap; | |
6342 | ||
6343 | return usec * 1000 / coal_cap->timer_units; | |
6344 | } | |
6345 | ||
6346 | static void bnxt_hwrm_set_coal_params(struct bnxt *bp, | |
6347 | struct bnxt_coal *hw_coal, | |
bb053f52 MC |
6348 | struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req) |
6349 | { | |
74706afa MC |
6350 | struct bnxt_coal_cap *coal_cap = &bp->coal_cap; |
6351 | u32 cmpl_params = coal_cap->cmpl_params; | |
6352 | u16 val, tmr, max, flags = 0; | |
f8503969 MC |
6353 | |
6354 | max = hw_coal->bufs_per_record * 128; | |
6355 | if (hw_coal->budget) | |
6356 | max = hw_coal->bufs_per_record * hw_coal->budget; | |
74706afa | 6357 | max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max); |
f8503969 MC |
6358 | |
6359 | val = clamp_t(u16, hw_coal->coal_bufs, 1, max); | |
6360 | req->num_cmpl_aggr_int = cpu_to_le16(val); | |
b153cbc5 | 6361 | |
74706afa | 6362 | val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max); |
f8503969 MC |
6363 | req->num_cmpl_dma_aggr = cpu_to_le16(val); |
6364 | ||
74706afa MC |
6365 | val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, |
6366 | coal_cap->num_cmpl_dma_aggr_during_int_max); | |
f8503969 MC |
6367 | req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val); |
6368 | ||
74706afa MC |
6369 | tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks); |
6370 | tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max); | |
f8503969 MC |
6371 | req->int_lat_tmr_max = cpu_to_le16(tmr); |
6372 | ||
6373 | /* min timer set to 1/2 of interrupt timer */ | |
74706afa MC |
6374 | if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) { |
6375 | val = tmr / 2; | |
6376 | val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max); | |
6377 | req->int_lat_tmr_min = cpu_to_le16(val); | |
6378 | req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); | |
6379 | } | |
f8503969 MC |
6380 | |
6381 | /* buf timer set to 1/4 of interrupt timer */ | |
74706afa | 6382 | val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max); |
f8503969 MC |
6383 | req->cmpl_aggr_dma_tmr = cpu_to_le16(val); |
6384 | ||
74706afa MC |
6385 | if (cmpl_params & |
6386 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) { | |
6387 | tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq); | |
6388 | val = clamp_t(u16, tmr, 1, | |
6389 | coal_cap->cmpl_aggr_dma_tmr_during_int_max); | |
6adc4601 | 6390 | req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val); |
74706afa MC |
6391 | req->enables |= |
6392 | cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE); | |
6393 | } | |
f8503969 | 6394 | |
74706afa MC |
6395 | if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET) |
6396 | flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; | |
6397 | if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) && | |
6398 | hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh) | |
f8503969 | 6399 | flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; |
bb053f52 | 6400 | req->flags = cpu_to_le16(flags); |
74706afa | 6401 | req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES); |
bb053f52 MC |
6402 | } |
6403 | ||
58590c8d MC |
6404 | /* Caller holds bp->hwrm_cmd_lock */ |
6405 | static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi, | |
6406 | struct bnxt_coal *hw_coal) | |
6407 | { | |
6408 | struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0}; | |
6409 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
6410 | struct bnxt_coal_cap *coal_cap = &bp->coal_cap; | |
6411 | u32 nq_params = coal_cap->nq_params; | |
6412 | u16 tmr; | |
6413 | ||
6414 | if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN)) | |
6415 | return 0; | |
6416 | ||
6417 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, | |
6418 | -1, -1); | |
6419 | req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id); | |
6420 | req.flags = | |
6421 | cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ); | |
6422 | ||
6423 | tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2; | |
6424 | tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max); | |
6425 | req.int_lat_tmr_min = cpu_to_le16(tmr); | |
6426 | req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); | |
6427 | return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
6428 | } | |
6429 | ||
6a8788f2 AG |
6430 | int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi) |
6431 | { | |
6432 | struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}; | |
6433 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
6434 | struct bnxt_coal coal; | |
6a8788f2 AG |
6435 | |
6436 | /* Tick values in micro seconds. | |
6437 | * 1 coal_buf x bufs_per_record = 1 completion record. | |
6438 | */ | |
6439 | memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal)); | |
6440 | ||
6441 | coal.coal_ticks = cpr->rx_ring_coal.coal_ticks; | |
6442 | coal.coal_bufs = cpr->rx_ring_coal.coal_bufs; | |
6443 | ||
6444 | if (!bnapi->rx_ring) | |
6445 | return -ENODEV; | |
6446 | ||
6447 | bnxt_hwrm_cmd_hdr_init(bp, &req_rx, | |
6448 | HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); | |
6449 | ||
74706afa | 6450 | bnxt_hwrm_set_coal_params(bp, &coal, &req_rx); |
6a8788f2 | 6451 | |
2c61d211 | 6452 | req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring)); |
6a8788f2 AG |
6453 | |
6454 | return hwrm_send_message(bp, &req_rx, sizeof(req_rx), | |
6455 | HWRM_CMD_TIMEOUT); | |
6456 | } | |
6457 | ||
c0c050c5 MC |
6458 | int bnxt_hwrm_set_coal(struct bnxt *bp) |
6459 | { | |
6460 | int i, rc = 0; | |
dfc9c94a MC |
6461 | struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}, |
6462 | req_tx = {0}, *req; | |
c0c050c5 | 6463 | |
dfc9c94a MC |
6464 | bnxt_hwrm_cmd_hdr_init(bp, &req_rx, |
6465 | HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); | |
6466 | bnxt_hwrm_cmd_hdr_init(bp, &req_tx, | |
6467 | HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); | |
c0c050c5 | 6468 | |
74706afa MC |
6469 | bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx); |
6470 | bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx); | |
c0c050c5 MC |
6471 | |
6472 | mutex_lock(&bp->hwrm_cmd_lock); | |
6473 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
dfc9c94a | 6474 | struct bnxt_napi *bnapi = bp->bnapi[i]; |
58590c8d | 6475 | struct bnxt_coal *hw_coal; |
2c61d211 | 6476 | u16 ring_id; |
c0c050c5 | 6477 | |
dfc9c94a | 6478 | req = &req_rx; |
2c61d211 MC |
6479 | if (!bnapi->rx_ring) { |
6480 | ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); | |
dfc9c94a | 6481 | req = &req_tx; |
2c61d211 MC |
6482 | } else { |
6483 | ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring); | |
6484 | } | |
6485 | req->ring_id = cpu_to_le16(ring_id); | |
dfc9c94a MC |
6486 | |
6487 | rc = _hwrm_send_message(bp, req, sizeof(*req), | |
c0c050c5 MC |
6488 | HWRM_CMD_TIMEOUT); |
6489 | if (rc) | |
6490 | break; | |
58590c8d MC |
6491 | |
6492 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
6493 | continue; | |
6494 | ||
6495 | if (bnapi->rx_ring && bnapi->tx_ring) { | |
6496 | req = &req_tx; | |
6497 | ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); | |
6498 | req->ring_id = cpu_to_le16(ring_id); | |
6499 | rc = _hwrm_send_message(bp, req, sizeof(*req), | |
6500 | HWRM_CMD_TIMEOUT); | |
6501 | if (rc) | |
6502 | break; | |
6503 | } | |
6504 | if (bnapi->rx_ring) | |
6505 | hw_coal = &bp->rx_coal; | |
6506 | else | |
6507 | hw_coal = &bp->tx_coal; | |
6508 | __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal); | |
c0c050c5 MC |
6509 | } |
6510 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6511 | return rc; | |
6512 | } | |
6513 | ||
3d061591 | 6514 | static void bnxt_hwrm_stat_ctx_free(struct bnxt *bp) |
c0c050c5 | 6515 | { |
c2dec363 | 6516 | struct hwrm_stat_ctx_clr_stats_input req0 = {0}; |
c0c050c5 | 6517 | struct hwrm_stat_ctx_free_input req = {0}; |
3d061591 | 6518 | int i; |
c0c050c5 MC |
6519 | |
6520 | if (!bp->bnapi) | |
3d061591 | 6521 | return; |
c0c050c5 | 6522 | |
3e8060fa | 6523 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) |
3d061591 | 6524 | return; |
3e8060fa | 6525 | |
c2dec363 | 6526 | bnxt_hwrm_cmd_hdr_init(bp, &req0, HWRM_STAT_CTX_CLR_STATS, -1, -1); |
c0c050c5 MC |
6527 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1); |
6528 | ||
6529 | mutex_lock(&bp->hwrm_cmd_lock); | |
6530 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
6531 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
6532 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
6533 | ||
6534 | if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { | |
6535 | req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); | |
c2dec363 MC |
6536 | if (BNXT_FW_MAJ(bp) <= 20) { |
6537 | req0.stat_ctx_id = req.stat_ctx_id; | |
6538 | _hwrm_send_message(bp, &req0, sizeof(req0), | |
6539 | HWRM_CMD_TIMEOUT); | |
6540 | } | |
3d061591 VV |
6541 | _hwrm_send_message(bp, &req, sizeof(req), |
6542 | HWRM_CMD_TIMEOUT); | |
c0c050c5 MC |
6543 | |
6544 | cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; | |
6545 | } | |
6546 | } | |
6547 | mutex_unlock(&bp->hwrm_cmd_lock); | |
c0c050c5 MC |
6548 | } |
6549 | ||
6550 | static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) | |
6551 | { | |
6552 | int rc = 0, i; | |
6553 | struct hwrm_stat_ctx_alloc_input req = {0}; | |
6554 | struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
6555 | ||
3e8060fa PS |
6556 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) |
6557 | return 0; | |
6558 | ||
c0c050c5 MC |
6559 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1); |
6560 | ||
4e748506 | 6561 | req.stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size); |
51f30785 | 6562 | req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000); |
c0c050c5 MC |
6563 | |
6564 | mutex_lock(&bp->hwrm_cmd_lock); | |
6565 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
6566 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
6567 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
6568 | ||
177a6cde | 6569 | req.stats_dma_addr = cpu_to_le64(cpr->stats.hw_stats_map); |
c0c050c5 MC |
6570 | |
6571 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
6572 | HWRM_CMD_TIMEOUT); | |
6573 | if (rc) | |
6574 | break; | |
6575 | ||
6576 | cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); | |
6577 | ||
6578 | bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; | |
6579 | } | |
6580 | mutex_unlock(&bp->hwrm_cmd_lock); | |
89aa8445 | 6581 | return rc; |
c0c050c5 MC |
6582 | } |
6583 | ||
cf6645f8 MC |
6584 | static int bnxt_hwrm_func_qcfg(struct bnxt *bp) |
6585 | { | |
6586 | struct hwrm_func_qcfg_input req = {0}; | |
567b2abe | 6587 | struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; |
8ae24738 | 6588 | u32 min_db_offset = 0; |
9315edca | 6589 | u16 flags; |
cf6645f8 MC |
6590 | int rc; |
6591 | ||
6592 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); | |
6593 | req.fid = cpu_to_le16(0xffff); | |
6594 | mutex_lock(&bp->hwrm_cmd_lock); | |
6595 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
6596 | if (rc) | |
6597 | goto func_qcfg_exit; | |
6598 | ||
6599 | #ifdef CONFIG_BNXT_SRIOV | |
6600 | if (BNXT_VF(bp)) { | |
cf6645f8 MC |
6601 | struct bnxt_vf_info *vf = &bp->vf; |
6602 | ||
6603 | vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK; | |
230d1f0d MC |
6604 | } else { |
6605 | bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs); | |
cf6645f8 MC |
6606 | } |
6607 | #endif | |
9315edca MC |
6608 | flags = le16_to_cpu(resp->flags); |
6609 | if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED | | |
6610 | FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) { | |
97381a18 | 6611 | bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT; |
9315edca | 6612 | if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED) |
97381a18 | 6613 | bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT; |
9315edca MC |
6614 | } |
6615 | if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)) | |
6616 | bp->flags |= BNXT_FLAG_MULTI_HOST; | |
bc39f885 | 6617 | |
567b2abe SB |
6618 | switch (resp->port_partition_type) { |
6619 | case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0: | |
6620 | case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5: | |
6621 | case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0: | |
6622 | bp->port_partition_type = resp->port_partition_type; | |
6623 | break; | |
6624 | } | |
32e8239c MC |
6625 | if (bp->hwrm_spec_code < 0x10707 || |
6626 | resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB) | |
6627 | bp->br_mode = BRIDGE_MODE_VEB; | |
6628 | else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA) | |
6629 | bp->br_mode = BRIDGE_MODE_VEPA; | |
6630 | else | |
6631 | bp->br_mode = BRIDGE_MODE_UNDEF; | |
cf6645f8 | 6632 | |
7eb9bb3a MC |
6633 | bp->max_mtu = le16_to_cpu(resp->max_mtu_configured); |
6634 | if (!bp->max_mtu) | |
6635 | bp->max_mtu = BNXT_MAX_MTU; | |
6636 | ||
8ae24738 MC |
6637 | if (bp->db_size) |
6638 | goto func_qcfg_exit; | |
6639 | ||
6640 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
6641 | if (BNXT_PF(bp)) | |
6642 | min_db_offset = DB_PF_OFFSET_P5; | |
6643 | else | |
6644 | min_db_offset = DB_VF_OFFSET_P5; | |
6645 | } | |
6646 | bp->db_size = PAGE_ALIGN(le16_to_cpu(resp->l2_doorbell_bar_size_kb) * | |
6647 | 1024); | |
6648 | if (!bp->db_size || bp->db_size > pci_resource_len(bp->pdev, 2) || | |
6649 | bp->db_size <= min_db_offset) | |
6650 | bp->db_size = pci_resource_len(bp->pdev, 2); | |
6651 | ||
cf6645f8 MC |
6652 | func_qcfg_exit: |
6653 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6654 | return rc; | |
6655 | } | |
6656 | ||
98f04cf0 MC |
6657 | static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp) |
6658 | { | |
6659 | struct hwrm_func_backing_store_qcaps_input req = {0}; | |
6660 | struct hwrm_func_backing_store_qcaps_output *resp = | |
6661 | bp->hwrm_cmd_resp_addr; | |
6662 | int rc; | |
6663 | ||
6664 | if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx) | |
6665 | return 0; | |
6666 | ||
6667 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1); | |
6668 | mutex_lock(&bp->hwrm_cmd_lock); | |
6669 | rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
6670 | if (!rc) { | |
6671 | struct bnxt_ctx_pg_info *ctx_pg; | |
6672 | struct bnxt_ctx_mem_info *ctx; | |
ac3158cb | 6673 | int i, tqm_rings; |
98f04cf0 MC |
6674 | |
6675 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); | |
6676 | if (!ctx) { | |
6677 | rc = -ENOMEM; | |
6678 | goto ctx_err; | |
6679 | } | |
98f04cf0 MC |
6680 | ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries); |
6681 | ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries); | |
6682 | ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries); | |
6683 | ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size); | |
6684 | ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries); | |
6685 | ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries); | |
6686 | ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size); | |
6687 | ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries); | |
6688 | ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries); | |
6689 | ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size); | |
6690 | ctx->vnic_max_vnic_entries = | |
6691 | le16_to_cpu(resp->vnic_max_vnic_entries); | |
6692 | ctx->vnic_max_ring_table_entries = | |
6693 | le16_to_cpu(resp->vnic_max_ring_table_entries); | |
6694 | ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size); | |
6695 | ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries); | |
6696 | ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size); | |
6697 | ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size); | |
6698 | ctx->tqm_min_entries_per_ring = | |
6699 | le32_to_cpu(resp->tqm_min_entries_per_ring); | |
6700 | ctx->tqm_max_entries_per_ring = | |
6701 | le32_to_cpu(resp->tqm_max_entries_per_ring); | |
6702 | ctx->tqm_entries_multiple = resp->tqm_entries_multiple; | |
6703 | if (!ctx->tqm_entries_multiple) | |
6704 | ctx->tqm_entries_multiple = 1; | |
6705 | ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries); | |
6706 | ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size); | |
53579e37 DS |
6707 | ctx->mrav_num_entries_units = |
6708 | le16_to_cpu(resp->mrav_num_entries_units); | |
98f04cf0 MC |
6709 | ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size); |
6710 | ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries); | |
3be8136c | 6711 | ctx->ctx_kind_initializer = resp->ctx_kind_initializer; |
ac3158cb MC |
6712 | ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count; |
6713 | if (!ctx->tqm_fp_rings_count) | |
6714 | ctx->tqm_fp_rings_count = bp->max_q; | |
6715 | ||
6716 | tqm_rings = ctx->tqm_fp_rings_count + 1; | |
6717 | ctx_pg = kcalloc(tqm_rings, sizeof(*ctx_pg), GFP_KERNEL); | |
6718 | if (!ctx_pg) { | |
6719 | kfree(ctx); | |
6720 | rc = -ENOMEM; | |
6721 | goto ctx_err; | |
6722 | } | |
6723 | for (i = 0; i < tqm_rings; i++, ctx_pg++) | |
6724 | ctx->tqm_mem[i] = ctx_pg; | |
6725 | bp->ctx = ctx; | |
98f04cf0 MC |
6726 | } else { |
6727 | rc = 0; | |
6728 | } | |
6729 | ctx_err: | |
6730 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6731 | return rc; | |
6732 | } | |
6733 | ||
1b9394e5 MC |
6734 | static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr, |
6735 | __le64 *pg_dir) | |
6736 | { | |
6737 | u8 pg_size = 0; | |
6738 | ||
6739 | if (BNXT_PAGE_SHIFT == 13) | |
6740 | pg_size = 1 << 4; | |
6741 | else if (BNXT_PAGE_SIZE == 16) | |
6742 | pg_size = 2 << 4; | |
6743 | ||
6744 | *pg_attr = pg_size; | |
08fe9d18 MC |
6745 | if (rmem->depth >= 1) { |
6746 | if (rmem->depth == 2) | |
6747 | *pg_attr |= 2; | |
6748 | else | |
6749 | *pg_attr |= 1; | |
1b9394e5 MC |
6750 | *pg_dir = cpu_to_le64(rmem->pg_tbl_map); |
6751 | } else { | |
6752 | *pg_dir = cpu_to_le64(rmem->dma_arr[0]); | |
6753 | } | |
6754 | } | |
6755 | ||
6756 | #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \ | |
6757 | (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \ | |
6758 | FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \ | |
6759 | FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \ | |
6760 | FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \ | |
6761 | FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) | |
6762 | ||
6763 | static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables) | |
6764 | { | |
6765 | struct hwrm_func_backing_store_cfg_input req = {0}; | |
6766 | struct bnxt_ctx_mem_info *ctx = bp->ctx; | |
6767 | struct bnxt_ctx_pg_info *ctx_pg; | |
6768 | __le32 *num_entries; | |
6769 | __le64 *pg_dir; | |
53579e37 | 6770 | u32 flags = 0; |
1b9394e5 | 6771 | u8 *pg_attr; |
1b9394e5 | 6772 | u32 ena; |
9f90445c | 6773 | int i; |
1b9394e5 MC |
6774 | |
6775 | if (!ctx) | |
6776 | return 0; | |
6777 | ||
6778 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1); | |
6779 | req.enables = cpu_to_le32(enables); | |
6780 | ||
6781 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) { | |
6782 | ctx_pg = &ctx->qp_mem; | |
6783 | req.qp_num_entries = cpu_to_le32(ctx_pg->entries); | |
6784 | req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries); | |
6785 | req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries); | |
6786 | req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size); | |
6787 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6788 | &req.qpc_pg_size_qpc_lvl, | |
6789 | &req.qpc_page_dir); | |
6790 | } | |
6791 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) { | |
6792 | ctx_pg = &ctx->srq_mem; | |
6793 | req.srq_num_entries = cpu_to_le32(ctx_pg->entries); | |
6794 | req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries); | |
6795 | req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size); | |
6796 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6797 | &req.srq_pg_size_srq_lvl, | |
6798 | &req.srq_page_dir); | |
6799 | } | |
6800 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) { | |
6801 | ctx_pg = &ctx->cq_mem; | |
6802 | req.cq_num_entries = cpu_to_le32(ctx_pg->entries); | |
6803 | req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries); | |
6804 | req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size); | |
6805 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl, | |
6806 | &req.cq_page_dir); | |
6807 | } | |
6808 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) { | |
6809 | ctx_pg = &ctx->vnic_mem; | |
6810 | req.vnic_num_vnic_entries = | |
6811 | cpu_to_le16(ctx->vnic_max_vnic_entries); | |
6812 | req.vnic_num_ring_table_entries = | |
6813 | cpu_to_le16(ctx->vnic_max_ring_table_entries); | |
6814 | req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size); | |
6815 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6816 | &req.vnic_pg_size_vnic_lvl, | |
6817 | &req.vnic_page_dir); | |
6818 | } | |
6819 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) { | |
6820 | ctx_pg = &ctx->stat_mem; | |
6821 | req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries); | |
6822 | req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size); | |
6823 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6824 | &req.stat_pg_size_stat_lvl, | |
6825 | &req.stat_page_dir); | |
6826 | } | |
cf6daed0 MC |
6827 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) { |
6828 | ctx_pg = &ctx->mrav_mem; | |
6829 | req.mrav_num_entries = cpu_to_le32(ctx_pg->entries); | |
53579e37 DS |
6830 | if (ctx->mrav_num_entries_units) |
6831 | flags |= | |
6832 | FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT; | |
cf6daed0 MC |
6833 | req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size); |
6834 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6835 | &req.mrav_pg_size_mrav_lvl, | |
6836 | &req.mrav_page_dir); | |
6837 | } | |
6838 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) { | |
6839 | ctx_pg = &ctx->tim_mem; | |
6840 | req.tim_num_entries = cpu_to_le32(ctx_pg->entries); | |
6841 | req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size); | |
6842 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6843 | &req.tim_pg_size_tim_lvl, | |
6844 | &req.tim_page_dir); | |
6845 | } | |
1b9394e5 MC |
6846 | for (i = 0, num_entries = &req.tqm_sp_num_entries, |
6847 | pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl, | |
6848 | pg_dir = &req.tqm_sp_page_dir, | |
6849 | ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP; | |
6850 | i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) { | |
6851 | if (!(enables & ena)) | |
6852 | continue; | |
6853 | ||
6854 | req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size); | |
6855 | ctx_pg = ctx->tqm_mem[i]; | |
6856 | *num_entries = cpu_to_le32(ctx_pg->entries); | |
6857 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir); | |
6858 | } | |
53579e37 | 6859 | req.flags = cpu_to_le32(flags); |
9f90445c | 6860 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
1b9394e5 MC |
6861 | } |
6862 | ||
98f04cf0 | 6863 | static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, |
08fe9d18 | 6864 | struct bnxt_ctx_pg_info *ctx_pg) |
98f04cf0 MC |
6865 | { |
6866 | struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; | |
6867 | ||
98f04cf0 MC |
6868 | rmem->page_size = BNXT_PAGE_SIZE; |
6869 | rmem->pg_arr = ctx_pg->ctx_pg_arr; | |
6870 | rmem->dma_arr = ctx_pg->ctx_dma_arr; | |
1b9394e5 | 6871 | rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; |
08fe9d18 MC |
6872 | if (rmem->depth >= 1) |
6873 | rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG; | |
98f04cf0 MC |
6874 | return bnxt_alloc_ring(bp, rmem); |
6875 | } | |
6876 | ||
08fe9d18 MC |
6877 | static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp, |
6878 | struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size, | |
3be8136c | 6879 | u8 depth, bool use_init_val) |
08fe9d18 MC |
6880 | { |
6881 | struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; | |
6882 | int rc; | |
6883 | ||
6884 | if (!mem_size) | |
bbf211b1 | 6885 | return -EINVAL; |
08fe9d18 MC |
6886 | |
6887 | ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); | |
6888 | if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) { | |
6889 | ctx_pg->nr_pages = 0; | |
6890 | return -EINVAL; | |
6891 | } | |
6892 | if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) { | |
6893 | int nr_tbls, i; | |
6894 | ||
6895 | rmem->depth = 2; | |
6896 | ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg), | |
6897 | GFP_KERNEL); | |
6898 | if (!ctx_pg->ctx_pg_tbl) | |
6899 | return -ENOMEM; | |
6900 | nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES); | |
6901 | rmem->nr_pages = nr_tbls; | |
6902 | rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); | |
6903 | if (rc) | |
6904 | return rc; | |
6905 | for (i = 0; i < nr_tbls; i++) { | |
6906 | struct bnxt_ctx_pg_info *pg_tbl; | |
6907 | ||
6908 | pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL); | |
6909 | if (!pg_tbl) | |
6910 | return -ENOMEM; | |
6911 | ctx_pg->ctx_pg_tbl[i] = pg_tbl; | |
6912 | rmem = &pg_tbl->ring_mem; | |
6913 | rmem->pg_tbl = ctx_pg->ctx_pg_arr[i]; | |
6914 | rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i]; | |
6915 | rmem->depth = 1; | |
6916 | rmem->nr_pages = MAX_CTX_PAGES; | |
3be8136c MC |
6917 | if (use_init_val) |
6918 | rmem->init_val = bp->ctx->ctx_kind_initializer; | |
6ef982de MC |
6919 | if (i == (nr_tbls - 1)) { |
6920 | int rem = ctx_pg->nr_pages % MAX_CTX_PAGES; | |
6921 | ||
6922 | if (rem) | |
6923 | rmem->nr_pages = rem; | |
6924 | } | |
08fe9d18 MC |
6925 | rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl); |
6926 | if (rc) | |
6927 | break; | |
6928 | } | |
6929 | } else { | |
6930 | rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); | |
6931 | if (rmem->nr_pages > 1 || depth) | |
6932 | rmem->depth = 1; | |
3be8136c MC |
6933 | if (use_init_val) |
6934 | rmem->init_val = bp->ctx->ctx_kind_initializer; | |
08fe9d18 MC |
6935 | rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); |
6936 | } | |
6937 | return rc; | |
6938 | } | |
6939 | ||
6940 | static void bnxt_free_ctx_pg_tbls(struct bnxt *bp, | |
6941 | struct bnxt_ctx_pg_info *ctx_pg) | |
6942 | { | |
6943 | struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; | |
6944 | ||
6945 | if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES || | |
6946 | ctx_pg->ctx_pg_tbl) { | |
6947 | int i, nr_tbls = rmem->nr_pages; | |
6948 | ||
6949 | for (i = 0; i < nr_tbls; i++) { | |
6950 | struct bnxt_ctx_pg_info *pg_tbl; | |
6951 | struct bnxt_ring_mem_info *rmem2; | |
6952 | ||
6953 | pg_tbl = ctx_pg->ctx_pg_tbl[i]; | |
6954 | if (!pg_tbl) | |
6955 | continue; | |
6956 | rmem2 = &pg_tbl->ring_mem; | |
6957 | bnxt_free_ring(bp, rmem2); | |
6958 | ctx_pg->ctx_pg_arr[i] = NULL; | |
6959 | kfree(pg_tbl); | |
6960 | ctx_pg->ctx_pg_tbl[i] = NULL; | |
6961 | } | |
6962 | kfree(ctx_pg->ctx_pg_tbl); | |
6963 | ctx_pg->ctx_pg_tbl = NULL; | |
6964 | } | |
6965 | bnxt_free_ring(bp, rmem); | |
6966 | ctx_pg->nr_pages = 0; | |
6967 | } | |
6968 | ||
98f04cf0 MC |
6969 | static void bnxt_free_ctx_mem(struct bnxt *bp) |
6970 | { | |
6971 | struct bnxt_ctx_mem_info *ctx = bp->ctx; | |
6972 | int i; | |
6973 | ||
6974 | if (!ctx) | |
6975 | return; | |
6976 | ||
6977 | if (ctx->tqm_mem[0]) { | |
ac3158cb | 6978 | for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) |
08fe9d18 | 6979 | bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]); |
98f04cf0 MC |
6980 | kfree(ctx->tqm_mem[0]); |
6981 | ctx->tqm_mem[0] = NULL; | |
6982 | } | |
6983 | ||
cf6daed0 MC |
6984 | bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem); |
6985 | bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem); | |
08fe9d18 MC |
6986 | bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem); |
6987 | bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem); | |
6988 | bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem); | |
6989 | bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem); | |
6990 | bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem); | |
98f04cf0 MC |
6991 | ctx->flags &= ~BNXT_CTX_FLAG_INITED; |
6992 | } | |
6993 | ||
6994 | static int bnxt_alloc_ctx_mem(struct bnxt *bp) | |
6995 | { | |
6996 | struct bnxt_ctx_pg_info *ctx_pg; | |
6997 | struct bnxt_ctx_mem_info *ctx; | |
1b9394e5 | 6998 | u32 mem_size, ena, entries; |
c7dd7ab4 | 6999 | u32 entries_sp, min; |
53579e37 | 7000 | u32 num_mr, num_ah; |
cf6daed0 MC |
7001 | u32 extra_srqs = 0; |
7002 | u32 extra_qps = 0; | |
7003 | u8 pg_lvl = 1; | |
98f04cf0 MC |
7004 | int i, rc; |
7005 | ||
7006 | rc = bnxt_hwrm_func_backing_store_qcaps(bp); | |
7007 | if (rc) { | |
7008 | netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n", | |
7009 | rc); | |
7010 | return rc; | |
7011 | } | |
7012 | ctx = bp->ctx; | |
7013 | if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) | |
7014 | return 0; | |
7015 | ||
d629522e | 7016 | if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) { |
cf6daed0 MC |
7017 | pg_lvl = 2; |
7018 | extra_qps = 65536; | |
7019 | extra_srqs = 8192; | |
7020 | } | |
7021 | ||
98f04cf0 | 7022 | ctx_pg = &ctx->qp_mem; |
cf6daed0 MC |
7023 | ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries + |
7024 | extra_qps; | |
98f04cf0 | 7025 | mem_size = ctx->qp_entry_size * ctx_pg->entries; |
3be8136c | 7026 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); |
98f04cf0 MC |
7027 | if (rc) |
7028 | return rc; | |
7029 | ||
7030 | ctx_pg = &ctx->srq_mem; | |
cf6daed0 | 7031 | ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs; |
98f04cf0 | 7032 | mem_size = ctx->srq_entry_size * ctx_pg->entries; |
3be8136c | 7033 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); |
98f04cf0 MC |
7034 | if (rc) |
7035 | return rc; | |
7036 | ||
7037 | ctx_pg = &ctx->cq_mem; | |
cf6daed0 | 7038 | ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2; |
98f04cf0 | 7039 | mem_size = ctx->cq_entry_size * ctx_pg->entries; |
3be8136c | 7040 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); |
98f04cf0 MC |
7041 | if (rc) |
7042 | return rc; | |
7043 | ||
7044 | ctx_pg = &ctx->vnic_mem; | |
7045 | ctx_pg->entries = ctx->vnic_max_vnic_entries + | |
7046 | ctx->vnic_max_ring_table_entries; | |
7047 | mem_size = ctx->vnic_entry_size * ctx_pg->entries; | |
3be8136c | 7048 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true); |
98f04cf0 MC |
7049 | if (rc) |
7050 | return rc; | |
7051 | ||
7052 | ctx_pg = &ctx->stat_mem; | |
7053 | ctx_pg->entries = ctx->stat_max_entries; | |
7054 | mem_size = ctx->stat_entry_size * ctx_pg->entries; | |
3be8136c | 7055 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true); |
98f04cf0 MC |
7056 | if (rc) |
7057 | return rc; | |
7058 | ||
cf6daed0 MC |
7059 | ena = 0; |
7060 | if (!(bp->flags & BNXT_FLAG_ROCE_CAP)) | |
7061 | goto skip_rdma; | |
7062 | ||
7063 | ctx_pg = &ctx->mrav_mem; | |
53579e37 DS |
7064 | /* 128K extra is needed to accommodate static AH context |
7065 | * allocation by f/w. | |
7066 | */ | |
7067 | num_mr = 1024 * 256; | |
7068 | num_ah = 1024 * 128; | |
7069 | ctx_pg->entries = num_mr + num_ah; | |
cf6daed0 | 7070 | mem_size = ctx->mrav_entry_size * ctx_pg->entries; |
3be8136c | 7071 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, true); |
cf6daed0 MC |
7072 | if (rc) |
7073 | return rc; | |
7074 | ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV; | |
53579e37 DS |
7075 | if (ctx->mrav_num_entries_units) |
7076 | ctx_pg->entries = | |
7077 | ((num_mr / ctx->mrav_num_entries_units) << 16) | | |
7078 | (num_ah / ctx->mrav_num_entries_units); | |
cf6daed0 MC |
7079 | |
7080 | ctx_pg = &ctx->tim_mem; | |
7081 | ctx_pg->entries = ctx->qp_mem.entries; | |
7082 | mem_size = ctx->tim_entry_size * ctx_pg->entries; | |
3be8136c | 7083 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false); |
cf6daed0 MC |
7084 | if (rc) |
7085 | return rc; | |
7086 | ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM; | |
7087 | ||
7088 | skip_rdma: | |
c7dd7ab4 MC |
7089 | min = ctx->tqm_min_entries_per_ring; |
7090 | entries_sp = ctx->vnic_max_vnic_entries + ctx->qp_max_l2_entries + | |
7091 | 2 * (extra_qps + ctx->qp_min_qp1_entries) + min; | |
7092 | entries_sp = roundup(entries_sp, ctx->tqm_entries_multiple); | |
7093 | entries = ctx->qp_max_l2_entries + extra_qps + ctx->qp_min_qp1_entries; | |
98f04cf0 | 7094 | entries = roundup(entries, ctx->tqm_entries_multiple); |
c7dd7ab4 | 7095 | entries = clamp_t(u32, entries, min, ctx->tqm_max_entries_per_ring); |
ac3158cb | 7096 | for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) { |
98f04cf0 | 7097 | ctx_pg = ctx->tqm_mem[i]; |
c7dd7ab4 MC |
7098 | ctx_pg->entries = i ? entries : entries_sp; |
7099 | mem_size = ctx->tqm_entry_size * ctx_pg->entries; | |
3be8136c | 7100 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false); |
98f04cf0 MC |
7101 | if (rc) |
7102 | return rc; | |
1b9394e5 | 7103 | ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i; |
98f04cf0 | 7104 | } |
1b9394e5 MC |
7105 | ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES; |
7106 | rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); | |
0b5b561c | 7107 | if (rc) { |
1b9394e5 MC |
7108 | netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n", |
7109 | rc); | |
0b5b561c MC |
7110 | return rc; |
7111 | } | |
7112 | ctx->flags |= BNXT_CTX_FLAG_INITED; | |
98f04cf0 MC |
7113 | return 0; |
7114 | } | |
7115 | ||
db4723b3 | 7116 | int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all) |
be0dd9c4 MC |
7117 | { |
7118 | struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
7119 | struct hwrm_func_resource_qcaps_input req = {0}; | |
7120 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
7121 | int rc; | |
7122 | ||
7123 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1); | |
7124 | req.fid = cpu_to_le16(0xffff); | |
7125 | ||
7126 | mutex_lock(&bp->hwrm_cmd_lock); | |
351cbde9 JT |
7127 | rc = _hwrm_send_message_silent(bp, &req, sizeof(req), |
7128 | HWRM_CMD_TIMEOUT); | |
d4f1420d | 7129 | if (rc) |
be0dd9c4 | 7130 | goto hwrm_func_resc_qcaps_exit; |
be0dd9c4 | 7131 | |
db4723b3 MC |
7132 | hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs); |
7133 | if (!all) | |
7134 | goto hwrm_func_resc_qcaps_exit; | |
7135 | ||
be0dd9c4 MC |
7136 | hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx); |
7137 | hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); | |
7138 | hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings); | |
7139 | hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); | |
7140 | hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings); | |
7141 | hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); | |
7142 | hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings); | |
7143 | hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); | |
7144 | hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps); | |
7145 | hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps); | |
7146 | hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs); | |
7147 | hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); | |
7148 | hw_resc->min_vnics = le16_to_cpu(resp->min_vnics); | |
7149 | hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); | |
7150 | hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx); | |
7151 | hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); | |
7152 | ||
9c1fabdf MC |
7153 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
7154 | u16 max_msix = le16_to_cpu(resp->max_msix); | |
7155 | ||
f7588cd8 | 7156 | hw_resc->max_nqs = max_msix; |
9c1fabdf MC |
7157 | hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings; |
7158 | } | |
7159 | ||
4673d664 MC |
7160 | if (BNXT_PF(bp)) { |
7161 | struct bnxt_pf_info *pf = &bp->pf; | |
7162 | ||
7163 | pf->vf_resv_strategy = | |
7164 | le16_to_cpu(resp->vf_reservation_strategy); | |
bf82736d | 7165 | if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC) |
4673d664 MC |
7166 | pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL; |
7167 | } | |
be0dd9c4 MC |
7168 | hwrm_func_resc_qcaps_exit: |
7169 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7170 | return rc; | |
7171 | } | |
7172 | ||
7173 | static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) | |
c0c050c5 MC |
7174 | { |
7175 | int rc = 0; | |
7176 | struct hwrm_func_qcaps_input req = {0}; | |
7177 | struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
6a4f2947 | 7178 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; |
1da63ddd | 7179 | u32 flags, flags_ext; |
c0c050c5 MC |
7180 | |
7181 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1); | |
7182 | req.fid = cpu_to_le16(0xffff); | |
7183 | ||
7184 | mutex_lock(&bp->hwrm_cmd_lock); | |
7185 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7186 | if (rc) | |
7187 | goto hwrm_func_qcaps_exit; | |
7188 | ||
6a4f2947 MC |
7189 | flags = le32_to_cpu(resp->flags); |
7190 | if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED) | |
e4060d30 | 7191 | bp->flags |= BNXT_FLAG_ROCEV1_CAP; |
6a4f2947 | 7192 | if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED) |
e4060d30 | 7193 | bp->flags |= BNXT_FLAG_ROCEV2_CAP; |
55e4398d VV |
7194 | if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED) |
7195 | bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED; | |
0a3f4e4f VV |
7196 | if (flags & FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE) |
7197 | bp->fw_cap |= BNXT_FW_CAP_HOT_RESET; | |
6154532f VV |
7198 | if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED) |
7199 | bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED; | |
07f83d72 MC |
7200 | if (flags & FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE) |
7201 | bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY; | |
4037eb71 VV |
7202 | if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD) |
7203 | bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD; | |
1da63ddd EP |
7204 | if (!(flags & FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED)) |
7205 | bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT; | |
7206 | ||
7207 | flags_ext = le32_to_cpu(resp->flags_ext); | |
7208 | if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED) | |
7209 | bp->fw_cap |= BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED; | |
e4060d30 | 7210 | |
7cc5a20e | 7211 | bp->tx_push_thresh = 0; |
fed7edd1 MC |
7212 | if ((flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) && |
7213 | BNXT_FW_MAJ(bp) > 217) | |
7cc5a20e MC |
7214 | bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; |
7215 | ||
6a4f2947 MC |
7216 | hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); |
7217 | hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); | |
7218 | hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); | |
7219 | hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); | |
7220 | hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); | |
7221 | if (!hw_resc->max_hw_ring_grps) | |
7222 | hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings; | |
7223 | hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); | |
7224 | hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); | |
7225 | hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); | |
7226 | ||
c0c050c5 MC |
7227 | if (BNXT_PF(bp)) { |
7228 | struct bnxt_pf_info *pf = &bp->pf; | |
7229 | ||
7230 | pf->fw_fid = le16_to_cpu(resp->fid); | |
7231 | pf->port_id = le16_to_cpu(resp->port_id); | |
11f15ed3 | 7232 | memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN); |
c0c050c5 MC |
7233 | pf->first_vf_id = le16_to_cpu(resp->first_vf_id); |
7234 | pf->max_vfs = le16_to_cpu(resp->max_vfs); | |
7235 | pf->max_encap_records = le32_to_cpu(resp->max_encap_records); | |
7236 | pf->max_decap_records = le32_to_cpu(resp->max_decap_records); | |
7237 | pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); | |
7238 | pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); | |
7239 | pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); | |
7240 | pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); | |
ba642ab7 | 7241 | bp->flags &= ~BNXT_FLAG_WOL_CAP; |
6a4f2947 | 7242 | if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED) |
c1ef146a | 7243 | bp->flags |= BNXT_FLAG_WOL_CAP; |
c0c050c5 | 7244 | } else { |
379a80a1 | 7245 | #ifdef CONFIG_BNXT_SRIOV |
c0c050c5 MC |
7246 | struct bnxt_vf_info *vf = &bp->vf; |
7247 | ||
7248 | vf->fw_fid = le16_to_cpu(resp->fid); | |
7cc5a20e | 7249 | memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN); |
379a80a1 | 7250 | #endif |
c0c050c5 MC |
7251 | } |
7252 | ||
c0c050c5 MC |
7253 | hwrm_func_qcaps_exit: |
7254 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7255 | return rc; | |
7256 | } | |
7257 | ||
804fba4e MC |
7258 | static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp); |
7259 | ||
be0dd9c4 MC |
7260 | static int bnxt_hwrm_func_qcaps(struct bnxt *bp) |
7261 | { | |
7262 | int rc; | |
7263 | ||
7264 | rc = __bnxt_hwrm_func_qcaps(bp); | |
7265 | if (rc) | |
7266 | return rc; | |
804fba4e MC |
7267 | rc = bnxt_hwrm_queue_qportcfg(bp); |
7268 | if (rc) { | |
7269 | netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc); | |
7270 | return rc; | |
7271 | } | |
be0dd9c4 | 7272 | if (bp->hwrm_spec_code >= 0x10803) { |
98f04cf0 MC |
7273 | rc = bnxt_alloc_ctx_mem(bp); |
7274 | if (rc) | |
7275 | return rc; | |
db4723b3 | 7276 | rc = bnxt_hwrm_func_resc_qcaps(bp, true); |
be0dd9c4 | 7277 | if (!rc) |
97381a18 | 7278 | bp->fw_cap |= BNXT_FW_CAP_NEW_RM; |
be0dd9c4 MC |
7279 | } |
7280 | return 0; | |
7281 | } | |
7282 | ||
e969ae5b MC |
7283 | static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp) |
7284 | { | |
7285 | struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0}; | |
7286 | struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp; | |
7287 | int rc = 0; | |
7288 | u32 flags; | |
7289 | ||
7290 | if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW)) | |
7291 | return 0; | |
7292 | ||
7293 | resp = bp->hwrm_cmd_resp_addr; | |
7294 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1); | |
7295 | ||
7296 | mutex_lock(&bp->hwrm_cmd_lock); | |
7297 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7298 | if (rc) | |
7299 | goto hwrm_cfa_adv_qcaps_exit; | |
7300 | ||
7301 | flags = le32_to_cpu(resp->flags); | |
7302 | if (flags & | |
41136ab3 MC |
7303 | CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED) |
7304 | bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2; | |
e969ae5b MC |
7305 | |
7306 | hwrm_cfa_adv_qcaps_exit: | |
7307 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7308 | return rc; | |
7309 | } | |
7310 | ||
9ffbd677 MC |
7311 | static int bnxt_map_fw_health_regs(struct bnxt *bp) |
7312 | { | |
7313 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
7314 | u32 reg_base = 0xffffffff; | |
7315 | int i; | |
7316 | ||
7317 | /* Only pre-map the monitoring GRC registers using window 3 */ | |
7318 | for (i = 0; i < 4; i++) { | |
7319 | u32 reg = fw_health->regs[i]; | |
7320 | ||
7321 | if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC) | |
7322 | continue; | |
7323 | if (reg_base == 0xffffffff) | |
7324 | reg_base = reg & BNXT_GRC_BASE_MASK; | |
7325 | if ((reg & BNXT_GRC_BASE_MASK) != reg_base) | |
7326 | return -ERANGE; | |
7327 | fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_BASE + | |
7328 | (reg & BNXT_GRC_OFFSET_MASK); | |
7329 | } | |
7330 | if (reg_base == 0xffffffff) | |
7331 | return 0; | |
7332 | ||
7333 | writel(reg_base, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + | |
7334 | BNXT_FW_HEALTH_WIN_MAP_OFF); | |
7335 | return 0; | |
7336 | } | |
7337 | ||
07f83d72 MC |
7338 | static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp) |
7339 | { | |
7340 | struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
7341 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
7342 | struct hwrm_error_recovery_qcfg_input req = {0}; | |
7343 | int rc, i; | |
7344 | ||
7345 | if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) | |
7346 | return 0; | |
7347 | ||
7348 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_ERROR_RECOVERY_QCFG, -1, -1); | |
7349 | mutex_lock(&bp->hwrm_cmd_lock); | |
7350 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7351 | if (rc) | |
7352 | goto err_recovery_out; | |
07f83d72 MC |
7353 | fw_health->flags = le32_to_cpu(resp->flags); |
7354 | if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) && | |
7355 | !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) { | |
7356 | rc = -EINVAL; | |
7357 | goto err_recovery_out; | |
7358 | } | |
7359 | fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq); | |
7360 | fw_health->master_func_wait_dsecs = | |
7361 | le32_to_cpu(resp->master_func_wait_period); | |
7362 | fw_health->normal_func_wait_dsecs = | |
7363 | le32_to_cpu(resp->normal_func_wait_period); | |
7364 | fw_health->post_reset_wait_dsecs = | |
7365 | le32_to_cpu(resp->master_func_wait_period_after_reset); | |
7366 | fw_health->post_reset_max_wait_dsecs = | |
7367 | le32_to_cpu(resp->max_bailout_time_after_reset); | |
7368 | fw_health->regs[BNXT_FW_HEALTH_REG] = | |
7369 | le32_to_cpu(resp->fw_health_status_reg); | |
7370 | fw_health->regs[BNXT_FW_HEARTBEAT_REG] = | |
7371 | le32_to_cpu(resp->fw_heartbeat_reg); | |
7372 | fw_health->regs[BNXT_FW_RESET_CNT_REG] = | |
7373 | le32_to_cpu(resp->fw_reset_cnt_reg); | |
7374 | fw_health->regs[BNXT_FW_RESET_INPROG_REG] = | |
7375 | le32_to_cpu(resp->reset_inprogress_reg); | |
7376 | fw_health->fw_reset_inprog_reg_mask = | |
7377 | le32_to_cpu(resp->reset_inprogress_reg_mask); | |
7378 | fw_health->fw_reset_seq_cnt = resp->reg_array_cnt; | |
7379 | if (fw_health->fw_reset_seq_cnt >= 16) { | |
7380 | rc = -EINVAL; | |
7381 | goto err_recovery_out; | |
7382 | } | |
7383 | for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) { | |
7384 | fw_health->fw_reset_seq_regs[i] = | |
7385 | le32_to_cpu(resp->reset_reg[i]); | |
7386 | fw_health->fw_reset_seq_vals[i] = | |
7387 | le32_to_cpu(resp->reset_reg_val[i]); | |
7388 | fw_health->fw_reset_seq_delay_msec[i] = | |
7389 | resp->delay_after_reset[i]; | |
7390 | } | |
7391 | err_recovery_out: | |
7392 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9ffbd677 MC |
7393 | if (!rc) |
7394 | rc = bnxt_map_fw_health_regs(bp); | |
07f83d72 MC |
7395 | if (rc) |
7396 | bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; | |
7397 | return rc; | |
7398 | } | |
7399 | ||
c0c050c5 MC |
7400 | static int bnxt_hwrm_func_reset(struct bnxt *bp) |
7401 | { | |
7402 | struct hwrm_func_reset_input req = {0}; | |
7403 | ||
7404 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1); | |
7405 | req.enables = 0; | |
7406 | ||
7407 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT); | |
7408 | } | |
7409 | ||
7410 | static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) | |
7411 | { | |
7412 | int rc = 0; | |
7413 | struct hwrm_queue_qportcfg_input req = {0}; | |
7414 | struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
aabfc016 MC |
7415 | u8 i, j, *qptr; |
7416 | bool no_rdma; | |
c0c050c5 MC |
7417 | |
7418 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1); | |
7419 | ||
7420 | mutex_lock(&bp->hwrm_cmd_lock); | |
7421 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7422 | if (rc) | |
7423 | goto qportcfg_exit; | |
7424 | ||
7425 | if (!resp->max_configurable_queues) { | |
7426 | rc = -EINVAL; | |
7427 | goto qportcfg_exit; | |
7428 | } | |
7429 | bp->max_tc = resp->max_configurable_queues; | |
87c374de | 7430 | bp->max_lltc = resp->max_configurable_lossless_queues; |
c0c050c5 MC |
7431 | if (bp->max_tc > BNXT_MAX_QUEUE) |
7432 | bp->max_tc = BNXT_MAX_QUEUE; | |
7433 | ||
aabfc016 MC |
7434 | no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP); |
7435 | qptr = &resp->queue_id0; | |
7436 | for (i = 0, j = 0; i < bp->max_tc; i++) { | |
98f04cf0 MC |
7437 | bp->q_info[j].queue_id = *qptr; |
7438 | bp->q_ids[i] = *qptr++; | |
aabfc016 MC |
7439 | bp->q_info[j].queue_profile = *qptr++; |
7440 | bp->tc_to_qidx[j] = j; | |
7441 | if (!BNXT_CNPQ(bp->q_info[j].queue_profile) || | |
7442 | (no_rdma && BNXT_PF(bp))) | |
7443 | j++; | |
7444 | } | |
98f04cf0 | 7445 | bp->max_q = bp->max_tc; |
aabfc016 MC |
7446 | bp->max_tc = max_t(u8, j, 1); |
7447 | ||
441cabbb MC |
7448 | if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) |
7449 | bp->max_tc = 1; | |
7450 | ||
87c374de MC |
7451 | if (bp->max_lltc > bp->max_tc) |
7452 | bp->max_lltc = bp->max_tc; | |
7453 | ||
c0c050c5 MC |
7454 | qportcfg_exit: |
7455 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7456 | return rc; | |
7457 | } | |
7458 | ||
ba642ab7 | 7459 | static int __bnxt_hwrm_ver_get(struct bnxt *bp, bool silent) |
c0c050c5 | 7460 | { |
c0c050c5 | 7461 | struct hwrm_ver_get_input req = {0}; |
ba642ab7 | 7462 | int rc; |
c0c050c5 MC |
7463 | |
7464 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1); | |
7465 | req.hwrm_intf_maj = HWRM_VERSION_MAJOR; | |
7466 | req.hwrm_intf_min = HWRM_VERSION_MINOR; | |
7467 | req.hwrm_intf_upd = HWRM_VERSION_UPDATE; | |
ba642ab7 MC |
7468 | |
7469 | rc = bnxt_hwrm_do_send_msg(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT, | |
7470 | silent); | |
7471 | return rc; | |
7472 | } | |
7473 | ||
7474 | static int bnxt_hwrm_ver_get(struct bnxt *bp) | |
7475 | { | |
7476 | struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr; | |
d0ad2ea2 | 7477 | u16 fw_maj, fw_min, fw_bld, fw_rsv; |
b7a444f0 | 7478 | u32 dev_caps_cfg, hwrm_ver; |
d0ad2ea2 | 7479 | int rc, len; |
ba642ab7 MC |
7480 | |
7481 | bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN; | |
c0c050c5 | 7482 | mutex_lock(&bp->hwrm_cmd_lock); |
ba642ab7 | 7483 | rc = __bnxt_hwrm_ver_get(bp, false); |
c0c050c5 MC |
7484 | if (rc) |
7485 | goto hwrm_ver_get_exit; | |
7486 | ||
7487 | memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); | |
7488 | ||
894aa69a MC |
7489 | bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 | |
7490 | resp->hwrm_intf_min_8b << 8 | | |
7491 | resp->hwrm_intf_upd_8b; | |
7492 | if (resp->hwrm_intf_maj_8b < 1) { | |
c193554e | 7493 | netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", |
894aa69a MC |
7494 | resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, |
7495 | resp->hwrm_intf_upd_8b); | |
c193554e | 7496 | netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); |
c0c050c5 | 7497 | } |
b7a444f0 VV |
7498 | |
7499 | hwrm_ver = HWRM_VERSION_MAJOR << 16 | HWRM_VERSION_MINOR << 8 | | |
7500 | HWRM_VERSION_UPDATE; | |
7501 | ||
7502 | if (bp->hwrm_spec_code > hwrm_ver) | |
7503 | snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d", | |
7504 | HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, | |
7505 | HWRM_VERSION_UPDATE); | |
7506 | else | |
7507 | snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d", | |
7508 | resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, | |
7509 | resp->hwrm_intf_upd_8b); | |
7510 | ||
d0ad2ea2 MC |
7511 | fw_maj = le16_to_cpu(resp->hwrm_fw_major); |
7512 | if (bp->hwrm_spec_code > 0x10803 && fw_maj) { | |
7513 | fw_min = le16_to_cpu(resp->hwrm_fw_minor); | |
7514 | fw_bld = le16_to_cpu(resp->hwrm_fw_build); | |
7515 | fw_rsv = le16_to_cpu(resp->hwrm_fw_patch); | |
7516 | len = FW_VER_STR_LEN; | |
7517 | } else { | |
7518 | fw_maj = resp->hwrm_fw_maj_8b; | |
7519 | fw_min = resp->hwrm_fw_min_8b; | |
7520 | fw_bld = resp->hwrm_fw_bld_8b; | |
7521 | fw_rsv = resp->hwrm_fw_rsvd_8b; | |
7522 | len = BC_HWRM_STR_LEN; | |
7523 | } | |
7524 | bp->fw_ver_code = BNXT_FW_VER_CODE(fw_maj, fw_min, fw_bld, fw_rsv); | |
7525 | snprintf(bp->fw_ver_str, len, "%d.%d.%d.%d", fw_maj, fw_min, fw_bld, | |
7526 | fw_rsv); | |
c0c050c5 | 7527 | |
691aa620 VV |
7528 | if (strlen(resp->active_pkg_name)) { |
7529 | int fw_ver_len = strlen(bp->fw_ver_str); | |
7530 | ||
7531 | snprintf(bp->fw_ver_str + fw_ver_len, | |
7532 | FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s", | |
7533 | resp->active_pkg_name); | |
7534 | bp->fw_cap |= BNXT_FW_CAP_PKG_VER; | |
7535 | } | |
7536 | ||
ff4fe81d MC |
7537 | bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout); |
7538 | if (!bp->hwrm_cmd_timeout) | |
7539 | bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; | |
7540 | ||
1dfddc41 | 7541 | if (resp->hwrm_intf_maj_8b >= 1) { |
e6ef2699 | 7542 | bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len); |
1dfddc41 MC |
7543 | bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len); |
7544 | } | |
7545 | if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN) | |
7546 | bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN; | |
e6ef2699 | 7547 | |
659c805c | 7548 | bp->chip_num = le16_to_cpu(resp->chip_num); |
5313845f | 7549 | bp->chip_rev = resp->chip_rev; |
3e8060fa PS |
7550 | if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev && |
7551 | !resp->chip_metal) | |
7552 | bp->flags |= BNXT_FLAG_CHIP_NITRO_A0; | |
659c805c | 7553 | |
e605db80 DK |
7554 | dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg); |
7555 | if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && | |
7556 | (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) | |
97381a18 | 7557 | bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD; |
e605db80 | 7558 | |
760b6d33 VD |
7559 | if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) |
7560 | bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL; | |
7561 | ||
abd43a13 VD |
7562 | if (dev_caps_cfg & |
7563 | VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED) | |
7564 | bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE; | |
7565 | ||
2a516444 MC |
7566 | if (dev_caps_cfg & |
7567 | VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED) | |
7568 | bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF; | |
7569 | ||
e969ae5b MC |
7570 | if (dev_caps_cfg & |
7571 | VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) | |
7572 | bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW; | |
7573 | ||
c0c050c5 MC |
7574 | hwrm_ver_get_exit: |
7575 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7576 | return rc; | |
7577 | } | |
7578 | ||
5ac67d8b RS |
7579 | int bnxt_hwrm_fw_set_time(struct bnxt *bp) |
7580 | { | |
7581 | struct hwrm_fw_set_time_input req = {0}; | |
7dfaa7bc AB |
7582 | struct tm tm; |
7583 | time64_t now = ktime_get_real_seconds(); | |
5ac67d8b | 7584 | |
ca2c39e2 MC |
7585 | if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) || |
7586 | bp->hwrm_spec_code < 0x10400) | |
5ac67d8b RS |
7587 | return -EOPNOTSUPP; |
7588 | ||
7dfaa7bc | 7589 | time64_to_tm(now, 0, &tm); |
5ac67d8b RS |
7590 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1); |
7591 | req.year = cpu_to_le16(1900 + tm.tm_year); | |
7592 | req.month = 1 + tm.tm_mon; | |
7593 | req.day = tm.tm_mday; | |
7594 | req.hour = tm.tm_hour; | |
7595 | req.minute = tm.tm_min; | |
7596 | req.second = tm.tm_sec; | |
7597 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7598 | } | |
7599 | ||
fea6b333 MC |
7600 | static void bnxt_add_one_ctr(u64 hw, u64 *sw, u64 mask) |
7601 | { | |
7602 | u64 sw_tmp; | |
7603 | ||
7604 | sw_tmp = (*sw & ~mask) | hw; | |
7605 | if (hw < (*sw & mask)) | |
7606 | sw_tmp += mask + 1; | |
7607 | WRITE_ONCE(*sw, sw_tmp); | |
7608 | } | |
7609 | ||
7610 | static void __bnxt_accumulate_stats(__le64 *hw_stats, u64 *sw_stats, u64 *masks, | |
7611 | int count, bool ignore_zero) | |
7612 | { | |
7613 | int i; | |
7614 | ||
7615 | for (i = 0; i < count; i++) { | |
7616 | u64 hw = le64_to_cpu(READ_ONCE(hw_stats[i])); | |
7617 | ||
7618 | if (ignore_zero && !hw) | |
7619 | continue; | |
7620 | ||
7621 | if (masks[i] == -1ULL) | |
7622 | sw_stats[i] = hw; | |
7623 | else | |
7624 | bnxt_add_one_ctr(hw, &sw_stats[i], masks[i]); | |
7625 | } | |
7626 | } | |
7627 | ||
7628 | static void bnxt_accumulate_stats(struct bnxt_stats_mem *stats) | |
7629 | { | |
7630 | if (!stats->hw_stats) | |
7631 | return; | |
7632 | ||
7633 | __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats, | |
7634 | stats->hw_masks, stats->len / 8, false); | |
7635 | } | |
7636 | ||
7637 | static void bnxt_accumulate_all_stats(struct bnxt *bp) | |
7638 | { | |
7639 | struct bnxt_stats_mem *ring0_stats; | |
7640 | bool ignore_zero = false; | |
7641 | int i; | |
7642 | ||
7643 | /* Chip bug. Counter intermittently becomes 0. */ | |
7644 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
7645 | ignore_zero = true; | |
7646 | ||
7647 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
7648 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
7649 | struct bnxt_cp_ring_info *cpr; | |
7650 | struct bnxt_stats_mem *stats; | |
7651 | ||
7652 | cpr = &bnapi->cp_ring; | |
7653 | stats = &cpr->stats; | |
7654 | if (!i) | |
7655 | ring0_stats = stats; | |
7656 | __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats, | |
7657 | ring0_stats->hw_masks, | |
7658 | ring0_stats->len / 8, ignore_zero); | |
7659 | } | |
7660 | if (bp->flags & BNXT_FLAG_PORT_STATS) { | |
7661 | struct bnxt_stats_mem *stats = &bp->port_stats; | |
7662 | __le64 *hw_stats = stats->hw_stats; | |
7663 | u64 *sw_stats = stats->sw_stats; | |
7664 | u64 *masks = stats->hw_masks; | |
7665 | int cnt; | |
7666 | ||
7667 | cnt = sizeof(struct rx_port_stats) / 8; | |
7668 | __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false); | |
7669 | ||
7670 | hw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; | |
7671 | sw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; | |
7672 | masks += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; | |
7673 | cnt = sizeof(struct tx_port_stats) / 8; | |
7674 | __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false); | |
7675 | } | |
7676 | if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { | |
7677 | bnxt_accumulate_stats(&bp->rx_port_stats_ext); | |
7678 | bnxt_accumulate_stats(&bp->tx_port_stats_ext); | |
7679 | } | |
7680 | } | |
7681 | ||
531d1d26 | 7682 | static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags) |
3bdf56c4 | 7683 | { |
3bdf56c4 MC |
7684 | struct bnxt_pf_info *pf = &bp->pf; |
7685 | struct hwrm_port_qstats_input req = {0}; | |
7686 | ||
7687 | if (!(bp->flags & BNXT_FLAG_PORT_STATS)) | |
7688 | return 0; | |
7689 | ||
531d1d26 MC |
7690 | if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED)) |
7691 | return -EOPNOTSUPP; | |
7692 | ||
7693 | req.flags = flags; | |
3bdf56c4 MC |
7694 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1); |
7695 | req.port_id = cpu_to_le16(pf->port_id); | |
177a6cde MC |
7696 | req.tx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map + |
7697 | BNXT_TX_PORT_STATS_BYTE_OFFSET); | |
7698 | req.rx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map); | |
9f90445c | 7699 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
3bdf56c4 MC |
7700 | } |
7701 | ||
531d1d26 | 7702 | static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags) |
00db3cba | 7703 | { |
36e53349 | 7704 | struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr; |
e37fed79 | 7705 | struct hwrm_queue_pri2cos_qcfg_input req2 = {0}; |
00db3cba VV |
7706 | struct hwrm_port_qstats_ext_input req = {0}; |
7707 | struct bnxt_pf_info *pf = &bp->pf; | |
ad361adf | 7708 | u32 tx_stat_size; |
36e53349 | 7709 | int rc; |
00db3cba VV |
7710 | |
7711 | if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) | |
7712 | return 0; | |
7713 | ||
531d1d26 MC |
7714 | if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED)) |
7715 | return -EOPNOTSUPP; | |
7716 | ||
00db3cba | 7717 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1); |
531d1d26 | 7718 | req.flags = flags; |
00db3cba VV |
7719 | req.port_id = cpu_to_le16(pf->port_id); |
7720 | req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext)); | |
177a6cde MC |
7721 | req.rx_stat_host_addr = cpu_to_le64(bp->rx_port_stats_ext.hw_stats_map); |
7722 | tx_stat_size = bp->tx_port_stats_ext.hw_stats ? | |
7723 | sizeof(struct tx_port_stats_ext) : 0; | |
ad361adf | 7724 | req.tx_stat_size = cpu_to_le16(tx_stat_size); |
177a6cde | 7725 | req.tx_stat_host_addr = cpu_to_le64(bp->tx_port_stats_ext.hw_stats_map); |
36e53349 MC |
7726 | mutex_lock(&bp->hwrm_cmd_lock); |
7727 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7728 | if (!rc) { | |
7729 | bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8; | |
ad361adf MC |
7730 | bp->fw_tx_stats_ext_size = tx_stat_size ? |
7731 | le16_to_cpu(resp->tx_stat_size) / 8 : 0; | |
36e53349 MC |
7732 | } else { |
7733 | bp->fw_rx_stats_ext_size = 0; | |
7734 | bp->fw_tx_stats_ext_size = 0; | |
7735 | } | |
531d1d26 MC |
7736 | if (flags) |
7737 | goto qstats_done; | |
7738 | ||
e37fed79 MC |
7739 | if (bp->fw_tx_stats_ext_size <= |
7740 | offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) { | |
7741 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7742 | bp->pri2cos_valid = 0; | |
7743 | return rc; | |
7744 | } | |
7745 | ||
7746 | bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1); | |
7747 | req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN); | |
7748 | ||
7749 | rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT); | |
7750 | if (!rc) { | |
7751 | struct hwrm_queue_pri2cos_qcfg_output *resp2; | |
7752 | u8 *pri2cos; | |
7753 | int i, j; | |
7754 | ||
7755 | resp2 = bp->hwrm_cmd_resp_addr; | |
7756 | pri2cos = &resp2->pri0_cos_queue_id; | |
7757 | for (i = 0; i < 8; i++) { | |
7758 | u8 queue_id = pri2cos[i]; | |
a24ec322 | 7759 | u8 queue_idx; |
e37fed79 | 7760 | |
a24ec322 MC |
7761 | /* Per port queue IDs start from 0, 10, 20, etc */ |
7762 | queue_idx = queue_id % 10; | |
7763 | if (queue_idx > BNXT_MAX_QUEUE) { | |
7764 | bp->pri2cos_valid = false; | |
7765 | goto qstats_done; | |
7766 | } | |
e37fed79 MC |
7767 | for (j = 0; j < bp->max_q; j++) { |
7768 | if (bp->q_ids[j] == queue_id) | |
a24ec322 | 7769 | bp->pri2cos_idx[i] = queue_idx; |
e37fed79 MC |
7770 | } |
7771 | } | |
7772 | bp->pri2cos_valid = 1; | |
7773 | } | |
a24ec322 | 7774 | qstats_done: |
36e53349 MC |
7775 | mutex_unlock(&bp->hwrm_cmd_lock); |
7776 | return rc; | |
00db3cba VV |
7777 | } |
7778 | ||
c0c050c5 MC |
7779 | static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) |
7780 | { | |
442a35a5 | 7781 | if (bp->vxlan_fw_dst_port_id != INVALID_HW_RING_ID) |
c0c050c5 MC |
7782 | bnxt_hwrm_tunnel_dst_port_free( |
7783 | bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); | |
442a35a5 | 7784 | if (bp->nge_fw_dst_port_id != INVALID_HW_RING_ID) |
c0c050c5 MC |
7785 | bnxt_hwrm_tunnel_dst_port_free( |
7786 | bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); | |
c0c050c5 MC |
7787 | } |
7788 | ||
7789 | static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) | |
7790 | { | |
7791 | int rc, i; | |
7792 | u32 tpa_flags = 0; | |
7793 | ||
7794 | if (set_tpa) | |
7795 | tpa_flags = bp->flags & BNXT_FLAG_TPA; | |
b4fff207 MC |
7796 | else if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) |
7797 | return 0; | |
c0c050c5 MC |
7798 | for (i = 0; i < bp->nr_vnics; i++) { |
7799 | rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); | |
7800 | if (rc) { | |
7801 | netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", | |
23e12c89 | 7802 | i, rc); |
c0c050c5 MC |
7803 | return rc; |
7804 | } | |
7805 | } | |
7806 | return 0; | |
7807 | } | |
7808 | ||
7809 | static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) | |
7810 | { | |
7811 | int i; | |
7812 | ||
7813 | for (i = 0; i < bp->nr_vnics; i++) | |
7814 | bnxt_hwrm_vnic_set_rss(bp, i, false); | |
7815 | } | |
7816 | ||
a46ecb11 | 7817 | static void bnxt_clear_vnic(struct bnxt *bp) |
c0c050c5 | 7818 | { |
a46ecb11 MC |
7819 | if (!bp->vnic_info) |
7820 | return; | |
7821 | ||
7822 | bnxt_hwrm_clear_vnic_filter(bp); | |
7823 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) { | |
c0c050c5 MC |
7824 | /* clear all RSS setting before free vnic ctx */ |
7825 | bnxt_hwrm_clear_vnic_rss(bp); | |
7826 | bnxt_hwrm_vnic_ctx_free(bp); | |
c0c050c5 | 7827 | } |
a46ecb11 MC |
7828 | /* before free the vnic, undo the vnic tpa settings */ |
7829 | if (bp->flags & BNXT_FLAG_TPA) | |
7830 | bnxt_set_tpa(bp, false); | |
7831 | bnxt_hwrm_vnic_free(bp); | |
7832 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
7833 | bnxt_hwrm_vnic_ctx_free(bp); | |
7834 | } | |
7835 | ||
7836 | static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, | |
7837 | bool irq_re_init) | |
7838 | { | |
7839 | bnxt_clear_vnic(bp); | |
c0c050c5 MC |
7840 | bnxt_hwrm_ring_free(bp, close_path); |
7841 | bnxt_hwrm_ring_grp_free(bp); | |
7842 | if (irq_re_init) { | |
7843 | bnxt_hwrm_stat_ctx_free(bp); | |
7844 | bnxt_hwrm_free_tunnel_ports(bp); | |
7845 | } | |
7846 | } | |
7847 | ||
39d8ba2e MC |
7848 | static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode) |
7849 | { | |
7850 | struct hwrm_func_cfg_input req = {0}; | |
39d8ba2e MC |
7851 | |
7852 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); | |
7853 | req.fid = cpu_to_le16(0xffff); | |
7854 | req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE); | |
7855 | if (br_mode == BRIDGE_MODE_VEB) | |
7856 | req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB; | |
7857 | else if (br_mode == BRIDGE_MODE_VEPA) | |
7858 | req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA; | |
7859 | else | |
7860 | return -EINVAL; | |
9f90445c | 7861 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
39d8ba2e MC |
7862 | } |
7863 | ||
c3480a60 MC |
7864 | static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size) |
7865 | { | |
7866 | struct hwrm_func_cfg_input req = {0}; | |
c3480a60 MC |
7867 | |
7868 | if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803) | |
7869 | return 0; | |
7870 | ||
7871 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); | |
7872 | req.fid = cpu_to_le16(0xffff); | |
7873 | req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE); | |
d4f52de0 | 7874 | req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64; |
c3480a60 | 7875 | if (size == 128) |
d4f52de0 | 7876 | req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128; |
c3480a60 | 7877 | |
9f90445c | 7878 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
c3480a60 MC |
7879 | } |
7880 | ||
7b3af4f7 | 7881 | static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) |
c0c050c5 | 7882 | { |
ae10ae74 | 7883 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
c0c050c5 MC |
7884 | int rc; |
7885 | ||
ae10ae74 MC |
7886 | if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) |
7887 | goto skip_rss_ctx; | |
7888 | ||
c0c050c5 | 7889 | /* allocate context for vnic */ |
94ce9caa | 7890 | rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0); |
c0c050c5 MC |
7891 | if (rc) { |
7892 | netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", | |
7893 | vnic_id, rc); | |
7894 | goto vnic_setup_err; | |
7895 | } | |
7896 | bp->rsscos_nr_ctxs++; | |
7897 | ||
94ce9caa PS |
7898 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { |
7899 | rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1); | |
7900 | if (rc) { | |
7901 | netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n", | |
7902 | vnic_id, rc); | |
7903 | goto vnic_setup_err; | |
7904 | } | |
7905 | bp->rsscos_nr_ctxs++; | |
7906 | } | |
7907 | ||
ae10ae74 | 7908 | skip_rss_ctx: |
c0c050c5 MC |
7909 | /* configure default vnic, ring grp */ |
7910 | rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); | |
7911 | if (rc) { | |
7912 | netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", | |
7913 | vnic_id, rc); | |
7914 | goto vnic_setup_err; | |
7915 | } | |
7916 | ||
7917 | /* Enable RSS hashing on vnic */ | |
7918 | rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); | |
7919 | if (rc) { | |
7920 | netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", | |
7921 | vnic_id, rc); | |
7922 | goto vnic_setup_err; | |
7923 | } | |
7924 | ||
7925 | if (bp->flags & BNXT_FLAG_AGG_RINGS) { | |
7926 | rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); | |
7927 | if (rc) { | |
7928 | netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", | |
7929 | vnic_id, rc); | |
7930 | } | |
7931 | } | |
7932 | ||
7933 | vnic_setup_err: | |
7934 | return rc; | |
7935 | } | |
7936 | ||
7b3af4f7 MC |
7937 | static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id) |
7938 | { | |
7939 | int rc, i, nr_ctxs; | |
7940 | ||
f9f6a3fb | 7941 | nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings); |
7b3af4f7 MC |
7942 | for (i = 0; i < nr_ctxs; i++) { |
7943 | rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i); | |
7944 | if (rc) { | |
7945 | netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n", | |
7946 | vnic_id, i, rc); | |
7947 | break; | |
7948 | } | |
7949 | bp->rsscos_nr_ctxs++; | |
7950 | } | |
7951 | if (i < nr_ctxs) | |
7952 | return -ENOMEM; | |
7953 | ||
7954 | rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true); | |
7955 | if (rc) { | |
7956 | netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n", | |
7957 | vnic_id, rc); | |
7958 | return rc; | |
7959 | } | |
7960 | rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); | |
7961 | if (rc) { | |
7962 | netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", | |
7963 | vnic_id, rc); | |
7964 | return rc; | |
7965 | } | |
7966 | if (bp->flags & BNXT_FLAG_AGG_RINGS) { | |
7967 | rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); | |
7968 | if (rc) { | |
7969 | netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", | |
7970 | vnic_id, rc); | |
7971 | } | |
7972 | } | |
7973 | return rc; | |
7974 | } | |
7975 | ||
7976 | static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) | |
7977 | { | |
7978 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
7979 | return __bnxt_setup_vnic_p5(bp, vnic_id); | |
7980 | else | |
7981 | return __bnxt_setup_vnic(bp, vnic_id); | |
7982 | } | |
7983 | ||
c0c050c5 MC |
7984 | static int bnxt_alloc_rfs_vnics(struct bnxt *bp) |
7985 | { | |
7986 | #ifdef CONFIG_RFS_ACCEL | |
7987 | int i, rc = 0; | |
7988 | ||
9b3d15e6 MC |
7989 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
7990 | return 0; | |
7991 | ||
c0c050c5 | 7992 | for (i = 0; i < bp->rx_nr_rings; i++) { |
ae10ae74 | 7993 | struct bnxt_vnic_info *vnic; |
c0c050c5 MC |
7994 | u16 vnic_id = i + 1; |
7995 | u16 ring_id = i; | |
7996 | ||
7997 | if (vnic_id >= bp->nr_vnics) | |
7998 | break; | |
7999 | ||
ae10ae74 MC |
8000 | vnic = &bp->vnic_info[vnic_id]; |
8001 | vnic->flags |= BNXT_VNIC_RFS_FLAG; | |
8002 | if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) | |
8003 | vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG; | |
b81a90d3 | 8004 | rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); |
c0c050c5 MC |
8005 | if (rc) { |
8006 | netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", | |
8007 | vnic_id, rc); | |
8008 | break; | |
8009 | } | |
8010 | rc = bnxt_setup_vnic(bp, vnic_id); | |
8011 | if (rc) | |
8012 | break; | |
8013 | } | |
8014 | return rc; | |
8015 | #else | |
8016 | return 0; | |
8017 | #endif | |
8018 | } | |
8019 | ||
17c71ac3 MC |
8020 | /* Allow PF and VF with default VLAN to be in promiscuous mode */ |
8021 | static bool bnxt_promisc_ok(struct bnxt *bp) | |
8022 | { | |
8023 | #ifdef CONFIG_BNXT_SRIOV | |
8024 | if (BNXT_VF(bp) && !bp->vf.vlan) | |
8025 | return false; | |
8026 | #endif | |
8027 | return true; | |
8028 | } | |
8029 | ||
dc52c6c7 PS |
8030 | static int bnxt_setup_nitroa0_vnic(struct bnxt *bp) |
8031 | { | |
8032 | unsigned int rc = 0; | |
8033 | ||
8034 | rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1); | |
8035 | if (rc) { | |
8036 | netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", | |
8037 | rc); | |
8038 | return rc; | |
8039 | } | |
8040 | ||
8041 | rc = bnxt_hwrm_vnic_cfg(bp, 1); | |
8042 | if (rc) { | |
8043 | netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", | |
8044 | rc); | |
8045 | return rc; | |
8046 | } | |
8047 | return rc; | |
8048 | } | |
8049 | ||
b664f008 | 8050 | static int bnxt_cfg_rx_mode(struct bnxt *); |
7d2837dd | 8051 | static bool bnxt_mc_list_updated(struct bnxt *, u32 *); |
b664f008 | 8052 | |
c0c050c5 MC |
8053 | static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) |
8054 | { | |
7d2837dd | 8055 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; |
c0c050c5 | 8056 | int rc = 0; |
76595193 | 8057 | unsigned int rx_nr_rings = bp->rx_nr_rings; |
c0c050c5 MC |
8058 | |
8059 | if (irq_re_init) { | |
8060 | rc = bnxt_hwrm_stat_ctx_alloc(bp); | |
8061 | if (rc) { | |
8062 | netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", | |
8063 | rc); | |
8064 | goto err_out; | |
8065 | } | |
8066 | } | |
8067 | ||
8068 | rc = bnxt_hwrm_ring_alloc(bp); | |
8069 | if (rc) { | |
8070 | netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); | |
8071 | goto err_out; | |
8072 | } | |
8073 | ||
8074 | rc = bnxt_hwrm_ring_grp_alloc(bp); | |
8075 | if (rc) { | |
8076 | netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); | |
8077 | goto err_out; | |
8078 | } | |
8079 | ||
76595193 PS |
8080 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) |
8081 | rx_nr_rings--; | |
8082 | ||
c0c050c5 | 8083 | /* default vnic 0 */ |
76595193 | 8084 | rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings); |
c0c050c5 MC |
8085 | if (rc) { |
8086 | netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); | |
8087 | goto err_out; | |
8088 | } | |
8089 | ||
8090 | rc = bnxt_setup_vnic(bp, 0); | |
8091 | if (rc) | |
8092 | goto err_out; | |
8093 | ||
8094 | if (bp->flags & BNXT_FLAG_RFS) { | |
8095 | rc = bnxt_alloc_rfs_vnics(bp); | |
8096 | if (rc) | |
8097 | goto err_out; | |
8098 | } | |
8099 | ||
8100 | if (bp->flags & BNXT_FLAG_TPA) { | |
8101 | rc = bnxt_set_tpa(bp, true); | |
8102 | if (rc) | |
8103 | goto err_out; | |
8104 | } | |
8105 | ||
8106 | if (BNXT_VF(bp)) | |
8107 | bnxt_update_vf_mac(bp); | |
8108 | ||
8109 | /* Filter for default vnic 0 */ | |
8110 | rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); | |
8111 | if (rc) { | |
8112 | netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); | |
8113 | goto err_out; | |
8114 | } | |
7d2837dd | 8115 | vnic->uc_filter_count = 1; |
c0c050c5 | 8116 | |
30e33848 MC |
8117 | vnic->rx_mask = 0; |
8118 | if (bp->dev->flags & IFF_BROADCAST) | |
8119 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; | |
c0c050c5 | 8120 | |
17c71ac3 | 8121 | if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) |
7d2837dd MC |
8122 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; |
8123 | ||
8124 | if (bp->dev->flags & IFF_ALLMULTI) { | |
8125 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; | |
8126 | vnic->mc_list_count = 0; | |
8127 | } else { | |
8128 | u32 mask = 0; | |
8129 | ||
8130 | bnxt_mc_list_updated(bp, &mask); | |
8131 | vnic->rx_mask |= mask; | |
8132 | } | |
c0c050c5 | 8133 | |
b664f008 MC |
8134 | rc = bnxt_cfg_rx_mode(bp); |
8135 | if (rc) | |
c0c050c5 | 8136 | goto err_out; |
c0c050c5 MC |
8137 | |
8138 | rc = bnxt_hwrm_set_coal(bp); | |
8139 | if (rc) | |
8140 | netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", | |
dc52c6c7 PS |
8141 | rc); |
8142 | ||
8143 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { | |
8144 | rc = bnxt_setup_nitroa0_vnic(bp); | |
8145 | if (rc) | |
8146 | netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n", | |
8147 | rc); | |
8148 | } | |
c0c050c5 | 8149 | |
cf6645f8 MC |
8150 | if (BNXT_VF(bp)) { |
8151 | bnxt_hwrm_func_qcfg(bp); | |
8152 | netdev_update_features(bp->dev); | |
8153 | } | |
8154 | ||
c0c050c5 MC |
8155 | return 0; |
8156 | ||
8157 | err_out: | |
8158 | bnxt_hwrm_resource_free(bp, 0, true); | |
8159 | ||
8160 | return rc; | |
8161 | } | |
8162 | ||
8163 | static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) | |
8164 | { | |
8165 | bnxt_hwrm_resource_free(bp, 1, irq_re_init); | |
8166 | return 0; | |
8167 | } | |
8168 | ||
8169 | static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) | |
8170 | { | |
2247925f | 8171 | bnxt_init_cp_rings(bp); |
c0c050c5 MC |
8172 | bnxt_init_rx_rings(bp); |
8173 | bnxt_init_tx_rings(bp); | |
8174 | bnxt_init_ring_grps(bp, irq_re_init); | |
8175 | bnxt_init_vnics(bp); | |
8176 | ||
8177 | return bnxt_init_chip(bp, irq_re_init); | |
8178 | } | |
8179 | ||
c0c050c5 MC |
8180 | static int bnxt_set_real_num_queues(struct bnxt *bp) |
8181 | { | |
8182 | int rc; | |
8183 | struct net_device *dev = bp->dev; | |
8184 | ||
5f449249 MC |
8185 | rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings - |
8186 | bp->tx_nr_rings_xdp); | |
c0c050c5 MC |
8187 | if (rc) |
8188 | return rc; | |
8189 | ||
8190 | rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); | |
8191 | if (rc) | |
8192 | return rc; | |
8193 | ||
8194 | #ifdef CONFIG_RFS_ACCEL | |
45019a18 | 8195 | if (bp->flags & BNXT_FLAG_RFS) |
c0c050c5 | 8196 | dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); |
c0c050c5 MC |
8197 | #endif |
8198 | ||
8199 | return rc; | |
8200 | } | |
8201 | ||
6e6c5a57 MC |
8202 | static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, |
8203 | bool shared) | |
8204 | { | |
8205 | int _rx = *rx, _tx = *tx; | |
8206 | ||
8207 | if (shared) { | |
8208 | *rx = min_t(int, _rx, max); | |
8209 | *tx = min_t(int, _tx, max); | |
8210 | } else { | |
8211 | if (max < 2) | |
8212 | return -ENOMEM; | |
8213 | ||
8214 | while (_rx + _tx > max) { | |
8215 | if (_rx > _tx && _rx > 1) | |
8216 | _rx--; | |
8217 | else if (_tx > 1) | |
8218 | _tx--; | |
8219 | } | |
8220 | *rx = _rx; | |
8221 | *tx = _tx; | |
8222 | } | |
8223 | return 0; | |
8224 | } | |
8225 | ||
7809592d MC |
8226 | static void bnxt_setup_msix(struct bnxt *bp) |
8227 | { | |
8228 | const int len = sizeof(bp->irq_tbl[0].name); | |
8229 | struct net_device *dev = bp->dev; | |
8230 | int tcs, i; | |
8231 | ||
8232 | tcs = netdev_get_num_tc(dev); | |
18e4960c | 8233 | if (tcs) { |
d1e7925e | 8234 | int i, off, count; |
7809592d | 8235 | |
d1e7925e MC |
8236 | for (i = 0; i < tcs; i++) { |
8237 | count = bp->tx_nr_rings_per_tc; | |
8238 | off = i * count; | |
8239 | netdev_set_tc_queue(dev, i, count, off); | |
7809592d MC |
8240 | } |
8241 | } | |
8242 | ||
8243 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
e5811b8c | 8244 | int map_idx = bnxt_cp_num_to_irq_num(bp, i); |
7809592d MC |
8245 | char *attr; |
8246 | ||
8247 | if (bp->flags & BNXT_FLAG_SHARED_RINGS) | |
8248 | attr = "TxRx"; | |
8249 | else if (i < bp->rx_nr_rings) | |
8250 | attr = "rx"; | |
8251 | else | |
8252 | attr = "tx"; | |
8253 | ||
e5811b8c MC |
8254 | snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name, |
8255 | attr, i); | |
8256 | bp->irq_tbl[map_idx].handler = bnxt_msix; | |
7809592d MC |
8257 | } |
8258 | } | |
8259 | ||
8260 | static void bnxt_setup_inta(struct bnxt *bp) | |
8261 | { | |
8262 | const int len = sizeof(bp->irq_tbl[0].name); | |
8263 | ||
8264 | if (netdev_get_num_tc(bp->dev)) | |
8265 | netdev_reset_tc(bp->dev); | |
8266 | ||
8267 | snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx", | |
8268 | 0); | |
8269 | bp->irq_tbl[0].handler = bnxt_inta; | |
8270 | } | |
8271 | ||
8272 | static int bnxt_setup_int_mode(struct bnxt *bp) | |
8273 | { | |
8274 | int rc; | |
8275 | ||
8276 | if (bp->flags & BNXT_FLAG_USING_MSIX) | |
8277 | bnxt_setup_msix(bp); | |
8278 | else | |
8279 | bnxt_setup_inta(bp); | |
8280 | ||
8281 | rc = bnxt_set_real_num_queues(bp); | |
8282 | return rc; | |
8283 | } | |
8284 | ||
b7429954 | 8285 | #ifdef CONFIG_RFS_ACCEL |
8079e8f1 MC |
8286 | static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp) |
8287 | { | |
6a4f2947 | 8288 | return bp->hw_resc.max_rsscos_ctxs; |
8079e8f1 MC |
8289 | } |
8290 | ||
8291 | static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp) | |
8292 | { | |
6a4f2947 | 8293 | return bp->hw_resc.max_vnics; |
8079e8f1 | 8294 | } |
b7429954 | 8295 | #endif |
8079e8f1 | 8296 | |
e4060d30 MC |
8297 | unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp) |
8298 | { | |
6a4f2947 | 8299 | return bp->hw_resc.max_stat_ctxs; |
e4060d30 MC |
8300 | } |
8301 | ||
8302 | unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp) | |
8303 | { | |
6a4f2947 | 8304 | return bp->hw_resc.max_cp_rings; |
e4060d30 MC |
8305 | } |
8306 | ||
e916b081 | 8307 | static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp) |
a588e458 | 8308 | { |
c0b8cda0 MC |
8309 | unsigned int cp = bp->hw_resc.max_cp_rings; |
8310 | ||
8311 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
8312 | cp -= bnxt_get_ulp_msix_num(bp); | |
8313 | ||
8314 | return cp; | |
a588e458 MC |
8315 | } |
8316 | ||
ad95c27b | 8317 | static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp) |
7809592d | 8318 | { |
6a4f2947 MC |
8319 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; |
8320 | ||
f7588cd8 MC |
8321 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
8322 | return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs); | |
8323 | ||
6a4f2947 | 8324 | return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings); |
7809592d MC |
8325 | } |
8326 | ||
30f52947 | 8327 | static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs) |
33c2657e | 8328 | { |
6a4f2947 | 8329 | bp->hw_resc.max_irqs = max_irqs; |
33c2657e MC |
8330 | } |
8331 | ||
e916b081 MC |
8332 | unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp) |
8333 | { | |
8334 | unsigned int cp; | |
8335 | ||
8336 | cp = bnxt_get_max_func_cp_rings_for_en(bp); | |
8337 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
8338 | return cp - bp->rx_nr_rings - bp->tx_nr_rings; | |
8339 | else | |
8340 | return cp - bp->cp_nr_rings; | |
8341 | } | |
8342 | ||
c027c6b4 VV |
8343 | unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp) |
8344 | { | |
d77b1ad8 | 8345 | return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp); |
c027c6b4 VV |
8346 | } |
8347 | ||
fbcfc8e4 MC |
8348 | int bnxt_get_avail_msix(struct bnxt *bp, int num) |
8349 | { | |
8350 | int max_cp = bnxt_get_max_func_cp_rings(bp); | |
8351 | int max_irq = bnxt_get_max_func_irqs(bp); | |
8352 | int total_req = bp->cp_nr_rings + num; | |
8353 | int max_idx, avail_msix; | |
8354 | ||
75720e63 MC |
8355 | max_idx = bp->total_irqs; |
8356 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
8357 | max_idx = min_t(int, bp->total_irqs, max_cp); | |
fbcfc8e4 | 8358 | avail_msix = max_idx - bp->cp_nr_rings; |
f1ca94de | 8359 | if (!BNXT_NEW_RM(bp) || avail_msix >= num) |
fbcfc8e4 MC |
8360 | return avail_msix; |
8361 | ||
8362 | if (max_irq < total_req) { | |
8363 | num = max_irq - bp->cp_nr_rings; | |
8364 | if (num <= 0) | |
8365 | return 0; | |
8366 | } | |
8367 | return num; | |
8368 | } | |
8369 | ||
08654eb2 MC |
8370 | static int bnxt_get_num_msix(struct bnxt *bp) |
8371 | { | |
f1ca94de | 8372 | if (!BNXT_NEW_RM(bp)) |
08654eb2 MC |
8373 | return bnxt_get_max_func_irqs(bp); |
8374 | ||
c0b8cda0 | 8375 | return bnxt_nq_rings_in_use(bp); |
08654eb2 MC |
8376 | } |
8377 | ||
7809592d | 8378 | static int bnxt_init_msix(struct bnxt *bp) |
c0c050c5 | 8379 | { |
fbcfc8e4 | 8380 | int i, total_vecs, max, rc = 0, min = 1, ulp_msix; |
7809592d | 8381 | struct msix_entry *msix_ent; |
c0c050c5 | 8382 | |
08654eb2 MC |
8383 | total_vecs = bnxt_get_num_msix(bp); |
8384 | max = bnxt_get_max_func_irqs(bp); | |
8385 | if (total_vecs > max) | |
8386 | total_vecs = max; | |
8387 | ||
2773dfb2 MC |
8388 | if (!total_vecs) |
8389 | return 0; | |
8390 | ||
c0c050c5 MC |
8391 | msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); |
8392 | if (!msix_ent) | |
8393 | return -ENOMEM; | |
8394 | ||
8395 | for (i = 0; i < total_vecs; i++) { | |
8396 | msix_ent[i].entry = i; | |
8397 | msix_ent[i].vector = 0; | |
8398 | } | |
8399 | ||
01657bcd MC |
8400 | if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) |
8401 | min = 2; | |
8402 | ||
8403 | total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); | |
fbcfc8e4 MC |
8404 | ulp_msix = bnxt_get_ulp_msix_num(bp); |
8405 | if (total_vecs < 0 || total_vecs < ulp_msix) { | |
c0c050c5 MC |
8406 | rc = -ENODEV; |
8407 | goto msix_setup_exit; | |
8408 | } | |
8409 | ||
8410 | bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); | |
8411 | if (bp->irq_tbl) { | |
7809592d MC |
8412 | for (i = 0; i < total_vecs; i++) |
8413 | bp->irq_tbl[i].vector = msix_ent[i].vector; | |
c0c050c5 | 8414 | |
7809592d | 8415 | bp->total_irqs = total_vecs; |
c0c050c5 | 8416 | /* Trim rings based upon num of vectors allocated */ |
6e6c5a57 | 8417 | rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, |
fbcfc8e4 | 8418 | total_vecs - ulp_msix, min == 1); |
6e6c5a57 MC |
8419 | if (rc) |
8420 | goto msix_setup_exit; | |
8421 | ||
7809592d MC |
8422 | bp->cp_nr_rings = (min == 1) ? |
8423 | max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : | |
8424 | bp->tx_nr_rings + bp->rx_nr_rings; | |
c0c050c5 | 8425 | |
c0c050c5 MC |
8426 | } else { |
8427 | rc = -ENOMEM; | |
8428 | goto msix_setup_exit; | |
8429 | } | |
8430 | bp->flags |= BNXT_FLAG_USING_MSIX; | |
8431 | kfree(msix_ent); | |
8432 | return 0; | |
8433 | ||
8434 | msix_setup_exit: | |
7809592d MC |
8435 | netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc); |
8436 | kfree(bp->irq_tbl); | |
8437 | bp->irq_tbl = NULL; | |
c0c050c5 MC |
8438 | pci_disable_msix(bp->pdev); |
8439 | kfree(msix_ent); | |
8440 | return rc; | |
8441 | } | |
8442 | ||
7809592d | 8443 | static int bnxt_init_inta(struct bnxt *bp) |
c0c050c5 | 8444 | { |
c0c050c5 | 8445 | bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL); |
7809592d MC |
8446 | if (!bp->irq_tbl) |
8447 | return -ENOMEM; | |
8448 | ||
8449 | bp->total_irqs = 1; | |
c0c050c5 MC |
8450 | bp->rx_nr_rings = 1; |
8451 | bp->tx_nr_rings = 1; | |
8452 | bp->cp_nr_rings = 1; | |
01657bcd | 8453 | bp->flags |= BNXT_FLAG_SHARED_RINGS; |
c0c050c5 | 8454 | bp->irq_tbl[0].vector = bp->pdev->irq; |
7809592d | 8455 | return 0; |
c0c050c5 MC |
8456 | } |
8457 | ||
7809592d | 8458 | static int bnxt_init_int_mode(struct bnxt *bp) |
c0c050c5 MC |
8459 | { |
8460 | int rc = 0; | |
8461 | ||
8462 | if (bp->flags & BNXT_FLAG_MSIX_CAP) | |
7809592d | 8463 | rc = bnxt_init_msix(bp); |
c0c050c5 | 8464 | |
1fa72e29 | 8465 | if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) { |
c0c050c5 | 8466 | /* fallback to INTA */ |
7809592d | 8467 | rc = bnxt_init_inta(bp); |
c0c050c5 MC |
8468 | } |
8469 | return rc; | |
8470 | } | |
8471 | ||
7809592d MC |
8472 | static void bnxt_clear_int_mode(struct bnxt *bp) |
8473 | { | |
8474 | if (bp->flags & BNXT_FLAG_USING_MSIX) | |
8475 | pci_disable_msix(bp->pdev); | |
8476 | ||
8477 | kfree(bp->irq_tbl); | |
8478 | bp->irq_tbl = NULL; | |
8479 | bp->flags &= ~BNXT_FLAG_USING_MSIX; | |
8480 | } | |
8481 | ||
1b3f0b75 | 8482 | int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init) |
674f50a5 | 8483 | { |
674f50a5 | 8484 | int tcs = netdev_get_num_tc(bp->dev); |
1b3f0b75 | 8485 | bool irq_cleared = false; |
674f50a5 MC |
8486 | int rc; |
8487 | ||
8488 | if (!bnxt_need_reserve_rings(bp)) | |
8489 | return 0; | |
8490 | ||
1b3f0b75 MC |
8491 | if (irq_re_init && BNXT_NEW_RM(bp) && |
8492 | bnxt_get_num_msix(bp) != bp->total_irqs) { | |
ec86f14e | 8493 | bnxt_ulp_irq_stop(bp); |
674f50a5 | 8494 | bnxt_clear_int_mode(bp); |
1b3f0b75 | 8495 | irq_cleared = true; |
36d65be9 MC |
8496 | } |
8497 | rc = __bnxt_reserve_rings(bp); | |
1b3f0b75 | 8498 | if (irq_cleared) { |
36d65be9 MC |
8499 | if (!rc) |
8500 | rc = bnxt_init_int_mode(bp); | |
ec86f14e | 8501 | bnxt_ulp_irq_restart(bp, rc); |
36d65be9 | 8502 | } |
bd3191b5 MC |
8503 | if (!netif_is_rxfh_configured(bp->dev)) |
8504 | bnxt_set_dflt_rss_indir_tbl(bp); | |
f33a305d | 8505 | |
36d65be9 MC |
8506 | if (rc) { |
8507 | netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc); | |
8508 | return rc; | |
674f50a5 MC |
8509 | } |
8510 | if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) { | |
8511 | netdev_err(bp->dev, "tx ring reservation failure\n"); | |
8512 | netdev_reset_tc(bp->dev); | |
8513 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; | |
8514 | return -ENOMEM; | |
8515 | } | |
674f50a5 MC |
8516 | return 0; |
8517 | } | |
8518 | ||
c0c050c5 MC |
8519 | static void bnxt_free_irq(struct bnxt *bp) |
8520 | { | |
8521 | struct bnxt_irq *irq; | |
8522 | int i; | |
8523 | ||
8524 | #ifdef CONFIG_RFS_ACCEL | |
8525 | free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); | |
8526 | bp->dev->rx_cpu_rmap = NULL; | |
8527 | #endif | |
cb98526b | 8528 | if (!bp->irq_tbl || !bp->bnapi) |
c0c050c5 MC |
8529 | return; |
8530 | ||
8531 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
e5811b8c MC |
8532 | int map_idx = bnxt_cp_num_to_irq_num(bp, i); |
8533 | ||
8534 | irq = &bp->irq_tbl[map_idx]; | |
56f0fd80 VV |
8535 | if (irq->requested) { |
8536 | if (irq->have_cpumask) { | |
8537 | irq_set_affinity_hint(irq->vector, NULL); | |
8538 | free_cpumask_var(irq->cpu_mask); | |
8539 | irq->have_cpumask = 0; | |
8540 | } | |
c0c050c5 | 8541 | free_irq(irq->vector, bp->bnapi[i]); |
56f0fd80 VV |
8542 | } |
8543 | ||
c0c050c5 MC |
8544 | irq->requested = 0; |
8545 | } | |
c0c050c5 MC |
8546 | } |
8547 | ||
8548 | static int bnxt_request_irq(struct bnxt *bp) | |
8549 | { | |
b81a90d3 | 8550 | int i, j, rc = 0; |
c0c050c5 MC |
8551 | unsigned long flags = 0; |
8552 | #ifdef CONFIG_RFS_ACCEL | |
e5811b8c | 8553 | struct cpu_rmap *rmap; |
c0c050c5 MC |
8554 | #endif |
8555 | ||
e5811b8c MC |
8556 | rc = bnxt_setup_int_mode(bp); |
8557 | if (rc) { | |
8558 | netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", | |
8559 | rc); | |
8560 | return rc; | |
8561 | } | |
8562 | #ifdef CONFIG_RFS_ACCEL | |
8563 | rmap = bp->dev->rx_cpu_rmap; | |
8564 | #endif | |
c0c050c5 MC |
8565 | if (!(bp->flags & BNXT_FLAG_USING_MSIX)) |
8566 | flags = IRQF_SHARED; | |
8567 | ||
b81a90d3 | 8568 | for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { |
e5811b8c MC |
8569 | int map_idx = bnxt_cp_num_to_irq_num(bp, i); |
8570 | struct bnxt_irq *irq = &bp->irq_tbl[map_idx]; | |
8571 | ||
c0c050c5 | 8572 | #ifdef CONFIG_RFS_ACCEL |
b81a90d3 | 8573 | if (rmap && bp->bnapi[i]->rx_ring) { |
c0c050c5 MC |
8574 | rc = irq_cpu_rmap_add(rmap, irq->vector); |
8575 | if (rc) | |
8576 | netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", | |
b81a90d3 MC |
8577 | j); |
8578 | j++; | |
c0c050c5 MC |
8579 | } |
8580 | #endif | |
8581 | rc = request_irq(irq->vector, irq->handler, flags, irq->name, | |
8582 | bp->bnapi[i]); | |
8583 | if (rc) | |
8584 | break; | |
8585 | ||
8586 | irq->requested = 1; | |
56f0fd80 VV |
8587 | |
8588 | if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) { | |
8589 | int numa_node = dev_to_node(&bp->pdev->dev); | |
8590 | ||
8591 | irq->have_cpumask = 1; | |
8592 | cpumask_set_cpu(cpumask_local_spread(i, numa_node), | |
8593 | irq->cpu_mask); | |
8594 | rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask); | |
8595 | if (rc) { | |
8596 | netdev_warn(bp->dev, | |
8597 | "Set affinity failed, IRQ = %d\n", | |
8598 | irq->vector); | |
8599 | break; | |
8600 | } | |
8601 | } | |
c0c050c5 MC |
8602 | } |
8603 | return rc; | |
8604 | } | |
8605 | ||
8606 | static void bnxt_del_napi(struct bnxt *bp) | |
8607 | { | |
8608 | int i; | |
8609 | ||
8610 | if (!bp->bnapi) | |
8611 | return; | |
8612 | ||
8613 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
8614 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
8615 | ||
8616 | napi_hash_del(&bnapi->napi); | |
8617 | netif_napi_del(&bnapi->napi); | |
8618 | } | |
e5f6f564 ED |
8619 | /* We called napi_hash_del() before netif_napi_del(), we need |
8620 | * to respect an RCU grace period before freeing napi structures. | |
8621 | */ | |
8622 | synchronize_net(); | |
c0c050c5 MC |
8623 | } |
8624 | ||
8625 | static void bnxt_init_napi(struct bnxt *bp) | |
8626 | { | |
8627 | int i; | |
10bbdaf5 | 8628 | unsigned int cp_nr_rings = bp->cp_nr_rings; |
c0c050c5 MC |
8629 | struct bnxt_napi *bnapi; |
8630 | ||
8631 | if (bp->flags & BNXT_FLAG_USING_MSIX) { | |
0fcec985 MC |
8632 | int (*poll_fn)(struct napi_struct *, int) = bnxt_poll; |
8633 | ||
8634 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
8635 | poll_fn = bnxt_poll_p5; | |
8636 | else if (BNXT_CHIP_TYPE_NITRO_A0(bp)) | |
10bbdaf5 PS |
8637 | cp_nr_rings--; |
8638 | for (i = 0; i < cp_nr_rings; i++) { | |
c0c050c5 | 8639 | bnapi = bp->bnapi[i]; |
0fcec985 | 8640 | netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64); |
c0c050c5 | 8641 | } |
10bbdaf5 PS |
8642 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { |
8643 | bnapi = bp->bnapi[cp_nr_rings]; | |
8644 | netif_napi_add(bp->dev, &bnapi->napi, | |
8645 | bnxt_poll_nitroa0, 64); | |
10bbdaf5 | 8646 | } |
c0c050c5 MC |
8647 | } else { |
8648 | bnapi = bp->bnapi[0]; | |
8649 | netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64); | |
c0c050c5 MC |
8650 | } |
8651 | } | |
8652 | ||
8653 | static void bnxt_disable_napi(struct bnxt *bp) | |
8654 | { | |
8655 | int i; | |
8656 | ||
8657 | if (!bp->bnapi) | |
8658 | return; | |
8659 | ||
0bc0b97f AG |
8660 | for (i = 0; i < bp->cp_nr_rings; i++) { |
8661 | struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; | |
8662 | ||
8663 | if (bp->bnapi[i]->rx_ring) | |
8664 | cancel_work_sync(&cpr->dim.work); | |
8665 | ||
c0c050c5 | 8666 | napi_disable(&bp->bnapi[i]->napi); |
0bc0b97f | 8667 | } |
c0c050c5 MC |
8668 | } |
8669 | ||
8670 | static void bnxt_enable_napi(struct bnxt *bp) | |
8671 | { | |
8672 | int i; | |
8673 | ||
8674 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
6a8788f2 | 8675 | struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; |
fa7e2812 | 8676 | bp->bnapi[i]->in_reset = false; |
6a8788f2 AG |
8677 | |
8678 | if (bp->bnapi[i]->rx_ring) { | |
8679 | INIT_WORK(&cpr->dim.work, bnxt_dim_work); | |
c002bd52 | 8680 | cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; |
6a8788f2 | 8681 | } |
c0c050c5 MC |
8682 | napi_enable(&bp->bnapi[i]->napi); |
8683 | } | |
8684 | } | |
8685 | ||
7df4ae9f | 8686 | void bnxt_tx_disable(struct bnxt *bp) |
c0c050c5 MC |
8687 | { |
8688 | int i; | |
c0c050c5 | 8689 | struct bnxt_tx_ring_info *txr; |
c0c050c5 | 8690 | |
b6ab4b01 | 8691 | if (bp->tx_ring) { |
c0c050c5 | 8692 | for (i = 0; i < bp->tx_nr_rings; i++) { |
b6ab4b01 | 8693 | txr = &bp->tx_ring[i]; |
c0c050c5 | 8694 | txr->dev_state = BNXT_DEV_STATE_CLOSING; |
c0c050c5 MC |
8695 | } |
8696 | } | |
8697 | /* Stop all TX queues */ | |
8698 | netif_tx_disable(bp->dev); | |
8699 | netif_carrier_off(bp->dev); | |
8700 | } | |
8701 | ||
7df4ae9f | 8702 | void bnxt_tx_enable(struct bnxt *bp) |
c0c050c5 MC |
8703 | { |
8704 | int i; | |
c0c050c5 | 8705 | struct bnxt_tx_ring_info *txr; |
c0c050c5 MC |
8706 | |
8707 | for (i = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 8708 | txr = &bp->tx_ring[i]; |
c0c050c5 MC |
8709 | txr->dev_state = 0; |
8710 | } | |
8711 | netif_tx_wake_all_queues(bp->dev); | |
8712 | if (bp->link_info.link_up) | |
8713 | netif_carrier_on(bp->dev); | |
8714 | } | |
8715 | ||
8716 | static void bnxt_report_link(struct bnxt *bp) | |
8717 | { | |
8718 | if (bp->link_info.link_up) { | |
8719 | const char *duplex; | |
8720 | const char *flow_ctrl; | |
38a21b34 DK |
8721 | u32 speed; |
8722 | u16 fec; | |
c0c050c5 MC |
8723 | |
8724 | netif_carrier_on(bp->dev); | |
8725 | if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) | |
8726 | duplex = "full"; | |
8727 | else | |
8728 | duplex = "half"; | |
8729 | if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) | |
8730 | flow_ctrl = "ON - receive & transmit"; | |
8731 | else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) | |
8732 | flow_ctrl = "ON - transmit"; | |
8733 | else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) | |
8734 | flow_ctrl = "ON - receive"; | |
8735 | else | |
8736 | flow_ctrl = "none"; | |
8737 | speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); | |
38a21b34 | 8738 | netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n", |
c0c050c5 | 8739 | speed, duplex, flow_ctrl); |
170ce013 MC |
8740 | if (bp->flags & BNXT_FLAG_EEE_CAP) |
8741 | netdev_info(bp->dev, "EEE is %s\n", | |
8742 | bp->eee.eee_active ? "active" : | |
8743 | "not active"); | |
e70c752f MC |
8744 | fec = bp->link_info.fec_cfg; |
8745 | if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED)) | |
8746 | netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n", | |
8747 | (fec & BNXT_FEC_AUTONEG) ? "on" : "off", | |
8748 | (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" : | |
8749 | (fec & BNXT_FEC_ENC_RS) ? "RS" : "None"); | |
c0c050c5 MC |
8750 | } else { |
8751 | netif_carrier_off(bp->dev); | |
8752 | netdev_err(bp->dev, "NIC Link is Down\n"); | |
8753 | } | |
8754 | } | |
8755 | ||
170ce013 MC |
8756 | static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) |
8757 | { | |
8758 | int rc = 0; | |
8759 | struct hwrm_port_phy_qcaps_input req = {0}; | |
8760 | struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
93ed8117 | 8761 | struct bnxt_link_info *link_info = &bp->link_info; |
170ce013 | 8762 | |
ba642ab7 MC |
8763 | bp->flags &= ~BNXT_FLAG_EEE_CAP; |
8764 | if (bp->test_info) | |
8a60efd1 MC |
8765 | bp->test_info->flags &= ~(BNXT_TEST_FL_EXT_LPBK | |
8766 | BNXT_TEST_FL_AN_PHY_LPBK); | |
170ce013 MC |
8767 | if (bp->hwrm_spec_code < 0x10201) |
8768 | return 0; | |
8769 | ||
8770 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); | |
8771 | ||
8772 | mutex_lock(&bp->hwrm_cmd_lock); | |
8773 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8774 | if (rc) | |
8775 | goto hwrm_phy_qcaps_exit; | |
8776 | ||
acb20054 | 8777 | if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) { |
170ce013 MC |
8778 | struct ethtool_eee *eee = &bp->eee; |
8779 | u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode); | |
8780 | ||
8781 | bp->flags |= BNXT_FLAG_EEE_CAP; | |
8782 | eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); | |
8783 | bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) & | |
8784 | PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK; | |
8785 | bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) & | |
8786 | PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK; | |
8787 | } | |
55fd0cf3 MC |
8788 | if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) { |
8789 | if (bp->test_info) | |
8790 | bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK; | |
8791 | } | |
8a60efd1 MC |
8792 | if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED) { |
8793 | if (bp->test_info) | |
8794 | bp->test_info->flags |= BNXT_TEST_FL_AN_PHY_LPBK; | |
8795 | } | |
c7e457f4 MC |
8796 | if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED) { |
8797 | if (BNXT_PF(bp)) | |
8798 | bp->fw_cap |= BNXT_FW_CAP_SHARED_PORT_CFG; | |
8799 | } | |
fea6b333 MC |
8800 | if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET) |
8801 | bp->fw_cap |= BNXT_FW_CAP_PORT_STATS_NO_RESET; | |
8802 | ||
520ad89a MC |
8803 | if (resp->supported_speeds_auto_mode) |
8804 | link_info->support_auto_speeds = | |
8805 | le16_to_cpu(resp->supported_speeds_auto_mode); | |
170ce013 | 8806 | |
d5430d31 MC |
8807 | bp->port_count = resp->port_cnt; |
8808 | ||
170ce013 MC |
8809 | hwrm_phy_qcaps_exit: |
8810 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8811 | return rc; | |
8812 | } | |
8813 | ||
c0c050c5 MC |
8814 | static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) |
8815 | { | |
8816 | int rc = 0; | |
8817 | struct bnxt_link_info *link_info = &bp->link_info; | |
8818 | struct hwrm_port_phy_qcfg_input req = {0}; | |
8819 | struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
8820 | u8 link_up = link_info->link_up; | |
286ef9d6 | 8821 | u16 diff; |
c0c050c5 MC |
8822 | |
8823 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1); | |
8824 | ||
8825 | mutex_lock(&bp->hwrm_cmd_lock); | |
8826 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8827 | if (rc) { | |
8828 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8829 | return rc; | |
8830 | } | |
8831 | ||
8832 | memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); | |
8833 | link_info->phy_link_status = resp->link; | |
acb20054 MC |
8834 | link_info->duplex = resp->duplex_cfg; |
8835 | if (bp->hwrm_spec_code >= 0x10800) | |
8836 | link_info->duplex = resp->duplex_state; | |
c0c050c5 MC |
8837 | link_info->pause = resp->pause; |
8838 | link_info->auto_mode = resp->auto_mode; | |
8839 | link_info->auto_pause_setting = resp->auto_pause; | |
3277360e | 8840 | link_info->lp_pause = resp->link_partner_adv_pause; |
c0c050c5 | 8841 | link_info->force_pause_setting = resp->force_pause; |
acb20054 | 8842 | link_info->duplex_setting = resp->duplex_cfg; |
c0c050c5 MC |
8843 | if (link_info->phy_link_status == BNXT_LINK_LINK) |
8844 | link_info->link_speed = le16_to_cpu(resp->link_speed); | |
8845 | else | |
8846 | link_info->link_speed = 0; | |
8847 | link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); | |
c0c050c5 MC |
8848 | link_info->support_speeds = le16_to_cpu(resp->support_speeds); |
8849 | link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); | |
3277360e MC |
8850 | link_info->lp_auto_link_speeds = |
8851 | le16_to_cpu(resp->link_partner_adv_speeds); | |
c0c050c5 MC |
8852 | link_info->preemphasis = le32_to_cpu(resp->preemphasis); |
8853 | link_info->phy_ver[0] = resp->phy_maj; | |
8854 | link_info->phy_ver[1] = resp->phy_min; | |
8855 | link_info->phy_ver[2] = resp->phy_bld; | |
8856 | link_info->media_type = resp->media_type; | |
03efbec0 | 8857 | link_info->phy_type = resp->phy_type; |
11f15ed3 | 8858 | link_info->transceiver = resp->xcvr_pkg_type; |
170ce013 MC |
8859 | link_info->phy_addr = resp->eee_config_phy_addr & |
8860 | PORT_PHY_QCFG_RESP_PHY_ADDR_MASK; | |
42ee18fe | 8861 | link_info->module_status = resp->module_status; |
170ce013 MC |
8862 | |
8863 | if (bp->flags & BNXT_FLAG_EEE_CAP) { | |
8864 | struct ethtool_eee *eee = &bp->eee; | |
8865 | u16 fw_speeds; | |
8866 | ||
8867 | eee->eee_active = 0; | |
8868 | if (resp->eee_config_phy_addr & | |
8869 | PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) { | |
8870 | eee->eee_active = 1; | |
8871 | fw_speeds = le16_to_cpu( | |
8872 | resp->link_partner_adv_eee_link_speed_mask); | |
8873 | eee->lp_advertised = | |
8874 | _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); | |
8875 | } | |
8876 | ||
8877 | /* Pull initial EEE config */ | |
8878 | if (!chng_link_state) { | |
8879 | if (resp->eee_config_phy_addr & | |
8880 | PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED) | |
8881 | eee->eee_enabled = 1; | |
c0c050c5 | 8882 | |
170ce013 MC |
8883 | fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask); |
8884 | eee->advertised = | |
8885 | _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); | |
8886 | ||
8887 | if (resp->eee_config_phy_addr & | |
8888 | PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) { | |
8889 | __le32 tmr; | |
8890 | ||
8891 | eee->tx_lpi_enabled = 1; | |
8892 | tmr = resp->xcvr_identifier_type_tx_lpi_timer; | |
8893 | eee->tx_lpi_timer = le32_to_cpu(tmr) & | |
8894 | PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK; | |
8895 | } | |
8896 | } | |
8897 | } | |
e70c752f MC |
8898 | |
8899 | link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED; | |
8900 | if (bp->hwrm_spec_code >= 0x10504) | |
8901 | link_info->fec_cfg = le16_to_cpu(resp->fec_cfg); | |
8902 | ||
c0c050c5 MC |
8903 | /* TODO: need to add more logic to report VF link */ |
8904 | if (chng_link_state) { | |
8905 | if (link_info->phy_link_status == BNXT_LINK_LINK) | |
8906 | link_info->link_up = 1; | |
8907 | else | |
8908 | link_info->link_up = 0; | |
8909 | if (link_up != link_info->link_up) | |
8910 | bnxt_report_link(bp); | |
8911 | } else { | |
8912 | /* alwasy link down if not require to update link state */ | |
8913 | link_info->link_up = 0; | |
8914 | } | |
8915 | mutex_unlock(&bp->hwrm_cmd_lock); | |
286ef9d6 | 8916 | |
c7e457f4 | 8917 | if (!BNXT_PHY_CFG_ABLE(bp)) |
dac04907 MC |
8918 | return 0; |
8919 | ||
286ef9d6 MC |
8920 | diff = link_info->support_auto_speeds ^ link_info->advertising; |
8921 | if ((link_info->support_auto_speeds | diff) != | |
8922 | link_info->support_auto_speeds) { | |
8923 | /* An advertised speed is no longer supported, so we need to | |
0eaa24b9 MC |
8924 | * update the advertisement settings. Caller holds RTNL |
8925 | * so we can modify link settings. | |
286ef9d6 | 8926 | */ |
286ef9d6 | 8927 | link_info->advertising = link_info->support_auto_speeds; |
0eaa24b9 | 8928 | if (link_info->autoneg & BNXT_AUTONEG_SPEED) |
286ef9d6 | 8929 | bnxt_hwrm_set_link_setting(bp, true, false); |
286ef9d6 | 8930 | } |
c0c050c5 MC |
8931 | return 0; |
8932 | } | |
8933 | ||
10289bec MC |
8934 | static void bnxt_get_port_module_status(struct bnxt *bp) |
8935 | { | |
8936 | struct bnxt_link_info *link_info = &bp->link_info; | |
8937 | struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; | |
8938 | u8 module_status; | |
8939 | ||
8940 | if (bnxt_update_link(bp, true)) | |
8941 | return; | |
8942 | ||
8943 | module_status = link_info->module_status; | |
8944 | switch (module_status) { | |
8945 | case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX: | |
8946 | case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: | |
8947 | case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG: | |
8948 | netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n", | |
8949 | bp->pf.port_id); | |
8950 | if (bp->hwrm_spec_code >= 0x10201) { | |
8951 | netdev_warn(bp->dev, "Module part number %s\n", | |
8952 | resp->phy_vendor_partnumber); | |
8953 | } | |
8954 | if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX) | |
8955 | netdev_warn(bp->dev, "TX is disabled\n"); | |
8956 | if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN) | |
8957 | netdev_warn(bp->dev, "SFP+ module is shutdown\n"); | |
8958 | } | |
8959 | } | |
8960 | ||
c0c050c5 MC |
8961 | static void |
8962 | bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) | |
8963 | { | |
8964 | if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { | |
c9ee9516 MC |
8965 | if (bp->hwrm_spec_code >= 0x10201) |
8966 | req->auto_pause = | |
8967 | PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; | |
c0c050c5 MC |
8968 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) |
8969 | req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; | |
8970 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) | |
49b5c7a1 | 8971 | req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX; |
c0c050c5 MC |
8972 | req->enables |= |
8973 | cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); | |
8974 | } else { | |
8975 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) | |
8976 | req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; | |
8977 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) | |
8978 | req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; | |
8979 | req->enables |= | |
8980 | cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); | |
c9ee9516 MC |
8981 | if (bp->hwrm_spec_code >= 0x10201) { |
8982 | req->auto_pause = req->force_pause; | |
8983 | req->enables |= cpu_to_le32( | |
8984 | PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); | |
8985 | } | |
c0c050c5 MC |
8986 | } |
8987 | } | |
8988 | ||
8989 | static void bnxt_hwrm_set_link_common(struct bnxt *bp, | |
8990 | struct hwrm_port_phy_cfg_input *req) | |
8991 | { | |
8992 | u8 autoneg = bp->link_info.autoneg; | |
8993 | u16 fw_link_speed = bp->link_info.req_link_speed; | |
68515a18 | 8994 | u16 advertising = bp->link_info.advertising; |
c0c050c5 MC |
8995 | |
8996 | if (autoneg & BNXT_AUTONEG_SPEED) { | |
8997 | req->auto_mode |= | |
11f15ed3 | 8998 | PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK; |
c0c050c5 MC |
8999 | |
9000 | req->enables |= cpu_to_le32( | |
9001 | PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); | |
9002 | req->auto_link_speed_mask = cpu_to_le16(advertising); | |
9003 | ||
9004 | req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); | |
9005 | req->flags |= | |
9006 | cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); | |
9007 | } else { | |
9008 | req->force_link_speed = cpu_to_le16(fw_link_speed); | |
9009 | req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); | |
9010 | } | |
9011 | ||
c0c050c5 MC |
9012 | /* tell chimp that the setting takes effect immediately */ |
9013 | req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); | |
9014 | } | |
9015 | ||
9016 | int bnxt_hwrm_set_pause(struct bnxt *bp) | |
9017 | { | |
9018 | struct hwrm_port_phy_cfg_input req = {0}; | |
9019 | int rc; | |
9020 | ||
9021 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); | |
9022 | bnxt_hwrm_set_pause_common(bp, &req); | |
9023 | ||
9024 | if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || | |
9025 | bp->link_info.force_link_chng) | |
9026 | bnxt_hwrm_set_link_common(bp, &req); | |
9027 | ||
9028 | mutex_lock(&bp->hwrm_cmd_lock); | |
9029 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
9030 | if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { | |
9031 | /* since changing of pause setting doesn't trigger any link | |
9032 | * change event, the driver needs to update the current pause | |
9033 | * result upon successfully return of the phy_cfg command | |
9034 | */ | |
9035 | bp->link_info.pause = | |
9036 | bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; | |
9037 | bp->link_info.auto_pause_setting = 0; | |
9038 | if (!bp->link_info.force_link_chng) | |
9039 | bnxt_report_link(bp); | |
9040 | } | |
9041 | bp->link_info.force_link_chng = false; | |
9042 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9043 | return rc; | |
9044 | } | |
9045 | ||
939f7f0c MC |
9046 | static void bnxt_hwrm_set_eee(struct bnxt *bp, |
9047 | struct hwrm_port_phy_cfg_input *req) | |
9048 | { | |
9049 | struct ethtool_eee *eee = &bp->eee; | |
9050 | ||
9051 | if (eee->eee_enabled) { | |
9052 | u16 eee_speeds; | |
9053 | u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE; | |
9054 | ||
9055 | if (eee->tx_lpi_enabled) | |
9056 | flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE; | |
9057 | else | |
9058 | flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE; | |
9059 | ||
9060 | req->flags |= cpu_to_le32(flags); | |
9061 | eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); | |
9062 | req->eee_link_speed_mask = cpu_to_le16(eee_speeds); | |
9063 | req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer); | |
9064 | } else { | |
9065 | req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE); | |
9066 | } | |
9067 | } | |
9068 | ||
9069 | int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee) | |
c0c050c5 MC |
9070 | { |
9071 | struct hwrm_port_phy_cfg_input req = {0}; | |
9072 | ||
9073 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); | |
9074 | if (set_pause) | |
9075 | bnxt_hwrm_set_pause_common(bp, &req); | |
9076 | ||
9077 | bnxt_hwrm_set_link_common(bp, &req); | |
939f7f0c MC |
9078 | |
9079 | if (set_eee) | |
9080 | bnxt_hwrm_set_eee(bp, &req); | |
c0c050c5 MC |
9081 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
9082 | } | |
9083 | ||
33f7d55f MC |
9084 | static int bnxt_hwrm_shutdown_link(struct bnxt *bp) |
9085 | { | |
9086 | struct hwrm_port_phy_cfg_input req = {0}; | |
9087 | ||
567b2abe | 9088 | if (!BNXT_SINGLE_PF(bp)) |
33f7d55f MC |
9089 | return 0; |
9090 | ||
9091 | if (pci_num_vf(bp->pdev)) | |
9092 | return 0; | |
9093 | ||
9094 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); | |
16d663a6 | 9095 | req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN); |
33f7d55f MC |
9096 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
9097 | } | |
9098 | ||
ec5d31e3 MC |
9099 | static int bnxt_fw_init_one(struct bnxt *bp); |
9100 | ||
25e1acd6 MC |
9101 | static int bnxt_hwrm_if_change(struct bnxt *bp, bool up) |
9102 | { | |
9103 | struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr; | |
9104 | struct hwrm_func_drv_if_change_input req = {0}; | |
ec5d31e3 MC |
9105 | bool resc_reinit = false, fw_reset = false; |
9106 | u32 flags = 0; | |
25e1acd6 MC |
9107 | int rc; |
9108 | ||
9109 | if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE)) | |
9110 | return 0; | |
9111 | ||
9112 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1); | |
9113 | if (up) | |
9114 | req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP); | |
9115 | mutex_lock(&bp->hwrm_cmd_lock); | |
9116 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
ec5d31e3 MC |
9117 | if (!rc) |
9118 | flags = le32_to_cpu(resp->flags); | |
25e1acd6 | 9119 | mutex_unlock(&bp->hwrm_cmd_lock); |
ec5d31e3 MC |
9120 | if (rc) |
9121 | return rc; | |
25e1acd6 | 9122 | |
ec5d31e3 MC |
9123 | if (!up) |
9124 | return 0; | |
25e1acd6 | 9125 | |
ec5d31e3 MC |
9126 | if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE) |
9127 | resc_reinit = true; | |
9128 | if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE) | |
9129 | fw_reset = true; | |
9130 | ||
3bc7d4a3 MC |
9131 | if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) { |
9132 | netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n"); | |
9133 | return -ENODEV; | |
9134 | } | |
ec5d31e3 MC |
9135 | if (resc_reinit || fw_reset) { |
9136 | if (fw_reset) { | |
f3a6d206 VV |
9137 | if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) |
9138 | bnxt_ulp_stop(bp); | |
325f85f3 MC |
9139 | bnxt_free_ctx_mem(bp); |
9140 | kfree(bp->ctx); | |
9141 | bp->ctx = NULL; | |
843d699d | 9142 | bnxt_dcb_free(bp); |
ec5d31e3 MC |
9143 | rc = bnxt_fw_init_one(bp); |
9144 | if (rc) { | |
9145 | set_bit(BNXT_STATE_ABORT_ERR, &bp->state); | |
9146 | return rc; | |
9147 | } | |
9148 | bnxt_clear_int_mode(bp); | |
9149 | rc = bnxt_init_int_mode(bp); | |
9150 | if (rc) { | |
9151 | netdev_err(bp->dev, "init int mode failed\n"); | |
9152 | return rc; | |
9153 | } | |
9154 | set_bit(BNXT_STATE_FW_RESET_DET, &bp->state); | |
9155 | } | |
9156 | if (BNXT_NEW_RM(bp)) { | |
9157 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
9158 | ||
9159 | rc = bnxt_hwrm_func_resc_qcaps(bp, true); | |
9160 | hw_resc->resv_cp_rings = 0; | |
9161 | hw_resc->resv_stat_ctxs = 0; | |
9162 | hw_resc->resv_irqs = 0; | |
9163 | hw_resc->resv_tx_rings = 0; | |
9164 | hw_resc->resv_rx_rings = 0; | |
9165 | hw_resc->resv_hw_ring_grps = 0; | |
9166 | hw_resc->resv_vnics = 0; | |
9167 | if (!fw_reset) { | |
9168 | bp->tx_nr_rings = 0; | |
9169 | bp->rx_nr_rings = 0; | |
9170 | } | |
9171 | } | |
25e1acd6 | 9172 | } |
ec5d31e3 | 9173 | return 0; |
25e1acd6 MC |
9174 | } |
9175 | ||
5ad2cbee MC |
9176 | static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) |
9177 | { | |
9178 | struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
9179 | struct hwrm_port_led_qcaps_input req = {0}; | |
9180 | struct bnxt_pf_info *pf = &bp->pf; | |
9181 | int rc; | |
9182 | ||
ba642ab7 | 9183 | bp->num_leds = 0; |
5ad2cbee MC |
9184 | if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601) |
9185 | return 0; | |
9186 | ||
9187 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1); | |
9188 | req.port_id = cpu_to_le16(pf->port_id); | |
9189 | mutex_lock(&bp->hwrm_cmd_lock); | |
9190 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
9191 | if (rc) { | |
9192 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9193 | return rc; | |
9194 | } | |
9195 | if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) { | |
9196 | int i; | |
9197 | ||
9198 | bp->num_leds = resp->num_leds; | |
9199 | memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) * | |
9200 | bp->num_leds); | |
9201 | for (i = 0; i < bp->num_leds; i++) { | |
9202 | struct bnxt_led_info *led = &bp->leds[i]; | |
9203 | __le16 caps = led->led_state_caps; | |
9204 | ||
9205 | if (!led->led_group_id || | |
9206 | !BNXT_LED_ALT_BLINK_CAP(caps)) { | |
9207 | bp->num_leds = 0; | |
9208 | break; | |
9209 | } | |
9210 | } | |
9211 | } | |
9212 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9213 | return 0; | |
9214 | } | |
9215 | ||
5282db6c MC |
9216 | int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp) |
9217 | { | |
9218 | struct hwrm_wol_filter_alloc_input req = {0}; | |
9219 | struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
9220 | int rc; | |
9221 | ||
9222 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1); | |
9223 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
9224 | req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT; | |
9225 | req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS); | |
9226 | memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN); | |
9227 | mutex_lock(&bp->hwrm_cmd_lock); | |
9228 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
9229 | if (!rc) | |
9230 | bp->wol_filter_id = resp->wol_filter_id; | |
9231 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9232 | return rc; | |
9233 | } | |
9234 | ||
9235 | int bnxt_hwrm_free_wol_fltr(struct bnxt *bp) | |
9236 | { | |
9237 | struct hwrm_wol_filter_free_input req = {0}; | |
5282db6c MC |
9238 | |
9239 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1); | |
9240 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
9241 | req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID); | |
9242 | req.wol_filter_id = bp->wol_filter_id; | |
9f90445c | 9243 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
5282db6c MC |
9244 | } |
9245 | ||
c1ef146a MC |
9246 | static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle) |
9247 | { | |
9248 | struct hwrm_wol_filter_qcfg_input req = {0}; | |
9249 | struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
9250 | u16 next_handle = 0; | |
9251 | int rc; | |
9252 | ||
9253 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1); | |
9254 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
9255 | req.handle = cpu_to_le16(handle); | |
9256 | mutex_lock(&bp->hwrm_cmd_lock); | |
9257 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
9258 | if (!rc) { | |
9259 | next_handle = le16_to_cpu(resp->next_handle); | |
9260 | if (next_handle != 0) { | |
9261 | if (resp->wol_type == | |
9262 | WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) { | |
9263 | bp->wol = 1; | |
9264 | bp->wol_filter_id = resp->wol_filter_id; | |
9265 | } | |
9266 | } | |
9267 | } | |
9268 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9269 | return next_handle; | |
9270 | } | |
9271 | ||
9272 | static void bnxt_get_wol_settings(struct bnxt *bp) | |
9273 | { | |
9274 | u16 handle = 0; | |
9275 | ||
ba642ab7 | 9276 | bp->wol = 0; |
c1ef146a MC |
9277 | if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP)) |
9278 | return; | |
9279 | ||
9280 | do { | |
9281 | handle = bnxt_hwrm_get_wol_fltrs(bp, handle); | |
9282 | } while (handle && handle != 0xffff); | |
9283 | } | |
9284 | ||
cde49a42 VV |
9285 | #ifdef CONFIG_BNXT_HWMON |
9286 | static ssize_t bnxt_show_temp(struct device *dev, | |
9287 | struct device_attribute *devattr, char *buf) | |
9288 | { | |
9289 | struct hwrm_temp_monitor_query_input req = {0}; | |
9290 | struct hwrm_temp_monitor_query_output *resp; | |
9291 | struct bnxt *bp = dev_get_drvdata(dev); | |
9292 | u32 temp = 0; | |
9293 | ||
9294 | resp = bp->hwrm_cmd_resp_addr; | |
9295 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1); | |
9296 | mutex_lock(&bp->hwrm_cmd_lock); | |
9297 | if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT)) | |
9298 | temp = resp->temp * 1000; /* display millidegree */ | |
9299 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9300 | ||
9301 | return sprintf(buf, "%u\n", temp); | |
9302 | } | |
9303 | static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0); | |
9304 | ||
9305 | static struct attribute *bnxt_attrs[] = { | |
9306 | &sensor_dev_attr_temp1_input.dev_attr.attr, | |
9307 | NULL | |
9308 | }; | |
9309 | ATTRIBUTE_GROUPS(bnxt); | |
9310 | ||
9311 | static void bnxt_hwmon_close(struct bnxt *bp) | |
9312 | { | |
9313 | if (bp->hwmon_dev) { | |
9314 | hwmon_device_unregister(bp->hwmon_dev); | |
9315 | bp->hwmon_dev = NULL; | |
9316 | } | |
9317 | } | |
9318 | ||
9319 | static void bnxt_hwmon_open(struct bnxt *bp) | |
9320 | { | |
9321 | struct pci_dev *pdev = bp->pdev; | |
9322 | ||
ba642ab7 MC |
9323 | if (bp->hwmon_dev) |
9324 | return; | |
9325 | ||
cde49a42 VV |
9326 | bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, |
9327 | DRV_MODULE_NAME, bp, | |
9328 | bnxt_groups); | |
9329 | if (IS_ERR(bp->hwmon_dev)) { | |
9330 | bp->hwmon_dev = NULL; | |
9331 | dev_warn(&pdev->dev, "Cannot register hwmon device\n"); | |
9332 | } | |
9333 | } | |
9334 | #else | |
9335 | static void bnxt_hwmon_close(struct bnxt *bp) | |
9336 | { | |
9337 | } | |
9338 | ||
9339 | static void bnxt_hwmon_open(struct bnxt *bp) | |
9340 | { | |
9341 | } | |
9342 | #endif | |
9343 | ||
939f7f0c MC |
9344 | static bool bnxt_eee_config_ok(struct bnxt *bp) |
9345 | { | |
9346 | struct ethtool_eee *eee = &bp->eee; | |
9347 | struct bnxt_link_info *link_info = &bp->link_info; | |
9348 | ||
9349 | if (!(bp->flags & BNXT_FLAG_EEE_CAP)) | |
9350 | return true; | |
9351 | ||
9352 | if (eee->eee_enabled) { | |
9353 | u32 advertising = | |
9354 | _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); | |
9355 | ||
9356 | if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { | |
9357 | eee->eee_enabled = 0; | |
9358 | return false; | |
9359 | } | |
9360 | if (eee->advertised & ~advertising) { | |
9361 | eee->advertised = advertising & eee->supported; | |
9362 | return false; | |
9363 | } | |
9364 | } | |
9365 | return true; | |
9366 | } | |
9367 | ||
c0c050c5 MC |
9368 | static int bnxt_update_phy_setting(struct bnxt *bp) |
9369 | { | |
9370 | int rc; | |
9371 | bool update_link = false; | |
9372 | bool update_pause = false; | |
939f7f0c | 9373 | bool update_eee = false; |
c0c050c5 MC |
9374 | struct bnxt_link_info *link_info = &bp->link_info; |
9375 | ||
9376 | rc = bnxt_update_link(bp, true); | |
9377 | if (rc) { | |
9378 | netdev_err(bp->dev, "failed to update link (rc: %x)\n", | |
9379 | rc); | |
9380 | return rc; | |
9381 | } | |
33dac24a MC |
9382 | if (!BNXT_SINGLE_PF(bp)) |
9383 | return 0; | |
9384 | ||
c0c050c5 | 9385 | if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && |
c9ee9516 MC |
9386 | (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) != |
9387 | link_info->req_flow_ctrl) | |
c0c050c5 MC |
9388 | update_pause = true; |
9389 | if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && | |
9390 | link_info->force_pause_setting != link_info->req_flow_ctrl) | |
9391 | update_pause = true; | |
c0c050c5 MC |
9392 | if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { |
9393 | if (BNXT_AUTO_MODE(link_info->auto_mode)) | |
9394 | update_link = true; | |
9395 | if (link_info->req_link_speed != link_info->force_link_speed) | |
9396 | update_link = true; | |
de73018f MC |
9397 | if (link_info->req_duplex != link_info->duplex_setting) |
9398 | update_link = true; | |
c0c050c5 MC |
9399 | } else { |
9400 | if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) | |
9401 | update_link = true; | |
9402 | if (link_info->advertising != link_info->auto_link_speeds) | |
9403 | update_link = true; | |
c0c050c5 MC |
9404 | } |
9405 | ||
16d663a6 MC |
9406 | /* The last close may have shutdown the link, so need to call |
9407 | * PHY_CFG to bring it back up. | |
9408 | */ | |
83d8f5e9 | 9409 | if (!bp->link_info.link_up) |
16d663a6 MC |
9410 | update_link = true; |
9411 | ||
939f7f0c MC |
9412 | if (!bnxt_eee_config_ok(bp)) |
9413 | update_eee = true; | |
9414 | ||
c0c050c5 | 9415 | if (update_link) |
939f7f0c | 9416 | rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee); |
c0c050c5 MC |
9417 | else if (update_pause) |
9418 | rc = bnxt_hwrm_set_pause(bp); | |
9419 | if (rc) { | |
9420 | netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", | |
9421 | rc); | |
9422 | return rc; | |
9423 | } | |
9424 | ||
9425 | return rc; | |
9426 | } | |
9427 | ||
11809490 JH |
9428 | /* Common routine to pre-map certain register block to different GRC window. |
9429 | * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows | |
9430 | * in PF and 3 windows in VF that can be customized to map in different | |
9431 | * register blocks. | |
9432 | */ | |
9433 | static void bnxt_preset_reg_win(struct bnxt *bp) | |
9434 | { | |
9435 | if (BNXT_PF(bp)) { | |
9436 | /* CAG registers map to GRC window #4 */ | |
9437 | writel(BNXT_CAG_REG_BASE, | |
9438 | bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); | |
9439 | } | |
9440 | } | |
9441 | ||
47558acd MC |
9442 | static int bnxt_init_dflt_ring_mode(struct bnxt *bp); |
9443 | ||
c0c050c5 MC |
9444 | static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) |
9445 | { | |
9446 | int rc = 0; | |
9447 | ||
11809490 | 9448 | bnxt_preset_reg_win(bp); |
c0c050c5 MC |
9449 | netif_carrier_off(bp->dev); |
9450 | if (irq_re_init) { | |
47558acd MC |
9451 | /* Reserve rings now if none were reserved at driver probe. */ |
9452 | rc = bnxt_init_dflt_ring_mode(bp); | |
9453 | if (rc) { | |
9454 | netdev_err(bp->dev, "Failed to reserve default rings at open\n"); | |
9455 | return rc; | |
9456 | } | |
c0c050c5 | 9457 | } |
1b3f0b75 | 9458 | rc = bnxt_reserve_rings(bp, irq_re_init); |
41e8d798 MC |
9459 | if (rc) |
9460 | return rc; | |
c0c050c5 MC |
9461 | if ((bp->flags & BNXT_FLAG_RFS) && |
9462 | !(bp->flags & BNXT_FLAG_USING_MSIX)) { | |
9463 | /* disable RFS if falling back to INTA */ | |
9464 | bp->dev->hw_features &= ~NETIF_F_NTUPLE; | |
9465 | bp->flags &= ~BNXT_FLAG_RFS; | |
9466 | } | |
9467 | ||
9468 | rc = bnxt_alloc_mem(bp, irq_re_init); | |
9469 | if (rc) { | |
9470 | netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); | |
9471 | goto open_err_free_mem; | |
9472 | } | |
9473 | ||
9474 | if (irq_re_init) { | |
9475 | bnxt_init_napi(bp); | |
9476 | rc = bnxt_request_irq(bp); | |
9477 | if (rc) { | |
9478 | netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); | |
c58387ab | 9479 | goto open_err_irq; |
c0c050c5 MC |
9480 | } |
9481 | } | |
9482 | ||
9483 | bnxt_enable_napi(bp); | |
cabfb09d | 9484 | bnxt_debug_dev_init(bp); |
c0c050c5 MC |
9485 | |
9486 | rc = bnxt_init_nic(bp, irq_re_init); | |
9487 | if (rc) { | |
9488 | netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); | |
9489 | goto open_err; | |
9490 | } | |
9491 | ||
9492 | if (link_re_init) { | |
e2dc9b6e | 9493 | mutex_lock(&bp->link_lock); |
c0c050c5 | 9494 | rc = bnxt_update_phy_setting(bp); |
e2dc9b6e | 9495 | mutex_unlock(&bp->link_lock); |
a1ef4a79 | 9496 | if (rc) { |
ba41d46f | 9497 | netdev_warn(bp->dev, "failed to update phy settings\n"); |
a1ef4a79 MC |
9498 | if (BNXT_SINGLE_PF(bp)) { |
9499 | bp->link_info.phy_retry = true; | |
9500 | bp->link_info.phy_retry_expires = | |
9501 | jiffies + 5 * HZ; | |
9502 | } | |
9503 | } | |
c0c050c5 MC |
9504 | } |
9505 | ||
7cdd5fc3 | 9506 | if (irq_re_init) |
442a35a5 | 9507 | udp_tunnel_nic_reset_ntf(bp->dev); |
c0c050c5 | 9508 | |
caefe526 | 9509 | set_bit(BNXT_STATE_OPEN, &bp->state); |
c0c050c5 MC |
9510 | bnxt_enable_int(bp); |
9511 | /* Enable TX queues */ | |
9512 | bnxt_tx_enable(bp); | |
9513 | mod_timer(&bp->timer, jiffies + bp->current_interval); | |
10289bec MC |
9514 | /* Poll link status and check for SFP+ module status */ |
9515 | bnxt_get_port_module_status(bp); | |
c0c050c5 | 9516 | |
ee5c7fb3 SP |
9517 | /* VF-reps may need to be re-opened after the PF is re-opened */ |
9518 | if (BNXT_PF(bp)) | |
9519 | bnxt_vf_reps_open(bp); | |
c0c050c5 MC |
9520 | return 0; |
9521 | ||
9522 | open_err: | |
cabfb09d | 9523 | bnxt_debug_dev_exit(bp); |
c0c050c5 | 9524 | bnxt_disable_napi(bp); |
c58387ab VG |
9525 | |
9526 | open_err_irq: | |
c0c050c5 MC |
9527 | bnxt_del_napi(bp); |
9528 | ||
9529 | open_err_free_mem: | |
9530 | bnxt_free_skbs(bp); | |
9531 | bnxt_free_irq(bp); | |
9532 | bnxt_free_mem(bp, true); | |
9533 | return rc; | |
9534 | } | |
9535 | ||
9536 | /* rtnl_lock held */ | |
9537 | int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) | |
9538 | { | |
9539 | int rc = 0; | |
9540 | ||
9541 | rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); | |
9542 | if (rc) { | |
9543 | netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); | |
9544 | dev_close(bp->dev); | |
9545 | } | |
9546 | return rc; | |
9547 | } | |
9548 | ||
f7dc1ea6 MC |
9549 | /* rtnl_lock held, open the NIC half way by allocating all resources, but |
9550 | * NAPI, IRQ, and TX are not enabled. This is mainly used for offline | |
9551 | * self tests. | |
9552 | */ | |
9553 | int bnxt_half_open_nic(struct bnxt *bp) | |
9554 | { | |
9555 | int rc = 0; | |
9556 | ||
9557 | rc = bnxt_alloc_mem(bp, false); | |
9558 | if (rc) { | |
9559 | netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); | |
9560 | goto half_open_err; | |
9561 | } | |
9562 | rc = bnxt_init_nic(bp, false); | |
9563 | if (rc) { | |
9564 | netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); | |
9565 | goto half_open_err; | |
9566 | } | |
9567 | return 0; | |
9568 | ||
9569 | half_open_err: | |
9570 | bnxt_free_skbs(bp); | |
9571 | bnxt_free_mem(bp, false); | |
9572 | dev_close(bp->dev); | |
9573 | return rc; | |
9574 | } | |
9575 | ||
9576 | /* rtnl_lock held, this call can only be made after a previous successful | |
9577 | * call to bnxt_half_open_nic(). | |
9578 | */ | |
9579 | void bnxt_half_close_nic(struct bnxt *bp) | |
9580 | { | |
9581 | bnxt_hwrm_resource_free(bp, false, false); | |
9582 | bnxt_free_skbs(bp); | |
9583 | bnxt_free_mem(bp, false); | |
9584 | } | |
9585 | ||
c16d4ee0 MC |
9586 | static void bnxt_reenable_sriov(struct bnxt *bp) |
9587 | { | |
9588 | if (BNXT_PF(bp)) { | |
9589 | struct bnxt_pf_info *pf = &bp->pf; | |
9590 | int n = pf->active_vfs; | |
9591 | ||
9592 | if (n) | |
9593 | bnxt_cfg_hw_sriov(bp, &n, true); | |
9594 | } | |
9595 | } | |
9596 | ||
c0c050c5 MC |
9597 | static int bnxt_open(struct net_device *dev) |
9598 | { | |
9599 | struct bnxt *bp = netdev_priv(dev); | |
25e1acd6 | 9600 | int rc; |
c0c050c5 | 9601 | |
ec5d31e3 MC |
9602 | if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) { |
9603 | netdev_err(bp->dev, "A previous firmware reset did not complete, aborting\n"); | |
9604 | return -ENODEV; | |
9605 | } | |
9606 | ||
9607 | rc = bnxt_hwrm_if_change(bp, true); | |
25e1acd6 | 9608 | if (rc) |
ec5d31e3 MC |
9609 | return rc; |
9610 | rc = __bnxt_open_nic(bp, true, true); | |
9611 | if (rc) { | |
25e1acd6 | 9612 | bnxt_hwrm_if_change(bp, false); |
ec5d31e3 | 9613 | } else { |
f3a6d206 | 9614 | if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) { |
12de2ead | 9615 | if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { |
f3a6d206 | 9616 | bnxt_ulp_start(bp, 0); |
12de2ead MC |
9617 | bnxt_reenable_sriov(bp); |
9618 | } | |
ec5d31e3 MC |
9619 | } |
9620 | bnxt_hwmon_open(bp); | |
9621 | } | |
cde49a42 | 9622 | |
25e1acd6 | 9623 | return rc; |
c0c050c5 MC |
9624 | } |
9625 | ||
f9b76ebd MC |
9626 | static bool bnxt_drv_busy(struct bnxt *bp) |
9627 | { | |
9628 | return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) || | |
9629 | test_bit(BNXT_STATE_READ_STATS, &bp->state)); | |
9630 | } | |
9631 | ||
b8875ca3 MC |
9632 | static void bnxt_get_ring_stats(struct bnxt *bp, |
9633 | struct rtnl_link_stats64 *stats); | |
9634 | ||
86e953db MC |
9635 | static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init, |
9636 | bool link_re_init) | |
c0c050c5 | 9637 | { |
ee5c7fb3 SP |
9638 | /* Close the VF-reps before closing PF */ |
9639 | if (BNXT_PF(bp)) | |
9640 | bnxt_vf_reps_close(bp); | |
86e953db | 9641 | |
c0c050c5 MC |
9642 | /* Change device state to avoid TX queue wake up's */ |
9643 | bnxt_tx_disable(bp); | |
9644 | ||
caefe526 | 9645 | clear_bit(BNXT_STATE_OPEN, &bp->state); |
4cebdcec | 9646 | smp_mb__after_atomic(); |
f9b76ebd | 9647 | while (bnxt_drv_busy(bp)) |
4cebdcec | 9648 | msleep(20); |
c0c050c5 | 9649 | |
9d8bc097 | 9650 | /* Flush rings and and disable interrupts */ |
c0c050c5 MC |
9651 | bnxt_shutdown_nic(bp, irq_re_init); |
9652 | ||
9653 | /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ | |
9654 | ||
cabfb09d | 9655 | bnxt_debug_dev_exit(bp); |
c0c050c5 | 9656 | bnxt_disable_napi(bp); |
c0c050c5 MC |
9657 | del_timer_sync(&bp->timer); |
9658 | bnxt_free_skbs(bp); | |
9659 | ||
b8875ca3 | 9660 | /* Save ring stats before shutdown */ |
b8056e84 | 9661 | if (bp->bnapi && irq_re_init) |
b8875ca3 | 9662 | bnxt_get_ring_stats(bp, &bp->net_stats_prev); |
c0c050c5 MC |
9663 | if (irq_re_init) { |
9664 | bnxt_free_irq(bp); | |
9665 | bnxt_del_napi(bp); | |
9666 | } | |
9667 | bnxt_free_mem(bp, irq_re_init); | |
86e953db MC |
9668 | } |
9669 | ||
9670 | int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) | |
9671 | { | |
9672 | int rc = 0; | |
9673 | ||
3bc7d4a3 MC |
9674 | if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { |
9675 | /* If we get here, it means firmware reset is in progress | |
9676 | * while we are trying to close. We can safely proceed with | |
9677 | * the close because we are holding rtnl_lock(). Some firmware | |
9678 | * messages may fail as we proceed to close. We set the | |
9679 | * ABORT_ERR flag here so that the FW reset thread will later | |
9680 | * abort when it gets the rtnl_lock() and sees the flag. | |
9681 | */ | |
9682 | netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n"); | |
9683 | set_bit(BNXT_STATE_ABORT_ERR, &bp->state); | |
9684 | } | |
9685 | ||
86e953db MC |
9686 | #ifdef CONFIG_BNXT_SRIOV |
9687 | if (bp->sriov_cfg) { | |
9688 | rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, | |
9689 | !bp->sriov_cfg, | |
9690 | BNXT_SRIOV_CFG_WAIT_TMO); | |
9691 | if (rc) | |
9692 | netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); | |
9693 | } | |
9694 | #endif | |
9695 | __bnxt_close_nic(bp, irq_re_init, link_re_init); | |
c0c050c5 MC |
9696 | return rc; |
9697 | } | |
9698 | ||
9699 | static int bnxt_close(struct net_device *dev) | |
9700 | { | |
9701 | struct bnxt *bp = netdev_priv(dev); | |
9702 | ||
cde49a42 | 9703 | bnxt_hwmon_close(bp); |
c0c050c5 | 9704 | bnxt_close_nic(bp, true, true); |
33f7d55f | 9705 | bnxt_hwrm_shutdown_link(bp); |
25e1acd6 | 9706 | bnxt_hwrm_if_change(bp, false); |
c0c050c5 MC |
9707 | return 0; |
9708 | } | |
9709 | ||
0ca12be9 VV |
9710 | static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg, |
9711 | u16 *val) | |
9712 | { | |
9713 | struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr; | |
9714 | struct hwrm_port_phy_mdio_read_input req = {0}; | |
9715 | int rc; | |
9716 | ||
9717 | if (bp->hwrm_spec_code < 0x10a00) | |
9718 | return -EOPNOTSUPP; | |
9719 | ||
9720 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1); | |
9721 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
9722 | req.phy_addr = phy_addr; | |
9723 | req.reg_addr = cpu_to_le16(reg & 0x1f); | |
2730214d | 9724 | if (mdio_phy_id_is_c45(phy_addr)) { |
0ca12be9 VV |
9725 | req.cl45_mdio = 1; |
9726 | req.phy_addr = mdio_phy_id_prtad(phy_addr); | |
9727 | req.dev_addr = mdio_phy_id_devad(phy_addr); | |
9728 | req.reg_addr = cpu_to_le16(reg); | |
9729 | } | |
9730 | ||
9731 | mutex_lock(&bp->hwrm_cmd_lock); | |
9732 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
9733 | if (!rc) | |
9734 | *val = le16_to_cpu(resp->reg_data); | |
9735 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9736 | return rc; | |
9737 | } | |
9738 | ||
9739 | static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg, | |
9740 | u16 val) | |
9741 | { | |
9742 | struct hwrm_port_phy_mdio_write_input req = {0}; | |
9743 | ||
9744 | if (bp->hwrm_spec_code < 0x10a00) | |
9745 | return -EOPNOTSUPP; | |
9746 | ||
9747 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1); | |
9748 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
9749 | req.phy_addr = phy_addr; | |
9750 | req.reg_addr = cpu_to_le16(reg & 0x1f); | |
2730214d | 9751 | if (mdio_phy_id_is_c45(phy_addr)) { |
0ca12be9 VV |
9752 | req.cl45_mdio = 1; |
9753 | req.phy_addr = mdio_phy_id_prtad(phy_addr); | |
9754 | req.dev_addr = mdio_phy_id_devad(phy_addr); | |
9755 | req.reg_addr = cpu_to_le16(reg); | |
9756 | } | |
9757 | req.reg_data = cpu_to_le16(val); | |
9758 | ||
9759 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
9760 | } | |
9761 | ||
c0c050c5 MC |
9762 | /* rtnl_lock held */ |
9763 | static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
9764 | { | |
0ca12be9 VV |
9765 | struct mii_ioctl_data *mdio = if_mii(ifr); |
9766 | struct bnxt *bp = netdev_priv(dev); | |
9767 | int rc; | |
9768 | ||
c0c050c5 MC |
9769 | switch (cmd) { |
9770 | case SIOCGMIIPHY: | |
0ca12be9 VV |
9771 | mdio->phy_id = bp->link_info.phy_addr; |
9772 | ||
c0c050c5 MC |
9773 | /* fallthru */ |
9774 | case SIOCGMIIREG: { | |
0ca12be9 VV |
9775 | u16 mii_regval = 0; |
9776 | ||
c0c050c5 MC |
9777 | if (!netif_running(dev)) |
9778 | return -EAGAIN; | |
9779 | ||
0ca12be9 VV |
9780 | rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num, |
9781 | &mii_regval); | |
9782 | mdio->val_out = mii_regval; | |
9783 | return rc; | |
c0c050c5 MC |
9784 | } |
9785 | ||
9786 | case SIOCSMIIREG: | |
9787 | if (!netif_running(dev)) | |
9788 | return -EAGAIN; | |
9789 | ||
0ca12be9 VV |
9790 | return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num, |
9791 | mdio->val_in); | |
c0c050c5 MC |
9792 | |
9793 | default: | |
9794 | /* do nothing */ | |
9795 | break; | |
9796 | } | |
9797 | return -EOPNOTSUPP; | |
9798 | } | |
9799 | ||
b8875ca3 MC |
9800 | static void bnxt_get_ring_stats(struct bnxt *bp, |
9801 | struct rtnl_link_stats64 *stats) | |
c0c050c5 | 9802 | { |
b8875ca3 | 9803 | int i; |
c0c050c5 | 9804 | |
c0c050c5 MC |
9805 | for (i = 0; i < bp->cp_nr_rings; i++) { |
9806 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
9807 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
a0c30621 | 9808 | u64 *sw = cpr->stats.sw_stats; |
c0c050c5 | 9809 | |
a0c30621 MC |
9810 | stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_ucast_pkts); |
9811 | stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts); | |
9812 | stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_bcast_pkts); | |
c0c050c5 | 9813 | |
a0c30621 MC |
9814 | stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_ucast_pkts); |
9815 | stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_mcast_pkts); | |
9816 | stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_bcast_pkts); | |
c0c050c5 | 9817 | |
a0c30621 MC |
9818 | stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_ucast_bytes); |
9819 | stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_mcast_bytes); | |
9820 | stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_bcast_bytes); | |
c0c050c5 | 9821 | |
a0c30621 MC |
9822 | stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_ucast_bytes); |
9823 | stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_mcast_bytes); | |
9824 | stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_bcast_bytes); | |
c0c050c5 MC |
9825 | |
9826 | stats->rx_missed_errors += | |
a0c30621 | 9827 | BNXT_GET_RING_STATS64(sw, rx_discard_pkts); |
c0c050c5 | 9828 | |
a0c30621 | 9829 | stats->multicast += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts); |
c0c050c5 | 9830 | |
a0c30621 | 9831 | stats->tx_dropped += BNXT_GET_RING_STATS64(sw, tx_error_pkts); |
c0c050c5 | 9832 | } |
b8875ca3 MC |
9833 | } |
9834 | ||
9835 | static void bnxt_add_prev_stats(struct bnxt *bp, | |
9836 | struct rtnl_link_stats64 *stats) | |
9837 | { | |
9838 | struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev; | |
9839 | ||
9840 | stats->rx_packets += prev_stats->rx_packets; | |
9841 | stats->tx_packets += prev_stats->tx_packets; | |
9842 | stats->rx_bytes += prev_stats->rx_bytes; | |
9843 | stats->tx_bytes += prev_stats->tx_bytes; | |
9844 | stats->rx_missed_errors += prev_stats->rx_missed_errors; | |
9845 | stats->multicast += prev_stats->multicast; | |
9846 | stats->tx_dropped += prev_stats->tx_dropped; | |
9847 | } | |
9848 | ||
9849 | static void | |
9850 | bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) | |
9851 | { | |
9852 | struct bnxt *bp = netdev_priv(dev); | |
9853 | ||
9854 | set_bit(BNXT_STATE_READ_STATS, &bp->state); | |
9855 | /* Make sure bnxt_close_nic() sees that we are reading stats before | |
9856 | * we check the BNXT_STATE_OPEN flag. | |
9857 | */ | |
9858 | smp_mb__after_atomic(); | |
9859 | if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { | |
9860 | clear_bit(BNXT_STATE_READ_STATS, &bp->state); | |
9861 | *stats = bp->net_stats_prev; | |
9862 | return; | |
9863 | } | |
9864 | ||
9865 | bnxt_get_ring_stats(bp, stats); | |
9866 | bnxt_add_prev_stats(bp, stats); | |
c0c050c5 | 9867 | |
9947f83f | 9868 | if (bp->flags & BNXT_FLAG_PORT_STATS) { |
a0c30621 MC |
9869 | u64 *rx = bp->port_stats.sw_stats; |
9870 | u64 *tx = bp->port_stats.sw_stats + | |
9871 | BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; | |
9872 | ||
9873 | stats->rx_crc_errors = | |
9874 | BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); | |
9875 | stats->rx_frame_errors = | |
9876 | BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); | |
9877 | stats->rx_length_errors = | |
9878 | BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames) + | |
9879 | BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames) + | |
9880 | BNXT_GET_RX_PORT_STATS64(rx, rx_runt_frames); | |
9881 | stats->rx_errors = | |
9882 | BNXT_GET_RX_PORT_STATS64(rx, rx_false_carrier_frames) + | |
9883 | BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); | |
9884 | stats->collisions = | |
9885 | BNXT_GET_TX_PORT_STATS64(tx, tx_total_collisions); | |
9886 | stats->tx_fifo_errors = | |
9887 | BNXT_GET_TX_PORT_STATS64(tx, tx_fifo_underruns); | |
9888 | stats->tx_errors = BNXT_GET_TX_PORT_STATS64(tx, tx_err); | |
9947f83f | 9889 | } |
f9b76ebd | 9890 | clear_bit(BNXT_STATE_READ_STATS, &bp->state); |
c0c050c5 MC |
9891 | } |
9892 | ||
9893 | static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) | |
9894 | { | |
9895 | struct net_device *dev = bp->dev; | |
9896 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; | |
9897 | struct netdev_hw_addr *ha; | |
9898 | u8 *haddr; | |
9899 | int mc_count = 0; | |
9900 | bool update = false; | |
9901 | int off = 0; | |
9902 | ||
9903 | netdev_for_each_mc_addr(ha, dev) { | |
9904 | if (mc_count >= BNXT_MAX_MC_ADDRS) { | |
9905 | *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; | |
9906 | vnic->mc_list_count = 0; | |
9907 | return false; | |
9908 | } | |
9909 | haddr = ha->addr; | |
9910 | if (!ether_addr_equal(haddr, vnic->mc_list + off)) { | |
9911 | memcpy(vnic->mc_list + off, haddr, ETH_ALEN); | |
9912 | update = true; | |
9913 | } | |
9914 | off += ETH_ALEN; | |
9915 | mc_count++; | |
9916 | } | |
9917 | if (mc_count) | |
9918 | *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; | |
9919 | ||
9920 | if (mc_count != vnic->mc_list_count) { | |
9921 | vnic->mc_list_count = mc_count; | |
9922 | update = true; | |
9923 | } | |
9924 | return update; | |
9925 | } | |
9926 | ||
9927 | static bool bnxt_uc_list_updated(struct bnxt *bp) | |
9928 | { | |
9929 | struct net_device *dev = bp->dev; | |
9930 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; | |
9931 | struct netdev_hw_addr *ha; | |
9932 | int off = 0; | |
9933 | ||
9934 | if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) | |
9935 | return true; | |
9936 | ||
9937 | netdev_for_each_uc_addr(ha, dev) { | |
9938 | if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) | |
9939 | return true; | |
9940 | ||
9941 | off += ETH_ALEN; | |
9942 | } | |
9943 | return false; | |
9944 | } | |
9945 | ||
9946 | static void bnxt_set_rx_mode(struct net_device *dev) | |
9947 | { | |
9948 | struct bnxt *bp = netdev_priv(dev); | |
268d0895 | 9949 | struct bnxt_vnic_info *vnic; |
c0c050c5 MC |
9950 | bool mc_update = false; |
9951 | bool uc_update; | |
268d0895 | 9952 | u32 mask; |
c0c050c5 | 9953 | |
268d0895 | 9954 | if (!test_bit(BNXT_STATE_OPEN, &bp->state)) |
c0c050c5 MC |
9955 | return; |
9956 | ||
268d0895 MC |
9957 | vnic = &bp->vnic_info[0]; |
9958 | mask = vnic->rx_mask; | |
c0c050c5 MC |
9959 | mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | |
9960 | CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | | |
30e33848 MC |
9961 | CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST | |
9962 | CFA_L2_SET_RX_MASK_REQ_MASK_BCAST); | |
c0c050c5 | 9963 | |
17c71ac3 | 9964 | if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) |
c0c050c5 MC |
9965 | mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; |
9966 | ||
9967 | uc_update = bnxt_uc_list_updated(bp); | |
9968 | ||
30e33848 MC |
9969 | if (dev->flags & IFF_BROADCAST) |
9970 | mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; | |
c0c050c5 MC |
9971 | if (dev->flags & IFF_ALLMULTI) { |
9972 | mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; | |
9973 | vnic->mc_list_count = 0; | |
9974 | } else { | |
9975 | mc_update = bnxt_mc_list_updated(bp, &mask); | |
9976 | } | |
9977 | ||
9978 | if (mask != vnic->rx_mask || uc_update || mc_update) { | |
9979 | vnic->rx_mask = mask; | |
9980 | ||
9981 | set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); | |
c213eae8 | 9982 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
9983 | } |
9984 | } | |
9985 | ||
b664f008 | 9986 | static int bnxt_cfg_rx_mode(struct bnxt *bp) |
c0c050c5 MC |
9987 | { |
9988 | struct net_device *dev = bp->dev; | |
9989 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; | |
9990 | struct netdev_hw_addr *ha; | |
9991 | int i, off = 0, rc; | |
9992 | bool uc_update; | |
9993 | ||
9994 | netif_addr_lock_bh(dev); | |
9995 | uc_update = bnxt_uc_list_updated(bp); | |
9996 | netif_addr_unlock_bh(dev); | |
9997 | ||
9998 | if (!uc_update) | |
9999 | goto skip_uc; | |
10000 | ||
10001 | mutex_lock(&bp->hwrm_cmd_lock); | |
10002 | for (i = 1; i < vnic->uc_filter_count; i++) { | |
10003 | struct hwrm_cfa_l2_filter_free_input req = {0}; | |
10004 | ||
10005 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1, | |
10006 | -1); | |
10007 | ||
10008 | req.l2_filter_id = vnic->fw_l2_filter_id[i]; | |
10009 | ||
10010 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
10011 | HWRM_CMD_TIMEOUT); | |
10012 | } | |
10013 | mutex_unlock(&bp->hwrm_cmd_lock); | |
10014 | ||
10015 | vnic->uc_filter_count = 1; | |
10016 | ||
10017 | netif_addr_lock_bh(dev); | |
10018 | if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { | |
10019 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; | |
10020 | } else { | |
10021 | netdev_for_each_uc_addr(ha, dev) { | |
10022 | memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); | |
10023 | off += ETH_ALEN; | |
10024 | vnic->uc_filter_count++; | |
10025 | } | |
10026 | } | |
10027 | netif_addr_unlock_bh(dev); | |
10028 | ||
10029 | for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { | |
10030 | rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); | |
10031 | if (rc) { | |
10032 | netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", | |
10033 | rc); | |
10034 | vnic->uc_filter_count = i; | |
b664f008 | 10035 | return rc; |
c0c050c5 MC |
10036 | } |
10037 | } | |
10038 | ||
10039 | skip_uc: | |
10040 | rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); | |
b4e30e8e MC |
10041 | if (rc && vnic->mc_list_count) { |
10042 | netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n", | |
10043 | rc); | |
10044 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; | |
10045 | vnic->mc_list_count = 0; | |
10046 | rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); | |
10047 | } | |
c0c050c5 | 10048 | if (rc) |
b4e30e8e | 10049 | netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n", |
c0c050c5 | 10050 | rc); |
b664f008 MC |
10051 | |
10052 | return rc; | |
c0c050c5 MC |
10053 | } |
10054 | ||
2773dfb2 MC |
10055 | static bool bnxt_can_reserve_rings(struct bnxt *bp) |
10056 | { | |
10057 | #ifdef CONFIG_BNXT_SRIOV | |
f1ca94de | 10058 | if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) { |
2773dfb2 MC |
10059 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; |
10060 | ||
10061 | /* No minimum rings were provisioned by the PF. Don't | |
10062 | * reserve rings by default when device is down. | |
10063 | */ | |
10064 | if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings) | |
10065 | return true; | |
10066 | ||
10067 | if (!netif_running(bp->dev)) | |
10068 | return false; | |
10069 | } | |
10070 | #endif | |
10071 | return true; | |
10072 | } | |
10073 | ||
8079e8f1 MC |
10074 | /* If the chip and firmware supports RFS */ |
10075 | static bool bnxt_rfs_supported(struct bnxt *bp) | |
10076 | { | |
e969ae5b | 10077 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
41136ab3 | 10078 | if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) |
e969ae5b | 10079 | return true; |
41e8d798 | 10080 | return false; |
e969ae5b | 10081 | } |
8079e8f1 MC |
10082 | if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) |
10083 | return true; | |
ae10ae74 MC |
10084 | if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) |
10085 | return true; | |
8079e8f1 MC |
10086 | return false; |
10087 | } | |
10088 | ||
10089 | /* If runtime conditions support RFS */ | |
2bcfa6f6 MC |
10090 | static bool bnxt_rfs_capable(struct bnxt *bp) |
10091 | { | |
10092 | #ifdef CONFIG_RFS_ACCEL | |
8079e8f1 | 10093 | int vnics, max_vnics, max_rss_ctxs; |
2bcfa6f6 | 10094 | |
41e8d798 | 10095 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
ac33906c | 10096 | return bnxt_rfs_supported(bp); |
2773dfb2 | 10097 | if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp)) |
2bcfa6f6 MC |
10098 | return false; |
10099 | ||
10100 | vnics = 1 + bp->rx_nr_rings; | |
8079e8f1 MC |
10101 | max_vnics = bnxt_get_max_func_vnics(bp); |
10102 | max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp); | |
ae10ae74 MC |
10103 | |
10104 | /* RSS contexts not a limiting factor */ | |
10105 | if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) | |
10106 | max_rss_ctxs = max_vnics; | |
8079e8f1 | 10107 | if (vnics > max_vnics || vnics > max_rss_ctxs) { |
6a1eef5b MC |
10108 | if (bp->rx_nr_rings > 1) |
10109 | netdev_warn(bp->dev, | |
10110 | "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n", | |
10111 | min(max_rss_ctxs - 1, max_vnics - 1)); | |
2bcfa6f6 | 10112 | return false; |
a2304909 | 10113 | } |
2bcfa6f6 | 10114 | |
f1ca94de | 10115 | if (!BNXT_NEW_RM(bp)) |
6a1eef5b MC |
10116 | return true; |
10117 | ||
10118 | if (vnics == bp->hw_resc.resv_vnics) | |
10119 | return true; | |
10120 | ||
780baad4 | 10121 | bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics); |
6a1eef5b MC |
10122 | if (vnics <= bp->hw_resc.resv_vnics) |
10123 | return true; | |
10124 | ||
10125 | netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n"); | |
780baad4 | 10126 | bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1); |
6a1eef5b | 10127 | return false; |
2bcfa6f6 MC |
10128 | #else |
10129 | return false; | |
10130 | #endif | |
10131 | } | |
10132 | ||
c0c050c5 MC |
10133 | static netdev_features_t bnxt_fix_features(struct net_device *dev, |
10134 | netdev_features_t features) | |
10135 | { | |
2bcfa6f6 | 10136 | struct bnxt *bp = netdev_priv(dev); |
c72cb303 | 10137 | netdev_features_t vlan_features; |
2bcfa6f6 | 10138 | |
a2304909 | 10139 | if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp)) |
2bcfa6f6 | 10140 | features &= ~NETIF_F_NTUPLE; |
5a9f6b23 | 10141 | |
1054aee8 MC |
10142 | if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) |
10143 | features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); | |
10144 | ||
10145 | if (!(features & NETIF_F_GRO)) | |
10146 | features &= ~NETIF_F_GRO_HW; | |
10147 | ||
10148 | if (features & NETIF_F_GRO_HW) | |
10149 | features &= ~NETIF_F_LRO; | |
10150 | ||
5a9f6b23 MC |
10151 | /* Both CTAG and STAG VLAN accelaration on the RX side have to be |
10152 | * turned on or off together. | |
10153 | */ | |
a196e96b EP |
10154 | vlan_features = features & BNXT_HW_FEATURE_VLAN_ALL_RX; |
10155 | if (vlan_features != BNXT_HW_FEATURE_VLAN_ALL_RX) { | |
10156 | if (dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX) | |
10157 | features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX; | |
c72cb303 | 10158 | else if (vlan_features) |
a196e96b | 10159 | features |= BNXT_HW_FEATURE_VLAN_ALL_RX; |
5a9f6b23 | 10160 | } |
cf6645f8 | 10161 | #ifdef CONFIG_BNXT_SRIOV |
a196e96b EP |
10162 | if (BNXT_VF(bp) && bp->vf.vlan) |
10163 | features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX; | |
cf6645f8 | 10164 | #endif |
c0c050c5 MC |
10165 | return features; |
10166 | } | |
10167 | ||
10168 | static int bnxt_set_features(struct net_device *dev, netdev_features_t features) | |
10169 | { | |
10170 | struct bnxt *bp = netdev_priv(dev); | |
10171 | u32 flags = bp->flags; | |
10172 | u32 changes; | |
10173 | int rc = 0; | |
10174 | bool re_init = false; | |
10175 | bool update_tpa = false; | |
10176 | ||
10177 | flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; | |
1054aee8 | 10178 | if (features & NETIF_F_GRO_HW) |
c0c050c5 | 10179 | flags |= BNXT_FLAG_GRO; |
1054aee8 | 10180 | else if (features & NETIF_F_LRO) |
c0c050c5 MC |
10181 | flags |= BNXT_FLAG_LRO; |
10182 | ||
bdbd1eb5 MC |
10183 | if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) |
10184 | flags &= ~BNXT_FLAG_TPA; | |
10185 | ||
a196e96b | 10186 | if (features & BNXT_HW_FEATURE_VLAN_ALL_RX) |
c0c050c5 MC |
10187 | flags |= BNXT_FLAG_STRIP_VLAN; |
10188 | ||
10189 | if (features & NETIF_F_NTUPLE) | |
10190 | flags |= BNXT_FLAG_RFS; | |
10191 | ||
10192 | changes = flags ^ bp->flags; | |
10193 | if (changes & BNXT_FLAG_TPA) { | |
10194 | update_tpa = true; | |
10195 | if ((bp->flags & BNXT_FLAG_TPA) == 0 || | |
f45b7b78 MC |
10196 | (flags & BNXT_FLAG_TPA) == 0 || |
10197 | (bp->flags & BNXT_FLAG_CHIP_P5)) | |
c0c050c5 MC |
10198 | re_init = true; |
10199 | } | |
10200 | ||
10201 | if (changes & ~BNXT_FLAG_TPA) | |
10202 | re_init = true; | |
10203 | ||
10204 | if (flags != bp->flags) { | |
10205 | u32 old_flags = bp->flags; | |
10206 | ||
2bcfa6f6 | 10207 | if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { |
f45b7b78 | 10208 | bp->flags = flags; |
c0c050c5 MC |
10209 | if (update_tpa) |
10210 | bnxt_set_ring_params(bp); | |
10211 | return rc; | |
10212 | } | |
10213 | ||
10214 | if (re_init) { | |
10215 | bnxt_close_nic(bp, false, false); | |
f45b7b78 | 10216 | bp->flags = flags; |
c0c050c5 MC |
10217 | if (update_tpa) |
10218 | bnxt_set_ring_params(bp); | |
10219 | ||
10220 | return bnxt_open_nic(bp, false, false); | |
10221 | } | |
10222 | if (update_tpa) { | |
f45b7b78 | 10223 | bp->flags = flags; |
c0c050c5 MC |
10224 | rc = bnxt_set_tpa(bp, |
10225 | (flags & BNXT_FLAG_TPA) ? | |
10226 | true : false); | |
10227 | if (rc) | |
10228 | bp->flags = old_flags; | |
10229 | } | |
10230 | } | |
10231 | return rc; | |
10232 | } | |
10233 | ||
b5d600b0 VV |
10234 | int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words, |
10235 | u32 *reg_buf) | |
10236 | { | |
10237 | struct hwrm_dbg_read_direct_output *resp = bp->hwrm_cmd_resp_addr; | |
10238 | struct hwrm_dbg_read_direct_input req = {0}; | |
10239 | __le32 *dbg_reg_buf; | |
10240 | dma_addr_t mapping; | |
10241 | int rc, i; | |
10242 | ||
10243 | dbg_reg_buf = dma_alloc_coherent(&bp->pdev->dev, num_words * 4, | |
10244 | &mapping, GFP_KERNEL); | |
10245 | if (!dbg_reg_buf) | |
10246 | return -ENOMEM; | |
10247 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_READ_DIRECT, -1, -1); | |
10248 | req.host_dest_addr = cpu_to_le64(mapping); | |
10249 | req.read_addr = cpu_to_le32(reg_off + CHIMP_REG_VIEW_ADDR); | |
10250 | req.read_len32 = cpu_to_le32(num_words); | |
10251 | mutex_lock(&bp->hwrm_cmd_lock); | |
10252 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
10253 | if (rc || resp->error_code) { | |
10254 | rc = -EIO; | |
10255 | goto dbg_rd_reg_exit; | |
10256 | } | |
10257 | for (i = 0; i < num_words; i++) | |
10258 | reg_buf[i] = le32_to_cpu(dbg_reg_buf[i]); | |
10259 | ||
10260 | dbg_rd_reg_exit: | |
10261 | mutex_unlock(&bp->hwrm_cmd_lock); | |
10262 | dma_free_coherent(&bp->pdev->dev, num_words * 4, dbg_reg_buf, mapping); | |
10263 | return rc; | |
10264 | } | |
10265 | ||
ffd77621 MC |
10266 | static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type, |
10267 | u32 ring_id, u32 *prod, u32 *cons) | |
10268 | { | |
10269 | struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr; | |
10270 | struct hwrm_dbg_ring_info_get_input req = {0}; | |
10271 | int rc; | |
10272 | ||
10273 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1); | |
10274 | req.ring_type = ring_type; | |
10275 | req.fw_ring_id = cpu_to_le32(ring_id); | |
10276 | mutex_lock(&bp->hwrm_cmd_lock); | |
10277 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
10278 | if (!rc) { | |
10279 | *prod = le32_to_cpu(resp->producer_index); | |
10280 | *cons = le32_to_cpu(resp->consumer_index); | |
10281 | } | |
10282 | mutex_unlock(&bp->hwrm_cmd_lock); | |
10283 | return rc; | |
10284 | } | |
10285 | ||
9f554590 MC |
10286 | static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) |
10287 | { | |
b6ab4b01 | 10288 | struct bnxt_tx_ring_info *txr = bnapi->tx_ring; |
9f554590 MC |
10289 | int i = bnapi->index; |
10290 | ||
3b2b7d9d MC |
10291 | if (!txr) |
10292 | return; | |
10293 | ||
9f554590 MC |
10294 | netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", |
10295 | i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, | |
10296 | txr->tx_cons); | |
10297 | } | |
10298 | ||
10299 | static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) | |
10300 | { | |
b6ab4b01 | 10301 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
9f554590 MC |
10302 | int i = bnapi->index; |
10303 | ||
3b2b7d9d MC |
10304 | if (!rxr) |
10305 | return; | |
10306 | ||
9f554590 MC |
10307 | netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", |
10308 | i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, | |
10309 | rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, | |
10310 | rxr->rx_sw_agg_prod); | |
10311 | } | |
10312 | ||
10313 | static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) | |
10314 | { | |
10315 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
10316 | int i = bnapi->index; | |
10317 | ||
10318 | netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", | |
10319 | i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); | |
10320 | } | |
10321 | ||
c0c050c5 MC |
10322 | static void bnxt_dbg_dump_states(struct bnxt *bp) |
10323 | { | |
10324 | int i; | |
10325 | struct bnxt_napi *bnapi; | |
c0c050c5 MC |
10326 | |
10327 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
10328 | bnapi = bp->bnapi[i]; | |
c0c050c5 | 10329 | if (netif_msg_drv(bp)) { |
9f554590 MC |
10330 | bnxt_dump_tx_sw_state(bnapi); |
10331 | bnxt_dump_rx_sw_state(bnapi); | |
10332 | bnxt_dump_cp_sw_state(bnapi); | |
c0c050c5 MC |
10333 | } |
10334 | } | |
10335 | } | |
10336 | ||
6988bd92 | 10337 | static void bnxt_reset_task(struct bnxt *bp, bool silent) |
c0c050c5 | 10338 | { |
6988bd92 MC |
10339 | if (!silent) |
10340 | bnxt_dbg_dump_states(bp); | |
028de140 | 10341 | if (netif_running(bp->dev)) { |
b386cd36 MC |
10342 | int rc; |
10343 | ||
aa46dfff VV |
10344 | if (silent) { |
10345 | bnxt_close_nic(bp, false, false); | |
10346 | bnxt_open_nic(bp, false, false); | |
10347 | } else { | |
b386cd36 | 10348 | bnxt_ulp_stop(bp); |
aa46dfff VV |
10349 | bnxt_close_nic(bp, true, false); |
10350 | rc = bnxt_open_nic(bp, true, false); | |
10351 | bnxt_ulp_start(bp, rc); | |
10352 | } | |
028de140 | 10353 | } |
c0c050c5 MC |
10354 | } |
10355 | ||
0290bd29 | 10356 | static void bnxt_tx_timeout(struct net_device *dev, unsigned int txqueue) |
c0c050c5 MC |
10357 | { |
10358 | struct bnxt *bp = netdev_priv(dev); | |
10359 | ||
10360 | netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); | |
10361 | set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); | |
c213eae8 | 10362 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
10363 | } |
10364 | ||
acfb50e4 VV |
10365 | static void bnxt_fw_health_check(struct bnxt *bp) |
10366 | { | |
10367 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
10368 | u32 val; | |
10369 | ||
0797c10d | 10370 | if (!fw_health->enabled || test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) |
acfb50e4 VV |
10371 | return; |
10372 | ||
10373 | if (fw_health->tmr_counter) { | |
10374 | fw_health->tmr_counter--; | |
10375 | return; | |
10376 | } | |
10377 | ||
10378 | val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); | |
10379 | if (val == fw_health->last_fw_heartbeat) | |
10380 | goto fw_reset; | |
10381 | ||
10382 | fw_health->last_fw_heartbeat = val; | |
10383 | ||
10384 | val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); | |
10385 | if (val != fw_health->last_fw_reset_cnt) | |
10386 | goto fw_reset; | |
10387 | ||
10388 | fw_health->tmr_counter = fw_health->tmr_multiplier; | |
10389 | return; | |
10390 | ||
10391 | fw_reset: | |
10392 | set_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event); | |
10393 | bnxt_queue_sp_work(bp); | |
10394 | } | |
10395 | ||
e99e88a9 | 10396 | static void bnxt_timer(struct timer_list *t) |
c0c050c5 | 10397 | { |
e99e88a9 | 10398 | struct bnxt *bp = from_timer(bp, t, timer); |
c0c050c5 MC |
10399 | struct net_device *dev = bp->dev; |
10400 | ||
e0009404 | 10401 | if (!netif_running(dev) || !test_bit(BNXT_STATE_OPEN, &bp->state)) |
c0c050c5 MC |
10402 | return; |
10403 | ||
10404 | if (atomic_read(&bp->intr_sem) != 0) | |
10405 | goto bnxt_restart_timer; | |
10406 | ||
acfb50e4 VV |
10407 | if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) |
10408 | bnxt_fw_health_check(bp); | |
10409 | ||
fea6b333 | 10410 | if (bp->link_info.link_up && bp->stats_coal_ticks) { |
3bdf56c4 | 10411 | set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event); |
c213eae8 | 10412 | bnxt_queue_sp_work(bp); |
3bdf56c4 | 10413 | } |
5a84acbe SP |
10414 | |
10415 | if (bnxt_tc_flower_enabled(bp)) { | |
10416 | set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event); | |
10417 | bnxt_queue_sp_work(bp); | |
10418 | } | |
a1ef4a79 | 10419 | |
87d67f59 PC |
10420 | #ifdef CONFIG_RFS_ACCEL |
10421 | if ((bp->flags & BNXT_FLAG_RFS) && bp->ntp_fltr_count) { | |
10422 | set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); | |
10423 | bnxt_queue_sp_work(bp); | |
10424 | } | |
10425 | #endif /*CONFIG_RFS_ACCEL*/ | |
10426 | ||
a1ef4a79 MC |
10427 | if (bp->link_info.phy_retry) { |
10428 | if (time_after(jiffies, bp->link_info.phy_retry_expires)) { | |
acda6180 | 10429 | bp->link_info.phy_retry = false; |
a1ef4a79 MC |
10430 | netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n"); |
10431 | } else { | |
10432 | set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event); | |
10433 | bnxt_queue_sp_work(bp); | |
10434 | } | |
10435 | } | |
ffd77621 | 10436 | |
5313845f MC |
10437 | if ((bp->flags & BNXT_FLAG_CHIP_P5) && !bp->chip_rev && |
10438 | netif_carrier_ok(dev)) { | |
ffd77621 MC |
10439 | set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event); |
10440 | bnxt_queue_sp_work(bp); | |
10441 | } | |
c0c050c5 MC |
10442 | bnxt_restart_timer: |
10443 | mod_timer(&bp->timer, jiffies + bp->current_interval); | |
10444 | } | |
10445 | ||
a551ee94 | 10446 | static void bnxt_rtnl_lock_sp(struct bnxt *bp) |
6988bd92 | 10447 | { |
a551ee94 MC |
10448 | /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK |
10449 | * set. If the device is being closed, bnxt_close() may be holding | |
6988bd92 MC |
10450 | * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we |
10451 | * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). | |
10452 | */ | |
10453 | clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); | |
10454 | rtnl_lock(); | |
a551ee94 MC |
10455 | } |
10456 | ||
10457 | static void bnxt_rtnl_unlock_sp(struct bnxt *bp) | |
10458 | { | |
6988bd92 MC |
10459 | set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); |
10460 | rtnl_unlock(); | |
10461 | } | |
10462 | ||
a551ee94 MC |
10463 | /* Only called from bnxt_sp_task() */ |
10464 | static void bnxt_reset(struct bnxt *bp, bool silent) | |
10465 | { | |
10466 | bnxt_rtnl_lock_sp(bp); | |
10467 | if (test_bit(BNXT_STATE_OPEN, &bp->state)) | |
10468 | bnxt_reset_task(bp, silent); | |
10469 | bnxt_rtnl_unlock_sp(bp); | |
10470 | } | |
10471 | ||
230d1f0d MC |
10472 | static void bnxt_fw_reset_close(struct bnxt *bp) |
10473 | { | |
f3a6d206 | 10474 | bnxt_ulp_stop(bp); |
d4073028 VV |
10475 | /* When firmware is fatal state, disable PCI device to prevent |
10476 | * any potential bad DMAs before freeing kernel memory. | |
10477 | */ | |
10478 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) | |
10479 | pci_disable_device(bp->pdev); | |
230d1f0d | 10480 | __bnxt_close_nic(bp, true, false); |
230d1f0d MC |
10481 | bnxt_clear_int_mode(bp); |
10482 | bnxt_hwrm_func_drv_unrgtr(bp); | |
d4073028 VV |
10483 | if (pci_is_enabled(bp->pdev)) |
10484 | pci_disable_device(bp->pdev); | |
230d1f0d MC |
10485 | bnxt_free_ctx_mem(bp); |
10486 | kfree(bp->ctx); | |
10487 | bp->ctx = NULL; | |
10488 | } | |
10489 | ||
acfb50e4 VV |
10490 | static bool is_bnxt_fw_ok(struct bnxt *bp) |
10491 | { | |
10492 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
10493 | bool no_heartbeat = false, has_reset = false; | |
10494 | u32 val; | |
10495 | ||
10496 | val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); | |
10497 | if (val == fw_health->last_fw_heartbeat) | |
10498 | no_heartbeat = true; | |
10499 | ||
10500 | val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); | |
10501 | if (val != fw_health->last_fw_reset_cnt) | |
10502 | has_reset = true; | |
10503 | ||
10504 | if (!no_heartbeat && has_reset) | |
10505 | return true; | |
10506 | ||
10507 | return false; | |
10508 | } | |
10509 | ||
d1db9e16 MC |
10510 | /* rtnl_lock is acquired before calling this function */ |
10511 | static void bnxt_force_fw_reset(struct bnxt *bp) | |
10512 | { | |
10513 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
10514 | u32 wait_dsecs; | |
10515 | ||
10516 | if (!test_bit(BNXT_STATE_OPEN, &bp->state) || | |
10517 | test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) | |
10518 | return; | |
10519 | ||
10520 | set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
10521 | bnxt_fw_reset_close(bp); | |
10522 | wait_dsecs = fw_health->master_func_wait_dsecs; | |
10523 | if (fw_health->master) { | |
10524 | if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) | |
10525 | wait_dsecs = 0; | |
10526 | bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; | |
10527 | } else { | |
10528 | bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10; | |
10529 | wait_dsecs = fw_health->normal_func_wait_dsecs; | |
10530 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
10531 | } | |
4037eb71 VV |
10532 | |
10533 | bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs; | |
d1db9e16 MC |
10534 | bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs; |
10535 | bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); | |
10536 | } | |
10537 | ||
10538 | void bnxt_fw_exception(struct bnxt *bp) | |
10539 | { | |
a2b31e27 | 10540 | netdev_warn(bp->dev, "Detected firmware fatal condition, initiating reset\n"); |
d1db9e16 MC |
10541 | set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); |
10542 | bnxt_rtnl_lock_sp(bp); | |
10543 | bnxt_force_fw_reset(bp); | |
10544 | bnxt_rtnl_unlock_sp(bp); | |
10545 | } | |
10546 | ||
e72cb7d6 MC |
10547 | /* Returns the number of registered VFs, or 1 if VF configuration is pending, or |
10548 | * < 0 on error. | |
10549 | */ | |
10550 | static int bnxt_get_registered_vfs(struct bnxt *bp) | |
230d1f0d | 10551 | { |
e72cb7d6 | 10552 | #ifdef CONFIG_BNXT_SRIOV |
230d1f0d MC |
10553 | int rc; |
10554 | ||
e72cb7d6 MC |
10555 | if (!BNXT_PF(bp)) |
10556 | return 0; | |
10557 | ||
10558 | rc = bnxt_hwrm_func_qcfg(bp); | |
10559 | if (rc) { | |
10560 | netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc); | |
10561 | return rc; | |
10562 | } | |
10563 | if (bp->pf.registered_vfs) | |
10564 | return bp->pf.registered_vfs; | |
10565 | if (bp->sriov_cfg) | |
10566 | return 1; | |
10567 | #endif | |
10568 | return 0; | |
10569 | } | |
10570 | ||
10571 | void bnxt_fw_reset(struct bnxt *bp) | |
10572 | { | |
230d1f0d MC |
10573 | bnxt_rtnl_lock_sp(bp); |
10574 | if (test_bit(BNXT_STATE_OPEN, &bp->state) && | |
10575 | !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { | |
4037eb71 | 10576 | int n = 0, tmo; |
e72cb7d6 | 10577 | |
230d1f0d | 10578 | set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); |
e72cb7d6 MC |
10579 | if (bp->pf.active_vfs && |
10580 | !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) | |
10581 | n = bnxt_get_registered_vfs(bp); | |
10582 | if (n < 0) { | |
10583 | netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n", | |
10584 | n); | |
10585 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
10586 | dev_close(bp->dev); | |
10587 | goto fw_reset_exit; | |
10588 | } else if (n > 0) { | |
10589 | u16 vf_tmo_dsecs = n * 10; | |
10590 | ||
10591 | if (bp->fw_reset_max_dsecs < vf_tmo_dsecs) | |
10592 | bp->fw_reset_max_dsecs = vf_tmo_dsecs; | |
10593 | bp->fw_reset_state = | |
10594 | BNXT_FW_RESET_STATE_POLL_VF; | |
10595 | bnxt_queue_fw_reset_work(bp, HZ / 10); | |
10596 | goto fw_reset_exit; | |
230d1f0d MC |
10597 | } |
10598 | bnxt_fw_reset_close(bp); | |
4037eb71 VV |
10599 | if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { |
10600 | bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; | |
10601 | tmo = HZ / 10; | |
10602 | } else { | |
10603 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
10604 | tmo = bp->fw_reset_min_dsecs * HZ / 10; | |
10605 | } | |
10606 | bnxt_queue_fw_reset_work(bp, tmo); | |
230d1f0d MC |
10607 | } |
10608 | fw_reset_exit: | |
10609 | bnxt_rtnl_unlock_sp(bp); | |
10610 | } | |
10611 | ||
ffd77621 MC |
10612 | static void bnxt_chk_missed_irq(struct bnxt *bp) |
10613 | { | |
10614 | int i; | |
10615 | ||
10616 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
10617 | return; | |
10618 | ||
10619 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
10620 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
10621 | struct bnxt_cp_ring_info *cpr; | |
10622 | u32 fw_ring_id; | |
10623 | int j; | |
10624 | ||
10625 | if (!bnapi) | |
10626 | continue; | |
10627 | ||
10628 | cpr = &bnapi->cp_ring; | |
10629 | for (j = 0; j < 2; j++) { | |
10630 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; | |
10631 | u32 val[2]; | |
10632 | ||
10633 | if (!cpr2 || cpr2->has_more_work || | |
10634 | !bnxt_has_work(bp, cpr2)) | |
10635 | continue; | |
10636 | ||
10637 | if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) { | |
10638 | cpr2->last_cp_raw_cons = cpr2->cp_raw_cons; | |
10639 | continue; | |
10640 | } | |
10641 | fw_ring_id = cpr2->cp_ring_struct.fw_ring_id; | |
10642 | bnxt_dbg_hwrm_ring_info_get(bp, | |
10643 | DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL, | |
10644 | fw_ring_id, &val[0], &val[1]); | |
9d8b5f05 | 10645 | cpr->sw_stats.cmn.missed_irqs++; |
ffd77621 MC |
10646 | } |
10647 | } | |
10648 | } | |
10649 | ||
c0c050c5 MC |
10650 | static void bnxt_cfg_ntp_filters(struct bnxt *); |
10651 | ||
8119e49b MC |
10652 | static void bnxt_init_ethtool_link_settings(struct bnxt *bp) |
10653 | { | |
10654 | struct bnxt_link_info *link_info = &bp->link_info; | |
10655 | ||
10656 | if (BNXT_AUTO_MODE(link_info->auto_mode)) { | |
10657 | link_info->autoneg = BNXT_AUTONEG_SPEED; | |
10658 | if (bp->hwrm_spec_code >= 0x10201) { | |
10659 | if (link_info->auto_pause_setting & | |
10660 | PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE) | |
10661 | link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; | |
10662 | } else { | |
10663 | link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; | |
10664 | } | |
10665 | link_info->advertising = link_info->auto_link_speeds; | |
10666 | } else { | |
10667 | link_info->req_link_speed = link_info->force_link_speed; | |
10668 | link_info->req_duplex = link_info->duplex_setting; | |
10669 | } | |
10670 | if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) | |
10671 | link_info->req_flow_ctrl = | |
10672 | link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH; | |
10673 | else | |
10674 | link_info->req_flow_ctrl = link_info->force_pause_setting; | |
10675 | } | |
10676 | ||
c0c050c5 MC |
10677 | static void bnxt_sp_task(struct work_struct *work) |
10678 | { | |
10679 | struct bnxt *bp = container_of(work, struct bnxt, sp_task); | |
c0c050c5 | 10680 | |
4cebdcec MC |
10681 | set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); |
10682 | smp_mb__after_atomic(); | |
10683 | if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { | |
10684 | clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); | |
c0c050c5 | 10685 | return; |
4cebdcec | 10686 | } |
c0c050c5 MC |
10687 | |
10688 | if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) | |
10689 | bnxt_cfg_rx_mode(bp); | |
10690 | ||
10691 | if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) | |
10692 | bnxt_cfg_ntp_filters(bp); | |
c0c050c5 MC |
10693 | if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) |
10694 | bnxt_hwrm_exec_fwd_req(bp); | |
00db3cba | 10695 | if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) { |
531d1d26 MC |
10696 | bnxt_hwrm_port_qstats(bp, 0); |
10697 | bnxt_hwrm_port_qstats_ext(bp, 0); | |
fea6b333 | 10698 | bnxt_accumulate_all_stats(bp); |
00db3cba | 10699 | } |
3bdf56c4 | 10700 | |
0eaa24b9 | 10701 | if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { |
e2dc9b6e | 10702 | int rc; |
0eaa24b9 | 10703 | |
e2dc9b6e | 10704 | mutex_lock(&bp->link_lock); |
0eaa24b9 MC |
10705 | if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, |
10706 | &bp->sp_event)) | |
10707 | bnxt_hwrm_phy_qcaps(bp); | |
10708 | ||
e2dc9b6e | 10709 | rc = bnxt_update_link(bp, true); |
0eaa24b9 MC |
10710 | if (rc) |
10711 | netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", | |
10712 | rc); | |
ca0c7538 VV |
10713 | |
10714 | if (test_and_clear_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, | |
10715 | &bp->sp_event)) | |
10716 | bnxt_init_ethtool_link_settings(bp); | |
10717 | mutex_unlock(&bp->link_lock); | |
0eaa24b9 | 10718 | } |
a1ef4a79 MC |
10719 | if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) { |
10720 | int rc; | |
10721 | ||
10722 | mutex_lock(&bp->link_lock); | |
10723 | rc = bnxt_update_phy_setting(bp); | |
10724 | mutex_unlock(&bp->link_lock); | |
10725 | if (rc) { | |
10726 | netdev_warn(bp->dev, "update phy settings retry failed\n"); | |
10727 | } else { | |
10728 | bp->link_info.phy_retry = false; | |
10729 | netdev_info(bp->dev, "update phy settings retry succeeded\n"); | |
10730 | } | |
10731 | } | |
90c694bb | 10732 | if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) { |
e2dc9b6e MC |
10733 | mutex_lock(&bp->link_lock); |
10734 | bnxt_get_port_module_status(bp); | |
10735 | mutex_unlock(&bp->link_lock); | |
90c694bb | 10736 | } |
5a84acbe SP |
10737 | |
10738 | if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event)) | |
10739 | bnxt_tc_flow_stats_work(bp); | |
10740 | ||
ffd77621 MC |
10741 | if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event)) |
10742 | bnxt_chk_missed_irq(bp); | |
10743 | ||
e2dc9b6e MC |
10744 | /* These functions below will clear BNXT_STATE_IN_SP_TASK. They |
10745 | * must be the last functions to be called before exiting. | |
10746 | */ | |
6988bd92 MC |
10747 | if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) |
10748 | bnxt_reset(bp, false); | |
4cebdcec | 10749 | |
fc0f1929 MC |
10750 | if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event)) |
10751 | bnxt_reset(bp, true); | |
10752 | ||
657a33c8 VV |
10753 | if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event)) |
10754 | bnxt_devlink_health_report(bp, BNXT_FW_RESET_NOTIFY_SP_EVENT); | |
10755 | ||
acfb50e4 VV |
10756 | if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) { |
10757 | if (!is_bnxt_fw_ok(bp)) | |
10758 | bnxt_devlink_health_report(bp, | |
10759 | BNXT_FW_EXCEPTION_SP_EVENT); | |
10760 | } | |
10761 | ||
4cebdcec MC |
10762 | smp_mb__before_atomic(); |
10763 | clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); | |
c0c050c5 MC |
10764 | } |
10765 | ||
d1e7925e | 10766 | /* Under rtnl_lock */ |
98fdbe73 MC |
10767 | int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, |
10768 | int tx_xdp) | |
d1e7925e MC |
10769 | { |
10770 | int max_rx, max_tx, tx_sets = 1; | |
780baad4 | 10771 | int tx_rings_needed, stats; |
8f23d638 | 10772 | int rx_rings = rx; |
6fc2ffdf | 10773 | int cp, vnics, rc; |
d1e7925e | 10774 | |
d1e7925e MC |
10775 | if (tcs) |
10776 | tx_sets = tcs; | |
10777 | ||
10778 | rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh); | |
10779 | if (rc) | |
10780 | return rc; | |
10781 | ||
10782 | if (max_rx < rx) | |
10783 | return -ENOMEM; | |
10784 | ||
5f449249 | 10785 | tx_rings_needed = tx * tx_sets + tx_xdp; |
d1e7925e MC |
10786 | if (max_tx < tx_rings_needed) |
10787 | return -ENOMEM; | |
10788 | ||
6fc2ffdf | 10789 | vnics = 1; |
9b3d15e6 | 10790 | if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) |
6fc2ffdf EW |
10791 | vnics += rx_rings; |
10792 | ||
8f23d638 MC |
10793 | if (bp->flags & BNXT_FLAG_AGG_RINGS) |
10794 | rx_rings <<= 1; | |
10795 | cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx; | |
780baad4 VV |
10796 | stats = cp; |
10797 | if (BNXT_NEW_RM(bp)) { | |
11c3ec7b | 10798 | cp += bnxt_get_ulp_msix_num(bp); |
780baad4 VV |
10799 | stats += bnxt_get_ulp_stat_ctxs(bp); |
10800 | } | |
6fc2ffdf | 10801 | return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp, |
780baad4 | 10802 | stats, vnics); |
d1e7925e MC |
10803 | } |
10804 | ||
17086399 SP |
10805 | static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev) |
10806 | { | |
10807 | if (bp->bar2) { | |
10808 | pci_iounmap(pdev, bp->bar2); | |
10809 | bp->bar2 = NULL; | |
10810 | } | |
10811 | ||
10812 | if (bp->bar1) { | |
10813 | pci_iounmap(pdev, bp->bar1); | |
10814 | bp->bar1 = NULL; | |
10815 | } | |
10816 | ||
10817 | if (bp->bar0) { | |
10818 | pci_iounmap(pdev, bp->bar0); | |
10819 | bp->bar0 = NULL; | |
10820 | } | |
10821 | } | |
10822 | ||
10823 | static void bnxt_cleanup_pci(struct bnxt *bp) | |
10824 | { | |
10825 | bnxt_unmap_bars(bp, bp->pdev); | |
10826 | pci_release_regions(bp->pdev); | |
f6824308 VV |
10827 | if (pci_is_enabled(bp->pdev)) |
10828 | pci_disable_device(bp->pdev); | |
17086399 SP |
10829 | } |
10830 | ||
18775aa8 MC |
10831 | static void bnxt_init_dflt_coal(struct bnxt *bp) |
10832 | { | |
10833 | struct bnxt_coal *coal; | |
10834 | ||
10835 | /* Tick values in micro seconds. | |
10836 | * 1 coal_buf x bufs_per_record = 1 completion record. | |
10837 | */ | |
10838 | coal = &bp->rx_coal; | |
0c2ff8d7 | 10839 | coal->coal_ticks = 10; |
18775aa8 MC |
10840 | coal->coal_bufs = 30; |
10841 | coal->coal_ticks_irq = 1; | |
10842 | coal->coal_bufs_irq = 2; | |
05abe4dd | 10843 | coal->idle_thresh = 50; |
18775aa8 MC |
10844 | coal->bufs_per_record = 2; |
10845 | coal->budget = 64; /* NAPI budget */ | |
10846 | ||
10847 | coal = &bp->tx_coal; | |
10848 | coal->coal_ticks = 28; | |
10849 | coal->coal_bufs = 30; | |
10850 | coal->coal_ticks_irq = 2; | |
10851 | coal->coal_bufs_irq = 2; | |
10852 | coal->bufs_per_record = 1; | |
10853 | ||
10854 | bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS; | |
10855 | } | |
10856 | ||
8280b38e VV |
10857 | static void bnxt_alloc_fw_health(struct bnxt *bp) |
10858 | { | |
10859 | if (bp->fw_health) | |
10860 | return; | |
10861 | ||
10862 | if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) && | |
10863 | !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) | |
10864 | return; | |
10865 | ||
10866 | bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL); | |
10867 | if (!bp->fw_health) { | |
10868 | netdev_warn(bp->dev, "Failed to allocate fw_health\n"); | |
10869 | bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET; | |
10870 | bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; | |
10871 | } | |
10872 | } | |
10873 | ||
7c380918 MC |
10874 | static int bnxt_fw_init_one_p1(struct bnxt *bp) |
10875 | { | |
10876 | int rc; | |
10877 | ||
10878 | bp->fw_cap = 0; | |
10879 | rc = bnxt_hwrm_ver_get(bp); | |
10880 | if (rc) | |
10881 | return rc; | |
10882 | ||
10883 | if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) { | |
10884 | rc = bnxt_alloc_kong_hwrm_resources(bp); | |
10885 | if (rc) | |
10886 | bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL; | |
10887 | } | |
10888 | ||
10889 | if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || | |
10890 | bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) { | |
10891 | rc = bnxt_alloc_hwrm_short_cmd_req(bp); | |
10892 | if (rc) | |
10893 | return rc; | |
10894 | } | |
10895 | rc = bnxt_hwrm_func_reset(bp); | |
10896 | if (rc) | |
10897 | return -ENODEV; | |
10898 | ||
10899 | bnxt_hwrm_fw_set_time(bp); | |
10900 | return 0; | |
10901 | } | |
10902 | ||
10903 | static int bnxt_fw_init_one_p2(struct bnxt *bp) | |
10904 | { | |
10905 | int rc; | |
10906 | ||
10907 | /* Get the MAX capabilities for this function */ | |
10908 | rc = bnxt_hwrm_func_qcaps(bp); | |
10909 | if (rc) { | |
10910 | netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", | |
10911 | rc); | |
10912 | return -ENODEV; | |
10913 | } | |
10914 | ||
10915 | rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp); | |
10916 | if (rc) | |
10917 | netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n", | |
10918 | rc); | |
10919 | ||
8280b38e | 10920 | bnxt_alloc_fw_health(bp); |
07f83d72 MC |
10921 | rc = bnxt_hwrm_error_recovery_qcfg(bp); |
10922 | if (rc) | |
10923 | netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n", | |
10924 | rc); | |
10925 | ||
2e882468 | 10926 | rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false); |
7c380918 MC |
10927 | if (rc) |
10928 | return -ENODEV; | |
10929 | ||
10930 | bnxt_hwrm_func_qcfg(bp); | |
10931 | bnxt_hwrm_vnic_qcaps(bp); | |
10932 | bnxt_hwrm_port_led_qcaps(bp); | |
10933 | bnxt_ethtool_init(bp); | |
10934 | bnxt_dcb_init(bp); | |
10935 | return 0; | |
10936 | } | |
10937 | ||
ba642ab7 MC |
10938 | static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp) |
10939 | { | |
10940 | bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP; | |
10941 | bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 | | |
10942 | VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 | | |
10943 | VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | | |
10944 | VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; | |
c66c06c5 | 10945 | if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) { |
ba642ab7 MC |
10946 | bp->flags |= BNXT_FLAG_UDP_RSS_CAP; |
10947 | bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 | | |
10948 | VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; | |
10949 | } | |
10950 | } | |
10951 | ||
10952 | static void bnxt_set_dflt_rfs(struct bnxt *bp) | |
10953 | { | |
10954 | struct net_device *dev = bp->dev; | |
10955 | ||
10956 | dev->hw_features &= ~NETIF_F_NTUPLE; | |
10957 | dev->features &= ~NETIF_F_NTUPLE; | |
10958 | bp->flags &= ~BNXT_FLAG_RFS; | |
10959 | if (bnxt_rfs_supported(bp)) { | |
10960 | dev->hw_features |= NETIF_F_NTUPLE; | |
10961 | if (bnxt_rfs_capable(bp)) { | |
10962 | bp->flags |= BNXT_FLAG_RFS; | |
10963 | dev->features |= NETIF_F_NTUPLE; | |
10964 | } | |
10965 | } | |
10966 | } | |
10967 | ||
10968 | static void bnxt_fw_init_one_p3(struct bnxt *bp) | |
10969 | { | |
10970 | struct pci_dev *pdev = bp->pdev; | |
10971 | ||
10972 | bnxt_set_dflt_rss_hash_type(bp); | |
10973 | bnxt_set_dflt_rfs(bp); | |
10974 | ||
10975 | bnxt_get_wol_settings(bp); | |
10976 | if (bp->flags & BNXT_FLAG_WOL_CAP) | |
10977 | device_set_wakeup_enable(&pdev->dev, bp->wol); | |
10978 | else | |
10979 | device_set_wakeup_capable(&pdev->dev, false); | |
10980 | ||
10981 | bnxt_hwrm_set_cache_line_size(bp, cache_line_size()); | |
10982 | bnxt_hwrm_coal_params_qcaps(bp); | |
10983 | } | |
10984 | ||
ec5d31e3 MC |
10985 | static int bnxt_fw_init_one(struct bnxt *bp) |
10986 | { | |
10987 | int rc; | |
10988 | ||
10989 | rc = bnxt_fw_init_one_p1(bp); | |
10990 | if (rc) { | |
10991 | netdev_err(bp->dev, "Firmware init phase 1 failed\n"); | |
10992 | return rc; | |
10993 | } | |
10994 | rc = bnxt_fw_init_one_p2(bp); | |
10995 | if (rc) { | |
10996 | netdev_err(bp->dev, "Firmware init phase 2 failed\n"); | |
10997 | return rc; | |
10998 | } | |
10999 | rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false); | |
11000 | if (rc) | |
11001 | return rc; | |
937f188c VV |
11002 | |
11003 | /* In case fw capabilities have changed, destroy the unneeded | |
11004 | * reporters and create newly capable ones. | |
11005 | */ | |
11006 | bnxt_dl_fw_reporters_destroy(bp, false); | |
11007 | bnxt_dl_fw_reporters_create(bp); | |
ec5d31e3 MC |
11008 | bnxt_fw_init_one_p3(bp); |
11009 | return 0; | |
11010 | } | |
11011 | ||
cbb51067 MC |
11012 | static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx) |
11013 | { | |
11014 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
11015 | u32 reg = fw_health->fw_reset_seq_regs[reg_idx]; | |
11016 | u32 val = fw_health->fw_reset_seq_vals[reg_idx]; | |
11017 | u32 reg_type, reg_off, delay_msecs; | |
11018 | ||
11019 | delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx]; | |
11020 | reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); | |
11021 | reg_off = BNXT_FW_HEALTH_REG_OFF(reg); | |
11022 | switch (reg_type) { | |
11023 | case BNXT_FW_HEALTH_REG_TYPE_CFG: | |
11024 | pci_write_config_dword(bp->pdev, reg_off, val); | |
11025 | break; | |
11026 | case BNXT_FW_HEALTH_REG_TYPE_GRC: | |
11027 | writel(reg_off & BNXT_GRC_BASE_MASK, | |
11028 | bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); | |
11029 | reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000; | |
11030 | /* fall through */ | |
11031 | case BNXT_FW_HEALTH_REG_TYPE_BAR0: | |
11032 | writel(val, bp->bar0 + reg_off); | |
11033 | break; | |
11034 | case BNXT_FW_HEALTH_REG_TYPE_BAR1: | |
11035 | writel(val, bp->bar1 + reg_off); | |
11036 | break; | |
11037 | } | |
11038 | if (delay_msecs) { | |
11039 | pci_read_config_dword(bp->pdev, 0, &val); | |
11040 | msleep(delay_msecs); | |
11041 | } | |
11042 | } | |
11043 | ||
11044 | static void bnxt_reset_all(struct bnxt *bp) | |
11045 | { | |
11046 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
e07ab202 VV |
11047 | int i, rc; |
11048 | ||
11049 | if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { | |
11050 | #ifdef CONFIG_TEE_BNXT_FW | |
11051 | rc = tee_bnxt_fw_load(); | |
11052 | if (rc) | |
11053 | netdev_err(bp->dev, "Unable to reset FW rc=%d\n", rc); | |
11054 | bp->fw_reset_timestamp = jiffies; | |
11055 | #endif | |
11056 | return; | |
11057 | } | |
cbb51067 MC |
11058 | |
11059 | if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) { | |
11060 | for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) | |
11061 | bnxt_fw_reset_writel(bp, i); | |
11062 | } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) { | |
11063 | struct hwrm_fw_reset_input req = {0}; | |
cbb51067 MC |
11064 | |
11065 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1); | |
11066 | req.resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); | |
11067 | req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP; | |
11068 | req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP; | |
11069 | req.flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; | |
11070 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
11071 | if (rc) | |
11072 | netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc); | |
11073 | } | |
11074 | bp->fw_reset_timestamp = jiffies; | |
11075 | } | |
11076 | ||
230d1f0d MC |
11077 | static void bnxt_fw_reset_task(struct work_struct *work) |
11078 | { | |
11079 | struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work); | |
11080 | int rc; | |
11081 | ||
11082 | if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { | |
11083 | netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n"); | |
11084 | return; | |
11085 | } | |
11086 | ||
11087 | switch (bp->fw_reset_state) { | |
e72cb7d6 MC |
11088 | case BNXT_FW_RESET_STATE_POLL_VF: { |
11089 | int n = bnxt_get_registered_vfs(bp); | |
4037eb71 | 11090 | int tmo; |
e72cb7d6 MC |
11091 | |
11092 | if (n < 0) { | |
230d1f0d | 11093 | netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n", |
e72cb7d6 | 11094 | n, jiffies_to_msecs(jiffies - |
230d1f0d MC |
11095 | bp->fw_reset_timestamp)); |
11096 | goto fw_reset_abort; | |
e72cb7d6 | 11097 | } else if (n > 0) { |
230d1f0d MC |
11098 | if (time_after(jiffies, bp->fw_reset_timestamp + |
11099 | (bp->fw_reset_max_dsecs * HZ / 10))) { | |
11100 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
11101 | bp->fw_reset_state = 0; | |
e72cb7d6 MC |
11102 | netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n", |
11103 | n); | |
230d1f0d MC |
11104 | return; |
11105 | } | |
11106 | bnxt_queue_fw_reset_work(bp, HZ / 10); | |
11107 | return; | |
11108 | } | |
11109 | bp->fw_reset_timestamp = jiffies; | |
11110 | rtnl_lock(); | |
11111 | bnxt_fw_reset_close(bp); | |
4037eb71 VV |
11112 | if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { |
11113 | bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; | |
11114 | tmo = HZ / 10; | |
11115 | } else { | |
11116 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
11117 | tmo = bp->fw_reset_min_dsecs * HZ / 10; | |
11118 | } | |
230d1f0d | 11119 | rtnl_unlock(); |
4037eb71 | 11120 | bnxt_queue_fw_reset_work(bp, tmo); |
230d1f0d | 11121 | return; |
e72cb7d6 | 11122 | } |
4037eb71 VV |
11123 | case BNXT_FW_RESET_STATE_POLL_FW_DOWN: { |
11124 | u32 val; | |
11125 | ||
11126 | val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); | |
11127 | if (!(val & BNXT_FW_STATUS_SHUTDOWN) && | |
11128 | !time_after(jiffies, bp->fw_reset_timestamp + | |
11129 | (bp->fw_reset_max_dsecs * HZ / 10))) { | |
11130 | bnxt_queue_fw_reset_work(bp, HZ / 5); | |
11131 | return; | |
11132 | } | |
11133 | ||
11134 | if (!bp->fw_health->master) { | |
11135 | u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs; | |
11136 | ||
11137 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
11138 | bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); | |
11139 | return; | |
11140 | } | |
11141 | bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; | |
11142 | } | |
11143 | /* fall through */ | |
c6a9e7aa | 11144 | case BNXT_FW_RESET_STATE_RESET_FW: |
cbb51067 MC |
11145 | bnxt_reset_all(bp); |
11146 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
c6a9e7aa | 11147 | bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10); |
cbb51067 | 11148 | return; |
230d1f0d | 11149 | case BNXT_FW_RESET_STATE_ENABLE_DEV: |
0797c10d | 11150 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) { |
d1db9e16 MC |
11151 | u32 val; |
11152 | ||
11153 | val = bnxt_fw_health_readl(bp, | |
11154 | BNXT_FW_RESET_INPROG_REG); | |
11155 | if (val) | |
11156 | netdev_warn(bp->dev, "FW reset inprog %x after min wait time.\n", | |
11157 | val); | |
11158 | } | |
b4fff207 | 11159 | clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); |
230d1f0d MC |
11160 | if (pci_enable_device(bp->pdev)) { |
11161 | netdev_err(bp->dev, "Cannot re-enable PCI device\n"); | |
11162 | goto fw_reset_abort; | |
11163 | } | |
11164 | pci_set_master(bp->pdev); | |
11165 | bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW; | |
11166 | /* fall through */ | |
11167 | case BNXT_FW_RESET_STATE_POLL_FW: | |
11168 | bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT; | |
11169 | rc = __bnxt_hwrm_ver_get(bp, true); | |
11170 | if (rc) { | |
11171 | if (time_after(jiffies, bp->fw_reset_timestamp + | |
11172 | (bp->fw_reset_max_dsecs * HZ / 10))) { | |
11173 | netdev_err(bp->dev, "Firmware reset aborted\n"); | |
11174 | goto fw_reset_abort; | |
11175 | } | |
11176 | bnxt_queue_fw_reset_work(bp, HZ / 5); | |
11177 | return; | |
11178 | } | |
11179 | bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; | |
11180 | bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING; | |
11181 | /* fall through */ | |
11182 | case BNXT_FW_RESET_STATE_OPENING: | |
11183 | while (!rtnl_trylock()) { | |
11184 | bnxt_queue_fw_reset_work(bp, HZ / 10); | |
11185 | return; | |
11186 | } | |
11187 | rc = bnxt_open(bp->dev); | |
11188 | if (rc) { | |
11189 | netdev_err(bp->dev, "bnxt_open_nic() failed\n"); | |
11190 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
11191 | dev_close(bp->dev); | |
11192 | } | |
230d1f0d MC |
11193 | |
11194 | bp->fw_reset_state = 0; | |
11195 | /* Make sure fw_reset_state is 0 before clearing the flag */ | |
11196 | smp_mb__before_atomic(); | |
11197 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
f3a6d206 | 11198 | bnxt_ulp_start(bp, rc); |
12de2ead MC |
11199 | if (!rc) |
11200 | bnxt_reenable_sriov(bp); | |
737d7a6c | 11201 | bnxt_dl_health_recovery_done(bp); |
e4e38237 | 11202 | bnxt_dl_health_status_update(bp, true); |
f3a6d206 | 11203 | rtnl_unlock(); |
230d1f0d MC |
11204 | break; |
11205 | } | |
11206 | return; | |
11207 | ||
11208 | fw_reset_abort: | |
11209 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
e4e38237 VV |
11210 | if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF) |
11211 | bnxt_dl_health_status_update(bp, false); | |
230d1f0d MC |
11212 | bp->fw_reset_state = 0; |
11213 | rtnl_lock(); | |
11214 | dev_close(bp->dev); | |
11215 | rtnl_unlock(); | |
11216 | } | |
11217 | ||
c0c050c5 MC |
11218 | static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) |
11219 | { | |
11220 | int rc; | |
11221 | struct bnxt *bp = netdev_priv(dev); | |
11222 | ||
11223 | SET_NETDEV_DEV(dev, &pdev->dev); | |
11224 | ||
11225 | /* enable device (incl. PCI PM wakeup), and bus-mastering */ | |
11226 | rc = pci_enable_device(pdev); | |
11227 | if (rc) { | |
11228 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); | |
11229 | goto init_err; | |
11230 | } | |
11231 | ||
11232 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
11233 | dev_err(&pdev->dev, | |
11234 | "Cannot find PCI device base address, aborting\n"); | |
11235 | rc = -ENODEV; | |
11236 | goto init_err_disable; | |
11237 | } | |
11238 | ||
11239 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
11240 | if (rc) { | |
11241 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); | |
11242 | goto init_err_disable; | |
11243 | } | |
11244 | ||
11245 | if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && | |
11246 | dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { | |
11247 | dev_err(&pdev->dev, "System does not support DMA, aborting\n"); | |
11248 | goto init_err_disable; | |
11249 | } | |
11250 | ||
11251 | pci_set_master(pdev); | |
11252 | ||
11253 | bp->dev = dev; | |
11254 | bp->pdev = pdev; | |
11255 | ||
8ae24738 MC |
11256 | /* Doorbell BAR bp->bar1 is mapped after bnxt_fw_init_one_p2() |
11257 | * determines the BAR size. | |
11258 | */ | |
c0c050c5 MC |
11259 | bp->bar0 = pci_ioremap_bar(pdev, 0); |
11260 | if (!bp->bar0) { | |
11261 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); | |
11262 | rc = -ENOMEM; | |
11263 | goto init_err_release; | |
11264 | } | |
11265 | ||
c0c050c5 MC |
11266 | bp->bar2 = pci_ioremap_bar(pdev, 4); |
11267 | if (!bp->bar2) { | |
11268 | dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); | |
11269 | rc = -ENOMEM; | |
11270 | goto init_err_release; | |
11271 | } | |
11272 | ||
6316ea6d SB |
11273 | pci_enable_pcie_error_reporting(pdev); |
11274 | ||
c0c050c5 | 11275 | INIT_WORK(&bp->sp_task, bnxt_sp_task); |
230d1f0d | 11276 | INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task); |
c0c050c5 MC |
11277 | |
11278 | spin_lock_init(&bp->ntp_fltr_lock); | |
697197e5 MC |
11279 | #if BITS_PER_LONG == 32 |
11280 | spin_lock_init(&bp->db_lock); | |
11281 | #endif | |
c0c050c5 MC |
11282 | |
11283 | bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; | |
11284 | bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; | |
11285 | ||
18775aa8 | 11286 | bnxt_init_dflt_coal(bp); |
51f30785 | 11287 | |
e99e88a9 | 11288 | timer_setup(&bp->timer, bnxt_timer, 0); |
c0c050c5 MC |
11289 | bp->current_interval = BNXT_TIMER_INTERVAL; |
11290 | ||
442a35a5 JK |
11291 | bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID; |
11292 | bp->nge_fw_dst_port_id = INVALID_HW_RING_ID; | |
11293 | ||
caefe526 | 11294 | clear_bit(BNXT_STATE_OPEN, &bp->state); |
c0c050c5 MC |
11295 | return 0; |
11296 | ||
11297 | init_err_release: | |
17086399 | 11298 | bnxt_unmap_bars(bp, pdev); |
c0c050c5 MC |
11299 | pci_release_regions(pdev); |
11300 | ||
11301 | init_err_disable: | |
11302 | pci_disable_device(pdev); | |
11303 | ||
11304 | init_err: | |
11305 | return rc; | |
11306 | } | |
11307 | ||
11308 | /* rtnl_lock held */ | |
11309 | static int bnxt_change_mac_addr(struct net_device *dev, void *p) | |
11310 | { | |
11311 | struct sockaddr *addr = p; | |
1fc2cfd0 JH |
11312 | struct bnxt *bp = netdev_priv(dev); |
11313 | int rc = 0; | |
c0c050c5 MC |
11314 | |
11315 | if (!is_valid_ether_addr(addr->sa_data)) | |
11316 | return -EADDRNOTAVAIL; | |
11317 | ||
c1a7bdff MC |
11318 | if (ether_addr_equal(addr->sa_data, dev->dev_addr)) |
11319 | return 0; | |
11320 | ||
28ea334b | 11321 | rc = bnxt_approve_mac(bp, addr->sa_data, true); |
84c33dd3 MC |
11322 | if (rc) |
11323 | return rc; | |
bdd4347b | 11324 | |
c0c050c5 | 11325 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
1fc2cfd0 JH |
11326 | if (netif_running(dev)) { |
11327 | bnxt_close_nic(bp, false, false); | |
11328 | rc = bnxt_open_nic(bp, false, false); | |
11329 | } | |
c0c050c5 | 11330 | |
1fc2cfd0 | 11331 | return rc; |
c0c050c5 MC |
11332 | } |
11333 | ||
11334 | /* rtnl_lock held */ | |
11335 | static int bnxt_change_mtu(struct net_device *dev, int new_mtu) | |
11336 | { | |
11337 | struct bnxt *bp = netdev_priv(dev); | |
11338 | ||
c0c050c5 | 11339 | if (netif_running(dev)) |
a9b952d2 | 11340 | bnxt_close_nic(bp, true, false); |
c0c050c5 MC |
11341 | |
11342 | dev->mtu = new_mtu; | |
11343 | bnxt_set_ring_params(bp); | |
11344 | ||
11345 | if (netif_running(dev)) | |
a9b952d2 | 11346 | return bnxt_open_nic(bp, true, false); |
c0c050c5 MC |
11347 | |
11348 | return 0; | |
11349 | } | |
11350 | ||
c5e3deb8 | 11351 | int bnxt_setup_mq_tc(struct net_device *dev, u8 tc) |
c0c050c5 MC |
11352 | { |
11353 | struct bnxt *bp = netdev_priv(dev); | |
3ffb6a39 | 11354 | bool sh = false; |
d1e7925e | 11355 | int rc; |
16e5cc64 | 11356 | |
c0c050c5 | 11357 | if (tc > bp->max_tc) { |
b451c8b6 | 11358 | netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n", |
c0c050c5 MC |
11359 | tc, bp->max_tc); |
11360 | return -EINVAL; | |
11361 | } | |
11362 | ||
11363 | if (netdev_get_num_tc(dev) == tc) | |
11364 | return 0; | |
11365 | ||
3ffb6a39 MC |
11366 | if (bp->flags & BNXT_FLAG_SHARED_RINGS) |
11367 | sh = true; | |
11368 | ||
98fdbe73 MC |
11369 | rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings, |
11370 | sh, tc, bp->tx_nr_rings_xdp); | |
d1e7925e MC |
11371 | if (rc) |
11372 | return rc; | |
c0c050c5 MC |
11373 | |
11374 | /* Needs to close the device and do hw resource re-allocations */ | |
11375 | if (netif_running(bp->dev)) | |
11376 | bnxt_close_nic(bp, true, false); | |
11377 | ||
11378 | if (tc) { | |
11379 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; | |
11380 | netdev_set_num_tc(dev, tc); | |
11381 | } else { | |
11382 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc; | |
11383 | netdev_reset_tc(dev); | |
11384 | } | |
87e9b377 | 11385 | bp->tx_nr_rings += bp->tx_nr_rings_xdp; |
3ffb6a39 MC |
11386 | bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : |
11387 | bp->tx_nr_rings + bp->rx_nr_rings; | |
c0c050c5 MC |
11388 | |
11389 | if (netif_running(bp->dev)) | |
11390 | return bnxt_open_nic(bp, true, false); | |
11391 | ||
11392 | return 0; | |
11393 | } | |
11394 | ||
9e0fd15d JP |
11395 | static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data, |
11396 | void *cb_priv) | |
c5e3deb8 | 11397 | { |
9e0fd15d | 11398 | struct bnxt *bp = cb_priv; |
de4784ca | 11399 | |
312324f1 JK |
11400 | if (!bnxt_tc_flower_enabled(bp) || |
11401 | !tc_cls_can_offload_and_chain0(bp->dev, type_data)) | |
38cf0426 | 11402 | return -EOPNOTSUPP; |
c5e3deb8 | 11403 | |
9e0fd15d JP |
11404 | switch (type) { |
11405 | case TC_SETUP_CLSFLOWER: | |
11406 | return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data); | |
11407 | default: | |
11408 | return -EOPNOTSUPP; | |
11409 | } | |
11410 | } | |
11411 | ||
627c89d0 | 11412 | LIST_HEAD(bnxt_block_cb_list); |
955bcb6e | 11413 | |
2ae7408f SP |
11414 | static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type, |
11415 | void *type_data) | |
11416 | { | |
4e95bc26 PNA |
11417 | struct bnxt *bp = netdev_priv(dev); |
11418 | ||
2ae7408f | 11419 | switch (type) { |
9e0fd15d | 11420 | case TC_SETUP_BLOCK: |
955bcb6e PNA |
11421 | return flow_block_cb_setup_simple(type_data, |
11422 | &bnxt_block_cb_list, | |
4e95bc26 PNA |
11423 | bnxt_setup_tc_block_cb, |
11424 | bp, bp, true); | |
575ed7d3 | 11425 | case TC_SETUP_QDISC_MQPRIO: { |
2ae7408f SP |
11426 | struct tc_mqprio_qopt *mqprio = type_data; |
11427 | ||
11428 | mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; | |
56f36acd | 11429 | |
2ae7408f SP |
11430 | return bnxt_setup_mq_tc(dev, mqprio->num_tc); |
11431 | } | |
11432 | default: | |
11433 | return -EOPNOTSUPP; | |
11434 | } | |
c5e3deb8 MC |
11435 | } |
11436 | ||
c0c050c5 MC |
11437 | #ifdef CONFIG_RFS_ACCEL |
11438 | static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, | |
11439 | struct bnxt_ntuple_filter *f2) | |
11440 | { | |
11441 | struct flow_keys *keys1 = &f1->fkeys; | |
11442 | struct flow_keys *keys2 = &f2->fkeys; | |
11443 | ||
6fc7caa8 MC |
11444 | if (keys1->basic.n_proto != keys2->basic.n_proto || |
11445 | keys1->basic.ip_proto != keys2->basic.ip_proto) | |
11446 | return false; | |
11447 | ||
11448 | if (keys1->basic.n_proto == htons(ETH_P_IP)) { | |
11449 | if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src || | |
11450 | keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst) | |
11451 | return false; | |
11452 | } else { | |
11453 | if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src, | |
11454 | sizeof(keys1->addrs.v6addrs.src)) || | |
11455 | memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst, | |
11456 | sizeof(keys1->addrs.v6addrs.dst))) | |
11457 | return false; | |
11458 | } | |
11459 | ||
11460 | if (keys1->ports.ports == keys2->ports.ports && | |
61aad724 | 11461 | keys1->control.flags == keys2->control.flags && |
a54c4d74 MC |
11462 | ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) && |
11463 | ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr)) | |
c0c050c5 MC |
11464 | return true; |
11465 | ||
11466 | return false; | |
11467 | } | |
11468 | ||
11469 | static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, | |
11470 | u16 rxq_index, u32 flow_id) | |
11471 | { | |
11472 | struct bnxt *bp = netdev_priv(dev); | |
11473 | struct bnxt_ntuple_filter *fltr, *new_fltr; | |
11474 | struct flow_keys *fkeys; | |
11475 | struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); | |
a54c4d74 | 11476 | int rc = 0, idx, bit_id, l2_idx = 0; |
c0c050c5 | 11477 | struct hlist_head *head; |
f47d0e19 | 11478 | u32 flags; |
c0c050c5 | 11479 | |
a54c4d74 MC |
11480 | if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) { |
11481 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; | |
11482 | int off = 0, j; | |
11483 | ||
11484 | netif_addr_lock_bh(dev); | |
11485 | for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) { | |
11486 | if (ether_addr_equal(eth->h_dest, | |
11487 | vnic->uc_list + off)) { | |
11488 | l2_idx = j + 1; | |
11489 | break; | |
11490 | } | |
11491 | } | |
11492 | netif_addr_unlock_bh(dev); | |
11493 | if (!l2_idx) | |
11494 | return -EINVAL; | |
11495 | } | |
c0c050c5 MC |
11496 | new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); |
11497 | if (!new_fltr) | |
11498 | return -ENOMEM; | |
11499 | ||
11500 | fkeys = &new_fltr->fkeys; | |
11501 | if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { | |
11502 | rc = -EPROTONOSUPPORT; | |
11503 | goto err_free; | |
11504 | } | |
11505 | ||
dda0e746 MC |
11506 | if ((fkeys->basic.n_proto != htons(ETH_P_IP) && |
11507 | fkeys->basic.n_proto != htons(ETH_P_IPV6)) || | |
c0c050c5 MC |
11508 | ((fkeys->basic.ip_proto != IPPROTO_TCP) && |
11509 | (fkeys->basic.ip_proto != IPPROTO_UDP))) { | |
11510 | rc = -EPROTONOSUPPORT; | |
11511 | goto err_free; | |
11512 | } | |
dda0e746 MC |
11513 | if (fkeys->basic.n_proto == htons(ETH_P_IPV6) && |
11514 | bp->hwrm_spec_code < 0x10601) { | |
11515 | rc = -EPROTONOSUPPORT; | |
11516 | goto err_free; | |
11517 | } | |
f47d0e19 MC |
11518 | flags = fkeys->control.flags; |
11519 | if (((flags & FLOW_DIS_ENCAPSULATION) && | |
11520 | bp->hwrm_spec_code < 0x10601) || (flags & FLOW_DIS_IS_FRAGMENT)) { | |
61aad724 MC |
11521 | rc = -EPROTONOSUPPORT; |
11522 | goto err_free; | |
11523 | } | |
c0c050c5 | 11524 | |
a54c4d74 | 11525 | memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN); |
c0c050c5 MC |
11526 | memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); |
11527 | ||
11528 | idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; | |
11529 | head = &bp->ntp_fltr_hash_tbl[idx]; | |
11530 | rcu_read_lock(); | |
11531 | hlist_for_each_entry_rcu(fltr, head, hash) { | |
11532 | if (bnxt_fltr_match(fltr, new_fltr)) { | |
11533 | rcu_read_unlock(); | |
11534 | rc = 0; | |
11535 | goto err_free; | |
11536 | } | |
11537 | } | |
11538 | rcu_read_unlock(); | |
11539 | ||
11540 | spin_lock_bh(&bp->ntp_fltr_lock); | |
84e86b98 MC |
11541 | bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, |
11542 | BNXT_NTP_FLTR_MAX_FLTR, 0); | |
11543 | if (bit_id < 0) { | |
c0c050c5 MC |
11544 | spin_unlock_bh(&bp->ntp_fltr_lock); |
11545 | rc = -ENOMEM; | |
11546 | goto err_free; | |
11547 | } | |
11548 | ||
84e86b98 | 11549 | new_fltr->sw_id = (u16)bit_id; |
c0c050c5 | 11550 | new_fltr->flow_id = flow_id; |
a54c4d74 | 11551 | new_fltr->l2_fltr_idx = l2_idx; |
c0c050c5 MC |
11552 | new_fltr->rxq = rxq_index; |
11553 | hlist_add_head_rcu(&new_fltr->hash, head); | |
11554 | bp->ntp_fltr_count++; | |
11555 | spin_unlock_bh(&bp->ntp_fltr_lock); | |
11556 | ||
11557 | set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); | |
c213eae8 | 11558 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
11559 | |
11560 | return new_fltr->sw_id; | |
11561 | ||
11562 | err_free: | |
11563 | kfree(new_fltr); | |
11564 | return rc; | |
11565 | } | |
11566 | ||
11567 | static void bnxt_cfg_ntp_filters(struct bnxt *bp) | |
11568 | { | |
11569 | int i; | |
11570 | ||
11571 | for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { | |
11572 | struct hlist_head *head; | |
11573 | struct hlist_node *tmp; | |
11574 | struct bnxt_ntuple_filter *fltr; | |
11575 | int rc; | |
11576 | ||
11577 | head = &bp->ntp_fltr_hash_tbl[i]; | |
11578 | hlist_for_each_entry_safe(fltr, tmp, head, hash) { | |
11579 | bool del = false; | |
11580 | ||
11581 | if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { | |
11582 | if (rps_may_expire_flow(bp->dev, fltr->rxq, | |
11583 | fltr->flow_id, | |
11584 | fltr->sw_id)) { | |
11585 | bnxt_hwrm_cfa_ntuple_filter_free(bp, | |
11586 | fltr); | |
11587 | del = true; | |
11588 | } | |
11589 | } else { | |
11590 | rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, | |
11591 | fltr); | |
11592 | if (rc) | |
11593 | del = true; | |
11594 | else | |
11595 | set_bit(BNXT_FLTR_VALID, &fltr->state); | |
11596 | } | |
11597 | ||
11598 | if (del) { | |
11599 | spin_lock_bh(&bp->ntp_fltr_lock); | |
11600 | hlist_del_rcu(&fltr->hash); | |
11601 | bp->ntp_fltr_count--; | |
11602 | spin_unlock_bh(&bp->ntp_fltr_lock); | |
11603 | synchronize_rcu(); | |
11604 | clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); | |
11605 | kfree(fltr); | |
11606 | } | |
11607 | } | |
11608 | } | |
19241368 | 11609 | if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event)) |
9a005c38 | 11610 | netdev_info(bp->dev, "Receive PF driver unload event!\n"); |
c0c050c5 MC |
11611 | } |
11612 | ||
11613 | #else | |
11614 | ||
11615 | static void bnxt_cfg_ntp_filters(struct bnxt *bp) | |
11616 | { | |
11617 | } | |
11618 | ||
11619 | #endif /* CONFIG_RFS_ACCEL */ | |
11620 | ||
442a35a5 | 11621 | static int bnxt_udp_tunnel_sync(struct net_device *netdev, unsigned int table) |
c0c050c5 | 11622 | { |
442a35a5 JK |
11623 | struct bnxt *bp = netdev_priv(netdev); |
11624 | struct udp_tunnel_info ti; | |
11625 | unsigned int cmd; | |
c0c050c5 | 11626 | |
442a35a5 JK |
11627 | udp_tunnel_nic_get_port(netdev, table, 0, &ti); |
11628 | if (ti.type == UDP_TUNNEL_TYPE_VXLAN) | |
11629 | cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN; | |
11630 | else | |
11631 | cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE; | |
7cdd5fc3 | 11632 | |
442a35a5 JK |
11633 | if (ti.port) |
11634 | return bnxt_hwrm_tunnel_dst_port_alloc(bp, ti.port, cmd); | |
ad51b8e9 | 11635 | |
442a35a5 | 11636 | return bnxt_hwrm_tunnel_dst_port_free(bp, cmd); |
c0c050c5 MC |
11637 | } |
11638 | ||
442a35a5 JK |
11639 | static const struct udp_tunnel_nic_info bnxt_udp_tunnels = { |
11640 | .sync_table = bnxt_udp_tunnel_sync, | |
11641 | .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP | | |
11642 | UDP_TUNNEL_NIC_INFO_OPEN_ONLY, | |
11643 | .tables = { | |
11644 | { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, | |
11645 | { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, }, | |
11646 | }, | |
11647 | }; | |
c0c050c5 | 11648 | |
39d8ba2e MC |
11649 | static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, |
11650 | struct net_device *dev, u32 filter_mask, | |
11651 | int nlflags) | |
11652 | { | |
11653 | struct bnxt *bp = netdev_priv(dev); | |
11654 | ||
11655 | return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0, | |
11656 | nlflags, filter_mask, NULL); | |
11657 | } | |
11658 | ||
11659 | static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, | |
2fd527b7 | 11660 | u16 flags, struct netlink_ext_ack *extack) |
39d8ba2e MC |
11661 | { |
11662 | struct bnxt *bp = netdev_priv(dev); | |
11663 | struct nlattr *attr, *br_spec; | |
11664 | int rem, rc = 0; | |
11665 | ||
11666 | if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp)) | |
11667 | return -EOPNOTSUPP; | |
11668 | ||
11669 | br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); | |
11670 | if (!br_spec) | |
11671 | return -EINVAL; | |
11672 | ||
11673 | nla_for_each_nested(attr, br_spec, rem) { | |
11674 | u16 mode; | |
11675 | ||
11676 | if (nla_type(attr) != IFLA_BRIDGE_MODE) | |
11677 | continue; | |
11678 | ||
11679 | if (nla_len(attr) < sizeof(mode)) | |
11680 | return -EINVAL; | |
11681 | ||
11682 | mode = nla_get_u16(attr); | |
11683 | if (mode == bp->br_mode) | |
11684 | break; | |
11685 | ||
11686 | rc = bnxt_hwrm_set_br_mode(bp, mode); | |
11687 | if (!rc) | |
11688 | bp->br_mode = mode; | |
11689 | break; | |
11690 | } | |
11691 | return rc; | |
11692 | } | |
11693 | ||
52d5254a FF |
11694 | int bnxt_get_port_parent_id(struct net_device *dev, |
11695 | struct netdev_phys_item_id *ppid) | |
c124a62f | 11696 | { |
52d5254a FF |
11697 | struct bnxt *bp = netdev_priv(dev); |
11698 | ||
c124a62f SP |
11699 | if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV) |
11700 | return -EOPNOTSUPP; | |
11701 | ||
11702 | /* The PF and it's VF-reps only support the switchdev framework */ | |
d061b241 | 11703 | if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_DSN_VALID)) |
c124a62f SP |
11704 | return -EOPNOTSUPP; |
11705 | ||
b014232f VV |
11706 | ppid->id_len = sizeof(bp->dsn); |
11707 | memcpy(ppid->id, bp->dsn, ppid->id_len); | |
c124a62f | 11708 | |
52d5254a | 11709 | return 0; |
c124a62f SP |
11710 | } |
11711 | ||
c9c49a65 JP |
11712 | static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev) |
11713 | { | |
11714 | struct bnxt *bp = netdev_priv(dev); | |
11715 | ||
11716 | return &bp->dl_port; | |
11717 | } | |
11718 | ||
c0c050c5 MC |
11719 | static const struct net_device_ops bnxt_netdev_ops = { |
11720 | .ndo_open = bnxt_open, | |
11721 | .ndo_start_xmit = bnxt_start_xmit, | |
11722 | .ndo_stop = bnxt_close, | |
11723 | .ndo_get_stats64 = bnxt_get_stats64, | |
11724 | .ndo_set_rx_mode = bnxt_set_rx_mode, | |
11725 | .ndo_do_ioctl = bnxt_ioctl, | |
11726 | .ndo_validate_addr = eth_validate_addr, | |
11727 | .ndo_set_mac_address = bnxt_change_mac_addr, | |
11728 | .ndo_change_mtu = bnxt_change_mtu, | |
11729 | .ndo_fix_features = bnxt_fix_features, | |
11730 | .ndo_set_features = bnxt_set_features, | |
11731 | .ndo_tx_timeout = bnxt_tx_timeout, | |
11732 | #ifdef CONFIG_BNXT_SRIOV | |
11733 | .ndo_get_vf_config = bnxt_get_vf_config, | |
11734 | .ndo_set_vf_mac = bnxt_set_vf_mac, | |
11735 | .ndo_set_vf_vlan = bnxt_set_vf_vlan, | |
11736 | .ndo_set_vf_rate = bnxt_set_vf_bw, | |
11737 | .ndo_set_vf_link_state = bnxt_set_vf_link_state, | |
11738 | .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, | |
746df139 | 11739 | .ndo_set_vf_trust = bnxt_set_vf_trust, |
c0c050c5 MC |
11740 | #endif |
11741 | .ndo_setup_tc = bnxt_setup_tc, | |
11742 | #ifdef CONFIG_RFS_ACCEL | |
11743 | .ndo_rx_flow_steer = bnxt_rx_flow_steer, | |
11744 | #endif | |
442a35a5 JK |
11745 | .ndo_udp_tunnel_add = udp_tunnel_nic_add_port, |
11746 | .ndo_udp_tunnel_del = udp_tunnel_nic_del_port, | |
f4e63525 | 11747 | .ndo_bpf = bnxt_xdp, |
f18c2b77 | 11748 | .ndo_xdp_xmit = bnxt_xdp_xmit, |
39d8ba2e MC |
11749 | .ndo_bridge_getlink = bnxt_bridge_getlink, |
11750 | .ndo_bridge_setlink = bnxt_bridge_setlink, | |
c9c49a65 | 11751 | .ndo_get_devlink_port = bnxt_get_devlink_port, |
c0c050c5 MC |
11752 | }; |
11753 | ||
11754 | static void bnxt_remove_one(struct pci_dev *pdev) | |
11755 | { | |
11756 | struct net_device *dev = pci_get_drvdata(pdev); | |
11757 | struct bnxt *bp = netdev_priv(dev); | |
11758 | ||
7e334fc8 | 11759 | if (BNXT_PF(bp)) |
c0c050c5 MC |
11760 | bnxt_sriov_disable(bp); |
11761 | ||
7e334fc8 | 11762 | bnxt_dl_fw_reporters_destroy(bp, true); |
0fcfc7a1 VV |
11763 | if (BNXT_PF(bp)) |
11764 | devlink_port_type_clear(&bp->dl_port); | |
6316ea6d | 11765 | pci_disable_pcie_error_reporting(pdev); |
c0c050c5 | 11766 | unregister_netdev(dev); |
cda2cab0 | 11767 | bnxt_dl_unregister(bp); |
2ae7408f | 11768 | bnxt_shutdown_tc(bp); |
b148bb23 | 11769 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); |
c213eae8 | 11770 | bnxt_cancel_sp_work(bp); |
c0c050c5 MC |
11771 | bp->sp_event = 0; |
11772 | ||
7809592d | 11773 | bnxt_clear_int_mode(bp); |
be58a0da | 11774 | bnxt_hwrm_func_drv_unrgtr(bp); |
c0c050c5 | 11775 | bnxt_free_hwrm_resources(bp); |
e605db80 | 11776 | bnxt_free_hwrm_short_cmd_req(bp); |
eb513658 | 11777 | bnxt_ethtool_free(bp); |
7df4ae9f | 11778 | bnxt_dcb_free(bp); |
a588e458 MC |
11779 | kfree(bp->edev); |
11780 | bp->edev = NULL; | |
8280b38e VV |
11781 | kfree(bp->fw_health); |
11782 | bp->fw_health = NULL; | |
c20dc142 | 11783 | bnxt_cleanup_pci(bp); |
98f04cf0 MC |
11784 | bnxt_free_ctx_mem(bp); |
11785 | kfree(bp->ctx); | |
11786 | bp->ctx = NULL; | |
1667cbf6 MC |
11787 | kfree(bp->rss_indir_tbl); |
11788 | bp->rss_indir_tbl = NULL; | |
fd3ab1c7 | 11789 | bnxt_free_port_stats(bp); |
c0c050c5 | 11790 | free_netdev(dev); |
c0c050c5 MC |
11791 | } |
11792 | ||
ba642ab7 | 11793 | static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt) |
c0c050c5 MC |
11794 | { |
11795 | int rc = 0; | |
11796 | struct bnxt_link_info *link_info = &bp->link_info; | |
c0c050c5 | 11797 | |
170ce013 MC |
11798 | rc = bnxt_hwrm_phy_qcaps(bp); |
11799 | if (rc) { | |
11800 | netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n", | |
11801 | rc); | |
11802 | return rc; | |
11803 | } | |
43a5107d MC |
11804 | if (!fw_dflt) |
11805 | return 0; | |
11806 | ||
c0c050c5 MC |
11807 | rc = bnxt_update_link(bp, false); |
11808 | if (rc) { | |
11809 | netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", | |
11810 | rc); | |
11811 | return rc; | |
11812 | } | |
11813 | ||
93ed8117 MC |
11814 | /* Older firmware does not have supported_auto_speeds, so assume |
11815 | * that all supported speeds can be autonegotiated. | |
11816 | */ | |
11817 | if (link_info->auto_link_speeds && !link_info->support_auto_speeds) | |
11818 | link_info->support_auto_speeds = link_info->support_speeds; | |
11819 | ||
8119e49b | 11820 | bnxt_init_ethtool_link_settings(bp); |
ba642ab7 | 11821 | return 0; |
c0c050c5 MC |
11822 | } |
11823 | ||
11824 | static int bnxt_get_max_irq(struct pci_dev *pdev) | |
11825 | { | |
11826 | u16 ctrl; | |
11827 | ||
11828 | if (!pdev->msix_cap) | |
11829 | return 1; | |
11830 | ||
11831 | pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); | |
11832 | return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; | |
11833 | } | |
11834 | ||
6e6c5a57 MC |
11835 | static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, |
11836 | int *max_cp) | |
c0c050c5 | 11837 | { |
6a4f2947 | 11838 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; |
e30fbc33 | 11839 | int max_ring_grps = 0, max_irq; |
c0c050c5 | 11840 | |
6a4f2947 MC |
11841 | *max_tx = hw_resc->max_tx_rings; |
11842 | *max_rx = hw_resc->max_rx_rings; | |
e30fbc33 MC |
11843 | *max_cp = bnxt_get_max_func_cp_rings_for_en(bp); |
11844 | max_irq = min_t(int, bnxt_get_max_func_irqs(bp) - | |
11845 | bnxt_get_ulp_msix_num(bp), | |
c027c6b4 | 11846 | hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp)); |
e30fbc33 MC |
11847 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) |
11848 | *max_cp = min_t(int, *max_cp, max_irq); | |
6a4f2947 | 11849 | max_ring_grps = hw_resc->max_hw_ring_grps; |
76595193 PS |
11850 | if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) { |
11851 | *max_cp -= 1; | |
11852 | *max_rx -= 2; | |
11853 | } | |
c0c050c5 MC |
11854 | if (bp->flags & BNXT_FLAG_AGG_RINGS) |
11855 | *max_rx >>= 1; | |
e30fbc33 MC |
11856 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
11857 | bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false); | |
11858 | /* On P5 chips, max_cp output param should be available NQs */ | |
11859 | *max_cp = max_irq; | |
11860 | } | |
b72d4a68 | 11861 | *max_rx = min_t(int, *max_rx, max_ring_grps); |
6e6c5a57 MC |
11862 | } |
11863 | ||
11864 | int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) | |
11865 | { | |
11866 | int rx, tx, cp; | |
11867 | ||
11868 | _bnxt_get_max_rings(bp, &rx, &tx, &cp); | |
78f058a4 MC |
11869 | *max_rx = rx; |
11870 | *max_tx = tx; | |
6e6c5a57 MC |
11871 | if (!rx || !tx || !cp) |
11872 | return -ENOMEM; | |
11873 | ||
6e6c5a57 MC |
11874 | return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); |
11875 | } | |
11876 | ||
e4060d30 MC |
11877 | static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx, |
11878 | bool shared) | |
11879 | { | |
11880 | int rc; | |
11881 | ||
11882 | rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); | |
bdbd1eb5 MC |
11883 | if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) { |
11884 | /* Not enough rings, try disabling agg rings. */ | |
11885 | bp->flags &= ~BNXT_FLAG_AGG_RINGS; | |
11886 | rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); | |
07f4fde5 MC |
11887 | if (rc) { |
11888 | /* set BNXT_FLAG_AGG_RINGS back for consistency */ | |
11889 | bp->flags |= BNXT_FLAG_AGG_RINGS; | |
bdbd1eb5 | 11890 | return rc; |
07f4fde5 | 11891 | } |
bdbd1eb5 | 11892 | bp->flags |= BNXT_FLAG_NO_AGG_RINGS; |
1054aee8 MC |
11893 | bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); |
11894 | bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); | |
bdbd1eb5 MC |
11895 | bnxt_set_ring_params(bp); |
11896 | } | |
e4060d30 MC |
11897 | |
11898 | if (bp->flags & BNXT_FLAG_ROCE_CAP) { | |
11899 | int max_cp, max_stat, max_irq; | |
11900 | ||
11901 | /* Reserve minimum resources for RoCE */ | |
11902 | max_cp = bnxt_get_max_func_cp_rings(bp); | |
11903 | max_stat = bnxt_get_max_func_stat_ctxs(bp); | |
11904 | max_irq = bnxt_get_max_func_irqs(bp); | |
11905 | if (max_cp <= BNXT_MIN_ROCE_CP_RINGS || | |
11906 | max_irq <= BNXT_MIN_ROCE_CP_RINGS || | |
11907 | max_stat <= BNXT_MIN_ROCE_STAT_CTXS) | |
11908 | return 0; | |
11909 | ||
11910 | max_cp -= BNXT_MIN_ROCE_CP_RINGS; | |
11911 | max_irq -= BNXT_MIN_ROCE_CP_RINGS; | |
11912 | max_stat -= BNXT_MIN_ROCE_STAT_CTXS; | |
11913 | max_cp = min_t(int, max_cp, max_irq); | |
11914 | max_cp = min_t(int, max_cp, max_stat); | |
11915 | rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared); | |
11916 | if (rc) | |
11917 | rc = 0; | |
11918 | } | |
11919 | return rc; | |
11920 | } | |
11921 | ||
58ea801a MC |
11922 | /* In initial default shared ring setting, each shared ring must have a |
11923 | * RX/TX ring pair. | |
11924 | */ | |
11925 | static void bnxt_trim_dflt_sh_rings(struct bnxt *bp) | |
11926 | { | |
11927 | bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings); | |
11928 | bp->rx_nr_rings = bp->cp_nr_rings; | |
11929 | bp->tx_nr_rings_per_tc = bp->cp_nr_rings; | |
11930 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc; | |
11931 | } | |
11932 | ||
702c221c | 11933 | static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh) |
6e6c5a57 MC |
11934 | { |
11935 | int dflt_rings, max_rx_rings, max_tx_rings, rc; | |
6e6c5a57 | 11936 | |
2773dfb2 MC |
11937 | if (!bnxt_can_reserve_rings(bp)) |
11938 | return 0; | |
11939 | ||
6e6c5a57 MC |
11940 | if (sh) |
11941 | bp->flags |= BNXT_FLAG_SHARED_RINGS; | |
d629522e | 11942 | dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues(); |
1d3ef13d MC |
11943 | /* Reduce default rings on multi-port cards so that total default |
11944 | * rings do not exceed CPU count. | |
11945 | */ | |
11946 | if (bp->port_count > 1) { | |
11947 | int max_rings = | |
11948 | max_t(int, num_online_cpus() / bp->port_count, 1); | |
11949 | ||
11950 | dflt_rings = min_t(int, dflt_rings, max_rings); | |
11951 | } | |
e4060d30 | 11952 | rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh); |
6e6c5a57 MC |
11953 | if (rc) |
11954 | return rc; | |
11955 | bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); | |
11956 | bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); | |
58ea801a MC |
11957 | if (sh) |
11958 | bnxt_trim_dflt_sh_rings(bp); | |
11959 | else | |
11960 | bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings; | |
11961 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc; | |
391be5c2 | 11962 | |
674f50a5 | 11963 | rc = __bnxt_reserve_rings(bp); |
391be5c2 MC |
11964 | if (rc) |
11965 | netdev_warn(bp->dev, "Unable to reserve tx rings\n"); | |
58ea801a MC |
11966 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; |
11967 | if (sh) | |
11968 | bnxt_trim_dflt_sh_rings(bp); | |
391be5c2 | 11969 | |
674f50a5 MC |
11970 | /* Rings may have been trimmed, re-reserve the trimmed rings. */ |
11971 | if (bnxt_need_reserve_rings(bp)) { | |
11972 | rc = __bnxt_reserve_rings(bp); | |
11973 | if (rc) | |
11974 | netdev_warn(bp->dev, "2nd rings reservation failed.\n"); | |
11975 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; | |
11976 | } | |
76595193 PS |
11977 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { |
11978 | bp->rx_nr_rings++; | |
11979 | bp->cp_nr_rings++; | |
11980 | } | |
5d765a5e VV |
11981 | if (rc) { |
11982 | bp->tx_nr_rings = 0; | |
11983 | bp->rx_nr_rings = 0; | |
11984 | } | |
6e6c5a57 | 11985 | return rc; |
c0c050c5 MC |
11986 | } |
11987 | ||
47558acd MC |
11988 | static int bnxt_init_dflt_ring_mode(struct bnxt *bp) |
11989 | { | |
11990 | int rc; | |
11991 | ||
11992 | if (bp->tx_nr_rings) | |
11993 | return 0; | |
11994 | ||
6b95c3e9 MC |
11995 | bnxt_ulp_irq_stop(bp); |
11996 | bnxt_clear_int_mode(bp); | |
47558acd MC |
11997 | rc = bnxt_set_dflt_rings(bp, true); |
11998 | if (rc) { | |
11999 | netdev_err(bp->dev, "Not enough rings available.\n"); | |
6b95c3e9 | 12000 | goto init_dflt_ring_err; |
47558acd MC |
12001 | } |
12002 | rc = bnxt_init_int_mode(bp); | |
12003 | if (rc) | |
6b95c3e9 MC |
12004 | goto init_dflt_ring_err; |
12005 | ||
47558acd MC |
12006 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; |
12007 | if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) { | |
12008 | bp->flags |= BNXT_FLAG_RFS; | |
12009 | bp->dev->features |= NETIF_F_NTUPLE; | |
12010 | } | |
6b95c3e9 MC |
12011 | init_dflt_ring_err: |
12012 | bnxt_ulp_irq_restart(bp, rc); | |
12013 | return rc; | |
47558acd MC |
12014 | } |
12015 | ||
80fcaf46 | 12016 | int bnxt_restore_pf_fw_resources(struct bnxt *bp) |
7b08f661 | 12017 | { |
80fcaf46 MC |
12018 | int rc; |
12019 | ||
7b08f661 MC |
12020 | ASSERT_RTNL(); |
12021 | bnxt_hwrm_func_qcaps(bp); | |
1a037782 VD |
12022 | |
12023 | if (netif_running(bp->dev)) | |
12024 | __bnxt_close_nic(bp, true, false); | |
12025 | ||
ec86f14e | 12026 | bnxt_ulp_irq_stop(bp); |
80fcaf46 MC |
12027 | bnxt_clear_int_mode(bp); |
12028 | rc = bnxt_init_int_mode(bp); | |
ec86f14e | 12029 | bnxt_ulp_irq_restart(bp, rc); |
1a037782 VD |
12030 | |
12031 | if (netif_running(bp->dev)) { | |
12032 | if (rc) | |
12033 | dev_close(bp->dev); | |
12034 | else | |
12035 | rc = bnxt_open_nic(bp, true, false); | |
12036 | } | |
12037 | ||
80fcaf46 | 12038 | return rc; |
7b08f661 MC |
12039 | } |
12040 | ||
a22a6ac2 MC |
12041 | static int bnxt_init_mac_addr(struct bnxt *bp) |
12042 | { | |
12043 | int rc = 0; | |
12044 | ||
12045 | if (BNXT_PF(bp)) { | |
12046 | memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN); | |
12047 | } else { | |
12048 | #ifdef CONFIG_BNXT_SRIOV | |
12049 | struct bnxt_vf_info *vf = &bp->vf; | |
28ea334b | 12050 | bool strict_approval = true; |
a22a6ac2 MC |
12051 | |
12052 | if (is_valid_ether_addr(vf->mac_addr)) { | |
91cdda40 | 12053 | /* overwrite netdev dev_addr with admin VF MAC */ |
a22a6ac2 | 12054 | memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN); |
28ea334b MC |
12055 | /* Older PF driver or firmware may not approve this |
12056 | * correctly. | |
12057 | */ | |
12058 | strict_approval = false; | |
a22a6ac2 MC |
12059 | } else { |
12060 | eth_hw_addr_random(bp->dev); | |
a22a6ac2 | 12061 | } |
28ea334b | 12062 | rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval); |
a22a6ac2 MC |
12063 | #endif |
12064 | } | |
12065 | return rc; | |
12066 | } | |
12067 | ||
a0d0fd70 VV |
12068 | #define BNXT_VPD_LEN 512 |
12069 | static void bnxt_vpd_read_info(struct bnxt *bp) | |
12070 | { | |
12071 | struct pci_dev *pdev = bp->pdev; | |
12072 | int i, len, pos, ro_size; | |
12073 | ssize_t vpd_size; | |
12074 | u8 *vpd_data; | |
12075 | ||
12076 | vpd_data = kmalloc(BNXT_VPD_LEN, GFP_KERNEL); | |
12077 | if (!vpd_data) | |
12078 | return; | |
12079 | ||
12080 | vpd_size = pci_read_vpd(pdev, 0, BNXT_VPD_LEN, vpd_data); | |
12081 | if (vpd_size <= 0) { | |
12082 | netdev_err(bp->dev, "Unable to read VPD\n"); | |
12083 | goto exit; | |
12084 | } | |
12085 | ||
12086 | i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); | |
12087 | if (i < 0) { | |
12088 | netdev_err(bp->dev, "VPD READ-Only not found\n"); | |
12089 | goto exit; | |
12090 | } | |
12091 | ||
12092 | ro_size = pci_vpd_lrdt_size(&vpd_data[i]); | |
12093 | i += PCI_VPD_LRDT_TAG_SIZE; | |
12094 | if (i + ro_size > vpd_size) | |
12095 | goto exit; | |
12096 | ||
12097 | pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size, | |
12098 | PCI_VPD_RO_KEYWORD_PARTNO); | |
12099 | if (pos < 0) | |
12100 | goto read_sn; | |
12101 | ||
12102 | len = pci_vpd_info_field_size(&vpd_data[pos]); | |
12103 | pos += PCI_VPD_INFO_FLD_HDR_SIZE; | |
12104 | if (len + pos > vpd_size) | |
12105 | goto read_sn; | |
12106 | ||
12107 | strlcpy(bp->board_partno, &vpd_data[pos], min(len, BNXT_VPD_FLD_LEN)); | |
12108 | ||
12109 | read_sn: | |
12110 | pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size, | |
12111 | PCI_VPD_RO_KEYWORD_SERIALNO); | |
12112 | if (pos < 0) | |
12113 | goto exit; | |
12114 | ||
12115 | len = pci_vpd_info_field_size(&vpd_data[pos]); | |
12116 | pos += PCI_VPD_INFO_FLD_HDR_SIZE; | |
12117 | if (len + pos > vpd_size) | |
12118 | goto exit; | |
12119 | ||
12120 | strlcpy(bp->board_serialno, &vpd_data[pos], min(len, BNXT_VPD_FLD_LEN)); | |
12121 | exit: | |
12122 | kfree(vpd_data); | |
12123 | } | |
12124 | ||
03213a99 JP |
12125 | static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[]) |
12126 | { | |
12127 | struct pci_dev *pdev = bp->pdev; | |
8d85b75b | 12128 | u64 qword; |
03213a99 | 12129 | |
8d85b75b JK |
12130 | qword = pci_get_dsn(pdev); |
12131 | if (!qword) { | |
12132 | netdev_info(bp->dev, "Unable to read adapter's DSN\n"); | |
03213a99 JP |
12133 | return -EOPNOTSUPP; |
12134 | } | |
12135 | ||
8d85b75b JK |
12136 | put_unaligned_le64(qword, dsn); |
12137 | ||
d061b241 | 12138 | bp->flags |= BNXT_FLAG_DSN_VALID; |
03213a99 JP |
12139 | return 0; |
12140 | } | |
12141 | ||
8ae24738 MC |
12142 | static int bnxt_map_db_bar(struct bnxt *bp) |
12143 | { | |
12144 | if (!bp->db_size) | |
12145 | return -ENODEV; | |
12146 | bp->bar1 = pci_iomap(bp->pdev, 2, bp->db_size); | |
12147 | if (!bp->bar1) | |
12148 | return -ENOMEM; | |
12149 | return 0; | |
12150 | } | |
12151 | ||
c0c050c5 MC |
12152 | static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
12153 | { | |
c0c050c5 MC |
12154 | struct net_device *dev; |
12155 | struct bnxt *bp; | |
6e6c5a57 | 12156 | int rc, max_irqs; |
c0c050c5 | 12157 | |
4e00338a | 12158 | if (pci_is_bridge(pdev)) |
fa853dda PS |
12159 | return -ENODEV; |
12160 | ||
8743db4a VV |
12161 | /* Clear any pending DMA transactions from crash kernel |
12162 | * while loading driver in capture kernel. | |
12163 | */ | |
12164 | if (is_kdump_kernel()) { | |
12165 | pci_clear_master(pdev); | |
12166 | pcie_flr(pdev); | |
12167 | } | |
12168 | ||
c0c050c5 MC |
12169 | max_irqs = bnxt_get_max_irq(pdev); |
12170 | dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); | |
12171 | if (!dev) | |
12172 | return -ENOMEM; | |
12173 | ||
12174 | bp = netdev_priv(dev); | |
9c1fabdf | 12175 | bnxt_set_max_func_irqs(bp, max_irqs); |
c0c050c5 MC |
12176 | |
12177 | if (bnxt_vf_pciid(ent->driver_data)) | |
12178 | bp->flags |= BNXT_FLAG_VF; | |
12179 | ||
2bcfa6f6 | 12180 | if (pdev->msix_cap) |
c0c050c5 | 12181 | bp->flags |= BNXT_FLAG_MSIX_CAP; |
c0c050c5 MC |
12182 | |
12183 | rc = bnxt_init_board(pdev, dev); | |
12184 | if (rc < 0) | |
12185 | goto init_err_free; | |
12186 | ||
12187 | dev->netdev_ops = &bnxt_netdev_ops; | |
12188 | dev->watchdog_timeo = BNXT_TX_TIMEOUT; | |
12189 | dev->ethtool_ops = &bnxt_ethtool_ops; | |
c0c050c5 MC |
12190 | pci_set_drvdata(pdev, dev); |
12191 | ||
c55e28a8 VV |
12192 | if (BNXT_PF(bp)) |
12193 | bnxt_vpd_read_info(bp); | |
a0d0fd70 | 12194 | |
3e8060fa PS |
12195 | rc = bnxt_alloc_hwrm_resources(bp); |
12196 | if (rc) | |
17086399 | 12197 | goto init_err_pci_clean; |
3e8060fa PS |
12198 | |
12199 | mutex_init(&bp->hwrm_cmd_lock); | |
ba642ab7 | 12200 | mutex_init(&bp->link_lock); |
7c380918 MC |
12201 | |
12202 | rc = bnxt_fw_init_one_p1(bp); | |
3e8060fa | 12203 | if (rc) |
17086399 | 12204 | goto init_err_pci_clean; |
3e8060fa | 12205 | |
e38287b7 MC |
12206 | if (BNXT_CHIP_P5(bp)) |
12207 | bp->flags |= BNXT_FLAG_CHIP_P5; | |
12208 | ||
7c380918 | 12209 | rc = bnxt_fw_init_one_p2(bp); |
3c2217a6 MC |
12210 | if (rc) |
12211 | goto init_err_pci_clean; | |
12212 | ||
8ae24738 MC |
12213 | rc = bnxt_map_db_bar(bp); |
12214 | if (rc) { | |
12215 | dev_err(&pdev->dev, "Cannot map doorbell BAR rc = %d, aborting\n", | |
12216 | rc); | |
12217 | goto init_err_pci_clean; | |
12218 | } | |
12219 | ||
c0c050c5 MC |
12220 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | |
12221 | NETIF_F_TSO | NETIF_F_TSO6 | | |
12222 | NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | | |
7e13318d | 12223 | NETIF_F_GSO_IPXIP4 | |
152971ee AD |
12224 | NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | |
12225 | NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH | | |
3e8060fa PS |
12226 | NETIF_F_RXCSUM | NETIF_F_GRO; |
12227 | ||
e38287b7 | 12228 | if (BNXT_SUPPORTS_TPA(bp)) |
3e8060fa | 12229 | dev->hw_features |= NETIF_F_LRO; |
c0c050c5 | 12230 | |
c0c050c5 MC |
12231 | dev->hw_enc_features = |
12232 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | | |
12233 | NETIF_F_TSO | NETIF_F_TSO6 | | |
12234 | NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | | |
152971ee | 12235 | NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | |
7e13318d | 12236 | NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL; |
442a35a5 JK |
12237 | dev->udp_tunnel_nic_info = &bnxt_udp_tunnels; |
12238 | ||
152971ee AD |
12239 | dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM | |
12240 | NETIF_F_GSO_GRE_CSUM; | |
c0c050c5 | 12241 | dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; |
1da63ddd EP |
12242 | if (bp->fw_cap & BNXT_FW_CAP_VLAN_RX_STRIP) |
12243 | dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_RX; | |
12244 | if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT) | |
12245 | dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_TX; | |
e38287b7 | 12246 | if (BNXT_SUPPORTS_TPA(bp)) |
1054aee8 | 12247 | dev->hw_features |= NETIF_F_GRO_HW; |
c0c050c5 | 12248 | dev->features |= dev->hw_features | NETIF_F_HIGHDMA; |
1054aee8 MC |
12249 | if (dev->features & NETIF_F_GRO_HW) |
12250 | dev->features &= ~NETIF_F_LRO; | |
c0c050c5 MC |
12251 | dev->priv_flags |= IFF_UNICAST_FLT; |
12252 | ||
12253 | #ifdef CONFIG_BNXT_SRIOV | |
12254 | init_waitqueue_head(&bp->sriov_cfg_wait); | |
4ab0c6a8 | 12255 | mutex_init(&bp->sriov_lock); |
c0c050c5 | 12256 | #endif |
e38287b7 MC |
12257 | if (BNXT_SUPPORTS_TPA(bp)) { |
12258 | bp->gro_func = bnxt_gro_func_5730x; | |
67912c36 | 12259 | if (BNXT_CHIP_P4(bp)) |
e38287b7 | 12260 | bp->gro_func = bnxt_gro_func_5731x; |
67912c36 MC |
12261 | else if (BNXT_CHIP_P5(bp)) |
12262 | bp->gro_func = bnxt_gro_func_5750x; | |
e38287b7 MC |
12263 | } |
12264 | if (!BNXT_CHIP_P4_PLUS(bp)) | |
434c975a | 12265 | bp->flags |= BNXT_FLAG_DOUBLE_DB; |
309369c9 | 12266 | |
a588e458 MC |
12267 | bp->ulp_probe = bnxt_ulp_probe; |
12268 | ||
a22a6ac2 MC |
12269 | rc = bnxt_init_mac_addr(bp); |
12270 | if (rc) { | |
12271 | dev_err(&pdev->dev, "Unable to initialize mac address.\n"); | |
12272 | rc = -EADDRNOTAVAIL; | |
12273 | goto init_err_pci_clean; | |
12274 | } | |
c0c050c5 | 12275 | |
2e9217d1 VV |
12276 | if (BNXT_PF(bp)) { |
12277 | /* Read the adapter's DSN to use as the eswitch switch_id */ | |
b014232f | 12278 | rc = bnxt_pcie_dsn_get(bp, bp->dsn); |
2e9217d1 | 12279 | } |
567b2abe | 12280 | |
7eb9bb3a MC |
12281 | /* MTU range: 60 - FW defined max */ |
12282 | dev->min_mtu = ETH_ZLEN; | |
12283 | dev->max_mtu = bp->max_mtu; | |
12284 | ||
ba642ab7 | 12285 | rc = bnxt_probe_phy(bp, true); |
d5430d31 MC |
12286 | if (rc) |
12287 | goto init_err_pci_clean; | |
12288 | ||
c61fb99c | 12289 | bnxt_set_rx_skb_mode(bp, false); |
c0c050c5 MC |
12290 | bnxt_set_tpa_flags(bp); |
12291 | bnxt_set_ring_params(bp); | |
702c221c | 12292 | rc = bnxt_set_dflt_rings(bp, true); |
bdbd1eb5 MC |
12293 | if (rc) { |
12294 | netdev_err(bp->dev, "Not enough rings available.\n"); | |
12295 | rc = -ENOMEM; | |
17086399 | 12296 | goto init_err_pci_clean; |
bdbd1eb5 | 12297 | } |
c0c050c5 | 12298 | |
ba642ab7 | 12299 | bnxt_fw_init_one_p3(bp); |
2bcfa6f6 | 12300 | |
a196e96b | 12301 | if (dev->hw_features & BNXT_HW_FEATURE_VLAN_ALL_RX) |
c0c050c5 MC |
12302 | bp->flags |= BNXT_FLAG_STRIP_VLAN; |
12303 | ||
7809592d | 12304 | rc = bnxt_init_int_mode(bp); |
c0c050c5 | 12305 | if (rc) |
17086399 | 12306 | goto init_err_pci_clean; |
c0c050c5 | 12307 | |
832aed16 MC |
12308 | /* No TC has been set yet and rings may have been trimmed due to |
12309 | * limited MSIX, so we re-initialize the TX rings per TC. | |
12310 | */ | |
12311 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; | |
12312 | ||
1667cbf6 MC |
12313 | rc = bnxt_alloc_rss_indir_tbl(bp); |
12314 | if (rc) | |
12315 | goto init_err_pci_clean; | |
12316 | bnxt_set_dflt_rss_indir_tbl(bp); | |
12317 | ||
c213eae8 MC |
12318 | if (BNXT_PF(bp)) { |
12319 | if (!bnxt_pf_wq) { | |
12320 | bnxt_pf_wq = | |
12321 | create_singlethread_workqueue("bnxt_pf_wq"); | |
12322 | if (!bnxt_pf_wq) { | |
12323 | dev_err(&pdev->dev, "Unable to create workqueue.\n"); | |
12324 | goto init_err_pci_clean; | |
12325 | } | |
12326 | } | |
18c7015c JK |
12327 | rc = bnxt_init_tc(bp); |
12328 | if (rc) | |
12329 | netdev_err(dev, "Failed to initialize TC flower offload, err = %d.\n", | |
12330 | rc); | |
c213eae8 | 12331 | } |
2ae7408f | 12332 | |
cda2cab0 VV |
12333 | bnxt_dl_register(bp); |
12334 | ||
7809592d MC |
12335 | rc = register_netdev(dev); |
12336 | if (rc) | |
cda2cab0 | 12337 | goto init_err_cleanup; |
7809592d | 12338 | |
cda2cab0 VV |
12339 | if (BNXT_PF(bp)) |
12340 | devlink_port_type_eth_set(&bp->dl_port, bp->dev); | |
7e334fc8 | 12341 | bnxt_dl_fw_reporters_create(bp); |
4ab0c6a8 | 12342 | |
c0c050c5 MC |
12343 | netdev_info(dev, "%s found at mem %lx, node addr %pM\n", |
12344 | board_info[ent->driver_data].name, | |
12345 | (long)pci_resource_start(pdev, 0), dev->dev_addr); | |
af125b75 | 12346 | pcie_print_link_status(pdev); |
90c4f788 | 12347 | |
df3875ec | 12348 | pci_save_state(pdev); |
c0c050c5 MC |
12349 | return 0; |
12350 | ||
cda2cab0 VV |
12351 | init_err_cleanup: |
12352 | bnxt_dl_unregister(bp); | |
2ae7408f | 12353 | bnxt_shutdown_tc(bp); |
7809592d MC |
12354 | bnxt_clear_int_mode(bp); |
12355 | ||
17086399 | 12356 | init_err_pci_clean: |
bdb38602 | 12357 | bnxt_hwrm_func_drv_unrgtr(bp); |
f9099d61 | 12358 | bnxt_free_hwrm_short_cmd_req(bp); |
a2bf74f4 | 12359 | bnxt_free_hwrm_resources(bp); |
07f83d72 MC |
12360 | kfree(bp->fw_health); |
12361 | bp->fw_health = NULL; | |
17086399 | 12362 | bnxt_cleanup_pci(bp); |
62bfb932 MC |
12363 | bnxt_free_ctx_mem(bp); |
12364 | kfree(bp->ctx); | |
12365 | bp->ctx = NULL; | |
1667cbf6 MC |
12366 | kfree(bp->rss_indir_tbl); |
12367 | bp->rss_indir_tbl = NULL; | |
c0c050c5 MC |
12368 | |
12369 | init_err_free: | |
12370 | free_netdev(dev); | |
12371 | return rc; | |
12372 | } | |
12373 | ||
d196ece7 MC |
12374 | static void bnxt_shutdown(struct pci_dev *pdev) |
12375 | { | |
12376 | struct net_device *dev = pci_get_drvdata(pdev); | |
12377 | struct bnxt *bp; | |
12378 | ||
12379 | if (!dev) | |
12380 | return; | |
12381 | ||
12382 | rtnl_lock(); | |
12383 | bp = netdev_priv(dev); | |
12384 | if (!bp) | |
12385 | goto shutdown_exit; | |
12386 | ||
12387 | if (netif_running(dev)) | |
12388 | dev_close(dev); | |
12389 | ||
a7f3f939 | 12390 | bnxt_ulp_shutdown(bp); |
5567ae4a VV |
12391 | bnxt_clear_int_mode(bp); |
12392 | pci_disable_device(pdev); | |
a7f3f939 | 12393 | |
d196ece7 | 12394 | if (system_state == SYSTEM_POWER_OFF) { |
d196ece7 MC |
12395 | pci_wake_from_d3(pdev, bp->wol); |
12396 | pci_set_power_state(pdev, PCI_D3hot); | |
12397 | } | |
12398 | ||
12399 | shutdown_exit: | |
12400 | rtnl_unlock(); | |
12401 | } | |
12402 | ||
f65a2044 MC |
12403 | #ifdef CONFIG_PM_SLEEP |
12404 | static int bnxt_suspend(struct device *device) | |
12405 | { | |
f521eaa9 | 12406 | struct net_device *dev = dev_get_drvdata(device); |
f65a2044 MC |
12407 | struct bnxt *bp = netdev_priv(dev); |
12408 | int rc = 0; | |
12409 | ||
12410 | rtnl_lock(); | |
6a68749d | 12411 | bnxt_ulp_stop(bp); |
f65a2044 MC |
12412 | if (netif_running(dev)) { |
12413 | netif_device_detach(dev); | |
12414 | rc = bnxt_close(dev); | |
12415 | } | |
12416 | bnxt_hwrm_func_drv_unrgtr(bp); | |
ef02af8c | 12417 | pci_disable_device(bp->pdev); |
f9b69d7f VV |
12418 | bnxt_free_ctx_mem(bp); |
12419 | kfree(bp->ctx); | |
12420 | bp->ctx = NULL; | |
f65a2044 MC |
12421 | rtnl_unlock(); |
12422 | return rc; | |
12423 | } | |
12424 | ||
12425 | static int bnxt_resume(struct device *device) | |
12426 | { | |
f521eaa9 | 12427 | struct net_device *dev = dev_get_drvdata(device); |
f65a2044 MC |
12428 | struct bnxt *bp = netdev_priv(dev); |
12429 | int rc = 0; | |
12430 | ||
12431 | rtnl_lock(); | |
ef02af8c MC |
12432 | rc = pci_enable_device(bp->pdev); |
12433 | if (rc) { | |
12434 | netdev_err(dev, "Cannot re-enable PCI device during resume, err = %d\n", | |
12435 | rc); | |
12436 | goto resume_exit; | |
12437 | } | |
12438 | pci_set_master(bp->pdev); | |
f92335d8 | 12439 | if (bnxt_hwrm_ver_get(bp)) { |
f65a2044 MC |
12440 | rc = -ENODEV; |
12441 | goto resume_exit; | |
12442 | } | |
12443 | rc = bnxt_hwrm_func_reset(bp); | |
12444 | if (rc) { | |
12445 | rc = -EBUSY; | |
12446 | goto resume_exit; | |
12447 | } | |
f92335d8 | 12448 | |
2084ccf6 MC |
12449 | rc = bnxt_hwrm_func_qcaps(bp); |
12450 | if (rc) | |
f9b69d7f | 12451 | goto resume_exit; |
f92335d8 VV |
12452 | |
12453 | if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) { | |
12454 | rc = -ENODEV; | |
12455 | goto resume_exit; | |
12456 | } | |
12457 | ||
f65a2044 MC |
12458 | bnxt_get_wol_settings(bp); |
12459 | if (netif_running(dev)) { | |
12460 | rc = bnxt_open(dev); | |
12461 | if (!rc) | |
12462 | netif_device_attach(dev); | |
12463 | } | |
12464 | ||
12465 | resume_exit: | |
6a68749d | 12466 | bnxt_ulp_start(bp, rc); |
59ae2101 MC |
12467 | if (!rc) |
12468 | bnxt_reenable_sriov(bp); | |
f65a2044 MC |
12469 | rtnl_unlock(); |
12470 | return rc; | |
12471 | } | |
12472 | ||
12473 | static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume); | |
12474 | #define BNXT_PM_OPS (&bnxt_pm_ops) | |
12475 | ||
12476 | #else | |
12477 | ||
12478 | #define BNXT_PM_OPS NULL | |
12479 | ||
12480 | #endif /* CONFIG_PM_SLEEP */ | |
12481 | ||
6316ea6d SB |
12482 | /** |
12483 | * bnxt_io_error_detected - called when PCI error is detected | |
12484 | * @pdev: Pointer to PCI device | |
12485 | * @state: The current pci connection state | |
12486 | * | |
12487 | * This function is called after a PCI bus error affecting | |
12488 | * this device has been detected. | |
12489 | */ | |
12490 | static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev, | |
12491 | pci_channel_state_t state) | |
12492 | { | |
12493 | struct net_device *netdev = pci_get_drvdata(pdev); | |
a588e458 | 12494 | struct bnxt *bp = netdev_priv(netdev); |
6316ea6d SB |
12495 | |
12496 | netdev_info(netdev, "PCI I/O error detected\n"); | |
12497 | ||
12498 | rtnl_lock(); | |
12499 | netif_device_detach(netdev); | |
12500 | ||
a588e458 MC |
12501 | bnxt_ulp_stop(bp); |
12502 | ||
6316ea6d SB |
12503 | if (state == pci_channel_io_perm_failure) { |
12504 | rtnl_unlock(); | |
12505 | return PCI_ERS_RESULT_DISCONNECT; | |
12506 | } | |
12507 | ||
12508 | if (netif_running(netdev)) | |
12509 | bnxt_close(netdev); | |
12510 | ||
12511 | pci_disable_device(pdev); | |
6e2f8388 MC |
12512 | bnxt_free_ctx_mem(bp); |
12513 | kfree(bp->ctx); | |
12514 | bp->ctx = NULL; | |
6316ea6d SB |
12515 | rtnl_unlock(); |
12516 | ||
12517 | /* Request a slot slot reset. */ | |
12518 | return PCI_ERS_RESULT_NEED_RESET; | |
12519 | } | |
12520 | ||
12521 | /** | |
12522 | * bnxt_io_slot_reset - called after the pci bus has been reset. | |
12523 | * @pdev: Pointer to PCI device | |
12524 | * | |
12525 | * Restart the card from scratch, as if from a cold-boot. | |
12526 | * At this point, the card has exprienced a hard reset, | |
12527 | * followed by fixups by BIOS, and has its config space | |
12528 | * set up identically to what it was at cold boot. | |
12529 | */ | |
12530 | static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) | |
12531 | { | |
12532 | struct net_device *netdev = pci_get_drvdata(pdev); | |
12533 | struct bnxt *bp = netdev_priv(netdev); | |
12534 | int err = 0; | |
12535 | pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; | |
12536 | ||
12537 | netdev_info(bp->dev, "PCI Slot Reset\n"); | |
12538 | ||
12539 | rtnl_lock(); | |
12540 | ||
12541 | if (pci_enable_device(pdev)) { | |
12542 | dev_err(&pdev->dev, | |
12543 | "Cannot re-enable PCI device after reset.\n"); | |
12544 | } else { | |
12545 | pci_set_master(pdev); | |
df3875ec VV |
12546 | pci_restore_state(pdev); |
12547 | pci_save_state(pdev); | |
6316ea6d | 12548 | |
aa8ed021 | 12549 | err = bnxt_hwrm_func_reset(bp); |
6e2f8388 MC |
12550 | if (!err) { |
12551 | err = bnxt_hwrm_func_qcaps(bp); | |
12552 | if (!err && netif_running(netdev)) | |
12553 | err = bnxt_open(netdev); | |
12554 | } | |
aa46dfff | 12555 | bnxt_ulp_start(bp, err); |
6e2f8388 MC |
12556 | if (!err) { |
12557 | bnxt_reenable_sriov(bp); | |
12558 | result = PCI_ERS_RESULT_RECOVERED; | |
12559 | } | |
6316ea6d SB |
12560 | } |
12561 | ||
bae361c5 MC |
12562 | if (result != PCI_ERS_RESULT_RECOVERED) { |
12563 | if (netif_running(netdev)) | |
12564 | dev_close(netdev); | |
12565 | pci_disable_device(pdev); | |
12566 | } | |
6316ea6d SB |
12567 | |
12568 | rtnl_unlock(); | |
12569 | ||
bae361c5 | 12570 | return result; |
6316ea6d SB |
12571 | } |
12572 | ||
12573 | /** | |
12574 | * bnxt_io_resume - called when traffic can start flowing again. | |
12575 | * @pdev: Pointer to PCI device | |
12576 | * | |
12577 | * This callback is called when the error recovery driver tells | |
12578 | * us that its OK to resume normal operation. | |
12579 | */ | |
12580 | static void bnxt_io_resume(struct pci_dev *pdev) | |
12581 | { | |
12582 | struct net_device *netdev = pci_get_drvdata(pdev); | |
12583 | ||
12584 | rtnl_lock(); | |
12585 | ||
12586 | netif_device_attach(netdev); | |
12587 | ||
12588 | rtnl_unlock(); | |
12589 | } | |
12590 | ||
12591 | static const struct pci_error_handlers bnxt_err_handler = { | |
12592 | .error_detected = bnxt_io_error_detected, | |
12593 | .slot_reset = bnxt_io_slot_reset, | |
12594 | .resume = bnxt_io_resume | |
12595 | }; | |
12596 | ||
c0c050c5 MC |
12597 | static struct pci_driver bnxt_pci_driver = { |
12598 | .name = DRV_MODULE_NAME, | |
12599 | .id_table = bnxt_pci_tbl, | |
12600 | .probe = bnxt_init_one, | |
12601 | .remove = bnxt_remove_one, | |
d196ece7 | 12602 | .shutdown = bnxt_shutdown, |
f65a2044 | 12603 | .driver.pm = BNXT_PM_OPS, |
6316ea6d | 12604 | .err_handler = &bnxt_err_handler, |
c0c050c5 MC |
12605 | #if defined(CONFIG_BNXT_SRIOV) |
12606 | .sriov_configure = bnxt_sriov_configure, | |
12607 | #endif | |
12608 | }; | |
12609 | ||
c213eae8 MC |
12610 | static int __init bnxt_init(void) |
12611 | { | |
cabfb09d | 12612 | bnxt_debug_init(); |
c213eae8 MC |
12613 | return pci_register_driver(&bnxt_pci_driver); |
12614 | } | |
12615 | ||
12616 | static void __exit bnxt_exit(void) | |
12617 | { | |
12618 | pci_unregister_driver(&bnxt_pci_driver); | |
12619 | if (bnxt_pf_wq) | |
12620 | destroy_workqueue(bnxt_pf_wq); | |
cabfb09d | 12621 | bnxt_debug_exit(); |
c213eae8 MC |
12622 | } |
12623 | ||
12624 | module_init(bnxt_init); | |
12625 | module_exit(bnxt_exit); |