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c0c050c5 MC |
1 | /* Broadcom NetXtreme-C/E network driver. |
2 | * | |
11f15ed3 | 3 | * Copyright (c) 2014-2016 Broadcom Corporation |
bac9a7e0 | 4 | * Copyright (c) 2016-2017 Broadcom Limited |
c0c050c5 MC |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifndef BNXT_H | |
12 | #define BNXT_H | |
13 | ||
14 | #define DRV_MODULE_NAME "bnxt_en" | |
bac9a7e0 | 15 | #define DRV_MODULE_VERSION "1.7.0" |
c0c050c5 | 16 | |
c193554e | 17 | #define DRV_VER_MAJ 1 |
bac9a7e0 | 18 | #define DRV_VER_MIN 7 |
c193554e | 19 | #define DRV_VER_UPD 0 |
c0c050c5 | 20 | |
282ccf6e FW |
21 | #include <linux/interrupt.h> |
22 | ||
c0c050c5 MC |
23 | struct tx_bd { |
24 | __le32 tx_bd_len_flags_type; | |
25 | #define TX_BD_TYPE (0x3f << 0) | |
26 | #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0) | |
27 | #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0) | |
28 | #define TX_BD_FLAGS_PACKET_END (1 << 6) | |
29 | #define TX_BD_FLAGS_NO_CMPL (1 << 7) | |
30 | #define TX_BD_FLAGS_BD_CNT (0x1f << 8) | |
31 | #define TX_BD_FLAGS_BD_CNT_SHIFT 8 | |
32 | #define TX_BD_FLAGS_LHINT (3 << 13) | |
33 | #define TX_BD_FLAGS_LHINT_SHIFT 13 | |
34 | #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13) | |
35 | #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13) | |
36 | #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13) | |
37 | #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13) | |
38 | #define TX_BD_FLAGS_COAL_NOW (1 << 15) | |
39 | #define TX_BD_LEN (0xffff << 16) | |
40 | #define TX_BD_LEN_SHIFT 16 | |
41 | ||
42 | u32 tx_bd_opaque; | |
43 | __le64 tx_bd_haddr; | |
44 | } __packed; | |
45 | ||
46 | struct tx_bd_ext { | |
47 | __le32 tx_bd_hsize_lflags; | |
48 | #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0) | |
49 | #define TX_BD_FLAGS_IP_CKSUM (1 << 1) | |
50 | #define TX_BD_FLAGS_NO_CRC (1 << 2) | |
51 | #define TX_BD_FLAGS_STAMP (1 << 3) | |
52 | #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4) | |
53 | #define TX_BD_FLAGS_LSO (1 << 5) | |
54 | #define TX_BD_FLAGS_IPID_FMT (1 << 6) | |
55 | #define TX_BD_FLAGS_T_IPID (1 << 7) | |
56 | #define TX_BD_HSIZE (0xff << 16) | |
57 | #define TX_BD_HSIZE_SHIFT 16 | |
58 | ||
59 | __le32 tx_bd_mss; | |
60 | __le32 tx_bd_cfa_action; | |
61 | #define TX_BD_CFA_ACTION (0xffff << 16) | |
62 | #define TX_BD_CFA_ACTION_SHIFT 16 | |
63 | ||
64 | __le32 tx_bd_cfa_meta; | |
65 | #define TX_BD_CFA_META_MASK 0xfffffff | |
66 | #define TX_BD_CFA_META_VID_MASK 0xfff | |
67 | #define TX_BD_CFA_META_PRI_MASK (0xf << 12) | |
68 | #define TX_BD_CFA_META_PRI_SHIFT 12 | |
69 | #define TX_BD_CFA_META_TPID_MASK (3 << 16) | |
70 | #define TX_BD_CFA_META_TPID_SHIFT 16 | |
71 | #define TX_BD_CFA_META_KEY (0xf << 28) | |
72 | #define TX_BD_CFA_META_KEY_SHIFT 28 | |
73 | #define TX_BD_CFA_META_KEY_VLAN (1 << 28) | |
74 | }; | |
75 | ||
76 | struct rx_bd { | |
77 | __le32 rx_bd_len_flags_type; | |
78 | #define RX_BD_TYPE (0x3f << 0) | |
79 | #define RX_BD_TYPE_RX_PACKET_BD 0x4 | |
80 | #define RX_BD_TYPE_RX_BUFFER_BD 0x5 | |
81 | #define RX_BD_TYPE_RX_AGG_BD 0x6 | |
82 | #define RX_BD_TYPE_16B_BD_SIZE (0 << 4) | |
83 | #define RX_BD_TYPE_32B_BD_SIZE (1 << 4) | |
84 | #define RX_BD_TYPE_48B_BD_SIZE (2 << 4) | |
85 | #define RX_BD_TYPE_64B_BD_SIZE (3 << 4) | |
86 | #define RX_BD_FLAGS_SOP (1 << 6) | |
87 | #define RX_BD_FLAGS_EOP (1 << 7) | |
88 | #define RX_BD_FLAGS_BUFFERS (3 << 8) | |
89 | #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8) | |
90 | #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8) | |
91 | #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8) | |
92 | #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8) | |
93 | #define RX_BD_LEN (0xffff << 16) | |
94 | #define RX_BD_LEN_SHIFT 16 | |
95 | ||
96 | u32 rx_bd_opaque; | |
97 | __le64 rx_bd_haddr; | |
98 | }; | |
99 | ||
100 | struct tx_cmp { | |
101 | __le32 tx_cmp_flags_type; | |
102 | #define CMP_TYPE (0x3f << 0) | |
103 | #define CMP_TYPE_TX_L2_CMP 0 | |
104 | #define CMP_TYPE_RX_L2_CMP 17 | |
105 | #define CMP_TYPE_RX_AGG_CMP 18 | |
106 | #define CMP_TYPE_RX_L2_TPA_START_CMP 19 | |
107 | #define CMP_TYPE_RX_L2_TPA_END_CMP 21 | |
108 | #define CMP_TYPE_STATUS_CMP 32 | |
109 | #define CMP_TYPE_REMOTE_DRIVER_REQ 34 | |
110 | #define CMP_TYPE_REMOTE_DRIVER_RESP 36 | |
111 | #define CMP_TYPE_ERROR_STATUS 48 | |
441cabbb MC |
112 | #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL |
113 | #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL | |
114 | #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL | |
115 | #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL | |
116 | #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL | |
c0c050c5 MC |
117 | |
118 | #define TX_CMP_FLAGS_ERROR (1 << 6) | |
119 | #define TX_CMP_FLAGS_PUSH (1 << 7) | |
120 | ||
121 | u32 tx_cmp_opaque; | |
122 | __le32 tx_cmp_errors_v; | |
123 | #define TX_CMP_V (1 << 0) | |
124 | #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1) | |
125 | #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0 | |
126 | #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2 | |
127 | #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4 | |
128 | #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5 | |
129 | #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4) | |
130 | #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5) | |
131 | #define TX_CMP_ERRORS_DMA_ERROR (1 << 6) | |
132 | #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7) | |
133 | ||
134 | __le32 tx_cmp_unsed_3; | |
135 | }; | |
136 | ||
137 | struct rx_cmp { | |
138 | __le32 rx_cmp_len_flags_type; | |
139 | #define RX_CMP_CMP_TYPE (0x3f << 0) | |
140 | #define RX_CMP_FLAGS_ERROR (1 << 6) | |
141 | #define RX_CMP_FLAGS_PLACEMENT (7 << 7) | |
142 | #define RX_CMP_FLAGS_RSS_VALID (1 << 10) | |
143 | #define RX_CMP_FLAGS_UNUSED (1 << 11) | |
144 | #define RX_CMP_FLAGS_ITYPES_SHIFT 12 | |
145 | #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12) | |
146 | #define RX_CMP_FLAGS_ITYPE_IP (1 << 12) | |
147 | #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12) | |
148 | #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12) | |
149 | #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12) | |
150 | #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12) | |
151 | #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12) | |
152 | #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12) | |
153 | #define RX_CMP_LEN (0xffff << 16) | |
154 | #define RX_CMP_LEN_SHIFT 16 | |
155 | ||
156 | u32 rx_cmp_opaque; | |
157 | __le32 rx_cmp_misc_v1; | |
158 | #define RX_CMP_V1 (1 << 0) | |
159 | #define RX_CMP_AGG_BUFS (0x1f << 1) | |
160 | #define RX_CMP_AGG_BUFS_SHIFT 1 | |
161 | #define RX_CMP_RSS_HASH_TYPE (0x7f << 9) | |
162 | #define RX_CMP_RSS_HASH_TYPE_SHIFT 9 | |
163 | #define RX_CMP_PAYLOAD_OFFSET (0xff << 16) | |
164 | #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16 | |
165 | ||
166 | __le32 rx_cmp_rss_hash; | |
167 | }; | |
168 | ||
169 | #define RX_CMP_HASH_VALID(rxcmp) \ | |
170 | ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID)) | |
171 | ||
614388ce MC |
172 | #define RSS_PROFILE_ID_MASK 0x1f |
173 | ||
c0c050c5 | 174 | #define RX_CMP_HASH_TYPE(rxcmp) \ |
614388ce MC |
175 | (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\ |
176 | RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) | |
c0c050c5 MC |
177 | |
178 | struct rx_cmp_ext { | |
179 | __le32 rx_cmp_flags2; | |
180 | #define RX_CMP_FLAGS2_IP_CS_CALC 0x1 | |
181 | #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) | |
182 | #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) | |
183 | #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) | |
184 | #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4) | |
185 | __le32 rx_cmp_meta_data; | |
186 | #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff | |
187 | #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000 | |
188 | #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16 | |
189 | __le32 rx_cmp_cfa_code_errors_v2; | |
190 | #define RX_CMP_V (1 << 0) | |
191 | #define RX_CMPL_ERRORS_MASK (0x7fff << 1) | |
192 | #define RX_CMPL_ERRORS_SFT 1 | |
193 | #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1) | |
194 | #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1) | |
195 | #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1) | |
196 | #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1) | |
197 | #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1) | |
198 | #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4) | |
199 | #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5) | |
200 | #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6) | |
201 | #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7) | |
202 | #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8) | |
203 | #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9) | |
204 | #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9) | |
205 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9) | |
206 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9) | |
207 | #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9) | |
208 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9) | |
209 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9) | |
210 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9) | |
211 | #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12) | |
212 | #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12) | |
213 | #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12) | |
214 | #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12) | |
215 | #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12) | |
216 | #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12) | |
217 | #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12) | |
218 | #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12) | |
219 | #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12) | |
220 | #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12) | |
221 | ||
222 | #define RX_CMPL_CFA_CODE_MASK (0xffff << 16) | |
223 | #define RX_CMPL_CFA_CODE_SFT 16 | |
224 | ||
225 | __le32 rx_cmp_unused3; | |
226 | }; | |
227 | ||
228 | #define RX_CMP_L2_ERRORS \ | |
229 | cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR) | |
230 | ||
231 | #define RX_CMP_L4_CS_BITS \ | |
232 | (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC)) | |
233 | ||
234 | #define RX_CMP_L4_CS_ERR_BITS \ | |
235 | (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR)) | |
236 | ||
237 | #define RX_CMP_L4_CS_OK(rxcmp1) \ | |
238 | (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \ | |
239 | !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS)) | |
240 | ||
241 | #define RX_CMP_ENCAP(rxcmp1) \ | |
242 | ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \ | |
243 | RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3) | |
244 | ||
245 | struct rx_agg_cmp { | |
246 | __le32 rx_agg_cmp_len_flags_type; | |
247 | #define RX_AGG_CMP_TYPE (0x3f << 0) | |
248 | #define RX_AGG_CMP_LEN (0xffff << 16) | |
249 | #define RX_AGG_CMP_LEN_SHIFT 16 | |
250 | u32 rx_agg_cmp_opaque; | |
251 | __le32 rx_agg_cmp_v; | |
252 | #define RX_AGG_CMP_V (1 << 0) | |
253 | __le32 rx_agg_cmp_unused; | |
254 | }; | |
255 | ||
256 | struct rx_tpa_start_cmp { | |
257 | __le32 rx_tpa_start_cmp_len_flags_type; | |
258 | #define RX_TPA_START_CMP_TYPE (0x3f << 0) | |
259 | #define RX_TPA_START_CMP_FLAGS (0x3ff << 6) | |
260 | #define RX_TPA_START_CMP_FLAGS_SHIFT 6 | |
261 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7) | |
262 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7 | |
263 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) | |
264 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) | |
265 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) | |
266 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) | |
267 | #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10) | |
268 | #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12) | |
269 | #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12 | |
270 | #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12) | |
271 | #define RX_TPA_START_CMP_LEN (0xffff << 16) | |
272 | #define RX_TPA_START_CMP_LEN_SHIFT 16 | |
273 | ||
274 | u32 rx_tpa_start_cmp_opaque; | |
275 | __le32 rx_tpa_start_cmp_misc_v1; | |
276 | #define RX_TPA_START_CMP_V1 (0x1 << 0) | |
277 | #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9) | |
278 | #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9 | |
279 | #define RX_TPA_START_CMP_AGG_ID (0x7f << 25) | |
280 | #define RX_TPA_START_CMP_AGG_ID_SHIFT 25 | |
281 | ||
282 | __le32 rx_tpa_start_cmp_rss_hash; | |
283 | }; | |
284 | ||
285 | #define TPA_START_HASH_VALID(rx_tpa_start) \ | |
286 | ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \ | |
287 | cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID)) | |
288 | ||
289 | #define TPA_START_HASH_TYPE(rx_tpa_start) \ | |
614388ce MC |
290 | (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ |
291 | RX_TPA_START_CMP_RSS_HASH_TYPE) >> \ | |
292 | RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) | |
c0c050c5 MC |
293 | |
294 | #define TPA_START_AGG_ID(rx_tpa_start) \ | |
295 | ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ | |
296 | RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT) | |
297 | ||
298 | struct rx_tpa_start_cmp_ext { | |
299 | __le32 rx_tpa_start_cmp_flags2; | |
300 | #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0) | |
301 | #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) | |
302 | #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) | |
303 | #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) | |
94758f8d | 304 | #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8) |
c0c050c5 MC |
305 | |
306 | __le32 rx_tpa_start_cmp_metadata; | |
307 | __le32 rx_tpa_start_cmp_cfa_code_v2; | |
308 | #define RX_TPA_START_CMP_V2 (0x1 << 0) | |
309 | #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16) | |
310 | #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16 | |
94758f8d | 311 | __le32 rx_tpa_start_cmp_hdr_info; |
c0c050c5 MC |
312 | }; |
313 | ||
314 | struct rx_tpa_end_cmp { | |
315 | __le32 rx_tpa_end_cmp_len_flags_type; | |
316 | #define RX_TPA_END_CMP_TYPE (0x3f << 0) | |
317 | #define RX_TPA_END_CMP_FLAGS (0x3ff << 6) | |
318 | #define RX_TPA_END_CMP_FLAGS_SHIFT 6 | |
319 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7) | |
320 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7 | |
321 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) | |
322 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) | |
323 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) | |
324 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) | |
325 | #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10) | |
326 | #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12) | |
327 | #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12 | |
328 | #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12) | |
329 | #define RX_TPA_END_CMP_LEN (0xffff << 16) | |
330 | #define RX_TPA_END_CMP_LEN_SHIFT 16 | |
331 | ||
332 | u32 rx_tpa_end_cmp_opaque; | |
333 | __le32 rx_tpa_end_cmp_misc_v1; | |
334 | #define RX_TPA_END_CMP_V1 (0x1 << 0) | |
335 | #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1) | |
336 | #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1 | |
337 | #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8) | |
338 | #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8 | |
339 | #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16) | |
340 | #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16 | |
341 | #define RX_TPA_END_CMP_AGG_ID (0x7f << 25) | |
342 | #define RX_TPA_END_CMP_AGG_ID_SHIFT 25 | |
343 | ||
344 | __le32 rx_tpa_end_cmp_tsdelta; | |
345 | #define RX_TPA_END_GRO_TS (0x1 << 31) | |
346 | }; | |
347 | ||
348 | #define TPA_END_AGG_ID(rx_tpa_end) \ | |
349 | ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ | |
350 | RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT) | |
351 | ||
352 | #define TPA_END_TPA_SEGS(rx_tpa_end) \ | |
353 | ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ | |
354 | RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT) | |
355 | ||
356 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \ | |
357 | cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \ | |
358 | RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS) | |
359 | ||
360 | #define TPA_END_GRO(rx_tpa_end) \ | |
361 | ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \ | |
362 | RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO) | |
363 | ||
364 | #define TPA_END_GRO_TS(rx_tpa_end) \ | |
a58a3e68 MC |
365 | (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \ |
366 | cpu_to_le32(RX_TPA_END_GRO_TS))) | |
c0c050c5 MC |
367 | |
368 | struct rx_tpa_end_cmp_ext { | |
369 | __le32 rx_tpa_end_cmp_dup_acks; | |
370 | #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0) | |
371 | ||
372 | __le32 rx_tpa_end_cmp_seg_len; | |
373 | #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0) | |
374 | ||
375 | __le32 rx_tpa_end_cmp_errors_v2; | |
376 | #define RX_TPA_END_CMP_V2 (0x1 << 0) | |
377 | #define RX_TPA_END_CMP_ERRORS (0x7fff << 1) | |
378 | #define RX_TPA_END_CMPL_ERRORS_SHIFT 1 | |
379 | ||
380 | u32 rx_tpa_end_cmp_start_opaque; | |
381 | }; | |
382 | ||
383 | #define DB_IDX_MASK 0xffffff | |
384 | #define DB_IDX_VALID (0x1 << 26) | |
385 | #define DB_IRQ_DIS (0x1 << 27) | |
386 | #define DB_KEY_TX (0x0 << 28) | |
387 | #define DB_KEY_RX (0x1 << 28) | |
388 | #define DB_KEY_CP (0x2 << 28) | |
389 | #define DB_KEY_ST (0x3 << 28) | |
390 | #define DB_KEY_TX_PUSH (0x4 << 28) | |
391 | #define DB_LONG_TX_PUSH (0x2 << 24) | |
392 | ||
e4060d30 MC |
393 | #define BNXT_MIN_ROCE_CP_RINGS 2 |
394 | #define BNXT_MIN_ROCE_STAT_CTXS 1 | |
395 | ||
c0c050c5 MC |
396 | #define INVALID_HW_RING_ID ((u16)-1) |
397 | ||
c0c050c5 MC |
398 | /* The hardware supports certain page sizes. Use the supported page sizes |
399 | * to allocate the rings. | |
400 | */ | |
401 | #if (PAGE_SHIFT < 12) | |
402 | #define BNXT_PAGE_SHIFT 12 | |
403 | #elif (PAGE_SHIFT <= 13) | |
404 | #define BNXT_PAGE_SHIFT PAGE_SHIFT | |
405 | #elif (PAGE_SHIFT < 16) | |
406 | #define BNXT_PAGE_SHIFT 13 | |
407 | #else | |
408 | #define BNXT_PAGE_SHIFT 16 | |
409 | #endif | |
410 | ||
411 | #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT) | |
412 | ||
2839f28b MC |
413 | /* The RXBD length is 16-bit so we can only support page sizes < 64K */ |
414 | #if (PAGE_SHIFT > 15) | |
415 | #define BNXT_RX_PAGE_SHIFT 15 | |
416 | #else | |
417 | #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT | |
418 | #endif | |
419 | ||
420 | #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT) | |
421 | ||
c61fb99c MC |
422 | #define BNXT_MAX_MTU 9500 |
423 | #define BNXT_MAX_PAGE_MODE_MTU \ | |
c6d30e83 MC |
424 | ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \ |
425 | XDP_PACKET_HEADROOM) | |
c61fb99c | 426 | |
4ffcd582 | 427 | #define BNXT_MIN_PKT_SIZE 52 |
c0c050c5 MC |
428 | |
429 | #define BNXT_NUM_TESTS(bp) 0 | |
430 | ||
51dd55b5 MC |
431 | #define BNXT_DEFAULT_RX_RING_SIZE 511 |
432 | #define BNXT_DEFAULT_TX_RING_SIZE 511 | |
c0c050c5 MC |
433 | |
434 | #define MAX_TPA 64 | |
435 | ||
d0a42d6f MC |
436 | #if (BNXT_PAGE_SHIFT == 16) |
437 | #define MAX_RX_PAGES 1 | |
438 | #define MAX_RX_AGG_PAGES 4 | |
439 | #define MAX_TX_PAGES 1 | |
440 | #define MAX_CP_PAGES 8 | |
441 | #else | |
c0c050c5 MC |
442 | #define MAX_RX_PAGES 8 |
443 | #define MAX_RX_AGG_PAGES 32 | |
444 | #define MAX_TX_PAGES 8 | |
445 | #define MAX_CP_PAGES 64 | |
d0a42d6f | 446 | #endif |
c0c050c5 MC |
447 | |
448 | #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd)) | |
449 | #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd)) | |
450 | #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp)) | |
451 | ||
452 | #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT) | |
453 | #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT) | |
454 | ||
455 | #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT) | |
456 | ||
457 | #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT) | |
458 | #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT) | |
459 | ||
460 | #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT) | |
461 | ||
462 | #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1) | |
463 | #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1) | |
464 | #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1) | |
465 | ||
466 | #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) | |
467 | #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1)) | |
468 | ||
469 | #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) | |
470 | #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1)) | |
471 | ||
472 | #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) | |
473 | #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1)) | |
474 | ||
475 | #define TX_CMP_VALID(txcmp, raw_cons) \ | |
476 | (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \ | |
477 | !((raw_cons) & bp->cp_bit)) | |
478 | ||
479 | #define RX_CMP_VALID(rxcmp1, raw_cons) \ | |
480 | (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\ | |
481 | !((raw_cons) & bp->cp_bit)) | |
482 | ||
483 | #define RX_AGG_CMP_VALID(agg, raw_cons) \ | |
484 | (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \ | |
485 | !((raw_cons) & bp->cp_bit)) | |
486 | ||
487 | #define TX_CMP_TYPE(txcmp) \ | |
488 | (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE) | |
489 | ||
490 | #define RX_CMP_TYPE(rxcmp) \ | |
491 | (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE) | |
492 | ||
493 | #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask) | |
494 | ||
495 | #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask) | |
496 | ||
497 | #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask) | |
498 | ||
499 | #define ADV_RAW_CMP(idx, n) ((idx) + (n)) | |
500 | #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1) | |
501 | #define RING_CMP(idx) ((idx) & bp->cp_ring_mask) | |
502 | #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1)) | |
503 | ||
e6ef2699 | 504 | #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len) |
ff4fe81d MC |
505 | #define DFLT_HWRM_CMD_TIMEOUT 500 |
506 | #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout) | |
c0c050c5 MC |
507 | #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4) |
508 | #define HWRM_RESP_ERR_CODE_MASK 0xffff | |
a8643e16 | 509 | #define HWRM_RESP_LEN_OFFSET 4 |
c0c050c5 MC |
510 | #define HWRM_RESP_LEN_MASK 0xffff0000 |
511 | #define HWRM_RESP_LEN_SFT 16 | |
512 | #define HWRM_RESP_VALID_MASK 0xff000000 | |
a8643e16 | 513 | #define HWRM_SEQ_ID_INVALID -1 |
c0c050c5 MC |
514 | #define BNXT_HWRM_REQ_MAX_SIZE 128 |
515 | #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \ | |
516 | BNXT_HWRM_REQ_MAX_SIZE) | |
517 | ||
4e5dbbda MC |
518 | #define BNXT_RX_EVENT 1 |
519 | #define BNXT_AGG_EVENT 2 | |
38413406 | 520 | #define BNXT_TX_EVENT 4 |
4e5dbbda | 521 | |
c0c050c5 MC |
522 | struct bnxt_sw_tx_bd { |
523 | struct sk_buff *skb; | |
524 | DEFINE_DMA_UNMAP_ADDR(mapping); | |
525 | u8 is_gso; | |
526 | u8 is_push; | |
38413406 MC |
527 | union { |
528 | unsigned short nr_frags; | |
529 | u16 rx_prod; | |
530 | }; | |
c0c050c5 MC |
531 | }; |
532 | ||
533 | struct bnxt_sw_rx_bd { | |
6bb19474 MC |
534 | void *data; |
535 | u8 *data_ptr; | |
11cd119d | 536 | dma_addr_t mapping; |
c0c050c5 MC |
537 | }; |
538 | ||
539 | struct bnxt_sw_rx_agg_bd { | |
540 | struct page *page; | |
89d0a06c | 541 | unsigned int offset; |
c0c050c5 MC |
542 | dma_addr_t mapping; |
543 | }; | |
544 | ||
545 | struct bnxt_ring_struct { | |
546 | int nr_pages; | |
547 | int page_size; | |
548 | void **pg_arr; | |
549 | dma_addr_t *dma_arr; | |
550 | ||
551 | __le64 *pg_tbl; | |
552 | dma_addr_t pg_tbl_map; | |
553 | ||
554 | int vmem_size; | |
555 | void **vmem; | |
556 | ||
557 | u16 fw_ring_id; /* Ring id filled by Chimp FW */ | |
558 | u8 queue_id; | |
559 | }; | |
560 | ||
561 | struct tx_push_bd { | |
562 | __le32 doorbell; | |
4419dbe6 MC |
563 | __le32 tx_bd_len_flags_type; |
564 | u32 tx_bd_opaque; | |
c0c050c5 MC |
565 | struct tx_bd_ext txbd2; |
566 | }; | |
567 | ||
4419dbe6 MC |
568 | struct tx_push_buffer { |
569 | struct tx_push_bd push_bd; | |
570 | u32 data[25]; | |
571 | }; | |
572 | ||
c0c050c5 | 573 | struct bnxt_tx_ring_info { |
b6ab4b01 | 574 | struct bnxt_napi *bnapi; |
c0c050c5 MC |
575 | u16 tx_prod; |
576 | u16 tx_cons; | |
a960dec9 | 577 | u16 txq_index; |
c0c050c5 MC |
578 | void __iomem *tx_doorbell; |
579 | ||
580 | struct tx_bd *tx_desc_ring[MAX_TX_PAGES]; | |
581 | struct bnxt_sw_tx_bd *tx_buf_ring; | |
582 | ||
583 | dma_addr_t tx_desc_mapping[MAX_TX_PAGES]; | |
584 | ||
4419dbe6 | 585 | struct tx_push_buffer *tx_push; |
c0c050c5 | 586 | dma_addr_t tx_push_mapping; |
4419dbe6 | 587 | __le64 data_mapping; |
c0c050c5 MC |
588 | |
589 | #define BNXT_DEV_STATE_CLOSING 0x1 | |
590 | u32 dev_state; | |
591 | ||
592 | struct bnxt_ring_struct tx_ring_struct; | |
593 | }; | |
594 | ||
595 | struct bnxt_tpa_info { | |
6bb19474 MC |
596 | void *data; |
597 | u8 *data_ptr; | |
c0c050c5 MC |
598 | dma_addr_t mapping; |
599 | u16 len; | |
600 | unsigned short gso_type; | |
601 | u32 flags2; | |
602 | u32 metadata; | |
603 | enum pkt_hash_types hash_type; | |
604 | u32 rss_hash; | |
94758f8d MC |
605 | u32 hdr_info; |
606 | ||
607 | #define BNXT_TPA_L4_SIZE(hdr_info) \ | |
608 | (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32) | |
609 | ||
610 | #define BNXT_TPA_INNER_L3_OFF(hdr_info) \ | |
611 | (((hdr_info) >> 18) & 0x1ff) | |
612 | ||
613 | #define BNXT_TPA_INNER_L2_OFF(hdr_info) \ | |
614 | (((hdr_info) >> 9) & 0x1ff) | |
615 | ||
616 | #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \ | |
617 | ((hdr_info) & 0x1ff) | |
c0c050c5 MC |
618 | }; |
619 | ||
620 | struct bnxt_rx_ring_info { | |
b6ab4b01 | 621 | struct bnxt_napi *bnapi; |
c0c050c5 MC |
622 | u16 rx_prod; |
623 | u16 rx_agg_prod; | |
624 | u16 rx_sw_agg_prod; | |
376a5b86 | 625 | u16 rx_next_cons; |
c0c050c5 MC |
626 | void __iomem *rx_doorbell; |
627 | void __iomem *rx_agg_doorbell; | |
628 | ||
c6d30e83 MC |
629 | struct bpf_prog *xdp_prog; |
630 | ||
c0c050c5 MC |
631 | struct rx_bd *rx_desc_ring[MAX_RX_PAGES]; |
632 | struct bnxt_sw_rx_bd *rx_buf_ring; | |
633 | ||
634 | struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES]; | |
635 | struct bnxt_sw_rx_agg_bd *rx_agg_ring; | |
636 | ||
637 | unsigned long *rx_agg_bmap; | |
638 | u16 rx_agg_bmap_size; | |
639 | ||
89d0a06c MC |
640 | struct page *rx_page; |
641 | unsigned int rx_page_offset; | |
642 | ||
c0c050c5 MC |
643 | dma_addr_t rx_desc_mapping[MAX_RX_PAGES]; |
644 | dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES]; | |
645 | ||
646 | struct bnxt_tpa_info *rx_tpa; | |
647 | ||
648 | struct bnxt_ring_struct rx_ring_struct; | |
649 | struct bnxt_ring_struct rx_agg_ring_struct; | |
650 | }; | |
651 | ||
652 | struct bnxt_cp_ring_info { | |
653 | u32 cp_raw_cons; | |
654 | void __iomem *cp_doorbell; | |
655 | ||
656 | struct tx_cmp *cp_desc_ring[MAX_CP_PAGES]; | |
657 | ||
658 | dma_addr_t cp_desc_mapping[MAX_CP_PAGES]; | |
659 | ||
660 | struct ctx_hw_stats *hw_stats; | |
661 | dma_addr_t hw_stats_map; | |
662 | u32 hw_stats_ctx_id; | |
663 | u64 rx_l4_csum_errors; | |
664 | ||
665 | struct bnxt_ring_struct cp_ring_struct; | |
666 | }; | |
667 | ||
668 | struct bnxt_napi { | |
669 | struct napi_struct napi; | |
670 | struct bnxt *bp; | |
671 | ||
672 | int index; | |
673 | struct bnxt_cp_ring_info cp_ring; | |
b6ab4b01 MC |
674 | struct bnxt_rx_ring_info *rx_ring; |
675 | struct bnxt_tx_ring_info *tx_ring; | |
c0c050c5 | 676 | |
fa3e93e8 MC |
677 | void (*tx_int)(struct bnxt *, struct bnxt_napi *, |
678 | int); | |
679 | u32 flags; | |
680 | #define BNXT_NAPI_FLAG_XDP 0x1 | |
681 | ||
fa7e2812 | 682 | bool in_reset; |
c0c050c5 MC |
683 | }; |
684 | ||
c0c050c5 MC |
685 | struct bnxt_irq { |
686 | irq_handler_t handler; | |
687 | unsigned int vector; | |
688 | u8 requested; | |
689 | char name[IFNAMSIZ + 2]; | |
690 | }; | |
691 | ||
692 | #define HWRM_RING_ALLOC_TX 0x1 | |
693 | #define HWRM_RING_ALLOC_RX 0x2 | |
694 | #define HWRM_RING_ALLOC_AGG 0x4 | |
695 | #define HWRM_RING_ALLOC_CMPL 0x8 | |
696 | ||
697 | #define INVALID_STATS_CTX_ID -1 | |
698 | ||
c0c050c5 MC |
699 | struct bnxt_ring_grp_info { |
700 | u16 fw_stats_ctx; | |
701 | u16 fw_grp_id; | |
702 | u16 rx_fw_ring_id; | |
703 | u16 agg_fw_ring_id; | |
704 | u16 cp_fw_ring_id; | |
705 | }; | |
706 | ||
707 | struct bnxt_vnic_info { | |
708 | u16 fw_vnic_id; /* returned by Chimp during alloc */ | |
94ce9caa PS |
709 | #define BNXT_MAX_CTX_PER_VNIC 2 |
710 | u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC]; | |
c0c050c5 MC |
711 | u16 fw_l2_ctx_id; |
712 | #define BNXT_MAX_UC_ADDRS 4 | |
713 | __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS]; | |
714 | /* index 0 always dev_addr */ | |
715 | u16 uc_filter_count; | |
716 | u8 *uc_list; | |
717 | ||
718 | u16 *fw_grp_ids; | |
c0c050c5 MC |
719 | dma_addr_t rss_table_dma_addr; |
720 | __le16 *rss_table; | |
721 | dma_addr_t rss_hash_key_dma_addr; | |
722 | u64 *rss_hash_key; | |
723 | u32 rx_mask; | |
724 | ||
725 | u8 *mc_list; | |
726 | int mc_list_size; | |
727 | int mc_list_count; | |
728 | dma_addr_t mc_list_mapping; | |
729 | #define BNXT_MAX_MC_ADDRS 16 | |
730 | ||
731 | u32 flags; | |
732 | #define BNXT_VNIC_RSS_FLAG 1 | |
733 | #define BNXT_VNIC_RFS_FLAG 2 | |
734 | #define BNXT_VNIC_MCAST_FLAG 4 | |
735 | #define BNXT_VNIC_UCAST_FLAG 8 | |
ae10ae74 | 736 | #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10 |
c0c050c5 MC |
737 | }; |
738 | ||
739 | #if defined(CONFIG_BNXT_SRIOV) | |
740 | struct bnxt_vf_info { | |
741 | u16 fw_fid; | |
742 | u8 mac_addr[ETH_ALEN]; | |
743 | u16 max_rsscos_ctxs; | |
744 | u16 max_cp_rings; | |
745 | u16 max_tx_rings; | |
746 | u16 max_rx_rings; | |
b72d4a68 | 747 | u16 max_hw_ring_grps; |
c0c050c5 MC |
748 | u16 max_l2_ctxs; |
749 | u16 max_irqs; | |
750 | u16 max_vnics; | |
751 | u16 max_stat_ctxs; | |
752 | u16 vlan; | |
753 | u32 flags; | |
754 | #define BNXT_VF_QOS 0x1 | |
755 | #define BNXT_VF_SPOOFCHK 0x2 | |
756 | #define BNXT_VF_LINK_FORCED 0x4 | |
757 | #define BNXT_VF_LINK_UP 0x8 | |
758 | u32 func_flags; /* func cfg flags */ | |
759 | u32 min_tx_rate; | |
760 | u32 max_tx_rate; | |
761 | void *hwrm_cmd_req_addr; | |
762 | dma_addr_t hwrm_cmd_req_dma_addr; | |
763 | }; | |
379a80a1 | 764 | #endif |
c0c050c5 MC |
765 | |
766 | struct bnxt_pf_info { | |
767 | #define BNXT_FIRST_PF_FID 1 | |
768 | #define BNXT_FIRST_VF_FID 128 | |
a58a3e68 MC |
769 | u16 fw_fid; |
770 | u16 port_id; | |
c0c050c5 MC |
771 | u8 mac_addr[ETH_ALEN]; |
772 | u16 max_rsscos_ctxs; | |
773 | u16 max_cp_rings; | |
774 | u16 max_tx_rings; /* HW assigned max tx rings for this PF */ | |
c0c050c5 | 775 | u16 max_rx_rings; /* HW assigned max rx rings for this PF */ |
b72d4a68 | 776 | u16 max_hw_ring_grps; |
c0c050c5 MC |
777 | u16 max_irqs; |
778 | u16 max_l2_ctxs; | |
779 | u16 max_vnics; | |
780 | u16 max_stat_ctxs; | |
781 | u32 first_vf_id; | |
782 | u16 active_vfs; | |
783 | u16 max_vfs; | |
784 | u32 max_encap_records; | |
785 | u32 max_decap_records; | |
786 | u32 max_tx_em_flows; | |
787 | u32 max_tx_wm_flows; | |
788 | u32 max_rx_em_flows; | |
789 | u32 max_rx_wm_flows; | |
790 | unsigned long *vf_event_bmap; | |
791 | u16 hwrm_cmd_req_pages; | |
792 | void *hwrm_cmd_req_addr[4]; | |
793 | dma_addr_t hwrm_cmd_req_dma_addr[4]; | |
794 | struct bnxt_vf_info *vf; | |
795 | }; | |
c0c050c5 MC |
796 | |
797 | struct bnxt_ntuple_filter { | |
798 | struct hlist_node hash; | |
a54c4d74 | 799 | u8 dst_mac_addr[ETH_ALEN]; |
c0c050c5 MC |
800 | u8 src_mac_addr[ETH_ALEN]; |
801 | struct flow_keys fkeys; | |
802 | __le64 filter_id; | |
803 | u16 sw_id; | |
a54c4d74 | 804 | u8 l2_fltr_idx; |
c0c050c5 MC |
805 | u16 rxq; |
806 | u32 flow_id; | |
807 | unsigned long state; | |
808 | #define BNXT_FLTR_VALID 0 | |
809 | #define BNXT_FLTR_UPDATE 1 | |
810 | }; | |
811 | ||
c0c050c5 | 812 | struct bnxt_link_info { |
03efbec0 | 813 | u8 phy_type; |
c0c050c5 MC |
814 | u8 media_type; |
815 | u8 transceiver; | |
816 | u8 phy_addr; | |
817 | u8 phy_link_status; | |
818 | #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK | |
819 | #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL | |
820 | #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK | |
821 | u8 wire_speed; | |
822 | u8 loop_back; | |
823 | u8 link_up; | |
824 | u8 duplex; | |
825 | #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_HALF | |
826 | #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_FULL | |
827 | u8 pause; | |
828 | #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX | |
829 | #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX | |
830 | #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \ | |
831 | PORT_PHY_QCFG_RESP_PAUSE_TX) | |
3277360e | 832 | u8 lp_pause; |
c0c050c5 MC |
833 | u8 auto_pause_setting; |
834 | u8 force_pause_setting; | |
835 | u8 duplex_setting; | |
836 | u8 auto_mode; | |
837 | #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \ | |
838 | (mode) <= BNXT_LINK_AUTO_MSK) | |
839 | #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE | |
840 | #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS | |
841 | #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED | |
842 | #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW | |
11f15ed3 | 843 | #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK |
c0c050c5 MC |
844 | #define PHY_VER_LEN 3 |
845 | u8 phy_ver[PHY_VER_LEN]; | |
846 | u16 link_speed; | |
847 | #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB | |
848 | #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB | |
849 | #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB | |
850 | #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB | |
851 | #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB | |
852 | #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB | |
853 | #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB | |
854 | #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB | |
855 | #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB | |
856 | u16 support_speeds; | |
68515a18 | 857 | u16 auto_link_speeds; /* fw adv setting */ |
c0c050c5 MC |
858 | #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB |
859 | #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB | |
860 | #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB | |
861 | #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB | |
862 | #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB | |
863 | #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB | |
864 | #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB | |
865 | #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB | |
866 | #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB | |
93ed8117 | 867 | u16 support_auto_speeds; |
3277360e | 868 | u16 lp_auto_link_speeds; |
c0c050c5 MC |
869 | u16 force_link_speed; |
870 | u32 preemphasis; | |
42ee18fe | 871 | u8 module_status; |
e70c752f MC |
872 | u16 fec_cfg; |
873 | #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED | |
874 | #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED | |
875 | #define BNXT_FEC_ENC_RS PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED | |
c0c050c5 MC |
876 | |
877 | /* copy of requested setting from ethtool cmd */ | |
878 | u8 autoneg; | |
879 | #define BNXT_AUTONEG_SPEED 1 | |
880 | #define BNXT_AUTONEG_FLOW_CTRL 2 | |
881 | u8 req_duplex; | |
882 | u8 req_flow_ctrl; | |
883 | u16 req_link_speed; | |
68515a18 | 884 | u16 advertising; /* user adv setting */ |
c0c050c5 | 885 | bool force_link_chng; |
4bb13abf | 886 | |
c0c050c5 MC |
887 | /* a copy of phy_qcfg output used to report link |
888 | * info to VF | |
889 | */ | |
890 | struct hwrm_port_phy_qcfg_output phy_qcfg_resp; | |
891 | }; | |
892 | ||
893 | #define BNXT_MAX_QUEUE 8 | |
894 | ||
895 | struct bnxt_queue_info { | |
896 | u8 queue_id; | |
897 | u8 queue_profile; | |
898 | }; | |
899 | ||
5ad2cbee MC |
900 | #define BNXT_MAX_LED 4 |
901 | ||
902 | struct bnxt_led_info { | |
903 | u8 led_id; | |
904 | u8 led_type; | |
905 | u8 led_group_id; | |
906 | u8 unused; | |
907 | __le16 led_state_caps; | |
908 | #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \ | |
909 | cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED)) | |
910 | ||
911 | __le16 led_color_caps; | |
912 | }; | |
913 | ||
11809490 JH |
914 | #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 |
915 | #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014 | |
916 | #define BNXT_CAG_REG_BASE 0x300000 | |
917 | ||
c0c050c5 MC |
918 | struct bnxt { |
919 | void __iomem *bar0; | |
920 | void __iomem *bar1; | |
921 | void __iomem *bar2; | |
922 | ||
923 | u32 reg_base; | |
659c805c MC |
924 | u16 chip_num; |
925 | #define CHIP_NUM_57301 0x16c8 | |
926 | #define CHIP_NUM_57302 0x16c9 | |
927 | #define CHIP_NUM_57304 0x16ca | |
3e8060fa | 928 | #define CHIP_NUM_58700 0x16cd |
659c805c MC |
929 | #define CHIP_NUM_57402 0x16d0 |
930 | #define CHIP_NUM_57404 0x16d1 | |
931 | #define CHIP_NUM_57406 0x16d2 | |
932 | ||
933 | #define CHIP_NUM_57311 0x16ce | |
934 | #define CHIP_NUM_57312 0x16cf | |
935 | #define CHIP_NUM_57314 0x16df | |
936 | #define CHIP_NUM_57412 0x16d6 | |
937 | #define CHIP_NUM_57414 0x16d7 | |
938 | #define CHIP_NUM_57416 0x16d8 | |
939 | #define CHIP_NUM_57417 0x16d9 | |
940 | ||
941 | #define BNXT_CHIP_NUM_5730X(chip_num) \ | |
942 | ((chip_num) >= CHIP_NUM_57301 && \ | |
943 | (chip_num) <= CHIP_NUM_57304) | |
944 | ||
945 | #define BNXT_CHIP_NUM_5740X(chip_num) \ | |
946 | ((chip_num) >= CHIP_NUM_57402 && \ | |
947 | (chip_num) <= CHIP_NUM_57406) | |
948 | ||
949 | #define BNXT_CHIP_NUM_5731X(chip_num) \ | |
950 | ((chip_num) == CHIP_NUM_57311 || \ | |
951 | (chip_num) == CHIP_NUM_57312 || \ | |
952 | (chip_num) == CHIP_NUM_57314) | |
953 | ||
954 | #define BNXT_CHIP_NUM_5741X(chip_num) \ | |
955 | ((chip_num) >= CHIP_NUM_57412 && \ | |
956 | (chip_num) <= CHIP_NUM_57417) | |
957 | ||
958 | #define BNXT_CHIP_NUM_57X0X(chip_num) \ | |
959 | (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num)) | |
960 | ||
961 | #define BNXT_CHIP_NUM_57X1X(chip_num) \ | |
962 | (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num)) | |
c0c050c5 MC |
963 | |
964 | struct net_device *dev; | |
965 | struct pci_dev *pdev; | |
966 | ||
967 | atomic_t intr_sem; | |
968 | ||
969 | u32 flags; | |
970 | #define BNXT_FLAG_DCB_ENABLED 0x1 | |
971 | #define BNXT_FLAG_VF 0x2 | |
972 | #define BNXT_FLAG_LRO 0x4 | |
d1611c3a | 973 | #ifdef CONFIG_INET |
c0c050c5 | 974 | #define BNXT_FLAG_GRO 0x8 |
d1611c3a MC |
975 | #else |
976 | /* Cannot support hardware GRO if CONFIG_INET is not set */ | |
977 | #define BNXT_FLAG_GRO 0x0 | |
978 | #endif | |
c0c050c5 MC |
979 | #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO) |
980 | #define BNXT_FLAG_JUMBO 0x10 | |
981 | #define BNXT_FLAG_STRIP_VLAN 0x20 | |
982 | #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \ | |
983 | BNXT_FLAG_LRO) | |
984 | #define BNXT_FLAG_USING_MSIX 0x40 | |
985 | #define BNXT_FLAG_MSIX_CAP 0x80 | |
986 | #define BNXT_FLAG_RFS 0x100 | |
6e6c5a57 | 987 | #define BNXT_FLAG_SHARED_RINGS 0x200 |
3bdf56c4 | 988 | #define BNXT_FLAG_PORT_STATS 0x400 |
87da7f79 | 989 | #define BNXT_FLAG_UDP_RSS_CAP 0x800 |
170ce013 | 990 | #define BNXT_FLAG_EEE_CAP 0x1000 |
8fdefd63 | 991 | #define BNXT_FLAG_NEW_RSS_CAP 0x2000 |
c1ef146a | 992 | #define BNXT_FLAG_WOL_CAP 0x4000 |
e4060d30 MC |
993 | #define BNXT_FLAG_ROCEV1_CAP 0x8000 |
994 | #define BNXT_FLAG_ROCEV2_CAP 0x10000 | |
995 | #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \ | |
996 | BNXT_FLAG_ROCEV2_CAP) | |
bdbd1eb5 | 997 | #define BNXT_FLAG_NO_AGG_RINGS 0x20000 |
c61fb99c | 998 | #define BNXT_FLAG_RX_PAGE_MODE 0x40000 |
bc39f885 | 999 | #define BNXT_FLAG_FW_LLDP_AGENT 0x80000 |
3e8060fa | 1000 | #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000 |
6e6c5a57 | 1001 | |
c0c050c5 MC |
1002 | #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \ |
1003 | BNXT_FLAG_RFS | \ | |
1004 | BNXT_FLAG_STRIP_VLAN) | |
1005 | ||
1006 | #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) | |
1007 | #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) | |
567b2abe SB |
1008 | #define BNXT_NPAR(bp) ((bp)->port_partition_type) |
1009 | #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp)) | |
3e8060fa | 1010 | #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0) |
c61fb99c | 1011 | #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE) |
c0c050c5 | 1012 | |
a588e458 MC |
1013 | struct bnxt_en_dev *edev; |
1014 | struct bnxt_en_dev * (*ulp_probe)(struct net_device *); | |
1015 | ||
c0c050c5 MC |
1016 | struct bnxt_napi **bnapi; |
1017 | ||
b6ab4b01 MC |
1018 | struct bnxt_rx_ring_info *rx_ring; |
1019 | struct bnxt_tx_ring_info *tx_ring; | |
a960dec9 | 1020 | u16 *tx_ring_map; |
b6ab4b01 | 1021 | |
309369c9 MC |
1022 | struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int, |
1023 | struct sk_buff *); | |
1024 | ||
6bb19474 MC |
1025 | struct sk_buff * (*rx_skb_func)(struct bnxt *, |
1026 | struct bnxt_rx_ring_info *, | |
1027 | u16, void *, u8 *, dma_addr_t, | |
1028 | unsigned int); | |
1029 | ||
c0c050c5 MC |
1030 | u32 rx_buf_size; |
1031 | u32 rx_buf_use_size; /* useable size */ | |
b3dba77c MC |
1032 | u16 rx_offset; |
1033 | u16 rx_dma_offset; | |
745fc05c | 1034 | enum dma_data_direction rx_dir; |
c0c050c5 MC |
1035 | u32 rx_ring_size; |
1036 | u32 rx_agg_ring_size; | |
1037 | u32 rx_copy_thresh; | |
1038 | u32 rx_ring_mask; | |
1039 | u32 rx_agg_ring_mask; | |
1040 | int rx_nr_pages; | |
1041 | int rx_agg_nr_pages; | |
1042 | int rx_nr_rings; | |
1043 | int rsscos_nr_ctxs; | |
1044 | ||
1045 | u32 tx_ring_size; | |
1046 | u32 tx_ring_mask; | |
1047 | int tx_nr_pages; | |
1048 | int tx_nr_rings; | |
1049 | int tx_nr_rings_per_tc; | |
5f449249 | 1050 | int tx_nr_rings_xdp; |
c0c050c5 MC |
1051 | |
1052 | int tx_wake_thresh; | |
1053 | int tx_push_thresh; | |
1054 | int tx_push_size; | |
1055 | ||
1056 | u32 cp_ring_size; | |
1057 | u32 cp_ring_mask; | |
1058 | u32 cp_bit; | |
1059 | int cp_nr_pages; | |
1060 | int cp_nr_rings; | |
1061 | ||
1062 | int num_stat_ctxs; | |
b81a90d3 MC |
1063 | |
1064 | /* grp_info indexed by completion ring index */ | |
c0c050c5 MC |
1065 | struct bnxt_ring_grp_info *grp_info; |
1066 | struct bnxt_vnic_info *vnic_info; | |
1067 | int nr_vnics; | |
87da7f79 | 1068 | u32 rss_hash_cfg; |
c0c050c5 MC |
1069 | |
1070 | u8 max_tc; | |
87c374de | 1071 | u8 max_lltc; /* lossless TCs */ |
c0c050c5 MC |
1072 | struct bnxt_queue_info q_info[BNXT_MAX_QUEUE]; |
1073 | ||
1074 | unsigned int current_interval; | |
3bdf56c4 | 1075 | #define BNXT_TIMER_INTERVAL HZ |
c0c050c5 MC |
1076 | |
1077 | struct timer_list timer; | |
1078 | ||
caefe526 MC |
1079 | unsigned long state; |
1080 | #define BNXT_STATE_OPEN 0 | |
4cebdcec | 1081 | #define BNXT_STATE_IN_SP_TASK 1 |
c0c050c5 MC |
1082 | |
1083 | struct bnxt_irq *irq_tbl; | |
7809592d | 1084 | int total_irqs; |
c0c050c5 MC |
1085 | u8 mac_addr[ETH_ALEN]; |
1086 | ||
7df4ae9f MC |
1087 | #ifdef CONFIG_BNXT_DCB |
1088 | struct ieee_pfc *ieee_pfc; | |
1089 | struct ieee_ets *ieee_ets; | |
1090 | u8 dcbx_cap; | |
1091 | u8 default_pri; | |
1092 | #endif /* CONFIG_BNXT_DCB */ | |
1093 | ||
c0c050c5 MC |
1094 | u32 msg_enable; |
1095 | ||
11f15ed3 | 1096 | u32 hwrm_spec_code; |
c0c050c5 MC |
1097 | u16 hwrm_cmd_seq; |
1098 | u32 hwrm_intr_seq_id; | |
1099 | void *hwrm_cmd_resp_addr; | |
1100 | dma_addr_t hwrm_cmd_resp_dma_addr; | |
1101 | void *hwrm_dbg_resp_addr; | |
1102 | dma_addr_t hwrm_dbg_resp_dma_addr; | |
1103 | #define HWRM_DBG_REG_BUF_SIZE 128 | |
3bdf56c4 MC |
1104 | |
1105 | struct rx_port_stats *hw_rx_port_stats; | |
1106 | struct tx_port_stats *hw_tx_port_stats; | |
1107 | dma_addr_t hw_rx_port_stats_map; | |
1108 | dma_addr_t hw_tx_port_stats_map; | |
1109 | int hw_port_stats_size; | |
1110 | ||
e6ef2699 | 1111 | u16 hwrm_max_req_len; |
ff4fe81d | 1112 | int hwrm_cmd_timeout; |
c0c050c5 MC |
1113 | struct mutex hwrm_cmd_lock; /* serialize hwrm messages */ |
1114 | struct hwrm_ver_get_output ver_resp; | |
1115 | #define FW_VER_STR_LEN 32 | |
1116 | #define BC_HWRM_STR_LEN 21 | |
1117 | #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN) | |
1118 | char fw_ver_str[FW_VER_STR_LEN]; | |
1119 | __be16 vxlan_port; | |
1120 | u8 vxlan_port_cnt; | |
1121 | __le16 vxlan_fw_dst_port_id; | |
7cdd5fc3 | 1122 | __be16 nge_port; |
c0c050c5 MC |
1123 | u8 nge_port_cnt; |
1124 | __le16 nge_fw_dst_port_id; | |
567b2abe | 1125 | u8 port_partition_type; |
dfc9c94a | 1126 | |
dfb5b894 MC |
1127 | u16 rx_coal_ticks; |
1128 | u16 rx_coal_ticks_irq; | |
1129 | u16 rx_coal_bufs; | |
1130 | u16 rx_coal_bufs_irq; | |
dfc9c94a MC |
1131 | u16 tx_coal_ticks; |
1132 | u16 tx_coal_ticks_irq; | |
1133 | u16 tx_coal_bufs; | |
1134 | u16 tx_coal_bufs_irq; | |
c0c050c5 MC |
1135 | |
1136 | #define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2) | |
c0c050c5 | 1137 | |
51f30785 MC |
1138 | u32 stats_coal_ticks; |
1139 | #define BNXT_DEF_STATS_COAL_TICKS 1000000 | |
1140 | #define BNXT_MIN_STATS_COAL_TICKS 250000 | |
1141 | #define BNXT_MAX_STATS_COAL_TICKS 1000000 | |
1142 | ||
c0c050c5 MC |
1143 | struct work_struct sp_task; |
1144 | unsigned long sp_event; | |
1145 | #define BNXT_RX_MASK_SP_EVENT 0 | |
1146 | #define BNXT_RX_NTP_FLTR_SP_EVENT 1 | |
1147 | #define BNXT_LINK_CHNG_SP_EVENT 2 | |
c5d7774d JH |
1148 | #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3 |
1149 | #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4 | |
1150 | #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5 | |
1151 | #define BNXT_RESET_TASK_SP_EVENT 6 | |
1152 | #define BNXT_RST_RING_SP_EVENT 7 | |
19241368 | 1153 | #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8 |
3bdf56c4 | 1154 | #define BNXT_PERIODIC_STATS_SP_EVENT 9 |
4bb13abf | 1155 | #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10 |
fc0f1929 | 1156 | #define BNXT_RESET_TASK_SILENT_SP_EVENT 11 |
7cdd5fc3 AD |
1157 | #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12 |
1158 | #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13 | |
286ef9d6 | 1159 | #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14 |
c0c050c5 | 1160 | |
379a80a1 | 1161 | struct bnxt_pf_info pf; |
c0c050c5 MC |
1162 | #ifdef CONFIG_BNXT_SRIOV |
1163 | int nr_vfs; | |
c0c050c5 MC |
1164 | struct bnxt_vf_info vf; |
1165 | wait_queue_head_t sriov_cfg_wait; | |
1166 | bool sriov_cfg; | |
1167 | #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000) | |
1168 | #endif | |
1169 | ||
1170 | #define BNXT_NTP_FLTR_MAX_FLTR 4096 | |
1171 | #define BNXT_NTP_FLTR_HASH_SIZE 512 | |
1172 | #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1) | |
1173 | struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE]; | |
1174 | spinlock_t ntp_fltr_lock; /* for hash table add, del */ | |
1175 | ||
1176 | unsigned long *ntp_fltr_bmap; | |
1177 | int ntp_fltr_count; | |
1178 | ||
1179 | struct bnxt_link_info link_info; | |
170ce013 MC |
1180 | struct ethtool_eee eee; |
1181 | u32 lpi_tmr_lo; | |
1182 | u32 lpi_tmr_hi; | |
5ad2cbee | 1183 | |
c1ef146a MC |
1184 | u8 wol_filter_id; |
1185 | u8 wol; | |
1186 | ||
5ad2cbee MC |
1187 | u8 num_leds; |
1188 | struct bnxt_led_info leds[BNXT_MAX_LED]; | |
c6d30e83 MC |
1189 | |
1190 | struct bpf_prog *xdp_prog; | |
c0c050c5 MC |
1191 | }; |
1192 | ||
c77192f2 MC |
1193 | #define BNXT_RX_STATS_OFFSET(counter) \ |
1194 | (offsetof(struct rx_port_stats, counter) / 8) | |
1195 | ||
1196 | #define BNXT_TX_STATS_OFFSET(counter) \ | |
1197 | ((offsetof(struct tx_port_stats, counter) + \ | |
1198 | sizeof(struct rx_port_stats) + 512) / 8) | |
1199 | ||
42ee18fe AK |
1200 | #define I2C_DEV_ADDR_A0 0xa0 |
1201 | #define I2C_DEV_ADDR_A2 0xa2 | |
1202 | #define SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e | |
1203 | #define SFP_EEPROM_SFF_8472_COMP_SIZE 1 | |
1204 | #define SFF_MODULE_ID_SFP 0x3 | |
1205 | #define SFF_MODULE_ID_QSFP 0xc | |
1206 | #define SFF_MODULE_ID_QSFP_PLUS 0xd | |
1207 | #define SFF_MODULE_ID_QSFP28 0x11 | |
1208 | #define BNXT_MAX_PHY_I2C_RESP_SIZE 64 | |
1209 | ||
38413406 MC |
1210 | static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr) |
1211 | { | |
1212 | /* Tell compiler to fetch tx indices from memory. */ | |
1213 | barrier(); | |
1214 | ||
1215 | return bp->tx_ring_size - | |
1216 | ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask); | |
1217 | } | |
1218 | ||
1219 | extern const u16 bnxt_lhint_arr[]; | |
1220 | ||
1221 | int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, | |
1222 | u16 prod, gfp_t gfp); | |
c6d30e83 MC |
1223 | void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data); |
1224 | void bnxt_set_tpa_flags(struct bnxt *bp); | |
c0c050c5 | 1225 | void bnxt_set_ring_params(struct bnxt *); |
c61fb99c | 1226 | int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode); |
c0c050c5 MC |
1227 | void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16); |
1228 | int _hwrm_send_message(struct bnxt *, void *, u32, int); | |
1229 | int hwrm_send_message(struct bnxt *, void *, u32, int); | |
90e20921 | 1230 | int hwrm_send_message_silent(struct bnxt *, void *, u32, int); |
a1653b13 MC |
1231 | int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap, |
1232 | int bmap_size); | |
a588e458 | 1233 | int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id); |
391be5c2 | 1234 | int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings); |
c0c050c5 | 1235 | int bnxt_hwrm_set_coal(struct bnxt *); |
e4060d30 | 1236 | unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp); |
a588e458 | 1237 | void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max); |
e4060d30 | 1238 | unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp); |
a588e458 | 1239 | void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max); |
33c2657e | 1240 | void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max); |
7df4ae9f MC |
1241 | void bnxt_tx_disable(struct bnxt *bp); |
1242 | void bnxt_tx_enable(struct bnxt *bp); | |
c0c050c5 | 1243 | int bnxt_hwrm_set_pause(struct bnxt *); |
939f7f0c | 1244 | int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool); |
5ac67d8b | 1245 | int bnxt_hwrm_fw_set_time(struct bnxt *); |
c0c050c5 MC |
1246 | int bnxt_open_nic(struct bnxt *, bool, bool); |
1247 | int bnxt_close_nic(struct bnxt *, bool, bool); | |
5f449249 | 1248 | int bnxt_reserve_rings(struct bnxt *bp, int tx, int rx, int tcs, int tx_xdp); |
c5e3deb8 | 1249 | int bnxt_setup_mq_tc(struct net_device *dev, u8 tc); |
6e6c5a57 | 1250 | int bnxt_get_max_rings(struct bnxt *, int *, int *, bool); |
7b08f661 | 1251 | void bnxt_restore_pf_fw_resources(struct bnxt *bp); |
c0c050c5 | 1252 | #endif |