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net: thunderx: Add ethtool support for supported ports and link modes.
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / cavium / thunder / thunder_bgx.c
CommitLineData
4863dea3
SG		 1/*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
46b903a0 9#include <linux/acpi.h>
4863dea3
SG		 10#include <linux/module.h>
11#include <linux/interrupt.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/phy.h>
16#include <linux/of.h>
17#include <linux/of_mdio.h>
18#include <linux/of_net.h>
19
20#include "nic_reg.h"
21#include "nic.h"
22#include "thunder_bgx.h"
23
24#define DRV_NAME "thunder-BGX"
25#define DRV_VERSION "1.0"
26
27struct lmac {
28 struct bgx *bgx;
29 int dmac;
46b903a0 30 u8 mac[ETH_ALEN];
0bcb7d51
SG		 31 u8 lmac_type;
32 u8 lane_to_sds;
33 bool use_training;
4863dea3
SG		 34 bool link_up;
35 int lmacid; /* ID within BGX */
36 int lmacid_bd; /* ID on board */
37 struct net_device netdev;
38 struct phy_device *phydev;
39 unsigned int last_duplex;
40 unsigned int last_link;
41 unsigned int last_speed;
42 bool is_sgmii;
43 struct delayed_work dwork;
44 struct workqueue_struct *check_link;
0c886a1d 45};
4863dea3
SG		 46
47struct bgx {
48 u8 bgx_id;
4863dea3
SG		 49 struct lmac lmac[MAX_LMAC_PER_BGX];
50 int lmac_count;
6465859a 51 u8 max_lmac;
4863dea3
SG		 52 void __iomem *reg_base;
53 struct pci_dev *pdev;
09de3917 54 bool is_dlm;
6465859a 55 bool is_rgx;
0c886a1d 56};
4863dea3 57
fd7ec062 58static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
4863dea3
SG		 59static int lmac_count; /* Total no of LMACs in system */
60
61static int bgx_xaui_check_link(struct lmac *lmac);
62
63/* Supported devices */
64static const struct pci_device_id bgx_id_table[] = {
65 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) },
6465859a 66 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_RGX) },
4863dea3
SG		 67 { 0, } /* end of table */
68};
69
70MODULE_AUTHOR("Cavium Inc");
71MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver");
72MODULE_LICENSE("GPL v2");
73MODULE_VERSION(DRV_VERSION);
74MODULE_DEVICE_TABLE(pci, bgx_id_table);
75
76/* The Cavium ThunderX network controller can *only* be found in SoCs
77 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
78 * registers on this platform are implicitly strongly ordered with respect
79 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
80 * with no memory barriers in this driver. The readq()/writeq() functions add
81 * explicit ordering operation which in this case are redundant, and only
82 * add overhead.
83 */
84
85/* Register read/write APIs */
86static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset)
87{
88 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
89
90 return readq_relaxed(addr);
91}
92
93static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
94{
95 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
96
97 writeq_relaxed(val, addr);
98}
99
100static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
101{
102 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
103
104 writeq_relaxed(val | readq_relaxed(addr), addr);
105}
106
107static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero)
108{
109 int timeout = 100;
110 u64 reg_val;
111
112 while (timeout) {
113 reg_val = bgx_reg_read(bgx, lmac, reg);
114 if (zero && !(reg_val & mask))
115 return 0;
116 if (!zero && (reg_val & mask))
117 return 0;
118 usleep_range(1000, 2000);
119 timeout--;
120 }
121 return 1;
122}
123
124/* Return number of BGX present in HW */
125unsigned bgx_get_map(int node)
126{
127 int i;
128 unsigned map = 0;
129
09de3917
SG		 130 for (i = 0; i < MAX_BGX_PER_NODE; i++) {
131 if (bgx_vnic[(node * MAX_BGX_PER_NODE) + i])
4863dea3
SG		 132 map |= (1 << i);
133 }
134
135 return map;
136}
137EXPORT_SYMBOL(bgx_get_map);
138
139/* Return number of LMAC configured for this BGX */
140int bgx_get_lmac_count(int node, int bgx_idx)
141{
142 struct bgx *bgx;
143
09de3917 144 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
4863dea3
SG		 145 if (bgx)
146 return bgx->lmac_count;
147
148 return 0;
149}
150EXPORT_SYMBOL(bgx_get_lmac_count);
151
152/* Returns the current link status of LMAC */
153void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status)
154{
155 struct bgx_link_status *link = (struct bgx_link_status *)status;
156 struct bgx *bgx;
157 struct lmac *lmac;
158
09de3917 159 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
4863dea3
SG		 160 if (!bgx)
161 return;
162
163 lmac = &bgx->lmac[lmacid];
1cc70259 164 link->mac_type = lmac->lmac_type;
4863dea3
SG		 165 link->link_up = lmac->link_up;
166 link->duplex = lmac->last_duplex;
167 link->speed = lmac->last_speed;
168}
169EXPORT_SYMBOL(bgx_get_lmac_link_state);
170
e610cb32 171const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
4863dea3 172{
09de3917 173 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
4863dea3
SG		 174
175 if (bgx)
176 return bgx->lmac[lmacid].mac;
177
178 return NULL;
179}
180EXPORT_SYMBOL(bgx_get_lmac_mac);
181
e610cb32 182void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac)
4863dea3 183{
09de3917 184 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
4863dea3
SG		 185
186 if (!bgx)
187 return;
188
189 ether_addr_copy(bgx->lmac[lmacid].mac, mac);
190}
191EXPORT_SYMBOL(bgx_set_lmac_mac);
192
bc69fdfc
SG		 193void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable)
194{
09de3917 195 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
6465859a 196 struct lmac *lmac;
bc69fdfc
SG		 197 u64 cfg;
198
199 if (!bgx)
200 return;
6465859a 201 lmac = &bgx->lmac[lmacid];
bc69fdfc
SG		 202
203 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
204 if (enable)
205 cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN;
206 else
207 cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
208 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
6465859a
SG		 209
210 if (bgx->is_rgx)
211 xcv_setup_link(enable ? lmac->link_up : 0, lmac->last_speed);
bc69fdfc
SG		 212}
213EXPORT_SYMBOL(bgx_lmac_rx_tx_enable);
214
4863dea3
SG		 215static void bgx_sgmii_change_link_state(struct lmac *lmac)
216{
217 struct bgx *bgx = lmac->bgx;
218 u64 cmr_cfg;
219 u64 port_cfg = 0;
220 u64 misc_ctl = 0;
221
222 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
223 cmr_cfg &= ~CMR_EN;
224 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
225
226 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
227 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
228
229 if (lmac->link_up) {
230 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO;
231 port_cfg &= ~GMI_PORT_CFG_DUPLEX;
232 port_cfg |= (lmac->last_duplex << 2);
233 } else {
234 misc_ctl |= PCS_MISC_CTL_GMX_ENO;
235 }
236
237 switch (lmac->last_speed) {
238 case 10:
239 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
240 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */
241 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
242 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
243 misc_ctl |= 50; /* samp_pt */
244 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
245 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
246 break;
247 case 100:
248 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
249 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
250 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
251 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
252 misc_ctl |= 5; /* samp_pt */
253 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
254 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
255 break;
256 case 1000:
257 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */
258 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
259 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */
260 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
261 misc_ctl |= 1; /* samp_pt */
262 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512);
263 if (lmac->last_duplex)
264 bgx_reg_write(bgx, lmac->lmacid,
265 BGX_GMP_GMI_TXX_BURST, 0);
266 else
267 bgx_reg_write(bgx, lmac->lmacid,
268 BGX_GMP_GMI_TXX_BURST, 8192);
269 break;
270 default:
271 break;
272 }
273 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
274 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
275
276 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
277
6465859a 278 /* Re-enable lmac */
4863dea3
SG		 279 cmr_cfg |= CMR_EN;
280 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
6465859a
SG		 281
282 if (bgx->is_rgx && (cmr_cfg & (CMR_PKT_RX_EN | CMR_PKT_TX_EN)))
283 xcv_setup_link(lmac->link_up, lmac->last_speed);
4863dea3
SG		 284}
285
fd7ec062 286static void bgx_lmac_handler(struct net_device *netdev)
4863dea3
SG		 287{
288 struct lmac *lmac = container_of(netdev, struct lmac, netdev);
099a728d 289 struct phy_device *phydev;
4863dea3
SG		 290 int link_changed = 0;
291
292 if (!lmac)
293 return;
294
099a728d 295 phydev = lmac->phydev;
296
4863dea3
SG		 297 if (!phydev->link && lmac->last_link)
298 link_changed = -1;
299
300 if (phydev->link &&
301 (lmac->last_duplex != phydev->duplex ||
302 lmac->last_link != phydev->link ||
303 lmac->last_speed != phydev->speed)) {
304 link_changed = 1;
305 }
306
307 lmac->last_link = phydev->link;
308 lmac->last_speed = phydev->speed;
309 lmac->last_duplex = phydev->duplex;
310
311 if (!link_changed)
312 return;
313
314 if (link_changed > 0)
315 lmac->link_up = true;
316 else
317 lmac->link_up = false;
318
319 if (lmac->is_sgmii)
320 bgx_sgmii_change_link_state(lmac);
321 else
322 bgx_xaui_check_link(lmac);
323}
324
325u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx)
326{
327 struct bgx *bgx;
328
09de3917 329 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
4863dea3
SG		 330 if (!bgx)
331 return 0;
332
333 if (idx > 8)
334 lmac = 0;
335 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8));
336}
337EXPORT_SYMBOL(bgx_get_rx_stats);
338
339u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx)
340{
341 struct bgx *bgx;
342
09de3917 343 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
4863dea3
SG		 344 if (!bgx)
345 return 0;
346
347 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8));
348}
349EXPORT_SYMBOL(bgx_get_tx_stats);
350
351static void bgx_flush_dmac_addrs(struct bgx *bgx, int lmac)
352{
353 u64 offset;
354
355 while (bgx->lmac[lmac].dmac > 0) {
356 offset = ((bgx->lmac[lmac].dmac - 1) * sizeof(u64)) +
357 (lmac * MAX_DMAC_PER_LMAC * sizeof(u64));
358 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, 0);
359 bgx->lmac[lmac].dmac--;
360 }
361}
362
d77a2384
SG		 363/* Configure BGX LMAC in internal loopback mode */
364void bgx_lmac_internal_loopback(int node, int bgx_idx,
365 int lmac_idx, bool enable)
366{
367 struct bgx *bgx;
368 struct lmac *lmac;
369 u64 cfg;
370
09de3917 371 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
d77a2384
SG		 372 if (!bgx)
373 return;
374
375 lmac = &bgx->lmac[lmac_idx];
376 if (lmac->is_sgmii) {
377 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL);
378 if (enable)
379 cfg |= PCS_MRX_CTL_LOOPBACK1;
380 else
381 cfg &= ~PCS_MRX_CTL_LOOPBACK1;
382 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg);
383 } else {
384 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1);
385 if (enable)
386 cfg |= SPU_CTL_LOOPBACK;
387 else
388 cfg &= ~SPU_CTL_LOOPBACK;
389 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg);
390 }
391}
392EXPORT_SYMBOL(bgx_lmac_internal_loopback);
393
3f8057cf 394static int bgx_lmac_sgmii_init(struct bgx *bgx, struct lmac *lmac)
4863dea3 395{
3f8057cf 396 int lmacid = lmac->lmacid;
4863dea3
SG		 397 u64 cfg;
398
399 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30);
400 /* max packet size */
401 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE);
402
403 /* Disable frame alignment if using preamble */
404 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
405 if (cfg & 1)
406 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0);
407
408 /* Enable lmac */
409 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
410
411 /* PCS reset */
412 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET);
413 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL,
414 PCS_MRX_CTL_RESET, true)) {
415 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n");
416 return -1;
417 }
418
419 /* power down, reset autoneg, autoneg enable */
420 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL);
421 cfg &= ~PCS_MRX_CTL_PWR_DN;
422 cfg |= (PCS_MRX_CTL_RST_AN | PCS_MRX_CTL_AN_EN);
423 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg);
424
3f8057cf
SG		 425 if (lmac->lmac_type == BGX_MODE_QSGMII) {
426 /* Disable disparity check for QSGMII */
427 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL);
428 cfg &= ~PCS_MISC_CTL_DISP_EN;
429 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL, cfg);
430 return 0;
431 }
432
6465859a
SG		 433 if (lmac->lmac_type == BGX_MODE_SGMII) {
434 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS,
435 PCS_MRX_STATUS_AN_CPT, false)) {
436 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n");
437 return -1;
438 }
4863dea3
SG		 439 }
440
441 return 0;
442}
443
0bcb7d51 444static int bgx_lmac_xaui_init(struct bgx *bgx, struct lmac *lmac)
4863dea3
SG		 445{
446 u64 cfg;
0bcb7d51 447 int lmacid = lmac->lmacid;
4863dea3
SG		 448
449 /* Reset SPU */
450 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET);
451 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
452 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
453 return -1;
454 }
455
456 /* Disable LMAC */
457 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
458 cfg &= ~CMR_EN;
459 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
460
461 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
462 /* Set interleaved running disparity for RXAUI */
93db2cf8 463 if (lmac->lmac_type == BGX_MODE_RXAUI)
4863dea3 464 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL,
93db2cf8
SG		 465 SPU_MISC_CTL_INTLV_RDISP);
466
467 /* Clear receive packet disable */
468 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL);
469 cfg &= ~SPU_MISC_CTL_RX_DIS;
470 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg);
4863dea3
SG		 471
472 /* clear all interrupts */
473 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT);
474 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg);
475 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT);
476 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg);
477 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
478 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
479
0bcb7d51 480 if (lmac->use_training) {
4863dea3
SG		 481 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00);
482 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00);
483 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00);
484 /* training enable */
485 bgx_reg_modify(bgx, lmacid,
486 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN);
487 }
488
489 /* Append FCS to each packet */
490 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D);
491
492 /* Disable forward error correction */
493 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL);
494 cfg &= ~SPU_FEC_CTL_FEC_EN;
495 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg);
496
497 /* Disable autoneg */
498 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL);
499 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN);
500 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg);
501
502 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV);
0bcb7d51 503 if (lmac->lmac_type == BGX_MODE_10G_KR)
4863dea3 504 cfg |= (1 << 23);
0bcb7d51 505 else if (lmac->lmac_type == BGX_MODE_40G_KR)
4863dea3
SG		 506 cfg |= (1 << 24);
507 else
508 cfg &= ~((1 << 23) | (1 << 24));
509 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12)));
510 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg);
511
512 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL);
513 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN;
514 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg);
515
516 /* Enable lmac */
517 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
518
519 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1);
520 cfg &= ~SPU_CTL_LOW_POWER;
521 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg);
522
523 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL);
524 cfg &= ~SMU_TX_CTL_UNI_EN;
525 cfg |= SMU_TX_CTL_DIC_EN;
526 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg);
527
528 /* take lmac_count into account */
529 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1));
530 /* max packet size */
531 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE);
532
533 return 0;
534}
535
536static int bgx_xaui_check_link(struct lmac *lmac)
537{
538 struct bgx *bgx = lmac->bgx;
539 int lmacid = lmac->lmacid;
0bcb7d51 540 int lmac_type = lmac->lmac_type;
4863dea3
SG		 541 u64 cfg;
542
0bcb7d51 543 if (lmac->use_training) {
4863dea3
SG		 544 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
545 if (!(cfg & (1ull << 13))) {
546 cfg = (1ull << 13) | (1ull << 14);
547 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
548 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL);
549 cfg |= (1ull << 0);
550 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg);
551 return -1;
552 }
553 }
554
555 /* wait for PCS to come out of reset */
556 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
557 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
558 return -1;
559 }
560
561 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) ||
562 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) {
563 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1,
564 SPU_BR_STATUS_BLK_LOCK, false)) {
565 dev_err(&bgx->pdev->dev,
566 "SPU_BR_STATUS_BLK_LOCK not completed\n");
567 return -1;
568 }
569 } else {
570 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS,
571 SPU_BX_STATUS_RX_ALIGN, false)) {
572 dev_err(&bgx->pdev->dev,
573 "SPU_BX_STATUS_RX_ALIGN not completed\n");
574 return -1;
575 }
576 }
577
578 /* Clear rcvflt bit (latching high) and read it back */
3f4c68cf
SG		 579 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT)
580 bgx_reg_modify(bgx, lmacid,
581 BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT);
4863dea3
SG		 582 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
583 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n");
0bcb7d51 584 if (lmac->use_training) {
4863dea3
SG		 585 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
586 if (!(cfg & (1ull << 13))) {
587 cfg = (1ull << 13) | (1ull << 14);
588 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
589 cfg = bgx_reg_read(bgx, lmacid,
590 BGX_SPUX_BR_PMD_CRTL);
591 cfg |= (1ull << 0);
592 bgx_reg_write(bgx, lmacid,
593 BGX_SPUX_BR_PMD_CRTL, cfg);
594 return -1;
595 }
596 }
597 return -1;
598 }
599
4863dea3
SG		 600 /* Wait for BGX RX to be idle */
601 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) {
602 dev_err(&bgx->pdev->dev, "SMU RX not idle\n");
603 return -1;
604 }
605
606 /* Wait for BGX TX to be idle */
607 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) {
608 dev_err(&bgx->pdev->dev, "SMU TX not idle\n");
609 return -1;
610 }
611
3f4c68cf
SG		 612 /* Check for MAC RX faults */
613 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_CTL);
614 /* 0 - Link is okay, 1 - Local fault, 2 - Remote fault */
615 cfg &= SMU_RX_CTL_STATUS;
616 if (!cfg)
617 return 0;
618
619 /* Rx local/remote fault seen.
620 * Do lmac reinit to see if condition recovers
621 */
0bcb7d51 622 bgx_lmac_xaui_init(bgx, lmac);
3f4c68cf
SG		 623
624 return -1;
4863dea3
SG		 625}
626
627static void bgx_poll_for_link(struct work_struct *work)
628{
629 struct lmac *lmac;
3f4c68cf 630 u64 spu_link, smu_link;
4863dea3
SG		 631
632 lmac = container_of(work, struct lmac, dwork.work);
633
634 /* Receive link is latching low. Force it high and verify it */
635 bgx_reg_modify(lmac->bgx, lmac->lmacid,
636 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
637 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1,
638 SPU_STATUS1_RCV_LNK, false);
639
3f4c68cf
SG		 640 spu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1);
641 smu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SMUX_RX_CTL);
642
643 if ((spu_link & SPU_STATUS1_RCV_LNK) &&
644 !(smu_link & SMU_RX_CTL_STATUS)) {
4863dea3 645 lmac->link_up = 1;
0bcb7d51 646 if (lmac->lmac_type == BGX_MODE_XLAUI)
4863dea3
SG		 647 lmac->last_speed = 40000;
648 else
649 lmac->last_speed = 10000;
650 lmac->last_duplex = 1;
651 } else {
652 lmac->link_up = 0;
0b72a9a1
SG		 653 lmac->last_speed = SPEED_UNKNOWN;
654 lmac->last_duplex = DUPLEX_UNKNOWN;
4863dea3
SG		 655 }
656
657 if (lmac->last_link != lmac->link_up) {
3f4c68cf
SG		 658 if (lmac->link_up) {
659 if (bgx_xaui_check_link(lmac)) {
660 /* Errors, clear link_up state */
661 lmac->link_up = 0;
662 lmac->last_speed = SPEED_UNKNOWN;
663 lmac->last_duplex = DUPLEX_UNKNOWN;
664 }
665 }
4863dea3 666 lmac->last_link = lmac->link_up;
4863dea3
SG		 667 }
668
669 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2);
670}
671
3f8057cf
SG		 672static int phy_interface_mode(u8 lmac_type)
673{
674 if (lmac_type == BGX_MODE_QSGMII)
675 return PHY_INTERFACE_MODE_QSGMII;
6465859a
SG		 676 if (lmac_type == BGX_MODE_RGMII)
677 return PHY_INTERFACE_MODE_RGMII;
3f8057cf
SG		 678
679 return PHY_INTERFACE_MODE_SGMII;
680}
681
4863dea3
SG		 682static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid)
683{
684 struct lmac *lmac;
685 u64 cfg;
686
687 lmac = &bgx->lmac[lmacid];
688 lmac->bgx = bgx;
689
3f8057cf 690 if ((lmac->lmac_type == BGX_MODE_SGMII) ||
6465859a
SG		 691 (lmac->lmac_type == BGX_MODE_QSGMII) ||
692 (lmac->lmac_type == BGX_MODE_RGMII)) {
4863dea3 693 lmac->is_sgmii = 1;
3f8057cf 694 if (bgx_lmac_sgmii_init(bgx, lmac))
4863dea3
SG		 695 return -1;
696 } else {
697 lmac->is_sgmii = 0;
0bcb7d51 698 if (bgx_lmac_xaui_init(bgx, lmac))
4863dea3
SG		 699 return -1;
700 }
701
702 if (lmac->is_sgmii) {
703 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
704 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
705 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg);
706 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1);
707 } else {
708 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND);
709 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
710 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg);
711 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4);
712 }
713
714 /* Enable lmac */
bc69fdfc 715 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
4863dea3
SG		 716
717 /* Restore default cfg, incase low level firmware changed it */
718 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03);
719
0bcb7d51
SG		 720 if ((lmac->lmac_type != BGX_MODE_XFI) &&
721 (lmac->lmac_type != BGX_MODE_XLAUI) &&
722 (lmac->lmac_type != BGX_MODE_40G_KR) &&
723 (lmac->lmac_type != BGX_MODE_10G_KR)) {
4863dea3
SG		 724 if (!lmac->phydev)
725 return -ENODEV;
726
727 lmac->phydev->dev_flags = 0;
728
729 if (phy_connect_direct(&lmac->netdev, lmac->phydev,
730 bgx_lmac_handler,
3f8057cf 731 phy_interface_mode(lmac->lmac_type)))
4863dea3
SG		 732 return -ENODEV;
733
734 phy_start_aneg(lmac->phydev);
735 } else {
736 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND |
737 WQ_MEM_RECLAIM, 1);
738 if (!lmac->check_link)
739 return -ENOMEM;
740 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link);
741 queue_delayed_work(lmac->check_link, &lmac->dwork, 0);
742 }
743
744 return 0;
745}
746
fd7ec062 747static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid)
4863dea3
SG		 748{
749 struct lmac *lmac;
3f4c68cf 750 u64 cfg;
4863dea3
SG		 751
752 lmac = &bgx->lmac[lmacid];
753 if (lmac->check_link) {
754 /* Destroy work queue */
a7b1f535 755 cancel_delayed_work_sync(&lmac->dwork);
4863dea3
SG		 756 destroy_workqueue(lmac->check_link);
757 }
758
3f4c68cf
SG		 759 /* Disable packet reception */
760 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
761 cfg &= ~CMR_PKT_RX_EN;
762 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
763
764 /* Give chance for Rx/Tx FIFO to get drained */
765 bgx_poll_reg(bgx, lmacid, BGX_CMRX_RX_FIFO_LEN, (u64)0x1FFF, true);
766 bgx_poll_reg(bgx, lmacid, BGX_CMRX_TX_FIFO_LEN, (u64)0x3FFF, true);
767
768 /* Disable packet transmission */
769 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
770 cfg &= ~CMR_PKT_TX_EN;
771 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
772
773 /* Disable serdes lanes */
774 if (!lmac->is_sgmii)
775 bgx_reg_modify(bgx, lmacid,
776 BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
777 else
778 bgx_reg_modify(bgx, lmacid,
779 BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_PWR_DN);
780
781 /* Disable LMAC */
782 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
783 cfg &= ~CMR_EN;
784 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
785
4863dea3
SG		 786 bgx_flush_dmac_addrs(bgx, lmacid);
787
0bcb7d51
SG		 788 if ((lmac->lmac_type != BGX_MODE_XFI) &&
789 (lmac->lmac_type != BGX_MODE_XLAUI) &&
790 (lmac->lmac_type != BGX_MODE_40G_KR) &&
791 (lmac->lmac_type != BGX_MODE_10G_KR) && lmac->phydev)
4863dea3
SG		 792 phy_disconnect(lmac->phydev);
793
794 lmac->phydev = NULL;
795}
796
4863dea3
SG		 797static void bgx_init_hw(struct bgx *bgx)
798{
799 int i;
0bcb7d51 800 struct lmac *lmac;
4863dea3
SG		 801
802 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP);
803 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS))
804 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id);
805
806 /* Set lmac type and lane2serdes mapping */
807 for (i = 0; i < bgx->lmac_count; i++) {
0bcb7d51 808 lmac = &bgx->lmac[i];
4863dea3 809 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
0bcb7d51 810 (lmac->lmac_type << 8) | lmac->lane_to_sds);
4863dea3
SG		 811 bgx->lmac[i].lmacid_bd = lmac_count;
812 lmac_count++;
813 }
814
815 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count);
816 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count);
817
818 /* Set the backpressure AND mask */
819 for (i = 0; i < bgx->lmac_count; i++)
820 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND,
821 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) <<
822 (i * MAX_BGX_CHANS_PER_LMAC));
823
824 /* Disable all MAC filtering */
825 for (i = 0; i < RX_DMAC_COUNT; i++)
826 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00);
827
828 /* Disable MAC steering (NCSI traffic) */
829 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++)
830 bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00);
831}
832
3f8057cf
SG		 833static u8 bgx_get_lane2sds_cfg(struct bgx *bgx, struct lmac *lmac)
834{
835 return (u8)(bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG) & 0xFF);
836}
837
0bcb7d51 838static void bgx_print_qlm_mode(struct bgx *bgx, u8 lmacid)
4863dea3
SG		 839{
840 struct device *dev = &bgx->pdev->dev;
0bcb7d51
SG		 841 struct lmac *lmac;
842 char str[20];
57aaf63c
SG		 843 u8 dlm;
844
6465859a 845 if (lmacid > bgx->max_lmac)
57aaf63c 846 return;
4863dea3 847
0bcb7d51 848 lmac = &bgx->lmac[lmacid];
57aaf63c 849 dlm = (lmacid / 2) + (bgx->bgx_id * 2);
09de3917 850 if (!bgx->is_dlm)
57aaf63c
SG		 851 sprintf(str, "BGX%d QLM mode", bgx->bgx_id);
852 else
853 sprintf(str, "BGX%d DLM%d mode", bgx->bgx_id, dlm);
4863dea3 854
0bcb7d51 855 switch (lmac->lmac_type) {
4863dea3 856 case BGX_MODE_SGMII:
0bcb7d51 857 dev_info(dev, "%s: SGMII\n", (char *)str);
4863dea3
SG		 858 break;
859 case BGX_MODE_XAUI:
0bcb7d51 860 dev_info(dev, "%s: XAUI\n", (char *)str);
4863dea3
SG		 861 break;
862 case BGX_MODE_RXAUI:
0bcb7d51 863 dev_info(dev, "%s: RXAUI\n", (char *)str);
4863dea3
SG		 864 break;
865 case BGX_MODE_XFI:
0bcb7d51
SG		 866 if (!lmac->use_training)
867 dev_info(dev, "%s: XFI\n", (char *)str);
868 else
869 dev_info(dev, "%s: 10G_KR\n", (char *)str);
4863dea3
SG		 870 break;
871 case BGX_MODE_XLAUI:
0bcb7d51
SG		 872 if (!lmac->use_training)
873 dev_info(dev, "%s: XLAUI\n", (char *)str);
874 else
875 dev_info(dev, "%s: 40G_KR4\n", (char *)str);
4863dea3 876 break;
3f8057cf
SG		 877 case BGX_MODE_QSGMII:
878 if ((lmacid == 0) &&
879 (bgx_get_lane2sds_cfg(bgx, lmac) != lmacid))
880 return;
881 if ((lmacid == 2) &&
882 (bgx_get_lane2sds_cfg(bgx, lmac) == lmacid))
883 return;
884 dev_info(dev, "%s: QSGMII\n", (char *)str);
885 break;
6465859a
SG		 886 case BGX_MODE_RGMII:
887 dev_info(dev, "%s: RGMII\n", (char *)str);
888 break;
3f8057cf
SG		 889 case BGX_MODE_INVALID:
890 /* Nothing to do */
891 break;
4863dea3
SG		 892 }
893}
894
3f8057cf 895static void lmac_set_lane2sds(struct bgx *bgx, struct lmac *lmac)
0bcb7d51
SG		 896{
897 switch (lmac->lmac_type) {
898 case BGX_MODE_SGMII:
899 case BGX_MODE_XFI:
900 lmac->lane_to_sds = lmac->lmacid;
901 break;
902 case BGX_MODE_XAUI:
903 case BGX_MODE_XLAUI:
6465859a 904 case BGX_MODE_RGMII:
0bcb7d51
SG		 905 lmac->lane_to_sds = 0xE4;
906 break;
907 case BGX_MODE_RXAUI:
908 lmac->lane_to_sds = (lmac->lmacid) ? 0xE : 0x4;
909 break;
3f8057cf
SG		 910 case BGX_MODE_QSGMII:
911 /* There is no way to determine if DLM0/2 is QSGMII or
912 * DLM1/3 is configured to QSGMII as bootloader will
913 * configure all LMACs, so take whatever is configured
914 * by low level firmware.
915 */
916 lmac->lane_to_sds = bgx_get_lane2sds_cfg(bgx, lmac);
917 break;
0bcb7d51
SG		 918 default:
919 lmac->lane_to_sds = 0;
920 break;
921 }
922}
923
6465859a
SG		 924static void lmac_set_training(struct bgx *bgx, struct lmac *lmac, int lmacid)
925{
926 if ((lmac->lmac_type != BGX_MODE_10G_KR) &&
927 (lmac->lmac_type != BGX_MODE_40G_KR)) {
928 lmac->use_training = 0;
929 return;
930 }
931
932 lmac->use_training = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL) &
933 SPU_PMD_CRTL_TRAIN_EN;
934}
935
0bcb7d51
SG		 936static void bgx_set_lmac_config(struct bgx *bgx, u8 idx)
937{
938 struct lmac *lmac;
57aaf63c 939 struct lmac *olmac;
0bcb7d51 940 u64 cmr_cfg;
57aaf63c
SG		 941 u8 lmac_type;
942 u8 lane_to_sds;
0bcb7d51
SG		 943
944 lmac = &bgx->lmac[idx];
0bcb7d51 945
09de3917 946 if (!bgx->is_dlm || bgx->is_rgx) {
57aaf63c
SG		 947 /* Read LMAC0 type to figure out QLM mode
948 * This is configured by low level firmware
949 */
950 cmr_cfg = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
951 lmac->lmac_type = (cmr_cfg >> 8) & 0x07;
6465859a
SG		 952 if (bgx->is_rgx)
953 lmac->lmac_type = BGX_MODE_RGMII;
954 lmac_set_training(bgx, lmac, 0);
3f8057cf 955 lmac_set_lane2sds(bgx, lmac);
57aaf63c
SG		 956 return;
957 }
958
959 /* On 81xx BGX can be split across 2 DLMs
960 * firmware programs lmac_type of LMAC0 and LMAC2
0bcb7d51 961 */
57aaf63c
SG		 962 if ((idx == 0) || (idx == 2)) {
963 cmr_cfg = bgx_reg_read(bgx, idx, BGX_CMRX_CFG);
964 lmac_type = (u8)((cmr_cfg >> 8) & 0x07);
965 lane_to_sds = (u8)(cmr_cfg & 0xFF);
966 /* Check if config is not reset value */
967 if ((lmac_type == 0) && (lane_to_sds == 0xE4))
968 lmac->lmac_type = BGX_MODE_INVALID;
969 else
970 lmac->lmac_type = lmac_type;
6465859a 971 lmac_set_training(bgx, lmac, lmac->lmacid);
3f8057cf 972 lmac_set_lane2sds(bgx, lmac);
57aaf63c 973
57aaf63c 974 olmac = &bgx->lmac[idx + 1];
5271156b
SG		 975 /* Check if other LMAC on the same DLM is already configured by
976 * firmware, if so use the same config or else set as same, as
977 * that of LMAC 0/2.
978 * This check is needed as on 80xx only one lane of each of the
979 * DLM of BGX0 is used, so have to rely on firmware for
980 * distingushing 80xx from 81xx.
981 */
982 cmr_cfg = bgx_reg_read(bgx, idx + 1, BGX_CMRX_CFG);
983 lmac_type = (u8)((cmr_cfg >> 8) & 0x07);
984 lane_to_sds = (u8)(cmr_cfg & 0xFF);
985 if ((lmac_type == 0) && (lane_to_sds == 0xE4)) {
986 olmac->lmac_type = lmac->lmac_type;
987 lmac_set_lane2sds(bgx, olmac);
988 } else {
989 olmac->lmac_type = lmac_type;
990 olmac->lane_to_sds = lane_to_sds;
991 }
6465859a 992 lmac_set_training(bgx, olmac, olmac->lmacid);
57aaf63c
SG		 993 }
994}
995
996static bool is_dlm0_in_bgx_mode(struct bgx *bgx)
997{
998 struct lmac *lmac;
999
09de3917 1000 if (!bgx->is_dlm)
57aaf63c
SG		 1001 return true;
1002
3f8057cf 1003 lmac = &bgx->lmac[0];
57aaf63c
SG		 1004 if (lmac->lmac_type == BGX_MODE_INVALID)
1005 return false;
1006
1007 return true;
0bcb7d51
SG		 1008}
1009
1010static void bgx_get_qlm_mode(struct bgx *bgx)
1011{
57aaf63c
SG		 1012 struct lmac *lmac;
1013 struct lmac *lmac01;
1014 struct lmac *lmac23;
0bcb7d51
SG		 1015 u8 idx;
1016
57aaf63c 1017 /* Init all LMAC's type to invalid */
6465859a 1018 for (idx = 0; idx < bgx->max_lmac; idx++) {
57aaf63c 1019 lmac = &bgx->lmac[idx];
57aaf63c 1020 lmac->lmacid = idx;
6465859a
SG		 1021 lmac->lmac_type = BGX_MODE_INVALID;
1022 lmac->use_training = false;
57aaf63c
SG		 1023 }
1024
0bcb7d51
SG		 1025 /* It is assumed that low level firmware sets this value */
1026 bgx->lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
6465859a
SG		 1027 if (bgx->lmac_count > bgx->max_lmac)
1028 bgx->lmac_count = bgx->max_lmac;
0bcb7d51 1029
6465859a 1030 for (idx = 0; idx < bgx->max_lmac; idx++)
0bcb7d51 1031 bgx_set_lmac_config(bgx, idx);
57aaf63c 1032
09de3917 1033 if (!bgx->is_dlm || bgx->is_rgx) {
57aaf63c
SG		 1034 bgx_print_qlm_mode(bgx, 0);
1035 return;
1036 }
1037
1038 if (bgx->lmac_count) {
1039 bgx_print_qlm_mode(bgx, 0);
1040 bgx_print_qlm_mode(bgx, 2);
1041 }
1042
1043 /* If DLM0 is not in BGX mode then LMAC0/1 have
1044 * to be configured with serdes lanes of DLM1
1045 */
1046 if (is_dlm0_in_bgx_mode(bgx) || (bgx->lmac_count > 2))
1047 return;
1048 for (idx = 0; idx < bgx->lmac_count; idx++) {
1049 lmac01 = &bgx->lmac[idx];
1050 lmac23 = &bgx->lmac[idx + 2];
1051 lmac01->lmac_type = lmac23->lmac_type;
1052 lmac01->lane_to_sds = lmac23->lane_to_sds;
1053 }
0bcb7d51
SG		 1054}
1055
46b903a0
DD		 1056#ifdef CONFIG_ACPI
1057
1d82efac
RR		 1058static int acpi_get_mac_address(struct device *dev, struct acpi_device *adev,
1059 u8 *dst)
46b903a0
DD		 1060{
1061 u8 mac[ETH_ALEN];
1062 int ret;
1063
1064 ret = fwnode_property_read_u8_array(acpi_fwnode_handle(adev),
1065 "mac-address", mac, ETH_ALEN);
1066 if (ret)
1067 goto out;
1068
1069 if (!is_valid_ether_addr(mac)) {
1d82efac 1070 dev_err(dev, "MAC address invalid: %pM\n", mac);
46b903a0
DD		 1071 ret = -EINVAL;
1072 goto out;
1073 }
1074
1d82efac
RR		 1075 dev_info(dev, "MAC address set to: %pM\n", mac);
1076
46b903a0
DD		 1077 memcpy(dst, mac, ETH_ALEN);
1078out:
1079 return ret;
1080}
1081
1082/* Currently only sets the MAC address. */
1083static acpi_status bgx_acpi_register_phy(acpi_handle handle,
1084 u32 lvl, void *context, void **rv)
1085{
1086 struct bgx *bgx = context;
1d82efac 1087 struct device *dev = &bgx->pdev->dev;
46b903a0
DD		 1088 struct acpi_device *adev;
1089
1090 if (acpi_bus_get_device(handle, &adev))
1091 goto out;
1092
1d82efac 1093 acpi_get_mac_address(dev, adev, bgx->lmac[bgx->lmac_count].mac);
46b903a0 1094
1d82efac 1095 SET_NETDEV_DEV(&bgx->lmac[bgx->lmac_count].netdev, dev);
46b903a0
DD		 1096
1097 bgx->lmac[bgx->lmac_count].lmacid = bgx->lmac_count;
1098out:
1099 bgx->lmac_count++;
1100 return AE_OK;
1101}
1102
1103static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl,
1104 void *context, void **ret_val)
1105{
1106 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1107 struct bgx *bgx = context;
1108 char bgx_sel[5];
1109
1110 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id);
1111 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
1112 pr_warn("Invalid link device\n");
1113 return AE_OK;
1114 }
1115
1116 if (strncmp(string.pointer, bgx_sel, 4))
1117 return AE_OK;
1118
1119 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
1120 bgx_acpi_register_phy, NULL, bgx, NULL);
1121
1122 kfree(string.pointer);
1123 return AE_CTRL_TERMINATE;
1124}
1125
1126static int bgx_init_acpi_phy(struct bgx *bgx)
1127{
1128 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL);
1129 return 0;
1130}
1131
1132#else
1133
1134static int bgx_init_acpi_phy(struct bgx *bgx)
1135{
1136 return -ENODEV;
1137}
1138
1139#endif /* CONFIG_ACPI */
1140
de387e11
RR		 1141#if IS_ENABLED(CONFIG_OF_MDIO)
1142
1143static int bgx_init_of_phy(struct bgx *bgx)
4863dea3 1144{
eee326fd 1145 struct fwnode_handle *fwn;
b7d3e3d3 1146 struct device_node *node = NULL;
4863dea3
SG		 1147 u8 lmac = 0;
1148
eee326fd 1149 device_for_each_child_node(&bgx->pdev->dev, fwn) {
5fc7cf17 1150 struct phy_device *pd;
eee326fd 1151 struct device_node *phy_np;
b7d3e3d3 1152 const char *mac;
eee326fd 1153
5fc7cf17
DD		 1154 /* Should always be an OF node. But if it is not, we
1155 * cannot handle it, so exit the loop.
eee326fd 1156 */
b7d3e3d3 1157 node = to_of_node(fwn);
eee326fd
DD		 1158 if (!node)
1159 break;
4863dea3 1160
eee326fd 1161 mac = of_get_mac_address(node);
4863dea3
SG		 1162 if (mac)
1163 ether_addr_copy(bgx->lmac[lmac].mac, mac);
1164
1165 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev);
1166 bgx->lmac[lmac].lmacid = lmac;
5fc7cf17
DD		 1167
1168 phy_np = of_parse_phandle(node, "phy-handle", 0);
1169 /* If there is no phy or defective firmware presents
1170 * this cortina phy, for which there is no driver
1171 * support, ignore it.
1172 */
1173 if (phy_np &&
1174 !of_device_is_compatible(phy_np, "cortina,cs4223-slice")) {
1175 /* Wait until the phy drivers are available */
1176 pd = of_phy_find_device(phy_np);
1177 if (!pd)
b7d3e3d3 1178 goto defer;
5fc7cf17
DD		 1179 bgx->lmac[lmac].phydev = pd;
1180 }
1181
4863dea3 1182 lmac++;
6465859a 1183 if (lmac == bgx->max_lmac) {
65c66af6 1184 of_node_put(node);
4863dea3 1185 break;
65c66af6 1186 }
4863dea3 1187 }
de387e11 1188 return 0;
b7d3e3d3
DD		 1189
1190defer:
1191 /* We are bailing out, try not to leak device reference counts
1192 * for phy devices we may have already found.
1193 */
1194 while (lmac) {
1195 if (bgx->lmac[lmac].phydev) {
1196 put_device(&bgx->lmac[lmac].phydev->mdio.dev);
1197 bgx->lmac[lmac].phydev = NULL;
1198 }
1199 lmac--;
1200 }
1201 of_node_put(node);
1202 return -EPROBE_DEFER;
de387e11
RR		 1203}
1204
1205#else
1206
1207static int bgx_init_of_phy(struct bgx *bgx)
1208{
1209 return -ENODEV;
1210}
1211
1212#endif /* CONFIG_OF_MDIO */
1213
1214static int bgx_init_phy(struct bgx *bgx)
1215{
46b903a0
DD		 1216 if (!acpi_disabled)
1217 return bgx_init_acpi_phy(bgx);
1218
de387e11 1219 return bgx_init_of_phy(bgx);
4863dea3
SG		 1220}
1221
1222static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1223{
1224 int err;
1225 struct device *dev = &pdev->dev;
1226 struct bgx *bgx = NULL;
4863dea3 1227 u8 lmac;
57aaf63c 1228 u16 sdevid;
4863dea3
SG		 1229
1230 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL);
1231 if (!bgx)
1232 return -ENOMEM;
1233 bgx->pdev = pdev;
1234
1235 pci_set_drvdata(pdev, bgx);
1236
1237 err = pci_enable_device(pdev);
1238 if (err) {
1239 dev_err(dev, "Failed to enable PCI device\n");
1240 pci_set_drvdata(pdev, NULL);
1241 return err;
1242 }
1243
1244 err = pci_request_regions(pdev, DRV_NAME);
1245 if (err) {
1246 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1247 goto err_disable_device;
1248 }
1249
1250 /* MAP configuration registers */
1251 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1252 if (!bgx->reg_base) {
1253 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n");
1254 err = -ENOMEM;
1255 goto err_release_regions;
1256 }
d768b678 1257
6465859a
SG		 1258 pci_read_config_word(pdev, PCI_DEVICE_ID, &sdevid);
1259 if (sdevid != PCI_DEVICE_ID_THUNDER_RGX) {
612e94bd
RMC		 1260 bgx->bgx_id = (pci_resource_start(pdev,
1261 PCI_CFG_REG_BAR_NUM) >> 24) & BGX_ID_MASK;
09de3917 1262 bgx->bgx_id += nic_get_node_id(pdev) * MAX_BGX_PER_NODE;
6465859a
SG		 1263 bgx->max_lmac = MAX_LMAC_PER_BGX;
1264 bgx_vnic[bgx->bgx_id] = bgx;
1265 } else {
1266 bgx->is_rgx = true;
1267 bgx->max_lmac = 1;
1268 bgx->bgx_id = MAX_BGX_PER_CN81XX - 1;
1269 bgx_vnic[bgx->bgx_id] = bgx;
1270 xcv_init_hw();
1271 }
1272
09de3917
SG		 1273 /* On 81xx all are DLMs and on 83xx there are 3 BGX QLMs and one
1274 * BGX i.e BGX2 can be split across 2 DLMs.
1275 */
1276 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
1277 if ((sdevid == PCI_SUBSYS_DEVID_81XX_BGX) ||
1278 ((sdevid == PCI_SUBSYS_DEVID_83XX_BGX) && (bgx->bgx_id == 2)))
1279 bgx->is_dlm = true;
1280
4863dea3
SG		 1281 bgx_get_qlm_mode(bgx);
1282
de387e11
RR		 1283 err = bgx_init_phy(bgx);
1284 if (err)
1285 goto err_enable;
4863dea3
SG		 1286
1287 bgx_init_hw(bgx);
1288
1289 /* Enable all LMACs */
1290 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1291 err = bgx_lmac_enable(bgx, lmac);
1292 if (err) {
1293 dev_err(dev, "BGX%d failed to enable lmac%d\n",
1294 bgx->bgx_id, lmac);
57aaf63c
SG		 1295 while (lmac)
1296 bgx_lmac_disable(bgx, --lmac);
4863dea3
SG		 1297 goto err_enable;
1298 }
1299 }
1300
1301 return 0;
1302
1303err_enable:
1304 bgx_vnic[bgx->bgx_id] = NULL;
1305err_release_regions:
1306 pci_release_regions(pdev);
1307err_disable_device:
1308 pci_disable_device(pdev);
1309 pci_set_drvdata(pdev, NULL);
1310 return err;
1311}
1312
1313static void bgx_remove(struct pci_dev *pdev)
1314{
1315 struct bgx *bgx = pci_get_drvdata(pdev);
1316 u8 lmac;
1317
1318 /* Disable all LMACs */
1319 for (lmac = 0; lmac < bgx->lmac_count; lmac++)
1320 bgx_lmac_disable(bgx, lmac);
1321
1322 bgx_vnic[bgx->bgx_id] = NULL;
1323 pci_release_regions(pdev);
1324 pci_disable_device(pdev);
1325 pci_set_drvdata(pdev, NULL);
1326}
1327
1328static struct pci_driver bgx_driver = {
1329 .name = DRV_NAME,
1330 .id_table = bgx_id_table,
1331 .probe = bgx_probe,
1332 .remove = bgx_remove,
1333};
1334
1335static int __init bgx_init_module(void)
1336{
1337 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1338
1339 return pci_register_driver(&bgx_driver);
1340}
1341
1342static void __exit bgx_cleanup_module(void)
1343{
1344 pci_unregister_driver(&bgx_driver);
1345}
1346
1347module_init(bgx_init_module);
1348module_exit(bgx_cleanup_module);
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