[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / chelsio / cxgb4 / cudbg_entity.h

/*
 *  Copyright (C) 2017 Chelsio Communications.  All rights reserved.
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms and conditions of the GNU General Public License,
 *  version 2, as published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 *  more details.
 *
 *  The full GNU General Public License is included in this distribution in
 *  the file called "COPYING".
 *
 */

#ifndef __CUDBG_ENTITY_H__
#define __CUDBG_ENTITY_H__

#define EDC0_FLAG 3
#define EDC1_FLAG 4

#define CUDBG_ENTITY_SIGNATURE 0xCCEDB001

struct card_mem {
	u16 size_edc0;
	u16 size_edc1;
	u16 mem_flag;
};

struct cudbg_mbox_log {
	struct mbox_cmd entry;
	u32 hi[MBOX_LEN / 8];
	u32 lo[MBOX_LEN / 8];
};

struct cudbg_cim_qcfg {
	u8 chip;
	u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
	u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
	u16 thres[CIM_NUM_IBQ];
	u32 obq_wr[2 * CIM_NUM_OBQ_T5];
	u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)];
};

struct cudbg_rss_vf_conf {
	u32 rss_vf_vfl;
	u32 rss_vf_vfh;
};

struct cudbg_pm_stats {
	u32 tx_cnt[T6_PM_NSTATS];
	u32 rx_cnt[T6_PM_NSTATS];
	u64 tx_cyc[T6_PM_NSTATS];
	u64 rx_cyc[T6_PM_NSTATS];
};

struct cudbg_hw_sched {
	u32 kbps[NTX_SCHED];
	u32 ipg[NTX_SCHED];
	u32 pace_tab[NTX_SCHED];
	u32 mode;
	u32 map;
};

struct ireg_field {
	u32 ireg_addr;
	u32 ireg_data;
	u32 ireg_local_offset;
	u32 ireg_offset_range;
};

struct ireg_buf {
	struct ireg_field tp_pio;
	u32 outbuf[32];
};

struct cudbg_ulprx_la {
	u32 data[ULPRX_LA_SIZE * 8];
	u32 size;
};

struct cudbg_tp_la {
	u32 size;
	u32 mode;
	u8 data[0];
};

struct cudbg_cim_pif_la {
	int size;
	u8 data[0];
};

struct cudbg_clk_info {
	u64 retransmit_min;
	u64 retransmit_max;
	u64 persist_timer_min;
	u64 persist_timer_max;
	u64 keepalive_idle_timer;
	u64 keepalive_interval;
	u64 initial_srtt;
	u64 finwait2_timer;
	u32 dack_timer;
	u32 res;
	u32 cclk_ps;
	u32 tre;
	u32 dack_re;
};

struct cudbg_tid_info_region {
	u32 ntids;
	u32 nstids;
	u32 stid_base;
	u32 hash_base;

	u32 natids;
	u32 nftids;
	u32 ftid_base;
	u32 aftid_base;
	u32 aftid_end;

	u32 sftid_base;
	u32 nsftids;

	u32 uotid_base;
	u32 nuotids;

	u32 sb;
	u32 flags;
	u32 le_db_conf;
	u32 ip_users;
	u32 ipv6_users;

	u32 hpftid_base;
	u32 nhpftids;
};

#define CUDBG_TID_INFO_REV 1

struct cudbg_tid_info_region_rev1 {
	struct cudbg_ver_hdr ver_hdr;
	struct cudbg_tid_info_region tid;
	u32 tid_start;
	u32 reserved[16];
};

#define CUDBG_MAX_RPLC_SIZE 128

struct cudbg_mps_tcam {
	u64 mask;
	u32 rplc[8];
	u32 idx;
	u32 cls_lo;
	u32 cls_hi;
	u32 rplc_size;
	u32 vniy;
	u32 vnix;
	u32 dip_hit;
	u32 vlan_vld;
	u32 repli;
	u16 ivlan;
	u8 addr[ETH_ALEN];
	u8 lookup_type;
	u8 port_num;
	u8 reserved[2];
};

#define CUDBG_VPD_PF_SIZE 0x800
#define CUDBG_SCFG_VER_ADDR 0x06
#define CUDBG_SCFG_VER_LEN 4
#define CUDBG_VPD_VER_ADDR 0x18c7
#define CUDBG_VPD_VER_LEN 2

struct cudbg_vpd_data {
	u8 sn[SERNUM_LEN + 1];
	u8 bn[PN_LEN + 1];
	u8 na[MACADDR_LEN + 1];
	u8 mn[ID_LEN + 1];
	u16 fw_major;
	u16 fw_minor;
	u16 fw_micro;
	u16 fw_build;
	u32 scfg_vers;
	u32 vpd_vers;
};

#define CUDBG_NUM_ULPTX 11
#define CUDBG_NUM_ULPTX_READ 512

struct cudbg_ulptx_la {
	u32 rdptr[CUDBG_NUM_ULPTX];
	u32 wrptr[CUDBG_NUM_ULPTX];
	u32 rddata[CUDBG_NUM_ULPTX];
	u32 rd_data[CUDBG_NUM_ULPTX][CUDBG_NUM_ULPTX_READ];
};

#define CUDBG_CHAC_PBT_ADDR 0x2800
#define CUDBG_CHAC_PBT_LRF  0x3000
#define CUDBG_CHAC_PBT_DATA 0x3800
#define CUDBG_PBT_DYNAMIC_ENTRIES 8
#define CUDBG_PBT_STATIC_ENTRIES 16
#define CUDBG_LRF_ENTRIES 8
#define CUDBG_PBT_DATA_ENTRIES 512

struct cudbg_pbt_tables {
	u32 pbt_dynamic[CUDBG_PBT_DYNAMIC_ENTRIES];
	u32 pbt_static[CUDBG_PBT_STATIC_ENTRIES];
	u32 lrf_table[CUDBG_LRF_ENTRIES];
	u32 pbt_data[CUDBG_PBT_DATA_ENTRIES];
};

#define IREG_NUM_ELEM 4

static const u32 t6_tp_pio_array[][IREG_NUM_ELEM] = {
	{0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */
	{0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */
	{0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */
	{0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */
	{0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */
	{0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */
	{0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */
	{0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */
	{0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */
	{0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */
	{0x7e40, 0x7e44, 0x24a, 3}, /* t6_tp_pio_regs_24c */
	{0x7e40, 0x7e44, 0x8C0, 1} /* t6_tp_pio_regs_8c0 */
};

static const u32 t5_tp_pio_array[][IREG_NUM_ELEM] = {
	{0x7e40, 0x7e44, 0x020, 28}, /* t5_tp_pio_regs_20_to_3b */
	{0x7e40, 0x7e44, 0x040, 19}, /* t5_tp_pio_regs_40_to_52 */
	{0x7e40, 0x7e44, 0x054, 2}, /* t5_tp_pio_regs_54_to_55 */
	{0x7e40, 0x7e44, 0x060, 13}, /* t5_tp_pio_regs_60_to_6c */
	{0x7e40, 0x7e44, 0x06F, 1}, /* t5_tp_pio_regs_6f */
	{0x7e40, 0x7e44, 0x120, 4}, /* t5_tp_pio_regs_120_to_123 */
	{0x7e40, 0x7e44, 0x12b, 2}, /* t5_tp_pio_regs_12b_to_12c */
	{0x7e40, 0x7e44, 0x12f, 21}, /* t5_tp_pio_regs_12f_to_143 */
	{0x7e40, 0x7e44, 0x145, 19}, /* t5_tp_pio_regs_145_to_157 */
	{0x7e40, 0x7e44, 0x230, 25}, /* t5_tp_pio_regs_230_to_248 */
	{0x7e40, 0x7e44, 0x8C0, 1} /* t5_tp_pio_regs_8c0 */
};

static const u32 t6_tp_tm_pio_array[][IREG_NUM_ELEM] = {
	{0x7e18, 0x7e1c, 0x0, 12}
};

static const u32 t5_tp_tm_pio_array[][IREG_NUM_ELEM] = {
	{0x7e18, 0x7e1c, 0x0, 12}
};

static const u32 t6_tp_mib_index_array[6][IREG_NUM_ELEM] = {
	{0x7e50, 0x7e54, 0x0, 13},
	{0x7e50, 0x7e54, 0x10, 6},
	{0x7e50, 0x7e54, 0x18, 21},
	{0x7e50, 0x7e54, 0x30, 32},
	{0x7e50, 0x7e54, 0x50, 22},
	{0x7e50, 0x7e54, 0x68, 12}
};

static const u32 t5_tp_mib_index_array[9][IREG_NUM_ELEM] = {
	{0x7e50, 0x7e54, 0x0, 13},
	{0x7e50, 0x7e54, 0x10, 6},
	{0x7e50, 0x7e54, 0x18, 8},
	{0x7e50, 0x7e54, 0x20, 13},
	{0x7e50, 0x7e54, 0x30, 16},
	{0x7e50, 0x7e54, 0x40, 16},
	{0x7e50, 0x7e54, 0x50, 16},
	{0x7e50, 0x7e54, 0x60, 6},
	{0x7e50, 0x7e54, 0x68, 4}
};

static const u32 t5_sge_dbg_index_array[2][IREG_NUM_ELEM] = {
	{0x10cc, 0x10d0, 0x0, 16},
	{0x10cc, 0x10d4, 0x0, 16},
};

static const u32 t5_pcie_pdbg_array[][IREG_NUM_ELEM] = {
	{0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */
	{0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */
	{0x5a04, 0x5a0c, 0x41, 0x10}, /* t5_pcie_pdbg_regs_41_to_50 */
};

static const u32 t5_pcie_cdbg_array[][IREG_NUM_ELEM] = {
	{0x5a10, 0x5a18, 0x00, 0x20}, /* t5_pcie_cdbg_regs_00_to_20 */
	{0x5a10, 0x5a18, 0x21, 0x18}, /* t5_pcie_cdbg_regs_21_to_37 */
};

static const u32 t5_pm_rx_array[][IREG_NUM_ELEM] = {
	{0x8FD0, 0x8FD4, 0x10000, 0x20}, /* t5_pm_rx_regs_10000_to_10020 */
	{0x8FD0, 0x8FD4, 0x10021, 0x0D}, /* t5_pm_rx_regs_10021_to_1002c */
};

static const u32 t5_pm_tx_array[][IREG_NUM_ELEM] = {
	{0x8FF0, 0x8FF4, 0x10000, 0x20}, /* t5_pm_tx_regs_10000_to_10020 */
	{0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */
};

static const u32 t6_ma_ireg_array[][IREG_NUM_ELEM] = {
	{0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */
	{0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */
	{0x78f8, 0x78fc, 0xa800, 20} /* t6_ma_regs_a800_to_a813 */
};

static const u32 t6_ma_ireg_array2[][IREG_NUM_ELEM] = {
	{0x78f8, 0x78fc, 0xe400, 17}, /* t6_ma_regs_e400_to_e600 */
	{0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */
};

static const u32 t6_up_cim_reg_array[][IREG_NUM_ELEM] = {
	{0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
	{0x7b50, 0x7b54, 0x2080, 0x1d}, /* up_cim_2080_to_20fc */
	{0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
	{0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
	{0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
	{0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
	{0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
	{0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
	{0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
	{0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
	{0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
	{0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
	{0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */

};

static const u32 t5_up_cim_reg_array[][IREG_NUM_ELEM] = {
	{0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
	{0x7b50, 0x7b54, 0x2080, 0x19}, /* up_cim_2080_to_20ec */
	{0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
	{0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
	{0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
	{0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
	{0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
	{0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
	{0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
	{0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
	{0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
	{0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
	{0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */
};

static const u32 t6_hma_ireg_array[][IREG_NUM_ELEM] = {
	{0x51320, 0x51324, 0xa000, 32} /* t6_hma_regs_a000_to_a01f */
};
#endif /* __CUDBG_ENTITY_H__ */
Commit	Line	Data
b33af022 RL	1	/*
	2	* Copyright (C) 2017 Chelsio Communications. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* The full GNU General Public License is included in this distribution in
	14	* the file called "COPYING".
	15	*
	16	*/
	17
	18	#ifndef __CUDBG_ENTITY_H__
	19	#define __CUDBG_ENTITY_H__
	20
	21	#define EDC0_FLAG 3
	22	#define EDC1_FLAG 4
	23
9030e498 RL	24	#define CUDBG_ENTITY_SIGNATURE 0xCCEDB001
9030e498 RL	25
b33af022 RL	26	struct card_mem {
	27	u16 size_edc0;
	28	u16 size_edc1;
	29	u16 mem_flag;
	30	};
844d1b6f RL	31
	32	struct cudbg_mbox_log {
	33	struct mbox_cmd entry;
	34	u32 hi[MBOX_LEN / 8];
	35	u32 lo[MBOX_LEN / 8];
	36	};
4359cf33	37
3044d0fb RL	38	struct cudbg_cim_qcfg {
	39	u8 chip;
	40	u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
	41	u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
	42	u16 thres[CIM_NUM_IBQ];
	43	u32 obq_wr[2 * CIM_NUM_OBQ_T5];
	44	u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)];
	45	};
	46
28b44556 RL	47	struct cudbg_rss_vf_conf {
	48	u32 rss_vf_vfl;
	49	u32 rss_vf_vfh;
	50	};
	51
6f92a654 RL	52	struct cudbg_pm_stats {
	53	u32 tx_cnt[T6_PM_NSTATS];
	54	u32 rx_cnt[T6_PM_NSTATS];
	55	u64 tx_cyc[T6_PM_NSTATS];
	56	u64 rx_cyc[T6_PM_NSTATS];
	57	};
	58
08c4901b RL	59	struct cudbg_hw_sched {
	60	u32 kbps[NTX_SCHED];
	61	u32 ipg[NTX_SCHED];
	62	u32 pace_tab[NTX_SCHED];
	63	u32 mode;
	64	u32 map;
	65	};
	66
4359cf33 RL	67	struct ireg_field {
	68	u32 ireg_addr;
	69	u32 ireg_data;
	70	u32 ireg_local_offset;
	71	u32 ireg_offset_range;
	72	};
	73
	74	struct ireg_buf {
	75	struct ireg_field tp_pio;
	76	u32 outbuf[32];
	77	};
	78
27887bc7 RL	79	struct cudbg_ulprx_la {
	80	u32 data[ULPRX_LA_SIZE * 8];
	81	u32 size;
	82	};
	83
	84	struct cudbg_tp_la {
	85	u32 size;
	86	u32 mode;
	87	u8 data[0];
	88	};
	89
	90	struct cudbg_cim_pif_la {
	91	int size;
	92	u8 data[0];
	93	};
	94
6f92a654 RL	95	struct cudbg_clk_info {
	96	u64 retransmit_min;
	97	u64 retransmit_max;
	98	u64 persist_timer_min;
	99	u64 persist_timer_max;
	100	u64 keepalive_idle_timer;
	101	u64 keepalive_interval;
	102	u64 initial_srtt;
	103	u64 finwait2_timer;
	104	u32 dack_timer;
	105	u32 res;
	106	u32 cclk_ps;
	107	u32 tre;
	108	u32 dack_re;
	109	};
	110
9030e498 RL	111	struct cudbg_tid_info_region {
	112	u32 ntids;
	113	u32 nstids;
	114	u32 stid_base;
	115	u32 hash_base;
	116
	117	u32 natids;
	118	u32 nftids;
	119	u32 ftid_base;
	120	u32 aftid_base;
	121	u32 aftid_end;
	122
	123	u32 sftid_base;
	124	u32 nsftids;
	125
	126	u32 uotid_base;
	127	u32 nuotids;
	128
	129	u32 sb;
	130	u32 flags;
	131	u32 le_db_conf;
	132	u32 ip_users;
	133	u32 ipv6_users;
	134
	135	u32 hpftid_base;
	136	u32 nhpftids;
	137	};
	138
	139	#define CUDBG_TID_INFO_REV 1
	140
	141	struct cudbg_tid_info_region_rev1 {
	142	struct cudbg_ver_hdr ver_hdr;
	143	struct cudbg_tid_info_region tid;
	144	u32 tid_start;
	145	u32 reserved[16];
	146	};
	147
b289593e RL	148	#define CUDBG_MAX_RPLC_SIZE 128
	149
	150	struct cudbg_mps_tcam {
	151	u64 mask;
	152	u32 rplc[8];
	153	u32 idx;
	154	u32 cls_lo;
	155	u32 cls_hi;
	156	u32 rplc_size;
	157	u32 vniy;
	158	u32 vnix;
	159	u32 dip_hit;
	160	u32 vlan_vld;
	161	u32 repli;
	162	u16 ivlan;
	163	u8 addr[ETH_ALEN];
	164	u8 lookup_type;
	165	u8 port_num;
	166	u8 reserved[2];
	167	};
	168
940c9c45 RL	169	#define CUDBG_VPD_PF_SIZE 0x800
	170	#define CUDBG_SCFG_VER_ADDR 0x06
	171	#define CUDBG_SCFG_VER_LEN 4
	172	#define CUDBG_VPD_VER_ADDR 0x18c7
	173	#define CUDBG_VPD_VER_LEN 2
	174
6f92a654 RL	175	struct cudbg_vpd_data {
	176	u8 sn[SERNUM_LEN + 1];
	177	u8 bn[PN_LEN + 1];
	178	u8 na[MACADDR_LEN + 1];
	179	u8 mn[ID_LEN + 1];
	180	u16 fw_major;
	181	u16 fw_minor;
	182	u16 fw_micro;
	183	u16 fw_build;
	184	u32 scfg_vers;
	185	u32 vpd_vers;
	186	};
	187
27887bc7 RL	188	#define CUDBG_NUM_ULPTX 11
	189	#define CUDBG_NUM_ULPTX_READ 512
	190
	191	struct cudbg_ulptx_la {
	192	u32 rdptr[CUDBG_NUM_ULPTX];
	193	u32 wrptr[CUDBG_NUM_ULPTX];
	194	u32 rddata[CUDBG_NUM_ULPTX];
	195	u32 rd_data[CUDBG_NUM_ULPTX][CUDBG_NUM_ULPTX_READ];
	196	};
	197
db8cd7ce RL	198	#define CUDBG_CHAC_PBT_ADDR 0x2800
	199	#define CUDBG_CHAC_PBT_LRF 0x3000
	200	#define CUDBG_CHAC_PBT_DATA 0x3800
	201	#define CUDBG_PBT_DYNAMIC_ENTRIES 8
	202	#define CUDBG_PBT_STATIC_ENTRIES 16
	203	#define CUDBG_LRF_ENTRIES 8
	204	#define CUDBG_PBT_DATA_ENTRIES 512
	205
	206	struct cudbg_pbt_tables {
	207	u32 pbt_dynamic[CUDBG_PBT_DYNAMIC_ENTRIES];
	208	u32 pbt_static[CUDBG_PBT_STATIC_ENTRIES];
	209	u32 lrf_table[CUDBG_LRF_ENTRIES];
	210	u32 pbt_data[CUDBG_PBT_DATA_ENTRIES];
	211	};
	212
4359cf33 RL	213	#define IREG_NUM_ELEM 4
	214
	215	static const u32 t6_tp_pio_array[][IREG_NUM_ELEM] = {
	216	{0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */
	217	{0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */
	218	{0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */
	219	{0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */
	220	{0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */
	221	{0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */
	222	{0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */
	223	{0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */
	224	{0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */
	225	{0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */
	226	{0x7e40, 0x7e44, 0x24a, 3}, /* t6_tp_pio_regs_24c */
	227	{0x7e40, 0x7e44, 0x8C0, 1} /* t6_tp_pio_regs_8c0 */
	228	};
	229
	230	static const u32 t5_tp_pio_array[][IREG_NUM_ELEM] = {
	231	{0x7e40, 0x7e44, 0x020, 28}, /* t5_tp_pio_regs_20_to_3b */
	232	{0x7e40, 0x7e44, 0x040, 19}, /* t5_tp_pio_regs_40_to_52 */
	233	{0x7e40, 0x7e44, 0x054, 2}, /* t5_tp_pio_regs_54_to_55 */
	234	{0x7e40, 0x7e44, 0x060, 13}, /* t5_tp_pio_regs_60_to_6c */
	235	{0x7e40, 0x7e44, 0x06F, 1}, /* t5_tp_pio_regs_6f */
	236	{0x7e40, 0x7e44, 0x120, 4}, /* t5_tp_pio_regs_120_to_123 */
	237	{0x7e40, 0x7e44, 0x12b, 2}, /* t5_tp_pio_regs_12b_to_12c */
	238	{0x7e40, 0x7e44, 0x12f, 21}, /* t5_tp_pio_regs_12f_to_143 */
	239	{0x7e40, 0x7e44, 0x145, 19}, /* t5_tp_pio_regs_145_to_157 */
	240	{0x7e40, 0x7e44, 0x230, 25}, /* t5_tp_pio_regs_230_to_248 */
	241	{0x7e40, 0x7e44, 0x8C0, 1} /* t5_tp_pio_regs_8c0 */
	242	};
	243
	244	static const u32 t6_tp_tm_pio_array[][IREG_NUM_ELEM] = {
	245	{0x7e18, 0x7e1c, 0x0, 12}
	246	};
	247
	248	static const u32 t5_tp_tm_pio_array[][IREG_NUM_ELEM] = {
	249	{0x7e18, 0x7e1c, 0x0, 12}
	250	};
	251
	252	static const u32 t6_tp_mib_index_array[6][IREG_NUM_ELEM] = {
	253	{0x7e50, 0x7e54, 0x0, 13},
	254	{0x7e50, 0x7e54, 0x10, 6},
	255	{0x7e50, 0x7e54, 0x18, 21},
	256	{0x7e50, 0x7e54, 0x30, 32},
	257	{0x7e50, 0x7e54, 0x50, 22},
	258	{0x7e50, 0x7e54, 0x68, 12}
	259	};
	260
	261	static const u32 t5_tp_mib_index_array[9][IREG_NUM_ELEM] = {
	262	{0x7e50, 0x7e54, 0x0, 13},
	263	{0x7e50, 0x7e54, 0x10, 6},
	264	{0x7e50, 0x7e54, 0x18, 8},
	265	{0x7e50, 0x7e54, 0x20, 13},
	266	{0x7e50, 0x7e54, 0x30, 16},
	267	{0x7e50, 0x7e54, 0x40, 16},
	268	{0x7e50, 0x7e54, 0x50, 16},
	269	{0x7e50, 0x7e54, 0x60, 6},
	270	{0x7e50, 0x7e54, 0x68, 4}
	271	};
270d39bf RL	272
	273	static const u32 t5_sge_dbg_index_array[2][IREG_NUM_ELEM] = {
	274	{0x10cc, 0x10d0, 0x0, 16},
	275	{0x10cc, 0x10d4, 0x0, 16},
	276	};
	277
	278	static const u32 t5_pcie_pdbg_array[][IREG_NUM_ELEM] = {
	279	{0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */
	280	{0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */
	281	{0x5a04, 0x5a0c, 0x41, 0x10}, /* t5_pcie_pdbg_regs_41_to_50 */
	282	};
	283
	284	static const u32 t5_pcie_cdbg_array[][IREG_NUM_ELEM] = {
	285	{0x5a10, 0x5a18, 0x00, 0x20}, /* t5_pcie_cdbg_regs_00_to_20 */
	286	{0x5a10, 0x5a18, 0x21, 0x18}, /* t5_pcie_cdbg_regs_21_to_37 */
	287	};
	288
	289	static const u32 t5_pm_rx_array[][IREG_NUM_ELEM] = {
	290	{0x8FD0, 0x8FD4, 0x10000, 0x20}, /* t5_pm_rx_regs_10000_to_10020 */
	291	{0x8FD0, 0x8FD4, 0x10021, 0x0D}, /* t5_pm_rx_regs_10021_to_1002c */
	292	};
	293
	294	static const u32 t5_pm_tx_array[][IREG_NUM_ELEM] = {
	295	{0x8FF0, 0x8FF4, 0x10000, 0x20}, /* t5_pm_tx_regs_10000_to_10020 */
	296	{0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */
	297	};
	298
	299	static const u32 t6_ma_ireg_array[][IREG_NUM_ELEM] = {
	300	{0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */
	301	{0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */
	302	{0x78f8, 0x78fc, 0xa800, 20} /* t6_ma_regs_a800_to_a813 */
	303	};
	304
	305	static const u32 t6_ma_ireg_array2[][IREG_NUM_ELEM] = {
	306	{0x78f8, 0x78fc, 0xe400, 17}, /* t6_ma_regs_e400_to_e600 */
	307	{0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */
	308	};
	309
	310	static const u32 t6_up_cim_reg_array[][IREG_NUM_ELEM] = {
	311	{0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
	312	{0x7b50, 0x7b54, 0x2080, 0x1d}, /* up_cim_2080_to_20fc */
	313	{0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
	314	{0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
	315	{0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
	316	{0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
	317	{0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
	318	{0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
	319	{0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
	320	{0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
	321	{0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
	322	{0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
	323	{0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */
	324
	325	};
	326
	327	static const u32 t5_up_cim_reg_array[][IREG_NUM_ELEM] = {
	328	{0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
	329	{0x7b50, 0x7b54, 0x2080, 0x19}, /* up_cim_2080_to_20ec */
	330	{0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
	331	{0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
	332	{0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
	333	{0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
	334	{0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
	335	{0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
336	{0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
337	{0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
338	{0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
339	{0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
340	{0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */
341	};
342
343	static const u32 t6_hma_ireg_array[][IREG_NUM_ELEM] = {
344	{0x51320, 0x51324, 0xa000, 32} /* t6_hma_regs_a000_to_a01f */
345	};
b33af022	346	#endif /* __CUDBG_ENTITY_H__ */