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enic: fix rx skb checksum
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / cisco / enic / enic_main.c
CommitLineData
01f2e4ea 1/*
29046f9b 2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
01f2e4ea
SF		 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4 *
5 * This program is free software; you may redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
16 * SOFTWARE.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/string.h>
23#include <linux/errno.h>
24#include <linux/types.h>
25#include <linux/init.h>
a6b7a407 26#include <linux/interrupt.h>
01f2e4ea
SF		 27#include <linux/workqueue.h>
28#include <linux/pci.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
01789349 31#include <linux/if.h>
01f2e4ea
SF		 32#include <linux/if_ether.h>
33#include <linux/if_vlan.h>
01f2e4ea
SF		 34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/ipv6.h>
37#include <linux/tcp.h>
29046f9b 38#include <linux/rtnetlink.h>
70c71606 39#include <linux/prefetch.h>
b7c6bfb7 40#include <net/ip6_checksum.h>
7c2ce6e6 41#include <linux/ktime.h>
b6e97c13
GV		 42#ifdef CONFIG_RFS_ACCEL
43#include <linux/cpu_rmap.h>
44#endif
14747cd9
GV		 45#ifdef CONFIG_NET_RX_BUSY_POLL
46#include <net/busy_poll.h>
47#endif
01f2e4ea
SF		 48
49#include "cq_enet_desc.h"
50#include "vnic_dev.h"
51#include "vnic_intr.h"
52#include "vnic_stats.h"
f8bd9091 53#include "vnic_vic.h"
01f2e4ea
SF		 54#include "enic_res.h"
55#include "enic.h"
51987461 56#include "enic_dev.h"
b3abfbd2 57#include "enic_pp.h"
a145df23 58#include "enic_clsf.h"
01f2e4ea
SF		 59
60#define ENIC_NOTIFY_TIMER_PERIOD (2 * HZ)
ea0d7d91
SF		 61#define WQ_ENET_MAX_DESC_LEN (1 << WQ_ENET_LEN_BITS)
62#define MAX_TSO (1 << 16)
63#define ENIC_DESC_MAX_SPLITS (MAX_TSO / WQ_ENET_MAX_DESC_LEN + 1)
64
65#define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */
f8bd9091 66#define PCI_DEVICE_ID_CISCO_VIC_ENET_DYN 0x0044 /* enet dynamic vnic */
3a4adef5 67#define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */
01f2e4ea 68
a03bb56e
GV		 69#define RX_COPYBREAK_DEFAULT 256
70
01f2e4ea 71/* Supported devices */
9baa3c34 72static const struct pci_device_id enic_id_table[] = {
ea0d7d91 73 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET) },
f8bd9091 74 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_DYN) },
3a4adef5 75 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) },
01f2e4ea
SF		 76 { 0, } /* end of table */
77};
78
79MODULE_DESCRIPTION(DRV_DESCRIPTION);
80MODULE_AUTHOR("Scott Feldman <scofeldm@cisco.com>");
81MODULE_LICENSE("GPL");
82MODULE_VERSION(DRV_VERSION);
83MODULE_DEVICE_TABLE(pci, enic_id_table);
84
7c2ce6e6
SS		 85#define ENIC_LARGE_PKT_THRESHOLD 1000
86#define ENIC_MAX_COALESCE_TIMERS 10
87/* Interrupt moderation table, which will be used to decide the
88 * coalescing timer values
89 * {rx_rate in Mbps, mapping percentage of the range}
90 */
91struct enic_intr_mod_table mod_table[ENIC_MAX_COALESCE_TIMERS + 1] = {
92 {4000, 0},
93 {4400, 10},
94 {5060, 20},
95 {5230, 30},
96 {5540, 40},
97 {5820, 50},
98 {6120, 60},
99 {6435, 70},
100 {6745, 80},
101 {7000, 90},
102 {0xFFFFFFFF, 100}
103};
104
105/* This table helps the driver to pick different ranges for rx coalescing
106 * timer depending on the link speed.
107 */
108struct enic_intr_mod_range mod_range[ENIC_MAX_LINK_SPEEDS] = {
109 {0, 0}, /* 0 - 4 Gbps */
110 {0, 3}, /* 4 - 10 Gbps */
111 {3, 6}, /* 10 - 40 Gbps */
112};
113
3f192795 114int enic_is_dynamic(struct enic *enic)
f8bd9091
SF		 115{
116 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_DYN;
117}
118
8749b427
RP		 119int enic_sriov_enabled(struct enic *enic)
120{
121 return (enic->priv_flags & ENIC_SRIOV_ENABLED) ? 1 : 0;
122}
123
3a4adef5
RP		 124static int enic_is_sriov_vf(struct enic *enic)
125{
126 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_VF;
127}
128
889d13f5
RP		 129int enic_is_valid_vf(struct enic *enic, int vf)
130{
131#ifdef CONFIG_PCI_IOV
132 return vf >= 0 && vf < enic->num_vfs;
133#else
134 return 0;
135#endif
136}
137
01f2e4ea
SF		 138static void enic_free_wq_buf(struct vnic_wq *wq, struct vnic_wq_buf *buf)
139{
140 struct enic *enic = vnic_dev_priv(wq->vdev);
141
142 if (buf->sop)
143 pci_unmap_single(enic->pdev, buf->dma_addr,
144 buf->len, PCI_DMA_TODEVICE);
145 else
146 pci_unmap_page(enic->pdev, buf->dma_addr,
147 buf->len, PCI_DMA_TODEVICE);
148
149 if (buf->os_buf)
150 dev_kfree_skb_any(buf->os_buf);
151}
152
153static void enic_wq_free_buf(struct vnic_wq *wq,
154 struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque)
155{
156 enic_free_wq_buf(wq, buf);
157}
158
159static int enic_wq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
160 u8 type, u16 q_number, u16 completed_index, void *opaque)
161{
162 struct enic *enic = vnic_dev_priv(vdev);
163
164 spin_lock(&enic->wq_lock[q_number]);
165
166 vnic_wq_service(&enic->wq[q_number], cq_desc,
167 completed_index, enic_wq_free_buf,
168 opaque);
169
822473b6 170 if (netif_tx_queue_stopped(netdev_get_tx_queue(enic->netdev, q_number)) &&
ea0d7d91
SF		 171 vnic_wq_desc_avail(&enic->wq[q_number]) >=
172 (MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS))
822473b6 173 netif_wake_subqueue(enic->netdev, q_number);
01f2e4ea
SF		 174
175 spin_unlock(&enic->wq_lock[q_number]);
176
177 return 0;
178}
179
180static void enic_log_q_error(struct enic *enic)
181{
182 unsigned int i;
183 u32 error_status;
184
185 for (i = 0; i < enic->wq_count; i++) {
186 error_status = vnic_wq_error_status(&enic->wq[i]);
187 if (error_status)
a7a79deb
VK		 188 netdev_err(enic->netdev, "WQ[%d] error_status %d\n",
189 i, error_status);
01f2e4ea
SF		 190 }
191
192 for (i = 0; i < enic->rq_count; i++) {
193 error_status = vnic_rq_error_status(&enic->rq[i]);
194 if (error_status)
a7a79deb
VK		 195 netdev_err(enic->netdev, "RQ[%d] error_status %d\n",
196 i, error_status);
01f2e4ea
SF		 197 }
198}
199
383ab92f 200static void enic_msglvl_check(struct enic *enic)
01f2e4ea 201{
383ab92f 202 u32 msg_enable = vnic_dev_msg_lvl(enic->vdev);
01f2e4ea 203
383ab92f 204 if (msg_enable != enic->msg_enable) {
a7a79deb
VK		 205 netdev_info(enic->netdev, "msg lvl changed from 0x%x to 0x%x\n",
206 enic->msg_enable, msg_enable);
383ab92f 207 enic->msg_enable = msg_enable;
01f2e4ea
SF		 208 }
209}
210
211static void enic_mtu_check(struct enic *enic)
212{
213 u32 mtu = vnic_dev_mtu(enic->vdev);
a7a79deb 214 struct net_device *netdev = enic->netdev;
01f2e4ea 215
491598a4 216 if (mtu && mtu != enic->port_mtu) {
7c844599 217 enic->port_mtu = mtu;
7335903c 218 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
c97c894d
RP		 219 mtu = max_t(int, ENIC_MIN_MTU,
220 min_t(int, ENIC_MAX_MTU, mtu));
221 if (mtu != netdev->mtu)
222 schedule_work(&enic->change_mtu_work);
223 } else {
224 if (mtu < netdev->mtu)
225 netdev_warn(netdev,
226 "interface MTU (%d) set higher "
227 "than switch port MTU (%d)\n",
228 netdev->mtu, mtu);
229 }
01f2e4ea
SF		 230 }
231}
232
383ab92f 233static void enic_link_check(struct enic *enic)
01f2e4ea 234{
383ab92f
VK		 235 int link_status = vnic_dev_link_status(enic->vdev);
236 int carrier_ok = netif_carrier_ok(enic->netdev);
01f2e4ea 237
383ab92f 238 if (link_status && !carrier_ok) {
a7a79deb 239 netdev_info(enic->netdev, "Link UP\n");
383ab92f
VK		 240 netif_carrier_on(enic->netdev);
241 } else if (!link_status && carrier_ok) {
a7a79deb 242 netdev_info(enic->netdev, "Link DOWN\n");
383ab92f 243 netif_carrier_off(enic->netdev);
01f2e4ea
SF		 244 }
245}
246
247static void enic_notify_check(struct enic *enic)
248{
249 enic_msglvl_check(enic);
250 enic_mtu_check(enic);
251 enic_link_check(enic);
252}
253
254#define ENIC_TEST_INTR(pba, i) (pba & (1 << i))
255
256static irqreturn_t enic_isr_legacy(int irq, void *data)
257{
258 struct net_device *netdev = data;
259 struct enic *enic = netdev_priv(netdev);
717258ba
VK		 260 unsigned int io_intr = enic_legacy_io_intr();
261 unsigned int err_intr = enic_legacy_err_intr();
262 unsigned int notify_intr = enic_legacy_notify_intr();
01f2e4ea
SF		 263 u32 pba;
264
717258ba 265 vnic_intr_mask(&enic->intr[io_intr]);
01f2e4ea
SF		 266
267 pba = vnic_intr_legacy_pba(enic->legacy_pba);
268 if (!pba) {
717258ba 269 vnic_intr_unmask(&enic->intr[io_intr]);
01f2e4ea
SF		 270 return IRQ_NONE; /* not our interrupt */
271 }
272
717258ba
VK		 273 if (ENIC_TEST_INTR(pba, notify_intr)) {
274 vnic_intr_return_all_credits(&enic->intr[notify_intr]);
01f2e4ea 275 enic_notify_check(enic);
ed8af6b2 276 }
01f2e4ea 277
717258ba
VK		 278 if (ENIC_TEST_INTR(pba, err_intr)) {
279 vnic_intr_return_all_credits(&enic->intr[err_intr]);
01f2e4ea
SF		 280 enic_log_q_error(enic);
281 /* schedule recovery from WQ/RQ error */
282 schedule_work(&enic->reset);
283 return IRQ_HANDLED;
284 }
285
db40b3f5
GV		 286 if (ENIC_TEST_INTR(pba, io_intr))
287 napi_schedule_irqoff(&enic->napi[0]);
288 else
717258ba 289 vnic_intr_unmask(&enic->intr[io_intr]);
01f2e4ea
SF		 290
291 return IRQ_HANDLED;
292}
293
294static irqreturn_t enic_isr_msi(int irq, void *data)
295{
296 struct enic *enic = data;
297
298 /* With MSI, there is no sharing of interrupts, so this is
299 * our interrupt and there is no need to ack it. The device
300 * is not providing per-vector masking, so the OS will not
301 * write to PCI config space to mask/unmask the interrupt.
302 * We're using mask_on_assertion for MSI, so the device
303 * automatically masks the interrupt when the interrupt is
304 * generated. Later, when exiting polling, the interrupt
305 * will be unmasked (see enic_poll).
306 *
307 * Also, the device uses the same PCIe Traffic Class (TC)
308 * for Memory Write data and MSI, so there are no ordering
309 * issues; the MSI will always arrive at the Root Complex
310 * _after_ corresponding Memory Writes (i.e. descriptor
311 * writes).
312 */
313
db40b3f5 314 napi_schedule_irqoff(&enic->napi[0]);
01f2e4ea
SF		 315
316 return IRQ_HANDLED;
317}
318
4cfe8785 319static irqreturn_t enic_isr_msix(int irq, void *data)
01f2e4ea 320{
717258ba 321 struct napi_struct *napi = data;
01f2e4ea 322
db40b3f5 323 napi_schedule_irqoff(napi);
01f2e4ea
SF		 324
325 return IRQ_HANDLED;
326}
327
01f2e4ea
SF		 328static irqreturn_t enic_isr_msix_err(int irq, void *data)
329{
330 struct enic *enic = data;
717258ba 331 unsigned int intr = enic_msix_err_intr(enic);
01f2e4ea 332
717258ba 333 vnic_intr_return_all_credits(&enic->intr[intr]);
ed8af6b2 334
01f2e4ea
SF		 335 enic_log_q_error(enic);
336
337 /* schedule recovery from WQ/RQ error */
338 schedule_work(&enic->reset);
339
340 return IRQ_HANDLED;
341}
342
343static irqreturn_t enic_isr_msix_notify(int irq, void *data)
344{
345 struct enic *enic = data;
717258ba 346 unsigned int intr = enic_msix_notify_intr(enic);
01f2e4ea 347
717258ba 348 vnic_intr_return_all_credits(&enic->intr[intr]);
01f2e4ea 349 enic_notify_check(enic);
01f2e4ea
SF		 350
351 return IRQ_HANDLED;
352}
353
354static inline void enic_queue_wq_skb_cont(struct enic *enic,
355 struct vnic_wq *wq, struct sk_buff *skb,
1825aca6 356 unsigned int len_left, int loopback)
01f2e4ea 357{
9e903e08 358 const skb_frag_t *frag;
01f2e4ea
SF		 359
360 /* Queue additional data fragments */
361 for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
9e903e08 362 len_left -= skb_frag_size(frag);
01f2e4ea 363 enic_queue_wq_desc_cont(wq, skb,
4bf5adbf 364 skb_frag_dma_map(&enic->pdev->dev,
9e903e08 365 frag, 0, skb_frag_size(frag),
5d6bcdfe 366 DMA_TO_DEVICE),
9e903e08 367 skb_frag_size(frag),
1825aca6
VK		 368 (len_left == 0), /* EOP? */
369 loopback);
01f2e4ea
SF		 370 }
371}
372
373static inline void enic_queue_wq_skb_vlan(struct enic *enic,
374 struct vnic_wq *wq, struct sk_buff *skb,
1825aca6 375 int vlan_tag_insert, unsigned int vlan_tag, int loopback)
01f2e4ea
SF		 376{
377 unsigned int head_len = skb_headlen(skb);
378 unsigned int len_left = skb->len - head_len;
379 int eop = (len_left == 0);
380
ea0d7d91
SF		 381 /* Queue the main skb fragment. The fragments are no larger
382 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
383 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
384 * per fragment is queued.
385 */
01f2e4ea
SF		 386 enic_queue_wq_desc(wq, skb,
387 pci_map_single(enic->pdev, skb->data,
388 head_len, PCI_DMA_TODEVICE),
389 head_len,
390 vlan_tag_insert, vlan_tag,
1825aca6 391 eop, loopback);
01f2e4ea
SF		 392
393 if (!eop)
1825aca6 394 enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
01f2e4ea
SF		 395}
396
397static inline void enic_queue_wq_skb_csum_l4(struct enic *enic,
398 struct vnic_wq *wq, struct sk_buff *skb,
1825aca6 399 int vlan_tag_insert, unsigned int vlan_tag, int loopback)
01f2e4ea
SF		 400{
401 unsigned int head_len = skb_headlen(skb);
402 unsigned int len_left = skb->len - head_len;
0d0b1672 403 unsigned int hdr_len = skb_checksum_start_offset(skb);
01f2e4ea
SF		 404 unsigned int csum_offset = hdr_len + skb->csum_offset;
405 int eop = (len_left == 0);
406
ea0d7d91
SF		 407 /* Queue the main skb fragment. The fragments are no larger
408 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
409 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
410 * per fragment is queued.
411 */
01f2e4ea
SF		 412 enic_queue_wq_desc_csum_l4(wq, skb,
413 pci_map_single(enic->pdev, skb->data,
414 head_len, PCI_DMA_TODEVICE),
415 head_len,
416 csum_offset,
417 hdr_len,
418 vlan_tag_insert, vlan_tag,
1825aca6 419 eop, loopback);
01f2e4ea
SF		 420
421 if (!eop)
1825aca6 422 enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
01f2e4ea
SF		 423}
424
425static inline void enic_queue_wq_skb_tso(struct enic *enic,
426 struct vnic_wq *wq, struct sk_buff *skb, unsigned int mss,
1825aca6 427 int vlan_tag_insert, unsigned int vlan_tag, int loopback)
01f2e4ea 428{
ea0d7d91
SF		 429 unsigned int frag_len_left = skb_headlen(skb);
430 unsigned int len_left = skb->len - frag_len_left;
01f2e4ea
SF		 431 unsigned int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
432 int eop = (len_left == 0);
ea0d7d91
SF		 433 unsigned int len;
434 dma_addr_t dma_addr;
435 unsigned int offset = 0;
436 skb_frag_t *frag;
01f2e4ea
SF		 437
438 /* Preload TCP csum field with IP pseudo hdr calculated
439 * with IP length set to zero. HW will later add in length
440 * to each TCP segment resulting from the TSO.
441 */
442
09640e63 443 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
01f2e4ea
SF		 444 ip_hdr(skb)->check = 0;
445 tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
446 ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
09640e63 447 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
01f2e4ea
SF		 448 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
449 &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
450 }
451
ea0d7d91
SF		 452 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
453 * for the main skb fragment
454 */
455 while (frag_len_left) {
456 len = min(frag_len_left, (unsigned int)WQ_ENET_MAX_DESC_LEN);
457 dma_addr = pci_map_single(enic->pdev, skb->data + offset,
458 len, PCI_DMA_TODEVICE);
459 enic_queue_wq_desc_tso(wq, skb,
460 dma_addr,
461 len,
462 mss, hdr_len,
463 vlan_tag_insert, vlan_tag,
1825aca6 464 eop && (len == frag_len_left), loopback);
ea0d7d91
SF		 465 frag_len_left -= len;
466 offset += len;
467 }
01f2e4ea 468
ea0d7d91
SF		 469 if (eop)
470 return;
471
472 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
473 * for additional data fragments
474 */
475 for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
9e903e08
ED		 476 len_left -= skb_frag_size(frag);
477 frag_len_left = skb_frag_size(frag);
4bf5adbf 478 offset = 0;
ea0d7d91
SF		 479
480 while (frag_len_left) {
481 len = min(frag_len_left,
482 (unsigned int)WQ_ENET_MAX_DESC_LEN);
4bf5adbf
IC		 483 dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag,
484 offset, len,
5d6bcdfe 485 DMA_TO_DEVICE);
ea0d7d91
SF		 486 enic_queue_wq_desc_cont(wq, skb,
487 dma_addr,
488 len,
489 (len_left == 0) &&
1825aca6
VK		 490 (len == frag_len_left), /* EOP? */
491 loopback);
ea0d7d91
SF		 492 frag_len_left -= len;
493 offset += len;
494 }
495 }
01f2e4ea
SF		 496}
497
498static inline void enic_queue_wq_skb(struct enic *enic,
499 struct vnic_wq *wq, struct sk_buff *skb)
500{
501 unsigned int mss = skb_shinfo(skb)->gso_size;
502 unsigned int vlan_tag = 0;
503 int vlan_tag_insert = 0;
1825aca6 504 int loopback = 0;
01f2e4ea 505
eab6d18d 506 if (vlan_tx_tag_present(skb)) {
01f2e4ea
SF		 507 /* VLAN tag from trunking driver */
508 vlan_tag_insert = 1;
509 vlan_tag = vlan_tx_tag_get(skb);
1825aca6
VK		 510 } else if (enic->loop_enable) {
511 vlan_tag = enic->loop_tag;
512 loopback = 1;
01f2e4ea
SF		 513 }
514
515 if (mss)
516 enic_queue_wq_skb_tso(enic, wq, skb, mss,
1825aca6 517 vlan_tag_insert, vlan_tag, loopback);
01f2e4ea
SF		 518 else if (skb->ip_summed == CHECKSUM_PARTIAL)
519 enic_queue_wq_skb_csum_l4(enic, wq, skb,
1825aca6 520 vlan_tag_insert, vlan_tag, loopback);
01f2e4ea
SF		 521 else
522 enic_queue_wq_skb_vlan(enic, wq, skb,
1825aca6 523 vlan_tag_insert, vlan_tag, loopback);
01f2e4ea
SF		 524}
525
ed8af6b2 526/* netif_tx_lock held, process context with BHs disabled, or BH */
61357325 527static netdev_tx_t enic_hard_start_xmit(struct sk_buff *skb,
d87fd25d 528 struct net_device *netdev)
01f2e4ea
SF		 529{
530 struct enic *enic = netdev_priv(netdev);
822473b6 531 struct vnic_wq *wq;
822473b6 532 unsigned int txq_map;
f8e34d24 533 struct netdev_queue *txq;
01f2e4ea
SF		 534
535 if (skb->len <= 0) {
98d8a65d 536 dev_kfree_skb_any(skb);
01f2e4ea
SF		 537 return NETDEV_TX_OK;
538 }
539
822473b6 540 txq_map = skb_get_queue_mapping(skb) % enic->wq_count;
541 wq = &enic->wq[txq_map];
f8e34d24 542 txq = netdev_get_tx_queue(netdev, txq_map);
822473b6 543
01f2e4ea
SF		 544 /* Non-TSO sends must fit within ENIC_NON_TSO_MAX_DESC descs,
545 * which is very likely. In the off chance it's going to take
546 * more than * ENIC_NON_TSO_MAX_DESC, linearize the skb.
547 */
548
549 if (skb_shinfo(skb)->gso_size == 0 &&
550 skb_shinfo(skb)->nr_frags + 1 > ENIC_NON_TSO_MAX_DESC &&
551 skb_linearize(skb)) {
98d8a65d 552 dev_kfree_skb_any(skb);
01f2e4ea
SF		 553 return NETDEV_TX_OK;
554 }
555
78e2045d 556 spin_lock(&enic->wq_lock[txq_map]);
01f2e4ea 557
ea0d7d91
SF		 558 if (vnic_wq_desc_avail(wq) <
559 skb_shinfo(skb)->nr_frags + ENIC_DESC_MAX_SPLITS) {
f8e34d24 560 netif_tx_stop_queue(txq);
01f2e4ea 561 /* This is a hard error, log it */
a7a79deb 562 netdev_err(netdev, "BUG! Tx ring full when queue awake!\n");
78e2045d 563 spin_unlock(&enic->wq_lock[txq_map]);
01f2e4ea
SF		 564 return NETDEV_TX_BUSY;
565 }
566
567 enic_queue_wq_skb(enic, wq, skb);
568
ea0d7d91 569 if (vnic_wq_desc_avail(wq) < MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS)
f8e34d24
GV		 570 netif_tx_stop_queue(txq);
571 if (!skb->xmit_more || netif_xmit_stopped(txq))
572 vnic_wq_doorbell(wq);
01f2e4ea 573
78e2045d 574 spin_unlock(&enic->wq_lock[txq_map]);
01f2e4ea
SF		 575
576 return NETDEV_TX_OK;
577}
578
579/* dev_base_lock rwlock held, nominally process context */
f20530bc 580static struct rtnl_link_stats64 *enic_get_stats(struct net_device *netdev,
581 struct rtnl_link_stats64 *net_stats)
01f2e4ea
SF		 582{
583 struct enic *enic = netdev_priv(netdev);
584 struct vnic_stats *stats;
585
383ab92f 586 enic_dev_stats_dump(enic, &stats);
01f2e4ea 587
25f0a061
SF		 588 net_stats->tx_packets = stats->tx.tx_frames_ok;
589 net_stats->tx_bytes = stats->tx.tx_bytes_ok;
590 net_stats->tx_errors = stats->tx.tx_errors;
591 net_stats->tx_dropped = stats->tx.tx_drops;
01f2e4ea 592
25f0a061
SF		 593 net_stats->rx_packets = stats->rx.rx_frames_ok;
594 net_stats->rx_bytes = stats->rx.rx_bytes_ok;
595 net_stats->rx_errors = stats->rx.rx_errors;
596 net_stats->multicast = stats->rx.rx_multicast_frames_ok;
350991e1 597 net_stats->rx_over_errors = enic->rq_truncated_pkts;
bd9fb1a4 598 net_stats->rx_crc_errors = enic->rq_bad_fcs;
350991e1 599 net_stats->rx_dropped = stats->rx.rx_no_bufs + stats->rx.rx_drop;
01f2e4ea 600
25f0a061 601 return net_stats;
01f2e4ea
SF		 602}
603
f009618a
AD		 604static int enic_mc_sync(struct net_device *netdev, const u8 *mc_addr)
605{
606 struct enic *enic = netdev_priv(netdev);
607
608 if (enic->mc_count == ENIC_MULTICAST_PERFECT_FILTERS) {
609 unsigned int mc_count = netdev_mc_count(netdev);
610
611 netdev_warn(netdev, "Registering only %d out of %d multicast addresses\n",
612 ENIC_MULTICAST_PERFECT_FILTERS, mc_count);
613
614 return -ENOSPC;
615 }
616
617 enic_dev_add_addr(enic, mc_addr);
618 enic->mc_count++;
619
620 return 0;
621}
622
623static int enic_mc_unsync(struct net_device *netdev, const u8 *mc_addr)
624{
625 struct enic *enic = netdev_priv(netdev);
626
627 enic_dev_del_addr(enic, mc_addr);
628 enic->mc_count--;
629
630 return 0;
631}
632
633static int enic_uc_sync(struct net_device *netdev, const u8 *uc_addr)
634{
635 struct enic *enic = netdev_priv(netdev);
636
637 if (enic->uc_count == ENIC_UNICAST_PERFECT_FILTERS) {
638 unsigned int uc_count = netdev_uc_count(netdev);
639
640 netdev_warn(netdev, "Registering only %d out of %d unicast addresses\n",
641 ENIC_UNICAST_PERFECT_FILTERS, uc_count);
642
643 return -ENOSPC;
644 }
645
646 enic_dev_add_addr(enic, uc_addr);
647 enic->uc_count++;
648
649 return 0;
650}
651
652static int enic_uc_unsync(struct net_device *netdev, const u8 *uc_addr)
653{
654 struct enic *enic = netdev_priv(netdev);
655
656 enic_dev_del_addr(enic, uc_addr);
657 enic->uc_count--;
658
659 return 0;
660}
661
b3abfbd2 662void enic_reset_addr_lists(struct enic *enic)
01f2e4ea 663{
f009618a
AD		 664 struct net_device *netdev = enic->netdev;
665
666 __dev_uc_unsync(netdev, NULL);
667 __dev_mc_unsync(netdev, NULL);
668
01f2e4ea 669 enic->mc_count = 0;
e0afe53f 670 enic->uc_count = 0;
99ef5639 671 enic->flags = 0;
01f2e4ea
SF		 672}
673
674static int enic_set_mac_addr(struct net_device *netdev, char *addr)
675{
f8bd9091
SF		 676 struct enic *enic = netdev_priv(netdev);
677
7335903c 678 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
f8bd9091
SF		 679 if (!is_valid_ether_addr(addr) && !is_zero_ether_addr(addr))
680 return -EADDRNOTAVAIL;
681 } else {
682 if (!is_valid_ether_addr(addr))
683 return -EADDRNOTAVAIL;
684 }
01f2e4ea
SF		 685
686 memcpy(netdev->dev_addr, addr, netdev->addr_len);
687
688 return 0;
689}
690
f8bd9091
SF		 691static int enic_set_mac_address_dynamic(struct net_device *netdev, void *p)
692{
693 struct enic *enic = netdev_priv(netdev);
694 struct sockaddr *saddr = p;
695 char *addr = saddr->sa_data;
696 int err;
697
698 if (netif_running(enic->netdev)) {
699 err = enic_dev_del_station_addr(enic);
700 if (err)
701 return err;
702 }
703
704 err = enic_set_mac_addr(netdev, addr);
705 if (err)
706 return err;
707
708 if (netif_running(enic->netdev)) {
709 err = enic_dev_add_station_addr(enic);
710 if (err)
711 return err;
712 }
713
714 return err;
715}
716
717static int enic_set_mac_address(struct net_device *netdev, void *p)
718{
294dab25 719 struct sockaddr *saddr = p;
c76fd32d
VK		 720 char *addr = saddr->sa_data;
721 struct enic *enic = netdev_priv(netdev);
722 int err;
723
724 err = enic_dev_del_station_addr(enic);
725 if (err)
726 return err;
727
728 err = enic_set_mac_addr(netdev, addr);
729 if (err)
730 return err;
294dab25 731
c76fd32d 732 return enic_dev_add_station_addr(enic);
f8bd9091
SF		 733}
734
319d7e84
RP		 735/* netif_tx_lock held, BHs disabled */
736static void enic_set_rx_mode(struct net_device *netdev)
737{
738 struct enic *enic = netdev_priv(netdev);
739 int directed = 1;
740 int multicast = (netdev->flags & IFF_MULTICAST) ? 1 : 0;
741 int broadcast = (netdev->flags & IFF_BROADCAST) ? 1 : 0;
742 int promisc = (netdev->flags & IFF_PROMISC) ||
743 netdev_uc_count(netdev) > ENIC_UNICAST_PERFECT_FILTERS;
744 int allmulti = (netdev->flags & IFF_ALLMULTI) ||
745 netdev_mc_count(netdev) > ENIC_MULTICAST_PERFECT_FILTERS;
746 unsigned int flags = netdev->flags |
747 (allmulti ? IFF_ALLMULTI : 0) |
748 (promisc ? IFF_PROMISC : 0);
749
750 if (enic->flags != flags) {
751 enic->flags = flags;
752 enic_dev_packet_filter(enic, directed,
753 multicast, broadcast, promisc, allmulti);
754 }
755
756 if (!promisc) {
f009618a 757 __dev_uc_sync(netdev, enic_uc_sync, enic_uc_unsync);
319d7e84 758 if (!allmulti)
f009618a 759 __dev_mc_sync(netdev, enic_mc_sync, enic_mc_unsync);
319d7e84
RP		 760 }
761}
762
01f2e4ea
SF		 763/* netif_tx_lock held, BHs disabled */
764static void enic_tx_timeout(struct net_device *netdev)
765{
766 struct enic *enic = netdev_priv(netdev);
767 schedule_work(&enic->reset);
768}
769
0b1c00fc
RP		 770static int enic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
771{
772 struct enic *enic = netdev_priv(netdev);
3f192795
RP		 773 struct enic_port_profile *pp;
774 int err;
0b1c00fc 775
3f192795
RP		 776 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
777 if (err)
778 return err;
0b1c00fc 779
b8622cbd 780 if (is_valid_ether_addr(mac) || is_zero_ether_addr(mac)) {
b4765833
RP		 781 if (vf == PORT_SELF_VF) {
782 memcpy(pp->vf_mac, mac, ETH_ALEN);
783 return 0;
784 } else {
785 /*
786 * For sriov vf's set the mac in hw
787 */
788 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
789 vnic_dev_set_mac_addr, mac);
790 return enic_dev_status_to_errno(err);
791 }
0b1c00fc
RP		 792 } else
793 return -EINVAL;
794}
795
f8bd9091
SF		 796static int enic_set_vf_port(struct net_device *netdev, int vf,
797 struct nlattr *port[])
798{
799 struct enic *enic = netdev_priv(netdev);
b3abfbd2 800 struct enic_port_profile prev_pp;
3f192795 801 struct enic_port_profile *pp;
b3abfbd2 802 int err = 0, restore_pp = 1;
08f382eb 803
3f192795
RP		 804 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
805 if (err)
806 return err;
08f382eb 807
b3abfbd2
RP		 808 if (!port[IFLA_PORT_REQUEST])
809 return -EOPNOTSUPP;
810
3f192795
RP		 811 memcpy(&prev_pp, pp, sizeof(*enic->pp));
812 memset(pp, 0, sizeof(*enic->pp));
b3abfbd2 813
3f192795
RP		 814 pp->set |= ENIC_SET_REQUEST;
815 pp->request = nla_get_u8(port[IFLA_PORT_REQUEST]);
08f382eb
SF		 816
817 if (port[IFLA_PORT_PROFILE]) {
3f192795
RP		 818 pp->set |= ENIC_SET_NAME;
819 memcpy(pp->name, nla_data(port[IFLA_PORT_PROFILE]),
08f382eb
SF		 820 PORT_PROFILE_MAX);
821 }
822
823 if (port[IFLA_PORT_INSTANCE_UUID]) {
3f192795
RP		 824 pp->set |= ENIC_SET_INSTANCE;
825 memcpy(pp->instance_uuid,
08f382eb
SF		 826 nla_data(port[IFLA_PORT_INSTANCE_UUID]), PORT_UUID_MAX);
827 }
828
829 if (port[IFLA_PORT_HOST_UUID]) {
3f192795
RP		 830 pp->set |= ENIC_SET_HOST;
831 memcpy(pp->host_uuid,
08f382eb
SF		 832 nla_data(port[IFLA_PORT_HOST_UUID]), PORT_UUID_MAX);
833 }
f8bd9091 834
b4765833
RP		 835 if (vf == PORT_SELF_VF) {
836 /* Special case handling: mac came from IFLA_VF_MAC */
837 if (!is_zero_ether_addr(prev_pp.vf_mac))
838 memcpy(pp->mac_addr, prev_pp.vf_mac, ETH_ALEN);
418c437d 839
b4765833
RP		 840 if (is_zero_ether_addr(netdev->dev_addr))
841 eth_hw_addr_random(netdev);
842 } else {
843 /* SR-IOV VF: get mac from adapter */
844 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
845 vnic_dev_get_mac_addr, pp->mac_addr);
846 if (err) {
847 netdev_err(netdev, "Error getting mac for vf %d\n", vf);
848 memcpy(pp, &prev_pp, sizeof(*pp));
849 return enic_dev_status_to_errno(err);
850 }
851 }
f8bd9091 852
3f192795 853 err = enic_process_set_pp_request(enic, vf, &prev_pp, &restore_pp);
b3abfbd2
RP		 854 if (err) {
855 if (restore_pp) {
856 /* Things are still the way they were: Implicit
857 * DISASSOCIATE failed
858 */
3f192795 859 memcpy(pp, &prev_pp, sizeof(*pp));
b3abfbd2 860 } else {
3f192795
RP		 861 memset(pp, 0, sizeof(*pp));
862 if (vf == PORT_SELF_VF)
863 memset(netdev->dev_addr, 0, ETH_ALEN);
b3abfbd2
RP		 864 }
865 } else {
866 /* Set flag to indicate that the port assoc/disassoc
867 * request has been sent out to fw
868 */
3f192795 869 pp->set |= ENIC_PORT_REQUEST_APPLIED;
b3abfbd2
RP		 870
871 /* If DISASSOCIATE, clean up all assigned/saved macaddresses */
3f192795
RP		 872 if (pp->request == PORT_REQUEST_DISASSOCIATE) {
873 memset(pp->mac_addr, 0, ETH_ALEN);
874 if (vf == PORT_SELF_VF)
875 memset(netdev->dev_addr, 0, ETH_ALEN);
b3abfbd2
RP		 876 }
877 }
29639059 878
b4765833
RP		 879 if (vf == PORT_SELF_VF)
880 memset(pp->vf_mac, 0, ETH_ALEN);
29639059 881
29639059 882 return err;
f8bd9091
SF		 883}
884
885static int enic_get_vf_port(struct net_device *netdev, int vf,
886 struct sk_buff *skb)
887{
888 struct enic *enic = netdev_priv(netdev);
f8bd9091 889 u16 response = PORT_PROFILE_RESPONSE_SUCCESS;
3f192795 890 struct enic_port_profile *pp;
b3abfbd2 891 int err;
f8bd9091 892
3f192795
RP		 893 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
894 if (err)
895 return err;
896
897 if (!(pp->set & ENIC_PORT_REQUEST_APPLIED))
08f382eb 898 return -ENODATA;
f8bd9091 899
3f192795 900 err = enic_process_get_pp_request(enic, vf, pp->request, &response);
f8bd9091 901 if (err)
b3abfbd2 902 return err;
f8bd9091 903
1a106de6
DM		 904 if (nla_put_u16(skb, IFLA_PORT_REQUEST, pp->request) ||
905 nla_put_u16(skb, IFLA_PORT_RESPONSE, response) ||
906 ((pp->set & ENIC_SET_NAME) &&
907 nla_put(skb, IFLA_PORT_PROFILE, PORT_PROFILE_MAX, pp->name)) ||
908 ((pp->set & ENIC_SET_INSTANCE) &&
909 nla_put(skb, IFLA_PORT_INSTANCE_UUID, PORT_UUID_MAX,
910 pp->instance_uuid)) ||
911 ((pp->set & ENIC_SET_HOST) &&
912 nla_put(skb, IFLA_PORT_HOST_UUID, PORT_UUID_MAX, pp->host_uuid)))
913 goto nla_put_failure;
f8bd9091
SF		 914 return 0;
915
916nla_put_failure:
917 return -EMSGSIZE;
918}
919
01f2e4ea
SF		 920static void enic_free_rq_buf(struct vnic_rq *rq, struct vnic_rq_buf *buf)
921{
922 struct enic *enic = vnic_dev_priv(rq->vdev);
923
924 if (!buf->os_buf)
925 return;
926
927 pci_unmap_single(enic->pdev, buf->dma_addr,
928 buf->len, PCI_DMA_FROMDEVICE);
929 dev_kfree_skb_any(buf->os_buf);
a03bb56e 930 buf->os_buf = NULL;
01f2e4ea
SF		 931}
932
01f2e4ea
SF		 933static int enic_rq_alloc_buf(struct vnic_rq *rq)
934{
935 struct enic *enic = vnic_dev_priv(rq->vdev);
d19e22dc 936 struct net_device *netdev = enic->netdev;
01f2e4ea 937 struct sk_buff *skb;
1825aca6 938 unsigned int len = netdev->mtu + VLAN_ETH_HLEN;
01f2e4ea
SF		 939 unsigned int os_buf_index = 0;
940 dma_addr_t dma_addr;
a03bb56e
GV		 941 struct vnic_rq_buf *buf = rq->to_use;
942
943 if (buf->os_buf) {
f6b7734b
GV		 944 enic_queue_rq_desc(rq, buf->os_buf, os_buf_index, buf->dma_addr,
945 buf->len);
01f2e4ea 946
a03bb56e
GV		 947 return 0;
948 }
89d71a66 949 skb = netdev_alloc_skb_ip_align(netdev, len);
01f2e4ea
SF		 950 if (!skb)
951 return -ENOMEM;
952
953 dma_addr = pci_map_single(enic->pdev, skb->data,
954 len, PCI_DMA_FROMDEVICE);
955
956 enic_queue_rq_desc(rq, skb, os_buf_index,
957 dma_addr, len);
958
959 return 0;
960}
961
7c2ce6e6
SS		 962static void enic_intr_update_pkt_size(struct vnic_rx_bytes_counter *pkt_size,
963 u32 pkt_len)
964{
965 if (ENIC_LARGE_PKT_THRESHOLD <= pkt_len)
966 pkt_size->large_pkt_bytes_cnt += pkt_len;
967 else
968 pkt_size->small_pkt_bytes_cnt += pkt_len;
969}
970
a03bb56e
GV		 971static bool enic_rxcopybreak(struct net_device *netdev, struct sk_buff **skb,
972 struct vnic_rq_buf *buf, u16 len)
973{
974 struct enic *enic = netdev_priv(netdev);
975 struct sk_buff *new_skb;
976
977 if (len > enic->rx_copybreak)
978 return false;
979 new_skb = netdev_alloc_skb_ip_align(netdev, len);
980 if (!new_skb)
981 return false;
982 pci_dma_sync_single_for_cpu(enic->pdev, buf->dma_addr, len,
983 DMA_FROM_DEVICE);
984 memcpy(new_skb->data, (*skb)->data, len);
985 *skb = new_skb;
986
987 return true;
988}
989
01f2e4ea
SF		 990static void enic_rq_indicate_buf(struct vnic_rq *rq,
991 struct cq_desc *cq_desc, struct vnic_rq_buf *buf,
992 int skipped, void *opaque)
993{
994 struct enic *enic = vnic_dev_priv(rq->vdev);
86ca9db7 995 struct net_device *netdev = enic->netdev;
01f2e4ea 996 struct sk_buff *skb;
7c2ce6e6 997 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
01f2e4ea
SF		 998
999 u8 type, color, eop, sop, ingress_port, vlan_stripped;
1000 u8 fcoe, fcoe_sof, fcoe_fc_crc_ok, fcoe_enc_error, fcoe_eof;
1001 u8 tcp_udp_csum_ok, udp, tcp, ipv4_csum_ok;
1002 u8 ipv6, ipv4, ipv4_fragment, fcs_ok, rss_type, csum_not_calc;
1003 u8 packet_error;
f8cac14a 1004 u16 q_number, completed_index, bytes_written, vlan_tci, checksum;
01f2e4ea
SF		 1005 u32 rss_hash;
1006
1007 if (skipped)
1008 return;
1009
1010 skb = buf->os_buf;
01f2e4ea
SF		 1011
1012 cq_enet_rq_desc_dec((struct cq_enet_rq_desc *)cq_desc,
1013 &type, &color, &q_number, &completed_index,
1014 &ingress_port, &fcoe, &eop, &sop, &rss_type,
1015 &csum_not_calc, &rss_hash, &bytes_written,
f8cac14a 1016 &packet_error, &vlan_stripped, &vlan_tci, &checksum,
01f2e4ea
SF		 1017 &fcoe_sof, &fcoe_fc_crc_ok, &fcoe_enc_error,
1018 &fcoe_eof, &tcp_udp_csum_ok, &udp, &tcp,
1019 &ipv4_csum_ok, &ipv6, &ipv4, &ipv4_fragment,
1020 &fcs_ok);
1021
1022 if (packet_error) {
1023
350991e1
SF		 1024 if (!fcs_ok) {
1025 if (bytes_written > 0)
1026 enic->rq_bad_fcs++;
1027 else if (bytes_written == 0)
1028 enic->rq_truncated_pkts++;
1029 }
01f2e4ea 1030
44aa91ab
GV		 1031 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1032 PCI_DMA_FROMDEVICE);
01f2e4ea 1033 dev_kfree_skb_any(skb);
44aa91ab 1034 buf->os_buf = NULL;
01f2e4ea
SF		 1035
1036 return;
1037 }
1038
1039 if (eop && bytes_written > 0) {
1040
1041 /* Good receive
1042 */
1043
a03bb56e
GV		 1044 if (!enic_rxcopybreak(netdev, &skb, buf, bytes_written)) {
1045 buf->os_buf = NULL;
1046 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1047 PCI_DMA_FROMDEVICE);
1048 }
1049 prefetch(skb->data - NET_IP_ALIGN);
1050
01f2e4ea 1051 skb_put(skb, bytes_written);
86ca9db7 1052 skb->protocol = eth_type_trans(skb, netdev);
bf751ba8 1053 skb_record_rx_queue(skb, q_number);
1054 if (netdev->features & NETIF_F_RXHASH) {
3739acdd
TH		 1055 skb_set_hash(skb, rss_hash,
1056 (rss_type &
1057 (NIC_CFG_RSS_HASH_TYPE_TCP_IPV6_EX |
1058 NIC_CFG_RSS_HASH_TYPE_TCP_IPV6 |
1059 NIC_CFG_RSS_HASH_TYPE_TCP_IPV4)) ?
1060 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
bf751ba8 1061 }
01f2e4ea 1062
17e96834
GV		 1063 /* Hardware does not provide whole packet checksum. It only
1064 * provides pseudo checksum. Since hw validates the packet
1065 * checksum but not provide us the checksum value. use
1066 * CHECSUM_UNNECESSARY.
1067 */
1068 if ((netdev->features & NETIF_F_RXCSUM) && tcp_udp_csum_ok &&
1069 ipv4_csum_ok)
1070 skb->ip_summed = CHECKSUM_UNNECESSARY;
01f2e4ea 1071
6ede746b 1072 if (vlan_stripped)
86a9bad3 1073 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci);
01f2e4ea 1074
14747cd9
GV		 1075 skb_mark_napi_id(skb, &enic->napi[rq->index]);
1076 if (enic_poll_busy_polling(rq) ||
1077 !(netdev->features & NETIF_F_GRO))
6ede746b 1078 netif_receive_skb(skb);
14747cd9
GV		 1079 else
1080 napi_gro_receive(&enic->napi[q_number], skb);
7c2ce6e6
SS		 1081 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1082 enic_intr_update_pkt_size(&cq->pkt_size_counter,
1083 bytes_written);
01f2e4ea
SF		 1084 } else {
1085
1086 /* Buffer overflow
1087 */
1088
44aa91ab
GV		 1089 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1090 PCI_DMA_FROMDEVICE);
01f2e4ea 1091 dev_kfree_skb_any(skb);
44aa91ab 1092 buf->os_buf = NULL;
01f2e4ea
SF		 1093 }
1094}
1095
1096static int enic_rq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
1097 u8 type, u16 q_number, u16 completed_index, void *opaque)
1098{
1099 struct enic *enic = vnic_dev_priv(vdev);
1100
1101 vnic_rq_service(&enic->rq[q_number], cq_desc,
1102 completed_index, VNIC_RQ_RETURN_DESC,
1103 enic_rq_indicate_buf, opaque);
1104
1105 return 0;
1106}
1107
01f2e4ea
SF		 1108static int enic_poll(struct napi_struct *napi, int budget)
1109{
717258ba
VK		 1110 struct net_device *netdev = napi->dev;
1111 struct enic *enic = netdev_priv(netdev);
1112 unsigned int cq_rq = enic_cq_rq(enic, 0);
1113 unsigned int cq_wq = enic_cq_wq(enic, 0);
1114 unsigned int intr = enic_legacy_io_intr();
01f2e4ea
SF		 1115 unsigned int rq_work_to_do = budget;
1116 unsigned int wq_work_to_do = -1; /* no limit */
4c502549 1117 unsigned int work_done, rq_work_done = 0, wq_work_done;
2d6ddced 1118 int err;
01f2e4ea 1119
14747cd9
GV		 1120 wq_work_done = vnic_cq_service(&enic->cq[cq_wq], wq_work_to_do,
1121 enic_wq_service, NULL);
1122
1123 if (!enic_poll_lock_napi(&enic->rq[cq_rq])) {
1124 if (wq_work_done > 0)
1125 vnic_intr_return_credits(&enic->intr[intr],
1126 wq_work_done,
1127 0 /* dont unmask intr */,
1128 0 /* dont reset intr timer */);
1129 return rq_work_done;
1130 }
01f2e4ea 1131
4c502549
EB		 1132 if (budget > 0)
1133 rq_work_done = vnic_cq_service(&enic->cq[cq_rq],
1134 rq_work_to_do, enic_rq_service, NULL);
01f2e4ea 1135
01f2e4ea
SF		 1136 /* Accumulate intr event credits for this polling
1137 * cycle. An intr event is the completion of a
1138 * a WQ or RQ packet.
1139 */
1140
1141 work_done = rq_work_done + wq_work_done;
1142
1143 if (work_done > 0)
717258ba 1144 vnic_intr_return_credits(&enic->intr[intr],
01f2e4ea
SF		 1145 work_done,
1146 0 /* don't unmask intr */,
1147 0 /* don't reset intr timer */);
1148
0eb26022 1149 err = vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
01f2e4ea 1150
2d6ddced
SF		 1151 /* Buffer allocation failed. Stay in polling
1152 * mode so we can try to fill the ring again.
1153 */
01f2e4ea 1154
2d6ddced
SF		 1155 if (err)
1156 rq_work_done = rq_work_to_do;
01f2e4ea 1157
2d6ddced 1158 if (rq_work_done < rq_work_to_do) {
01f2e4ea 1159
2d6ddced 1160 /* Some work done, but not enough to stay in polling,
88132f55 1161 * exit polling
01f2e4ea
SF		 1162 */
1163
288379f0 1164 napi_complete(napi);
717258ba 1165 vnic_intr_unmask(&enic->intr[intr]);
01f2e4ea 1166 }
14747cd9 1167 enic_poll_unlock_napi(&enic->rq[cq_rq]);
01f2e4ea
SF		 1168
1169 return rq_work_done;
1170}
1171
7c2ce6e6
SS		 1172static void enic_set_int_moderation(struct enic *enic, struct vnic_rq *rq)
1173{
1174 unsigned int intr = enic_msix_rq_intr(enic, rq->index);
1175 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
1176 u32 timer = cq->tobe_rx_coal_timeval;
1177
1178 if (cq->tobe_rx_coal_timeval != cq->cur_rx_coal_timeval) {
1179 vnic_intr_coalescing_timer_set(&enic->intr[intr], timer);
1180 cq->cur_rx_coal_timeval = cq->tobe_rx_coal_timeval;
1181 }
1182}
1183
1184static void enic_calc_int_moderation(struct enic *enic, struct vnic_rq *rq)
1185{
1186 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
1187 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
1188 struct vnic_rx_bytes_counter *pkt_size_counter = &cq->pkt_size_counter;
1189 int index;
1190 u32 timer;
1191 u32 range_start;
1192 u32 traffic;
1193 u64 delta;
1194 ktime_t now = ktime_get();
1195
1196 delta = ktime_us_delta(now, cq->prev_ts);
1197 if (delta < ENIC_AIC_TS_BREAK)
1198 return;
1199 cq->prev_ts = now;
1200
1201 traffic = pkt_size_counter->large_pkt_bytes_cnt +
1202 pkt_size_counter->small_pkt_bytes_cnt;
1203 /* The table takes Mbps
1204 * traffic *= 8 => bits
1205 * traffic *= (10^6 / delta) => bps
1206 * traffic /= 10^6 => Mbps
1207 *
1208 * Combining, traffic *= (8 / delta)
1209 */
1210
1211 traffic <<= 3;
958c492c 1212 traffic = delta > UINT_MAX ? 0 : traffic / (u32)delta;
7c2ce6e6
SS		 1213
1214 for (index = 0; index < ENIC_MAX_COALESCE_TIMERS; index++)
1215 if (traffic < mod_table[index].rx_rate)
1216 break;
1217 range_start = (pkt_size_counter->small_pkt_bytes_cnt >
1218 pkt_size_counter->large_pkt_bytes_cnt << 1) ?
1219 rx_coal->small_pkt_range_start :
1220 rx_coal->large_pkt_range_start;
1221 timer = range_start + ((rx_coal->range_end - range_start) *
1222 mod_table[index].range_percent / 100);
1223 /* Damping */
1224 cq->tobe_rx_coal_timeval = (timer + cq->tobe_rx_coal_timeval) >> 1;
1225
1226 pkt_size_counter->large_pkt_bytes_cnt = 0;
1227 pkt_size_counter->small_pkt_bytes_cnt = 0;
1228}
1229
b6e97c13
GV		 1230#ifdef CONFIG_RFS_ACCEL
1231static void enic_free_rx_cpu_rmap(struct enic *enic)
1232{
1233 free_irq_cpu_rmap(enic->netdev->rx_cpu_rmap);
1234 enic->netdev->rx_cpu_rmap = NULL;
1235}
1236
1237static void enic_set_rx_cpu_rmap(struct enic *enic)
1238{
1239 int i, res;
1240
1241 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) {
1242 enic->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(enic->rq_count);
1243 if (unlikely(!enic->netdev->rx_cpu_rmap))
1244 return;
1245 for (i = 0; i < enic->rq_count; i++) {
1246 res = irq_cpu_rmap_add(enic->netdev->rx_cpu_rmap,
1247 enic->msix_entry[i].vector);
1248 if (unlikely(res)) {
1249 enic_free_rx_cpu_rmap(enic);
1250 return;
1251 }
1252 }
1253 }
1254}
1255
1256#else
1257
1258static void enic_free_rx_cpu_rmap(struct enic *enic)
1259{
1260}
1261
1262static void enic_set_rx_cpu_rmap(struct enic *enic)
1263{
1264}
1265
1266#endif /* CONFIG_RFS_ACCEL */
1267
14747cd9
GV		 1268#ifdef CONFIG_NET_RX_BUSY_POLL
1269int enic_busy_poll(struct napi_struct *napi)
1270{
1271 struct net_device *netdev = napi->dev;
1272 struct enic *enic = netdev_priv(netdev);
1273 unsigned int rq = (napi - &enic->napi[0]);
1274 unsigned int cq = enic_cq_rq(enic, rq);
1275 unsigned int intr = enic_msix_rq_intr(enic, rq);
1276 unsigned int work_to_do = -1; /* clean all pkts possible */
1277 unsigned int work_done;
1278
1279 if (!enic_poll_lock_poll(&enic->rq[rq]))
1280 return LL_FLUSH_BUSY;
1281 work_done = vnic_cq_service(&enic->cq[cq], work_to_do,
1282 enic_rq_service, NULL);
1283
1284 if (work_done > 0)
1285 vnic_intr_return_credits(&enic->intr[intr],
1286 work_done, 0, 0);
1287 vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf);
1288 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1289 enic_calc_int_moderation(enic, &enic->rq[rq]);
1290 enic_poll_unlock_poll(&enic->rq[rq]);
1291
1292 return work_done;
1293}
1294#endif /* CONFIG_NET_RX_BUSY_POLL */
1295
4cfe8785
GV		 1296static int enic_poll_msix_wq(struct napi_struct *napi, int budget)
1297{
1298 struct net_device *netdev = napi->dev;
1299 struct enic *enic = netdev_priv(netdev);
1300 unsigned int wq_index = (napi - &enic->napi[0]) - enic->rq_count;
1301 struct vnic_wq *wq = &enic->wq[wq_index];
1302 unsigned int cq;
1303 unsigned int intr;
1304 unsigned int wq_work_to_do = -1; /* clean all desc possible */
1305 unsigned int wq_work_done;
1306 unsigned int wq_irq;
1307
1308 wq_irq = wq->index;
1309 cq = enic_cq_wq(enic, wq_irq);
1310 intr = enic_msix_wq_intr(enic, wq_irq);
1311 wq_work_done = vnic_cq_service(&enic->cq[cq], wq_work_to_do,
1312 enic_wq_service, NULL);
1313
1314 vnic_intr_return_credits(&enic->intr[intr], wq_work_done,
1315 0 /* don't unmask intr */,
1316 1 /* reset intr timer */);
1317 if (!wq_work_done) {
1318 napi_complete(napi);
1319 vnic_intr_unmask(&enic->intr[intr]);
f41281d0 1320 return 0;
4cfe8785
GV		 1321 }
1322
f41281d0 1323 return budget;
4cfe8785
GV		 1324}
1325
1326static int enic_poll_msix_rq(struct napi_struct *napi, int budget)
01f2e4ea 1327{
717258ba
VK		 1328 struct net_device *netdev = napi->dev;
1329 struct enic *enic = netdev_priv(netdev);
1330 unsigned int rq = (napi - &enic->napi[0]);
1331 unsigned int cq = enic_cq_rq(enic, rq);
1332 unsigned int intr = enic_msix_rq_intr(enic, rq);
01f2e4ea 1333 unsigned int work_to_do = budget;
4c502549 1334 unsigned int work_done = 0;
2d6ddced 1335 int err;
01f2e4ea 1336
14747cd9
GV		 1337 if (!enic_poll_lock_napi(&enic->rq[rq]))
1338 return work_done;
01f2e4ea
SF		 1339 /* Service RQ
1340 */
1341
4c502549
EB		 1342 if (budget > 0)
1343 work_done = vnic_cq_service(&enic->cq[cq],
1344 work_to_do, enic_rq_service, NULL);
01f2e4ea 1345
2d6ddced
SF		 1346 /* Return intr event credits for this polling
1347 * cycle. An intr event is the completion of a
1348 * RQ packet.
1349 */
01f2e4ea 1350
2d6ddced 1351 if (work_done > 0)
717258ba 1352 vnic_intr_return_credits(&enic->intr[intr],
01f2e4ea
SF		 1353 work_done,
1354 0 /* don't unmask intr */,
1355 0 /* don't reset intr timer */);
01f2e4ea 1356
0eb26022 1357 err = vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf);
2d6ddced
SF		 1358
1359 /* Buffer allocation failed. Stay in polling mode
1360 * so we can try to fill the ring again.
1361 */
1362
1363 if (err)
1364 work_done = work_to_do;
7c2ce6e6
SS		 1365 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1366 /* Call the function which refreshes
1367 * the intr coalescing timer value based on
1368 * the traffic. This is supported only in
1369 * the case of MSI-x mode
1370 */
1371 enic_calc_int_moderation(enic, &enic->rq[rq]);
2d6ddced
SF		 1372
1373 if (work_done < work_to_do) {
1374
1375 /* Some work done, but not enough to stay in polling,
88132f55 1376 * exit polling
01f2e4ea
SF		 1377 */
1378
288379f0 1379 napi_complete(napi);
7c2ce6e6
SS		 1380 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1381 enic_set_int_moderation(enic, &enic->rq[rq]);
717258ba 1382 vnic_intr_unmask(&enic->intr[intr]);
01f2e4ea 1383 }
14747cd9 1384 enic_poll_unlock_napi(&enic->rq[rq]);
01f2e4ea
SF		 1385
1386 return work_done;
1387}
1388
1389static void enic_notify_timer(unsigned long data)
1390{
1391 struct enic *enic = (struct enic *)data;
1392
1393 enic_notify_check(enic);
1394
25f0a061
SF		 1395 mod_timer(&enic->notify_timer,
1396 round_jiffies(jiffies + ENIC_NOTIFY_TIMER_PERIOD));
01f2e4ea
SF		 1397}
1398
1399static void enic_free_intr(struct enic *enic)
1400{
1401 struct net_device *netdev = enic->netdev;
1402 unsigned int i;
1403
b6e97c13 1404 enic_free_rx_cpu_rmap(enic);
01f2e4ea
SF		 1405 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1406 case VNIC_DEV_INTR_MODE_INTX:
01f2e4ea
SF		 1407 free_irq(enic->pdev->irq, netdev);
1408 break;
8f4d248c
SF		 1409 case VNIC_DEV_INTR_MODE_MSI:
1410 free_irq(enic->pdev->irq, enic);
1411 break;
01f2e4ea
SF		 1412 case VNIC_DEV_INTR_MODE_MSIX:
1413 for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
1414 if (enic->msix[i].requested)
1415 free_irq(enic->msix_entry[i].vector,
1416 enic->msix[i].devid);
1417 break;
1418 default:
1419 break;
1420 }
1421}
1422
1423static int enic_request_intr(struct enic *enic)
1424{
1425 struct net_device *netdev = enic->netdev;
717258ba 1426 unsigned int i, intr;
01f2e4ea
SF		 1427 int err = 0;
1428
b6e97c13 1429 enic_set_rx_cpu_rmap(enic);
01f2e4ea
SF		 1430 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1431
1432 case VNIC_DEV_INTR_MODE_INTX:
1433
1434 err = request_irq(enic->pdev->irq, enic_isr_legacy,
1435 IRQF_SHARED, netdev->name, netdev);
1436 break;
1437
1438 case VNIC_DEV_INTR_MODE_MSI:
1439
1440 err = request_irq(enic->pdev->irq, enic_isr_msi,
1441 0, netdev->name, enic);
1442 break;
1443
1444 case VNIC_DEV_INTR_MODE_MSIX:
1445
717258ba
VK		 1446 for (i = 0; i < enic->rq_count; i++) {
1447 intr = enic_msix_rq_intr(enic, i);
4505f40a
DC		 1448 snprintf(enic->msix[intr].devname,
1449 sizeof(enic->msix[intr].devname),
717258ba 1450 "%.11s-rx-%d", netdev->name, i);
4cfe8785 1451 enic->msix[intr].isr = enic_isr_msix;
717258ba
VK		 1452 enic->msix[intr].devid = &enic->napi[i];
1453 }
01f2e4ea 1454
717258ba 1455 for (i = 0; i < enic->wq_count; i++) {
4cfe8785
GV		 1456 int wq = enic_cq_wq(enic, i);
1457
717258ba 1458 intr = enic_msix_wq_intr(enic, i);
4505f40a
DC		 1459 snprintf(enic->msix[intr].devname,
1460 sizeof(enic->msix[intr].devname),
717258ba 1461 "%.11s-tx-%d", netdev->name, i);
4cfe8785
GV		 1462 enic->msix[intr].isr = enic_isr_msix;
1463 enic->msix[intr].devid = &enic->napi[wq];
717258ba 1464 }
01f2e4ea 1465
717258ba 1466 intr = enic_msix_err_intr(enic);
4505f40a
DC		 1467 snprintf(enic->msix[intr].devname,
1468 sizeof(enic->msix[intr].devname),
01f2e4ea 1469 "%.11s-err", netdev->name);
717258ba
VK		 1470 enic->msix[intr].isr = enic_isr_msix_err;
1471 enic->msix[intr].devid = enic;
01f2e4ea 1472
717258ba 1473 intr = enic_msix_notify_intr(enic);
4505f40a
DC		 1474 snprintf(enic->msix[intr].devname,
1475 sizeof(enic->msix[intr].devname),
01f2e4ea 1476 "%.11s-notify", netdev->name);
717258ba
VK		 1477 enic->msix[intr].isr = enic_isr_msix_notify;
1478 enic->msix[intr].devid = enic;
1479
1480 for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
1481 enic->msix[i].requested = 0;
01f2e4ea 1482
717258ba 1483 for (i = 0; i < enic->intr_count; i++) {
01f2e4ea
SF		 1484 err = request_irq(enic->msix_entry[i].vector,
1485 enic->msix[i].isr, 0,
1486 enic->msix[i].devname,
1487 enic->msix[i].devid);
1488 if (err) {
1489 enic_free_intr(enic);
1490 break;
1491 }
1492 enic->msix[i].requested = 1;
1493 }
1494
1495 break;
1496
1497 default:
1498 break;
1499 }
1500
1501 return err;
1502}
1503
b3d18d19
SF		 1504static void enic_synchronize_irqs(struct enic *enic)
1505{
1506 unsigned int i;
1507
1508 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1509 case VNIC_DEV_INTR_MODE_INTX:
1510 case VNIC_DEV_INTR_MODE_MSI:
1511 synchronize_irq(enic->pdev->irq);
1512 break;
1513 case VNIC_DEV_INTR_MODE_MSIX:
1514 for (i = 0; i < enic->intr_count; i++)
1515 synchronize_irq(enic->msix_entry[i].vector);
1516 break;
1517 default:
1518 break;
1519 }
1520}
1521
7c2ce6e6
SS		 1522static void enic_set_rx_coal_setting(struct enic *enic)
1523{
1524 unsigned int speed;
1525 int index = -1;
1526 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
1527
1528 /* If intr mode is not MSIX, do not do adaptive coalescing */
1529 if (VNIC_DEV_INTR_MODE_MSIX != vnic_dev_get_intr_mode(enic->vdev)) {
1530 netdev_info(enic->netdev, "INTR mode is not MSIX, Not initializing adaptive coalescing");
1531 return;
1532 }
1533
1534 /* 1. Read the link speed from fw
1535 * 2. Pick the default range for the speed
1536 * 3. Update it in enic->rx_coalesce_setting
1537 */
1538 speed = vnic_dev_port_speed(enic->vdev);
1539 if (ENIC_LINK_SPEED_10G < speed)
1540 index = ENIC_LINK_40G_INDEX;
1541 else if (ENIC_LINK_SPEED_4G < speed)
1542 index = ENIC_LINK_10G_INDEX;
1543 else
1544 index = ENIC_LINK_4G_INDEX;
1545
1546 rx_coal->small_pkt_range_start = mod_range[index].small_pkt_range_start;
1547 rx_coal->large_pkt_range_start = mod_range[index].large_pkt_range_start;
1548 rx_coal->range_end = ENIC_RX_COALESCE_RANGE_END;
1549
1550 /* Start with the value provided by UCSM */
1551 for (index = 0; index < enic->rq_count; index++)
1552 enic->cq[index].cur_rx_coal_timeval =
1553 enic->config.intr_timer_usec;
1554
1555 rx_coal->use_adaptive_rx_coalesce = 1;
1556}
1557
383ab92f 1558static int enic_dev_notify_set(struct enic *enic)
01f2e4ea
SF		 1559{
1560 int err;
1561
8e091340 1562 spin_lock_bh(&enic->devcmd_lock);
01f2e4ea
SF		 1563 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1564 case VNIC_DEV_INTR_MODE_INTX:
717258ba
VK		 1565 err = vnic_dev_notify_set(enic->vdev,
1566 enic_legacy_notify_intr());
01f2e4ea
SF		 1567 break;
1568 case VNIC_DEV_INTR_MODE_MSIX:
717258ba
VK		 1569 err = vnic_dev_notify_set(enic->vdev,
1570 enic_msix_notify_intr(enic));
01f2e4ea
SF		 1571 break;
1572 default:
1573 err = vnic_dev_notify_set(enic->vdev, -1 /* no intr */);
1574 break;
1575 }
8e091340 1576 spin_unlock_bh(&enic->devcmd_lock);
01f2e4ea
SF		 1577
1578 return err;
1579}
1580
1581static void enic_notify_timer_start(struct enic *enic)
1582{
1583 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1584 case VNIC_DEV_INTR_MODE_MSI:
1585 mod_timer(&enic->notify_timer, jiffies);
1586 break;
1587 default:
1588 /* Using intr for notification for INTx/MSI-X */
1589 break;
6403eab1 1590 }
01f2e4ea
SF		 1591}
1592
1593/* rtnl lock is held, process context */
1594static int enic_open(struct net_device *netdev)
1595{
1596 struct enic *enic = netdev_priv(netdev);
1597 unsigned int i;
1598 int err;
1599
4b75a442
SF		 1600 err = enic_request_intr(enic);
1601 if (err) {
a7a79deb 1602 netdev_err(netdev, "Unable to request irq.\n");
4b75a442
SF		 1603 return err;
1604 }
1605
383ab92f 1606 err = enic_dev_notify_set(enic);
4b75a442 1607 if (err) {
a7a79deb
VK		 1608 netdev_err(netdev,
1609 "Failed to alloc notify buffer, aborting.\n");
4b75a442
SF		 1610 goto err_out_free_intr;
1611 }
1612
01f2e4ea 1613 for (i = 0; i < enic->rq_count; i++) {
0eb26022 1614 vnic_rq_fill(&enic->rq[i], enic_rq_alloc_buf);
2d6ddced
SF		 1615 /* Need at least one buffer on ring to get going */
1616 if (vnic_rq_desc_used(&enic->rq[i]) == 0) {
a7a79deb 1617 netdev_err(netdev, "Unable to alloc receive buffers\n");
2d6ddced 1618 err = -ENOMEM;
4b75a442 1619 goto err_out_notify_unset;
01f2e4ea
SF		 1620 }
1621 }
1622
1623 for (i = 0; i < enic->wq_count; i++)
1624 vnic_wq_enable(&enic->wq[i]);
1625 for (i = 0; i < enic->rq_count; i++)
1626 vnic_rq_enable(&enic->rq[i]);
1627
7335903c 1628 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
29639059 1629 enic_dev_add_station_addr(enic);
3f192795 1630
319d7e84 1631 enic_set_rx_mode(netdev);
01f2e4ea 1632
822473b6 1633 netif_tx_wake_all_queues(netdev);
717258ba 1634
14747cd9
GV		 1635 for (i = 0; i < enic->rq_count; i++) {
1636 enic_busy_poll_init_lock(&enic->rq[i]);
717258ba 1637 napi_enable(&enic->napi[i]);
14747cd9 1638 }
4cfe8785
GV		 1639 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
1640 for (i = 0; i < enic->wq_count; i++)
1641 napi_enable(&enic->napi[enic_cq_wq(enic, i)]);
383ab92f 1642 enic_dev_enable(enic);
01f2e4ea
SF		 1643
1644 for (i = 0; i < enic->intr_count; i++)
1645 vnic_intr_unmask(&enic->intr[i]);
1646
1647 enic_notify_timer_start(enic);
a145df23 1648 enic_rfs_flw_tbl_init(enic);
01f2e4ea
SF		 1649
1650 return 0;
4b75a442
SF		 1651
1652err_out_notify_unset:
383ab92f 1653 enic_dev_notify_unset(enic);
4b75a442
SF		 1654err_out_free_intr:
1655 enic_free_intr(enic);
1656
1657 return err;
01f2e4ea
SF		 1658}
1659
1660/* rtnl lock is held, process context */
1661static int enic_stop(struct net_device *netdev)
1662{
1663 struct enic *enic = netdev_priv(netdev);
1664 unsigned int i;
1665 int err;
1666
29046f9b 1667 for (i = 0; i < enic->intr_count; i++) {
b3d18d19 1668 vnic_intr_mask(&enic->intr[i]);
29046f9b
VK		 1669 (void)vnic_intr_masked(&enic->intr[i]); /* flush write */
1670 }
b3d18d19
SF		 1671
1672 enic_synchronize_irqs(enic);
1673
01f2e4ea 1674 del_timer_sync(&enic->notify_timer);
a145df23 1675 enic_rfs_flw_tbl_free(enic);
01f2e4ea 1676
383ab92f 1677 enic_dev_disable(enic);
717258ba 1678
14747cd9 1679 for (i = 0; i < enic->rq_count; i++) {
717258ba 1680 napi_disable(&enic->napi[i]);
39dc90c1 1681 local_bh_disable();
14747cd9
GV		 1682 while (!enic_poll_lock_napi(&enic->rq[i]))
1683 mdelay(1);
39dc90c1 1684 local_bh_enable();
14747cd9 1685 }
717258ba 1686
b3d18d19
SF		 1687 netif_carrier_off(netdev);
1688 netif_tx_disable(netdev);
4cfe8785
GV		 1689 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
1690 for (i = 0; i < enic->wq_count; i++)
1691 napi_disable(&enic->napi[enic_cq_wq(enic, i)]);
3f192795 1692
7335903c 1693 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
29639059 1694 enic_dev_del_station_addr(enic);
f8bd9091 1695
01f2e4ea
SF		 1696 for (i = 0; i < enic->wq_count; i++) {
1697 err = vnic_wq_disable(&enic->wq[i]);
1698 if (err)
1699 return err;
1700 }
1701 for (i = 0; i < enic->rq_count; i++) {
1702 err = vnic_rq_disable(&enic->rq[i]);
1703 if (err)
1704 return err;
1705 }
1706
383ab92f 1707 enic_dev_notify_unset(enic);
4b75a442
SF		 1708 enic_free_intr(enic);
1709
01f2e4ea
SF		 1710 for (i = 0; i < enic->wq_count; i++)
1711 vnic_wq_clean(&enic->wq[i], enic_free_wq_buf);
1712 for (i = 0; i < enic->rq_count; i++)
1713 vnic_rq_clean(&enic->rq[i], enic_free_rq_buf);
1714 for (i = 0; i < enic->cq_count; i++)
1715 vnic_cq_clean(&enic->cq[i]);
1716 for (i = 0; i < enic->intr_count; i++)
1717 vnic_intr_clean(&enic->intr[i]);
1718
1719 return 0;
1720}
1721
1722static int enic_change_mtu(struct net_device *netdev, int new_mtu)
1723{
1724 struct enic *enic = netdev_priv(netdev);
1725 int running = netif_running(netdev);
1726
25f0a061
SF		 1727 if (new_mtu < ENIC_MIN_MTU || new_mtu > ENIC_MAX_MTU)
1728 return -EINVAL;
1729
7335903c 1730 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
c97c894d
RP		 1731 return -EOPNOTSUPP;
1732
01f2e4ea
SF		 1733 if (running)
1734 enic_stop(netdev);
1735
01f2e4ea
SF		 1736 netdev->mtu = new_mtu;
1737
1738 if (netdev->mtu > enic->port_mtu)
a7a79deb
VK		 1739 netdev_warn(netdev,
1740 "interface MTU (%d) set higher than port MTU (%d)\n",
1741 netdev->mtu, enic->port_mtu);
01f2e4ea
SF		 1742
1743 if (running)
1744 enic_open(netdev);
1745
1746 return 0;
1747}
1748
c97c894d
RP		 1749static void enic_change_mtu_work(struct work_struct *work)
1750{
1751 struct enic *enic = container_of(work, struct enic, change_mtu_work);
1752 struct net_device *netdev = enic->netdev;
1753 int new_mtu = vnic_dev_mtu(enic->vdev);
1754 int err;
1755 unsigned int i;
1756
1757 new_mtu = max_t(int, ENIC_MIN_MTU, min_t(int, ENIC_MAX_MTU, new_mtu));
1758
1759 rtnl_lock();
1760
1761 /* Stop RQ */
1762 del_timer_sync(&enic->notify_timer);
1763
1764 for (i = 0; i < enic->rq_count; i++)
1765 napi_disable(&enic->napi[i]);
1766
1767 vnic_intr_mask(&enic->intr[0]);
1768 enic_synchronize_irqs(enic);
1769 err = vnic_rq_disable(&enic->rq[0]);
1770 if (err) {
e057590b 1771 rtnl_unlock();
c97c894d
RP		 1772 netdev_err(netdev, "Unable to disable RQ.\n");
1773 return;
1774 }
1775 vnic_rq_clean(&enic->rq[0], enic_free_rq_buf);
1776 vnic_cq_clean(&enic->cq[0]);
1777 vnic_intr_clean(&enic->intr[0]);
1778
1779 /* Fill RQ with new_mtu-sized buffers */
1780 netdev->mtu = new_mtu;
1781 vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
1782 /* Need at least one buffer on ring to get going */
1783 if (vnic_rq_desc_used(&enic->rq[0]) == 0) {
e057590b 1784 rtnl_unlock();
c97c894d
RP		 1785 netdev_err(netdev, "Unable to alloc receive buffers.\n");
1786 return;
1787 }
1788
1789 /* Start RQ */
1790 vnic_rq_enable(&enic->rq[0]);
1791 napi_enable(&enic->napi[0]);
1792 vnic_intr_unmask(&enic->intr[0]);
1793 enic_notify_timer_start(enic);
1794
1795 rtnl_unlock();
1796
1797 netdev_info(netdev, "interface MTU set as %d\n", netdev->mtu);
1798}
1799
01f2e4ea
SF		 1800#ifdef CONFIG_NET_POLL_CONTROLLER
1801static void enic_poll_controller(struct net_device *netdev)
1802{
1803 struct enic *enic = netdev_priv(netdev);
1804 struct vnic_dev *vdev = enic->vdev;
717258ba 1805 unsigned int i, intr;
01f2e4ea
SF		 1806
1807 switch (vnic_dev_get_intr_mode(vdev)) {
1808 case VNIC_DEV_INTR_MODE_MSIX:
717258ba
VK		 1809 for (i = 0; i < enic->rq_count; i++) {
1810 intr = enic_msix_rq_intr(enic, i);
4cfe8785
GV		 1811 enic_isr_msix(enic->msix_entry[intr].vector,
1812 &enic->napi[i]);
717258ba 1813 }
b880a954
VK		 1814
1815 for (i = 0; i < enic->wq_count; i++) {
1816 intr = enic_msix_wq_intr(enic, i);
4cfe8785
GV		 1817 enic_isr_msix(enic->msix_entry[intr].vector,
1818 &enic->napi[enic_cq_wq(enic, i)]);
b880a954
VK		 1819 }
1820
01f2e4ea
SF		 1821 break;
1822 case VNIC_DEV_INTR_MODE_MSI:
1823 enic_isr_msi(enic->pdev->irq, enic);
1824 break;
1825 case VNIC_DEV_INTR_MODE_INTX:
1826 enic_isr_legacy(enic->pdev->irq, netdev);
1827 break;
1828 default:
1829 break;
1830 }
1831}
1832#endif
1833
1834static int enic_dev_wait(struct vnic_dev *vdev,
1835 int (*start)(struct vnic_dev *, int),
1836 int (*finished)(struct vnic_dev *, int *),
1837 int arg)
1838{
1839 unsigned long time;
1840 int done;
1841 int err;
1842
1843 BUG_ON(in_interrupt());
1844
1845 err = start(vdev, arg);
1846 if (err)
1847 return err;
1848
1849 /* Wait for func to complete...2 seconds max
1850 */
1851
1852 time = jiffies + (HZ * 2);
1853 do {
1854
1855 err = finished(vdev, &done);
1856 if (err)
1857 return err;
1858
1859 if (done)
1860 return 0;
1861
1862 schedule_timeout_uninterruptible(HZ / 10);
1863
1864 } while (time_after(time, jiffies));
1865
1866 return -ETIMEDOUT;
1867}
1868
1869static int enic_dev_open(struct enic *enic)
1870{
1871 int err;
1872
1873 err = enic_dev_wait(enic->vdev, vnic_dev_open,
1874 vnic_dev_open_done, 0);
1875 if (err)
a7a79deb
VK		 1876 dev_err(enic_get_dev(enic), "vNIC device open failed, err %d\n",
1877 err);
01f2e4ea
SF		 1878
1879 return err;
1880}
1881
99ef5639 1882static int enic_dev_hang_reset(struct enic *enic)
01f2e4ea
SF		 1883{
1884 int err;
1885
99ef5639
VK		 1886 err = enic_dev_wait(enic->vdev, vnic_dev_hang_reset,
1887 vnic_dev_hang_reset_done, 0);
01f2e4ea 1888 if (err)
a7a79deb
VK		 1889 netdev_err(enic->netdev, "vNIC hang reset failed, err %d\n",
1890 err);
01f2e4ea
SF		 1891
1892 return err;
1893}
1894
4f675eb2 1895int __enic_set_rsskey(struct enic *enic)
717258ba 1896{
c33d23c2 1897 union vnic_rss_key *rss_key_buf_va;
1f4f067f 1898 dma_addr_t rss_key_buf_pa;
c33d23c2 1899 int i, kidx, bidx, err;
717258ba 1900
c33d23c2
ED		 1901 rss_key_buf_va = pci_zalloc_consistent(enic->pdev,
1902 sizeof(union vnic_rss_key),
1903 &rss_key_buf_pa);
717258ba
VK		 1904 if (!rss_key_buf_va)
1905 return -ENOMEM;
1906
c33d23c2
ED		 1907 for (i = 0; i < ENIC_RSS_LEN; i++) {
1908 kidx = i / ENIC_RSS_BYTES_PER_KEY;
1909 bidx = i % ENIC_RSS_BYTES_PER_KEY;
4f675eb2 1910 rss_key_buf_va->key[kidx].b[bidx] = enic->rss_key[i];
c33d23c2 1911 }
8e091340 1912 spin_lock_bh(&enic->devcmd_lock);
717258ba
VK		 1913 err = enic_set_rss_key(enic,
1914 rss_key_buf_pa,
1915 sizeof(union vnic_rss_key));
8e091340 1916 spin_unlock_bh(&enic->devcmd_lock);
717258ba
VK		 1917
1918 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_key),
1919 rss_key_buf_va, rss_key_buf_pa);
1920
1921 return err;
1922}
1923
4f675eb2
GV		 1924static int enic_set_rsskey(struct enic *enic)
1925{
1926 netdev_rss_key_fill(enic->rss_key, ENIC_RSS_LEN);
1927
1928 return __enic_set_rsskey(enic);
1929}
1930
717258ba
VK		 1931static int enic_set_rsscpu(struct enic *enic, u8 rss_hash_bits)
1932{
1f4f067f 1933 dma_addr_t rss_cpu_buf_pa;
717258ba
VK		 1934 union vnic_rss_cpu *rss_cpu_buf_va = NULL;
1935 unsigned int i;
1936 int err;
1937
1938 rss_cpu_buf_va = pci_alloc_consistent(enic->pdev,
1939 sizeof(union vnic_rss_cpu), &rss_cpu_buf_pa);
1940 if (!rss_cpu_buf_va)
1941 return -ENOMEM;
1942
1943 for (i = 0; i < (1 << rss_hash_bits); i++)
1944 (*rss_cpu_buf_va).cpu[i/4].b[i%4] = i % enic->rq_count;
1945
8e091340 1946 spin_lock_bh(&enic->devcmd_lock);
717258ba
VK		 1947 err = enic_set_rss_cpu(enic,
1948 rss_cpu_buf_pa,
1949 sizeof(union vnic_rss_cpu));
8e091340 1950 spin_unlock_bh(&enic->devcmd_lock);
717258ba
VK		 1951
1952 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_cpu),
1953 rss_cpu_buf_va, rss_cpu_buf_pa);
1954
1955 return err;
1956}
1957
1958static int enic_set_niccfg(struct enic *enic, u8 rss_default_cpu,
1959 u8 rss_hash_type, u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable)
68f71708 1960{
68f71708
SF		 1961 const u8 tso_ipid_split_en = 0;
1962 const u8 ig_vlan_strip_en = 1;
383ab92f 1963 int err;
68f71708 1964
717258ba
VK		 1965 /* Enable VLAN tag stripping.
1966 */
68f71708 1967
8e091340 1968 spin_lock_bh(&enic->devcmd_lock);
383ab92f 1969 err = enic_set_nic_cfg(enic,
68f71708
SF		 1970 rss_default_cpu, rss_hash_type,
1971 rss_hash_bits, rss_base_cpu,
1972 rss_enable, tso_ipid_split_en,
1973 ig_vlan_strip_en);
8e091340 1974 spin_unlock_bh(&enic->devcmd_lock);
383ab92f
VK		 1975
1976 return err;
1977}
1978
717258ba
VK		 1979static int enic_set_rss_nic_cfg(struct enic *enic)
1980{
1981 struct device *dev = enic_get_dev(enic);
1982 const u8 rss_default_cpu = 0;
1983 const u8 rss_hash_type = NIC_CFG_RSS_HASH_TYPE_IPV4 |
1984 NIC_CFG_RSS_HASH_TYPE_TCP_IPV4 |
1985 NIC_CFG_RSS_HASH_TYPE_IPV6 |
1986 NIC_CFG_RSS_HASH_TYPE_TCP_IPV6;
1987 const u8 rss_hash_bits = 7;
1988 const u8 rss_base_cpu = 0;
1989 u8 rss_enable = ENIC_SETTING(enic, RSS) && (enic->rq_count > 1);
1990
1991 if (rss_enable) {
1992 if (!enic_set_rsskey(enic)) {
1993 if (enic_set_rsscpu(enic, rss_hash_bits)) {
1994 rss_enable = 0;
1995 dev_warn(dev, "RSS disabled, "
1996 "Failed to set RSS cpu indirection table.");
1997 }
1998 } else {
1999 rss_enable = 0;
2000 dev_warn(dev, "RSS disabled, Failed to set RSS key.\n");
2001 }
2002 }
2003
2004 return enic_set_niccfg(enic, rss_default_cpu, rss_hash_type,
2005 rss_hash_bits, rss_base_cpu, rss_enable);
f8cac14a
VK		 2006}
2007
01f2e4ea
SF		 2008static void enic_reset(struct work_struct *work)
2009{
2010 struct enic *enic = container_of(work, struct enic, reset);
2011
2012 if (!netif_running(enic->netdev))
2013 return;
2014
2015 rtnl_lock();
2016
0b038566 2017 spin_lock(&enic->enic_api_lock);
383ab92f 2018 enic_dev_hang_notify(enic);
01f2e4ea 2019 enic_stop(enic->netdev);
99ef5639 2020 enic_dev_hang_reset(enic);
e0afe53f 2021 enic_reset_addr_lists(enic);
01f2e4ea 2022 enic_init_vnic_resources(enic);
717258ba 2023 enic_set_rss_nic_cfg(enic);
f8cac14a 2024 enic_dev_set_ig_vlan_rewrite_mode(enic);
01f2e4ea 2025 enic_open(enic->netdev);
0b038566 2026 spin_unlock(&enic->enic_api_lock);
d765bb41 2027 call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev);
01f2e4ea
SF		 2028
2029 rtnl_unlock();
2030}
2031
2032static int enic_set_intr_mode(struct enic *enic)
2033{
717258ba 2034 unsigned int n = min_t(unsigned int, enic->rq_count, ENIC_RQ_MAX);
1cbb1a61 2035 unsigned int m = min_t(unsigned int, enic->wq_count, ENIC_WQ_MAX);
01f2e4ea
SF		 2036 unsigned int i;
2037
2038 /* Set interrupt mode (INTx, MSI, MSI-X) depending
717258ba 2039 * on system capabilities.
01f2e4ea
SF		 2040 *
2041 * Try MSI-X first
2042 *
2043 * We need n RQs, m WQs, n+m CQs, and n+m+2 INTRs
2044 * (the second to last INTR is used for WQ/RQ errors)
2045 * (the last INTR is used for notifications)
2046 */
2047
2048 BUG_ON(ARRAY_SIZE(enic->msix_entry) < n + m + 2);
2049 for (i = 0; i < n + m + 2; i++)
2050 enic->msix_entry[i].entry = i;
2051
717258ba
VK		 2052 /* Use multiple RQs if RSS is enabled
2053 */
2054
2055 if (ENIC_SETTING(enic, RSS) &&
2056 enic->config.intr_mode < 1 &&
01f2e4ea
SF		 2057 enic->rq_count >= n &&
2058 enic->wq_count >= m &&
2059 enic->cq_count >= n + m &&
717258ba 2060 enic->intr_count >= n + m + 2) {
01f2e4ea 2061
abbb6a37
AG		 2062 if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
2063 n + m + 2, n + m + 2) > 0) {
01f2e4ea 2064
717258ba
VK		 2065 enic->rq_count = n;
2066 enic->wq_count = m;
2067 enic->cq_count = n + m;
2068 enic->intr_count = n + m + 2;
01f2e4ea 2069
717258ba
VK		 2070 vnic_dev_set_intr_mode(enic->vdev,
2071 VNIC_DEV_INTR_MODE_MSIX);
2072
2073 return 0;
2074 }
2075 }
2076
2077 if (enic->config.intr_mode < 1 &&
2078 enic->rq_count >= 1 &&
2079 enic->wq_count >= m &&
2080 enic->cq_count >= 1 + m &&
2081 enic->intr_count >= 1 + m + 2) {
abbb6a37
AG		 2082 if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
2083 1 + m + 2, 1 + m + 2) > 0) {
717258ba
VK		 2084
2085 enic->rq_count = 1;
2086 enic->wq_count = m;
2087 enic->cq_count = 1 + m;
2088 enic->intr_count = 1 + m + 2;
2089
2090 vnic_dev_set_intr_mode(enic->vdev,
2091 VNIC_DEV_INTR_MODE_MSIX);
2092
2093 return 0;
2094 }
01f2e4ea
SF		 2095 }
2096
2097 /* Next try MSI
2098 *
2099 * We need 1 RQ, 1 WQ, 2 CQs, and 1 INTR
2100 */
2101
2102 if (enic->config.intr_mode < 2 &&
2103 enic->rq_count >= 1 &&
2104 enic->wq_count >= 1 &&
2105 enic->cq_count >= 2 &&
2106 enic->intr_count >= 1 &&
2107 !pci_enable_msi(enic->pdev)) {
2108
2109 enic->rq_count = 1;
2110 enic->wq_count = 1;
2111 enic->cq_count = 2;
2112 enic->intr_count = 1;
2113
2114 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_MSI);
2115
2116 return 0;
2117 }
2118
2119 /* Next try INTx
2120 *
2121 * We need 1 RQ, 1 WQ, 2 CQs, and 3 INTRs
2122 * (the first INTR is used for WQ/RQ)
2123 * (the second INTR is used for WQ/RQ errors)
2124 * (the last INTR is used for notifications)
2125 */
2126
2127 if (enic->config.intr_mode < 3 &&
2128 enic->rq_count >= 1 &&
2129 enic->wq_count >= 1 &&
2130 enic->cq_count >= 2 &&
2131 enic->intr_count >= 3) {
2132
2133 enic->rq_count = 1;
2134 enic->wq_count = 1;
2135 enic->cq_count = 2;
2136 enic->intr_count = 3;
2137
2138 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_INTX);
2139
2140 return 0;
2141 }
2142
2143 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
2144
2145 return -EINVAL;
2146}
2147
2148static void enic_clear_intr_mode(struct enic *enic)
2149{
2150 switch (vnic_dev_get_intr_mode(enic->vdev)) {
2151 case VNIC_DEV_INTR_MODE_MSIX:
2152 pci_disable_msix(enic->pdev);
2153 break;
2154 case VNIC_DEV_INTR_MODE_MSI:
2155 pci_disable_msi(enic->pdev);
2156 break;
2157 default:
2158 break;
2159 }
2160
2161 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
2162}
2163
f8bd9091
SF		 2164static const struct net_device_ops enic_netdev_dynamic_ops = {
2165 .ndo_open = enic_open,
2166 .ndo_stop = enic_stop,
2167 .ndo_start_xmit = enic_hard_start_xmit,
f20530bc 2168 .ndo_get_stats64 = enic_get_stats,
f8bd9091 2169 .ndo_validate_addr = eth_validate_addr,
319d7e84 2170 .ndo_set_rx_mode = enic_set_rx_mode,
f8bd9091
SF		 2171 .ndo_set_mac_address = enic_set_mac_address_dynamic,
2172 .ndo_change_mtu = enic_change_mtu,
f8bd9091
SF		 2173 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
2174 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
2175 .ndo_tx_timeout = enic_tx_timeout,
2176 .ndo_set_vf_port = enic_set_vf_port,
2177 .ndo_get_vf_port = enic_get_vf_port,
0b1c00fc 2178 .ndo_set_vf_mac = enic_set_vf_mac,
f8bd9091
SF		 2179#ifdef CONFIG_NET_POLL_CONTROLLER
2180 .ndo_poll_controller = enic_poll_controller,
2181#endif
a145df23
GV		 2182#ifdef CONFIG_RFS_ACCEL
2183 .ndo_rx_flow_steer = enic_rx_flow_steer,
2184#endif
14747cd9
GV		 2185#ifdef CONFIG_NET_RX_BUSY_POLL
2186 .ndo_busy_poll = enic_busy_poll,
2187#endif
f8bd9091
SF		 2188};
2189
afe29f7a
SH		 2190static const struct net_device_ops enic_netdev_ops = {
2191 .ndo_open = enic_open,
2192 .ndo_stop = enic_stop,
00829823 2193 .ndo_start_xmit = enic_hard_start_xmit,
f20530bc 2194 .ndo_get_stats64 = enic_get_stats,
afe29f7a 2195 .ndo_validate_addr = eth_validate_addr,
f8bd9091 2196 .ndo_set_mac_address = enic_set_mac_address,
319d7e84 2197 .ndo_set_rx_mode = enic_set_rx_mode,
afe29f7a 2198 .ndo_change_mtu = enic_change_mtu,
afe29f7a
SH		 2199 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
2200 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
2201 .ndo_tx_timeout = enic_tx_timeout,
3f192795
RP		 2202 .ndo_set_vf_port = enic_set_vf_port,
2203 .ndo_get_vf_port = enic_get_vf_port,
2204 .ndo_set_vf_mac = enic_set_vf_mac,
afe29f7a
SH		 2205#ifdef CONFIG_NET_POLL_CONTROLLER
2206 .ndo_poll_controller = enic_poll_controller,
2207#endif
a145df23
GV		 2208#ifdef CONFIG_RFS_ACCEL
2209 .ndo_rx_flow_steer = enic_rx_flow_steer,
2210#endif
14747cd9
GV		 2211#ifdef CONFIG_NET_RX_BUSY_POLL
2212 .ndo_busy_poll = enic_busy_poll,
2213#endif
afe29f7a
SH		 2214};
2215
2fdba388 2216static void enic_dev_deinit(struct enic *enic)
6fdfa970 2217{
717258ba
VK		 2218 unsigned int i;
2219
14747cd9
GV		 2220 for (i = 0; i < enic->rq_count; i++) {
2221 napi_hash_del(&enic->napi[i]);
717258ba 2222 netif_napi_del(&enic->napi[i]);
14747cd9 2223 }
4cfe8785
GV		 2224 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
2225 for (i = 0; i < enic->wq_count; i++)
2226 netif_napi_del(&enic->napi[enic_cq_wq(enic, i)]);
717258ba 2227
6fdfa970
SF		 2228 enic_free_vnic_resources(enic);
2229 enic_clear_intr_mode(enic);
2230}
2231
2fdba388 2232static int enic_dev_init(struct enic *enic)
6fdfa970 2233{
a7a79deb 2234 struct device *dev = enic_get_dev(enic);
6fdfa970 2235 struct net_device *netdev = enic->netdev;
717258ba 2236 unsigned int i;
6fdfa970
SF		 2237 int err;
2238
ea7ea65a
VK		 2239 /* Get interrupt coalesce timer info */
2240 err = enic_dev_intr_coal_timer_info(enic);
2241 if (err) {
2242 dev_warn(dev, "Using default conversion factor for "
2243 "interrupt coalesce timer\n");
2244 vnic_dev_intr_coal_timer_info_default(enic->vdev);
2245 }
2246
6fdfa970
SF		 2247 /* Get vNIC configuration
2248 */
2249
2250 err = enic_get_vnic_config(enic);
2251 if (err) {
a7a79deb 2252 dev_err(dev, "Get vNIC configuration failed, aborting\n");
6fdfa970
SF		 2253 return err;
2254 }
2255
2256 /* Get available resource counts
2257 */
2258
2259 enic_get_res_counts(enic);
2260
2261 /* Set interrupt mode based on resource counts and system
2262 * capabilities
2263 */
2264
2265 err = enic_set_intr_mode(enic);
2266 if (err) {
a7a79deb
VK		 2267 dev_err(dev, "Failed to set intr mode based on resource "
2268 "counts and system capabilities, aborting\n");
6fdfa970
SF		 2269 return err;
2270 }
2271
2272 /* Allocate and configure vNIC resources
2273 */
2274
2275 err = enic_alloc_vnic_resources(enic);
2276 if (err) {
a7a79deb 2277 dev_err(dev, "Failed to alloc vNIC resources, aborting\n");
6fdfa970
SF		 2278 goto err_out_free_vnic_resources;
2279 }
2280
2281 enic_init_vnic_resources(enic);
2282
717258ba 2283 err = enic_set_rss_nic_cfg(enic);
6fdfa970 2284 if (err) {
a7a79deb 2285 dev_err(dev, "Failed to config nic, aborting\n");
6fdfa970
SF		 2286 goto err_out_free_vnic_resources;
2287 }
2288
2289 switch (vnic_dev_get_intr_mode(enic->vdev)) {
2290 default:
717258ba 2291 netif_napi_add(netdev, &enic->napi[0], enic_poll, 64);
14747cd9 2292 napi_hash_add(&enic->napi[0]);
6fdfa970
SF		 2293 break;
2294 case VNIC_DEV_INTR_MODE_MSIX:
14747cd9 2295 for (i = 0; i < enic->rq_count; i++) {
717258ba 2296 netif_napi_add(netdev, &enic->napi[i],
4cfe8785 2297 enic_poll_msix_rq, NAPI_POLL_WEIGHT);
14747cd9
GV		 2298 napi_hash_add(&enic->napi[i]);
2299 }
4cfe8785
GV		 2300 for (i = 0; i < enic->wq_count; i++)
2301 netif_napi_add(netdev, &enic->napi[enic_cq_wq(enic, i)],
2302 enic_poll_msix_wq, NAPI_POLL_WEIGHT);
6fdfa970
SF		 2303 break;
2304 }
2305
2306 return 0;
2307
2308err_out_free_vnic_resources:
2309 enic_clear_intr_mode(enic);
2310 enic_free_vnic_resources(enic);
2311
2312 return err;
2313}
2314
27e6c7d3
SF		 2315static void enic_iounmap(struct enic *enic)
2316{
2317 unsigned int i;
2318
2319 for (i = 0; i < ARRAY_SIZE(enic->bar); i++)
2320 if (enic->bar[i].vaddr)
2321 iounmap(enic->bar[i].vaddr);
2322}
2323
1dd06ae8 2324static int enic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
01f2e4ea 2325{
a7a79deb 2326 struct device *dev = &pdev->dev;
01f2e4ea
SF		 2327 struct net_device *netdev;
2328 struct enic *enic;
2329 int using_dac = 0;
2330 unsigned int i;
2331 int err;
8749b427
RP		 2332#ifdef CONFIG_PCI_IOV
2333 int pos = 0;
2334#endif
b67f231d 2335 int num_pps = 1;
01f2e4ea 2336
01f2e4ea
SF		 2337 /* Allocate net device structure and initialize. Private
2338 * instance data is initialized to zero.
2339 */
2340
822473b6 2341 netdev = alloc_etherdev_mqs(sizeof(struct enic),
2342 ENIC_RQ_MAX, ENIC_WQ_MAX);
41de8d4c 2343 if (!netdev)
01f2e4ea 2344 return -ENOMEM;
01f2e4ea 2345
01f2e4ea
SF		 2346 pci_set_drvdata(pdev, netdev);
2347
2348 SET_NETDEV_DEV(netdev, &pdev->dev);
2349
2350 enic = netdev_priv(netdev);
2351 enic->netdev = netdev;
2352 enic->pdev = pdev;
2353
2354 /* Setup PCI resources
2355 */
2356
29046f9b 2357 err = pci_enable_device_mem(pdev);
01f2e4ea 2358 if (err) {
a7a79deb 2359 dev_err(dev, "Cannot enable PCI device, aborting\n");
01f2e4ea
SF		 2360 goto err_out_free_netdev;
2361 }
2362
2363 err = pci_request_regions(pdev, DRV_NAME);
2364 if (err) {
a7a79deb 2365 dev_err(dev, "Cannot request PCI regions, aborting\n");
01f2e4ea
SF		 2366 goto err_out_disable_device;
2367 }
2368
2369 pci_set_master(pdev);
2370
2371 /* Query PCI controller on system for DMA addressing
624dbf55 2372 * limitation for the device. Try 64-bit first, and
01f2e4ea
SF		 2373 * fail to 32-bit.
2374 */
2375
624dbf55 2376 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
01f2e4ea 2377 if (err) {
284901a9 2378 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
01f2e4ea 2379 if (err) {
a7a79deb 2380 dev_err(dev, "No usable DMA configuration, aborting\n");
01f2e4ea
SF		 2381 goto err_out_release_regions;
2382 }
284901a9 2383 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
01f2e4ea 2384 if (err) {
a7a79deb
VK		 2385 dev_err(dev, "Unable to obtain %u-bit DMA "
2386 "for consistent allocations, aborting\n", 32);
01f2e4ea
SF		 2387 goto err_out_release_regions;
2388 }
2389 } else {
624dbf55 2390 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
01f2e4ea 2391 if (err) {
a7a79deb 2392 dev_err(dev, "Unable to obtain %u-bit DMA "
624dbf55 2393 "for consistent allocations, aborting\n", 64);
01f2e4ea
SF		 2394 goto err_out_release_regions;
2395 }
2396 using_dac = 1;
2397 }
2398
27e6c7d3 2399 /* Map vNIC resources from BAR0-5
01f2e4ea
SF		 2400 */
2401
27e6c7d3
SF		 2402 for (i = 0; i < ARRAY_SIZE(enic->bar); i++) {
2403 if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM))
2404 continue;
2405 enic->bar[i].len = pci_resource_len(pdev, i);
2406 enic->bar[i].vaddr = pci_iomap(pdev, i, enic->bar[i].len);
2407 if (!enic->bar[i].vaddr) {
a7a79deb 2408 dev_err(dev, "Cannot memory-map BAR %d, aborting\n", i);
27e6c7d3
SF		 2409 err = -ENODEV;
2410 goto err_out_iounmap;
2411 }
2412 enic->bar[i].bus_addr = pci_resource_start(pdev, i);
01f2e4ea
SF		 2413 }
2414
2415 /* Register vNIC device
2416 */
2417
27e6c7d3
SF		 2418 enic->vdev = vnic_dev_register(NULL, enic, pdev, enic->bar,
2419 ARRAY_SIZE(enic->bar));
01f2e4ea 2420 if (!enic->vdev) {
a7a79deb 2421 dev_err(dev, "vNIC registration failed, aborting\n");
01f2e4ea
SF		 2422 err = -ENODEV;
2423 goto err_out_iounmap;
2424 }
2425
8749b427
RP		 2426#ifdef CONFIG_PCI_IOV
2427 /* Get number of subvnics */
2428 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
2429 if (pos) {
2430 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF,
413708bb 2431 &enic->num_vfs);
8749b427
RP		 2432 if (enic->num_vfs) {
2433 err = pci_enable_sriov(pdev, enic->num_vfs);
2434 if (err) {
2435 dev_err(dev, "SRIOV enable failed, aborting."
2436 " pci_enable_sriov() returned %d\n",
2437 err);
2438 goto err_out_vnic_unregister;
2439 }
2440 enic->priv_flags |= ENIC_SRIOV_ENABLED;
b67f231d 2441 num_pps = enic->num_vfs;
8749b427
RP		 2442 }
2443 }
8749b427 2444#endif
ca2b721d 2445
3f192795 2446 /* Allocate structure for port profiles */
a1de2219 2447 enic->pp = kcalloc(num_pps, sizeof(*enic->pp), GFP_KERNEL);
3f192795 2448 if (!enic->pp) {
3f192795 2449 err = -ENOMEM;
ca2b721d 2450 goto err_out_disable_sriov_pp;
3f192795
RP		 2451 }
2452
01f2e4ea
SF		 2453 /* Issue device open to get device in known state
2454 */
2455
2456 err = enic_dev_open(enic);
2457 if (err) {
a7a79deb 2458 dev_err(dev, "vNIC dev open failed, aborting\n");
ca2b721d 2459 goto err_out_disable_sriov;
01f2e4ea
SF		 2460 }
2461
69161425
VK		 2462 /* Setup devcmd lock
2463 */
2464
2465 spin_lock_init(&enic->devcmd_lock);
0b038566 2466 spin_lock_init(&enic->enic_api_lock);
69161425
VK		 2467
2468 /*
2469 * Set ingress vlan rewrite mode before vnic initialization
2470 */
2471
2472 err = enic_dev_set_ig_vlan_rewrite_mode(enic);
2473 if (err) {
2474 dev_err(dev,
2475 "Failed to set ingress vlan rewrite mode, aborting.\n");
2476 goto err_out_dev_close;
2477 }
2478
01f2e4ea
SF		 2479 /* Issue device init to initialize the vnic-to-switch link.
2480 * We'll start with carrier off and wait for link UP
2481 * notification later to turn on carrier. We don't need
2482 * to wait here for the vnic-to-switch link initialization
2483 * to complete; link UP notification is the indication that
2484 * the process is complete.
2485 */
2486
2487 netif_carrier_off(netdev);
2488
a7a79deb
VK		 2489 /* Do not call dev_init for a dynamic vnic.
2490 * For a dynamic vnic, init_prov_info will be
2491 * called later by an upper layer.
2492 */
2493
2b68c181 2494 if (!enic_is_dynamic(enic)) {
f8bd9091
SF		 2495 err = vnic_dev_init(enic->vdev, 0);
2496 if (err) {
a7a79deb 2497 dev_err(dev, "vNIC dev init failed, aborting\n");
f8bd9091
SF		 2498 goto err_out_dev_close;
2499 }
01f2e4ea
SF		 2500 }
2501
6fdfa970 2502 err = enic_dev_init(enic);
01f2e4ea 2503 if (err) {
a7a79deb 2504 dev_err(dev, "Device initialization failed, aborting\n");
01f2e4ea
SF		 2505 goto err_out_dev_close;
2506 }
2507
822473b6 2508 netif_set_real_num_tx_queues(netdev, enic->wq_count);
bf751ba8 2509 netif_set_real_num_rx_queues(netdev, enic->rq_count);
822473b6 2510
383ab92f 2511 /* Setup notification timer, HW reset task, and wq locks
01f2e4ea
SF		 2512 */
2513
2514 init_timer(&enic->notify_timer);
2515 enic->notify_timer.function = enic_notify_timer;
2516 enic->notify_timer.data = (unsigned long)enic;
2517
7c2ce6e6 2518 enic_set_rx_coal_setting(enic);
01f2e4ea 2519 INIT_WORK(&enic->reset, enic_reset);
c97c894d 2520 INIT_WORK(&enic->change_mtu_work, enic_change_mtu_work);
01f2e4ea
SF		 2521
2522 for (i = 0; i < enic->wq_count; i++)
2523 spin_lock_init(&enic->wq_lock[i]);
2524
01f2e4ea
SF		 2525 /* Register net device
2526 */
2527
2528 enic->port_mtu = enic->config.mtu;
2529 (void)enic_change_mtu(netdev, enic->port_mtu);
2530
2531 err = enic_set_mac_addr(netdev, enic->mac_addr);
2532 if (err) {
a7a79deb 2533 dev_err(dev, "Invalid MAC address, aborting\n");
6fdfa970 2534 goto err_out_dev_deinit;
01f2e4ea
SF		 2535 }
2536
7c844599 2537 enic->tx_coalesce_usecs = enic->config.intr_timer_usec;
7c2ce6e6
SS		 2538 /* rx coalesce time already got initialized. This gets used
2539 * if adaptive coal is turned off
2540 */
7c844599
SF		 2541 enic->rx_coalesce_usecs = enic->tx_coalesce_usecs;
2542
7335903c 2543 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
f8bd9091
SF		 2544 netdev->netdev_ops = &enic_netdev_dynamic_ops;
2545 else
2546 netdev->netdev_ops = &enic_netdev_ops;
2547
01f2e4ea 2548 netdev->watchdog_timeo = 2 * HZ;
f13bbc2f 2549 enic_set_ethtool_ops(netdev);
01f2e4ea 2550
f646968f 2551 netdev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
1825aca6 2552 if (ENIC_SETTING(enic, LOOP)) {
f646968f 2553 netdev->features &= ~NETIF_F_HW_VLAN_CTAG_TX;
1825aca6
VK		 2554 enic->loop_enable = 1;
2555 enic->loop_tag = enic->config.loop_tag;
2556 dev_info(dev, "loopback tag=0x%04x\n", enic->loop_tag);
2557 }
01f2e4ea 2558 if (ENIC_SETTING(enic, TXCSUM))
5ec8f9b8 2559 netdev->hw_features |= NETIF_F_SG | NETIF_F_HW_CSUM;
01f2e4ea 2560 if (ENIC_SETTING(enic, TSO))
5ec8f9b8 2561 netdev->hw_features |= NETIF_F_TSO |
01f2e4ea 2562 NETIF_F_TSO6 | NETIF_F_TSO_ECN;
bf751ba8 2563 if (ENIC_SETTING(enic, RSS))
2564 netdev->hw_features |= NETIF_F_RXHASH;
5ec8f9b8
MM		 2565 if (ENIC_SETTING(enic, RXCSUM))
2566 netdev->hw_features |= NETIF_F_RXCSUM;
2567
2568 netdev->features |= netdev->hw_features;
2569
a145df23
GV		 2570#ifdef CONFIG_RFS_ACCEL
2571 netdev->hw_features |= NETIF_F_NTUPLE;
2572#endif
2573
01f2e4ea
SF		 2574 if (using_dac)
2575 netdev->features |= NETIF_F_HIGHDMA;
2576
01789349
JP		 2577 netdev->priv_flags |= IFF_UNICAST_FLT;
2578
01f2e4ea
SF		 2579 err = register_netdev(netdev);
2580 if (err) {
a7a79deb 2581 dev_err(dev, "Cannot register net device, aborting\n");
6fdfa970 2582 goto err_out_dev_deinit;
01f2e4ea 2583 }
a03bb56e 2584 enic->rx_copybreak = RX_COPYBREAK_DEFAULT;
01f2e4ea
SF		 2585
2586 return 0;
2587
6fdfa970
SF		 2588err_out_dev_deinit:
2589 enic_dev_deinit(enic);
01f2e4ea
SF		 2590err_out_dev_close:
2591 vnic_dev_close(enic->vdev);
8749b427 2592err_out_disable_sriov:
ca2b721d
RP		 2593 kfree(enic->pp);
2594err_out_disable_sriov_pp:
8749b427
RP		 2595#ifdef CONFIG_PCI_IOV
2596 if (enic_sriov_enabled(enic)) {
2597 pci_disable_sriov(pdev);
2598 enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
2599 }
01f2e4ea 2600err_out_vnic_unregister:
8749b427 2601#endif
35d87e33 2602 vnic_dev_unregister(enic->vdev);
01f2e4ea
SF		 2603err_out_iounmap:
2604 enic_iounmap(enic);
2605err_out_release_regions:
2606 pci_release_regions(pdev);
2607err_out_disable_device:
2608 pci_disable_device(pdev);
2609err_out_free_netdev:
01f2e4ea
SF		 2610 free_netdev(netdev);
2611
2612 return err;
2613}
2614
854de92f 2615static void enic_remove(struct pci_dev *pdev)
01f2e4ea
SF		 2616{
2617 struct net_device *netdev = pci_get_drvdata(pdev);
2618
2619 if (netdev) {
2620 struct enic *enic = netdev_priv(netdev);
2621
23f333a2 2622 cancel_work_sync(&enic->reset);
c97c894d 2623 cancel_work_sync(&enic->change_mtu_work);
01f2e4ea 2624 unregister_netdev(netdev);
6fdfa970 2625 enic_dev_deinit(enic);
01f2e4ea 2626 vnic_dev_close(enic->vdev);
8749b427
RP		 2627#ifdef CONFIG_PCI_IOV
2628 if (enic_sriov_enabled(enic)) {
2629 pci_disable_sriov(pdev);
2630 enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
2631 }
2632#endif
3f192795 2633 kfree(enic->pp);
01f2e4ea
SF		 2634 vnic_dev_unregister(enic->vdev);
2635 enic_iounmap(enic);
2636 pci_release_regions(pdev);
2637 pci_disable_device(pdev);
01f2e4ea
SF		 2638 free_netdev(netdev);
2639 }
2640}
2641
2642static struct pci_driver enic_driver = {
2643 .name = DRV_NAME,
2644 .id_table = enic_id_table,
2645 .probe = enic_probe,
854de92f 2646 .remove = enic_remove,
01f2e4ea
SF		 2647};
2648
2649static int __init enic_init_module(void)
2650{
a7a79deb 2651 pr_info("%s, ver %s\n", DRV_DESCRIPTION, DRV_VERSION);
01f2e4ea
SF		 2652
2653 return pci_register_driver(&enic_driver);
2654}
2655
2656static void __exit enic_cleanup_module(void)
2657{
2658 pci_unregister_driver(&enic_driver);
2659}
2660
2661module_init(enic_init_module);
2662module_exit(enic_cleanup_module);
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