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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
b5680e0b | 20 | * |
230dec61 | 21 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
1da177e4 LT |
22 | */ |
23 | ||
1da177e4 LT |
24 | #include <linux/module.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/ptrace.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/interrupt.h> | |
1da177e4 LT |
32 | #include <linux/delay.h> |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/skbuff.h> | |
4c09eed9 JB |
36 | #include <linux/in.h> |
37 | #include <linux/ip.h> | |
38 | #include <net/ip.h> | |
39 | #include <linux/tcp.h> | |
40 | #include <linux/udp.h> | |
41 | #include <linux/icmp.h> | |
1da177e4 LT |
42 | #include <linux/spinlock.h> |
43 | #include <linux/workqueue.h> | |
44 | #include <linux/bitops.h> | |
6f501b17 SH |
45 | #include <linux/io.h> |
46 | #include <linux/irq.h> | |
196719ec | 47 | #include <linux/clk.h> |
ead73183 | 48 | #include <linux/platform_device.h> |
e6b043d5 | 49 | #include <linux/phy.h> |
5eb32bd0 | 50 | #include <linux/fec.h> |
ca2cc333 SG |
51 | #include <linux/of.h> |
52 | #include <linux/of_device.h> | |
53 | #include <linux/of_gpio.h> | |
54 | #include <linux/of_net.h> | |
5fa9c0fe | 55 | #include <linux/regulator/consumer.h> |
cdffcf1b | 56 | #include <linux/if_vlan.h> |
a68ab98e | 57 | #include <linux/pinctrl/consumer.h> |
1da177e4 | 58 | |
080853af | 59 | #include <asm/cacheflush.h> |
196719ec | 60 | |
1da177e4 | 61 | #include "fec.h" |
1da177e4 | 62 | |
772e42b0 CM |
63 | static void set_multicast_list(struct net_device *ndev); |
64 | ||
085e79ed | 65 | #if defined(CONFIG_ARM) |
196719ec SH |
66 | #define FEC_ALIGNMENT 0xf |
67 | #else | |
68 | #define FEC_ALIGNMENT 0x3 | |
69 | #endif | |
70 | ||
b5680e0b SG |
71 | #define DRIVER_NAME "fec" |
72 | ||
baa70a5c FL |
73 | /* Pause frame feild and FIFO threshold */ |
74 | #define FEC_ENET_FCE (1 << 5) | |
75 | #define FEC_ENET_RSEM_V 0x84 | |
76 | #define FEC_ENET_RSFL_V 16 | |
77 | #define FEC_ENET_RAEM_V 0x8 | |
78 | #define FEC_ENET_RAFL_V 0x8 | |
79 | #define FEC_ENET_OPD_V 0xFFF0 | |
80 | ||
b5680e0b SG |
81 | /* Controller is ENET-MAC */ |
82 | #define FEC_QUIRK_ENET_MAC (1 << 0) | |
83 | /* Controller needs driver to swap frame */ | |
84 | #define FEC_QUIRK_SWAP_FRAME (1 << 1) | |
0ca1e290 SG |
85 | /* Controller uses gasket */ |
86 | #define FEC_QUIRK_USE_GASKET (1 << 2) | |
230dec61 SG |
87 | /* Controller has GBIT support */ |
88 | #define FEC_QUIRK_HAS_GBIT (1 << 3) | |
ff43da86 FL |
89 | /* Controller has extend desc buffer */ |
90 | #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) | |
48496255 SG |
91 | /* Controller has hardware checksum support */ |
92 | #define FEC_QUIRK_HAS_CSUM (1 << 5) | |
cdffcf1b JB |
93 | /* Controller has hardware vlan support */ |
94 | #define FEC_QUIRK_HAS_VLAN (1 << 6) | |
03191656 FL |
95 | /* ENET IP errata ERR006358 |
96 | * | |
97 | * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously | |
98 | * detected as not set during a prior frame transmission, then the | |
99 | * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs | |
100 | * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in | |
03191656 FL |
101 | * frames not being transmitted until there is a 0-to-1 transition on |
102 | * ENET_TDAR[TDAR]. | |
103 | */ | |
104 | #define FEC_QUIRK_ERR006358 (1 << 7) | |
b5680e0b SG |
105 | |
106 | static struct platform_device_id fec_devtype[] = { | |
107 | { | |
0ca1e290 | 108 | /* keep it for coldfire */ |
b5680e0b SG |
109 | .name = DRIVER_NAME, |
110 | .driver_data = 0, | |
0ca1e290 SG |
111 | }, { |
112 | .name = "imx25-fec", | |
113 | .driver_data = FEC_QUIRK_USE_GASKET, | |
114 | }, { | |
115 | .name = "imx27-fec", | |
116 | .driver_data = 0, | |
b5680e0b SG |
117 | }, { |
118 | .name = "imx28-fec", | |
119 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, | |
230dec61 SG |
120 | }, { |
121 | .name = "imx6q-fec", | |
ff43da86 | 122 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | |
cdffcf1b | 123 | FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | |
03191656 | 124 | FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358, |
ca7c4a45 | 125 | }, { |
36803542 | 126 | .name = "mvf600-fec", |
ca7c4a45 | 127 | .driver_data = FEC_QUIRK_ENET_MAC, |
0ca1e290 SG |
128 | }, { |
129 | /* sentinel */ | |
130 | } | |
b5680e0b | 131 | }; |
0ca1e290 | 132 | MODULE_DEVICE_TABLE(platform, fec_devtype); |
b5680e0b | 133 | |
ca2cc333 | 134 | enum imx_fec_type { |
a7dd3219 | 135 | IMX25_FEC = 1, /* runs on i.mx25/50/53 */ |
ca2cc333 SG |
136 | IMX27_FEC, /* runs on i.mx27/35/51 */ |
137 | IMX28_FEC, | |
230dec61 | 138 | IMX6Q_FEC, |
36803542 | 139 | MVF600_FEC, |
ca2cc333 SG |
140 | }; |
141 | ||
142 | static const struct of_device_id fec_dt_ids[] = { | |
143 | { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, | |
144 | { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, | |
145 | { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, | |
230dec61 | 146 | { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, |
36803542 | 147 | { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, |
ca2cc333 SG |
148 | { /* sentinel */ } |
149 | }; | |
150 | MODULE_DEVICE_TABLE(of, fec_dt_ids); | |
151 | ||
49da97dc SG |
152 | static unsigned char macaddr[ETH_ALEN]; |
153 | module_param_array(macaddr, byte, NULL, 0); | |
154 | MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); | |
1da177e4 | 155 | |
49da97dc | 156 | #if defined(CONFIG_M5272) |
1da177e4 LT |
157 | /* |
158 | * Some hardware gets it MAC address out of local flash memory. | |
159 | * if this is non-zero then assume it is the address to get MAC from. | |
160 | */ | |
161 | #if defined(CONFIG_NETtel) | |
162 | #define FEC_FLASHMAC 0xf0006006 | |
163 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
164 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
165 | #elif defined(CONFIG_CANCam) |
166 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
167 | #elif defined (CONFIG_M5272C3) |
168 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
169 | #elif defined(CONFIG_MOD5272) | |
a7dd3219 | 170 | #define FEC_FLASHMAC 0xffc0406b |
1da177e4 LT |
171 | #else |
172 | #define FEC_FLASHMAC 0 | |
173 | #endif | |
43be6366 | 174 | #endif /* CONFIG_M5272 */ |
ead73183 | 175 | |
ff43da86 | 176 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE) |
6b265293 | 177 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
178 | #endif |
179 | ||
22f6b860 | 180 | /* Interrupt events/masks. */ |
1da177e4 LT |
181 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
182 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
183 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
184 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
185 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
186 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
187 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
188 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
189 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
190 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
191 | ||
4bee1f9a | 192 | #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) |
dc975382 | 193 | #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) |
4bee1f9a | 194 | |
cdffcf1b | 195 | /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. |
1da177e4 | 196 | */ |
cdffcf1b | 197 | #define PKT_MAXBUF_SIZE 1522 |
1da177e4 | 198 | #define PKT_MINBUF_SIZE 64 |
cdffcf1b | 199 | #define PKT_MAXBLR_SIZE 1536 |
1da177e4 | 200 | |
4c09eed9 JB |
201 | /* FEC receive acceleration */ |
202 | #define FEC_RACC_IPDIS (1 << 1) | |
203 | #define FEC_RACC_PRODIS (1 << 2) | |
204 | #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) | |
205 | ||
1da177e4 | 206 | /* |
6b265293 | 207 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
208 | * size bits. Other FEC hardware does not, so we need to take that into |
209 | * account when setting it. | |
210 | */ | |
562d2f8c | 211 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
085e79ed | 212 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) |
1da177e4 LT |
213 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
214 | #else | |
215 | #define OPT_FRAME_SIZE 0 | |
216 | #endif | |
217 | ||
e6b043d5 BW |
218 | /* FEC MII MMFR bits definition */ |
219 | #define FEC_MMFR_ST (1 << 30) | |
220 | #define FEC_MMFR_OP_READ (2 << 28) | |
221 | #define FEC_MMFR_OP_WRITE (1 << 28) | |
222 | #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) | |
223 | #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) | |
224 | #define FEC_MMFR_TA (2 << 16) | |
225 | #define FEC_MMFR_DATA(v) (v & 0xffff) | |
1da177e4 | 226 | |
c3b084c2 | 227 | #define FEC_MII_TIMEOUT 30000 /* us */ |
1da177e4 | 228 | |
22f6b860 SH |
229 | /* Transmitter timeout */ |
230 | #define TX_TIMEOUT (2 * HZ) | |
1da177e4 | 231 | |
baa70a5c FL |
232 | #define FEC_PAUSE_FLAG_AUTONEG 0x1 |
233 | #define FEC_PAUSE_FLAG_ENABLE 0x2 | |
234 | ||
e163cc97 LW |
235 | static int mii_cnt; |
236 | ||
36e24e2e DFB |
237 | static inline |
238 | struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep) | |
ff43da86 | 239 | { |
36e24e2e DFB |
240 | struct bufdesc *new_bd = bdp + 1; |
241 | struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1; | |
242 | struct bufdesc_ex *ex_base; | |
243 | struct bufdesc *base; | |
244 | int ring_size; | |
245 | ||
246 | if (bdp >= fep->tx_bd_base) { | |
247 | base = fep->tx_bd_base; | |
248 | ring_size = fep->tx_ring_size; | |
249 | ex_base = (struct bufdesc_ex *)fep->tx_bd_base; | |
250 | } else { | |
251 | base = fep->rx_bd_base; | |
252 | ring_size = fep->rx_ring_size; | |
253 | ex_base = (struct bufdesc_ex *)fep->rx_bd_base; | |
254 | } | |
255 | ||
256 | if (fep->bufdesc_ex) | |
257 | return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ? | |
258 | ex_base : ex_new_bd); | |
ff43da86 | 259 | else |
36e24e2e DFB |
260 | return (new_bd >= (base + ring_size)) ? |
261 | base : new_bd; | |
ff43da86 FL |
262 | } |
263 | ||
36e24e2e DFB |
264 | static inline |
265 | struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep) | |
ff43da86 | 266 | { |
36e24e2e DFB |
267 | struct bufdesc *new_bd = bdp - 1; |
268 | struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1; | |
269 | struct bufdesc_ex *ex_base; | |
270 | struct bufdesc *base; | |
271 | int ring_size; | |
272 | ||
273 | if (bdp >= fep->tx_bd_base) { | |
274 | base = fep->tx_bd_base; | |
275 | ring_size = fep->tx_ring_size; | |
276 | ex_base = (struct bufdesc_ex *)fep->tx_bd_base; | |
277 | } else { | |
278 | base = fep->rx_bd_base; | |
279 | ring_size = fep->rx_ring_size; | |
280 | ex_base = (struct bufdesc_ex *)fep->rx_bd_base; | |
281 | } | |
282 | ||
283 | if (fep->bufdesc_ex) | |
284 | return (struct bufdesc *)((ex_new_bd < ex_base) ? | |
285 | (ex_new_bd + ring_size) : ex_new_bd); | |
ff43da86 | 286 | else |
36e24e2e | 287 | return (new_bd < base) ? (new_bd + ring_size) : new_bd; |
ff43da86 FL |
288 | } |
289 | ||
b5680e0b SG |
290 | static void *swap_buffer(void *bufaddr, int len) |
291 | { | |
292 | int i; | |
293 | unsigned int *buf = bufaddr; | |
294 | ||
ffed61e6 | 295 | for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++) |
b5680e0b SG |
296 | *buf = cpu_to_be32(*buf); |
297 | ||
298 | return bufaddr; | |
299 | } | |
300 | ||
4c09eed9 JB |
301 | static int |
302 | fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) | |
303 | { | |
304 | /* Only run for packets requiring a checksum. */ | |
305 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
306 | return 0; | |
307 | ||
308 | if (unlikely(skb_cow_head(skb, 0))) | |
309 | return -1; | |
310 | ||
311 | *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; | |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
c7621cb3 | 316 | static netdev_tx_t |
c556167f | 317 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
1da177e4 | 318 | { |
c556167f | 319 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
320 | const struct platform_device_id *id_entry = |
321 | platform_get_device_id(fep->pdev); | |
03191656 | 322 | struct bufdesc *bdp, *bdp_pre; |
9555b31e | 323 | void *bufaddr; |
0e702ab3 | 324 | unsigned short status; |
de5fb0a0 | 325 | unsigned int index; |
1da177e4 | 326 | |
1da177e4 LT |
327 | /* Fill in a Tx ring entry */ |
328 | bdp = fep->cur_tx; | |
329 | ||
0e702ab3 | 330 | status = bdp->cbd_sc; |
22f6b860 | 331 | |
0e702ab3 | 332 | if (status & BD_ENET_TX_READY) { |
1da177e4 | 333 | /* Ooops. All transmit buffers are full. Bail out. |
c556167f | 334 | * This should not happen, since ndev->tbusy should be set. |
1da177e4 | 335 | */ |
31b7720c | 336 | netdev_err(ndev, "tx queue full!\n"); |
5b548140 | 337 | return NETDEV_TX_BUSY; |
1da177e4 | 338 | } |
1da177e4 | 339 | |
4c09eed9 JB |
340 | /* Protocol checksum off-load for TCP and UDP. */ |
341 | if (fec_enet_clear_csum(skb, ndev)) { | |
8e7e6874 | 342 | dev_kfree_skb_any(skb); |
4c09eed9 JB |
343 | return NETDEV_TX_OK; |
344 | } | |
345 | ||
22f6b860 | 346 | /* Clear all of the status flags */ |
0e702ab3 | 347 | status &= ~BD_ENET_TX_STATS; |
1da177e4 | 348 | |
22f6b860 | 349 | /* Set buffer length and buffer pointer */ |
9555b31e | 350 | bufaddr = skb->data; |
1da177e4 LT |
351 | bdp->cbd_datlen = skb->len; |
352 | ||
353 | /* | |
22f6b860 SH |
354 | * On some FEC implementations data must be aligned on |
355 | * 4-byte boundaries. Use bounce buffers to copy data | |
356 | * and get it aligned. Ugh. | |
1da177e4 | 357 | */ |
de5fb0a0 FL |
358 | if (fep->bufdesc_ex) |
359 | index = (struct bufdesc_ex *)bdp - | |
360 | (struct bufdesc_ex *)fep->tx_bd_base; | |
361 | else | |
362 | index = bdp - fep->tx_bd_base; | |
363 | ||
9555b31e | 364 | if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { |
8a73b0bc | 365 | memcpy(fep->tx_bounce[index], skb->data, skb->len); |
9555b31e | 366 | bufaddr = fep->tx_bounce[index]; |
1da177e4 LT |
367 | } |
368 | ||
b5680e0b SG |
369 | /* |
370 | * Some design made an incorrect assumption on endian mode of | |
371 | * the system that it's running on. As the result, driver has to | |
372 | * swap every frame going to and coming from the controller. | |
373 | */ | |
374 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) | |
375 | swap_buffer(bufaddr, skb->len); | |
376 | ||
22f6b860 | 377 | /* Save skb pointer */ |
de5fb0a0 | 378 | fep->tx_skbuff[index] = skb; |
6aa20a22 | 379 | |
1da177e4 LT |
380 | /* Push the data cache so the CPM does not get stale memory |
381 | * data. | |
382 | */ | |
d1ab1f54 | 383 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, |
2488a54e | 384 | skb->len, DMA_TO_DEVICE); |
d842a31f DFB |
385 | if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) { |
386 | bdp->cbd_bufaddr = 0; | |
387 | fep->tx_skbuff[index] = NULL; | |
388 | dev_kfree_skb_any(skb); | |
389 | if (net_ratelimit()) | |
390 | netdev_err(ndev, "Tx DMA memory map failed\n"); | |
391 | return NETDEV_TX_OK; | |
392 | } | |
1da177e4 | 393 | |
ff43da86 FL |
394 | if (fep->bufdesc_ex) { |
395 | ||
396 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
397 | ebdp->cbd_bdu = 0; | |
398 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && | |
6605b730 | 399 | fep->hwts_tx_en)) { |
ff43da86 | 400 | ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT); |
6605b730 | 401 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
ff43da86 | 402 | } else { |
ff43da86 | 403 | ebdp->cbd_esc = BD_ENET_TX_INT; |
4c09eed9 JB |
404 | |
405 | /* Enable protocol checksum flags | |
406 | * We do not bother with the IP Checksum bits as they | |
407 | * are done by the kernel | |
408 | */ | |
409 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
410 | ebdp->cbd_esc |= BD_ENET_TX_PINS; | |
ff43da86 | 411 | } |
6605b730 | 412 | } |
03191656 | 413 | |
fb8ef788 DFB |
414 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
415 | * it's the last BD of the frame, and to put the CRC on the end. | |
416 | */ | |
417 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR | |
418 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); | |
419 | bdp->cbd_sc = status; | |
420 | ||
36e24e2e | 421 | bdp_pre = fec_enet_get_prevdesc(bdp, fep); |
03191656 FL |
422 | if ((id_entry->driver_data & FEC_QUIRK_ERR006358) && |
423 | !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) { | |
424 | fep->delay_work.trig_tx = true; | |
425 | schedule_delayed_work(&(fep->delay_work.delay_work), | |
426 | msecs_to_jiffies(1)); | |
427 | } | |
428 | ||
22f6b860 | 429 | /* If this was the last BD in the ring, start at the beginning again. */ |
36e24e2e | 430 | bdp = fec_enet_get_nextdesc(bdp, fep); |
1da177e4 | 431 | |
7a2a8451 ED |
432 | skb_tx_timestamp(skb); |
433 | ||
de5fb0a0 FL |
434 | fep->cur_tx = bdp; |
435 | ||
436 | if (fep->cur_tx == fep->dirty_tx) | |
c556167f | 437 | netif_stop_queue(ndev); |
1da177e4 | 438 | |
de5fb0a0 FL |
439 | /* Trigger transmission start */ |
440 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); | |
1da177e4 | 441 | |
6ed10654 | 442 | return NETDEV_TX_OK; |
1da177e4 LT |
443 | } |
444 | ||
14109a59 FL |
445 | /* Init RX & TX buffer descriptors |
446 | */ | |
447 | static void fec_enet_bd_init(struct net_device *dev) | |
448 | { | |
449 | struct fec_enet_private *fep = netdev_priv(dev); | |
450 | struct bufdesc *bdp; | |
451 | unsigned int i; | |
452 | ||
453 | /* Initialize the receive buffer descriptors. */ | |
454 | bdp = fep->rx_bd_base; | |
36e24e2e | 455 | for (i = 0; i < fep->rx_ring_size; i++) { |
14109a59 FL |
456 | |
457 | /* Initialize the BD for every fragment in the page. */ | |
458 | if (bdp->cbd_bufaddr) | |
459 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
460 | else | |
461 | bdp->cbd_sc = 0; | |
36e24e2e | 462 | bdp = fec_enet_get_nextdesc(bdp, fep); |
14109a59 FL |
463 | } |
464 | ||
465 | /* Set the last buffer to wrap */ | |
36e24e2e | 466 | bdp = fec_enet_get_prevdesc(bdp, fep); |
14109a59 FL |
467 | bdp->cbd_sc |= BD_SC_WRAP; |
468 | ||
469 | fep->cur_rx = fep->rx_bd_base; | |
470 | ||
471 | /* ...and the same for transmit */ | |
472 | bdp = fep->tx_bd_base; | |
473 | fep->cur_tx = bdp; | |
36e24e2e | 474 | for (i = 0; i < fep->tx_ring_size; i++) { |
14109a59 FL |
475 | |
476 | /* Initialize the BD for every fragment in the page. */ | |
477 | bdp->cbd_sc = 0; | |
478 | if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) { | |
479 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
480 | fep->tx_skbuff[i] = NULL; | |
481 | } | |
482 | bdp->cbd_bufaddr = 0; | |
36e24e2e | 483 | bdp = fec_enet_get_nextdesc(bdp, fep); |
14109a59 FL |
484 | } |
485 | ||
486 | /* Set the last buffer to wrap */ | |
36e24e2e | 487 | bdp = fec_enet_get_prevdesc(bdp, fep); |
14109a59 FL |
488 | bdp->cbd_sc |= BD_SC_WRAP; |
489 | fep->dirty_tx = bdp; | |
490 | } | |
491 | ||
45993653 UKK |
492 | /* This function is called to start or restart the FEC during a link |
493 | * change. This only happens when switching between half and full | |
494 | * duplex. | |
495 | */ | |
1da177e4 | 496 | static void |
45993653 | 497 | fec_restart(struct net_device *ndev, int duplex) |
1da177e4 | 498 | { |
c556167f | 499 | struct fec_enet_private *fep = netdev_priv(ndev); |
45993653 UKK |
500 | const struct platform_device_id *id_entry = |
501 | platform_get_device_id(fep->pdev); | |
502 | int i; | |
4c09eed9 | 503 | u32 val; |
cd1f402c UKK |
504 | u32 temp_mac[2]; |
505 | u32 rcntl = OPT_FRAME_SIZE | 0x04; | |
230dec61 | 506 | u32 ecntl = 0x2; /* ETHEREN */ |
1da177e4 | 507 | |
54309fa6 FL |
508 | if (netif_running(ndev)) { |
509 | netif_device_detach(ndev); | |
510 | napi_disable(&fep->napi); | |
511 | netif_stop_queue(ndev); | |
31691344 | 512 | netif_tx_lock_bh(ndev); |
54309fa6 FL |
513 | } |
514 | ||
45993653 UKK |
515 | /* Whack a reset. We should wait for this. */ |
516 | writel(1, fep->hwp + FEC_ECNTRL); | |
517 | udelay(10); | |
1da177e4 | 518 | |
45993653 UKK |
519 | /* |
520 | * enet-mac reset will reset mac address registers too, | |
521 | * so need to reconfigure it. | |
522 | */ | |
523 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
524 | memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); | |
525 | writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); | |
526 | writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); | |
527 | } | |
1da177e4 | 528 | |
45993653 UKK |
529 | /* Clear any outstanding interrupt. */ |
530 | writel(0xffc00000, fep->hwp + FEC_IEVENT); | |
1da177e4 | 531 | |
45993653 UKK |
532 | /* Set maximum receive buffer size. */ |
533 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); | |
1da177e4 | 534 | |
14109a59 FL |
535 | fec_enet_bd_init(ndev); |
536 | ||
45993653 UKK |
537 | /* Set receive and transmit descriptor base. */ |
538 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); | |
ff43da86 FL |
539 | if (fep->bufdesc_ex) |
540 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex) | |
36e24e2e | 541 | * fep->rx_ring_size, fep->hwp + FEC_X_DES_START); |
ff43da86 FL |
542 | else |
543 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) | |
36e24e2e | 544 | * fep->rx_ring_size, fep->hwp + FEC_X_DES_START); |
45993653 | 545 | |
45993653 | 546 | |
45993653 UKK |
547 | for (i = 0; i <= TX_RING_MOD_MASK; i++) { |
548 | if (fep->tx_skbuff[i]) { | |
549 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
550 | fep->tx_skbuff[i] = NULL; | |
1da177e4 | 551 | } |
45993653 | 552 | } |
97b72e43 | 553 | |
45993653 UKK |
554 | /* Enable MII mode */ |
555 | if (duplex) { | |
cd1f402c | 556 | /* FD enable */ |
45993653 UKK |
557 | writel(0x04, fep->hwp + FEC_X_CNTRL); |
558 | } else { | |
cd1f402c UKK |
559 | /* No Rcv on Xmit */ |
560 | rcntl |= 0x02; | |
45993653 UKK |
561 | writel(0x0, fep->hwp + FEC_X_CNTRL); |
562 | } | |
cd1f402c | 563 | |
45993653 UKK |
564 | fep->full_duplex = duplex; |
565 | ||
566 | /* Set MII speed */ | |
567 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
568 | ||
d1391930 | 569 | #if !defined(CONFIG_M5272) |
4c09eed9 JB |
570 | /* set RX checksum */ |
571 | val = readl(fep->hwp + FEC_RACC); | |
572 | if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) | |
573 | val |= FEC_RACC_OPTIONS; | |
574 | else | |
575 | val &= ~FEC_RACC_OPTIONS; | |
576 | writel(val, fep->hwp + FEC_RACC); | |
d1391930 | 577 | #endif |
4c09eed9 | 578 | |
45993653 UKK |
579 | /* |
580 | * The phy interface and speed need to get configured | |
581 | * differently on enet-mac. | |
582 | */ | |
583 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
cd1f402c UKK |
584 | /* Enable flow control and length check */ |
585 | rcntl |= 0x40000000 | 0x00000020; | |
45993653 | 586 | |
230dec61 SG |
587 | /* RGMII, RMII or MII */ |
588 | if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) | |
589 | rcntl |= (1 << 6); | |
590 | else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) | |
cd1f402c | 591 | rcntl |= (1 << 8); |
45993653 | 592 | else |
cd1f402c | 593 | rcntl &= ~(1 << 8); |
45993653 | 594 | |
230dec61 SG |
595 | /* 1G, 100M or 10M */ |
596 | if (fep->phy_dev) { | |
597 | if (fep->phy_dev->speed == SPEED_1000) | |
598 | ecntl |= (1 << 5); | |
599 | else if (fep->phy_dev->speed == SPEED_100) | |
600 | rcntl &= ~(1 << 9); | |
601 | else | |
602 | rcntl |= (1 << 9); | |
603 | } | |
45993653 UKK |
604 | } else { |
605 | #ifdef FEC_MIIGSK_ENR | |
0ca1e290 | 606 | if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { |
8d82f219 | 607 | u32 cfgr; |
45993653 UKK |
608 | /* disable the gasket and wait */ |
609 | writel(0, fep->hwp + FEC_MIIGSK_ENR); | |
610 | while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) | |
611 | udelay(1); | |
612 | ||
613 | /* | |
614 | * configure the gasket: | |
615 | * RMII, 50 MHz, no loopback, no echo | |
0ca1e290 | 616 | * MII, 25 MHz, no loopback, no echo |
45993653 | 617 | */ |
8d82f219 EB |
618 | cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) |
619 | ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; | |
620 | if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) | |
621 | cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; | |
622 | writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); | |
45993653 UKK |
623 | |
624 | /* re-enable the gasket */ | |
625 | writel(2, fep->hwp + FEC_MIIGSK_ENR); | |
97b72e43 | 626 | } |
45993653 UKK |
627 | #endif |
628 | } | |
baa70a5c | 629 | |
d1391930 | 630 | #if !defined(CONFIG_M5272) |
baa70a5c FL |
631 | /* enable pause frame*/ |
632 | if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || | |
633 | ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && | |
634 | fep->phy_dev && fep->phy_dev->pause)) { | |
635 | rcntl |= FEC_ENET_FCE; | |
636 | ||
4c09eed9 | 637 | /* set FIFO threshold parameter to reduce overrun */ |
baa70a5c FL |
638 | writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); |
639 | writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); | |
640 | writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); | |
641 | writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); | |
642 | ||
643 | /* OPD */ | |
644 | writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); | |
645 | } else { | |
646 | rcntl &= ~FEC_ENET_FCE; | |
647 | } | |
d1391930 | 648 | #endif /* !defined(CONFIG_M5272) */ |
baa70a5c | 649 | |
cd1f402c | 650 | writel(rcntl, fep->hwp + FEC_R_CNTRL); |
3b2b74ca | 651 | |
84fe6182 SW |
652 | /* Setup multicast filter. */ |
653 | set_multicast_list(ndev); | |
654 | #ifndef CONFIG_M5272 | |
655 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); | |
656 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
657 | #endif | |
658 | ||
230dec61 SG |
659 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
660 | /* enable ENET endian swap */ | |
661 | ecntl |= (1 << 8); | |
662 | /* enable ENET store and forward mode */ | |
663 | writel(1 << 8, fep->hwp + FEC_X_WMRK); | |
664 | } | |
665 | ||
ff43da86 FL |
666 | if (fep->bufdesc_ex) |
667 | ecntl |= (1 << 4); | |
6605b730 | 668 | |
38ae92dc | 669 | #ifndef CONFIG_M5272 |
b9eef55c JB |
670 | /* Enable the MIB statistic event counters */ |
671 | writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); | |
38ae92dc CH |
672 | #endif |
673 | ||
45993653 | 674 | /* And last, enable the transmit and receive processing */ |
230dec61 | 675 | writel(ecntl, fep->hwp + FEC_ECNTRL); |
45993653 UKK |
676 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); |
677 | ||
ff43da86 FL |
678 | if (fep->bufdesc_ex) |
679 | fec_ptp_start_cyclecounter(ndev); | |
680 | ||
45993653 UKK |
681 | /* Enable interrupts we wish to service */ |
682 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
54309fa6 FL |
683 | |
684 | if (netif_running(ndev)) { | |
31691344 | 685 | netif_tx_unlock_bh(ndev); |
54309fa6 | 686 | netif_wake_queue(ndev); |
1ed0d56c FE |
687 | napi_enable(&fep->napi); |
688 | netif_device_attach(ndev); | |
54309fa6 | 689 | } |
45993653 UKK |
690 | } |
691 | ||
692 | static void | |
693 | fec_stop(struct net_device *ndev) | |
694 | { | |
695 | struct fec_enet_private *fep = netdev_priv(ndev); | |
230dec61 SG |
696 | const struct platform_device_id *id_entry = |
697 | platform_get_device_id(fep->pdev); | |
42431dc2 | 698 | u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); |
45993653 UKK |
699 | |
700 | /* We cannot expect a graceful transmit stop without link !!! */ | |
701 | if (fep->link) { | |
702 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
703 | udelay(10); | |
704 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) | |
31b7720c | 705 | netdev_err(ndev, "Graceful transmit stop did not complete!\n"); |
45993653 UKK |
706 | } |
707 | ||
708 | /* Whack a reset. We should wait for this. */ | |
709 | writel(1, fep->hwp + FEC_ECNTRL); | |
710 | udelay(10); | |
711 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
712 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
230dec61 SG |
713 | |
714 | /* We have to keep ENET enabled to have MII interrupt stay working */ | |
42431dc2 | 715 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
230dec61 | 716 | writel(2, fep->hwp + FEC_ECNTRL); |
42431dc2 LW |
717 | writel(rmii_mode, fep->hwp + FEC_R_CNTRL); |
718 | } | |
1da177e4 LT |
719 | } |
720 | ||
721 | ||
45993653 UKK |
722 | static void |
723 | fec_timeout(struct net_device *ndev) | |
724 | { | |
725 | struct fec_enet_private *fep = netdev_priv(ndev); | |
726 | ||
727 | ndev->stats.tx_errors++; | |
728 | ||
54309fa6 FL |
729 | fep->delay_work.timeout = true; |
730 | schedule_delayed_work(&(fep->delay_work.delay_work), 0); | |
731 | } | |
732 | ||
733 | static void fec_enet_work(struct work_struct *work) | |
734 | { | |
735 | struct fec_enet_private *fep = | |
736 | container_of(work, | |
737 | struct fec_enet_private, | |
738 | delay_work.delay_work.work); | |
739 | ||
740 | if (fep->delay_work.timeout) { | |
741 | fep->delay_work.timeout = false; | |
742 | fec_restart(fep->netdev, fep->full_duplex); | |
743 | netif_wake_queue(fep->netdev); | |
744 | } | |
03191656 FL |
745 | |
746 | if (fep->delay_work.trig_tx) { | |
747 | fep->delay_work.trig_tx = false; | |
748 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); | |
749 | } | |
45993653 UKK |
750 | } |
751 | ||
1da177e4 | 752 | static void |
c556167f | 753 | fec_enet_tx(struct net_device *ndev) |
1da177e4 LT |
754 | { |
755 | struct fec_enet_private *fep; | |
2e28532f | 756 | struct bufdesc *bdp; |
0e702ab3 | 757 | unsigned short status; |
1da177e4 | 758 | struct sk_buff *skb; |
de5fb0a0 | 759 | int index = 0; |
1da177e4 | 760 | |
c556167f | 761 | fep = netdev_priv(ndev); |
1da177e4 LT |
762 | bdp = fep->dirty_tx; |
763 | ||
de5fb0a0 | 764 | /* get next bdp of dirty_tx */ |
36e24e2e | 765 | bdp = fec_enet_get_nextdesc(bdp, fep); |
de5fb0a0 | 766 | |
0e702ab3 | 767 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
de5fb0a0 FL |
768 | |
769 | /* current queue is empty */ | |
770 | if (bdp == fep->cur_tx) | |
f0b3fbea SH |
771 | break; |
772 | ||
de5fb0a0 FL |
773 | if (fep->bufdesc_ex) |
774 | index = (struct bufdesc_ex *)bdp - | |
775 | (struct bufdesc_ex *)fep->tx_bd_base; | |
776 | else | |
777 | index = bdp - fep->tx_bd_base; | |
778 | ||
de5fb0a0 | 779 | skb = fep->tx_skbuff[index]; |
2488a54e SS |
780 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, skb->len, |
781 | DMA_TO_DEVICE); | |
782 | bdp->cbd_bufaddr = 0; | |
de5fb0a0 | 783 | |
1da177e4 | 784 | /* Check for errors. */ |
0e702ab3 | 785 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
786 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
787 | BD_ENET_TX_CSL)) { | |
c556167f | 788 | ndev->stats.tx_errors++; |
0e702ab3 | 789 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
c556167f | 790 | ndev->stats.tx_heartbeat_errors++; |
0e702ab3 | 791 | if (status & BD_ENET_TX_LC) /* Late collision */ |
c556167f | 792 | ndev->stats.tx_window_errors++; |
0e702ab3 | 793 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
c556167f | 794 | ndev->stats.tx_aborted_errors++; |
0e702ab3 | 795 | if (status & BD_ENET_TX_UN) /* Underrun */ |
c556167f | 796 | ndev->stats.tx_fifo_errors++; |
0e702ab3 | 797 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
c556167f | 798 | ndev->stats.tx_carrier_errors++; |
1da177e4 | 799 | } else { |
c556167f | 800 | ndev->stats.tx_packets++; |
06efce71 | 801 | ndev->stats.tx_bytes += bdp->cbd_datlen; |
1da177e4 LT |
802 | } |
803 | ||
ff43da86 FL |
804 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && |
805 | fep->bufdesc_ex) { | |
6605b730 FL |
806 | struct skb_shared_hwtstamps shhwtstamps; |
807 | unsigned long flags; | |
ff43da86 | 808 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; |
6605b730 FL |
809 | |
810 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
811 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
812 | shhwtstamps.hwtstamp = ns_to_ktime( | |
ff43da86 | 813 | timecounter_cyc2time(&fep->tc, ebdp->ts)); |
6605b730 FL |
814 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
815 | skb_tstamp_tx(skb, &shhwtstamps); | |
816 | } | |
ff43da86 | 817 | |
0e702ab3 | 818 | if (status & BD_ENET_TX_READY) |
31b7720c | 819 | netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n"); |
22f6b860 | 820 | |
1da177e4 LT |
821 | /* Deferred means some collisions occurred during transmit, |
822 | * but we eventually sent the packet OK. | |
823 | */ | |
0e702ab3 | 824 | if (status & BD_ENET_TX_DEF) |
c556167f | 825 | ndev->stats.collisions++; |
6aa20a22 | 826 | |
22f6b860 | 827 | /* Free the sk buffer associated with this last transmit */ |
1da177e4 | 828 | dev_kfree_skb_any(skb); |
de5fb0a0 FL |
829 | fep->tx_skbuff[index] = NULL; |
830 | ||
831 | fep->dirty_tx = bdp; | |
6aa20a22 | 832 | |
22f6b860 | 833 | /* Update pointer to next buffer descriptor to be transmitted */ |
36e24e2e | 834 | bdp = fec_enet_get_nextdesc(bdp, fep); |
6aa20a22 | 835 | |
22f6b860 | 836 | /* Since we have freed up a buffer, the ring is no longer full |
1da177e4 | 837 | */ |
de5fb0a0 | 838 | if (fep->dirty_tx != fep->cur_tx) { |
c556167f UKK |
839 | if (netif_queue_stopped(ndev)) |
840 | netif_wake_queue(ndev); | |
1da177e4 LT |
841 | } |
842 | } | |
de5fb0a0 | 843 | return; |
1da177e4 LT |
844 | } |
845 | ||
846 | ||
847 | /* During a receive, the cur_rx points to the current incoming buffer. | |
848 | * When we update through the ring, if the next incoming buffer has | |
849 | * not been given to the system, we just set the empty indicator, | |
850 | * effectively tossing the packet. | |
851 | */ | |
dc975382 FL |
852 | static int |
853 | fec_enet_rx(struct net_device *ndev, int budget) | |
1da177e4 | 854 | { |
c556167f | 855 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
856 | const struct platform_device_id *id_entry = |
857 | platform_get_device_id(fep->pdev); | |
2e28532f | 858 | struct bufdesc *bdp; |
0e702ab3 | 859 | unsigned short status; |
1da177e4 LT |
860 | struct sk_buff *skb; |
861 | ushort pkt_len; | |
862 | __u8 *data; | |
dc975382 | 863 | int pkt_received = 0; |
cdffcf1b JB |
864 | struct bufdesc_ex *ebdp = NULL; |
865 | bool vlan_packet_rcvd = false; | |
866 | u16 vlan_tag; | |
d842a31f | 867 | int index = 0; |
6aa20a22 | 868 | |
0e702ab3 GU |
869 | #ifdef CONFIG_M532x |
870 | flush_cache_all(); | |
6aa20a22 | 871 | #endif |
1da177e4 | 872 | |
1da177e4 LT |
873 | /* First, grab all of the stats for the incoming packet. |
874 | * These get messed up if we get called due to a busy condition. | |
875 | */ | |
876 | bdp = fep->cur_rx; | |
877 | ||
22f6b860 | 878 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 | 879 | |
dc975382 FL |
880 | if (pkt_received >= budget) |
881 | break; | |
882 | pkt_received++; | |
883 | ||
22f6b860 SH |
884 | /* Since we have allocated space to hold a complete frame, |
885 | * the last indicator should be set. | |
886 | */ | |
887 | if ((status & BD_ENET_RX_LAST) == 0) | |
31b7720c | 888 | netdev_err(ndev, "rcv is not +last\n"); |
1da177e4 | 889 | |
22f6b860 SH |
890 | if (!fep->opened) |
891 | goto rx_processing_done; | |
1da177e4 | 892 | |
22f6b860 SH |
893 | /* Check for errors. */ |
894 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | | |
1da177e4 | 895 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
c556167f | 896 | ndev->stats.rx_errors++; |
22f6b860 SH |
897 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
898 | /* Frame too long or too short. */ | |
c556167f | 899 | ndev->stats.rx_length_errors++; |
22f6b860 SH |
900 | } |
901 | if (status & BD_ENET_RX_NO) /* Frame alignment */ | |
c556167f | 902 | ndev->stats.rx_frame_errors++; |
22f6b860 | 903 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
c556167f | 904 | ndev->stats.rx_crc_errors++; |
22f6b860 | 905 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
c556167f | 906 | ndev->stats.rx_fifo_errors++; |
1da177e4 | 907 | } |
1da177e4 | 908 | |
22f6b860 SH |
909 | /* Report late collisions as a frame error. |
910 | * On this error, the BD is closed, but we don't know what we | |
911 | * have in the buffer. So, just drop this frame on the floor. | |
912 | */ | |
913 | if (status & BD_ENET_RX_CL) { | |
c556167f UKK |
914 | ndev->stats.rx_errors++; |
915 | ndev->stats.rx_frame_errors++; | |
22f6b860 SH |
916 | goto rx_processing_done; |
917 | } | |
1da177e4 | 918 | |
22f6b860 | 919 | /* Process the incoming frame. */ |
c556167f | 920 | ndev->stats.rx_packets++; |
22f6b860 | 921 | pkt_len = bdp->cbd_datlen; |
c556167f | 922 | ndev->stats.rx_bytes += pkt_len; |
1da177e4 | 923 | |
d842a31f DFB |
924 | if (fep->bufdesc_ex) |
925 | index = (struct bufdesc_ex *)bdp - | |
926 | (struct bufdesc_ex *)fep->rx_bd_base; | |
927 | else | |
928 | index = bdp - fep->rx_bd_base; | |
929 | data = fep->rx_skbuff[index]->data; | |
930 | dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr, | |
931 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); | |
ccdc4f19 | 932 | |
b5680e0b SG |
933 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) |
934 | swap_buffer(data, pkt_len); | |
935 | ||
cdffcf1b JB |
936 | /* Extract the enhanced buffer descriptor */ |
937 | ebdp = NULL; | |
938 | if (fep->bufdesc_ex) | |
939 | ebdp = (struct bufdesc_ex *)bdp; | |
940 | ||
941 | /* If this is a VLAN packet remove the VLAN Tag */ | |
942 | vlan_packet_rcvd = false; | |
943 | if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && | |
944 | fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) { | |
945 | /* Push and remove the vlan tag */ | |
946 | struct vlan_hdr *vlan_header = | |
947 | (struct vlan_hdr *) (data + ETH_HLEN); | |
948 | vlan_tag = ntohs(vlan_header->h_vlan_TCI); | |
949 | pkt_len -= VLAN_HLEN; | |
950 | ||
951 | vlan_packet_rcvd = true; | |
952 | } | |
953 | ||
22f6b860 SH |
954 | /* This does 16 byte alignment, exactly what we need. |
955 | * The packet length includes FCS, but we don't want to | |
956 | * include that when passing upstream as it messes up | |
957 | * bridging applications. | |
958 | */ | |
b72061a3 | 959 | skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); |
1da177e4 | 960 | |
8549889c | 961 | if (unlikely(!skb)) { |
c556167f | 962 | ndev->stats.rx_dropped++; |
22f6b860 | 963 | } else { |
cdffcf1b | 964 | int payload_offset = (2 * ETH_ALEN); |
8549889c | 965 | skb_reserve(skb, NET_IP_ALIGN); |
22f6b860 | 966 | skb_put(skb, pkt_len - 4); /* Make room */ |
cdffcf1b JB |
967 | |
968 | /* Extract the frame data without the VLAN header. */ | |
969 | skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN)); | |
970 | if (vlan_packet_rcvd) | |
971 | payload_offset = (2 * ETH_ALEN) + VLAN_HLEN; | |
972 | skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN), | |
973 | data + payload_offset, | |
974 | pkt_len - 4 - (2 * ETH_ALEN)); | |
975 | ||
c556167f | 976 | skb->protocol = eth_type_trans(skb, ndev); |
ff43da86 | 977 | |
6605b730 | 978 | /* Get receive timestamp from the skb */ |
ff43da86 | 979 | if (fep->hwts_rx_en && fep->bufdesc_ex) { |
6605b730 FL |
980 | struct skb_shared_hwtstamps *shhwtstamps = |
981 | skb_hwtstamps(skb); | |
982 | unsigned long flags; | |
983 | ||
984 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
985 | ||
986 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
987 | shhwtstamps->hwtstamp = ns_to_ktime( | |
ff43da86 | 988 | timecounter_cyc2time(&fep->tc, ebdp->ts)); |
6605b730 FL |
989 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
990 | } | |
ff43da86 | 991 | |
4c09eed9 | 992 | if (fep->bufdesc_ex && |
cdffcf1b | 993 | (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { |
4c09eed9 JB |
994 | if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) { |
995 | /* don't check it */ | |
996 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
997 | } else { | |
998 | skb_checksum_none_assert(skb); | |
999 | } | |
1000 | } | |
1001 | ||
cdffcf1b JB |
1002 | /* Handle received VLAN packets */ |
1003 | if (vlan_packet_rcvd) | |
1004 | __vlan_hwaccel_put_tag(skb, | |
1005 | htons(ETH_P_8021Q), | |
1006 | vlan_tag); | |
1007 | ||
0affdf34 | 1008 | napi_gro_receive(&fep->napi, skb); |
22f6b860 | 1009 | } |
f0b3fbea | 1010 | |
d842a31f DFB |
1011 | dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr, |
1012 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); | |
22f6b860 SH |
1013 | rx_processing_done: |
1014 | /* Clear the status flags for this buffer */ | |
1015 | status &= ~BD_ENET_RX_STATS; | |
1da177e4 | 1016 | |
22f6b860 SH |
1017 | /* Mark the buffer empty */ |
1018 | status |= BD_ENET_RX_EMPTY; | |
1019 | bdp->cbd_sc = status; | |
6aa20a22 | 1020 | |
ff43da86 FL |
1021 | if (fep->bufdesc_ex) { |
1022 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
1023 | ||
1024 | ebdp->cbd_esc = BD_ENET_RX_INT; | |
1025 | ebdp->cbd_prot = 0; | |
1026 | ebdp->cbd_bdu = 0; | |
1027 | } | |
6605b730 | 1028 | |
22f6b860 | 1029 | /* Update BD pointer to next entry */ |
36e24e2e DFB |
1030 | bdp = fec_enet_get_nextdesc(bdp, fep); |
1031 | ||
22f6b860 SH |
1032 | /* Doing this here will keep the FEC running while we process |
1033 | * incoming frames. On a heavily loaded network, we should be | |
1034 | * able to keep up at the expense of system resources. | |
1035 | */ | |
1036 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
1037 | } | |
2e28532f | 1038 | fep->cur_rx = bdp; |
1da177e4 | 1039 | |
dc975382 | 1040 | return pkt_received; |
1da177e4 LT |
1041 | } |
1042 | ||
45993653 UKK |
1043 | static irqreturn_t |
1044 | fec_enet_interrupt(int irq, void *dev_id) | |
1045 | { | |
1046 | struct net_device *ndev = dev_id; | |
1047 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1048 | uint int_events; | |
1049 | irqreturn_t ret = IRQ_NONE; | |
1050 | ||
1051 | do { | |
1052 | int_events = readl(fep->hwp + FEC_IEVENT); | |
1053 | writel(int_events, fep->hwp + FEC_IEVENT); | |
1054 | ||
de5fb0a0 | 1055 | if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) { |
45993653 | 1056 | ret = IRQ_HANDLED; |
dc975382 FL |
1057 | |
1058 | /* Disable the RX interrupt */ | |
1059 | if (napi_schedule_prep(&fep->napi)) { | |
1060 | writel(FEC_RX_DISABLED_IMASK, | |
1061 | fep->hwp + FEC_IMASK); | |
1062 | __napi_schedule(&fep->napi); | |
1063 | } | |
45993653 UKK |
1064 | } |
1065 | ||
45993653 UKK |
1066 | if (int_events & FEC_ENET_MII) { |
1067 | ret = IRQ_HANDLED; | |
1068 | complete(&fep->mdio_done); | |
1069 | } | |
1070 | } while (int_events); | |
1071 | ||
1072 | return ret; | |
1073 | } | |
1074 | ||
dc975382 FL |
1075 | static int fec_enet_rx_napi(struct napi_struct *napi, int budget) |
1076 | { | |
1077 | struct net_device *ndev = napi->dev; | |
1078 | int pkts = fec_enet_rx(ndev, budget); | |
1079 | struct fec_enet_private *fep = netdev_priv(ndev); | |
45993653 | 1080 | |
de5fb0a0 FL |
1081 | fec_enet_tx(ndev); |
1082 | ||
dc975382 FL |
1083 | if (pkts < budget) { |
1084 | napi_complete(napi); | |
1085 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
1086 | } | |
1087 | return pkts; | |
1088 | } | |
45993653 | 1089 | |
e6b043d5 | 1090 | /* ------------------------------------------------------------------------- */ |
0c7768a0 | 1091 | static void fec_get_mac(struct net_device *ndev) |
1da177e4 | 1092 | { |
c556167f | 1093 | struct fec_enet_private *fep = netdev_priv(ndev); |
94660ba0 | 1094 | struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); |
e6b043d5 | 1095 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 | 1096 | |
49da97dc SG |
1097 | /* |
1098 | * try to get mac address in following order: | |
1099 | * | |
1100 | * 1) module parameter via kernel command line in form | |
1101 | * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 | |
1102 | */ | |
1103 | iap = macaddr; | |
1104 | ||
ca2cc333 SG |
1105 | /* |
1106 | * 2) from device tree data | |
1107 | */ | |
1108 | if (!is_valid_ether_addr(iap)) { | |
1109 | struct device_node *np = fep->pdev->dev.of_node; | |
1110 | if (np) { | |
1111 | const char *mac = of_get_mac_address(np); | |
1112 | if (mac) | |
1113 | iap = (unsigned char *) mac; | |
1114 | } | |
1115 | } | |
ca2cc333 | 1116 | |
49da97dc | 1117 | /* |
ca2cc333 | 1118 | * 3) from flash or fuse (via platform data) |
49da97dc SG |
1119 | */ |
1120 | if (!is_valid_ether_addr(iap)) { | |
1121 | #ifdef CONFIG_M5272 | |
1122 | if (FEC_FLASHMAC) | |
1123 | iap = (unsigned char *)FEC_FLASHMAC; | |
1124 | #else | |
1125 | if (pdata) | |
589efdc7 | 1126 | iap = (unsigned char *)&pdata->mac; |
49da97dc SG |
1127 | #endif |
1128 | } | |
1129 | ||
1130 | /* | |
ca2cc333 | 1131 | * 4) FEC mac registers set by bootloader |
49da97dc SG |
1132 | */ |
1133 | if (!is_valid_ether_addr(iap)) { | |
7d7628f3 DC |
1134 | *((__be32 *) &tmpaddr[0]) = |
1135 | cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); | |
1136 | *((__be16 *) &tmpaddr[4]) = | |
1137 | cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
e6b043d5 | 1138 | iap = &tmpaddr[0]; |
1da177e4 LT |
1139 | } |
1140 | ||
ff5b2fab LS |
1141 | /* |
1142 | * 5) random mac address | |
1143 | */ | |
1144 | if (!is_valid_ether_addr(iap)) { | |
1145 | /* Report it and use a random ethernet address instead */ | |
1146 | netdev_err(ndev, "Invalid MAC address: %pM\n", iap); | |
1147 | eth_hw_addr_random(ndev); | |
1148 | netdev_info(ndev, "Using random MAC address: %pM\n", | |
1149 | ndev->dev_addr); | |
1150 | return; | |
1151 | } | |
1152 | ||
c556167f | 1153 | memcpy(ndev->dev_addr, iap, ETH_ALEN); |
1da177e4 | 1154 | |
49da97dc SG |
1155 | /* Adjust MAC if using macaddr */ |
1156 | if (iap == macaddr) | |
43af940c | 1157 | ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; |
1da177e4 LT |
1158 | } |
1159 | ||
e6b043d5 | 1160 | /* ------------------------------------------------------------------------- */ |
1da177e4 | 1161 | |
e6b043d5 BW |
1162 | /* |
1163 | * Phy section | |
1164 | */ | |
c556167f | 1165 | static void fec_enet_adjust_link(struct net_device *ndev) |
1da177e4 | 1166 | { |
c556167f | 1167 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1168 | struct phy_device *phy_dev = fep->phy_dev; |
e6b043d5 | 1169 | int status_change = 0; |
1da177e4 | 1170 | |
e6b043d5 BW |
1171 | /* Prevent a state halted on mii error */ |
1172 | if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { | |
1173 | phy_dev->state = PHY_RESUMING; | |
54309fa6 | 1174 | return; |
e6b043d5 | 1175 | } |
1da177e4 | 1176 | |
e6b043d5 | 1177 | if (phy_dev->link) { |
d97e7497 | 1178 | if (!fep->link) { |
6ea0722f | 1179 | fep->link = phy_dev->link; |
e6b043d5 BW |
1180 | status_change = 1; |
1181 | } | |
1da177e4 | 1182 | |
d97e7497 LS |
1183 | if (fep->full_duplex != phy_dev->duplex) |
1184 | status_change = 1; | |
1185 | ||
1186 | if (phy_dev->speed != fep->speed) { | |
1187 | fep->speed = phy_dev->speed; | |
1188 | status_change = 1; | |
1189 | } | |
1190 | ||
1191 | /* if any of the above changed restart the FEC */ | |
1192 | if (status_change) | |
c556167f | 1193 | fec_restart(ndev, phy_dev->duplex); |
d97e7497 LS |
1194 | } else { |
1195 | if (fep->link) { | |
c556167f | 1196 | fec_stop(ndev); |
8d7ed0f0 | 1197 | fep->link = phy_dev->link; |
d97e7497 LS |
1198 | status_change = 1; |
1199 | } | |
1da177e4 | 1200 | } |
6aa20a22 | 1201 | |
e6b043d5 BW |
1202 | if (status_change) |
1203 | phy_print_status(phy_dev); | |
1204 | } | |
1da177e4 | 1205 | |
e6b043d5 | 1206 | static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
1da177e4 | 1207 | { |
e6b043d5 | 1208 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 1209 | unsigned long time_left; |
1da177e4 | 1210 | |
e6b043d5 | 1211 | fep->mii_timeout = 0; |
97b72e43 | 1212 | init_completion(&fep->mdio_done); |
e6b043d5 BW |
1213 | |
1214 | /* start a read op */ | |
1215 | writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | | |
1216 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | | |
1217 | FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); | |
1218 | ||
1219 | /* wait for end of transfer */ | |
97b72e43 BS |
1220 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
1221 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
1222 | if (time_left == 0) { | |
1223 | fep->mii_timeout = 1; | |
31b7720c | 1224 | netdev_err(fep->netdev, "MDIO read timeout\n"); |
97b72e43 | 1225 | return -ETIMEDOUT; |
1da177e4 | 1226 | } |
1da177e4 | 1227 | |
e6b043d5 BW |
1228 | /* return value */ |
1229 | return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); | |
7dd6a2aa | 1230 | } |
6aa20a22 | 1231 | |
e6b043d5 BW |
1232 | static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
1233 | u16 value) | |
1da177e4 | 1234 | { |
e6b043d5 | 1235 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 1236 | unsigned long time_left; |
1da177e4 | 1237 | |
e6b043d5 | 1238 | fep->mii_timeout = 0; |
97b72e43 | 1239 | init_completion(&fep->mdio_done); |
1da177e4 | 1240 | |
862f0982 SG |
1241 | /* start a write op */ |
1242 | writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | | |
e6b043d5 BW |
1243 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | |
1244 | FEC_MMFR_TA | FEC_MMFR_DATA(value), | |
1245 | fep->hwp + FEC_MII_DATA); | |
1246 | ||
1247 | /* wait for end of transfer */ | |
97b72e43 BS |
1248 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
1249 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
1250 | if (time_left == 0) { | |
1251 | fep->mii_timeout = 1; | |
31b7720c | 1252 | netdev_err(fep->netdev, "MDIO write timeout\n"); |
97b72e43 | 1253 | return -ETIMEDOUT; |
e6b043d5 | 1254 | } |
1da177e4 | 1255 | |
e6b043d5 BW |
1256 | return 0; |
1257 | } | |
1da177e4 | 1258 | |
e8fcfcd5 NA |
1259 | static int fec_enet_clk_enable(struct net_device *ndev, bool enable) |
1260 | { | |
1261 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1262 | int ret; | |
1263 | ||
1264 | if (enable) { | |
1265 | ret = clk_prepare_enable(fep->clk_ahb); | |
1266 | if (ret) | |
1267 | return ret; | |
1268 | ret = clk_prepare_enable(fep->clk_ipg); | |
1269 | if (ret) | |
1270 | goto failed_clk_ipg; | |
1271 | if (fep->clk_enet_out) { | |
1272 | ret = clk_prepare_enable(fep->clk_enet_out); | |
1273 | if (ret) | |
1274 | goto failed_clk_enet_out; | |
1275 | } | |
1276 | if (fep->clk_ptp) { | |
1277 | ret = clk_prepare_enable(fep->clk_ptp); | |
1278 | if (ret) | |
1279 | goto failed_clk_ptp; | |
1280 | } | |
1281 | } else { | |
1282 | clk_disable_unprepare(fep->clk_ahb); | |
1283 | clk_disable_unprepare(fep->clk_ipg); | |
1284 | if (fep->clk_enet_out) | |
1285 | clk_disable_unprepare(fep->clk_enet_out); | |
1286 | if (fep->clk_ptp) | |
1287 | clk_disable_unprepare(fep->clk_ptp); | |
1288 | } | |
1289 | ||
1290 | return 0; | |
1291 | failed_clk_ptp: | |
1292 | if (fep->clk_enet_out) | |
1293 | clk_disable_unprepare(fep->clk_enet_out); | |
1294 | failed_clk_enet_out: | |
1295 | clk_disable_unprepare(fep->clk_ipg); | |
1296 | failed_clk_ipg: | |
1297 | clk_disable_unprepare(fep->clk_ahb); | |
1298 | ||
1299 | return ret; | |
1300 | } | |
1301 | ||
c556167f | 1302 | static int fec_enet_mii_probe(struct net_device *ndev) |
562d2f8c | 1303 | { |
c556167f | 1304 | struct fec_enet_private *fep = netdev_priv(ndev); |
230dec61 SG |
1305 | const struct platform_device_id *id_entry = |
1306 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 1307 | struct phy_device *phy_dev = NULL; |
6fcc040f GU |
1308 | char mdio_bus_id[MII_BUS_ID_SIZE]; |
1309 | char phy_name[MII_BUS_ID_SIZE + 3]; | |
1310 | int phy_id; | |
43af940c | 1311 | int dev_id = fep->dev_id; |
562d2f8c | 1312 | |
418bd0d4 BW |
1313 | fep->phy_dev = NULL; |
1314 | ||
6fcc040f GU |
1315 | /* check for attached phy */ |
1316 | for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { | |
1317 | if ((fep->mii_bus->phy_mask & (1 << phy_id))) | |
1318 | continue; | |
1319 | if (fep->mii_bus->phy_map[phy_id] == NULL) | |
1320 | continue; | |
1321 | if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) | |
1322 | continue; | |
b5680e0b SG |
1323 | if (dev_id--) |
1324 | continue; | |
6fcc040f GU |
1325 | strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); |
1326 | break; | |
e6b043d5 | 1327 | } |
1da177e4 | 1328 | |
6fcc040f | 1329 | if (phy_id >= PHY_MAX_ADDR) { |
31b7720c | 1330 | netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); |
ea51ade9 | 1331 | strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); |
6fcc040f GU |
1332 | phy_id = 0; |
1333 | } | |
1334 | ||
a7ed07d5 | 1335 | snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); |
f9a8f83b | 1336 | phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, |
230dec61 | 1337 | fep->phy_interface); |
6fcc040f | 1338 | if (IS_ERR(phy_dev)) { |
31b7720c | 1339 | netdev_err(ndev, "could not attach to PHY\n"); |
6fcc040f | 1340 | return PTR_ERR(phy_dev); |
e6b043d5 | 1341 | } |
1da177e4 | 1342 | |
e6b043d5 | 1343 | /* mask with MAC supported features */ |
baa70a5c | 1344 | if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) { |
230dec61 | 1345 | phy_dev->supported &= PHY_GBIT_FEATURES; |
d1391930 | 1346 | #if !defined(CONFIG_M5272) |
baa70a5c | 1347 | phy_dev->supported |= SUPPORTED_Pause; |
d1391930 | 1348 | #endif |
baa70a5c | 1349 | } |
230dec61 SG |
1350 | else |
1351 | phy_dev->supported &= PHY_BASIC_FEATURES; | |
1352 | ||
e6b043d5 | 1353 | phy_dev->advertising = phy_dev->supported; |
1da177e4 | 1354 | |
e6b043d5 BW |
1355 | fep->phy_dev = phy_dev; |
1356 | fep->link = 0; | |
1357 | fep->full_duplex = 0; | |
1da177e4 | 1358 | |
31b7720c JP |
1359 | netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", |
1360 | fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), | |
1361 | fep->phy_dev->irq); | |
418bd0d4 | 1362 | |
e6b043d5 | 1363 | return 0; |
1da177e4 LT |
1364 | } |
1365 | ||
e6b043d5 | 1366 | static int fec_enet_mii_init(struct platform_device *pdev) |
562d2f8c | 1367 | { |
b5680e0b | 1368 | static struct mii_bus *fec0_mii_bus; |
c556167f UKK |
1369 | struct net_device *ndev = platform_get_drvdata(pdev); |
1370 | struct fec_enet_private *fep = netdev_priv(ndev); | |
b5680e0b SG |
1371 | const struct platform_device_id *id_entry = |
1372 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 1373 | int err = -ENXIO, i; |
6b265293 | 1374 | |
b5680e0b SG |
1375 | /* |
1376 | * The dual fec interfaces are not equivalent with enet-mac. | |
1377 | * Here are the differences: | |
1378 | * | |
1379 | * - fec0 supports MII & RMII modes while fec1 only supports RMII | |
1380 | * - fec0 acts as the 1588 time master while fec1 is slave | |
1381 | * - external phys can only be configured by fec0 | |
1382 | * | |
1383 | * That is to say fec1 can not work independently. It only works | |
1384 | * when fec0 is working. The reason behind this design is that the | |
1385 | * second interface is added primarily for Switch mode. | |
1386 | * | |
1387 | * Because of the last point above, both phys are attached on fec0 | |
1388 | * mdio interface in board design, and need to be configured by | |
1389 | * fec0 mii_bus. | |
1390 | */ | |
43af940c | 1391 | if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { |
b5680e0b | 1392 | /* fec1 uses fec0 mii_bus */ |
e163cc97 LW |
1393 | if (mii_cnt && fec0_mii_bus) { |
1394 | fep->mii_bus = fec0_mii_bus; | |
1395 | mii_cnt++; | |
1396 | return 0; | |
1397 | } | |
1398 | return -ENOENT; | |
b5680e0b SG |
1399 | } |
1400 | ||
e6b043d5 | 1401 | fep->mii_timeout = 0; |
1da177e4 | 1402 | |
e6b043d5 BW |
1403 | /* |
1404 | * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) | |
230dec61 SG |
1405 | * |
1406 | * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while | |
1407 | * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 | |
1408 | * Reference Manual has an error on this, and gets fixed on i.MX6Q | |
1409 | * document. | |
e6b043d5 | 1410 | */ |
98a6eeb8 | 1411 | fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000); |
230dec61 SG |
1412 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) |
1413 | fep->phy_speed--; | |
1414 | fep->phy_speed <<= 1; | |
e6b043d5 | 1415 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1da177e4 | 1416 | |
e6b043d5 BW |
1417 | fep->mii_bus = mdiobus_alloc(); |
1418 | if (fep->mii_bus == NULL) { | |
1419 | err = -ENOMEM; | |
1420 | goto err_out; | |
1da177e4 LT |
1421 | } |
1422 | ||
e6b043d5 BW |
1423 | fep->mii_bus->name = "fec_enet_mii_bus"; |
1424 | fep->mii_bus->read = fec_enet_mdio_read; | |
1425 | fep->mii_bus->write = fec_enet_mdio_write; | |
391420f7 FF |
1426 | snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
1427 | pdev->name, fep->dev_id + 1); | |
e6b043d5 BW |
1428 | fep->mii_bus->priv = fep; |
1429 | fep->mii_bus->parent = &pdev->dev; | |
1430 | ||
1431 | fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
1432 | if (!fep->mii_bus->irq) { | |
1433 | err = -ENOMEM; | |
1434 | goto err_out_free_mdiobus; | |
1da177e4 LT |
1435 | } |
1436 | ||
e6b043d5 BW |
1437 | for (i = 0; i < PHY_MAX_ADDR; i++) |
1438 | fep->mii_bus->irq[i] = PHY_POLL; | |
1da177e4 | 1439 | |
e6b043d5 BW |
1440 | if (mdiobus_register(fep->mii_bus)) |
1441 | goto err_out_free_mdio_irq; | |
1da177e4 | 1442 | |
e163cc97 LW |
1443 | mii_cnt++; |
1444 | ||
b5680e0b SG |
1445 | /* save fec0 mii_bus */ |
1446 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) | |
1447 | fec0_mii_bus = fep->mii_bus; | |
1448 | ||
e6b043d5 | 1449 | return 0; |
1da177e4 | 1450 | |
e6b043d5 BW |
1451 | err_out_free_mdio_irq: |
1452 | kfree(fep->mii_bus->irq); | |
1453 | err_out_free_mdiobus: | |
1454 | mdiobus_free(fep->mii_bus); | |
1455 | err_out: | |
1456 | return err; | |
1da177e4 LT |
1457 | } |
1458 | ||
e6b043d5 | 1459 | static void fec_enet_mii_remove(struct fec_enet_private *fep) |
1da177e4 | 1460 | { |
e163cc97 LW |
1461 | if (--mii_cnt == 0) { |
1462 | mdiobus_unregister(fep->mii_bus); | |
1463 | kfree(fep->mii_bus->irq); | |
1464 | mdiobus_free(fep->mii_bus); | |
1465 | } | |
1da177e4 LT |
1466 | } |
1467 | ||
c556167f | 1468 | static int fec_enet_get_settings(struct net_device *ndev, |
e6b043d5 | 1469 | struct ethtool_cmd *cmd) |
1da177e4 | 1470 | { |
c556167f | 1471 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1472 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1473 | |
e6b043d5 BW |
1474 | if (!phydev) |
1475 | return -ENODEV; | |
1da177e4 | 1476 | |
e6b043d5 | 1477 | return phy_ethtool_gset(phydev, cmd); |
1da177e4 LT |
1478 | } |
1479 | ||
c556167f | 1480 | static int fec_enet_set_settings(struct net_device *ndev, |
e6b043d5 | 1481 | struct ethtool_cmd *cmd) |
1da177e4 | 1482 | { |
c556167f | 1483 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1484 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1485 | |
e6b043d5 BW |
1486 | if (!phydev) |
1487 | return -ENODEV; | |
1da177e4 | 1488 | |
e6b043d5 | 1489 | return phy_ethtool_sset(phydev, cmd); |
1da177e4 LT |
1490 | } |
1491 | ||
c556167f | 1492 | static void fec_enet_get_drvinfo(struct net_device *ndev, |
e6b043d5 | 1493 | struct ethtool_drvinfo *info) |
1da177e4 | 1494 | { |
c556167f | 1495 | struct fec_enet_private *fep = netdev_priv(ndev); |
6aa20a22 | 1496 | |
7826d43f JP |
1497 | strlcpy(info->driver, fep->pdev->dev.driver->name, |
1498 | sizeof(info->driver)); | |
1499 | strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); | |
1500 | strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); | |
1da177e4 LT |
1501 | } |
1502 | ||
5ebae489 FL |
1503 | static int fec_enet_get_ts_info(struct net_device *ndev, |
1504 | struct ethtool_ts_info *info) | |
1505 | { | |
1506 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1507 | ||
1508 | if (fep->bufdesc_ex) { | |
1509 | ||
1510 | info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | | |
1511 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
1512 | SOF_TIMESTAMPING_SOFTWARE | | |
1513 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1514 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1515 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
1516 | if (fep->ptp_clock) | |
1517 | info->phc_index = ptp_clock_index(fep->ptp_clock); | |
1518 | else | |
1519 | info->phc_index = -1; | |
1520 | ||
1521 | info->tx_types = (1 << HWTSTAMP_TX_OFF) | | |
1522 | (1 << HWTSTAMP_TX_ON); | |
1523 | ||
1524 | info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | | |
1525 | (1 << HWTSTAMP_FILTER_ALL); | |
1526 | return 0; | |
1527 | } else { | |
1528 | return ethtool_op_get_ts_info(ndev, info); | |
1529 | } | |
1530 | } | |
1531 | ||
d1391930 GR |
1532 | #if !defined(CONFIG_M5272) |
1533 | ||
baa70a5c FL |
1534 | static void fec_enet_get_pauseparam(struct net_device *ndev, |
1535 | struct ethtool_pauseparam *pause) | |
1536 | { | |
1537 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1538 | ||
1539 | pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; | |
1540 | pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; | |
1541 | pause->rx_pause = pause->tx_pause; | |
1542 | } | |
1543 | ||
1544 | static int fec_enet_set_pauseparam(struct net_device *ndev, | |
1545 | struct ethtool_pauseparam *pause) | |
1546 | { | |
1547 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1548 | ||
1549 | if (pause->tx_pause != pause->rx_pause) { | |
1550 | netdev_info(ndev, | |
1551 | "hardware only support enable/disable both tx and rx"); | |
1552 | return -EINVAL; | |
1553 | } | |
1554 | ||
1555 | fep->pause_flag = 0; | |
1556 | ||
1557 | /* tx pause must be same as rx pause */ | |
1558 | fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; | |
1559 | fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; | |
1560 | ||
1561 | if (pause->rx_pause || pause->autoneg) { | |
1562 | fep->phy_dev->supported |= ADVERTISED_Pause; | |
1563 | fep->phy_dev->advertising |= ADVERTISED_Pause; | |
1564 | } else { | |
1565 | fep->phy_dev->supported &= ~ADVERTISED_Pause; | |
1566 | fep->phy_dev->advertising &= ~ADVERTISED_Pause; | |
1567 | } | |
1568 | ||
1569 | if (pause->autoneg) { | |
1570 | if (netif_running(ndev)) | |
1571 | fec_stop(ndev); | |
1572 | phy_start_aneg(fep->phy_dev); | |
1573 | } | |
1574 | if (netif_running(ndev)) | |
1575 | fec_restart(ndev, 0); | |
1576 | ||
1577 | return 0; | |
1578 | } | |
1579 | ||
38ae92dc CH |
1580 | static const struct fec_stat { |
1581 | char name[ETH_GSTRING_LEN]; | |
1582 | u16 offset; | |
1583 | } fec_stats[] = { | |
1584 | /* RMON TX */ | |
1585 | { "tx_dropped", RMON_T_DROP }, | |
1586 | { "tx_packets", RMON_T_PACKETS }, | |
1587 | { "tx_broadcast", RMON_T_BC_PKT }, | |
1588 | { "tx_multicast", RMON_T_MC_PKT }, | |
1589 | { "tx_crc_errors", RMON_T_CRC_ALIGN }, | |
1590 | { "tx_undersize", RMON_T_UNDERSIZE }, | |
1591 | { "tx_oversize", RMON_T_OVERSIZE }, | |
1592 | { "tx_fragment", RMON_T_FRAG }, | |
1593 | { "tx_jabber", RMON_T_JAB }, | |
1594 | { "tx_collision", RMON_T_COL }, | |
1595 | { "tx_64byte", RMON_T_P64 }, | |
1596 | { "tx_65to127byte", RMON_T_P65TO127 }, | |
1597 | { "tx_128to255byte", RMON_T_P128TO255 }, | |
1598 | { "tx_256to511byte", RMON_T_P256TO511 }, | |
1599 | { "tx_512to1023byte", RMON_T_P512TO1023 }, | |
1600 | { "tx_1024to2047byte", RMON_T_P1024TO2047 }, | |
1601 | { "tx_GTE2048byte", RMON_T_P_GTE2048 }, | |
1602 | { "tx_octets", RMON_T_OCTETS }, | |
1603 | ||
1604 | /* IEEE TX */ | |
1605 | { "IEEE_tx_drop", IEEE_T_DROP }, | |
1606 | { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, | |
1607 | { "IEEE_tx_1col", IEEE_T_1COL }, | |
1608 | { "IEEE_tx_mcol", IEEE_T_MCOL }, | |
1609 | { "IEEE_tx_def", IEEE_T_DEF }, | |
1610 | { "IEEE_tx_lcol", IEEE_T_LCOL }, | |
1611 | { "IEEE_tx_excol", IEEE_T_EXCOL }, | |
1612 | { "IEEE_tx_macerr", IEEE_T_MACERR }, | |
1613 | { "IEEE_tx_cserr", IEEE_T_CSERR }, | |
1614 | { "IEEE_tx_sqe", IEEE_T_SQE }, | |
1615 | { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, | |
1616 | { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, | |
1617 | ||
1618 | /* RMON RX */ | |
1619 | { "rx_packets", RMON_R_PACKETS }, | |
1620 | { "rx_broadcast", RMON_R_BC_PKT }, | |
1621 | { "rx_multicast", RMON_R_MC_PKT }, | |
1622 | { "rx_crc_errors", RMON_R_CRC_ALIGN }, | |
1623 | { "rx_undersize", RMON_R_UNDERSIZE }, | |
1624 | { "rx_oversize", RMON_R_OVERSIZE }, | |
1625 | { "rx_fragment", RMON_R_FRAG }, | |
1626 | { "rx_jabber", RMON_R_JAB }, | |
1627 | { "rx_64byte", RMON_R_P64 }, | |
1628 | { "rx_65to127byte", RMON_R_P65TO127 }, | |
1629 | { "rx_128to255byte", RMON_R_P128TO255 }, | |
1630 | { "rx_256to511byte", RMON_R_P256TO511 }, | |
1631 | { "rx_512to1023byte", RMON_R_P512TO1023 }, | |
1632 | { "rx_1024to2047byte", RMON_R_P1024TO2047 }, | |
1633 | { "rx_GTE2048byte", RMON_R_P_GTE2048 }, | |
1634 | { "rx_octets", RMON_R_OCTETS }, | |
1635 | ||
1636 | /* IEEE RX */ | |
1637 | { "IEEE_rx_drop", IEEE_R_DROP }, | |
1638 | { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, | |
1639 | { "IEEE_rx_crc", IEEE_R_CRC }, | |
1640 | { "IEEE_rx_align", IEEE_R_ALIGN }, | |
1641 | { "IEEE_rx_macerr", IEEE_R_MACERR }, | |
1642 | { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, | |
1643 | { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, | |
1644 | }; | |
1645 | ||
1646 | static void fec_enet_get_ethtool_stats(struct net_device *dev, | |
1647 | struct ethtool_stats *stats, u64 *data) | |
1648 | { | |
1649 | struct fec_enet_private *fep = netdev_priv(dev); | |
1650 | int i; | |
1651 | ||
1652 | for (i = 0; i < ARRAY_SIZE(fec_stats); i++) | |
1653 | data[i] = readl(fep->hwp + fec_stats[i].offset); | |
1654 | } | |
1655 | ||
1656 | static void fec_enet_get_strings(struct net_device *netdev, | |
1657 | u32 stringset, u8 *data) | |
1658 | { | |
1659 | int i; | |
1660 | switch (stringset) { | |
1661 | case ETH_SS_STATS: | |
1662 | for (i = 0; i < ARRAY_SIZE(fec_stats); i++) | |
1663 | memcpy(data + i * ETH_GSTRING_LEN, | |
1664 | fec_stats[i].name, ETH_GSTRING_LEN); | |
1665 | break; | |
1666 | } | |
1667 | } | |
1668 | ||
1669 | static int fec_enet_get_sset_count(struct net_device *dev, int sset) | |
1670 | { | |
1671 | switch (sset) { | |
1672 | case ETH_SS_STATS: | |
1673 | return ARRAY_SIZE(fec_stats); | |
1674 | default: | |
1675 | return -EOPNOTSUPP; | |
1676 | } | |
1677 | } | |
d1391930 | 1678 | #endif /* !defined(CONFIG_M5272) */ |
38ae92dc | 1679 | |
32bc9b46 CH |
1680 | static int fec_enet_nway_reset(struct net_device *dev) |
1681 | { | |
1682 | struct fec_enet_private *fep = netdev_priv(dev); | |
1683 | struct phy_device *phydev = fep->phy_dev; | |
1684 | ||
1685 | if (!phydev) | |
1686 | return -ENODEV; | |
1687 | ||
1688 | return genphy_restart_aneg(phydev); | |
1689 | } | |
1690 | ||
9b07be4b | 1691 | static const struct ethtool_ops fec_enet_ethtool_ops = { |
d1391930 | 1692 | #if !defined(CONFIG_M5272) |
baa70a5c FL |
1693 | .get_pauseparam = fec_enet_get_pauseparam, |
1694 | .set_pauseparam = fec_enet_set_pauseparam, | |
d1391930 | 1695 | #endif |
e6b043d5 BW |
1696 | .get_settings = fec_enet_get_settings, |
1697 | .set_settings = fec_enet_set_settings, | |
1698 | .get_drvinfo = fec_enet_get_drvinfo, | |
1699 | .get_link = ethtool_op_get_link, | |
5ebae489 | 1700 | .get_ts_info = fec_enet_get_ts_info, |
32bc9b46 | 1701 | .nway_reset = fec_enet_nway_reset, |
38ae92dc CH |
1702 | #ifndef CONFIG_M5272 |
1703 | .get_ethtool_stats = fec_enet_get_ethtool_stats, | |
1704 | .get_strings = fec_enet_get_strings, | |
1705 | .get_sset_count = fec_enet_get_sset_count, | |
1706 | #endif | |
e6b043d5 | 1707 | }; |
1da177e4 | 1708 | |
c556167f | 1709 | static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) |
1da177e4 | 1710 | { |
c556167f | 1711 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1712 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1713 | |
c556167f | 1714 | if (!netif_running(ndev)) |
e6b043d5 | 1715 | return -EINVAL; |
1da177e4 | 1716 | |
e6b043d5 BW |
1717 | if (!phydev) |
1718 | return -ENODEV; | |
1719 | ||
1d5244d0 BH |
1720 | if (fep->bufdesc_ex) { |
1721 | if (cmd == SIOCSHWTSTAMP) | |
1722 | return fec_ptp_set(ndev, rq); | |
1723 | if (cmd == SIOCGHWTSTAMP) | |
1724 | return fec_ptp_get(ndev, rq); | |
1725 | } | |
ff43da86 | 1726 | |
28b04113 | 1727 | return phy_mii_ioctl(phydev, rq, cmd); |
1da177e4 LT |
1728 | } |
1729 | ||
c556167f | 1730 | static void fec_enet_free_buffers(struct net_device *ndev) |
f0b3fbea | 1731 | { |
c556167f | 1732 | struct fec_enet_private *fep = netdev_priv(ndev); |
da2191e3 | 1733 | unsigned int i; |
f0b3fbea SH |
1734 | struct sk_buff *skb; |
1735 | struct bufdesc *bdp; | |
1736 | ||
1737 | bdp = fep->rx_bd_base; | |
36e24e2e | 1738 | for (i = 0; i < fep->rx_ring_size; i++) { |
f0b3fbea SH |
1739 | skb = fep->rx_skbuff[i]; |
1740 | ||
1741 | if (bdp->cbd_bufaddr) | |
d1ab1f54 | 1742 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
f0b3fbea SH |
1743 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1744 | if (skb) | |
1745 | dev_kfree_skb(skb); | |
36e24e2e | 1746 | bdp = fec_enet_get_nextdesc(bdp, fep); |
f0b3fbea SH |
1747 | } |
1748 | ||
1749 | bdp = fep->tx_bd_base; | |
36e24e2e | 1750 | for (i = 0; i < fep->tx_ring_size; i++) |
f0b3fbea SH |
1751 | kfree(fep->tx_bounce[i]); |
1752 | } | |
1753 | ||
c556167f | 1754 | static int fec_enet_alloc_buffers(struct net_device *ndev) |
f0b3fbea | 1755 | { |
c556167f | 1756 | struct fec_enet_private *fep = netdev_priv(ndev); |
da2191e3 | 1757 | unsigned int i; |
f0b3fbea SH |
1758 | struct sk_buff *skb; |
1759 | struct bufdesc *bdp; | |
1760 | ||
1761 | bdp = fep->rx_bd_base; | |
36e24e2e | 1762 | for (i = 0; i < fep->rx_ring_size; i++) { |
b72061a3 | 1763 | skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); |
f0b3fbea | 1764 | if (!skb) { |
c556167f | 1765 | fec_enet_free_buffers(ndev); |
f0b3fbea SH |
1766 | return -ENOMEM; |
1767 | } | |
1768 | fep->rx_skbuff[i] = skb; | |
1769 | ||
d1ab1f54 | 1770 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, |
f0b3fbea | 1771 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
d842a31f DFB |
1772 | if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) { |
1773 | fec_enet_free_buffers(ndev); | |
1774 | if (net_ratelimit()) | |
1775 | netdev_err(ndev, "Rx DMA memory map failed\n"); | |
1776 | return -ENOMEM; | |
1777 | } | |
f0b3fbea | 1778 | bdp->cbd_sc = BD_ENET_RX_EMPTY; |
ff43da86 FL |
1779 | |
1780 | if (fep->bufdesc_ex) { | |
1781 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
1782 | ebdp->cbd_esc = BD_ENET_RX_INT; | |
1783 | } | |
1784 | ||
36e24e2e | 1785 | bdp = fec_enet_get_nextdesc(bdp, fep); |
f0b3fbea SH |
1786 | } |
1787 | ||
1788 | /* Set the last buffer to wrap. */ | |
36e24e2e | 1789 | bdp = fec_enet_get_prevdesc(bdp, fep); |
f0b3fbea SH |
1790 | bdp->cbd_sc |= BD_SC_WRAP; |
1791 | ||
1792 | bdp = fep->tx_bd_base; | |
36e24e2e | 1793 | for (i = 0; i < fep->tx_ring_size; i++) { |
f0b3fbea SH |
1794 | fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); |
1795 | ||
1796 | bdp->cbd_sc = 0; | |
1797 | bdp->cbd_bufaddr = 0; | |
6605b730 | 1798 | |
ff43da86 FL |
1799 | if (fep->bufdesc_ex) { |
1800 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
96d2222b | 1801 | ebdp->cbd_esc = BD_ENET_TX_INT; |
ff43da86 FL |
1802 | } |
1803 | ||
36e24e2e | 1804 | bdp = fec_enet_get_nextdesc(bdp, fep); |
f0b3fbea SH |
1805 | } |
1806 | ||
1807 | /* Set the last buffer to wrap. */ | |
36e24e2e | 1808 | bdp = fec_enet_get_prevdesc(bdp, fep); |
f0b3fbea SH |
1809 | bdp->cbd_sc |= BD_SC_WRAP; |
1810 | ||
1811 | return 0; | |
1812 | } | |
1813 | ||
1da177e4 | 1814 | static int |
c556167f | 1815 | fec_enet_open(struct net_device *ndev) |
1da177e4 | 1816 | { |
c556167f | 1817 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1818 | int ret; |
1da177e4 | 1819 | |
5bbde4d2 | 1820 | pinctrl_pm_select_default_state(&fep->pdev->dev); |
e8fcfcd5 NA |
1821 | ret = fec_enet_clk_enable(ndev, true); |
1822 | if (ret) | |
1823 | return ret; | |
1824 | ||
1da177e4 LT |
1825 | /* I should reset the ring buffers here, but I don't yet know |
1826 | * a simple way to do that. | |
1827 | */ | |
1da177e4 | 1828 | |
c556167f | 1829 | ret = fec_enet_alloc_buffers(ndev); |
f0b3fbea SH |
1830 | if (ret) |
1831 | return ret; | |
1832 | ||
418bd0d4 | 1833 | /* Probe and connect to PHY when open the interface */ |
c556167f | 1834 | ret = fec_enet_mii_probe(ndev); |
418bd0d4 | 1835 | if (ret) { |
c556167f | 1836 | fec_enet_free_buffers(ndev); |
418bd0d4 BW |
1837 | return ret; |
1838 | } | |
ce5eaf02 RK |
1839 | |
1840 | napi_enable(&fep->napi); | |
e6b043d5 | 1841 | phy_start(fep->phy_dev); |
c556167f | 1842 | netif_start_queue(ndev); |
1da177e4 | 1843 | fep->opened = 1; |
22f6b860 | 1844 | return 0; |
1da177e4 LT |
1845 | } |
1846 | ||
1847 | static int | |
c556167f | 1848 | fec_enet_close(struct net_device *ndev) |
1da177e4 | 1849 | { |
c556167f | 1850 | struct fec_enet_private *fep = netdev_priv(ndev); |
1da177e4 | 1851 | |
22f6b860 | 1852 | /* Don't know what to do yet. */ |
3f104c38 | 1853 | napi_disable(&fep->napi); |
1da177e4 | 1854 | fep->opened = 0; |
c556167f UKK |
1855 | netif_stop_queue(ndev); |
1856 | fec_stop(ndev); | |
1da177e4 | 1857 | |
e497ba82 UKK |
1858 | if (fep->phy_dev) { |
1859 | phy_stop(fep->phy_dev); | |
418bd0d4 | 1860 | phy_disconnect(fep->phy_dev); |
e497ba82 | 1861 | } |
418bd0d4 | 1862 | |
e8fcfcd5 | 1863 | fec_enet_clk_enable(ndev, false); |
5bbde4d2 | 1864 | pinctrl_pm_select_sleep_state(&fep->pdev->dev); |
db8880bc | 1865 | fec_enet_free_buffers(ndev); |
f0b3fbea | 1866 | |
1da177e4 LT |
1867 | return 0; |
1868 | } | |
1869 | ||
1da177e4 LT |
1870 | /* Set or clear the multicast filter for this adaptor. |
1871 | * Skeleton taken from sunlance driver. | |
1872 | * The CPM Ethernet implementation allows Multicast as well as individual | |
1873 | * MAC address filtering. Some of the drivers check to make sure it is | |
1874 | * a group multicast address, and discard those that are not. I guess I | |
1875 | * will do the same for now, but just remove the test if you want | |
1876 | * individual filtering as well (do the upper net layers want or support | |
1877 | * this kind of feature?). | |
1878 | */ | |
1879 | ||
1880 | #define HASH_BITS 6 /* #bits in hash */ | |
1881 | #define CRC32_POLY 0xEDB88320 | |
1882 | ||
c556167f | 1883 | static void set_multicast_list(struct net_device *ndev) |
1da177e4 | 1884 | { |
c556167f | 1885 | struct fec_enet_private *fep = netdev_priv(ndev); |
22bedad3 | 1886 | struct netdev_hw_addr *ha; |
48e2f183 | 1887 | unsigned int i, bit, data, crc, tmp; |
1da177e4 LT |
1888 | unsigned char hash; |
1889 | ||
c556167f | 1890 | if (ndev->flags & IFF_PROMISC) { |
f44d6305 SH |
1891 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1892 | tmp |= 0x8; | |
1893 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
4e831836 SH |
1894 | return; |
1895 | } | |
1da177e4 | 1896 | |
4e831836 SH |
1897 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1898 | tmp &= ~0x8; | |
1899 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
1900 | ||
c556167f | 1901 | if (ndev->flags & IFF_ALLMULTI) { |
4e831836 SH |
1902 | /* Catch all multicast addresses, so set the |
1903 | * filter to all 1's | |
1904 | */ | |
1905 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1906 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1907 | ||
1908 | return; | |
1909 | } | |
1910 | ||
1911 | /* Clear filter and add the addresses in hash register | |
1912 | */ | |
1913 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1914 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1915 | ||
c556167f | 1916 | netdev_for_each_mc_addr(ha, ndev) { |
4e831836 SH |
1917 | /* calculate crc32 value of mac address */ |
1918 | crc = 0xffffffff; | |
1919 | ||
c556167f | 1920 | for (i = 0; i < ndev->addr_len; i++) { |
22bedad3 | 1921 | data = ha->addr[i]; |
4e831836 SH |
1922 | for (bit = 0; bit < 8; bit++, data >>= 1) { |
1923 | crc = (crc >> 1) ^ | |
1924 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1da177e4 LT |
1925 | } |
1926 | } | |
4e831836 SH |
1927 | |
1928 | /* only upper 6 bits (HASH_BITS) are used | |
1929 | * which point to specific bit in he hash registers | |
1930 | */ | |
1931 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
1932 | ||
1933 | if (hash > 31) { | |
1934 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1935 | tmp |= 1 << (hash - 32); | |
1936 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1937 | } else { | |
1938 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1939 | tmp |= 1 << hash; | |
1940 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1941 | } | |
1da177e4 LT |
1942 | } |
1943 | } | |
1944 | ||
22f6b860 | 1945 | /* Set a MAC change in hardware. */ |
009fda83 | 1946 | static int |
c556167f | 1947 | fec_set_mac_address(struct net_device *ndev, void *p) |
1da177e4 | 1948 | { |
c556167f | 1949 | struct fec_enet_private *fep = netdev_priv(ndev); |
009fda83 SH |
1950 | struct sockaddr *addr = p; |
1951 | ||
44934fac LS |
1952 | if (addr) { |
1953 | if (!is_valid_ether_addr(addr->sa_data)) | |
1954 | return -EADDRNOTAVAIL; | |
1955 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); | |
1956 | } | |
1da177e4 | 1957 | |
c556167f UKK |
1958 | writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | |
1959 | (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), | |
f44d6305 | 1960 | fep->hwp + FEC_ADDR_LOW); |
c556167f | 1961 | writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), |
7cff0943 | 1962 | fep->hwp + FEC_ADDR_HIGH); |
009fda83 | 1963 | return 0; |
1da177e4 LT |
1964 | } |
1965 | ||
7f5c6add | 1966 | #ifdef CONFIG_NET_POLL_CONTROLLER |
49ce9c2c BH |
1967 | /** |
1968 | * fec_poll_controller - FEC Poll controller function | |
7f5c6add XJ |
1969 | * @dev: The FEC network adapter |
1970 | * | |
1971 | * Polled functionality used by netconsole and others in non interrupt mode | |
1972 | * | |
1973 | */ | |
47a5247f | 1974 | static void fec_poll_controller(struct net_device *dev) |
7f5c6add XJ |
1975 | { |
1976 | int i; | |
1977 | struct fec_enet_private *fep = netdev_priv(dev); | |
1978 | ||
1979 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
1980 | if (fep->irq[i] > 0) { | |
1981 | disable_irq(fep->irq[i]); | |
1982 | fec_enet_interrupt(fep->irq[i], dev); | |
1983 | enable_irq(fep->irq[i]); | |
1984 | } | |
1985 | } | |
1986 | } | |
1987 | #endif | |
1988 | ||
4c09eed9 JB |
1989 | static int fec_set_features(struct net_device *netdev, |
1990 | netdev_features_t features) | |
1991 | { | |
1992 | struct fec_enet_private *fep = netdev_priv(netdev); | |
1993 | netdev_features_t changed = features ^ netdev->features; | |
1994 | ||
1995 | netdev->features = features; | |
1996 | ||
1997 | /* Receive checksum has been changed */ | |
1998 | if (changed & NETIF_F_RXCSUM) { | |
1999 | if (features & NETIF_F_RXCSUM) | |
2000 | fep->csum_flags |= FLAG_RX_CSUM_ENABLED; | |
2001 | else | |
2002 | fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; | |
2003 | ||
2004 | if (netif_running(netdev)) { | |
2005 | fec_stop(netdev); | |
2006 | fec_restart(netdev, fep->phy_dev->duplex); | |
2007 | netif_wake_queue(netdev); | |
2008 | } else { | |
2009 | fec_restart(netdev, fep->phy_dev->duplex); | |
2010 | } | |
2011 | } | |
2012 | ||
2013 | return 0; | |
2014 | } | |
2015 | ||
009fda83 SH |
2016 | static const struct net_device_ops fec_netdev_ops = { |
2017 | .ndo_open = fec_enet_open, | |
2018 | .ndo_stop = fec_enet_close, | |
2019 | .ndo_start_xmit = fec_enet_start_xmit, | |
afc4b13d | 2020 | .ndo_set_rx_mode = set_multicast_list, |
635ecaa7 | 2021 | .ndo_change_mtu = eth_change_mtu, |
009fda83 SH |
2022 | .ndo_validate_addr = eth_validate_addr, |
2023 | .ndo_tx_timeout = fec_timeout, | |
2024 | .ndo_set_mac_address = fec_set_mac_address, | |
db8880bc | 2025 | .ndo_do_ioctl = fec_enet_ioctl, |
7f5c6add XJ |
2026 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2027 | .ndo_poll_controller = fec_poll_controller, | |
2028 | #endif | |
4c09eed9 | 2029 | .ndo_set_features = fec_set_features, |
009fda83 SH |
2030 | }; |
2031 | ||
1da177e4 LT |
2032 | /* |
2033 | * XXX: We need to clean up on failure exits here. | |
ead73183 | 2034 | * |
1da177e4 | 2035 | */ |
c556167f | 2036 | static int fec_enet_init(struct net_device *ndev) |
1da177e4 | 2037 | { |
c556167f | 2038 | struct fec_enet_private *fep = netdev_priv(ndev); |
48496255 SG |
2039 | const struct platform_device_id *id_entry = |
2040 | platform_get_device_id(fep->pdev); | |
f0b3fbea | 2041 | struct bufdesc *cbd_base; |
1da177e4 | 2042 | |
8d4dd5cf SH |
2043 | /* Allocate memory for buffer descriptors. */ |
2044 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, | |
d0320f75 JP |
2045 | GFP_KERNEL); |
2046 | if (!cbd_base) | |
562d2f8c | 2047 | return -ENOMEM; |
562d2f8c | 2048 | |
14109a59 | 2049 | memset(cbd_base, 0, PAGE_SIZE); |
3b2b74ca | 2050 | |
c556167f | 2051 | fep->netdev = ndev; |
1da177e4 | 2052 | |
49da97dc | 2053 | /* Get the Ethernet address */ |
c556167f | 2054 | fec_get_mac(ndev); |
44934fac LS |
2055 | /* make sure MAC we just acquired is programmed into the hw */ |
2056 | fec_set_mac_address(ndev, NULL); | |
1da177e4 | 2057 | |
36e24e2e DFB |
2058 | /* init the tx & rx ring size */ |
2059 | fep->tx_ring_size = TX_RING_SIZE; | |
2060 | fep->rx_ring_size = RX_RING_SIZE; | |
2061 | ||
8d4dd5cf | 2062 | /* Set receive and transmit descriptor base. */ |
1da177e4 | 2063 | fep->rx_bd_base = cbd_base; |
ff43da86 FL |
2064 | if (fep->bufdesc_ex) |
2065 | fep->tx_bd_base = (struct bufdesc *) | |
36e24e2e | 2066 | (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size); |
ff43da86 | 2067 | else |
36e24e2e | 2068 | fep->tx_bd_base = cbd_base + fep->rx_ring_size; |
1da177e4 | 2069 | |
22f6b860 | 2070 | /* The FEC Ethernet specific entries in the device structure */ |
c556167f UKK |
2071 | ndev->watchdog_timeo = TX_TIMEOUT; |
2072 | ndev->netdev_ops = &fec_netdev_ops; | |
2073 | ndev->ethtool_ops = &fec_enet_ethtool_ops; | |
633e7533 | 2074 | |
dc975382 | 2075 | writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); |
322555f5 | 2076 | netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); |
dc975382 | 2077 | |
cdffcf1b JB |
2078 | if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) { |
2079 | /* enable hw VLAN support */ | |
2080 | ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; | |
2081 | ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; | |
2082 | } | |
2083 | ||
48496255 SG |
2084 | if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) { |
2085 | /* enable hw accelerator */ | |
2086 | ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
2087 | | NETIF_F_RXCSUM); | |
2088 | ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
2089 | | NETIF_F_RXCSUM); | |
2090 | fep->csum_flags |= FLAG_RX_CSUM_ENABLED; | |
2091 | } | |
4c09eed9 | 2092 | |
c556167f | 2093 | fec_restart(ndev, 0); |
1da177e4 | 2094 | |
1da177e4 LT |
2095 | return 0; |
2096 | } | |
2097 | ||
ca2cc333 | 2098 | #ifdef CONFIG_OF |
33897cc8 | 2099 | static void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
2100 | { |
2101 | int err, phy_reset; | |
a3caad0a | 2102 | int msec = 1; |
ca2cc333 SG |
2103 | struct device_node *np = pdev->dev.of_node; |
2104 | ||
2105 | if (!np) | |
a9b2c8ef | 2106 | return; |
ca2cc333 | 2107 | |
a3caad0a SG |
2108 | of_property_read_u32(np, "phy-reset-duration", &msec); |
2109 | /* A sane reset duration should not be longer than 1s */ | |
2110 | if (msec > 1000) | |
2111 | msec = 1; | |
2112 | ||
ca2cc333 | 2113 | phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); |
07dcf8e9 FE |
2114 | if (!gpio_is_valid(phy_reset)) |
2115 | return; | |
2116 | ||
119fc007 SG |
2117 | err = devm_gpio_request_one(&pdev->dev, phy_reset, |
2118 | GPIOF_OUT_INIT_LOW, "phy-reset"); | |
ca2cc333 | 2119 | if (err) { |
07dcf8e9 | 2120 | dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); |
a9b2c8ef | 2121 | return; |
ca2cc333 | 2122 | } |
a3caad0a | 2123 | msleep(msec); |
ca2cc333 | 2124 | gpio_set_value(phy_reset, 1); |
ca2cc333 SG |
2125 | } |
2126 | #else /* CONFIG_OF */ | |
0c7768a0 | 2127 | static void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
2128 | { |
2129 | /* | |
2130 | * In case of platform probe, the reset has been done | |
2131 | * by machine code. | |
2132 | */ | |
ca2cc333 SG |
2133 | } |
2134 | #endif /* CONFIG_OF */ | |
2135 | ||
33897cc8 | 2136 | static int |
ead73183 SH |
2137 | fec_probe(struct platform_device *pdev) |
2138 | { | |
2139 | struct fec_enet_private *fep; | |
5eb32bd0 | 2140 | struct fec_platform_data *pdata; |
ead73183 SH |
2141 | struct net_device *ndev; |
2142 | int i, irq, ret = 0; | |
2143 | struct resource *r; | |
ca2cc333 | 2144 | const struct of_device_id *of_id; |
43af940c | 2145 | static int dev_id; |
ca2cc333 SG |
2146 | |
2147 | of_id = of_match_device(fec_dt_ids, &pdev->dev); | |
2148 | if (of_id) | |
2149 | pdev->id_entry = of_id->data; | |
ead73183 | 2150 | |
ead73183 SH |
2151 | /* Init network device */ |
2152 | ndev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
83e519b6 FE |
2153 | if (!ndev) |
2154 | return -ENOMEM; | |
ead73183 SH |
2155 | |
2156 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
2157 | ||
2158 | /* setup board info structure */ | |
2159 | fep = netdev_priv(ndev); | |
ead73183 | 2160 | |
d1391930 | 2161 | #if !defined(CONFIG_M5272) |
baa70a5c FL |
2162 | /* default enable pause frame auto negotiation */ |
2163 | if (pdev->id_entry && | |
2164 | (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT)) | |
2165 | fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; | |
d1391930 | 2166 | #endif |
baa70a5c | 2167 | |
5bbde4d2 NA |
2168 | /* Select default pin state */ |
2169 | pinctrl_pm_select_default_state(&pdev->dev); | |
2170 | ||
399db75b | 2171 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
941e173a TB |
2172 | fep->hwp = devm_ioremap_resource(&pdev->dev, r); |
2173 | if (IS_ERR(fep->hwp)) { | |
2174 | ret = PTR_ERR(fep->hwp); | |
2175 | goto failed_ioremap; | |
2176 | } | |
2177 | ||
e6b043d5 | 2178 | fep->pdev = pdev; |
43af940c | 2179 | fep->dev_id = dev_id++; |
ead73183 | 2180 | |
ff43da86 FL |
2181 | fep->bufdesc_ex = 0; |
2182 | ||
ead73183 SH |
2183 | platform_set_drvdata(pdev, ndev); |
2184 | ||
6c5f7808 | 2185 | ret = of_get_phy_mode(pdev->dev.of_node); |
ca2cc333 | 2186 | if (ret < 0) { |
94660ba0 | 2187 | pdata = dev_get_platdata(&pdev->dev); |
ca2cc333 SG |
2188 | if (pdata) |
2189 | fep->phy_interface = pdata->phy; | |
2190 | else | |
2191 | fep->phy_interface = PHY_INTERFACE_MODE_MII; | |
2192 | } else { | |
2193 | fep->phy_interface = ret; | |
2194 | } | |
2195 | ||
f4d40de3 SH |
2196 | fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
2197 | if (IS_ERR(fep->clk_ipg)) { | |
2198 | ret = PTR_ERR(fep->clk_ipg); | |
ead73183 SH |
2199 | goto failed_clk; |
2200 | } | |
f4d40de3 SH |
2201 | |
2202 | fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
2203 | if (IS_ERR(fep->clk_ahb)) { | |
2204 | ret = PTR_ERR(fep->clk_ahb); | |
2205 | goto failed_clk; | |
2206 | } | |
2207 | ||
daa7d392 WS |
2208 | /* enet_out is optional, depends on board */ |
2209 | fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); | |
2210 | if (IS_ERR(fep->clk_enet_out)) | |
2211 | fep->clk_enet_out = NULL; | |
2212 | ||
6605b730 | 2213 | fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); |
e2f8d555 FE |
2214 | fep->bufdesc_ex = |
2215 | pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX; | |
6605b730 | 2216 | if (IS_ERR(fep->clk_ptp)) { |
c29dc2d7 | 2217 | fep->clk_ptp = NULL; |
ff43da86 | 2218 | fep->bufdesc_ex = 0; |
6605b730 | 2219 | } |
6605b730 | 2220 | |
e8fcfcd5 | 2221 | ret = fec_enet_clk_enable(ndev, true); |
13a097bd FE |
2222 | if (ret) |
2223 | goto failed_clk; | |
2224 | ||
f4e9f3d2 FE |
2225 | fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); |
2226 | if (!IS_ERR(fep->reg_phy)) { | |
2227 | ret = regulator_enable(fep->reg_phy); | |
5fa9c0fe SG |
2228 | if (ret) { |
2229 | dev_err(&pdev->dev, | |
2230 | "Failed to enable phy regulator: %d\n", ret); | |
2231 | goto failed_regulator; | |
2232 | } | |
f6a4d607 FE |
2233 | } else { |
2234 | fep->reg_phy = NULL; | |
5fa9c0fe SG |
2235 | } |
2236 | ||
2ca9b2aa SG |
2237 | fec_reset_phy(pdev); |
2238 | ||
e2f8d555 | 2239 | if (fep->bufdesc_ex) |
ca162a82 | 2240 | fec_ptp_init(pdev); |
e2f8d555 FE |
2241 | |
2242 | ret = fec_enet_init(ndev); | |
2243 | if (ret) | |
2244 | goto failed_init; | |
2245 | ||
2246 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
2247 | irq = platform_get_irq(pdev, i); | |
2248 | if (irq < 0) { | |
2249 | if (i) | |
2250 | break; | |
2251 | ret = irq; | |
2252 | goto failed_irq; | |
2253 | } | |
0d9b2ab1 | 2254 | ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, |
44a272dd | 2255 | 0, pdev->name, ndev); |
0d9b2ab1 | 2256 | if (ret) |
e2f8d555 | 2257 | goto failed_irq; |
e2f8d555 FE |
2258 | } |
2259 | ||
e6b043d5 BW |
2260 | ret = fec_enet_mii_init(pdev); |
2261 | if (ret) | |
2262 | goto failed_mii_init; | |
2263 | ||
03c698c9 OS |
2264 | /* Carrier starts down, phylib will bring it up */ |
2265 | netif_carrier_off(ndev); | |
e8fcfcd5 | 2266 | fec_enet_clk_enable(ndev, false); |
5bbde4d2 | 2267 | pinctrl_pm_select_sleep_state(&pdev->dev); |
03c698c9 | 2268 | |
ead73183 SH |
2269 | ret = register_netdev(ndev); |
2270 | if (ret) | |
2271 | goto failed_register; | |
2272 | ||
eb1d0640 FE |
2273 | if (fep->bufdesc_ex && fep->ptp_clock) |
2274 | netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); | |
2275 | ||
54309fa6 | 2276 | INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work); |
ead73183 SH |
2277 | return 0; |
2278 | ||
2279 | failed_register: | |
e6b043d5 BW |
2280 | fec_enet_mii_remove(fep); |
2281 | failed_mii_init: | |
7a2bbd8d | 2282 | failed_irq: |
7a2bbd8d | 2283 | failed_init: |
f6a4d607 FE |
2284 | if (fep->reg_phy) |
2285 | regulator_disable(fep->reg_phy); | |
5fa9c0fe | 2286 | failed_regulator: |
e8fcfcd5 | 2287 | fec_enet_clk_enable(ndev, false); |
ead73183 | 2288 | failed_clk: |
ead73183 SH |
2289 | failed_ioremap: |
2290 | free_netdev(ndev); | |
2291 | ||
2292 | return ret; | |
2293 | } | |
2294 | ||
33897cc8 | 2295 | static int |
ead73183 SH |
2296 | fec_drv_remove(struct platform_device *pdev) |
2297 | { | |
2298 | struct net_device *ndev = platform_get_drvdata(pdev); | |
2299 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2300 | ||
54309fa6 | 2301 | cancel_delayed_work_sync(&(fep->delay_work.delay_work)); |
e163cc97 | 2302 | unregister_netdev(ndev); |
e6b043d5 | 2303 | fec_enet_mii_remove(fep); |
6605b730 | 2304 | del_timer_sync(&fep->time_keep); |
f6a4d607 FE |
2305 | if (fep->reg_phy) |
2306 | regulator_disable(fep->reg_phy); | |
6605b730 FL |
2307 | if (fep->ptp_clock) |
2308 | ptp_clock_unregister(fep->ptp_clock); | |
e8fcfcd5 | 2309 | fec_enet_clk_enable(ndev, false); |
ead73183 | 2310 | free_netdev(ndev); |
28e2188e | 2311 | |
ead73183 SH |
2312 | return 0; |
2313 | } | |
2314 | ||
bf7bfd7f | 2315 | #ifdef CONFIG_PM_SLEEP |
ead73183 | 2316 | static int |
87cad5c3 | 2317 | fec_suspend(struct device *dev) |
ead73183 | 2318 | { |
87cad5c3 | 2319 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 2320 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 2321 | |
04e5216d UKK |
2322 | if (netif_running(ndev)) { |
2323 | fec_stop(ndev); | |
2324 | netif_device_detach(ndev); | |
ead73183 | 2325 | } |
e8fcfcd5 | 2326 | fec_enet_clk_enable(ndev, false); |
5bbde4d2 | 2327 | pinctrl_pm_select_sleep_state(&fep->pdev->dev); |
04e5216d | 2328 | |
238f7bc7 FE |
2329 | if (fep->reg_phy) |
2330 | regulator_disable(fep->reg_phy); | |
2331 | ||
ead73183 SH |
2332 | return 0; |
2333 | } | |
2334 | ||
2335 | static int | |
87cad5c3 | 2336 | fec_resume(struct device *dev) |
ead73183 | 2337 | { |
87cad5c3 | 2338 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 2339 | struct fec_enet_private *fep = netdev_priv(ndev); |
238f7bc7 FE |
2340 | int ret; |
2341 | ||
2342 | if (fep->reg_phy) { | |
2343 | ret = regulator_enable(fep->reg_phy); | |
2344 | if (ret) | |
2345 | return ret; | |
2346 | } | |
ead73183 | 2347 | |
5bbde4d2 | 2348 | pinctrl_pm_select_default_state(&fep->pdev->dev); |
e8fcfcd5 | 2349 | ret = fec_enet_clk_enable(ndev, true); |
13a097bd | 2350 | if (ret) |
e8fcfcd5 | 2351 | goto failed_clk; |
13a097bd | 2352 | |
04e5216d UKK |
2353 | if (netif_running(ndev)) { |
2354 | fec_restart(ndev, fep->full_duplex); | |
2355 | netif_device_attach(ndev); | |
ead73183 | 2356 | } |
04e5216d | 2357 | |
ead73183 | 2358 | return 0; |
13a097bd | 2359 | |
e8fcfcd5 | 2360 | failed_clk: |
13a097bd FE |
2361 | if (fep->reg_phy) |
2362 | regulator_disable(fep->reg_phy); | |
2363 | return ret; | |
ead73183 | 2364 | } |
bf7bfd7f | 2365 | #endif /* CONFIG_PM_SLEEP */ |
ead73183 | 2366 | |
bf7bfd7f | 2367 | static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume); |
59d4289b | 2368 | |
ead73183 SH |
2369 | static struct platform_driver fec_driver = { |
2370 | .driver = { | |
b5680e0b | 2371 | .name = DRIVER_NAME, |
87cad5c3 | 2372 | .owner = THIS_MODULE, |
87cad5c3 | 2373 | .pm = &fec_pm_ops, |
ca2cc333 | 2374 | .of_match_table = fec_dt_ids, |
ead73183 | 2375 | }, |
b5680e0b | 2376 | .id_table = fec_devtype, |
87cad5c3 | 2377 | .probe = fec_probe, |
33897cc8 | 2378 | .remove = fec_drv_remove, |
ead73183 SH |
2379 | }; |
2380 | ||
aaca2377 | 2381 | module_platform_driver(fec_driver); |
1da177e4 | 2382 | |
f8c0aca9 | 2383 | MODULE_ALIAS("platform:"DRIVER_NAME); |
1da177e4 | 2384 | MODULE_LICENSE("GPL"); |