]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
b5680e0b | 20 | * |
230dec61 | 21 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
1da177e4 LT |
22 | */ |
23 | ||
1da177e4 LT |
24 | #include <linux/module.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/ptrace.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/interrupt.h> | |
1da177e4 LT |
32 | #include <linux/init.h> |
33 | #include <linux/delay.h> | |
34 | #include <linux/netdevice.h> | |
35 | #include <linux/etherdevice.h> | |
36 | #include <linux/skbuff.h> | |
4c09eed9 JB |
37 | #include <linux/in.h> |
38 | #include <linux/ip.h> | |
39 | #include <net/ip.h> | |
40 | #include <linux/tcp.h> | |
41 | #include <linux/udp.h> | |
42 | #include <linux/icmp.h> | |
1da177e4 LT |
43 | #include <linux/spinlock.h> |
44 | #include <linux/workqueue.h> | |
45 | #include <linux/bitops.h> | |
6f501b17 SH |
46 | #include <linux/io.h> |
47 | #include <linux/irq.h> | |
196719ec | 48 | #include <linux/clk.h> |
ead73183 | 49 | #include <linux/platform_device.h> |
e6b043d5 | 50 | #include <linux/phy.h> |
5eb32bd0 | 51 | #include <linux/fec.h> |
ca2cc333 SG |
52 | #include <linux/of.h> |
53 | #include <linux/of_device.h> | |
54 | #include <linux/of_gpio.h> | |
55 | #include <linux/of_net.h> | |
5fa9c0fe | 56 | #include <linux/regulator/consumer.h> |
1da177e4 | 57 | |
080853af | 58 | #include <asm/cacheflush.h> |
196719ec | 59 | |
1da177e4 | 60 | #include "fec.h" |
1da177e4 | 61 | |
772e42b0 CM |
62 | static void set_multicast_list(struct net_device *ndev); |
63 | ||
085e79ed | 64 | #if defined(CONFIG_ARM) |
196719ec SH |
65 | #define FEC_ALIGNMENT 0xf |
66 | #else | |
67 | #define FEC_ALIGNMENT 0x3 | |
68 | #endif | |
69 | ||
b5680e0b | 70 | #define DRIVER_NAME "fec" |
dc975382 | 71 | #define FEC_NAPI_WEIGHT 64 |
b5680e0b | 72 | |
baa70a5c FL |
73 | /* Pause frame feild and FIFO threshold */ |
74 | #define FEC_ENET_FCE (1 << 5) | |
75 | #define FEC_ENET_RSEM_V 0x84 | |
76 | #define FEC_ENET_RSFL_V 16 | |
77 | #define FEC_ENET_RAEM_V 0x8 | |
78 | #define FEC_ENET_RAFL_V 0x8 | |
79 | #define FEC_ENET_OPD_V 0xFFF0 | |
80 | ||
b5680e0b SG |
81 | /* Controller is ENET-MAC */ |
82 | #define FEC_QUIRK_ENET_MAC (1 << 0) | |
83 | /* Controller needs driver to swap frame */ | |
84 | #define FEC_QUIRK_SWAP_FRAME (1 << 1) | |
0ca1e290 SG |
85 | /* Controller uses gasket */ |
86 | #define FEC_QUIRK_USE_GASKET (1 << 2) | |
230dec61 SG |
87 | /* Controller has GBIT support */ |
88 | #define FEC_QUIRK_HAS_GBIT (1 << 3) | |
ff43da86 FL |
89 | /* Controller has extend desc buffer */ |
90 | #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) | |
48496255 SG |
91 | /* Controller has hardware checksum support */ |
92 | #define FEC_QUIRK_HAS_CSUM (1 << 5) | |
b5680e0b SG |
93 | |
94 | static struct platform_device_id fec_devtype[] = { | |
95 | { | |
0ca1e290 | 96 | /* keep it for coldfire */ |
b5680e0b SG |
97 | .name = DRIVER_NAME, |
98 | .driver_data = 0, | |
0ca1e290 SG |
99 | }, { |
100 | .name = "imx25-fec", | |
101 | .driver_data = FEC_QUIRK_USE_GASKET, | |
102 | }, { | |
103 | .name = "imx27-fec", | |
104 | .driver_data = 0, | |
b5680e0b SG |
105 | }, { |
106 | .name = "imx28-fec", | |
107 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, | |
230dec61 SG |
108 | }, { |
109 | .name = "imx6q-fec", | |
ff43da86 | 110 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | |
48496255 | 111 | FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM, |
ca7c4a45 | 112 | }, { |
36803542 | 113 | .name = "mvf600-fec", |
ca7c4a45 | 114 | .driver_data = FEC_QUIRK_ENET_MAC, |
0ca1e290 SG |
115 | }, { |
116 | /* sentinel */ | |
117 | } | |
b5680e0b | 118 | }; |
0ca1e290 | 119 | MODULE_DEVICE_TABLE(platform, fec_devtype); |
b5680e0b | 120 | |
ca2cc333 | 121 | enum imx_fec_type { |
a7dd3219 | 122 | IMX25_FEC = 1, /* runs on i.mx25/50/53 */ |
ca2cc333 SG |
123 | IMX27_FEC, /* runs on i.mx27/35/51 */ |
124 | IMX28_FEC, | |
230dec61 | 125 | IMX6Q_FEC, |
36803542 | 126 | MVF600_FEC, |
ca2cc333 SG |
127 | }; |
128 | ||
129 | static const struct of_device_id fec_dt_ids[] = { | |
130 | { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, | |
131 | { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, | |
132 | { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, | |
230dec61 | 133 | { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, |
36803542 | 134 | { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, |
ca2cc333 SG |
135 | { /* sentinel */ } |
136 | }; | |
137 | MODULE_DEVICE_TABLE(of, fec_dt_ids); | |
138 | ||
49da97dc SG |
139 | static unsigned char macaddr[ETH_ALEN]; |
140 | module_param_array(macaddr, byte, NULL, 0); | |
141 | MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); | |
1da177e4 | 142 | |
49da97dc | 143 | #if defined(CONFIG_M5272) |
1da177e4 LT |
144 | /* |
145 | * Some hardware gets it MAC address out of local flash memory. | |
146 | * if this is non-zero then assume it is the address to get MAC from. | |
147 | */ | |
148 | #if defined(CONFIG_NETtel) | |
149 | #define FEC_FLASHMAC 0xf0006006 | |
150 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
151 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
152 | #elif defined(CONFIG_CANCam) |
153 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
154 | #elif defined (CONFIG_M5272C3) |
155 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
156 | #elif defined(CONFIG_MOD5272) | |
a7dd3219 | 157 | #define FEC_FLASHMAC 0xffc0406b |
1da177e4 LT |
158 | #else |
159 | #define FEC_FLASHMAC 0 | |
160 | #endif | |
43be6366 | 161 | #endif /* CONFIG_M5272 */ |
ead73183 | 162 | |
ff43da86 | 163 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE) |
6b265293 | 164 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
165 | #endif |
166 | ||
22f6b860 | 167 | /* Interrupt events/masks. */ |
1da177e4 LT |
168 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
169 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
170 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
171 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
172 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
173 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
174 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
175 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
176 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
177 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
178 | ||
4bee1f9a | 179 | #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) |
dc975382 | 180 | #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) |
4bee1f9a | 181 | |
1da177e4 LT |
182 | /* The FEC stores dest/src/type, data, and checksum for receive packets. |
183 | */ | |
184 | #define PKT_MAXBUF_SIZE 1518 | |
185 | #define PKT_MINBUF_SIZE 64 | |
186 | #define PKT_MAXBLR_SIZE 1520 | |
187 | ||
4c09eed9 JB |
188 | /* FEC receive acceleration */ |
189 | #define FEC_RACC_IPDIS (1 << 1) | |
190 | #define FEC_RACC_PRODIS (1 << 2) | |
191 | #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) | |
192 | ||
1da177e4 | 193 | /* |
6b265293 | 194 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
195 | * size bits. Other FEC hardware does not, so we need to take that into |
196 | * account when setting it. | |
197 | */ | |
562d2f8c | 198 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
085e79ed | 199 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) |
1da177e4 LT |
200 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
201 | #else | |
202 | #define OPT_FRAME_SIZE 0 | |
203 | #endif | |
204 | ||
e6b043d5 BW |
205 | /* FEC MII MMFR bits definition */ |
206 | #define FEC_MMFR_ST (1 << 30) | |
207 | #define FEC_MMFR_OP_READ (2 << 28) | |
208 | #define FEC_MMFR_OP_WRITE (1 << 28) | |
209 | #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) | |
210 | #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) | |
211 | #define FEC_MMFR_TA (2 << 16) | |
212 | #define FEC_MMFR_DATA(v) (v & 0xffff) | |
1da177e4 | 213 | |
c3b084c2 | 214 | #define FEC_MII_TIMEOUT 30000 /* us */ |
1da177e4 | 215 | |
22f6b860 SH |
216 | /* Transmitter timeout */ |
217 | #define TX_TIMEOUT (2 * HZ) | |
1da177e4 | 218 | |
baa70a5c FL |
219 | #define FEC_PAUSE_FLAG_AUTONEG 0x1 |
220 | #define FEC_PAUSE_FLAG_ENABLE 0x2 | |
221 | ||
e163cc97 LW |
222 | static int mii_cnt; |
223 | ||
ff43da86 FL |
224 | static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex) |
225 | { | |
226 | struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; | |
227 | if (is_ex) | |
228 | return (struct bufdesc *)(ex + 1); | |
229 | else | |
230 | return bdp + 1; | |
231 | } | |
232 | ||
233 | static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex) | |
234 | { | |
235 | struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; | |
236 | if (is_ex) | |
237 | return (struct bufdesc *)(ex - 1); | |
238 | else | |
239 | return bdp - 1; | |
240 | } | |
241 | ||
b5680e0b SG |
242 | static void *swap_buffer(void *bufaddr, int len) |
243 | { | |
244 | int i; | |
245 | unsigned int *buf = bufaddr; | |
246 | ||
ffed61e6 | 247 | for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++) |
b5680e0b SG |
248 | *buf = cpu_to_be32(*buf); |
249 | ||
250 | return bufaddr; | |
251 | } | |
252 | ||
4c09eed9 JB |
253 | static int |
254 | fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) | |
255 | { | |
256 | /* Only run for packets requiring a checksum. */ | |
257 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
258 | return 0; | |
259 | ||
260 | if (unlikely(skb_cow_head(skb, 0))) | |
261 | return -1; | |
262 | ||
263 | *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; | |
264 | ||
265 | return 0; | |
266 | } | |
267 | ||
c7621cb3 | 268 | static netdev_tx_t |
c556167f | 269 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
1da177e4 | 270 | { |
c556167f | 271 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
272 | const struct platform_device_id *id_entry = |
273 | platform_get_device_id(fep->pdev); | |
2e28532f | 274 | struct bufdesc *bdp; |
9555b31e | 275 | void *bufaddr; |
0e702ab3 | 276 | unsigned short status; |
de5fb0a0 | 277 | unsigned int index; |
1da177e4 | 278 | |
1da177e4 | 279 | if (!fep->link) { |
4c09eed9 | 280 | /* Link is down or auto-negotiation is in progress. */ |
5b548140 | 281 | return NETDEV_TX_BUSY; |
1da177e4 LT |
282 | } |
283 | ||
284 | /* Fill in a Tx ring entry */ | |
285 | bdp = fep->cur_tx; | |
286 | ||
0e702ab3 | 287 | status = bdp->cbd_sc; |
22f6b860 | 288 | |
0e702ab3 | 289 | if (status & BD_ENET_TX_READY) { |
1da177e4 | 290 | /* Ooops. All transmit buffers are full. Bail out. |
c556167f | 291 | * This should not happen, since ndev->tbusy should be set. |
1da177e4 | 292 | */ |
31b7720c | 293 | netdev_err(ndev, "tx queue full!\n"); |
5b548140 | 294 | return NETDEV_TX_BUSY; |
1da177e4 | 295 | } |
1da177e4 | 296 | |
4c09eed9 JB |
297 | /* Protocol checksum off-load for TCP and UDP. */ |
298 | if (fec_enet_clear_csum(skb, ndev)) { | |
299 | kfree_skb(skb); | |
300 | return NETDEV_TX_OK; | |
301 | } | |
302 | ||
22f6b860 | 303 | /* Clear all of the status flags */ |
0e702ab3 | 304 | status &= ~BD_ENET_TX_STATS; |
1da177e4 | 305 | |
22f6b860 | 306 | /* Set buffer length and buffer pointer */ |
9555b31e | 307 | bufaddr = skb->data; |
1da177e4 LT |
308 | bdp->cbd_datlen = skb->len; |
309 | ||
310 | /* | |
22f6b860 SH |
311 | * On some FEC implementations data must be aligned on |
312 | * 4-byte boundaries. Use bounce buffers to copy data | |
313 | * and get it aligned. Ugh. | |
1da177e4 | 314 | */ |
de5fb0a0 FL |
315 | if (fep->bufdesc_ex) |
316 | index = (struct bufdesc_ex *)bdp - | |
317 | (struct bufdesc_ex *)fep->tx_bd_base; | |
318 | else | |
319 | index = bdp - fep->tx_bd_base; | |
320 | ||
9555b31e | 321 | if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { |
8a73b0bc | 322 | memcpy(fep->tx_bounce[index], skb->data, skb->len); |
9555b31e | 323 | bufaddr = fep->tx_bounce[index]; |
1da177e4 LT |
324 | } |
325 | ||
b5680e0b SG |
326 | /* |
327 | * Some design made an incorrect assumption on endian mode of | |
328 | * the system that it's running on. As the result, driver has to | |
329 | * swap every frame going to and coming from the controller. | |
330 | */ | |
331 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) | |
332 | swap_buffer(bufaddr, skb->len); | |
333 | ||
22f6b860 | 334 | /* Save skb pointer */ |
de5fb0a0 | 335 | fep->tx_skbuff[index] = skb; |
6aa20a22 | 336 | |
1da177e4 LT |
337 | /* Push the data cache so the CPM does not get stale memory |
338 | * data. | |
339 | */ | |
d1ab1f54 | 340 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, |
f0b3fbea | 341 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); |
1da177e4 | 342 | |
0e702ab3 GU |
343 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
344 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 | 345 | */ |
0e702ab3 | 346 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 347 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 348 | bdp->cbd_sc = status; |
1da177e4 | 349 | |
ff43da86 FL |
350 | if (fep->bufdesc_ex) { |
351 | ||
352 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
353 | ebdp->cbd_bdu = 0; | |
354 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && | |
6605b730 | 355 | fep->hwts_tx_en)) { |
ff43da86 | 356 | ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT); |
6605b730 | 357 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
ff43da86 | 358 | } else { |
ff43da86 | 359 | ebdp->cbd_esc = BD_ENET_TX_INT; |
4c09eed9 JB |
360 | |
361 | /* Enable protocol checksum flags | |
362 | * We do not bother with the IP Checksum bits as they | |
363 | * are done by the kernel | |
364 | */ | |
365 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
366 | ebdp->cbd_esc |= BD_ENET_TX_PINS; | |
ff43da86 | 367 | } |
6605b730 | 368 | } |
22f6b860 SH |
369 | /* If this was the last BD in the ring, start at the beginning again. */ |
370 | if (status & BD_ENET_TX_WRAP) | |
1da177e4 | 371 | bdp = fep->tx_bd_base; |
22f6b860 | 372 | else |
ff43da86 | 373 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
1da177e4 | 374 | |
de5fb0a0 FL |
375 | fep->cur_tx = bdp; |
376 | ||
377 | if (fep->cur_tx == fep->dirty_tx) | |
c556167f | 378 | netif_stop_queue(ndev); |
1da177e4 | 379 | |
de5fb0a0 FL |
380 | /* Trigger transmission start */ |
381 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); | |
1da177e4 | 382 | |
18a03b97 RC |
383 | skb_tx_timestamp(skb); |
384 | ||
6ed10654 | 385 | return NETDEV_TX_OK; |
1da177e4 LT |
386 | } |
387 | ||
14109a59 FL |
388 | /* Init RX & TX buffer descriptors |
389 | */ | |
390 | static void fec_enet_bd_init(struct net_device *dev) | |
391 | { | |
392 | struct fec_enet_private *fep = netdev_priv(dev); | |
393 | struct bufdesc *bdp; | |
394 | unsigned int i; | |
395 | ||
396 | /* Initialize the receive buffer descriptors. */ | |
397 | bdp = fep->rx_bd_base; | |
398 | for (i = 0; i < RX_RING_SIZE; i++) { | |
399 | ||
400 | /* Initialize the BD for every fragment in the page. */ | |
401 | if (bdp->cbd_bufaddr) | |
402 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
403 | else | |
404 | bdp->cbd_sc = 0; | |
405 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
406 | } | |
407 | ||
408 | /* Set the last buffer to wrap */ | |
409 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); | |
410 | bdp->cbd_sc |= BD_SC_WRAP; | |
411 | ||
412 | fep->cur_rx = fep->rx_bd_base; | |
413 | ||
414 | /* ...and the same for transmit */ | |
415 | bdp = fep->tx_bd_base; | |
416 | fep->cur_tx = bdp; | |
417 | for (i = 0; i < TX_RING_SIZE; i++) { | |
418 | ||
419 | /* Initialize the BD for every fragment in the page. */ | |
420 | bdp->cbd_sc = 0; | |
421 | if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) { | |
422 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
423 | fep->tx_skbuff[i] = NULL; | |
424 | } | |
425 | bdp->cbd_bufaddr = 0; | |
426 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
427 | } | |
428 | ||
429 | /* Set the last buffer to wrap */ | |
430 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); | |
431 | bdp->cbd_sc |= BD_SC_WRAP; | |
432 | fep->dirty_tx = bdp; | |
433 | } | |
434 | ||
45993653 UKK |
435 | /* This function is called to start or restart the FEC during a link |
436 | * change. This only happens when switching between half and full | |
437 | * duplex. | |
438 | */ | |
1da177e4 | 439 | static void |
45993653 | 440 | fec_restart(struct net_device *ndev, int duplex) |
1da177e4 | 441 | { |
c556167f | 442 | struct fec_enet_private *fep = netdev_priv(ndev); |
45993653 UKK |
443 | const struct platform_device_id *id_entry = |
444 | platform_get_device_id(fep->pdev); | |
445 | int i; | |
4c09eed9 | 446 | u32 val; |
cd1f402c UKK |
447 | u32 temp_mac[2]; |
448 | u32 rcntl = OPT_FRAME_SIZE | 0x04; | |
230dec61 | 449 | u32 ecntl = 0x2; /* ETHEREN */ |
1da177e4 | 450 | |
54309fa6 FL |
451 | if (netif_running(ndev)) { |
452 | netif_device_detach(ndev); | |
453 | napi_disable(&fep->napi); | |
454 | netif_stop_queue(ndev); | |
31691344 | 455 | netif_tx_lock_bh(ndev); |
54309fa6 FL |
456 | } |
457 | ||
45993653 UKK |
458 | /* Whack a reset. We should wait for this. */ |
459 | writel(1, fep->hwp + FEC_ECNTRL); | |
460 | udelay(10); | |
1da177e4 | 461 | |
45993653 UKK |
462 | /* |
463 | * enet-mac reset will reset mac address registers too, | |
464 | * so need to reconfigure it. | |
465 | */ | |
466 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
467 | memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); | |
468 | writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); | |
469 | writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); | |
470 | } | |
1da177e4 | 471 | |
45993653 UKK |
472 | /* Clear any outstanding interrupt. */ |
473 | writel(0xffc00000, fep->hwp + FEC_IEVENT); | |
1da177e4 | 474 | |
772e42b0 CM |
475 | /* Setup multicast filter. */ |
476 | set_multicast_list(ndev); | |
45993653 UKK |
477 | #ifndef CONFIG_M5272 |
478 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); | |
479 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
480 | #endif | |
1da177e4 | 481 | |
45993653 UKK |
482 | /* Set maximum receive buffer size. */ |
483 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); | |
1da177e4 | 484 | |
14109a59 FL |
485 | fec_enet_bd_init(ndev); |
486 | ||
45993653 UKK |
487 | /* Set receive and transmit descriptor base. */ |
488 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); | |
ff43da86 FL |
489 | if (fep->bufdesc_ex) |
490 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex) | |
491 | * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); | |
492 | else | |
493 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) | |
494 | * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); | |
45993653 | 495 | |
45993653 | 496 | |
45993653 UKK |
497 | for (i = 0; i <= TX_RING_MOD_MASK; i++) { |
498 | if (fep->tx_skbuff[i]) { | |
499 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
500 | fep->tx_skbuff[i] = NULL; | |
1da177e4 | 501 | } |
45993653 | 502 | } |
97b72e43 | 503 | |
45993653 UKK |
504 | /* Enable MII mode */ |
505 | if (duplex) { | |
cd1f402c | 506 | /* FD enable */ |
45993653 UKK |
507 | writel(0x04, fep->hwp + FEC_X_CNTRL); |
508 | } else { | |
cd1f402c UKK |
509 | /* No Rcv on Xmit */ |
510 | rcntl |= 0x02; | |
45993653 UKK |
511 | writel(0x0, fep->hwp + FEC_X_CNTRL); |
512 | } | |
cd1f402c | 513 | |
45993653 UKK |
514 | fep->full_duplex = duplex; |
515 | ||
516 | /* Set MII speed */ | |
517 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
518 | ||
4c09eed9 JB |
519 | /* set RX checksum */ |
520 | val = readl(fep->hwp + FEC_RACC); | |
521 | if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) | |
522 | val |= FEC_RACC_OPTIONS; | |
523 | else | |
524 | val &= ~FEC_RACC_OPTIONS; | |
525 | writel(val, fep->hwp + FEC_RACC); | |
526 | ||
45993653 UKK |
527 | /* |
528 | * The phy interface and speed need to get configured | |
529 | * differently on enet-mac. | |
530 | */ | |
531 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
cd1f402c UKK |
532 | /* Enable flow control and length check */ |
533 | rcntl |= 0x40000000 | 0x00000020; | |
45993653 | 534 | |
230dec61 SG |
535 | /* RGMII, RMII or MII */ |
536 | if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) | |
537 | rcntl |= (1 << 6); | |
538 | else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) | |
cd1f402c | 539 | rcntl |= (1 << 8); |
45993653 | 540 | else |
cd1f402c | 541 | rcntl &= ~(1 << 8); |
45993653 | 542 | |
230dec61 SG |
543 | /* 1G, 100M or 10M */ |
544 | if (fep->phy_dev) { | |
545 | if (fep->phy_dev->speed == SPEED_1000) | |
546 | ecntl |= (1 << 5); | |
547 | else if (fep->phy_dev->speed == SPEED_100) | |
548 | rcntl &= ~(1 << 9); | |
549 | else | |
550 | rcntl |= (1 << 9); | |
551 | } | |
45993653 UKK |
552 | } else { |
553 | #ifdef FEC_MIIGSK_ENR | |
0ca1e290 | 554 | if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { |
8d82f219 | 555 | u32 cfgr; |
45993653 UKK |
556 | /* disable the gasket and wait */ |
557 | writel(0, fep->hwp + FEC_MIIGSK_ENR); | |
558 | while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) | |
559 | udelay(1); | |
560 | ||
561 | /* | |
562 | * configure the gasket: | |
563 | * RMII, 50 MHz, no loopback, no echo | |
0ca1e290 | 564 | * MII, 25 MHz, no loopback, no echo |
45993653 | 565 | */ |
8d82f219 EB |
566 | cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) |
567 | ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; | |
568 | if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) | |
569 | cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; | |
570 | writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); | |
45993653 UKK |
571 | |
572 | /* re-enable the gasket */ | |
573 | writel(2, fep->hwp + FEC_MIIGSK_ENR); | |
97b72e43 | 574 | } |
45993653 UKK |
575 | #endif |
576 | } | |
baa70a5c FL |
577 | |
578 | /* enable pause frame*/ | |
579 | if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || | |
580 | ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && | |
581 | fep->phy_dev && fep->phy_dev->pause)) { | |
582 | rcntl |= FEC_ENET_FCE; | |
583 | ||
4c09eed9 | 584 | /* set FIFO threshold parameter to reduce overrun */ |
baa70a5c FL |
585 | writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); |
586 | writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); | |
587 | writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); | |
588 | writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); | |
589 | ||
590 | /* OPD */ | |
591 | writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); | |
592 | } else { | |
593 | rcntl &= ~FEC_ENET_FCE; | |
594 | } | |
595 | ||
cd1f402c | 596 | writel(rcntl, fep->hwp + FEC_R_CNTRL); |
3b2b74ca | 597 | |
230dec61 SG |
598 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
599 | /* enable ENET endian swap */ | |
600 | ecntl |= (1 << 8); | |
601 | /* enable ENET store and forward mode */ | |
602 | writel(1 << 8, fep->hwp + FEC_X_WMRK); | |
603 | } | |
604 | ||
ff43da86 FL |
605 | if (fep->bufdesc_ex) |
606 | ecntl |= (1 << 4); | |
6605b730 | 607 | |
38ae92dc CH |
608 | #ifndef CONFIG_M5272 |
609 | /* Disable, clear, and enable the MIB */ | |
610 | writel(1 << 31, fep->hwp + FEC_MIB_CTRLSTAT); | |
611 | for (i = RMON_T_DROP; i < IEEE_R_OCTETS_OK; i++) | |
612 | writel(0, fep->hwp + i); | |
613 | writel(0, fep->hwp + FEC_MIB_CTRLSTAT); | |
614 | #endif | |
615 | ||
45993653 | 616 | /* And last, enable the transmit and receive processing */ |
230dec61 | 617 | writel(ecntl, fep->hwp + FEC_ECNTRL); |
45993653 UKK |
618 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); |
619 | ||
ff43da86 FL |
620 | if (fep->bufdesc_ex) |
621 | fec_ptp_start_cyclecounter(ndev); | |
622 | ||
45993653 UKK |
623 | /* Enable interrupts we wish to service */ |
624 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
54309fa6 FL |
625 | |
626 | if (netif_running(ndev)) { | |
31691344 | 627 | netif_tx_unlock_bh(ndev); |
54309fa6 | 628 | netif_wake_queue(ndev); |
1ed0d56c FE |
629 | napi_enable(&fep->napi); |
630 | netif_device_attach(ndev); | |
54309fa6 | 631 | } |
45993653 UKK |
632 | } |
633 | ||
634 | static void | |
635 | fec_stop(struct net_device *ndev) | |
636 | { | |
637 | struct fec_enet_private *fep = netdev_priv(ndev); | |
230dec61 SG |
638 | const struct platform_device_id *id_entry = |
639 | platform_get_device_id(fep->pdev); | |
42431dc2 | 640 | u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); |
45993653 UKK |
641 | |
642 | /* We cannot expect a graceful transmit stop without link !!! */ | |
643 | if (fep->link) { | |
644 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
645 | udelay(10); | |
646 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) | |
31b7720c | 647 | netdev_err(ndev, "Graceful transmit stop did not complete!\n"); |
45993653 UKK |
648 | } |
649 | ||
650 | /* Whack a reset. We should wait for this. */ | |
651 | writel(1, fep->hwp + FEC_ECNTRL); | |
652 | udelay(10); | |
653 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
654 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
230dec61 SG |
655 | |
656 | /* We have to keep ENET enabled to have MII interrupt stay working */ | |
42431dc2 | 657 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
230dec61 | 658 | writel(2, fep->hwp + FEC_ECNTRL); |
42431dc2 LW |
659 | writel(rmii_mode, fep->hwp + FEC_R_CNTRL); |
660 | } | |
1da177e4 LT |
661 | } |
662 | ||
663 | ||
45993653 UKK |
664 | static void |
665 | fec_timeout(struct net_device *ndev) | |
666 | { | |
667 | struct fec_enet_private *fep = netdev_priv(ndev); | |
668 | ||
669 | ndev->stats.tx_errors++; | |
670 | ||
54309fa6 FL |
671 | fep->delay_work.timeout = true; |
672 | schedule_delayed_work(&(fep->delay_work.delay_work), 0); | |
673 | } | |
674 | ||
675 | static void fec_enet_work(struct work_struct *work) | |
676 | { | |
677 | struct fec_enet_private *fep = | |
678 | container_of(work, | |
679 | struct fec_enet_private, | |
680 | delay_work.delay_work.work); | |
681 | ||
682 | if (fep->delay_work.timeout) { | |
683 | fep->delay_work.timeout = false; | |
684 | fec_restart(fep->netdev, fep->full_duplex); | |
685 | netif_wake_queue(fep->netdev); | |
686 | } | |
45993653 UKK |
687 | } |
688 | ||
1da177e4 | 689 | static void |
c556167f | 690 | fec_enet_tx(struct net_device *ndev) |
1da177e4 LT |
691 | { |
692 | struct fec_enet_private *fep; | |
2e28532f | 693 | struct bufdesc *bdp; |
0e702ab3 | 694 | unsigned short status; |
1da177e4 | 695 | struct sk_buff *skb; |
de5fb0a0 | 696 | int index = 0; |
1da177e4 | 697 | |
c556167f | 698 | fep = netdev_priv(ndev); |
1da177e4 LT |
699 | bdp = fep->dirty_tx; |
700 | ||
de5fb0a0 FL |
701 | /* get next bdp of dirty_tx */ |
702 | if (bdp->cbd_sc & BD_ENET_TX_WRAP) | |
703 | bdp = fep->tx_bd_base; | |
704 | else | |
705 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
706 | ||
0e702ab3 | 707 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
de5fb0a0 FL |
708 | |
709 | /* current queue is empty */ | |
710 | if (bdp == fep->cur_tx) | |
f0b3fbea SH |
711 | break; |
712 | ||
de5fb0a0 FL |
713 | if (fep->bufdesc_ex) |
714 | index = (struct bufdesc_ex *)bdp - | |
715 | (struct bufdesc_ex *)fep->tx_bd_base; | |
716 | else | |
717 | index = bdp - fep->tx_bd_base; | |
718 | ||
d1ab1f54 UKK |
719 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
720 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); | |
f0b3fbea | 721 | bdp->cbd_bufaddr = 0; |
1da177e4 | 722 | |
de5fb0a0 FL |
723 | skb = fep->tx_skbuff[index]; |
724 | ||
1da177e4 | 725 | /* Check for errors. */ |
0e702ab3 | 726 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
727 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
728 | BD_ENET_TX_CSL)) { | |
c556167f | 729 | ndev->stats.tx_errors++; |
0e702ab3 | 730 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
c556167f | 731 | ndev->stats.tx_heartbeat_errors++; |
0e702ab3 | 732 | if (status & BD_ENET_TX_LC) /* Late collision */ |
c556167f | 733 | ndev->stats.tx_window_errors++; |
0e702ab3 | 734 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
c556167f | 735 | ndev->stats.tx_aborted_errors++; |
0e702ab3 | 736 | if (status & BD_ENET_TX_UN) /* Underrun */ |
c556167f | 737 | ndev->stats.tx_fifo_errors++; |
0e702ab3 | 738 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
c556167f | 739 | ndev->stats.tx_carrier_errors++; |
1da177e4 | 740 | } else { |
c556167f | 741 | ndev->stats.tx_packets++; |
06efce71 | 742 | ndev->stats.tx_bytes += bdp->cbd_datlen; |
1da177e4 LT |
743 | } |
744 | ||
ff43da86 FL |
745 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && |
746 | fep->bufdesc_ex) { | |
6605b730 FL |
747 | struct skb_shared_hwtstamps shhwtstamps; |
748 | unsigned long flags; | |
ff43da86 | 749 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; |
6605b730 FL |
750 | |
751 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
752 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
753 | shhwtstamps.hwtstamp = ns_to_ktime( | |
ff43da86 | 754 | timecounter_cyc2time(&fep->tc, ebdp->ts)); |
6605b730 FL |
755 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
756 | skb_tstamp_tx(skb, &shhwtstamps); | |
757 | } | |
ff43da86 | 758 | |
0e702ab3 | 759 | if (status & BD_ENET_TX_READY) |
31b7720c | 760 | netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n"); |
22f6b860 | 761 | |
1da177e4 LT |
762 | /* Deferred means some collisions occurred during transmit, |
763 | * but we eventually sent the packet OK. | |
764 | */ | |
0e702ab3 | 765 | if (status & BD_ENET_TX_DEF) |
c556167f | 766 | ndev->stats.collisions++; |
6aa20a22 | 767 | |
22f6b860 | 768 | /* Free the sk buffer associated with this last transmit */ |
1da177e4 | 769 | dev_kfree_skb_any(skb); |
de5fb0a0 FL |
770 | fep->tx_skbuff[index] = NULL; |
771 | ||
772 | fep->dirty_tx = bdp; | |
6aa20a22 | 773 | |
22f6b860 | 774 | /* Update pointer to next buffer descriptor to be transmitted */ |
0e702ab3 | 775 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
776 | bdp = fep->tx_bd_base; |
777 | else | |
ff43da86 | 778 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
6aa20a22 | 779 | |
22f6b860 | 780 | /* Since we have freed up a buffer, the ring is no longer full |
1da177e4 | 781 | */ |
de5fb0a0 | 782 | if (fep->dirty_tx != fep->cur_tx) { |
c556167f UKK |
783 | if (netif_queue_stopped(ndev)) |
784 | netif_wake_queue(ndev); | |
1da177e4 LT |
785 | } |
786 | } | |
de5fb0a0 | 787 | return; |
1da177e4 LT |
788 | } |
789 | ||
790 | ||
791 | /* During a receive, the cur_rx points to the current incoming buffer. | |
792 | * When we update through the ring, if the next incoming buffer has | |
793 | * not been given to the system, we just set the empty indicator, | |
794 | * effectively tossing the packet. | |
795 | */ | |
dc975382 FL |
796 | static int |
797 | fec_enet_rx(struct net_device *ndev, int budget) | |
1da177e4 | 798 | { |
c556167f | 799 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
800 | const struct platform_device_id *id_entry = |
801 | platform_get_device_id(fep->pdev); | |
2e28532f | 802 | struct bufdesc *bdp; |
0e702ab3 | 803 | unsigned short status; |
1da177e4 LT |
804 | struct sk_buff *skb; |
805 | ushort pkt_len; | |
806 | __u8 *data; | |
dc975382 | 807 | int pkt_received = 0; |
6aa20a22 | 808 | |
0e702ab3 GU |
809 | #ifdef CONFIG_M532x |
810 | flush_cache_all(); | |
6aa20a22 | 811 | #endif |
1da177e4 | 812 | |
1da177e4 LT |
813 | /* First, grab all of the stats for the incoming packet. |
814 | * These get messed up if we get called due to a busy condition. | |
815 | */ | |
816 | bdp = fep->cur_rx; | |
817 | ||
22f6b860 | 818 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 | 819 | |
dc975382 FL |
820 | if (pkt_received >= budget) |
821 | break; | |
822 | pkt_received++; | |
823 | ||
22f6b860 SH |
824 | /* Since we have allocated space to hold a complete frame, |
825 | * the last indicator should be set. | |
826 | */ | |
827 | if ((status & BD_ENET_RX_LAST) == 0) | |
31b7720c | 828 | netdev_err(ndev, "rcv is not +last\n"); |
1da177e4 | 829 | |
22f6b860 SH |
830 | if (!fep->opened) |
831 | goto rx_processing_done; | |
1da177e4 | 832 | |
22f6b860 SH |
833 | /* Check for errors. */ |
834 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | | |
1da177e4 | 835 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
c556167f | 836 | ndev->stats.rx_errors++; |
22f6b860 SH |
837 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
838 | /* Frame too long or too short. */ | |
c556167f | 839 | ndev->stats.rx_length_errors++; |
22f6b860 SH |
840 | } |
841 | if (status & BD_ENET_RX_NO) /* Frame alignment */ | |
c556167f | 842 | ndev->stats.rx_frame_errors++; |
22f6b860 | 843 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
c556167f | 844 | ndev->stats.rx_crc_errors++; |
22f6b860 | 845 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
c556167f | 846 | ndev->stats.rx_fifo_errors++; |
1da177e4 | 847 | } |
1da177e4 | 848 | |
22f6b860 SH |
849 | /* Report late collisions as a frame error. |
850 | * On this error, the BD is closed, but we don't know what we | |
851 | * have in the buffer. So, just drop this frame on the floor. | |
852 | */ | |
853 | if (status & BD_ENET_RX_CL) { | |
c556167f UKK |
854 | ndev->stats.rx_errors++; |
855 | ndev->stats.rx_frame_errors++; | |
22f6b860 SH |
856 | goto rx_processing_done; |
857 | } | |
1da177e4 | 858 | |
22f6b860 | 859 | /* Process the incoming frame. */ |
c556167f | 860 | ndev->stats.rx_packets++; |
22f6b860 | 861 | pkt_len = bdp->cbd_datlen; |
c556167f | 862 | ndev->stats.rx_bytes += pkt_len; |
22f6b860 | 863 | data = (__u8*)__va(bdp->cbd_bufaddr); |
1da177e4 | 864 | |
d1ab1f54 UKK |
865 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
866 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
ccdc4f19 | 867 | |
b5680e0b SG |
868 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) |
869 | swap_buffer(data, pkt_len); | |
870 | ||
22f6b860 SH |
871 | /* This does 16 byte alignment, exactly what we need. |
872 | * The packet length includes FCS, but we don't want to | |
873 | * include that when passing upstream as it messes up | |
874 | * bridging applications. | |
875 | */ | |
b72061a3 | 876 | skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); |
1da177e4 | 877 | |
8549889c | 878 | if (unlikely(!skb)) { |
c556167f | 879 | ndev->stats.rx_dropped++; |
22f6b860 | 880 | } else { |
8549889c | 881 | skb_reserve(skb, NET_IP_ALIGN); |
22f6b860 SH |
882 | skb_put(skb, pkt_len - 4); /* Make room */ |
883 | skb_copy_to_linear_data(skb, data, pkt_len - 4); | |
c556167f | 884 | skb->protocol = eth_type_trans(skb, ndev); |
ff43da86 | 885 | |
6605b730 | 886 | /* Get receive timestamp from the skb */ |
ff43da86 | 887 | if (fep->hwts_rx_en && fep->bufdesc_ex) { |
6605b730 FL |
888 | struct skb_shared_hwtstamps *shhwtstamps = |
889 | skb_hwtstamps(skb); | |
890 | unsigned long flags; | |
ff43da86 FL |
891 | struct bufdesc_ex *ebdp = |
892 | (struct bufdesc_ex *)bdp; | |
6605b730 FL |
893 | |
894 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
895 | ||
896 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
897 | shhwtstamps->hwtstamp = ns_to_ktime( | |
ff43da86 | 898 | timecounter_cyc2time(&fep->tc, ebdp->ts)); |
6605b730 FL |
899 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
900 | } | |
ff43da86 | 901 | |
4c09eed9 JB |
902 | if (fep->bufdesc_ex && |
903 | (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { | |
904 | struct bufdesc_ex *ebdp = | |
905 | (struct bufdesc_ex *)bdp; | |
906 | if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) { | |
907 | /* don't check it */ | |
908 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
909 | } else { | |
910 | skb_checksum_none_assert(skb); | |
911 | } | |
912 | } | |
913 | ||
18a03b97 | 914 | if (!skb_defer_rx_timestamp(skb)) |
dc975382 | 915 | napi_gro_receive(&fep->napi, skb); |
22f6b860 | 916 | } |
f0b3fbea | 917 | |
d1ab1f54 UKK |
918 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data, |
919 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
22f6b860 SH |
920 | rx_processing_done: |
921 | /* Clear the status flags for this buffer */ | |
922 | status &= ~BD_ENET_RX_STATS; | |
1da177e4 | 923 | |
22f6b860 SH |
924 | /* Mark the buffer empty */ |
925 | status |= BD_ENET_RX_EMPTY; | |
926 | bdp->cbd_sc = status; | |
6aa20a22 | 927 | |
ff43da86 FL |
928 | if (fep->bufdesc_ex) { |
929 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
930 | ||
931 | ebdp->cbd_esc = BD_ENET_RX_INT; | |
932 | ebdp->cbd_prot = 0; | |
933 | ebdp->cbd_bdu = 0; | |
934 | } | |
6605b730 | 935 | |
22f6b860 SH |
936 | /* Update BD pointer to next entry */ |
937 | if (status & BD_ENET_RX_WRAP) | |
938 | bdp = fep->rx_bd_base; | |
939 | else | |
ff43da86 | 940 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
22f6b860 SH |
941 | /* Doing this here will keep the FEC running while we process |
942 | * incoming frames. On a heavily loaded network, we should be | |
943 | * able to keep up at the expense of system resources. | |
944 | */ | |
945 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
946 | } | |
2e28532f | 947 | fep->cur_rx = bdp; |
1da177e4 | 948 | |
dc975382 | 949 | return pkt_received; |
1da177e4 LT |
950 | } |
951 | ||
45993653 UKK |
952 | static irqreturn_t |
953 | fec_enet_interrupt(int irq, void *dev_id) | |
954 | { | |
955 | struct net_device *ndev = dev_id; | |
956 | struct fec_enet_private *fep = netdev_priv(ndev); | |
957 | uint int_events; | |
958 | irqreturn_t ret = IRQ_NONE; | |
959 | ||
960 | do { | |
961 | int_events = readl(fep->hwp + FEC_IEVENT); | |
962 | writel(int_events, fep->hwp + FEC_IEVENT); | |
963 | ||
de5fb0a0 | 964 | if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) { |
45993653 | 965 | ret = IRQ_HANDLED; |
dc975382 FL |
966 | |
967 | /* Disable the RX interrupt */ | |
968 | if (napi_schedule_prep(&fep->napi)) { | |
969 | writel(FEC_RX_DISABLED_IMASK, | |
970 | fep->hwp + FEC_IMASK); | |
971 | __napi_schedule(&fep->napi); | |
972 | } | |
45993653 UKK |
973 | } |
974 | ||
45993653 UKK |
975 | if (int_events & FEC_ENET_MII) { |
976 | ret = IRQ_HANDLED; | |
977 | complete(&fep->mdio_done); | |
978 | } | |
979 | } while (int_events); | |
980 | ||
981 | return ret; | |
982 | } | |
983 | ||
dc975382 FL |
984 | static int fec_enet_rx_napi(struct napi_struct *napi, int budget) |
985 | { | |
986 | struct net_device *ndev = napi->dev; | |
987 | int pkts = fec_enet_rx(ndev, budget); | |
988 | struct fec_enet_private *fep = netdev_priv(ndev); | |
45993653 | 989 | |
de5fb0a0 FL |
990 | fec_enet_tx(ndev); |
991 | ||
dc975382 FL |
992 | if (pkts < budget) { |
993 | napi_complete(napi); | |
994 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
995 | } | |
996 | return pkts; | |
997 | } | |
45993653 | 998 | |
e6b043d5 | 999 | /* ------------------------------------------------------------------------- */ |
0c7768a0 | 1000 | static void fec_get_mac(struct net_device *ndev) |
1da177e4 | 1001 | { |
c556167f | 1002 | struct fec_enet_private *fep = netdev_priv(ndev); |
49da97dc | 1003 | struct fec_platform_data *pdata = fep->pdev->dev.platform_data; |
e6b043d5 | 1004 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 | 1005 | |
49da97dc SG |
1006 | /* |
1007 | * try to get mac address in following order: | |
1008 | * | |
1009 | * 1) module parameter via kernel command line in form | |
1010 | * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 | |
1011 | */ | |
1012 | iap = macaddr; | |
1013 | ||
ca2cc333 SG |
1014 | /* |
1015 | * 2) from device tree data | |
1016 | */ | |
1017 | if (!is_valid_ether_addr(iap)) { | |
1018 | struct device_node *np = fep->pdev->dev.of_node; | |
1019 | if (np) { | |
1020 | const char *mac = of_get_mac_address(np); | |
1021 | if (mac) | |
1022 | iap = (unsigned char *) mac; | |
1023 | } | |
1024 | } | |
ca2cc333 | 1025 | |
49da97dc | 1026 | /* |
ca2cc333 | 1027 | * 3) from flash or fuse (via platform data) |
49da97dc SG |
1028 | */ |
1029 | if (!is_valid_ether_addr(iap)) { | |
1030 | #ifdef CONFIG_M5272 | |
1031 | if (FEC_FLASHMAC) | |
1032 | iap = (unsigned char *)FEC_FLASHMAC; | |
1033 | #else | |
1034 | if (pdata) | |
589efdc7 | 1035 | iap = (unsigned char *)&pdata->mac; |
49da97dc SG |
1036 | #endif |
1037 | } | |
1038 | ||
1039 | /* | |
ca2cc333 | 1040 | * 4) FEC mac registers set by bootloader |
49da97dc SG |
1041 | */ |
1042 | if (!is_valid_ether_addr(iap)) { | |
1043 | *((unsigned long *) &tmpaddr[0]) = | |
1044 | be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); | |
1045 | *((unsigned short *) &tmpaddr[4]) = | |
1046 | be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
e6b043d5 | 1047 | iap = &tmpaddr[0]; |
1da177e4 LT |
1048 | } |
1049 | ||
ff5b2fab LS |
1050 | /* |
1051 | * 5) random mac address | |
1052 | */ | |
1053 | if (!is_valid_ether_addr(iap)) { | |
1054 | /* Report it and use a random ethernet address instead */ | |
1055 | netdev_err(ndev, "Invalid MAC address: %pM\n", iap); | |
1056 | eth_hw_addr_random(ndev); | |
1057 | netdev_info(ndev, "Using random MAC address: %pM\n", | |
1058 | ndev->dev_addr); | |
1059 | return; | |
1060 | } | |
1061 | ||
c556167f | 1062 | memcpy(ndev->dev_addr, iap, ETH_ALEN); |
1da177e4 | 1063 | |
49da97dc SG |
1064 | /* Adjust MAC if using macaddr */ |
1065 | if (iap == macaddr) | |
43af940c | 1066 | ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; |
1da177e4 LT |
1067 | } |
1068 | ||
e6b043d5 | 1069 | /* ------------------------------------------------------------------------- */ |
1da177e4 | 1070 | |
e6b043d5 BW |
1071 | /* |
1072 | * Phy section | |
1073 | */ | |
c556167f | 1074 | static void fec_enet_adjust_link(struct net_device *ndev) |
1da177e4 | 1075 | { |
c556167f | 1076 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1077 | struct phy_device *phy_dev = fep->phy_dev; |
e6b043d5 | 1078 | int status_change = 0; |
1da177e4 | 1079 | |
e6b043d5 BW |
1080 | /* Prevent a state halted on mii error */ |
1081 | if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { | |
1082 | phy_dev->state = PHY_RESUMING; | |
54309fa6 | 1083 | return; |
e6b043d5 | 1084 | } |
1da177e4 | 1085 | |
e6b043d5 | 1086 | if (phy_dev->link) { |
d97e7497 | 1087 | if (!fep->link) { |
6ea0722f | 1088 | fep->link = phy_dev->link; |
e6b043d5 BW |
1089 | status_change = 1; |
1090 | } | |
1da177e4 | 1091 | |
d97e7497 LS |
1092 | if (fep->full_duplex != phy_dev->duplex) |
1093 | status_change = 1; | |
1094 | ||
1095 | if (phy_dev->speed != fep->speed) { | |
1096 | fep->speed = phy_dev->speed; | |
1097 | status_change = 1; | |
1098 | } | |
1099 | ||
1100 | /* if any of the above changed restart the FEC */ | |
1101 | if (status_change) | |
c556167f | 1102 | fec_restart(ndev, phy_dev->duplex); |
d97e7497 LS |
1103 | } else { |
1104 | if (fep->link) { | |
c556167f | 1105 | fec_stop(ndev); |
8d7ed0f0 | 1106 | fep->link = phy_dev->link; |
d97e7497 LS |
1107 | status_change = 1; |
1108 | } | |
1da177e4 | 1109 | } |
6aa20a22 | 1110 | |
e6b043d5 BW |
1111 | if (status_change) |
1112 | phy_print_status(phy_dev); | |
1113 | } | |
1da177e4 | 1114 | |
e6b043d5 | 1115 | static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
1da177e4 | 1116 | { |
e6b043d5 | 1117 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 1118 | unsigned long time_left; |
1da177e4 | 1119 | |
e6b043d5 | 1120 | fep->mii_timeout = 0; |
97b72e43 | 1121 | init_completion(&fep->mdio_done); |
e6b043d5 BW |
1122 | |
1123 | /* start a read op */ | |
1124 | writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | | |
1125 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | | |
1126 | FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); | |
1127 | ||
1128 | /* wait for end of transfer */ | |
97b72e43 BS |
1129 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
1130 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
1131 | if (time_left == 0) { | |
1132 | fep->mii_timeout = 1; | |
31b7720c | 1133 | netdev_err(fep->netdev, "MDIO read timeout\n"); |
97b72e43 | 1134 | return -ETIMEDOUT; |
1da177e4 | 1135 | } |
1da177e4 | 1136 | |
e6b043d5 BW |
1137 | /* return value */ |
1138 | return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); | |
7dd6a2aa | 1139 | } |
6aa20a22 | 1140 | |
e6b043d5 BW |
1141 | static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
1142 | u16 value) | |
1da177e4 | 1143 | { |
e6b043d5 | 1144 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 1145 | unsigned long time_left; |
1da177e4 | 1146 | |
e6b043d5 | 1147 | fep->mii_timeout = 0; |
97b72e43 | 1148 | init_completion(&fep->mdio_done); |
1da177e4 | 1149 | |
862f0982 SG |
1150 | /* start a write op */ |
1151 | writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | | |
e6b043d5 BW |
1152 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | |
1153 | FEC_MMFR_TA | FEC_MMFR_DATA(value), | |
1154 | fep->hwp + FEC_MII_DATA); | |
1155 | ||
1156 | /* wait for end of transfer */ | |
97b72e43 BS |
1157 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
1158 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
1159 | if (time_left == 0) { | |
1160 | fep->mii_timeout = 1; | |
31b7720c | 1161 | netdev_err(fep->netdev, "MDIO write timeout\n"); |
97b72e43 | 1162 | return -ETIMEDOUT; |
e6b043d5 | 1163 | } |
1da177e4 | 1164 | |
e6b043d5 BW |
1165 | return 0; |
1166 | } | |
1da177e4 | 1167 | |
e6b043d5 | 1168 | static int fec_enet_mdio_reset(struct mii_bus *bus) |
1da177e4 | 1169 | { |
e6b043d5 | 1170 | return 0; |
1da177e4 LT |
1171 | } |
1172 | ||
c556167f | 1173 | static int fec_enet_mii_probe(struct net_device *ndev) |
562d2f8c | 1174 | { |
c556167f | 1175 | struct fec_enet_private *fep = netdev_priv(ndev); |
230dec61 SG |
1176 | const struct platform_device_id *id_entry = |
1177 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 1178 | struct phy_device *phy_dev = NULL; |
6fcc040f GU |
1179 | char mdio_bus_id[MII_BUS_ID_SIZE]; |
1180 | char phy_name[MII_BUS_ID_SIZE + 3]; | |
1181 | int phy_id; | |
43af940c | 1182 | int dev_id = fep->dev_id; |
562d2f8c | 1183 | |
418bd0d4 BW |
1184 | fep->phy_dev = NULL; |
1185 | ||
6fcc040f GU |
1186 | /* check for attached phy */ |
1187 | for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { | |
1188 | if ((fep->mii_bus->phy_mask & (1 << phy_id))) | |
1189 | continue; | |
1190 | if (fep->mii_bus->phy_map[phy_id] == NULL) | |
1191 | continue; | |
1192 | if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) | |
1193 | continue; | |
b5680e0b SG |
1194 | if (dev_id--) |
1195 | continue; | |
6fcc040f GU |
1196 | strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); |
1197 | break; | |
e6b043d5 | 1198 | } |
1da177e4 | 1199 | |
6fcc040f | 1200 | if (phy_id >= PHY_MAX_ADDR) { |
31b7720c | 1201 | netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); |
ea51ade9 | 1202 | strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); |
6fcc040f GU |
1203 | phy_id = 0; |
1204 | } | |
1205 | ||
a7ed07d5 | 1206 | snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); |
f9a8f83b | 1207 | phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, |
230dec61 | 1208 | fep->phy_interface); |
6fcc040f | 1209 | if (IS_ERR(phy_dev)) { |
31b7720c | 1210 | netdev_err(ndev, "could not attach to PHY\n"); |
6fcc040f | 1211 | return PTR_ERR(phy_dev); |
e6b043d5 | 1212 | } |
1da177e4 | 1213 | |
e6b043d5 | 1214 | /* mask with MAC supported features */ |
baa70a5c | 1215 | if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) { |
230dec61 | 1216 | phy_dev->supported &= PHY_GBIT_FEATURES; |
baa70a5c FL |
1217 | phy_dev->supported |= SUPPORTED_Pause; |
1218 | } | |
230dec61 SG |
1219 | else |
1220 | phy_dev->supported &= PHY_BASIC_FEATURES; | |
1221 | ||
e6b043d5 | 1222 | phy_dev->advertising = phy_dev->supported; |
1da177e4 | 1223 | |
e6b043d5 BW |
1224 | fep->phy_dev = phy_dev; |
1225 | fep->link = 0; | |
1226 | fep->full_duplex = 0; | |
1da177e4 | 1227 | |
31b7720c JP |
1228 | netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", |
1229 | fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), | |
1230 | fep->phy_dev->irq); | |
418bd0d4 | 1231 | |
e6b043d5 | 1232 | return 0; |
1da177e4 LT |
1233 | } |
1234 | ||
e6b043d5 | 1235 | static int fec_enet_mii_init(struct platform_device *pdev) |
562d2f8c | 1236 | { |
b5680e0b | 1237 | static struct mii_bus *fec0_mii_bus; |
c556167f UKK |
1238 | struct net_device *ndev = platform_get_drvdata(pdev); |
1239 | struct fec_enet_private *fep = netdev_priv(ndev); | |
b5680e0b SG |
1240 | const struct platform_device_id *id_entry = |
1241 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 1242 | int err = -ENXIO, i; |
6b265293 | 1243 | |
b5680e0b SG |
1244 | /* |
1245 | * The dual fec interfaces are not equivalent with enet-mac. | |
1246 | * Here are the differences: | |
1247 | * | |
1248 | * - fec0 supports MII & RMII modes while fec1 only supports RMII | |
1249 | * - fec0 acts as the 1588 time master while fec1 is slave | |
1250 | * - external phys can only be configured by fec0 | |
1251 | * | |
1252 | * That is to say fec1 can not work independently. It only works | |
1253 | * when fec0 is working. The reason behind this design is that the | |
1254 | * second interface is added primarily for Switch mode. | |
1255 | * | |
1256 | * Because of the last point above, both phys are attached on fec0 | |
1257 | * mdio interface in board design, and need to be configured by | |
1258 | * fec0 mii_bus. | |
1259 | */ | |
43af940c | 1260 | if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { |
b5680e0b | 1261 | /* fec1 uses fec0 mii_bus */ |
e163cc97 LW |
1262 | if (mii_cnt && fec0_mii_bus) { |
1263 | fep->mii_bus = fec0_mii_bus; | |
1264 | mii_cnt++; | |
1265 | return 0; | |
1266 | } | |
1267 | return -ENOENT; | |
b5680e0b SG |
1268 | } |
1269 | ||
e6b043d5 | 1270 | fep->mii_timeout = 0; |
1da177e4 | 1271 | |
e6b043d5 BW |
1272 | /* |
1273 | * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) | |
230dec61 SG |
1274 | * |
1275 | * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while | |
1276 | * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 | |
1277 | * Reference Manual has an error on this, and gets fixed on i.MX6Q | |
1278 | * document. | |
e6b043d5 | 1279 | */ |
f4d40de3 | 1280 | fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000); |
230dec61 SG |
1281 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) |
1282 | fep->phy_speed--; | |
1283 | fep->phy_speed <<= 1; | |
e6b043d5 | 1284 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1da177e4 | 1285 | |
e6b043d5 BW |
1286 | fep->mii_bus = mdiobus_alloc(); |
1287 | if (fep->mii_bus == NULL) { | |
1288 | err = -ENOMEM; | |
1289 | goto err_out; | |
1da177e4 LT |
1290 | } |
1291 | ||
e6b043d5 BW |
1292 | fep->mii_bus->name = "fec_enet_mii_bus"; |
1293 | fep->mii_bus->read = fec_enet_mdio_read; | |
1294 | fep->mii_bus->write = fec_enet_mdio_write; | |
1295 | fep->mii_bus->reset = fec_enet_mdio_reset; | |
391420f7 FF |
1296 | snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
1297 | pdev->name, fep->dev_id + 1); | |
e6b043d5 BW |
1298 | fep->mii_bus->priv = fep; |
1299 | fep->mii_bus->parent = &pdev->dev; | |
1300 | ||
1301 | fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
1302 | if (!fep->mii_bus->irq) { | |
1303 | err = -ENOMEM; | |
1304 | goto err_out_free_mdiobus; | |
1da177e4 LT |
1305 | } |
1306 | ||
e6b043d5 BW |
1307 | for (i = 0; i < PHY_MAX_ADDR; i++) |
1308 | fep->mii_bus->irq[i] = PHY_POLL; | |
1da177e4 | 1309 | |
e6b043d5 BW |
1310 | if (mdiobus_register(fep->mii_bus)) |
1311 | goto err_out_free_mdio_irq; | |
1da177e4 | 1312 | |
e163cc97 LW |
1313 | mii_cnt++; |
1314 | ||
b5680e0b SG |
1315 | /* save fec0 mii_bus */ |
1316 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) | |
1317 | fec0_mii_bus = fep->mii_bus; | |
1318 | ||
e6b043d5 | 1319 | return 0; |
1da177e4 | 1320 | |
e6b043d5 BW |
1321 | err_out_free_mdio_irq: |
1322 | kfree(fep->mii_bus->irq); | |
1323 | err_out_free_mdiobus: | |
1324 | mdiobus_free(fep->mii_bus); | |
1325 | err_out: | |
1326 | return err; | |
1da177e4 LT |
1327 | } |
1328 | ||
e6b043d5 | 1329 | static void fec_enet_mii_remove(struct fec_enet_private *fep) |
1da177e4 | 1330 | { |
e163cc97 LW |
1331 | if (--mii_cnt == 0) { |
1332 | mdiobus_unregister(fep->mii_bus); | |
1333 | kfree(fep->mii_bus->irq); | |
1334 | mdiobus_free(fep->mii_bus); | |
1335 | } | |
1da177e4 LT |
1336 | } |
1337 | ||
c556167f | 1338 | static int fec_enet_get_settings(struct net_device *ndev, |
e6b043d5 | 1339 | struct ethtool_cmd *cmd) |
1da177e4 | 1340 | { |
c556167f | 1341 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1342 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1343 | |
e6b043d5 BW |
1344 | if (!phydev) |
1345 | return -ENODEV; | |
1da177e4 | 1346 | |
e6b043d5 | 1347 | return phy_ethtool_gset(phydev, cmd); |
1da177e4 LT |
1348 | } |
1349 | ||
c556167f | 1350 | static int fec_enet_set_settings(struct net_device *ndev, |
e6b043d5 | 1351 | struct ethtool_cmd *cmd) |
1da177e4 | 1352 | { |
c556167f | 1353 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1354 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1355 | |
e6b043d5 BW |
1356 | if (!phydev) |
1357 | return -ENODEV; | |
1da177e4 | 1358 | |
e6b043d5 | 1359 | return phy_ethtool_sset(phydev, cmd); |
1da177e4 LT |
1360 | } |
1361 | ||
c556167f | 1362 | static void fec_enet_get_drvinfo(struct net_device *ndev, |
e6b043d5 | 1363 | struct ethtool_drvinfo *info) |
1da177e4 | 1364 | { |
c556167f | 1365 | struct fec_enet_private *fep = netdev_priv(ndev); |
6aa20a22 | 1366 | |
7826d43f JP |
1367 | strlcpy(info->driver, fep->pdev->dev.driver->name, |
1368 | sizeof(info->driver)); | |
1369 | strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); | |
1370 | strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); | |
1da177e4 LT |
1371 | } |
1372 | ||
5ebae489 FL |
1373 | static int fec_enet_get_ts_info(struct net_device *ndev, |
1374 | struct ethtool_ts_info *info) | |
1375 | { | |
1376 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1377 | ||
1378 | if (fep->bufdesc_ex) { | |
1379 | ||
1380 | info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | | |
1381 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
1382 | SOF_TIMESTAMPING_SOFTWARE | | |
1383 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1384 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1385 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
1386 | if (fep->ptp_clock) | |
1387 | info->phc_index = ptp_clock_index(fep->ptp_clock); | |
1388 | else | |
1389 | info->phc_index = -1; | |
1390 | ||
1391 | info->tx_types = (1 << HWTSTAMP_TX_OFF) | | |
1392 | (1 << HWTSTAMP_TX_ON); | |
1393 | ||
1394 | info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | | |
1395 | (1 << HWTSTAMP_FILTER_ALL); | |
1396 | return 0; | |
1397 | } else { | |
1398 | return ethtool_op_get_ts_info(ndev, info); | |
1399 | } | |
1400 | } | |
1401 | ||
baa70a5c FL |
1402 | static void fec_enet_get_pauseparam(struct net_device *ndev, |
1403 | struct ethtool_pauseparam *pause) | |
1404 | { | |
1405 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1406 | ||
1407 | pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; | |
1408 | pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; | |
1409 | pause->rx_pause = pause->tx_pause; | |
1410 | } | |
1411 | ||
1412 | static int fec_enet_set_pauseparam(struct net_device *ndev, | |
1413 | struct ethtool_pauseparam *pause) | |
1414 | { | |
1415 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1416 | ||
1417 | if (pause->tx_pause != pause->rx_pause) { | |
1418 | netdev_info(ndev, | |
1419 | "hardware only support enable/disable both tx and rx"); | |
1420 | return -EINVAL; | |
1421 | } | |
1422 | ||
1423 | fep->pause_flag = 0; | |
1424 | ||
1425 | /* tx pause must be same as rx pause */ | |
1426 | fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; | |
1427 | fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; | |
1428 | ||
1429 | if (pause->rx_pause || pause->autoneg) { | |
1430 | fep->phy_dev->supported |= ADVERTISED_Pause; | |
1431 | fep->phy_dev->advertising |= ADVERTISED_Pause; | |
1432 | } else { | |
1433 | fep->phy_dev->supported &= ~ADVERTISED_Pause; | |
1434 | fep->phy_dev->advertising &= ~ADVERTISED_Pause; | |
1435 | } | |
1436 | ||
1437 | if (pause->autoneg) { | |
1438 | if (netif_running(ndev)) | |
1439 | fec_stop(ndev); | |
1440 | phy_start_aneg(fep->phy_dev); | |
1441 | } | |
1442 | if (netif_running(ndev)) | |
1443 | fec_restart(ndev, 0); | |
1444 | ||
1445 | return 0; | |
1446 | } | |
1447 | ||
38ae92dc CH |
1448 | #ifndef CONFIG_M5272 |
1449 | static const struct fec_stat { | |
1450 | char name[ETH_GSTRING_LEN]; | |
1451 | u16 offset; | |
1452 | } fec_stats[] = { | |
1453 | /* RMON TX */ | |
1454 | { "tx_dropped", RMON_T_DROP }, | |
1455 | { "tx_packets", RMON_T_PACKETS }, | |
1456 | { "tx_broadcast", RMON_T_BC_PKT }, | |
1457 | { "tx_multicast", RMON_T_MC_PKT }, | |
1458 | { "tx_crc_errors", RMON_T_CRC_ALIGN }, | |
1459 | { "tx_undersize", RMON_T_UNDERSIZE }, | |
1460 | { "tx_oversize", RMON_T_OVERSIZE }, | |
1461 | { "tx_fragment", RMON_T_FRAG }, | |
1462 | { "tx_jabber", RMON_T_JAB }, | |
1463 | { "tx_collision", RMON_T_COL }, | |
1464 | { "tx_64byte", RMON_T_P64 }, | |
1465 | { "tx_65to127byte", RMON_T_P65TO127 }, | |
1466 | { "tx_128to255byte", RMON_T_P128TO255 }, | |
1467 | { "tx_256to511byte", RMON_T_P256TO511 }, | |
1468 | { "tx_512to1023byte", RMON_T_P512TO1023 }, | |
1469 | { "tx_1024to2047byte", RMON_T_P1024TO2047 }, | |
1470 | { "tx_GTE2048byte", RMON_T_P_GTE2048 }, | |
1471 | { "tx_octets", RMON_T_OCTETS }, | |
1472 | ||
1473 | /* IEEE TX */ | |
1474 | { "IEEE_tx_drop", IEEE_T_DROP }, | |
1475 | { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, | |
1476 | { "IEEE_tx_1col", IEEE_T_1COL }, | |
1477 | { "IEEE_tx_mcol", IEEE_T_MCOL }, | |
1478 | { "IEEE_tx_def", IEEE_T_DEF }, | |
1479 | { "IEEE_tx_lcol", IEEE_T_LCOL }, | |
1480 | { "IEEE_tx_excol", IEEE_T_EXCOL }, | |
1481 | { "IEEE_tx_macerr", IEEE_T_MACERR }, | |
1482 | { "IEEE_tx_cserr", IEEE_T_CSERR }, | |
1483 | { "IEEE_tx_sqe", IEEE_T_SQE }, | |
1484 | { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, | |
1485 | { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, | |
1486 | ||
1487 | /* RMON RX */ | |
1488 | { "rx_packets", RMON_R_PACKETS }, | |
1489 | { "rx_broadcast", RMON_R_BC_PKT }, | |
1490 | { "rx_multicast", RMON_R_MC_PKT }, | |
1491 | { "rx_crc_errors", RMON_R_CRC_ALIGN }, | |
1492 | { "rx_undersize", RMON_R_UNDERSIZE }, | |
1493 | { "rx_oversize", RMON_R_OVERSIZE }, | |
1494 | { "rx_fragment", RMON_R_FRAG }, | |
1495 | { "rx_jabber", RMON_R_JAB }, | |
1496 | { "rx_64byte", RMON_R_P64 }, | |
1497 | { "rx_65to127byte", RMON_R_P65TO127 }, | |
1498 | { "rx_128to255byte", RMON_R_P128TO255 }, | |
1499 | { "rx_256to511byte", RMON_R_P256TO511 }, | |
1500 | { "rx_512to1023byte", RMON_R_P512TO1023 }, | |
1501 | { "rx_1024to2047byte", RMON_R_P1024TO2047 }, | |
1502 | { "rx_GTE2048byte", RMON_R_P_GTE2048 }, | |
1503 | { "rx_octets", RMON_R_OCTETS }, | |
1504 | ||
1505 | /* IEEE RX */ | |
1506 | { "IEEE_rx_drop", IEEE_R_DROP }, | |
1507 | { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, | |
1508 | { "IEEE_rx_crc", IEEE_R_CRC }, | |
1509 | { "IEEE_rx_align", IEEE_R_ALIGN }, | |
1510 | { "IEEE_rx_macerr", IEEE_R_MACERR }, | |
1511 | { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, | |
1512 | { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, | |
1513 | }; | |
1514 | ||
1515 | static void fec_enet_get_ethtool_stats(struct net_device *dev, | |
1516 | struct ethtool_stats *stats, u64 *data) | |
1517 | { | |
1518 | struct fec_enet_private *fep = netdev_priv(dev); | |
1519 | int i; | |
1520 | ||
1521 | for (i = 0; i < ARRAY_SIZE(fec_stats); i++) | |
1522 | data[i] = readl(fep->hwp + fec_stats[i].offset); | |
1523 | } | |
1524 | ||
1525 | static void fec_enet_get_strings(struct net_device *netdev, | |
1526 | u32 stringset, u8 *data) | |
1527 | { | |
1528 | int i; | |
1529 | switch (stringset) { | |
1530 | case ETH_SS_STATS: | |
1531 | for (i = 0; i < ARRAY_SIZE(fec_stats); i++) | |
1532 | memcpy(data + i * ETH_GSTRING_LEN, | |
1533 | fec_stats[i].name, ETH_GSTRING_LEN); | |
1534 | break; | |
1535 | } | |
1536 | } | |
1537 | ||
1538 | static int fec_enet_get_sset_count(struct net_device *dev, int sset) | |
1539 | { | |
1540 | switch (sset) { | |
1541 | case ETH_SS_STATS: | |
1542 | return ARRAY_SIZE(fec_stats); | |
1543 | default: | |
1544 | return -EOPNOTSUPP; | |
1545 | } | |
1546 | } | |
1547 | #endif | |
1548 | ||
32bc9b46 CH |
1549 | static int fec_enet_nway_reset(struct net_device *dev) |
1550 | { | |
1551 | struct fec_enet_private *fep = netdev_priv(dev); | |
1552 | struct phy_device *phydev = fep->phy_dev; | |
1553 | ||
1554 | if (!phydev) | |
1555 | return -ENODEV; | |
1556 | ||
1557 | return genphy_restart_aneg(phydev); | |
1558 | } | |
1559 | ||
9b07be4b | 1560 | static const struct ethtool_ops fec_enet_ethtool_ops = { |
baa70a5c FL |
1561 | .get_pauseparam = fec_enet_get_pauseparam, |
1562 | .set_pauseparam = fec_enet_set_pauseparam, | |
e6b043d5 BW |
1563 | .get_settings = fec_enet_get_settings, |
1564 | .set_settings = fec_enet_set_settings, | |
1565 | .get_drvinfo = fec_enet_get_drvinfo, | |
1566 | .get_link = ethtool_op_get_link, | |
5ebae489 | 1567 | .get_ts_info = fec_enet_get_ts_info, |
32bc9b46 | 1568 | .nway_reset = fec_enet_nway_reset, |
38ae92dc CH |
1569 | #ifndef CONFIG_M5272 |
1570 | .get_ethtool_stats = fec_enet_get_ethtool_stats, | |
1571 | .get_strings = fec_enet_get_strings, | |
1572 | .get_sset_count = fec_enet_get_sset_count, | |
1573 | #endif | |
e6b043d5 | 1574 | }; |
1da177e4 | 1575 | |
c556167f | 1576 | static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) |
1da177e4 | 1577 | { |
c556167f | 1578 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1579 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1580 | |
c556167f | 1581 | if (!netif_running(ndev)) |
e6b043d5 | 1582 | return -EINVAL; |
1da177e4 | 1583 | |
e6b043d5 BW |
1584 | if (!phydev) |
1585 | return -ENODEV; | |
1586 | ||
ff43da86 | 1587 | if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex) |
6605b730 | 1588 | return fec_ptp_ioctl(ndev, rq, cmd); |
ff43da86 | 1589 | |
28b04113 | 1590 | return phy_mii_ioctl(phydev, rq, cmd); |
1da177e4 LT |
1591 | } |
1592 | ||
c556167f | 1593 | static void fec_enet_free_buffers(struct net_device *ndev) |
f0b3fbea | 1594 | { |
c556167f | 1595 | struct fec_enet_private *fep = netdev_priv(ndev); |
da2191e3 | 1596 | unsigned int i; |
f0b3fbea SH |
1597 | struct sk_buff *skb; |
1598 | struct bufdesc *bdp; | |
1599 | ||
1600 | bdp = fep->rx_bd_base; | |
1601 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1602 | skb = fep->rx_skbuff[i]; | |
1603 | ||
1604 | if (bdp->cbd_bufaddr) | |
d1ab1f54 | 1605 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
f0b3fbea SH |
1606 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1607 | if (skb) | |
1608 | dev_kfree_skb(skb); | |
ff43da86 | 1609 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1610 | } |
1611 | ||
1612 | bdp = fep->tx_bd_base; | |
1613 | for (i = 0; i < TX_RING_SIZE; i++) | |
1614 | kfree(fep->tx_bounce[i]); | |
1615 | } | |
1616 | ||
c556167f | 1617 | static int fec_enet_alloc_buffers(struct net_device *ndev) |
f0b3fbea | 1618 | { |
c556167f | 1619 | struct fec_enet_private *fep = netdev_priv(ndev); |
da2191e3 | 1620 | unsigned int i; |
f0b3fbea SH |
1621 | struct sk_buff *skb; |
1622 | struct bufdesc *bdp; | |
1623 | ||
1624 | bdp = fep->rx_bd_base; | |
1625 | for (i = 0; i < RX_RING_SIZE; i++) { | |
b72061a3 | 1626 | skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); |
f0b3fbea | 1627 | if (!skb) { |
c556167f | 1628 | fec_enet_free_buffers(ndev); |
f0b3fbea SH |
1629 | return -ENOMEM; |
1630 | } | |
1631 | fep->rx_skbuff[i] = skb; | |
1632 | ||
d1ab1f54 | 1633 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, |
f0b3fbea SH |
1634 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1635 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
ff43da86 FL |
1636 | |
1637 | if (fep->bufdesc_ex) { | |
1638 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
1639 | ebdp->cbd_esc = BD_ENET_RX_INT; | |
1640 | } | |
1641 | ||
1642 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
f0b3fbea SH |
1643 | } |
1644 | ||
1645 | /* Set the last buffer to wrap. */ | |
ff43da86 | 1646 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1647 | bdp->cbd_sc |= BD_SC_WRAP; |
1648 | ||
1649 | bdp = fep->tx_bd_base; | |
1650 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1651 | fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); | |
1652 | ||
1653 | bdp->cbd_sc = 0; | |
1654 | bdp->cbd_bufaddr = 0; | |
6605b730 | 1655 | |
ff43da86 FL |
1656 | if (fep->bufdesc_ex) { |
1657 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
96d2222b | 1658 | ebdp->cbd_esc = BD_ENET_TX_INT; |
ff43da86 FL |
1659 | } |
1660 | ||
1661 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
f0b3fbea SH |
1662 | } |
1663 | ||
1664 | /* Set the last buffer to wrap. */ | |
ff43da86 | 1665 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1666 | bdp->cbd_sc |= BD_SC_WRAP; |
1667 | ||
1668 | return 0; | |
1669 | } | |
1670 | ||
1da177e4 | 1671 | static int |
c556167f | 1672 | fec_enet_open(struct net_device *ndev) |
1da177e4 | 1673 | { |
c556167f | 1674 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1675 | int ret; |
1da177e4 | 1676 | |
dc975382 FL |
1677 | napi_enable(&fep->napi); |
1678 | ||
1da177e4 LT |
1679 | /* I should reset the ring buffers here, but I don't yet know |
1680 | * a simple way to do that. | |
1681 | */ | |
1da177e4 | 1682 | |
c556167f | 1683 | ret = fec_enet_alloc_buffers(ndev); |
f0b3fbea SH |
1684 | if (ret) |
1685 | return ret; | |
1686 | ||
418bd0d4 | 1687 | /* Probe and connect to PHY when open the interface */ |
c556167f | 1688 | ret = fec_enet_mii_probe(ndev); |
418bd0d4 | 1689 | if (ret) { |
c556167f | 1690 | fec_enet_free_buffers(ndev); |
418bd0d4 BW |
1691 | return ret; |
1692 | } | |
e6b043d5 | 1693 | phy_start(fep->phy_dev); |
c556167f | 1694 | netif_start_queue(ndev); |
1da177e4 | 1695 | fep->opened = 1; |
22f6b860 | 1696 | return 0; |
1da177e4 LT |
1697 | } |
1698 | ||
1699 | static int | |
c556167f | 1700 | fec_enet_close(struct net_device *ndev) |
1da177e4 | 1701 | { |
c556167f | 1702 | struct fec_enet_private *fep = netdev_priv(ndev); |
1da177e4 | 1703 | |
22f6b860 | 1704 | /* Don't know what to do yet. */ |
3f104c38 | 1705 | napi_disable(&fep->napi); |
1da177e4 | 1706 | fep->opened = 0; |
c556167f UKK |
1707 | netif_stop_queue(ndev); |
1708 | fec_stop(ndev); | |
1da177e4 | 1709 | |
e497ba82 UKK |
1710 | if (fep->phy_dev) { |
1711 | phy_stop(fep->phy_dev); | |
418bd0d4 | 1712 | phy_disconnect(fep->phy_dev); |
e497ba82 | 1713 | } |
418bd0d4 | 1714 | |
db8880bc | 1715 | fec_enet_free_buffers(ndev); |
f0b3fbea | 1716 | |
1da177e4 LT |
1717 | return 0; |
1718 | } | |
1719 | ||
1da177e4 LT |
1720 | /* Set or clear the multicast filter for this adaptor. |
1721 | * Skeleton taken from sunlance driver. | |
1722 | * The CPM Ethernet implementation allows Multicast as well as individual | |
1723 | * MAC address filtering. Some of the drivers check to make sure it is | |
1724 | * a group multicast address, and discard those that are not. I guess I | |
1725 | * will do the same for now, but just remove the test if you want | |
1726 | * individual filtering as well (do the upper net layers want or support | |
1727 | * this kind of feature?). | |
1728 | */ | |
1729 | ||
1730 | #define HASH_BITS 6 /* #bits in hash */ | |
1731 | #define CRC32_POLY 0xEDB88320 | |
1732 | ||
c556167f | 1733 | static void set_multicast_list(struct net_device *ndev) |
1da177e4 | 1734 | { |
c556167f | 1735 | struct fec_enet_private *fep = netdev_priv(ndev); |
22bedad3 | 1736 | struct netdev_hw_addr *ha; |
48e2f183 | 1737 | unsigned int i, bit, data, crc, tmp; |
1da177e4 LT |
1738 | unsigned char hash; |
1739 | ||
c556167f | 1740 | if (ndev->flags & IFF_PROMISC) { |
f44d6305 SH |
1741 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1742 | tmp |= 0x8; | |
1743 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
4e831836 SH |
1744 | return; |
1745 | } | |
1da177e4 | 1746 | |
4e831836 SH |
1747 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1748 | tmp &= ~0x8; | |
1749 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
1750 | ||
c556167f | 1751 | if (ndev->flags & IFF_ALLMULTI) { |
4e831836 SH |
1752 | /* Catch all multicast addresses, so set the |
1753 | * filter to all 1's | |
1754 | */ | |
1755 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1756 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1757 | ||
1758 | return; | |
1759 | } | |
1760 | ||
1761 | /* Clear filter and add the addresses in hash register | |
1762 | */ | |
1763 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1764 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1765 | ||
c556167f | 1766 | netdev_for_each_mc_addr(ha, ndev) { |
4e831836 SH |
1767 | /* calculate crc32 value of mac address */ |
1768 | crc = 0xffffffff; | |
1769 | ||
c556167f | 1770 | for (i = 0; i < ndev->addr_len; i++) { |
22bedad3 | 1771 | data = ha->addr[i]; |
4e831836 SH |
1772 | for (bit = 0; bit < 8; bit++, data >>= 1) { |
1773 | crc = (crc >> 1) ^ | |
1774 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1da177e4 LT |
1775 | } |
1776 | } | |
4e831836 SH |
1777 | |
1778 | /* only upper 6 bits (HASH_BITS) are used | |
1779 | * which point to specific bit in he hash registers | |
1780 | */ | |
1781 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
1782 | ||
1783 | if (hash > 31) { | |
1784 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1785 | tmp |= 1 << (hash - 32); | |
1786 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1787 | } else { | |
1788 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1789 | tmp |= 1 << hash; | |
1790 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1791 | } | |
1da177e4 LT |
1792 | } |
1793 | } | |
1794 | ||
22f6b860 | 1795 | /* Set a MAC change in hardware. */ |
009fda83 | 1796 | static int |
c556167f | 1797 | fec_set_mac_address(struct net_device *ndev, void *p) |
1da177e4 | 1798 | { |
c556167f | 1799 | struct fec_enet_private *fep = netdev_priv(ndev); |
009fda83 SH |
1800 | struct sockaddr *addr = p; |
1801 | ||
1802 | if (!is_valid_ether_addr(addr->sa_data)) | |
1803 | return -EADDRNOTAVAIL; | |
1804 | ||
c556167f | 1805 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); |
1da177e4 | 1806 | |
c556167f UKK |
1807 | writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | |
1808 | (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), | |
f44d6305 | 1809 | fep->hwp + FEC_ADDR_LOW); |
c556167f | 1810 | writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), |
7cff0943 | 1811 | fep->hwp + FEC_ADDR_HIGH); |
009fda83 | 1812 | return 0; |
1da177e4 LT |
1813 | } |
1814 | ||
7f5c6add | 1815 | #ifdef CONFIG_NET_POLL_CONTROLLER |
49ce9c2c BH |
1816 | /** |
1817 | * fec_poll_controller - FEC Poll controller function | |
7f5c6add XJ |
1818 | * @dev: The FEC network adapter |
1819 | * | |
1820 | * Polled functionality used by netconsole and others in non interrupt mode | |
1821 | * | |
1822 | */ | |
47a5247f | 1823 | static void fec_poll_controller(struct net_device *dev) |
7f5c6add XJ |
1824 | { |
1825 | int i; | |
1826 | struct fec_enet_private *fep = netdev_priv(dev); | |
1827 | ||
1828 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
1829 | if (fep->irq[i] > 0) { | |
1830 | disable_irq(fep->irq[i]); | |
1831 | fec_enet_interrupt(fep->irq[i], dev); | |
1832 | enable_irq(fep->irq[i]); | |
1833 | } | |
1834 | } | |
1835 | } | |
1836 | #endif | |
1837 | ||
4c09eed9 JB |
1838 | static int fec_set_features(struct net_device *netdev, |
1839 | netdev_features_t features) | |
1840 | { | |
1841 | struct fec_enet_private *fep = netdev_priv(netdev); | |
1842 | netdev_features_t changed = features ^ netdev->features; | |
1843 | ||
1844 | netdev->features = features; | |
1845 | ||
1846 | /* Receive checksum has been changed */ | |
1847 | if (changed & NETIF_F_RXCSUM) { | |
1848 | if (features & NETIF_F_RXCSUM) | |
1849 | fep->csum_flags |= FLAG_RX_CSUM_ENABLED; | |
1850 | else | |
1851 | fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; | |
1852 | ||
1853 | if (netif_running(netdev)) { | |
1854 | fec_stop(netdev); | |
1855 | fec_restart(netdev, fep->phy_dev->duplex); | |
1856 | netif_wake_queue(netdev); | |
1857 | } else { | |
1858 | fec_restart(netdev, fep->phy_dev->duplex); | |
1859 | } | |
1860 | } | |
1861 | ||
1862 | return 0; | |
1863 | } | |
1864 | ||
009fda83 SH |
1865 | static const struct net_device_ops fec_netdev_ops = { |
1866 | .ndo_open = fec_enet_open, | |
1867 | .ndo_stop = fec_enet_close, | |
1868 | .ndo_start_xmit = fec_enet_start_xmit, | |
afc4b13d | 1869 | .ndo_set_rx_mode = set_multicast_list, |
635ecaa7 | 1870 | .ndo_change_mtu = eth_change_mtu, |
009fda83 SH |
1871 | .ndo_validate_addr = eth_validate_addr, |
1872 | .ndo_tx_timeout = fec_timeout, | |
1873 | .ndo_set_mac_address = fec_set_mac_address, | |
db8880bc | 1874 | .ndo_do_ioctl = fec_enet_ioctl, |
7f5c6add XJ |
1875 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1876 | .ndo_poll_controller = fec_poll_controller, | |
1877 | #endif | |
4c09eed9 | 1878 | .ndo_set_features = fec_set_features, |
009fda83 SH |
1879 | }; |
1880 | ||
1da177e4 LT |
1881 | /* |
1882 | * XXX: We need to clean up on failure exits here. | |
ead73183 | 1883 | * |
1da177e4 | 1884 | */ |
c556167f | 1885 | static int fec_enet_init(struct net_device *ndev) |
1da177e4 | 1886 | { |
c556167f | 1887 | struct fec_enet_private *fep = netdev_priv(ndev); |
48496255 SG |
1888 | const struct platform_device_id *id_entry = |
1889 | platform_get_device_id(fep->pdev); | |
f0b3fbea | 1890 | struct bufdesc *cbd_base; |
1da177e4 | 1891 | |
8d4dd5cf SH |
1892 | /* Allocate memory for buffer descriptors. */ |
1893 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, | |
d0320f75 JP |
1894 | GFP_KERNEL); |
1895 | if (!cbd_base) | |
562d2f8c | 1896 | return -ENOMEM; |
562d2f8c | 1897 | |
14109a59 | 1898 | memset(cbd_base, 0, PAGE_SIZE); |
3b2b74ca | 1899 | |
c556167f | 1900 | fep->netdev = ndev; |
1da177e4 | 1901 | |
49da97dc | 1902 | /* Get the Ethernet address */ |
c556167f | 1903 | fec_get_mac(ndev); |
1da177e4 | 1904 | |
8d4dd5cf | 1905 | /* Set receive and transmit descriptor base. */ |
1da177e4 | 1906 | fep->rx_bd_base = cbd_base; |
ff43da86 FL |
1907 | if (fep->bufdesc_ex) |
1908 | fep->tx_bd_base = (struct bufdesc *) | |
1909 | (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE); | |
1910 | else | |
1911 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
1da177e4 | 1912 | |
22f6b860 | 1913 | /* The FEC Ethernet specific entries in the device structure */ |
c556167f UKK |
1914 | ndev->watchdog_timeo = TX_TIMEOUT; |
1915 | ndev->netdev_ops = &fec_netdev_ops; | |
1916 | ndev->ethtool_ops = &fec_enet_ethtool_ops; | |
633e7533 | 1917 | |
dc975382 FL |
1918 | writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); |
1919 | netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT); | |
1920 | ||
48496255 SG |
1921 | if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) { |
1922 | /* enable hw accelerator */ | |
1923 | ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
1924 | | NETIF_F_RXCSUM); | |
1925 | ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
1926 | | NETIF_F_RXCSUM); | |
1927 | fep->csum_flags |= FLAG_RX_CSUM_ENABLED; | |
1928 | } | |
4c09eed9 | 1929 | |
c556167f | 1930 | fec_restart(ndev, 0); |
1da177e4 | 1931 | |
1da177e4 LT |
1932 | return 0; |
1933 | } | |
1934 | ||
ca2cc333 | 1935 | #ifdef CONFIG_OF |
33897cc8 | 1936 | static void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
1937 | { |
1938 | int err, phy_reset; | |
a3caad0a | 1939 | int msec = 1; |
ca2cc333 SG |
1940 | struct device_node *np = pdev->dev.of_node; |
1941 | ||
1942 | if (!np) | |
a9b2c8ef | 1943 | return; |
ca2cc333 | 1944 | |
a3caad0a SG |
1945 | of_property_read_u32(np, "phy-reset-duration", &msec); |
1946 | /* A sane reset duration should not be longer than 1s */ | |
1947 | if (msec > 1000) | |
1948 | msec = 1; | |
1949 | ||
ca2cc333 | 1950 | phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); |
07dcf8e9 FE |
1951 | if (!gpio_is_valid(phy_reset)) |
1952 | return; | |
1953 | ||
119fc007 SG |
1954 | err = devm_gpio_request_one(&pdev->dev, phy_reset, |
1955 | GPIOF_OUT_INIT_LOW, "phy-reset"); | |
ca2cc333 | 1956 | if (err) { |
07dcf8e9 | 1957 | dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); |
a9b2c8ef | 1958 | return; |
ca2cc333 | 1959 | } |
a3caad0a | 1960 | msleep(msec); |
ca2cc333 | 1961 | gpio_set_value(phy_reset, 1); |
ca2cc333 SG |
1962 | } |
1963 | #else /* CONFIG_OF */ | |
0c7768a0 | 1964 | static void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
1965 | { |
1966 | /* | |
1967 | * In case of platform probe, the reset has been done | |
1968 | * by machine code. | |
1969 | */ | |
ca2cc333 SG |
1970 | } |
1971 | #endif /* CONFIG_OF */ | |
1972 | ||
33897cc8 | 1973 | static int |
ead73183 SH |
1974 | fec_probe(struct platform_device *pdev) |
1975 | { | |
1976 | struct fec_enet_private *fep; | |
5eb32bd0 | 1977 | struct fec_platform_data *pdata; |
ead73183 SH |
1978 | struct net_device *ndev; |
1979 | int i, irq, ret = 0; | |
1980 | struct resource *r; | |
ca2cc333 | 1981 | const struct of_device_id *of_id; |
43af940c | 1982 | static int dev_id; |
ca2cc333 SG |
1983 | |
1984 | of_id = of_match_device(fec_dt_ids, &pdev->dev); | |
1985 | if (of_id) | |
1986 | pdev->id_entry = of_id->data; | |
ead73183 SH |
1987 | |
1988 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1989 | if (!r) | |
1990 | return -ENXIO; | |
1991 | ||
ead73183 SH |
1992 | /* Init network device */ |
1993 | ndev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
83e519b6 FE |
1994 | if (!ndev) |
1995 | return -ENOMEM; | |
ead73183 SH |
1996 | |
1997 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1998 | ||
1999 | /* setup board info structure */ | |
2000 | fep = netdev_priv(ndev); | |
ead73183 | 2001 | |
baa70a5c FL |
2002 | /* default enable pause frame auto negotiation */ |
2003 | if (pdev->id_entry && | |
2004 | (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT)) | |
2005 | fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; | |
2006 | ||
941e173a TB |
2007 | fep->hwp = devm_ioremap_resource(&pdev->dev, r); |
2008 | if (IS_ERR(fep->hwp)) { | |
2009 | ret = PTR_ERR(fep->hwp); | |
2010 | goto failed_ioremap; | |
2011 | } | |
2012 | ||
e6b043d5 | 2013 | fep->pdev = pdev; |
43af940c | 2014 | fep->dev_id = dev_id++; |
ead73183 | 2015 | |
ff43da86 FL |
2016 | fep->bufdesc_ex = 0; |
2017 | ||
ead73183 SH |
2018 | platform_set_drvdata(pdev, ndev); |
2019 | ||
6c5f7808 | 2020 | ret = of_get_phy_mode(pdev->dev.of_node); |
ca2cc333 SG |
2021 | if (ret < 0) { |
2022 | pdata = pdev->dev.platform_data; | |
2023 | if (pdata) | |
2024 | fep->phy_interface = pdata->phy; | |
2025 | else | |
2026 | fep->phy_interface = PHY_INTERFACE_MODE_MII; | |
2027 | } else { | |
2028 | fep->phy_interface = ret; | |
2029 | } | |
2030 | ||
f4d40de3 SH |
2031 | fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
2032 | if (IS_ERR(fep->clk_ipg)) { | |
2033 | ret = PTR_ERR(fep->clk_ipg); | |
ead73183 SH |
2034 | goto failed_clk; |
2035 | } | |
f4d40de3 SH |
2036 | |
2037 | fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
2038 | if (IS_ERR(fep->clk_ahb)) { | |
2039 | ret = PTR_ERR(fep->clk_ahb); | |
2040 | goto failed_clk; | |
2041 | } | |
2042 | ||
daa7d392 WS |
2043 | /* enet_out is optional, depends on board */ |
2044 | fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); | |
2045 | if (IS_ERR(fep->clk_enet_out)) | |
2046 | fep->clk_enet_out = NULL; | |
2047 | ||
6605b730 | 2048 | fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); |
e2f8d555 FE |
2049 | fep->bufdesc_ex = |
2050 | pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX; | |
6605b730 | 2051 | if (IS_ERR(fep->clk_ptp)) { |
c29dc2d7 | 2052 | fep->clk_ptp = NULL; |
ff43da86 | 2053 | fep->bufdesc_ex = 0; |
6605b730 | 2054 | } |
6605b730 | 2055 | |
f4d40de3 SH |
2056 | clk_prepare_enable(fep->clk_ahb); |
2057 | clk_prepare_enable(fep->clk_ipg); | |
daa7d392 | 2058 | clk_prepare_enable(fep->clk_enet_out); |
c29dc2d7 | 2059 | clk_prepare_enable(fep->clk_ptp); |
ff43da86 | 2060 | |
f4e9f3d2 FE |
2061 | fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); |
2062 | if (!IS_ERR(fep->reg_phy)) { | |
2063 | ret = regulator_enable(fep->reg_phy); | |
5fa9c0fe SG |
2064 | if (ret) { |
2065 | dev_err(&pdev->dev, | |
2066 | "Failed to enable phy regulator: %d\n", ret); | |
2067 | goto failed_regulator; | |
2068 | } | |
f6a4d607 FE |
2069 | } else { |
2070 | fep->reg_phy = NULL; | |
5fa9c0fe SG |
2071 | } |
2072 | ||
2ca9b2aa SG |
2073 | fec_reset_phy(pdev); |
2074 | ||
e2f8d555 | 2075 | if (fep->bufdesc_ex) |
ca162a82 | 2076 | fec_ptp_init(pdev); |
e2f8d555 FE |
2077 | |
2078 | ret = fec_enet_init(ndev); | |
2079 | if (ret) | |
2080 | goto failed_init; | |
2081 | ||
2082 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
2083 | irq = platform_get_irq(pdev, i); | |
2084 | if (irq < 0) { | |
2085 | if (i) | |
2086 | break; | |
2087 | ret = irq; | |
2088 | goto failed_irq; | |
2089 | } | |
2090 | ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); | |
2091 | if (ret) { | |
2092 | while (--i >= 0) { | |
2093 | irq = platform_get_irq(pdev, i); | |
2094 | free_irq(irq, ndev); | |
2095 | } | |
2096 | goto failed_irq; | |
2097 | } | |
2098 | } | |
2099 | ||
e6b043d5 BW |
2100 | ret = fec_enet_mii_init(pdev); |
2101 | if (ret) | |
2102 | goto failed_mii_init; | |
2103 | ||
03c698c9 OS |
2104 | /* Carrier starts down, phylib will bring it up */ |
2105 | netif_carrier_off(ndev); | |
2106 | ||
ead73183 SH |
2107 | ret = register_netdev(ndev); |
2108 | if (ret) | |
2109 | goto failed_register; | |
2110 | ||
eb1d0640 FE |
2111 | if (fep->bufdesc_ex && fep->ptp_clock) |
2112 | netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); | |
2113 | ||
54309fa6 | 2114 | INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work); |
ead73183 SH |
2115 | return 0; |
2116 | ||
2117 | failed_register: | |
e6b043d5 BW |
2118 | fec_enet_mii_remove(fep); |
2119 | failed_mii_init: | |
7a2bbd8d | 2120 | failed_irq: |
e2f8d555 FE |
2121 | for (i = 0; i < FEC_IRQ_NUM; i++) { |
2122 | irq = platform_get_irq(pdev, i); | |
2123 | if (irq > 0) | |
2124 | free_irq(irq, ndev); | |
2125 | } | |
7a2bbd8d | 2126 | failed_init: |
f6a4d607 FE |
2127 | if (fep->reg_phy) |
2128 | regulator_disable(fep->reg_phy); | |
5fa9c0fe | 2129 | failed_regulator: |
f4d40de3 SH |
2130 | clk_disable_unprepare(fep->clk_ahb); |
2131 | clk_disable_unprepare(fep->clk_ipg); | |
daa7d392 | 2132 | clk_disable_unprepare(fep->clk_enet_out); |
c29dc2d7 | 2133 | clk_disable_unprepare(fep->clk_ptp); |
ead73183 | 2134 | failed_clk: |
ead73183 SH |
2135 | failed_ioremap: |
2136 | free_netdev(ndev); | |
2137 | ||
2138 | return ret; | |
2139 | } | |
2140 | ||
33897cc8 | 2141 | static int |
ead73183 SH |
2142 | fec_drv_remove(struct platform_device *pdev) |
2143 | { | |
2144 | struct net_device *ndev = platform_get_drvdata(pdev); | |
2145 | struct fec_enet_private *fep = netdev_priv(ndev); | |
e163cc97 | 2146 | int i; |
ead73183 | 2147 | |
54309fa6 | 2148 | cancel_delayed_work_sync(&(fep->delay_work.delay_work)); |
e163cc97 | 2149 | unregister_netdev(ndev); |
e6b043d5 | 2150 | fec_enet_mii_remove(fep); |
6605b730 | 2151 | del_timer_sync(&fep->time_keep); |
c55284e4 FE |
2152 | for (i = 0; i < FEC_IRQ_NUM; i++) { |
2153 | int irq = platform_get_irq(pdev, i); | |
2154 | if (irq > 0) | |
2155 | free_irq(irq, ndev); | |
2156 | } | |
f6a4d607 FE |
2157 | if (fep->reg_phy) |
2158 | regulator_disable(fep->reg_phy); | |
6605b730 FL |
2159 | clk_disable_unprepare(fep->clk_ptp); |
2160 | if (fep->ptp_clock) | |
2161 | ptp_clock_unregister(fep->ptp_clock); | |
daa7d392 | 2162 | clk_disable_unprepare(fep->clk_enet_out); |
f4d40de3 SH |
2163 | clk_disable_unprepare(fep->clk_ahb); |
2164 | clk_disable_unprepare(fep->clk_ipg); | |
ead73183 | 2165 | free_netdev(ndev); |
28e2188e | 2166 | |
ead73183 SH |
2167 | return 0; |
2168 | } | |
2169 | ||
bf7bfd7f | 2170 | #ifdef CONFIG_PM_SLEEP |
ead73183 | 2171 | static int |
87cad5c3 | 2172 | fec_suspend(struct device *dev) |
ead73183 | 2173 | { |
87cad5c3 | 2174 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 2175 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 2176 | |
04e5216d UKK |
2177 | if (netif_running(ndev)) { |
2178 | fec_stop(ndev); | |
2179 | netif_device_detach(ndev); | |
ead73183 | 2180 | } |
daa7d392 | 2181 | clk_disable_unprepare(fep->clk_enet_out); |
f4d40de3 SH |
2182 | clk_disable_unprepare(fep->clk_ahb); |
2183 | clk_disable_unprepare(fep->clk_ipg); | |
04e5216d | 2184 | |
238f7bc7 FE |
2185 | if (fep->reg_phy) |
2186 | regulator_disable(fep->reg_phy); | |
2187 | ||
ead73183 SH |
2188 | return 0; |
2189 | } | |
2190 | ||
2191 | static int | |
87cad5c3 | 2192 | fec_resume(struct device *dev) |
ead73183 | 2193 | { |
87cad5c3 | 2194 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 2195 | struct fec_enet_private *fep = netdev_priv(ndev); |
238f7bc7 FE |
2196 | int ret; |
2197 | ||
2198 | if (fep->reg_phy) { | |
2199 | ret = regulator_enable(fep->reg_phy); | |
2200 | if (ret) | |
2201 | return ret; | |
2202 | } | |
ead73183 | 2203 | |
daa7d392 | 2204 | clk_prepare_enable(fep->clk_enet_out); |
f4d40de3 SH |
2205 | clk_prepare_enable(fep->clk_ahb); |
2206 | clk_prepare_enable(fep->clk_ipg); | |
04e5216d UKK |
2207 | if (netif_running(ndev)) { |
2208 | fec_restart(ndev, fep->full_duplex); | |
2209 | netif_device_attach(ndev); | |
ead73183 | 2210 | } |
04e5216d | 2211 | |
ead73183 SH |
2212 | return 0; |
2213 | } | |
bf7bfd7f | 2214 | #endif /* CONFIG_PM_SLEEP */ |
ead73183 | 2215 | |
bf7bfd7f | 2216 | static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume); |
59d4289b | 2217 | |
ead73183 SH |
2218 | static struct platform_driver fec_driver = { |
2219 | .driver = { | |
b5680e0b | 2220 | .name = DRIVER_NAME, |
87cad5c3 | 2221 | .owner = THIS_MODULE, |
87cad5c3 | 2222 | .pm = &fec_pm_ops, |
ca2cc333 | 2223 | .of_match_table = fec_dt_ids, |
ead73183 | 2224 | }, |
b5680e0b | 2225 | .id_table = fec_devtype, |
87cad5c3 | 2226 | .probe = fec_probe, |
33897cc8 | 2227 | .remove = fec_drv_remove, |
ead73183 SH |
2228 | }; |
2229 | ||
aaca2377 | 2230 | module_platform_driver(fec_driver); |
1da177e4 LT |
2231 | |
2232 | MODULE_LICENSE("GPL"); |