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net: fec: only restart or stop the device if it is present and running
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / freescale / fec_main.c
CommitLineData
1da177e4
LT		 1/*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
7dd6a2aa 5 * Right now, I am very wasteful with the buffers. I allocate memory
1da177e4
LT		 6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
562d2f8c
GU		 15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
7dd6a2aa
GU		 17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
677177c5 19 * Copyright (c) 2004-2006 Macq Electronique SA.
b5680e0b 20 *
230dec61 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
1da177e4
LT		 22 */
23
1da177e4
LT		 24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/string.h>
27#include <linux/ptrace.h>
28#include <linux/errno.h>
29#include <linux/ioport.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
1da177e4
LT		 32#include <linux/delay.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/skbuff.h>
4c09eed9
JB		 36#include <linux/in.h>
37#include <linux/ip.h>
38#include <net/ip.h>
79f33912 39#include <net/tso.h>
4c09eed9
JB		 40#include <linux/tcp.h>
41#include <linux/udp.h>
42#include <linux/icmp.h>
1da177e4
LT		 43#include <linux/spinlock.h>
44#include <linux/workqueue.h>
45#include <linux/bitops.h>
6f501b17
SH		 46#include <linux/io.h>
47#include <linux/irq.h>
196719ec 48#include <linux/clk.h>
ead73183 49#include <linux/platform_device.h>
e6b043d5 50#include <linux/phy.h>
5eb32bd0 51#include <linux/fec.h>
ca2cc333
SG		 52#include <linux/of.h>
53#include <linux/of_device.h>
54#include <linux/of_gpio.h>
55#include <linux/of_net.h>
5fa9c0fe 56#include <linux/regulator/consumer.h>
cdffcf1b 57#include <linux/if_vlan.h>
a68ab98e 58#include <linux/pinctrl/consumer.h>
1da177e4 59
080853af 60#include <asm/cacheflush.h>
196719ec 61
1da177e4 62#include "fec.h"
1da177e4 63
772e42b0
CM		 64static void set_multicast_list(struct net_device *ndev);
65
085e79ed 66#if defined(CONFIG_ARM)
196719ec
SH		 67#define FEC_ALIGNMENT 0xf
68#else
69#define FEC_ALIGNMENT 0x3
70#endif
71
b5680e0b
SG		 72#define DRIVER_NAME "fec"
73
baa70a5c
FL		 74/* Pause frame feild and FIFO threshold */
75#define FEC_ENET_FCE (1 << 5)
76#define FEC_ENET_RSEM_V 0x84
77#define FEC_ENET_RSFL_V 16
78#define FEC_ENET_RAEM_V 0x8
79#define FEC_ENET_RAFL_V 0x8
80#define FEC_ENET_OPD_V 0xFFF0
81
b5680e0b
SG		 82/* Controller is ENET-MAC */
83#define FEC_QUIRK_ENET_MAC (1 << 0)
84/* Controller needs driver to swap frame */
85#define FEC_QUIRK_SWAP_FRAME (1 << 1)
0ca1e290
SG		 86/* Controller uses gasket */
87#define FEC_QUIRK_USE_GASKET (1 << 2)
230dec61
SG		 88/* Controller has GBIT support */
89#define FEC_QUIRK_HAS_GBIT (1 << 3)
ff43da86
FL		 90/* Controller has extend desc buffer */
91#define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
48496255
SG		 92/* Controller has hardware checksum support */
93#define FEC_QUIRK_HAS_CSUM (1 << 5)
cdffcf1b
JB		 94/* Controller has hardware vlan support */
95#define FEC_QUIRK_HAS_VLAN (1 << 6)
03191656
FL		 96/* ENET IP errata ERR006358
97 *
98 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
99 * detected as not set during a prior frame transmission, then the
100 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
101 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
03191656
FL		 102 * frames not being transmitted until there is a 0-to-1 transition on
103 * ENET_TDAR[TDAR].
104 */
105#define FEC_QUIRK_ERR006358 (1 << 7)
b5680e0b
SG		 106
107static struct platform_device_id fec_devtype[] = {
108 {
0ca1e290 109 /* keep it for coldfire */
b5680e0b
SG		 110 .name = DRIVER_NAME,
111 .driver_data = 0,
0ca1e290
SG		 112 }, {
113 .name = "imx25-fec",
114 .driver_data = FEC_QUIRK_USE_GASKET,
115 }, {
116 .name = "imx27-fec",
117 .driver_data = 0,
b5680e0b
SG		 118 }, {
119 .name = "imx28-fec",
120 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
230dec61
SG		 121 }, {
122 .name = "imx6q-fec",
ff43da86 123 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
cdffcf1b 124 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
03191656 125 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
ca7c4a45 126 }, {
36803542 127 .name = "mvf600-fec",
ca7c4a45 128 .driver_data = FEC_QUIRK_ENET_MAC,
0ca1e290
SG		 129 }, {
130 /* sentinel */
131 }
b5680e0b 132};
0ca1e290 133MODULE_DEVICE_TABLE(platform, fec_devtype);
b5680e0b 134
ca2cc333 135enum imx_fec_type {
a7dd3219 136 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
ca2cc333
SG		 137 IMX27_FEC, /* runs on i.mx27/35/51 */
138 IMX28_FEC,
230dec61 139 IMX6Q_FEC,
36803542 140 MVF600_FEC,
ca2cc333
SG		 141};
142
143static const struct of_device_id fec_dt_ids[] = {
144 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
145 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
146 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
230dec61 147 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
36803542 148 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
ca2cc333
SG		 149 { /* sentinel */ }
150};
151MODULE_DEVICE_TABLE(of, fec_dt_ids);
152
49da97dc
SG		 153static unsigned char macaddr[ETH_ALEN];
154module_param_array(macaddr, byte, NULL, 0);
155MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
1da177e4 156
49da97dc 157#if defined(CONFIG_M5272)
1da177e4
LT		 158/*
159 * Some hardware gets it MAC address out of local flash memory.
160 * if this is non-zero then assume it is the address to get MAC from.
161 */
162#if defined(CONFIG_NETtel)
163#define FEC_FLASHMAC 0xf0006006
164#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
165#define FEC_FLASHMAC 0xf0006000
1da177e4
LT		 166#elif defined(CONFIG_CANCam)
167#define FEC_FLASHMAC 0xf0020000
7dd6a2aa
GU		 168#elif defined (CONFIG_M5272C3)
169#define FEC_FLASHMAC (0xffe04000 + 4)
170#elif defined(CONFIG_MOD5272)
a7dd3219 171#define FEC_FLASHMAC 0xffc0406b
1da177e4
LT		 172#else
173#define FEC_FLASHMAC 0
174#endif
43be6366 175#endif /* CONFIG_M5272 */
ead73183 176
22f6b860 177/* Interrupt events/masks. */
1da177e4
LT		 178#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
179#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
180#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
181#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
182#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
183#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
184#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
185#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
186#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
187#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
188
4bee1f9a 189#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
dc975382 190#define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
4bee1f9a 191
cdffcf1b 192/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
1da177e4 193 */
cdffcf1b 194#define PKT_MAXBUF_SIZE 1522
1da177e4 195#define PKT_MINBUF_SIZE 64
cdffcf1b 196#define PKT_MAXBLR_SIZE 1536
1da177e4 197
4c09eed9
JB		 198/* FEC receive acceleration */
199#define FEC_RACC_IPDIS (1 << 1)
200#define FEC_RACC_PRODIS (1 << 2)
201#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
202
1da177e4 203/*
6b265293 204 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
1da177e4
LT		 205 * size bits. Other FEC hardware does not, so we need to take that into
206 * account when setting it.
207 */
562d2f8c 208#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
085e79ed 209 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
1da177e4
LT		 210#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
211#else
212#define OPT_FRAME_SIZE 0
213#endif
214
e6b043d5
BW		 215/* FEC MII MMFR bits definition */
216#define FEC_MMFR_ST (1 << 30)
217#define FEC_MMFR_OP_READ (2 << 28)
218#define FEC_MMFR_OP_WRITE (1 << 28)
219#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
220#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
221#define FEC_MMFR_TA (2 << 16)
222#define FEC_MMFR_DATA(v) (v & 0xffff)
1da177e4 223
c3b084c2 224#define FEC_MII_TIMEOUT 30000 /* us */
1da177e4 225
22f6b860
SH		 226/* Transmitter timeout */
227#define TX_TIMEOUT (2 * HZ)
1da177e4 228
baa70a5c
FL		 229#define FEC_PAUSE_FLAG_AUTONEG 0x1
230#define FEC_PAUSE_FLAG_ENABLE 0x2
231
79f33912
NA		 232#define TSO_HEADER_SIZE 128
233/* Max number of allowed TCP segments for software TSO */
234#define FEC_MAX_TSO_SEGS 100
235#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
236
237#define IS_TSO_HEADER(txq, addr) \
238 ((addr >= txq->tso_hdrs_dma) && \
239 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
240
e163cc97
LW		 241static int mii_cnt;
242
36e24e2e
DFB		 243static inline
244struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
ff43da86 245{
36e24e2e
DFB		 246 struct bufdesc *new_bd = bdp + 1;
247 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
248 struct bufdesc_ex *ex_base;
249 struct bufdesc *base;
250 int ring_size;
251
252 if (bdp >= fep->tx_bd_base) {
253 base = fep->tx_bd_base;
254 ring_size = fep->tx_ring_size;
255 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
256 } else {
257 base = fep->rx_bd_base;
258 ring_size = fep->rx_ring_size;
259 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
260 }
261
262 if (fep->bufdesc_ex)
263 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
264 ex_base : ex_new_bd);
ff43da86 265 else
36e24e2e
DFB		 266 return (new_bd >= (base + ring_size)) ?
267 base : new_bd;
ff43da86
FL		 268}
269
36e24e2e
DFB		 270static inline
271struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
ff43da86 272{
36e24e2e
DFB		 273 struct bufdesc *new_bd = bdp - 1;
274 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
275 struct bufdesc_ex *ex_base;
276 struct bufdesc *base;
277 int ring_size;
278
279 if (bdp >= fep->tx_bd_base) {
280 base = fep->tx_bd_base;
281 ring_size = fep->tx_ring_size;
282 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
283 } else {
284 base = fep->rx_bd_base;
285 ring_size = fep->rx_ring_size;
286 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
287 }
288
289 if (fep->bufdesc_ex)
290 return (struct bufdesc *)((ex_new_bd < ex_base) ?
291 (ex_new_bd + ring_size) : ex_new_bd);
ff43da86 292 else
36e24e2e 293 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
ff43da86
FL		 294}
295
61a4427b
NA		 296static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
297 struct fec_enet_private *fep)
298{
299 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
300}
301
6e909283
NA		 302static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep)
303{
304 int entries;
305
306 entries = ((const char *)fep->dirty_tx -
307 (const char *)fep->cur_tx) / fep->bufdesc_size - 1;
308
309 return entries > 0 ? entries : entries + fep->tx_ring_size;
310}
311
b5680e0b
SG		 312static void *swap_buffer(void *bufaddr, int len)
313{
314 int i;
315 unsigned int *buf = bufaddr;
316
ffed61e6 317 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
b5680e0b
SG		 318 *buf = cpu_to_be32(*buf);
319
320 return bufaddr;
321}
322
62a02c98
FD		 323static inline bool is_ipv4_pkt(struct sk_buff *skb)
324{
325 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
326}
327
4c09eed9
JB		 328static int
329fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
330{
331 /* Only run for packets requiring a checksum. */
332 if (skb->ip_summed != CHECKSUM_PARTIAL)
333 return 0;
334
335 if (unlikely(skb_cow_head(skb, 0)))
336 return -1;
337
62a02c98
FD		 338 if (is_ipv4_pkt(skb))
339 ip_hdr(skb)->check = 0;
4c09eed9
JB		 340 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
341
342 return 0;
343}
344
6e909283
NA		 345static void
346fec_enet_submit_work(struct bufdesc *bdp, struct fec_enet_private *fep)
347{
348 const struct platform_device_id *id_entry =
349 platform_get_device_id(fep->pdev);
350 struct bufdesc *bdp_pre;
351
352 bdp_pre = fec_enet_get_prevdesc(bdp, fep);
353 if ((id_entry->driver_data & FEC_QUIRK_ERR006358) &&
354 !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) {
355 fep->delay_work.trig_tx = true;
356 schedule_delayed_work(&(fep->delay_work.delay_work),
357 msecs_to_jiffies(1));
358 }
359}
360
361static int
362fec_enet_txq_submit_frag_skb(struct sk_buff *skb, struct net_device *ndev)
1da177e4 363{
c556167f 364 struct fec_enet_private *fep = netdev_priv(ndev);
b5680e0b
SG		 365 const struct platform_device_id *id_entry =
366 platform_get_device_id(fep->pdev);
6e909283
NA		 367 struct bufdesc *bdp = fep->cur_tx;
368 struct bufdesc_ex *ebdp;
369 int nr_frags = skb_shinfo(skb)->nr_frags;
370 int frag, frag_len;
371 unsigned short status;
372 unsigned int estatus = 0;
373 skb_frag_t *this_frag;
de5fb0a0 374 unsigned int index;
6e909283 375 void *bufaddr;
d6bf3143 376 dma_addr_t addr;
6e909283 377 int i;
1da177e4 378
6e909283
NA		 379 for (frag = 0; frag < nr_frags; frag++) {
380 this_frag = &skb_shinfo(skb)->frags[frag];
381 bdp = fec_enet_get_nextdesc(bdp, fep);
382 ebdp = (struct bufdesc_ex *)bdp;
383
384 status = bdp->cbd_sc;
385 status &= ~BD_ENET_TX_STATS;
386 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
387 frag_len = skb_shinfo(skb)->frags[frag].size;
388
389 /* Handle the last BD specially */
390 if (frag == nr_frags - 1) {
391 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
392 if (fep->bufdesc_ex) {
393 estatus |= BD_ENET_TX_INT;
394 if (unlikely(skb_shinfo(skb)->tx_flags &
395 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
396 estatus |= BD_ENET_TX_TS;
397 }
398 }
399
400 if (fep->bufdesc_ex) {
401 if (skb->ip_summed == CHECKSUM_PARTIAL)
402 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
403 ebdp->cbd_bdu = 0;
404 ebdp->cbd_esc = estatus;
405 }
406
407 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
408
409 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
410 if (((unsigned long) bufaddr) & FEC_ALIGNMENT ||
411 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
412 memcpy(fep->tx_bounce[index], bufaddr, frag_len);
413 bufaddr = fep->tx_bounce[index];
414
415 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
416 swap_buffer(bufaddr, frag_len);
417 }
418
d6bf3143
RK		 419 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
420 DMA_TO_DEVICE);
421 if (dma_mapping_error(&fep->pdev->dev, addr)) {
6e909283
NA		 422 dev_kfree_skb_any(skb);
423 if (net_ratelimit())
424 netdev_err(ndev, "Tx DMA memory map failed\n");
425 goto dma_mapping_error;
426 }
427
d6bf3143 428 bdp->cbd_bufaddr = addr;
6e909283
NA		 429 bdp->cbd_datlen = frag_len;
430 bdp->cbd_sc = status;
431 }
432
433 fep->cur_tx = bdp;
434
435 return 0;
436
437dma_mapping_error:
1da177e4 438 bdp = fep->cur_tx;
6e909283
NA		 439 for (i = 0; i < frag; i++) {
440 bdp = fec_enet_get_nextdesc(bdp, fep);
441 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
442 bdp->cbd_datlen, DMA_TO_DEVICE);
443 }
444 return NETDEV_TX_OK;
445}
1da177e4 446
6e909283
NA		 447static int fec_enet_txq_submit_skb(struct sk_buff *skb, struct net_device *ndev)
448{
449 struct fec_enet_private *fep = netdev_priv(ndev);
450 const struct platform_device_id *id_entry =
451 platform_get_device_id(fep->pdev);
452 int nr_frags = skb_shinfo(skb)->nr_frags;
453 struct bufdesc *bdp, *last_bdp;
454 void *bufaddr;
d6bf3143 455 dma_addr_t addr;
6e909283
NA		 456 unsigned short status;
457 unsigned short buflen;
458 unsigned int estatus = 0;
459 unsigned int index;
79f33912 460 int entries_free;
6e909283 461 int ret;
22f6b860 462
79f33912
NA		 463 entries_free = fec_enet_get_free_txdesc_num(fep);
464 if (entries_free < MAX_SKB_FRAGS + 1) {
465 dev_kfree_skb_any(skb);
466 if (net_ratelimit())
467 netdev_err(ndev, "NOT enough BD for SG!\n");
468 return NETDEV_TX_OK;
469 }
470
4c09eed9
JB		 471 /* Protocol checksum off-load for TCP and UDP. */
472 if (fec_enet_clear_csum(skb, ndev)) {
8e7e6874 473 dev_kfree_skb_any(skb);
4c09eed9
JB		 474 return NETDEV_TX_OK;
475 }
476
6e909283
NA		 477 /* Fill in a Tx ring entry */
478 bdp = fep->cur_tx;
479 status = bdp->cbd_sc;
0e702ab3 480 status &= ~BD_ENET_TX_STATS;
1da177e4 481
22f6b860 482 /* Set buffer length and buffer pointer */
9555b31e 483 bufaddr = skb->data;
6e909283 484 buflen = skb_headlen(skb);
1da177e4 485
61a4427b 486 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
6e909283
NA		 487 if (((unsigned long) bufaddr) & FEC_ALIGNMENT ||
488 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
489 memcpy(fep->tx_bounce[index], skb->data, buflen);
9555b31e 490 bufaddr = fep->tx_bounce[index];
1da177e4 491
6e909283
NA		 492 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
493 swap_buffer(bufaddr, buflen);
494 }
6aa20a22 495
d6bf3143
RK		 496 /* Push the data cache so the CPM does not get stale memory data. */
497 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
498 if (dma_mapping_error(&fep->pdev->dev, addr)) {
d842a31f
DFB		 499 dev_kfree_skb_any(skb);
500 if (net_ratelimit())
501 netdev_err(ndev, "Tx DMA memory map failed\n");
502 return NETDEV_TX_OK;
503 }
1da177e4 504
6e909283
NA		 505 if (nr_frags) {
506 ret = fec_enet_txq_submit_frag_skb(skb, ndev);
507 if (ret)
508 return ret;
509 } else {
510 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
511 if (fep->bufdesc_ex) {
512 estatus = BD_ENET_TX_INT;
513 if (unlikely(skb_shinfo(skb)->tx_flags &
514 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
515 estatus |= BD_ENET_TX_TS;
516 }
517 }
518
ff43da86
FL		 519 if (fep->bufdesc_ex) {
520
521 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6e909283 522
ff43da86 523 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
6e909283 524 fep->hwts_tx_en))
6605b730 525 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4c09eed9 526
6e909283
NA		 527 if (skb->ip_summed == CHECKSUM_PARTIAL)
528 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
529
530 ebdp->cbd_bdu = 0;
531 ebdp->cbd_esc = estatus;
6605b730 532 }
03191656 533
6e909283
NA		 534 last_bdp = fep->cur_tx;
535 index = fec_enet_get_bd_index(fep->tx_bd_base, last_bdp, fep);
536 /* Save skb pointer */
537 fep->tx_skbuff[index] = skb;
538
539 bdp->cbd_datlen = buflen;
d6bf3143 540 bdp->cbd_bufaddr = addr;
6e909283 541
fb8ef788
DFB		 542 /* Send it on its way. Tell FEC it's ready, interrupt when done,
543 * it's the last BD of the frame, and to put the CRC on the end.
544 */
6e909283 545 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
fb8ef788
DFB		 546 bdp->cbd_sc = status;
547
6e909283 548 fec_enet_submit_work(bdp, fep);
03191656 549
22f6b860 550 /* If this was the last BD in the ring, start at the beginning again. */
6e909283 551 bdp = fec_enet_get_nextdesc(last_bdp, fep);
1da177e4 552
7a2a8451
ED		 553 skb_tx_timestamp(skb);
554
de5fb0a0
FL		 555 fep->cur_tx = bdp;
556
de5fb0a0
FL		 557 /* Trigger transmission start */
558 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
1da177e4 559
6e909283 560 return 0;
1da177e4
LT		 561}
562
79f33912
NA		 563static int
564fec_enet_txq_put_data_tso(struct sk_buff *skb, struct net_device *ndev,
565 struct bufdesc *bdp, int index, char *data,
566 int size, bool last_tcp, bool is_last)
61a4427b
NA		 567{
568 struct fec_enet_private *fep = netdev_priv(ndev);
79f33912
NA		 569 const struct platform_device_id *id_entry =
570 platform_get_device_id(fep->pdev);
571 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
572 unsigned short status;
573 unsigned int estatus = 0;
d6bf3143 574 dma_addr_t addr;
61a4427b
NA		 575
576 status = bdp->cbd_sc;
79f33912 577 status &= ~BD_ENET_TX_STATS;
61a4427b 578
79f33912 579 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
79f33912
NA		 580
581 if (((unsigned long) data) & FEC_ALIGNMENT ||
582 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
583 memcpy(fep->tx_bounce[index], data, size);
584 data = fep->tx_bounce[index];
585
586 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
587 swap_buffer(data, size);
588 }
589
d6bf3143
RK		 590 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
591 if (dma_mapping_error(&fep->pdev->dev, addr)) {
79f33912 592 dev_kfree_skb_any(skb);
6e909283 593 if (net_ratelimit())
79f33912 594 netdev_err(ndev, "Tx DMA memory map failed\n");
61a4427b
NA		 595 return NETDEV_TX_BUSY;
596 }
597
d6bf3143
RK		 598 bdp->cbd_datlen = size;
599 bdp->cbd_bufaddr = addr;
600
79f33912
NA		 601 if (fep->bufdesc_ex) {
602 if (skb->ip_summed == CHECKSUM_PARTIAL)
603 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
604 ebdp->cbd_bdu = 0;
605 ebdp->cbd_esc = estatus;
606 }
607
608 /* Handle the last BD specially */
609 if (last_tcp)
610 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
611 if (is_last) {
612 status |= BD_ENET_TX_INTR;
613 if (fep->bufdesc_ex)
614 ebdp->cbd_esc |= BD_ENET_TX_INT;
615 }
616
617 bdp->cbd_sc = status;
618
619 return 0;
620}
621
622static int
623fec_enet_txq_put_hdr_tso(struct sk_buff *skb, struct net_device *ndev,
624 struct bufdesc *bdp, int index)
625{
626 struct fec_enet_private *fep = netdev_priv(ndev);
627 const struct platform_device_id *id_entry =
628 platform_get_device_id(fep->pdev);
629 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
630 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
631 void *bufaddr;
632 unsigned long dmabuf;
633 unsigned short status;
634 unsigned int estatus = 0;
635
636 status = bdp->cbd_sc;
637 status &= ~BD_ENET_TX_STATS;
638 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
639
640 bufaddr = fep->tso_hdrs + index * TSO_HEADER_SIZE;
641 dmabuf = fep->tso_hdrs_dma + index * TSO_HEADER_SIZE;
642 if (((unsigned long) bufaddr) & FEC_ALIGNMENT ||
643 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
644 memcpy(fep->tx_bounce[index], skb->data, hdr_len);
645 bufaddr = fep->tx_bounce[index];
646
647 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
648 swap_buffer(bufaddr, hdr_len);
649
650 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
651 hdr_len, DMA_TO_DEVICE);
652 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
653 dev_kfree_skb_any(skb);
654 if (net_ratelimit())
655 netdev_err(ndev, "Tx DMA memory map failed\n");
656 return NETDEV_TX_BUSY;
657 }
658 }
659
660 bdp->cbd_bufaddr = dmabuf;
661 bdp->cbd_datlen = hdr_len;
662
663 if (fep->bufdesc_ex) {
664 if (skb->ip_summed == CHECKSUM_PARTIAL)
665 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
666 ebdp->cbd_bdu = 0;
667 ebdp->cbd_esc = estatus;
668 }
669
670 bdp->cbd_sc = status;
671
672 return 0;
673}
674
675static int fec_enet_txq_submit_tso(struct sk_buff *skb, struct net_device *ndev)
676{
677 struct fec_enet_private *fep = netdev_priv(ndev);
678 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
679 int total_len, data_left;
680 struct bufdesc *bdp = fep->cur_tx;
681 struct tso_t tso;
682 unsigned int index = 0;
683 int ret;
684
685 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep)) {
686 dev_kfree_skb_any(skb);
687 if (net_ratelimit())
688 netdev_err(ndev, "NOT enough BD for TSO!\n");
689 return NETDEV_TX_OK;
690 }
691
692 /* Protocol checksum off-load for TCP and UDP. */
693 if (fec_enet_clear_csum(skb, ndev)) {
694 dev_kfree_skb_any(skb);
695 return NETDEV_TX_OK;
696 }
697
698 /* Initialize the TSO handler, and prepare the first payload */
699 tso_start(skb, &tso);
700
701 total_len = skb->len - hdr_len;
702 while (total_len > 0) {
703 char *hdr;
704
705 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
706 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
707 total_len -= data_left;
708
709 /* prepare packet headers: MAC + IP + TCP */
710 hdr = fep->tso_hdrs + index * TSO_HEADER_SIZE;
711 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
712 ret = fec_enet_txq_put_hdr_tso(skb, ndev, bdp, index);
713 if (ret)
714 goto err_release;
715
716 while (data_left > 0) {
717 int size;
718
719 size = min_t(int, tso.size, data_left);
720 bdp = fec_enet_get_nextdesc(bdp, fep);
721 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
722 ret = fec_enet_txq_put_data_tso(skb, ndev, bdp, index, tso.data,
723 size, size == data_left,
724 total_len == 0);
725 if (ret)
726 goto err_release;
727
728 data_left -= size;
729 tso_build_data(skb, &tso, size);
730 }
731
732 bdp = fec_enet_get_nextdesc(bdp, fep);
733 }
734
735 /* Save skb pointer */
736 fep->tx_skbuff[index] = skb;
737
738 fec_enet_submit_work(bdp, fep);
739
740 skb_tx_timestamp(skb);
741 fep->cur_tx = bdp;
742
743 /* Trigger transmission start */
744 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
745
746 return 0;
747
748err_release:
749 /* TODO: Release all used data descriptors for TSO */
750 return ret;
751}
752
753static netdev_tx_t
754fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
755{
756 struct fec_enet_private *fep = netdev_priv(ndev);
757 int entries_free;
758 int ret;
759
760 if (skb_is_gso(skb))
761 ret = fec_enet_txq_submit_tso(skb, ndev);
762 else
763 ret = fec_enet_txq_submit_skb(skb, ndev);
6e909283
NA		 764 if (ret)
765 return ret;
61a4427b 766
6e909283 767 entries_free = fec_enet_get_free_txdesc_num(fep);
79f33912 768 if (entries_free <= fep->tx_stop_threshold)
61a4427b
NA		 769 netif_stop_queue(ndev);
770
771 return NETDEV_TX_OK;
772}
773
14109a59
FL		 774/* Init RX & TX buffer descriptors
775 */
776static void fec_enet_bd_init(struct net_device *dev)
777{
778 struct fec_enet_private *fep = netdev_priv(dev);
779 struct bufdesc *bdp;
780 unsigned int i;
781
782 /* Initialize the receive buffer descriptors. */
783 bdp = fep->rx_bd_base;
36e24e2e 784 for (i = 0; i < fep->rx_ring_size; i++) {
14109a59
FL		 785
786 /* Initialize the BD for every fragment in the page. */
787 if (bdp->cbd_bufaddr)
788 bdp->cbd_sc = BD_ENET_RX_EMPTY;
789 else
790 bdp->cbd_sc = 0;
36e24e2e 791 bdp = fec_enet_get_nextdesc(bdp, fep);
14109a59
FL		 792 }
793
794 /* Set the last buffer to wrap */
36e24e2e 795 bdp = fec_enet_get_prevdesc(bdp, fep);
14109a59
FL		 796 bdp->cbd_sc |= BD_SC_WRAP;
797
798 fep->cur_rx = fep->rx_bd_base;
799
800 /* ...and the same for transmit */
801 bdp = fep->tx_bd_base;
802 fep->cur_tx = bdp;
36e24e2e 803 for (i = 0; i < fep->tx_ring_size; i++) {
14109a59
FL		 804
805 /* Initialize the BD for every fragment in the page. */
806 bdp->cbd_sc = 0;
d6bf3143 807 if (fep->tx_skbuff[i]) {
14109a59
FL		 808 dev_kfree_skb_any(fep->tx_skbuff[i]);
809 fep->tx_skbuff[i] = NULL;
810 }
811 bdp->cbd_bufaddr = 0;
36e24e2e 812 bdp = fec_enet_get_nextdesc(bdp, fep);
14109a59
FL		 813 }
814
815 /* Set the last buffer to wrap */
36e24e2e 816 bdp = fec_enet_get_prevdesc(bdp, fep);
14109a59
FL		 817 bdp->cbd_sc |= BD_SC_WRAP;
818 fep->dirty_tx = bdp;
819}
820
45993653
UKK		 821/* This function is called to start or restart the FEC during a link
822 * change. This only happens when switching between half and full
823 * duplex.
824 */
1da177e4 825static void
45993653 826fec_restart(struct net_device *ndev, int duplex)
1da177e4 827{
c556167f 828 struct fec_enet_private *fep = netdev_priv(ndev);
45993653
UKK		 829 const struct platform_device_id *id_entry =
830 platform_get_device_id(fep->pdev);
831 int i;
4c09eed9 832 u32 val;
cd1f402c
UKK		 833 u32 temp_mac[2];
834 u32 rcntl = OPT_FRAME_SIZE | 0x04;
230dec61 835 u32 ecntl = 0x2; /* ETHEREN */
1da177e4 836
54309fa6
FL		 837 if (netif_running(ndev)) {
838 netif_device_detach(ndev);
839 napi_disable(&fep->napi);
b49cd504 840 netif_tx_disable(ndev);
31691344 841 netif_tx_lock_bh(ndev);
54309fa6
FL		 842 }
843
45993653
UKK		 844 /* Whack a reset. We should wait for this. */
845 writel(1, fep->hwp + FEC_ECNTRL);
846 udelay(10);
1da177e4 847
45993653
UKK		 848 /*
849 * enet-mac reset will reset mac address registers too,
850 * so need to reconfigure it.
851 */
852 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
853 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
854 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
855 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
856 }
1da177e4 857
45993653
UKK		 858 /* Clear any outstanding interrupt. */
859 writel(0xffc00000, fep->hwp + FEC_IEVENT);
1da177e4 860
45993653
UKK		 861 /* Set maximum receive buffer size. */
862 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
1da177e4 863
14109a59
FL		 864 fec_enet_bd_init(ndev);
865
45993653
UKK		 866 /* Set receive and transmit descriptor base. */
867 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
ff43da86
FL		 868 if (fep->bufdesc_ex)
869 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
36e24e2e 870 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
ff43da86
FL		 871 else
872 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
36e24e2e 873 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
45993653 874
45993653 875
45993653
UKK		 876 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
877 if (fep->tx_skbuff[i]) {
878 dev_kfree_skb_any(fep->tx_skbuff[i]);
879 fep->tx_skbuff[i] = NULL;
1da177e4 880 }
45993653 881 }
97b72e43 882
45993653
UKK		 883 /* Enable MII mode */
884 if (duplex) {
cd1f402c 885 /* FD enable */
45993653
UKK		 886 writel(0x04, fep->hwp + FEC_X_CNTRL);
887 } else {
cd1f402c
UKK		 888 /* No Rcv on Xmit */
889 rcntl |= 0x02;
45993653
UKK		 890 writel(0x0, fep->hwp + FEC_X_CNTRL);
891 }
cd1f402c 892
45993653
UKK		 893 fep->full_duplex = duplex;
894
895 /* Set MII speed */
896 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
897
d1391930 898#if !defined(CONFIG_M5272)
4c09eed9
JB		 899 /* set RX checksum */
900 val = readl(fep->hwp + FEC_RACC);
901 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
902 val |= FEC_RACC_OPTIONS;
903 else
904 val &= ~FEC_RACC_OPTIONS;
905 writel(val, fep->hwp + FEC_RACC);
d1391930 906#endif
4c09eed9 907
45993653
UKK		 908 /*
909 * The phy interface and speed need to get configured
910 * differently on enet-mac.
911 */
912 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
cd1f402c
UKK		 913 /* Enable flow control and length check */
914 rcntl |= 0x40000000 | 0x00000020;
45993653 915
230dec61
SG		 916 /* RGMII, RMII or MII */
917 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
918 rcntl |= (1 << 6);
919 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
cd1f402c 920 rcntl |= (1 << 8);
45993653 921 else
cd1f402c 922 rcntl &= ~(1 << 8);
45993653 923
230dec61
SG		 924 /* 1G, 100M or 10M */
925 if (fep->phy_dev) {
926 if (fep->phy_dev->speed == SPEED_1000)
927 ecntl |= (1 << 5);
928 else if (fep->phy_dev->speed == SPEED_100)
929 rcntl &= ~(1 << 9);
930 else
931 rcntl |= (1 << 9);
932 }
45993653
UKK		 933 } else {
934#ifdef FEC_MIIGSK_ENR
0ca1e290 935 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
8d82f219 936 u32 cfgr;
45993653
UKK		 937 /* disable the gasket and wait */
938 writel(0, fep->hwp + FEC_MIIGSK_ENR);
939 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
940 udelay(1);
941
942 /*
943 * configure the gasket:
944 * RMII, 50 MHz, no loopback, no echo
0ca1e290 945 * MII, 25 MHz, no loopback, no echo
45993653 946 */
8d82f219
EB		 947 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
948 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
949 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
950 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
951 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
45993653
UKK		 952
953 /* re-enable the gasket */
954 writel(2, fep->hwp + FEC_MIIGSK_ENR);
97b72e43 955 }
45993653
UKK		 956#endif
957 }
baa70a5c 958
d1391930 959#if !defined(CONFIG_M5272)
baa70a5c
FL		 960 /* enable pause frame*/
961 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
962 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
963 fep->phy_dev && fep->phy_dev->pause)) {
964 rcntl |= FEC_ENET_FCE;
965
4c09eed9 966 /* set FIFO threshold parameter to reduce overrun */
baa70a5c
FL		 967 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
968 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
969 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
970 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
971
972 /* OPD */
973 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
974 } else {
975 rcntl &= ~FEC_ENET_FCE;
976 }
d1391930 977#endif /* !defined(CONFIG_M5272) */
baa70a5c 978
cd1f402c 979 writel(rcntl, fep->hwp + FEC_R_CNTRL);
3b2b74ca 980
84fe6182
SW		 981 /* Setup multicast filter. */
982 set_multicast_list(ndev);
983#ifndef CONFIG_M5272
984 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
985 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
986#endif
987
230dec61
SG		 988 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
989 /* enable ENET endian swap */
990 ecntl |= (1 << 8);
991 /* enable ENET store and forward mode */
992 writel(1 << 8, fep->hwp + FEC_X_WMRK);
993 }
994
ff43da86
FL		 995 if (fep->bufdesc_ex)
996 ecntl |= (1 << 4);
6605b730 997
38ae92dc 998#ifndef CONFIG_M5272
b9eef55c
JB		 999 /* Enable the MIB statistic event counters */
1000 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
38ae92dc
CH		 1001#endif
1002
45993653 1003 /* And last, enable the transmit and receive processing */
230dec61 1004 writel(ecntl, fep->hwp + FEC_ECNTRL);
45993653
UKK		 1005 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1006
ff43da86
FL		 1007 if (fep->bufdesc_ex)
1008 fec_ptp_start_cyclecounter(ndev);
1009
45993653
UKK		 1010 /* Enable interrupts we wish to service */
1011 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
54309fa6
FL		 1012
1013 if (netif_running(ndev)) {
31691344 1014 netif_tx_unlock_bh(ndev);
54309fa6 1015 netif_wake_queue(ndev);
1ed0d56c
FE		 1016 napi_enable(&fep->napi);
1017 netif_device_attach(ndev);
54309fa6 1018 }
45993653
UKK		 1019}
1020
1021static void
1022fec_stop(struct net_device *ndev)
1023{
1024 struct fec_enet_private *fep = netdev_priv(ndev);
230dec61
SG		 1025 const struct platform_device_id *id_entry =
1026 platform_get_device_id(fep->pdev);
42431dc2 1027 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
45993653
UKK		 1028
1029 /* We cannot expect a graceful transmit stop without link !!! */
1030 if (fep->link) {
1031 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1032 udelay(10);
1033 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
31b7720c 1034 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
45993653
UKK		 1035 }
1036
1037 /* Whack a reset. We should wait for this. */
1038 writel(1, fep->hwp + FEC_ECNTRL);
1039 udelay(10);
1040 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1041 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
230dec61
SG		 1042
1043 /* We have to keep ENET enabled to have MII interrupt stay working */
42431dc2 1044 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
230dec61 1045 writel(2, fep->hwp + FEC_ECNTRL);
42431dc2
LW		 1046 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1047 }
1da177e4
LT		 1048}
1049
1050
45993653
UKK		 1051static void
1052fec_timeout(struct net_device *ndev)
1053{
1054 struct fec_enet_private *fep = netdev_priv(ndev);
1055
1056 ndev->stats.tx_errors++;
1057
54309fa6
FL		 1058 fep->delay_work.timeout = true;
1059 schedule_delayed_work(&(fep->delay_work.delay_work), 0);
1060}
1061
1062static void fec_enet_work(struct work_struct *work)
1063{
1064 struct fec_enet_private *fep =
1065 container_of(work,
1066 struct fec_enet_private,
1067 delay_work.delay_work.work);
8ce5624f 1068 struct net_device *ndev = fep->netdev;
54309fa6
FL		 1069
1070 if (fep->delay_work.timeout) {
1071 fep->delay_work.timeout = false;
da1774e5 1072 rtnl_lock();
8ce5624f
RK		 1073 if (netif_device_present(ndev) || netif_running(ndev)) {
1074 fec_restart(ndev, fep->full_duplex);
1075 netif_wake_queue(ndev);
1076 }
da1774e5 1077 rtnl_unlock();
54309fa6 1078 }
03191656
FL		 1079
1080 if (fep->delay_work.trig_tx) {
1081 fep->delay_work.trig_tx = false;
1082 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
1083 }
45993653
UKK		 1084}
1085
1da177e4 1086static void
c556167f 1087fec_enet_tx(struct net_device *ndev)
1da177e4
LT		 1088{
1089 struct fec_enet_private *fep;
2e28532f 1090 struct bufdesc *bdp;
0e702ab3 1091 unsigned short status;
1da177e4 1092 struct sk_buff *skb;
de5fb0a0 1093 int index = 0;
79f33912 1094 int entries_free;
1da177e4 1095
c556167f 1096 fep = netdev_priv(ndev);
1da177e4
LT		 1097 bdp = fep->dirty_tx;
1098
de5fb0a0 1099 /* get next bdp of dirty_tx */
36e24e2e 1100 bdp = fec_enet_get_nextdesc(bdp, fep);
de5fb0a0 1101
0e702ab3 1102 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
de5fb0a0
FL		 1103
1104 /* current queue is empty */
1105 if (bdp == fep->cur_tx)
f0b3fbea
SH		 1106 break;
1107
61a4427b 1108 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
de5fb0a0 1109
de5fb0a0 1110 skb = fep->tx_skbuff[index];
d6bf3143 1111 fep->tx_skbuff[index] = NULL;
79f33912
NA		 1112 if (!IS_TSO_HEADER(fep, bdp->cbd_bufaddr))
1113 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1114 bdp->cbd_datlen, DMA_TO_DEVICE);
2488a54e 1115 bdp->cbd_bufaddr = 0;
6e909283
NA		 1116 if (!skb) {
1117 bdp = fec_enet_get_nextdesc(bdp, fep);
1118 continue;
1119 }
de5fb0a0 1120
1da177e4 1121 /* Check for errors. */
0e702ab3 1122 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1da177e4
LT		 1123 BD_ENET_TX_RL | BD_ENET_TX_UN |
1124 BD_ENET_TX_CSL)) {
c556167f 1125 ndev->stats.tx_errors++;
0e702ab3 1126 if (status & BD_ENET_TX_HB) /* No heartbeat */
c556167f 1127 ndev->stats.tx_heartbeat_errors++;
0e702ab3 1128 if (status & BD_ENET_TX_LC) /* Late collision */
c556167f 1129 ndev->stats.tx_window_errors++;
0e702ab3 1130 if (status & BD_ENET_TX_RL) /* Retrans limit */
c556167f 1131 ndev->stats.tx_aborted_errors++;
0e702ab3 1132 if (status & BD_ENET_TX_UN) /* Underrun */
c556167f 1133 ndev->stats.tx_fifo_errors++;
0e702ab3 1134 if (status & BD_ENET_TX_CSL) /* Carrier lost */
c556167f 1135 ndev->stats.tx_carrier_errors++;
1da177e4 1136 } else {
c556167f 1137 ndev->stats.tx_packets++;
6e909283 1138 ndev->stats.tx_bytes += skb->len;
1da177e4
LT		 1139 }
1140
ff43da86
FL		 1141 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1142 fep->bufdesc_ex) {
6605b730
FL		 1143 struct skb_shared_hwtstamps shhwtstamps;
1144 unsigned long flags;
ff43da86 1145 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6605b730
FL		 1146
1147 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
1148 spin_lock_irqsave(&fep->tmreg_lock, flags);
1149 shhwtstamps.hwtstamp = ns_to_ktime(
ff43da86 1150 timecounter_cyc2time(&fep->tc, ebdp->ts));
6605b730
FL		 1151 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1152 skb_tstamp_tx(skb, &shhwtstamps);
1153 }
ff43da86 1154
0e702ab3 1155 if (status & BD_ENET_TX_READY)
31b7720c 1156 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
22f6b860 1157
1da177e4
LT		 1158 /* Deferred means some collisions occurred during transmit,
1159 * but we eventually sent the packet OK.
1160 */
0e702ab3 1161 if (status & BD_ENET_TX_DEF)
c556167f 1162 ndev->stats.collisions++;
6aa20a22 1163
22f6b860 1164 /* Free the sk buffer associated with this last transmit */
1da177e4 1165 dev_kfree_skb_any(skb);
de5fb0a0
FL		 1166
1167 fep->dirty_tx = bdp;
6aa20a22 1168
22f6b860 1169 /* Update pointer to next buffer descriptor to be transmitted */
36e24e2e 1170 bdp = fec_enet_get_nextdesc(bdp, fep);
6aa20a22 1171
22f6b860 1172 /* Since we have freed up a buffer, the ring is no longer full
1da177e4 1173 */
79f33912
NA		 1174 if (netif_queue_stopped(ndev)) {
1175 entries_free = fec_enet_get_free_txdesc_num(fep);
1176 if (entries_free >= fep->tx_wake_threshold)
1177 netif_wake_queue(ndev);
1178 }
1da177e4 1179 }
de5fb0a0 1180 return;
1da177e4
LT		 1181}
1182
1da177e4
LT		 1183/* During a receive, the cur_rx points to the current incoming buffer.
1184 * When we update through the ring, if the next incoming buffer has
1185 * not been given to the system, we just set the empty indicator,
1186 * effectively tossing the packet.
1187 */
dc975382
FL		 1188static int
1189fec_enet_rx(struct net_device *ndev, int budget)
1da177e4 1190{
c556167f 1191 struct fec_enet_private *fep = netdev_priv(ndev);
b5680e0b
SG		 1192 const struct platform_device_id *id_entry =
1193 platform_get_device_id(fep->pdev);
2e28532f 1194 struct bufdesc *bdp;
0e702ab3 1195 unsigned short status;
1da177e4
LT		 1196 struct sk_buff *skb;
1197 ushort pkt_len;
1198 __u8 *data;
dc975382 1199 int pkt_received = 0;
cdffcf1b
JB		 1200 struct bufdesc_ex *ebdp = NULL;
1201 bool vlan_packet_rcvd = false;
1202 u16 vlan_tag;
d842a31f 1203 int index = 0;
6aa20a22 1204
0e702ab3
GU		 1205#ifdef CONFIG_M532x
1206 flush_cache_all();
6aa20a22 1207#endif
1da177e4 1208
1da177e4
LT		 1209 /* First, grab all of the stats for the incoming packet.
1210 * These get messed up if we get called due to a busy condition.
1211 */
1212 bdp = fep->cur_rx;
1213
22f6b860 1214 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1da177e4 1215
dc975382
FL		 1216 if (pkt_received >= budget)
1217 break;
1218 pkt_received++;
1219
22f6b860
SH		 1220 /* Since we have allocated space to hold a complete frame,
1221 * the last indicator should be set.
1222 */
1223 if ((status & BD_ENET_RX_LAST) == 0)
31b7720c 1224 netdev_err(ndev, "rcv is not +last\n");
1da177e4 1225
22f6b860
SH		 1226 /* Check for errors. */
1227 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1da177e4 1228 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
c556167f 1229 ndev->stats.rx_errors++;
22f6b860
SH		 1230 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1231 /* Frame too long or too short. */
c556167f 1232 ndev->stats.rx_length_errors++;
22f6b860
SH		 1233 }
1234 if (status & BD_ENET_RX_NO) /* Frame alignment */
c556167f 1235 ndev->stats.rx_frame_errors++;
22f6b860 1236 if (status & BD_ENET_RX_CR) /* CRC Error */
c556167f 1237 ndev->stats.rx_crc_errors++;
22f6b860 1238 if (status & BD_ENET_RX_OV) /* FIFO overrun */
c556167f 1239 ndev->stats.rx_fifo_errors++;
1da177e4 1240 }
1da177e4 1241
22f6b860
SH		 1242 /* Report late collisions as a frame error.
1243 * On this error, the BD is closed, but we don't know what we
1244 * have in the buffer. So, just drop this frame on the floor.
1245 */
1246 if (status & BD_ENET_RX_CL) {
c556167f
UKK		 1247 ndev->stats.rx_errors++;
1248 ndev->stats.rx_frame_errors++;
22f6b860
SH		 1249 goto rx_processing_done;
1250 }
1da177e4 1251
22f6b860 1252 /* Process the incoming frame. */
c556167f 1253 ndev->stats.rx_packets++;
22f6b860 1254 pkt_len = bdp->cbd_datlen;
c556167f 1255 ndev->stats.rx_bytes += pkt_len;
1da177e4 1256
61a4427b 1257 index = fec_enet_get_bd_index(fep->rx_bd_base, bdp, fep);
d842a31f
DFB		 1258 data = fep->rx_skbuff[index]->data;
1259 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1260 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
ccdc4f19 1261
b5680e0b
SG		 1262 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
1263 swap_buffer(data, pkt_len);
1264
cdffcf1b
JB		 1265 /* Extract the enhanced buffer descriptor */
1266 ebdp = NULL;
1267 if (fep->bufdesc_ex)
1268 ebdp = (struct bufdesc_ex *)bdp;
1269
1270 /* If this is a VLAN packet remove the VLAN Tag */
1271 vlan_packet_rcvd = false;
1272 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1273 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
1274 /* Push and remove the vlan tag */
1275 struct vlan_hdr *vlan_header =
1276 (struct vlan_hdr *) (data + ETH_HLEN);
1277 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1278 pkt_len -= VLAN_HLEN;
1279
1280 vlan_packet_rcvd = true;
1281 }
1282
22f6b860
SH		 1283 /* This does 16 byte alignment, exactly what we need.
1284 * The packet length includes FCS, but we don't want to
1285 * include that when passing upstream as it messes up
1286 * bridging applications.
1287 */
b72061a3 1288 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
1da177e4 1289
8549889c 1290 if (unlikely(!skb)) {
c556167f 1291 ndev->stats.rx_dropped++;
22f6b860 1292 } else {
cdffcf1b 1293 int payload_offset = (2 * ETH_ALEN);
8549889c 1294 skb_reserve(skb, NET_IP_ALIGN);
22f6b860 1295 skb_put(skb, pkt_len - 4); /* Make room */
cdffcf1b
JB		 1296
1297 /* Extract the frame data without the VLAN header. */
1298 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
1299 if (vlan_packet_rcvd)
1300 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
1301 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
1302 data + payload_offset,
1303 pkt_len - 4 - (2 * ETH_ALEN));
1304
c556167f 1305 skb->protocol = eth_type_trans(skb, ndev);
ff43da86 1306
6605b730 1307 /* Get receive timestamp from the skb */
ff43da86 1308 if (fep->hwts_rx_en && fep->bufdesc_ex) {
6605b730
FL		 1309 struct skb_shared_hwtstamps *shhwtstamps =
1310 skb_hwtstamps(skb);
1311 unsigned long flags;
1312
1313 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1314
1315 spin_lock_irqsave(&fep->tmreg_lock, flags);
1316 shhwtstamps->hwtstamp = ns_to_ktime(
ff43da86 1317 timecounter_cyc2time(&fep->tc, ebdp->ts));
6605b730
FL		 1318 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1319 }
ff43da86 1320
4c09eed9 1321 if (fep->bufdesc_ex &&
cdffcf1b 1322 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
4c09eed9
JB		 1323 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1324 /* don't check it */
1325 skb->ip_summed = CHECKSUM_UNNECESSARY;
1326 } else {
1327 skb_checksum_none_assert(skb);
1328 }
1329 }
1330
cdffcf1b
JB		 1331 /* Handle received VLAN packets */
1332 if (vlan_packet_rcvd)
1333 __vlan_hwaccel_put_tag(skb,
1334 htons(ETH_P_8021Q),
1335 vlan_tag);
1336
0affdf34 1337 napi_gro_receive(&fep->napi, skb);
22f6b860 1338 }
f0b3fbea 1339
d842a31f
DFB		 1340 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1341 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
22f6b860
SH		 1342rx_processing_done:
1343 /* Clear the status flags for this buffer */
1344 status &= ~BD_ENET_RX_STATS;
1da177e4 1345
22f6b860
SH		 1346 /* Mark the buffer empty */
1347 status |= BD_ENET_RX_EMPTY;
1348 bdp->cbd_sc = status;
6aa20a22 1349
ff43da86
FL		 1350 if (fep->bufdesc_ex) {
1351 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1352
1353 ebdp->cbd_esc = BD_ENET_RX_INT;
1354 ebdp->cbd_prot = 0;
1355 ebdp->cbd_bdu = 0;
1356 }
6605b730 1357
22f6b860 1358 /* Update BD pointer to next entry */
36e24e2e
DFB		 1359 bdp = fec_enet_get_nextdesc(bdp, fep);
1360
22f6b860
SH		 1361 /* Doing this here will keep the FEC running while we process
1362 * incoming frames. On a heavily loaded network, we should be
1363 * able to keep up at the expense of system resources.
1364 */
1365 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1366 }
2e28532f 1367 fep->cur_rx = bdp;
1da177e4 1368
dc975382 1369 return pkt_received;
1da177e4
LT		 1370}
1371
45993653
UKK		 1372static irqreturn_t
1373fec_enet_interrupt(int irq, void *dev_id)
1374{
1375 struct net_device *ndev = dev_id;
1376 struct fec_enet_private *fep = netdev_priv(ndev);
7a16807c 1377 const unsigned napi_mask = FEC_ENET_RXF | FEC_ENET_TXF;
45993653
UKK		 1378 uint int_events;
1379 irqreturn_t ret = IRQ_NONE;
1380
7a16807c
RK		 1381 int_events = readl(fep->hwp + FEC_IEVENT);
1382 writel(int_events & ~napi_mask, fep->hwp + FEC_IEVENT);
45993653 1383
7a16807c
RK		 1384 if (int_events & napi_mask) {
1385 ret = IRQ_HANDLED;
dc975382 1386
7a16807c
RK		 1387 /* Disable the NAPI interrupts */
1388 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1389 napi_schedule(&fep->napi);
1390 }
45993653 1391
7a16807c
RK		 1392 if (int_events & FEC_ENET_MII) {
1393 ret = IRQ_HANDLED;
1394 complete(&fep->mdio_done);
1395 }
45993653
UKK		 1396
1397 return ret;
1398}
1399
dc975382
FL		 1400static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1401{
1402 struct net_device *ndev = napi->dev;
dc975382 1403 struct fec_enet_private *fep = netdev_priv(ndev);
7a16807c
RK		 1404 int pkts;
1405
1406 /*
1407 * Clear any pending transmit or receive interrupts before
1408 * processing the rings to avoid racing with the hardware.
1409 */
1410 writel(FEC_ENET_RXF | FEC_ENET_TXF, fep->hwp + FEC_IEVENT);
1411
1412 pkts = fec_enet_rx(ndev, budget);
45993653 1413
de5fb0a0
FL		 1414 fec_enet_tx(ndev);
1415
dc975382
FL		 1416 if (pkts < budget) {
1417 napi_complete(napi);
1418 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1419 }
1420 return pkts;
1421}
45993653 1422
e6b043d5 1423/* ------------------------------------------------------------------------- */
0c7768a0 1424static void fec_get_mac(struct net_device *ndev)
1da177e4 1425{
c556167f 1426 struct fec_enet_private *fep = netdev_priv(ndev);
94660ba0 1427 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
e6b043d5 1428 unsigned char *iap, tmpaddr[ETH_ALEN];
1da177e4 1429
49da97dc
SG		 1430 /*
1431 * try to get mac address in following order:
1432 *
1433 * 1) module parameter via kernel command line in form
1434 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1435 */
1436 iap = macaddr;
1437
ca2cc333
SG		 1438 /*
1439 * 2) from device tree data
1440 */
1441 if (!is_valid_ether_addr(iap)) {
1442 struct device_node *np = fep->pdev->dev.of_node;
1443 if (np) {
1444 const char *mac = of_get_mac_address(np);
1445 if (mac)
1446 iap = (unsigned char *) mac;
1447 }
1448 }
ca2cc333 1449
49da97dc 1450 /*
ca2cc333 1451 * 3) from flash or fuse (via platform data)
49da97dc
SG		 1452 */
1453 if (!is_valid_ether_addr(iap)) {
1454#ifdef CONFIG_M5272
1455 if (FEC_FLASHMAC)
1456 iap = (unsigned char *)FEC_FLASHMAC;
1457#else
1458 if (pdata)
589efdc7 1459 iap = (unsigned char *)&pdata->mac;
49da97dc
SG		 1460#endif
1461 }
1462
1463 /*
ca2cc333 1464 * 4) FEC mac registers set by bootloader
49da97dc
SG		 1465 */
1466 if (!is_valid_ether_addr(iap)) {
7d7628f3
DC		 1467 *((__be32 *) &tmpaddr[0]) =
1468 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1469 *((__be16 *) &tmpaddr[4]) =
1470 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
e6b043d5 1471 iap = &tmpaddr[0];
1da177e4
LT		 1472 }
1473
ff5b2fab
LS		 1474 /*
1475 * 5) random mac address
1476 */
1477 if (!is_valid_ether_addr(iap)) {
1478 /* Report it and use a random ethernet address instead */
1479 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1480 eth_hw_addr_random(ndev);
1481 netdev_info(ndev, "Using random MAC address: %pM\n",
1482 ndev->dev_addr);
1483 return;
1484 }
1485
c556167f 1486 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1da177e4 1487
49da97dc
SG		 1488 /* Adjust MAC if using macaddr */
1489 if (iap == macaddr)
43af940c 1490 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1da177e4
LT		 1491}
1492
e6b043d5 1493/* ------------------------------------------------------------------------- */
1da177e4 1494
e6b043d5
BW		 1495/*
1496 * Phy section
1497 */
c556167f 1498static void fec_enet_adjust_link(struct net_device *ndev)
1da177e4 1499{
c556167f 1500 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1501 struct phy_device *phy_dev = fep->phy_dev;
e6b043d5 1502 int status_change = 0;
1da177e4 1503
e6b043d5
BW		 1504 /* Prevent a state halted on mii error */
1505 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1506 phy_dev->state = PHY_RESUMING;
54309fa6 1507 return;
e6b043d5 1508 }
1da177e4 1509
8ce5624f
RK		 1510 /*
1511 * If the netdev is down, or is going down, we're not interested
1512 * in link state events, so just mark our idea of the link as down
1513 * and ignore the event.
1514 */
1515 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1516 fep->link = 0;
1517 } else if (phy_dev->link) {
d97e7497 1518 if (!fep->link) {
6ea0722f 1519 fep->link = phy_dev->link;
e6b043d5
BW		 1520 status_change = 1;
1521 }
1da177e4 1522
d97e7497
LS		 1523 if (fep->full_duplex != phy_dev->duplex)
1524 status_change = 1;
1525
1526 if (phy_dev->speed != fep->speed) {
1527 fep->speed = phy_dev->speed;
1528 status_change = 1;
1529 }
1530
1531 /* if any of the above changed restart the FEC */
1532 if (status_change)
c556167f 1533 fec_restart(ndev, phy_dev->duplex);
d97e7497
LS		 1534 } else {
1535 if (fep->link) {
c556167f 1536 fec_stop(ndev);
8d7ed0f0 1537 fep->link = phy_dev->link;
d97e7497
LS		 1538 status_change = 1;
1539 }
1da177e4 1540 }
6aa20a22 1541
e6b043d5
BW		 1542 if (status_change)
1543 phy_print_status(phy_dev);
1544}
1da177e4 1545
e6b043d5 1546static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1da177e4 1547{
e6b043d5 1548 struct fec_enet_private *fep = bus->priv;
97b72e43 1549 unsigned long time_left;
1da177e4 1550
e6b043d5 1551 fep->mii_timeout = 0;
97b72e43 1552 init_completion(&fep->mdio_done);
e6b043d5
BW		 1553
1554 /* start a read op */
1555 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1556 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1557 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1558
1559 /* wait for end of transfer */
97b72e43
BS		 1560 time_left = wait_for_completion_timeout(&fep->mdio_done,
1561 usecs_to_jiffies(FEC_MII_TIMEOUT));
1562 if (time_left == 0) {
1563 fep->mii_timeout = 1;
31b7720c 1564 netdev_err(fep->netdev, "MDIO read timeout\n");
97b72e43 1565 return -ETIMEDOUT;
1da177e4 1566 }
1da177e4 1567
e6b043d5
BW		 1568 /* return value */
1569 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
7dd6a2aa 1570}
6aa20a22 1571
e6b043d5
BW		 1572static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1573 u16 value)
1da177e4 1574{
e6b043d5 1575 struct fec_enet_private *fep = bus->priv;
97b72e43 1576 unsigned long time_left;
1da177e4 1577
e6b043d5 1578 fep->mii_timeout = 0;
97b72e43 1579 init_completion(&fep->mdio_done);
1da177e4 1580
862f0982
SG		 1581 /* start a write op */
1582 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
e6b043d5
BW		 1583 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1584 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1585 fep->hwp + FEC_MII_DATA);
1586
1587 /* wait for end of transfer */
97b72e43
BS		 1588 time_left = wait_for_completion_timeout(&fep->mdio_done,
1589 usecs_to_jiffies(FEC_MII_TIMEOUT));
1590 if (time_left == 0) {
1591 fep->mii_timeout = 1;
31b7720c 1592 netdev_err(fep->netdev, "MDIO write timeout\n");
97b72e43 1593 return -ETIMEDOUT;
e6b043d5 1594 }
1da177e4 1595
e6b043d5
BW		 1596 return 0;
1597}
1da177e4 1598
e8fcfcd5
NA		 1599static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1600{
1601 struct fec_enet_private *fep = netdev_priv(ndev);
1602 int ret;
1603
1604 if (enable) {
1605 ret = clk_prepare_enable(fep->clk_ahb);
1606 if (ret)
1607 return ret;
1608 ret = clk_prepare_enable(fep->clk_ipg);
1609 if (ret)
1610 goto failed_clk_ipg;
1611 if (fep->clk_enet_out) {
1612 ret = clk_prepare_enable(fep->clk_enet_out);
1613 if (ret)
1614 goto failed_clk_enet_out;
1615 }
1616 if (fep->clk_ptp) {
1617 ret = clk_prepare_enable(fep->clk_ptp);
1618 if (ret)
1619 goto failed_clk_ptp;
1620 }
1621 } else {
1622 clk_disable_unprepare(fep->clk_ahb);
1623 clk_disable_unprepare(fep->clk_ipg);
1624 if (fep->clk_enet_out)
1625 clk_disable_unprepare(fep->clk_enet_out);
1626 if (fep->clk_ptp)
1627 clk_disable_unprepare(fep->clk_ptp);
1628 }
1629
1630 return 0;
1631failed_clk_ptp:
1632 if (fep->clk_enet_out)
1633 clk_disable_unprepare(fep->clk_enet_out);
1634failed_clk_enet_out:
1635 clk_disable_unprepare(fep->clk_ipg);
1636failed_clk_ipg:
1637 clk_disable_unprepare(fep->clk_ahb);
1638
1639 return ret;
1640}
1641
c556167f 1642static int fec_enet_mii_probe(struct net_device *ndev)
562d2f8c 1643{
c556167f 1644 struct fec_enet_private *fep = netdev_priv(ndev);
230dec61
SG		 1645 const struct platform_device_id *id_entry =
1646 platform_get_device_id(fep->pdev);
e6b043d5 1647 struct phy_device *phy_dev = NULL;
6fcc040f
GU		 1648 char mdio_bus_id[MII_BUS_ID_SIZE];
1649 char phy_name[MII_BUS_ID_SIZE + 3];
1650 int phy_id;
43af940c 1651 int dev_id = fep->dev_id;
562d2f8c 1652
418bd0d4
BW		 1653 fep->phy_dev = NULL;
1654
6fcc040f
GU		 1655 /* check for attached phy */
1656 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1657 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1658 continue;
1659 if (fep->mii_bus->phy_map[phy_id] == NULL)
1660 continue;
1661 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1662 continue;
b5680e0b
SG		 1663 if (dev_id--)
1664 continue;
6fcc040f
GU		 1665 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1666 break;
e6b043d5 1667 }
1da177e4 1668
6fcc040f 1669 if (phy_id >= PHY_MAX_ADDR) {
31b7720c 1670 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
ea51ade9 1671 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
6fcc040f
GU		 1672 phy_id = 0;
1673 }
1674
a7ed07d5 1675 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
f9a8f83b 1676 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
230dec61 1677 fep->phy_interface);
6fcc040f 1678 if (IS_ERR(phy_dev)) {
31b7720c 1679 netdev_err(ndev, "could not attach to PHY\n");
6fcc040f 1680 return PTR_ERR(phy_dev);
e6b043d5 1681 }
1da177e4 1682
e6b043d5 1683 /* mask with MAC supported features */
baa70a5c 1684 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
230dec61 1685 phy_dev->supported &= PHY_GBIT_FEATURES;
b44592ff 1686 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
d1391930 1687#if !defined(CONFIG_M5272)
baa70a5c 1688 phy_dev->supported |= SUPPORTED_Pause;
d1391930 1689#endif
baa70a5c 1690 }
230dec61
SG		 1691 else
1692 phy_dev->supported &= PHY_BASIC_FEATURES;
1693
e6b043d5 1694 phy_dev->advertising = phy_dev->supported;
1da177e4 1695
e6b043d5
BW		 1696 fep->phy_dev = phy_dev;
1697 fep->link = 0;
1698 fep->full_duplex = 0;
1da177e4 1699
31b7720c
JP		 1700 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1701 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1702 fep->phy_dev->irq);
418bd0d4 1703
e6b043d5 1704 return 0;
1da177e4
LT		 1705}
1706
e6b043d5 1707static int fec_enet_mii_init(struct platform_device *pdev)
562d2f8c 1708{
b5680e0b 1709 static struct mii_bus *fec0_mii_bus;
c556167f
UKK		 1710 struct net_device *ndev = platform_get_drvdata(pdev);
1711 struct fec_enet_private *fep = netdev_priv(ndev);
b5680e0b
SG		 1712 const struct platform_device_id *id_entry =
1713 platform_get_device_id(fep->pdev);
e6b043d5 1714 int err = -ENXIO, i;
6b265293 1715
b5680e0b
SG		 1716 /*
1717 * The dual fec interfaces are not equivalent with enet-mac.
1718 * Here are the differences:
1719 *
1720 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1721 * - fec0 acts as the 1588 time master while fec1 is slave
1722 * - external phys can only be configured by fec0
1723 *
1724 * That is to say fec1 can not work independently. It only works
1725 * when fec0 is working. The reason behind this design is that the
1726 * second interface is added primarily for Switch mode.
1727 *
1728 * Because of the last point above, both phys are attached on fec0
1729 * mdio interface in board design, and need to be configured by
1730 * fec0 mii_bus.
1731 */
43af940c 1732 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
b5680e0b 1733 /* fec1 uses fec0 mii_bus */
e163cc97
LW		 1734 if (mii_cnt && fec0_mii_bus) {
1735 fep->mii_bus = fec0_mii_bus;
1736 mii_cnt++;
1737 return 0;
1738 }
1739 return -ENOENT;
b5680e0b
SG		 1740 }
1741
e6b043d5 1742 fep->mii_timeout = 0;
1da177e4 1743
e6b043d5
BW		 1744 /*
1745 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
230dec61
SG		 1746 *
1747 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1748 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1749 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1750 * document.
e6b043d5 1751 */
98a6eeb8 1752 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
230dec61
SG		 1753 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1754 fep->phy_speed--;
1755 fep->phy_speed <<= 1;
e6b043d5 1756 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1da177e4 1757
e6b043d5
BW		 1758 fep->mii_bus = mdiobus_alloc();
1759 if (fep->mii_bus == NULL) {
1760 err = -ENOMEM;
1761 goto err_out;
1da177e4
LT		 1762 }
1763
e6b043d5
BW		 1764 fep->mii_bus->name = "fec_enet_mii_bus";
1765 fep->mii_bus->read = fec_enet_mdio_read;
1766 fep->mii_bus->write = fec_enet_mdio_write;
391420f7
FF		 1767 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1768 pdev->name, fep->dev_id + 1);
e6b043d5
BW		 1769 fep->mii_bus->priv = fep;
1770 fep->mii_bus->parent = &pdev->dev;
1771
1772 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1773 if (!fep->mii_bus->irq) {
1774 err = -ENOMEM;
1775 goto err_out_free_mdiobus;
1da177e4
LT		 1776 }
1777
e6b043d5
BW		 1778 for (i = 0; i < PHY_MAX_ADDR; i++)
1779 fep->mii_bus->irq[i] = PHY_POLL;
1da177e4 1780
e6b043d5
BW		 1781 if (mdiobus_register(fep->mii_bus))
1782 goto err_out_free_mdio_irq;
1da177e4 1783
e163cc97
LW		 1784 mii_cnt++;
1785
b5680e0b
SG		 1786 /* save fec0 mii_bus */
1787 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1788 fec0_mii_bus = fep->mii_bus;
1789
e6b043d5 1790 return 0;
1da177e4 1791
e6b043d5
BW		 1792err_out_free_mdio_irq:
1793 kfree(fep->mii_bus->irq);
1794err_out_free_mdiobus:
1795 mdiobus_free(fep->mii_bus);
1796err_out:
1797 return err;
1da177e4
LT		 1798}
1799
e6b043d5 1800static void fec_enet_mii_remove(struct fec_enet_private *fep)
1da177e4 1801{
e163cc97
LW		 1802 if (--mii_cnt == 0) {
1803 mdiobus_unregister(fep->mii_bus);
1804 kfree(fep->mii_bus->irq);
1805 mdiobus_free(fep->mii_bus);
1806 }
1da177e4
LT		 1807}
1808
c556167f 1809static int fec_enet_get_settings(struct net_device *ndev,
e6b043d5 1810 struct ethtool_cmd *cmd)
1da177e4 1811{
c556167f 1812 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1813 struct phy_device *phydev = fep->phy_dev;
1da177e4 1814
e6b043d5
BW		 1815 if (!phydev)
1816 return -ENODEV;
1da177e4 1817
e6b043d5 1818 return phy_ethtool_gset(phydev, cmd);
1da177e4
LT		 1819}
1820
c556167f 1821static int fec_enet_set_settings(struct net_device *ndev,
e6b043d5 1822 struct ethtool_cmd *cmd)
1da177e4 1823{
c556167f 1824 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1825 struct phy_device *phydev = fep->phy_dev;
1da177e4 1826
e6b043d5
BW		 1827 if (!phydev)
1828 return -ENODEV;
1da177e4 1829
e6b043d5 1830 return phy_ethtool_sset(phydev, cmd);
1da177e4
LT		 1831}
1832
c556167f 1833static void fec_enet_get_drvinfo(struct net_device *ndev,
e6b043d5 1834 struct ethtool_drvinfo *info)
1da177e4 1835{
c556167f 1836 struct fec_enet_private *fep = netdev_priv(ndev);
6aa20a22 1837
7826d43f
JP		 1838 strlcpy(info->driver, fep->pdev->dev.driver->name,
1839 sizeof(info->driver));
1840 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1841 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1da177e4
LT		 1842}
1843
5ebae489
FL		 1844static int fec_enet_get_ts_info(struct net_device *ndev,
1845 struct ethtool_ts_info *info)
1846{
1847 struct fec_enet_private *fep = netdev_priv(ndev);
1848
1849 if (fep->bufdesc_ex) {
1850
1851 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1852 SOF_TIMESTAMPING_RX_SOFTWARE |
1853 SOF_TIMESTAMPING_SOFTWARE |
1854 SOF_TIMESTAMPING_TX_HARDWARE |
1855 SOF_TIMESTAMPING_RX_HARDWARE |
1856 SOF_TIMESTAMPING_RAW_HARDWARE;
1857 if (fep->ptp_clock)
1858 info->phc_index = ptp_clock_index(fep->ptp_clock);
1859 else
1860 info->phc_index = -1;
1861
1862 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1863 (1 << HWTSTAMP_TX_ON);
1864
1865 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1866 (1 << HWTSTAMP_FILTER_ALL);
1867 return 0;
1868 } else {
1869 return ethtool_op_get_ts_info(ndev, info);
1870 }
1871}
1872
d1391930
GR		 1873#if !defined(CONFIG_M5272)
1874
baa70a5c
FL		 1875static void fec_enet_get_pauseparam(struct net_device *ndev,
1876 struct ethtool_pauseparam *pause)
1877{
1878 struct fec_enet_private *fep = netdev_priv(ndev);
1879
1880 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1881 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1882 pause->rx_pause = pause->tx_pause;
1883}
1884
1885static int fec_enet_set_pauseparam(struct net_device *ndev,
1886 struct ethtool_pauseparam *pause)
1887{
1888 struct fec_enet_private *fep = netdev_priv(ndev);
1889
0b146ca8
RK		 1890 if (!fep->phy_dev)
1891 return -ENODEV;
1892
baa70a5c
FL		 1893 if (pause->tx_pause != pause->rx_pause) {
1894 netdev_info(ndev,
1895 "hardware only support enable/disable both tx and rx");
1896 return -EINVAL;
1897 }
1898
1899 fep->pause_flag = 0;
1900
1901 /* tx pause must be same as rx pause */
1902 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1903 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1904
1905 if (pause->rx_pause || pause->autoneg) {
1906 fep->phy_dev->supported |= ADVERTISED_Pause;
1907 fep->phy_dev->advertising |= ADVERTISED_Pause;
1908 } else {
1909 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1910 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1911 }
1912
1913 if (pause->autoneg) {
1914 if (netif_running(ndev))
1915 fec_stop(ndev);
1916 phy_start_aneg(fep->phy_dev);
1917 }
1918 if (netif_running(ndev))
9671a42e 1919 fec_restart(ndev, fep->full_duplex);
baa70a5c
FL		 1920
1921 return 0;
1922}
1923
38ae92dc
CH		 1924static const struct fec_stat {
1925 char name[ETH_GSTRING_LEN];
1926 u16 offset;
1927} fec_stats[] = {
1928 /* RMON TX */
1929 { "tx_dropped", RMON_T_DROP },
1930 { "tx_packets", RMON_T_PACKETS },
1931 { "tx_broadcast", RMON_T_BC_PKT },
1932 { "tx_multicast", RMON_T_MC_PKT },
1933 { "tx_crc_errors", RMON_T_CRC_ALIGN },
1934 { "tx_undersize", RMON_T_UNDERSIZE },
1935 { "tx_oversize", RMON_T_OVERSIZE },
1936 { "tx_fragment", RMON_T_FRAG },
1937 { "tx_jabber", RMON_T_JAB },
1938 { "tx_collision", RMON_T_COL },
1939 { "tx_64byte", RMON_T_P64 },
1940 { "tx_65to127byte", RMON_T_P65TO127 },
1941 { "tx_128to255byte", RMON_T_P128TO255 },
1942 { "tx_256to511byte", RMON_T_P256TO511 },
1943 { "tx_512to1023byte", RMON_T_P512TO1023 },
1944 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
1945 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
1946 { "tx_octets", RMON_T_OCTETS },
1947
1948 /* IEEE TX */
1949 { "IEEE_tx_drop", IEEE_T_DROP },
1950 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
1951 { "IEEE_tx_1col", IEEE_T_1COL },
1952 { "IEEE_tx_mcol", IEEE_T_MCOL },
1953 { "IEEE_tx_def", IEEE_T_DEF },
1954 { "IEEE_tx_lcol", IEEE_T_LCOL },
1955 { "IEEE_tx_excol", IEEE_T_EXCOL },
1956 { "IEEE_tx_macerr", IEEE_T_MACERR },
1957 { "IEEE_tx_cserr", IEEE_T_CSERR },
1958 { "IEEE_tx_sqe", IEEE_T_SQE },
1959 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
1960 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
1961
1962 /* RMON RX */
1963 { "rx_packets", RMON_R_PACKETS },
1964 { "rx_broadcast", RMON_R_BC_PKT },
1965 { "rx_multicast", RMON_R_MC_PKT },
1966 { "rx_crc_errors", RMON_R_CRC_ALIGN },
1967 { "rx_undersize", RMON_R_UNDERSIZE },
1968 { "rx_oversize", RMON_R_OVERSIZE },
1969 { "rx_fragment", RMON_R_FRAG },
1970 { "rx_jabber", RMON_R_JAB },
1971 { "rx_64byte", RMON_R_P64 },
1972 { "rx_65to127byte", RMON_R_P65TO127 },
1973 { "rx_128to255byte", RMON_R_P128TO255 },
1974 { "rx_256to511byte", RMON_R_P256TO511 },
1975 { "rx_512to1023byte", RMON_R_P512TO1023 },
1976 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
1977 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
1978 { "rx_octets", RMON_R_OCTETS },
1979
1980 /* IEEE RX */
1981 { "IEEE_rx_drop", IEEE_R_DROP },
1982 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
1983 { "IEEE_rx_crc", IEEE_R_CRC },
1984 { "IEEE_rx_align", IEEE_R_ALIGN },
1985 { "IEEE_rx_macerr", IEEE_R_MACERR },
1986 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
1987 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
1988};
1989
1990static void fec_enet_get_ethtool_stats(struct net_device *dev,
1991 struct ethtool_stats *stats, u64 *data)
1992{
1993 struct fec_enet_private *fep = netdev_priv(dev);
1994 int i;
1995
1996 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1997 data[i] = readl(fep->hwp + fec_stats[i].offset);
1998}
1999
2000static void fec_enet_get_strings(struct net_device *netdev,
2001 u32 stringset, u8 *data)
2002{
2003 int i;
2004 switch (stringset) {
2005 case ETH_SS_STATS:
2006 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2007 memcpy(data + i * ETH_GSTRING_LEN,
2008 fec_stats[i].name, ETH_GSTRING_LEN);
2009 break;
2010 }
2011}
2012
2013static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2014{
2015 switch (sset) {
2016 case ETH_SS_STATS:
2017 return ARRAY_SIZE(fec_stats);
2018 default:
2019 return -EOPNOTSUPP;
2020 }
2021}
d1391930 2022#endif /* !defined(CONFIG_M5272) */
38ae92dc 2023
32bc9b46
CH		 2024static int fec_enet_nway_reset(struct net_device *dev)
2025{
2026 struct fec_enet_private *fep = netdev_priv(dev);
2027 struct phy_device *phydev = fep->phy_dev;
2028
2029 if (!phydev)
2030 return -ENODEV;
2031
2032 return genphy_restart_aneg(phydev);
2033}
2034
9b07be4b 2035static const struct ethtool_ops fec_enet_ethtool_ops = {
d1391930 2036#if !defined(CONFIG_M5272)
baa70a5c
FL		 2037 .get_pauseparam = fec_enet_get_pauseparam,
2038 .set_pauseparam = fec_enet_set_pauseparam,
d1391930 2039#endif
e6b043d5
BW		 2040 .get_settings = fec_enet_get_settings,
2041 .set_settings = fec_enet_set_settings,
2042 .get_drvinfo = fec_enet_get_drvinfo,
2043 .get_link = ethtool_op_get_link,
5ebae489 2044 .get_ts_info = fec_enet_get_ts_info,
32bc9b46 2045 .nway_reset = fec_enet_nway_reset,
38ae92dc
CH		 2046#ifndef CONFIG_M5272
2047 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2048 .get_strings = fec_enet_get_strings,
2049 .get_sset_count = fec_enet_get_sset_count,
2050#endif
e6b043d5 2051};
1da177e4 2052
c556167f 2053static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1da177e4 2054{
c556167f 2055 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 2056 struct phy_device *phydev = fep->phy_dev;
1da177e4 2057
c556167f 2058 if (!netif_running(ndev))
e6b043d5 2059 return -EINVAL;
1da177e4 2060
e6b043d5
BW		 2061 if (!phydev)
2062 return -ENODEV;
2063
1d5244d0
BH		 2064 if (fep->bufdesc_ex) {
2065 if (cmd == SIOCSHWTSTAMP)
2066 return fec_ptp_set(ndev, rq);
2067 if (cmd == SIOCGHWTSTAMP)
2068 return fec_ptp_get(ndev, rq);
2069 }
ff43da86 2070
28b04113 2071 return phy_mii_ioctl(phydev, rq, cmd);
1da177e4
LT		 2072}
2073
c556167f 2074static void fec_enet_free_buffers(struct net_device *ndev)
f0b3fbea 2075{
c556167f 2076 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2077 unsigned int i;
f0b3fbea
SH		 2078 struct sk_buff *skb;
2079 struct bufdesc *bdp;
2080
2081 bdp = fep->rx_bd_base;
36e24e2e 2082 for (i = 0; i < fep->rx_ring_size; i++) {
f0b3fbea 2083 skb = fep->rx_skbuff[i];
730ee360
RK		 2084 fep->rx_skbuff[i] = NULL;
2085 if (skb) {
d1ab1f54 2086 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
f0b3fbea 2087 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
f0b3fbea 2088 dev_kfree_skb(skb);
730ee360 2089 }
36e24e2e 2090 bdp = fec_enet_get_nextdesc(bdp, fep);
f0b3fbea
SH		 2091 }
2092
2093 bdp = fep->tx_bd_base;
8b7c9efa 2094 for (i = 0; i < fep->tx_ring_size; i++) {
f0b3fbea 2095 kfree(fep->tx_bounce[i]);
8b7c9efa
RK		 2096 fep->tx_bounce[i] = NULL;
2097 skb = fep->tx_skbuff[i];
2098 fep->tx_skbuff[i] = NULL;
2099 dev_kfree_skb(skb);
2100 }
f0b3fbea
SH		 2101}
2102
c556167f 2103static int fec_enet_alloc_buffers(struct net_device *ndev)
f0b3fbea 2104{
c556167f 2105 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2106 unsigned int i;
f0b3fbea
SH		 2107 struct sk_buff *skb;
2108 struct bufdesc *bdp;
2109
2110 bdp = fep->rx_bd_base;
36e24e2e 2111 for (i = 0; i < fep->rx_ring_size; i++) {
730ee360
RK		 2112 dma_addr_t addr;
2113
b72061a3 2114 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
ffdce2cc
RK		 2115 if (!skb)
2116 goto err_alloc;
f0b3fbea 2117
730ee360 2118 addr = dma_map_single(&fep->pdev->dev, skb->data,
f0b3fbea 2119 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
730ee360
RK		 2120 if (dma_mapping_error(&fep->pdev->dev, addr)) {
2121 dev_kfree_skb(skb);
d842a31f
DFB		 2122 if (net_ratelimit())
2123 netdev_err(ndev, "Rx DMA memory map failed\n");
ffdce2cc 2124 goto err_alloc;
d842a31f 2125 }
730ee360
RK		 2126
2127 fep->rx_skbuff[i] = skb;
2128 bdp->cbd_bufaddr = addr;
f0b3fbea 2129 bdp->cbd_sc = BD_ENET_RX_EMPTY;
ff43da86
FL		 2130
2131 if (fep->bufdesc_ex) {
2132 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2133 ebdp->cbd_esc = BD_ENET_RX_INT;
2134 }
2135
36e24e2e 2136 bdp = fec_enet_get_nextdesc(bdp, fep);
f0b3fbea
SH		 2137 }
2138
2139 /* Set the last buffer to wrap. */
36e24e2e 2140 bdp = fec_enet_get_prevdesc(bdp, fep);
f0b3fbea
SH		 2141 bdp->cbd_sc |= BD_SC_WRAP;
2142
2143 bdp = fep->tx_bd_base;
36e24e2e 2144 for (i = 0; i < fep->tx_ring_size; i++) {
f0b3fbea 2145 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
ffdce2cc
RK		 2146 if (!fep->tx_bounce[i])
2147 goto err_alloc;
f0b3fbea
SH		 2148
2149 bdp->cbd_sc = 0;
2150 bdp->cbd_bufaddr = 0;
6605b730 2151
ff43da86
FL		 2152 if (fep->bufdesc_ex) {
2153 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
96d2222b 2154 ebdp->cbd_esc = BD_ENET_TX_INT;
ff43da86
FL		 2155 }
2156
36e24e2e 2157 bdp = fec_enet_get_nextdesc(bdp, fep);
f0b3fbea
SH		 2158 }
2159
2160 /* Set the last buffer to wrap. */
36e24e2e 2161 bdp = fec_enet_get_prevdesc(bdp, fep);
f0b3fbea
SH		 2162 bdp->cbd_sc |= BD_SC_WRAP;
2163
2164 return 0;
ffdce2cc
RK		 2165
2166 err_alloc:
2167 fec_enet_free_buffers(ndev);
2168 return -ENOMEM;
f0b3fbea
SH		 2169}
2170
1da177e4 2171static int
c556167f 2172fec_enet_open(struct net_device *ndev)
1da177e4 2173{
c556167f 2174 struct fec_enet_private *fep = netdev_priv(ndev);
f0b3fbea 2175 int ret;
1da177e4 2176
5bbde4d2 2177 pinctrl_pm_select_default_state(&fep->pdev->dev);
e8fcfcd5
NA		 2178 ret = fec_enet_clk_enable(ndev, true);
2179 if (ret)
2180 return ret;
2181
1da177e4
LT		 2182 /* I should reset the ring buffers here, but I don't yet know
2183 * a simple way to do that.
2184 */
1da177e4 2185
c556167f 2186 ret = fec_enet_alloc_buffers(ndev);
f0b3fbea
SH		 2187 if (ret)
2188 return ret;
2189
418bd0d4 2190 /* Probe and connect to PHY when open the interface */
c556167f 2191 ret = fec_enet_mii_probe(ndev);
418bd0d4 2192 if (ret) {
c556167f 2193 fec_enet_free_buffers(ndev);
418bd0d4
BW		 2194 return ret;
2195 }
ce5eaf02 2196
8ce5624f 2197 fec_restart(ndev, fep->full_duplex);
ce5eaf02 2198 napi_enable(&fep->napi);
e6b043d5 2199 phy_start(fep->phy_dev);
c556167f 2200 netif_start_queue(ndev);
22f6b860 2201 return 0;
1da177e4
LT		 2202}
2203
2204static int
c556167f 2205fec_enet_close(struct net_device *ndev)
1da177e4 2206{
c556167f 2207 struct fec_enet_private *fep = netdev_priv(ndev);
1da177e4 2208
d76cfae9
RK		 2209 phy_stop(fep->phy_dev);
2210
3f104c38 2211 napi_disable(&fep->napi);
b49cd504 2212 netif_tx_disable(ndev);
8bbbd3c1
RK		 2213 if (netif_device_present(ndev))
2214 fec_stop(ndev);
1da177e4 2215
635cf17c 2216 phy_disconnect(fep->phy_dev);
0b146ca8 2217 fep->phy_dev = NULL;
418bd0d4 2218
e8fcfcd5 2219 fec_enet_clk_enable(ndev, false);
5bbde4d2 2220 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
db8880bc 2221 fec_enet_free_buffers(ndev);
f0b3fbea 2222
1da177e4
LT		 2223 return 0;
2224}
2225
1da177e4
LT		 2226/* Set or clear the multicast filter for this adaptor.
2227 * Skeleton taken from sunlance driver.
2228 * The CPM Ethernet implementation allows Multicast as well as individual
2229 * MAC address filtering. Some of the drivers check to make sure it is
2230 * a group multicast address, and discard those that are not. I guess I
2231 * will do the same for now, but just remove the test if you want
2232 * individual filtering as well (do the upper net layers want or support
2233 * this kind of feature?).
2234 */
2235
2236#define HASH_BITS 6 /* #bits in hash */
2237#define CRC32_POLY 0xEDB88320
2238
c556167f 2239static void set_multicast_list(struct net_device *ndev)
1da177e4 2240{
c556167f 2241 struct fec_enet_private *fep = netdev_priv(ndev);
22bedad3 2242 struct netdev_hw_addr *ha;
48e2f183 2243 unsigned int i, bit, data, crc, tmp;
1da177e4
LT		 2244 unsigned char hash;
2245
c556167f 2246 if (ndev->flags & IFF_PROMISC) {
f44d6305
SH		 2247 tmp = readl(fep->hwp + FEC_R_CNTRL);
2248 tmp |= 0x8;
2249 writel(tmp, fep->hwp + FEC_R_CNTRL);
4e831836
SH		 2250 return;
2251 }
1da177e4 2252
4e831836
SH		 2253 tmp = readl(fep->hwp + FEC_R_CNTRL);
2254 tmp &= ~0x8;
2255 writel(tmp, fep->hwp + FEC_R_CNTRL);
2256
c556167f 2257 if (ndev->flags & IFF_ALLMULTI) {
4e831836
SH		 2258 /* Catch all multicast addresses, so set the
2259 * filter to all 1's
2260 */
2261 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2262 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2263
2264 return;
2265 }
2266
2267 /* Clear filter and add the addresses in hash register
2268 */
2269 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2270 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2271
c556167f 2272 netdev_for_each_mc_addr(ha, ndev) {
4e831836
SH		 2273 /* calculate crc32 value of mac address */
2274 crc = 0xffffffff;
2275
c556167f 2276 for (i = 0; i < ndev->addr_len; i++) {
22bedad3 2277 data = ha->addr[i];
4e831836
SH		 2278 for (bit = 0; bit < 8; bit++, data >>= 1) {
2279 crc = (crc >> 1) ^
2280 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1da177e4
LT		 2281 }
2282 }
4e831836
SH		 2283
2284 /* only upper 6 bits (HASH_BITS) are used
2285 * which point to specific bit in he hash registers
2286 */
2287 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2288
2289 if (hash > 31) {
2290 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2291 tmp |= 1 << (hash - 32);
2292 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2293 } else {
2294 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2295 tmp |= 1 << hash;
2296 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2297 }
1da177e4
LT		 2298 }
2299}
2300
22f6b860 2301/* Set a MAC change in hardware. */
009fda83 2302static int
c556167f 2303fec_set_mac_address(struct net_device *ndev, void *p)
1da177e4 2304{
c556167f 2305 struct fec_enet_private *fep = netdev_priv(ndev);
009fda83
SH		 2306 struct sockaddr *addr = p;
2307
44934fac
LS		 2308 if (addr) {
2309 if (!is_valid_ether_addr(addr->sa_data))
2310 return -EADDRNOTAVAIL;
2311 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2312 }
1da177e4 2313
c556167f
UKK		 2314 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2315 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
f44d6305 2316 fep->hwp + FEC_ADDR_LOW);
c556167f 2317 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
7cff0943 2318 fep->hwp + FEC_ADDR_HIGH);
009fda83 2319 return 0;
1da177e4
LT		 2320}
2321
7f5c6add 2322#ifdef CONFIG_NET_POLL_CONTROLLER
49ce9c2c
BH		 2323/**
2324 * fec_poll_controller - FEC Poll controller function
7f5c6add
XJ		 2325 * @dev: The FEC network adapter
2326 *
2327 * Polled functionality used by netconsole and others in non interrupt mode
2328 *
2329 */
47a5247f 2330static void fec_poll_controller(struct net_device *dev)
7f5c6add
XJ		 2331{
2332 int i;
2333 struct fec_enet_private *fep = netdev_priv(dev);
2334
2335 for (i = 0; i < FEC_IRQ_NUM; i++) {
2336 if (fep->irq[i] > 0) {
2337 disable_irq(fep->irq[i]);
2338 fec_enet_interrupt(fep->irq[i], dev);
2339 enable_irq(fep->irq[i]);
2340 }
2341 }
2342}
2343#endif
2344
4c09eed9
JB		 2345static int fec_set_features(struct net_device *netdev,
2346 netdev_features_t features)
2347{
2348 struct fec_enet_private *fep = netdev_priv(netdev);
2349 netdev_features_t changed = features ^ netdev->features;
2350
2351 netdev->features = features;
2352
2353 /* Receive checksum has been changed */
2354 if (changed & NETIF_F_RXCSUM) {
2355 if (features & NETIF_F_RXCSUM)
2356 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2357 else
2358 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
2359
2360 if (netif_running(netdev)) {
2361 fec_stop(netdev);
2362 fec_restart(netdev, fep->phy_dev->duplex);
2363 netif_wake_queue(netdev);
4c09eed9
JB		 2364 }
2365 }
2366
2367 return 0;
2368}
2369
009fda83
SH		 2370static const struct net_device_ops fec_netdev_ops = {
2371 .ndo_open = fec_enet_open,
2372 .ndo_stop = fec_enet_close,
2373 .ndo_start_xmit = fec_enet_start_xmit,
afc4b13d 2374 .ndo_set_rx_mode = set_multicast_list,
635ecaa7 2375 .ndo_change_mtu = eth_change_mtu,
009fda83
SH		 2376 .ndo_validate_addr = eth_validate_addr,
2377 .ndo_tx_timeout = fec_timeout,
2378 .ndo_set_mac_address = fec_set_mac_address,
db8880bc 2379 .ndo_do_ioctl = fec_enet_ioctl,
7f5c6add
XJ		 2380#ifdef CONFIG_NET_POLL_CONTROLLER
2381 .ndo_poll_controller = fec_poll_controller,
2382#endif
4c09eed9 2383 .ndo_set_features = fec_set_features,
009fda83
SH		 2384};
2385
1da177e4
LT		 2386 /*
2387 * XXX: We need to clean up on failure exits here.
ead73183 2388 *
1da177e4 2389 */
c556167f 2390static int fec_enet_init(struct net_device *ndev)
1da177e4 2391{
c556167f 2392 struct fec_enet_private *fep = netdev_priv(ndev);
48496255
SG		 2393 const struct platform_device_id *id_entry =
2394 platform_get_device_id(fep->pdev);
f0b3fbea 2395 struct bufdesc *cbd_base;
55d0218a
NA		 2396 int bd_size;
2397
2398 /* init the tx & rx ring size */
2399 fep->tx_ring_size = TX_RING_SIZE;
2400 fep->rx_ring_size = RX_RING_SIZE;
2401
79f33912
NA		 2402 fep->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2403 fep->tx_wake_threshold = (fep->tx_ring_size - fep->tx_stop_threshold) / 2;
2404
55d0218a
NA		 2405 if (fep->bufdesc_ex)
2406 fep->bufdesc_size = sizeof(struct bufdesc_ex);
2407 else
2408 fep->bufdesc_size = sizeof(struct bufdesc);
2409 bd_size = (fep->tx_ring_size + fep->rx_ring_size) *
2410 fep->bufdesc_size;
1da177e4 2411
8d4dd5cf 2412 /* Allocate memory for buffer descriptors. */
55d0218a 2413 cbd_base = dma_alloc_coherent(NULL, bd_size, &fep->bd_dma,
d0320f75
JP		 2414 GFP_KERNEL);
2415 if (!cbd_base)
562d2f8c 2416 return -ENOMEM;
562d2f8c 2417
79f33912
NA		 2418 fep->tso_hdrs = dma_alloc_coherent(NULL, fep->tx_ring_size * TSO_HEADER_SIZE,
2419 &fep->tso_hdrs_dma, GFP_KERNEL);
2420 if (!fep->tso_hdrs) {
2421 dma_free_coherent(NULL, bd_size, cbd_base, fep->bd_dma);
2422 return -ENOMEM;
2423 }
2424
14109a59 2425 memset(cbd_base, 0, PAGE_SIZE);
3b2b74ca 2426
c556167f 2427 fep->netdev = ndev;
1da177e4 2428
49da97dc 2429 /* Get the Ethernet address */
c556167f 2430 fec_get_mac(ndev);
44934fac
LS		 2431 /* make sure MAC we just acquired is programmed into the hw */
2432 fec_set_mac_address(ndev, NULL);
1da177e4 2433
8d4dd5cf 2434 /* Set receive and transmit descriptor base. */
1da177e4 2435 fep->rx_bd_base = cbd_base;
55d0218a 2436 if (fep->bufdesc_ex)
ff43da86 2437 fep->tx_bd_base = (struct bufdesc *)
36e24e2e 2438 (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size);
55d0218a 2439 else
36e24e2e 2440 fep->tx_bd_base = cbd_base + fep->rx_ring_size;
1da177e4 2441
22f6b860 2442 /* The FEC Ethernet specific entries in the device structure */
c556167f
UKK		 2443 ndev->watchdog_timeo = TX_TIMEOUT;
2444 ndev->netdev_ops = &fec_netdev_ops;
2445 ndev->ethtool_ops = &fec_enet_ethtool_ops;
633e7533 2446
dc975382 2447 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
322555f5 2448 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
dc975382 2449
09d1e541 2450 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN)
cdffcf1b
JB		 2451 /* enable hw VLAN support */
2452 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
cdffcf1b 2453
48496255 2454 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
79f33912
NA		 2455 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
2456
48496255
SG		 2457 /* enable hw accelerator */
2458 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
79f33912 2459 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
48496255
SG		 2460 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2461 }
4c09eed9 2462
09d1e541
NA		 2463 ndev->hw_features = ndev->features;
2464
c556167f 2465 fec_restart(ndev, 0);
1da177e4 2466
1da177e4
LT		 2467 return 0;
2468}
2469
ca2cc333 2470#ifdef CONFIG_OF
33897cc8 2471static void fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 2472{
2473 int err, phy_reset;
a3caad0a 2474 int msec = 1;
ca2cc333
SG		 2475 struct device_node *np = pdev->dev.of_node;
2476
2477 if (!np)
a9b2c8ef 2478 return;
ca2cc333 2479
a3caad0a
SG		 2480 of_property_read_u32(np, "phy-reset-duration", &msec);
2481 /* A sane reset duration should not be longer than 1s */
2482 if (msec > 1000)
2483 msec = 1;
2484
ca2cc333 2485 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
07dcf8e9
FE		 2486 if (!gpio_is_valid(phy_reset))
2487 return;
2488
119fc007
SG		 2489 err = devm_gpio_request_one(&pdev->dev, phy_reset,
2490 GPIOF_OUT_INIT_LOW, "phy-reset");
ca2cc333 2491 if (err) {
07dcf8e9 2492 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
a9b2c8ef 2493 return;
ca2cc333 2494 }
a3caad0a 2495 msleep(msec);
ca2cc333 2496 gpio_set_value(phy_reset, 1);
ca2cc333
SG		 2497}
2498#else /* CONFIG_OF */
0c7768a0 2499static void fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 2500{
2501 /*
2502 * In case of platform probe, the reset has been done
2503 * by machine code.
2504 */
ca2cc333
SG		 2505}
2506#endif /* CONFIG_OF */
2507
33897cc8 2508static int
ead73183
SH		 2509fec_probe(struct platform_device *pdev)
2510{
2511 struct fec_enet_private *fep;
5eb32bd0 2512 struct fec_platform_data *pdata;
ead73183
SH		 2513 struct net_device *ndev;
2514 int i, irq, ret = 0;
2515 struct resource *r;
ca2cc333 2516 const struct of_device_id *of_id;
43af940c 2517 static int dev_id;
ca2cc333
SG		 2518
2519 of_id = of_match_device(fec_dt_ids, &pdev->dev);
2520 if (of_id)
2521 pdev->id_entry = of_id->data;
ead73183 2522
ead73183
SH		 2523 /* Init network device */
2524 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
83e519b6
FE		 2525 if (!ndev)
2526 return -ENOMEM;
ead73183
SH		 2527
2528 SET_NETDEV_DEV(ndev, &pdev->dev);
2529
2530 /* setup board info structure */
2531 fep = netdev_priv(ndev);
ead73183 2532
d1391930 2533#if !defined(CONFIG_M5272)
baa70a5c
FL		 2534 /* default enable pause frame auto negotiation */
2535 if (pdev->id_entry &&
2536 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
2537 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
d1391930 2538#endif
baa70a5c 2539
5bbde4d2
NA		 2540 /* Select default pin state */
2541 pinctrl_pm_select_default_state(&pdev->dev);
2542
399db75b 2543 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
941e173a
TB		 2544 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
2545 if (IS_ERR(fep->hwp)) {
2546 ret = PTR_ERR(fep->hwp);
2547 goto failed_ioremap;
2548 }
2549
e6b043d5 2550 fep->pdev = pdev;
43af940c 2551 fep->dev_id = dev_id++;
ead73183 2552
ff43da86
FL		 2553 fep->bufdesc_ex = 0;
2554
ead73183
SH		 2555 platform_set_drvdata(pdev, ndev);
2556
6c5f7808 2557 ret = of_get_phy_mode(pdev->dev.of_node);
ca2cc333 2558 if (ret < 0) {
94660ba0 2559 pdata = dev_get_platdata(&pdev->dev);
ca2cc333
SG		 2560 if (pdata)
2561 fep->phy_interface = pdata->phy;
2562 else
2563 fep->phy_interface = PHY_INTERFACE_MODE_MII;
2564 } else {
2565 fep->phy_interface = ret;
2566 }
2567
f4d40de3
SH		 2568 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2569 if (IS_ERR(fep->clk_ipg)) {
2570 ret = PTR_ERR(fep->clk_ipg);
ead73183
SH		 2571 goto failed_clk;
2572 }
f4d40de3
SH		 2573
2574 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2575 if (IS_ERR(fep->clk_ahb)) {
2576 ret = PTR_ERR(fep->clk_ahb);
2577 goto failed_clk;
2578 }
2579
daa7d392
WS		 2580 /* enet_out is optional, depends on board */
2581 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
2582 if (IS_ERR(fep->clk_enet_out))
2583 fep->clk_enet_out = NULL;
2584
6605b730 2585 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
e2f8d555
FE		 2586 fep->bufdesc_ex =
2587 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
6605b730 2588 if (IS_ERR(fep->clk_ptp)) {
c29dc2d7 2589 fep->clk_ptp = NULL;
ff43da86 2590 fep->bufdesc_ex = 0;
6605b730 2591 }
6605b730 2592
e8fcfcd5 2593 ret = fec_enet_clk_enable(ndev, true);
13a097bd
FE		 2594 if (ret)
2595 goto failed_clk;
2596
f4e9f3d2
FE		 2597 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
2598 if (!IS_ERR(fep->reg_phy)) {
2599 ret = regulator_enable(fep->reg_phy);
5fa9c0fe
SG		 2600 if (ret) {
2601 dev_err(&pdev->dev,
2602 "Failed to enable phy regulator: %d\n", ret);
2603 goto failed_regulator;
2604 }
f6a4d607
FE		 2605 } else {
2606 fep->reg_phy = NULL;
5fa9c0fe
SG		 2607 }
2608
2ca9b2aa
SG		 2609 fec_reset_phy(pdev);
2610
e2f8d555 2611 if (fep->bufdesc_ex)
ca162a82 2612 fec_ptp_init(pdev);
e2f8d555
FE		 2613
2614 ret = fec_enet_init(ndev);
2615 if (ret)
2616 goto failed_init;
2617
2618 for (i = 0; i < FEC_IRQ_NUM; i++) {
2619 irq = platform_get_irq(pdev, i);
2620 if (irq < 0) {
2621 if (i)
2622 break;
2623 ret = irq;
2624 goto failed_irq;
2625 }
0d9b2ab1 2626 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
44a272dd 2627 0, pdev->name, ndev);
0d9b2ab1 2628 if (ret)
e2f8d555 2629 goto failed_irq;
e2f8d555
FE		 2630 }
2631
e6b043d5
BW		 2632 ret = fec_enet_mii_init(pdev);
2633 if (ret)
2634 goto failed_mii_init;
2635
03c698c9
OS		 2636 /* Carrier starts down, phylib will bring it up */
2637 netif_carrier_off(ndev);
e8fcfcd5 2638 fec_enet_clk_enable(ndev, false);
5bbde4d2 2639 pinctrl_pm_select_sleep_state(&pdev->dev);
03c698c9 2640
ead73183
SH		 2641 ret = register_netdev(ndev);
2642 if (ret)
2643 goto failed_register;
2644
eb1d0640
FE		 2645 if (fep->bufdesc_ex && fep->ptp_clock)
2646 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
2647
54309fa6 2648 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
ead73183
SH		 2649 return 0;
2650
2651failed_register:
e6b043d5
BW		 2652 fec_enet_mii_remove(fep);
2653failed_mii_init:
7a2bbd8d 2654failed_irq:
7a2bbd8d 2655failed_init:
f6a4d607
FE		 2656 if (fep->reg_phy)
2657 regulator_disable(fep->reg_phy);
5fa9c0fe 2658failed_regulator:
e8fcfcd5 2659 fec_enet_clk_enable(ndev, false);
ead73183 2660failed_clk:
ead73183
SH		 2661failed_ioremap:
2662 free_netdev(ndev);
2663
2664 return ret;
2665}
2666
33897cc8 2667static int
ead73183
SH		 2668fec_drv_remove(struct platform_device *pdev)
2669{
2670 struct net_device *ndev = platform_get_drvdata(pdev);
2671 struct fec_enet_private *fep = netdev_priv(ndev);
2672
54309fa6 2673 cancel_delayed_work_sync(&(fep->delay_work.delay_work));
e163cc97 2674 unregister_netdev(ndev);
e6b043d5 2675 fec_enet_mii_remove(fep);
6605b730 2676 del_timer_sync(&fep->time_keep);
f6a4d607
FE		 2677 if (fep->reg_phy)
2678 regulator_disable(fep->reg_phy);
6605b730
FL		 2679 if (fep->ptp_clock)
2680 ptp_clock_unregister(fep->ptp_clock);
e8fcfcd5 2681 fec_enet_clk_enable(ndev, false);
ead73183 2682 free_netdev(ndev);
28e2188e 2683
ead73183
SH		 2684 return 0;
2685}
2686
bf7bfd7f 2687#ifdef CONFIG_PM_SLEEP
ead73183 2688static int
87cad5c3 2689fec_suspend(struct device *dev)
ead73183 2690{
87cad5c3 2691 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 2692 struct fec_enet_private *fep = netdev_priv(ndev);
ead73183 2693
da1774e5 2694 rtnl_lock();
04e5216d 2695 if (netif_running(ndev)) {
d76cfae9 2696 phy_stop(fep->phy_dev);
04e5216d
UKK		 2697 fec_stop(ndev);
2698 netif_device_detach(ndev);
ead73183 2699 }
da1774e5
RK		 2700 rtnl_unlock();
2701
e8fcfcd5 2702 fec_enet_clk_enable(ndev, false);
5bbde4d2 2703 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
04e5216d 2704
238f7bc7
FE		 2705 if (fep->reg_phy)
2706 regulator_disable(fep->reg_phy);
2707
ead73183
SH		 2708 return 0;
2709}
2710
2711static int
87cad5c3 2712fec_resume(struct device *dev)
ead73183 2713{
87cad5c3 2714 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 2715 struct fec_enet_private *fep = netdev_priv(ndev);
238f7bc7
FE		 2716 int ret;
2717
2718 if (fep->reg_phy) {
2719 ret = regulator_enable(fep->reg_phy);
2720 if (ret)
2721 return ret;
2722 }
ead73183 2723
5bbde4d2 2724 pinctrl_pm_select_default_state(&fep->pdev->dev);
e8fcfcd5 2725 ret = fec_enet_clk_enable(ndev, true);
13a097bd 2726 if (ret)
e8fcfcd5 2727 goto failed_clk;
13a097bd 2728
da1774e5 2729 rtnl_lock();
04e5216d
UKK		 2730 if (netif_running(ndev)) {
2731 fec_restart(ndev, fep->full_duplex);
2732 netif_device_attach(ndev);
d76cfae9 2733 phy_start(fep->phy_dev);
ead73183 2734 }
da1774e5 2735 rtnl_unlock();
04e5216d 2736
ead73183 2737 return 0;
13a097bd 2738
e8fcfcd5 2739failed_clk:
13a097bd
FE		 2740 if (fep->reg_phy)
2741 regulator_disable(fep->reg_phy);
2742 return ret;
ead73183 2743}
bf7bfd7f 2744#endif /* CONFIG_PM_SLEEP */
ead73183 2745
bf7bfd7f 2746static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
59d4289b 2747
ead73183
SH		 2748static struct platform_driver fec_driver = {
2749 .driver = {
b5680e0b 2750 .name = DRIVER_NAME,
87cad5c3 2751 .owner = THIS_MODULE,
87cad5c3 2752 .pm = &fec_pm_ops,
ca2cc333 2753 .of_match_table = fec_dt_ids,
ead73183 2754 },
b5680e0b 2755 .id_table = fec_devtype,
87cad5c3 2756 .probe = fec_probe,
33897cc8 2757 .remove = fec_drv_remove,
ead73183
SH		 2758};
2759
aaca2377 2760module_platform_driver(fec_driver);
1da177e4 2761
f8c0aca9 2762MODULE_ALIAS("platform:"DRIVER_NAME);
1da177e4 2763MODULE_LICENSE("GPL");
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