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net: hns3: Add some interface for the support of DCB feature
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
46a3df9f
S		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/acpi.h>
11#include <linux/device.h>
12#include <linux/etherdevice.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/netdevice.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
20
21#include "hclge_cmd.h"
22#include "hclge_main.h"
23#include "hclge_mdio.h"
24#include "hclge_tm.h"
25#include "hnae3.h"
26
27#define HCLGE_NAME "hclge"
28#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
29#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
30#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
31#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
32
46a3df9f
S		 33static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
34 enum hclge_mta_dmac_sel_type mta_mac_sel,
35 bool enable);
36static int hclge_init_vlan_config(struct hclge_dev *hdev);
37
38static struct hnae3_ae_algo ae_algo;
39
40static const struct pci_device_id ae_algo_pci_tbl[] = {
41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 48 /* required last entry */
46a3df9f
S		 49 {0, }
50};
51
52static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
53 "Mac Loopback test",
54 "Serdes Loopback test",
55 "Phy Loopback test"
56};
57
58static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
59 {"igu_rx_oversize_pkt",
60 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
61 {"igu_rx_undersize_pkt",
62 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
63 {"igu_rx_out_all_pkt",
64 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
65 {"igu_rx_uni_pkt",
66 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
67 {"igu_rx_multi_pkt",
68 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
69 {"igu_rx_broad_pkt",
70 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
71 {"egu_tx_out_all_pkt",
72 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
73 {"egu_tx_uni_pkt",
74 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
75 {"egu_tx_multi_pkt",
76 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
77 {"egu_tx_broad_pkt",
78 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
79 {"ssu_ppp_mac_key_num",
80 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
81 {"ssu_ppp_host_key_num",
82 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
83 {"ppp_ssu_mac_rlt_num",
84 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
85 {"ppp_ssu_host_rlt_num",
86 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
87 {"ssu_tx_in_num",
88 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
89 {"ssu_tx_out_num",
90 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
91 {"ssu_rx_in_num",
92 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
93 {"ssu_rx_out_num",
94 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
95};
96
97static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
98 {"igu_rx_err_pkt",
99 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
100 {"igu_rx_no_eof_pkt",
101 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
102 {"igu_rx_no_sof_pkt",
103 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
104 {"egu_tx_1588_pkt",
105 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
106 {"ssu_full_drop_num",
107 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
108 {"ssu_part_drop_num",
109 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
110 {"ppp_key_drop_num",
111 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
112 {"ppp_rlt_drop_num",
113 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
114 {"ssu_key_drop_num",
115 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
116 {"pkt_curr_buf_cnt",
117 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
118 {"qcn_fb_rcv_cnt",
119 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
120 {"qcn_fb_drop_cnt",
121 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
122 {"qcn_fb_invaild_cnt",
123 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
124 {"rx_packet_tc0_in_cnt",
125 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
126 {"rx_packet_tc1_in_cnt",
127 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
128 {"rx_packet_tc2_in_cnt",
129 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
130 {"rx_packet_tc3_in_cnt",
131 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
132 {"rx_packet_tc4_in_cnt",
133 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
134 {"rx_packet_tc5_in_cnt",
135 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
136 {"rx_packet_tc6_in_cnt",
137 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
138 {"rx_packet_tc7_in_cnt",
139 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
140 {"rx_packet_tc0_out_cnt",
141 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
142 {"rx_packet_tc1_out_cnt",
143 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
144 {"rx_packet_tc2_out_cnt",
145 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
146 {"rx_packet_tc3_out_cnt",
147 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
148 {"rx_packet_tc4_out_cnt",
149 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
150 {"rx_packet_tc5_out_cnt",
151 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
152 {"rx_packet_tc6_out_cnt",
153 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
154 {"rx_packet_tc7_out_cnt",
155 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
156 {"tx_packet_tc0_in_cnt",
157 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
158 {"tx_packet_tc1_in_cnt",
159 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
160 {"tx_packet_tc2_in_cnt",
161 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
162 {"tx_packet_tc3_in_cnt",
163 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
164 {"tx_packet_tc4_in_cnt",
165 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
166 {"tx_packet_tc5_in_cnt",
167 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
168 {"tx_packet_tc6_in_cnt",
169 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
170 {"tx_packet_tc7_in_cnt",
171 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
172 {"tx_packet_tc0_out_cnt",
173 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
174 {"tx_packet_tc1_out_cnt",
175 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
176 {"tx_packet_tc2_out_cnt",
177 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
178 {"tx_packet_tc3_out_cnt",
179 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
180 {"tx_packet_tc4_out_cnt",
181 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
182 {"tx_packet_tc5_out_cnt",
183 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
184 {"tx_packet_tc6_out_cnt",
185 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
186 {"tx_packet_tc7_out_cnt",
187 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
188 {"pkt_curr_buf_tc0_cnt",
189 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
190 {"pkt_curr_buf_tc1_cnt",
191 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
192 {"pkt_curr_buf_tc2_cnt",
193 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
194 {"pkt_curr_buf_tc3_cnt",
195 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
196 {"pkt_curr_buf_tc4_cnt",
197 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
198 {"pkt_curr_buf_tc5_cnt",
199 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
200 {"pkt_curr_buf_tc6_cnt",
201 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
202 {"pkt_curr_buf_tc7_cnt",
203 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
204 {"mb_uncopy_num",
205 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
206 {"lo_pri_unicast_rlt_drop_num",
207 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
208 {"hi_pri_multicast_rlt_drop_num",
209 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
210 {"lo_pri_multicast_rlt_drop_num",
211 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
212 {"rx_oq_drop_pkt_cnt",
213 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
214 {"tx_oq_drop_pkt_cnt",
215 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
216 {"nic_l2_err_drop_pkt_cnt",
217 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
218 {"roc_l2_err_drop_pkt_cnt",
219 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
220};
221
222static const struct hclge_comm_stats_str g_mac_stats_string[] = {
223 {"mac_tx_mac_pause_num",
224 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
225 {"mac_rx_mac_pause_num",
226 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
227 {"mac_tx_pfc_pri0_pkt_num",
228 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
229 {"mac_tx_pfc_pri1_pkt_num",
230 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
231 {"mac_tx_pfc_pri2_pkt_num",
232 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
233 {"mac_tx_pfc_pri3_pkt_num",
234 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
235 {"mac_tx_pfc_pri4_pkt_num",
236 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
237 {"mac_tx_pfc_pri5_pkt_num",
238 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
239 {"mac_tx_pfc_pri6_pkt_num",
240 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
241 {"mac_tx_pfc_pri7_pkt_num",
242 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
243 {"mac_rx_pfc_pri0_pkt_num",
244 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
245 {"mac_rx_pfc_pri1_pkt_num",
246 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
247 {"mac_rx_pfc_pri2_pkt_num",
248 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
249 {"mac_rx_pfc_pri3_pkt_num",
250 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
251 {"mac_rx_pfc_pri4_pkt_num",
252 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
253 {"mac_rx_pfc_pri5_pkt_num",
254 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
255 {"mac_rx_pfc_pri6_pkt_num",
256 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
257 {"mac_rx_pfc_pri7_pkt_num",
258 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
259 {"mac_tx_total_pkt_num",
260 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
261 {"mac_tx_total_oct_num",
262 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
263 {"mac_tx_good_pkt_num",
264 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
265 {"mac_tx_bad_pkt_num",
266 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
267 {"mac_tx_good_oct_num",
268 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
269 {"mac_tx_bad_oct_num",
270 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
271 {"mac_tx_uni_pkt_num",
272 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
273 {"mac_tx_multi_pkt_num",
274 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
275 {"mac_tx_broad_pkt_num",
276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
277 {"mac_tx_undersize_pkt_num",
278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
279 {"mac_tx_overrsize_pkt_num",
280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_overrsize_pkt_num)},
281 {"mac_tx_64_oct_pkt_num",
282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
283 {"mac_tx_65_127_oct_pkt_num",
284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
285 {"mac_tx_128_255_oct_pkt_num",
286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
287 {"mac_tx_256_511_oct_pkt_num",
288 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
289 {"mac_tx_512_1023_oct_pkt_num",
290 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
291 {"mac_tx_1024_1518_oct_pkt_num",
292 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
293 {"mac_tx_1519_max_oct_pkt_num",
294 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num)},
295 {"mac_rx_total_pkt_num",
296 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
297 {"mac_rx_total_oct_num",
298 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
299 {"mac_rx_good_pkt_num",
300 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
301 {"mac_rx_bad_pkt_num",
302 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
303 {"mac_rx_good_oct_num",
304 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
305 {"mac_rx_bad_oct_num",
306 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
307 {"mac_rx_uni_pkt_num",
308 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
309 {"mac_rx_multi_pkt_num",
310 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
311 {"mac_rx_broad_pkt_num",
312 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
313 {"mac_rx_undersize_pkt_num",
314 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
315 {"mac_rx_overrsize_pkt_num",
316 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_overrsize_pkt_num)},
317 {"mac_rx_64_oct_pkt_num",
318 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
319 {"mac_rx_65_127_oct_pkt_num",
320 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
321 {"mac_rx_128_255_oct_pkt_num",
322 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
323 {"mac_rx_256_511_oct_pkt_num",
324 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
325 {"mac_rx_512_1023_oct_pkt_num",
326 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
327 {"mac_rx_1024_1518_oct_pkt_num",
328 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
329 {"mac_rx_1519_max_oct_pkt_num",
330 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num)},
331
332 {"mac_trans_fragment_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_fragment_pkt_num)},
334 {"mac_trans_undermin_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_undermin_pkt_num)},
336 {"mac_trans_jabber_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_jabber_pkt_num)},
338 {"mac_trans_err_all_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_err_all_pkt_num)},
340 {"mac_trans_from_app_good_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_good_pkt_num)},
342 {"mac_trans_from_app_bad_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_bad_pkt_num)},
344 {"mac_rcv_fragment_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fragment_pkt_num)},
346 {"mac_rcv_undermin_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_undermin_pkt_num)},
348 {"mac_rcv_jabber_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_jabber_pkt_num)},
350 {"mac_rcv_fcs_err_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fcs_err_pkt_num)},
352 {"mac_rcv_send_app_good_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_good_pkt_num)},
354 {"mac_rcv_send_app_bad_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_bad_pkt_num)}
356};
357
358static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
359{
360#define HCLGE_64_BIT_CMD_NUM 5
361#define HCLGE_64_BIT_RTN_DATANUM 4
362 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
363 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
364 u64 *desc_data;
365 int i, k, n;
366 int ret;
367
368 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
369 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
370 if (ret) {
371 dev_err(&hdev->pdev->dev,
372 "Get 64 bit pkt stats fail, status = %d.\n", ret);
373 return ret;
374 }
375
376 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
377 if (unlikely(i == 0)) {
378 desc_data = (u64 *)(&desc[i].data[0]);
379 n = HCLGE_64_BIT_RTN_DATANUM - 1;
380 } else {
381 desc_data = (u64 *)(&desc[i]);
382 n = HCLGE_64_BIT_RTN_DATANUM;
383 }
384 for (k = 0; k < n; k++) {
385 *data++ += cpu_to_le64(*desc_data);
386 desc_data++;
387 }
388 }
389
390 return 0;
391}
392
393static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
394{
395 stats->pkt_curr_buf_cnt = 0;
396 stats->pkt_curr_buf_tc0_cnt = 0;
397 stats->pkt_curr_buf_tc1_cnt = 0;
398 stats->pkt_curr_buf_tc2_cnt = 0;
399 stats->pkt_curr_buf_tc3_cnt = 0;
400 stats->pkt_curr_buf_tc4_cnt = 0;
401 stats->pkt_curr_buf_tc5_cnt = 0;
402 stats->pkt_curr_buf_tc6_cnt = 0;
403 stats->pkt_curr_buf_tc7_cnt = 0;
404}
405
406static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
407{
408#define HCLGE_32_BIT_CMD_NUM 8
409#define HCLGE_32_BIT_RTN_DATANUM 8
410
411 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
412 struct hclge_32_bit_stats *all_32_bit_stats;
413 u32 *desc_data;
414 int i, k, n;
415 u64 *data;
416 int ret;
417
418 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
419 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
420
421 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
422 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
423 if (ret) {
424 dev_err(&hdev->pdev->dev,
425 "Get 32 bit pkt stats fail, status = %d.\n", ret);
426
427 return ret;
428 }
429
430 hclge_reset_partial_32bit_counter(all_32_bit_stats);
431 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
432 if (unlikely(i == 0)) {
433 all_32_bit_stats->igu_rx_err_pkt +=
434 cpu_to_le32(desc[i].data[0]);
435 all_32_bit_stats->igu_rx_no_eof_pkt +=
436 cpu_to_le32(desc[i].data[1] & 0xffff);
437 all_32_bit_stats->igu_rx_no_sof_pkt +=
438 cpu_to_le32((desc[i].data[1] >> 16) & 0xffff);
439
440 desc_data = (u32 *)(&desc[i].data[2]);
441 n = HCLGE_32_BIT_RTN_DATANUM - 4;
442 } else {
443 desc_data = (u32 *)(&desc[i]);
444 n = HCLGE_32_BIT_RTN_DATANUM;
445 }
446 for (k = 0; k < n; k++) {
447 *data++ += cpu_to_le32(*desc_data);
448 desc_data++;
449 }
450 }
451
452 return 0;
453}
454
455static int hclge_mac_update_stats(struct hclge_dev *hdev)
456{
457#define HCLGE_MAC_CMD_NUM 17
458#define HCLGE_RTN_DATA_NUM 4
459
460 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
461 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
462 u64 *desc_data;
463 int i, k, n;
464 int ret;
465
466 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
467 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
468 if (ret) {
469 dev_err(&hdev->pdev->dev,
470 "Get MAC pkt stats fail, status = %d.\n", ret);
471
472 return ret;
473 }
474
475 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
476 if (unlikely(i == 0)) {
477 desc_data = (u64 *)(&desc[i].data[0]);
478 n = HCLGE_RTN_DATA_NUM - 2;
479 } else {
480 desc_data = (u64 *)(&desc[i]);
481 n = HCLGE_RTN_DATA_NUM;
482 }
483 for (k = 0; k < n; k++) {
484 *data++ += cpu_to_le64(*desc_data);
485 desc_data++;
486 }
487 }
488
489 return 0;
490}
491
492static int hclge_tqps_update_stats(struct hnae3_handle *handle)
493{
494 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
495 struct hclge_vport *vport = hclge_get_vport(handle);
496 struct hclge_dev *hdev = vport->back;
497 struct hnae3_queue *queue;
498 struct hclge_desc desc[1];
499 struct hclge_tqp *tqp;
500 int ret, i;
501
502 for (i = 0; i < kinfo->num_tqps; i++) {
503 queue = handle->kinfo.tqp[i];
504 tqp = container_of(queue, struct hclge_tqp, q);
505 /* command : HCLGE_OPC_QUERY_IGU_STAT */
506 hclge_cmd_setup_basic_desc(&desc[0],
507 HCLGE_OPC_QUERY_RX_STATUS,
508 true);
509
510 desc[0].data[0] = (tqp->index & 0x1ff);
511 ret = hclge_cmd_send(&hdev->hw, desc, 1);
512 if (ret) {
513 dev_err(&hdev->pdev->dev,
514 "Query tqp stat fail, status = %d,queue = %d\n",
515 ret, i);
516 return ret;
517 }
518 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
519 cpu_to_le32(desc[0].data[4]);
520 }
521
522 for (i = 0; i < kinfo->num_tqps; i++) {
523 queue = handle->kinfo.tqp[i];
524 tqp = container_of(queue, struct hclge_tqp, q);
525 /* command : HCLGE_OPC_QUERY_IGU_STAT */
526 hclge_cmd_setup_basic_desc(&desc[0],
527 HCLGE_OPC_QUERY_TX_STATUS,
528 true);
529
530 desc[0].data[0] = (tqp->index & 0x1ff);
531 ret = hclge_cmd_send(&hdev->hw, desc, 1);
532 if (ret) {
533 dev_err(&hdev->pdev->dev,
534 "Query tqp stat fail, status = %d,queue = %d\n",
535 ret, i);
536 return ret;
537 }
538 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
539 cpu_to_le32(desc[0].data[4]);
540 }
541
542 return 0;
543}
544
545static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
546{
547 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
548 struct hclge_tqp *tqp;
549 u64 *buff = data;
550 int i;
551
552 for (i = 0; i < kinfo->num_tqps; i++) {
553 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
554 *buff++ = cpu_to_le64(tqp->tqp_stats.rcb_tx_ring_pktnum_rcd);
555 }
556
557 for (i = 0; i < kinfo->num_tqps; i++) {
558 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
559 *buff++ = cpu_to_le64(tqp->tqp_stats.rcb_rx_ring_pktnum_rcd);
560 }
561
562 return buff;
563}
564
565static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
566{
567 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
568
569 return kinfo->num_tqps * (2);
570}
571
572static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
573{
574 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
575 u8 *buff = data;
576 int i = 0;
577
578 for (i = 0; i < kinfo->num_tqps; i++) {
579 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
580 struct hclge_tqp, q);
581 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_tx_pktnum_rcd",
582 tqp->index);
583 buff = buff + ETH_GSTRING_LEN;
584 }
585
586 for (i = 0; i < kinfo->num_tqps; i++) {
587 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
588 struct hclge_tqp, q);
589 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_rx_pktnum_rcd",
590 tqp->index);
591 buff = buff + ETH_GSTRING_LEN;
592 }
593
594 return buff;
595}
596
597static u64 *hclge_comm_get_stats(void *comm_stats,
598 const struct hclge_comm_stats_str strs[],
599 int size, u64 *data)
600{
601 u64 *buf = data;
602 u32 i;
603
604 for (i = 0; i < size; i++)
605 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
606
607 return buf + size;
608}
609
610static u8 *hclge_comm_get_strings(u32 stringset,
611 const struct hclge_comm_stats_str strs[],
612 int size, u8 *data)
613{
614 char *buff = (char *)data;
615 u32 i;
616
617 if (stringset != ETH_SS_STATS)
618 return buff;
619
620 for (i = 0; i < size; i++) {
621 snprintf(buff, ETH_GSTRING_LEN,
622 strs[i].desc);
623 buff = buff + ETH_GSTRING_LEN;
624 }
625
626 return (u8 *)buff;
627}
628
629static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
630 struct net_device_stats *net_stats)
631{
632 net_stats->tx_dropped = 0;
633 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
634 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
635 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
636
637 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
638 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
639 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_err_pkt;
640 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
641 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
642 net_stats->rx_errors += hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
643
644 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
645 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
646
647 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
648 net_stats->rx_length_errors =
649 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
650 net_stats->rx_length_errors +=
651 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
652 net_stats->rx_over_errors =
653 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
654}
655
656static void hclge_update_stats_for_all(struct hclge_dev *hdev)
657{
658 struct hnae3_handle *handle;
659 int status;
660
661 handle = &hdev->vport[0].nic;
662 if (handle->client) {
663 status = hclge_tqps_update_stats(handle);
664 if (status) {
665 dev_err(&hdev->pdev->dev,
666 "Update TQPS stats fail, status = %d.\n",
667 status);
668 }
669 }
670
671 status = hclge_mac_update_stats(hdev);
672 if (status)
673 dev_err(&hdev->pdev->dev,
674 "Update MAC stats fail, status = %d.\n", status);
675
676 status = hclge_32_bit_update_stats(hdev);
677 if (status)
678 dev_err(&hdev->pdev->dev,
679 "Update 32 bit stats fail, status = %d.\n",
680 status);
681
682 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
683}
684
685static void hclge_update_stats(struct hnae3_handle *handle,
686 struct net_device_stats *net_stats)
687{
688 struct hclge_vport *vport = hclge_get_vport(handle);
689 struct hclge_dev *hdev = vport->back;
690 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
691 int status;
692
693 status = hclge_mac_update_stats(hdev);
694 if (status)
695 dev_err(&hdev->pdev->dev,
696 "Update MAC stats fail, status = %d.\n",
697 status);
698
699 status = hclge_32_bit_update_stats(hdev);
700 if (status)
701 dev_err(&hdev->pdev->dev,
702 "Update 32 bit stats fail, status = %d.\n",
703 status);
704
705 status = hclge_64_bit_update_stats(hdev);
706 if (status)
707 dev_err(&hdev->pdev->dev,
708 "Update 64 bit stats fail, status = %d.\n",
709 status);
710
711 status = hclge_tqps_update_stats(handle);
712 if (status)
713 dev_err(&hdev->pdev->dev,
714 "Update TQPS stats fail, status = %d.\n",
715 status);
716
717 hclge_update_netstat(hw_stats, net_stats);
718}
719
720static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
721{
722#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
723
724 struct hclge_vport *vport = hclge_get_vport(handle);
725 struct hclge_dev *hdev = vport->back;
726 int count = 0;
727
728 /* Loopback test support rules:
729 * mac: only GE mode support
730 * serdes: all mac mode will support include GE/XGE/LGE/CGE
731 * phy: only support when phy device exist on board
732 */
733 if (stringset == ETH_SS_TEST) {
734 /* clear loopback bit flags at first */
735 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
736 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
737 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
738 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
739 count += 1;
740 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
741 } else {
742 count = -EOPNOTSUPP;
743 }
744 } else if (stringset == ETH_SS_STATS) {
745 count = ARRAY_SIZE(g_mac_stats_string) +
746 ARRAY_SIZE(g_all_32bit_stats_string) +
747 ARRAY_SIZE(g_all_64bit_stats_string) +
748 hclge_tqps_get_sset_count(handle, stringset);
749 }
750
751 return count;
752}
753
754static void hclge_get_strings(struct hnae3_handle *handle,
755 u32 stringset,
756 u8 *data)
757{
758 u8 *p = (char *)data;
759 int size;
760
761 if (stringset == ETH_SS_STATS) {
762 size = ARRAY_SIZE(g_mac_stats_string);
763 p = hclge_comm_get_strings(stringset,
764 g_mac_stats_string,
765 size,
766 p);
767 size = ARRAY_SIZE(g_all_32bit_stats_string);
768 p = hclge_comm_get_strings(stringset,
769 g_all_32bit_stats_string,
770 size,
771 p);
772 size = ARRAY_SIZE(g_all_64bit_stats_string);
773 p = hclge_comm_get_strings(stringset,
774 g_all_64bit_stats_string,
775 size,
776 p);
777 p = hclge_tqps_get_strings(handle, p);
778 } else if (stringset == ETH_SS_TEST) {
779 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
780 memcpy(p,
781 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
782 ETH_GSTRING_LEN);
783 p += ETH_GSTRING_LEN;
784 }
785 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
786 memcpy(p,
787 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
788 ETH_GSTRING_LEN);
789 p += ETH_GSTRING_LEN;
790 }
791 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
792 memcpy(p,
793 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
794 ETH_GSTRING_LEN);
795 p += ETH_GSTRING_LEN;
796 }
797 }
798}
799
800static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
801{
802 struct hclge_vport *vport = hclge_get_vport(handle);
803 struct hclge_dev *hdev = vport->back;
804 u64 *p;
805
806 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
807 g_mac_stats_string,
808 ARRAY_SIZE(g_mac_stats_string),
809 data);
810 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
811 g_all_32bit_stats_string,
812 ARRAY_SIZE(g_all_32bit_stats_string),
813 p);
814 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
815 g_all_64bit_stats_string,
816 ARRAY_SIZE(g_all_64bit_stats_string),
817 p);
818 p = hclge_tqps_get_stats(handle, p);
819}
820
821static int hclge_parse_func_status(struct hclge_dev *hdev,
822 struct hclge_func_status *status)
823{
824 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
825 return -EINVAL;
826
827 /* Set the pf to main pf */
828 if (status->pf_state & HCLGE_PF_STATE_MAIN)
829 hdev->flag |= HCLGE_FLAG_MAIN;
830 else
831 hdev->flag &= ~HCLGE_FLAG_MAIN;
832
833 hdev->num_req_vfs = status->vf_num / status->pf_num;
834 return 0;
835}
836
837static int hclge_query_function_status(struct hclge_dev *hdev)
838{
839 struct hclge_func_status *req;
840 struct hclge_desc desc;
841 int timeout = 0;
842 int ret;
843
844 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
845 req = (struct hclge_func_status *)desc.data;
846
847 do {
848 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
849 if (ret) {
850 dev_err(&hdev->pdev->dev,
851 "query function status failed %d.\n",
852 ret);
853
854 return ret;
855 }
856
857 /* Check pf reset is done */
858 if (req->pf_state)
859 break;
860 usleep_range(1000, 2000);
861 } while (timeout++ < 5);
862
863 ret = hclge_parse_func_status(hdev, req);
864
865 return ret;
866}
867
868static int hclge_query_pf_resource(struct hclge_dev *hdev)
869{
870 struct hclge_pf_res *req;
871 struct hclge_desc desc;
872 int ret;
873
874 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
875 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
876 if (ret) {
877 dev_err(&hdev->pdev->dev,
878 "query pf resource failed %d.\n", ret);
879 return ret;
880 }
881
882 req = (struct hclge_pf_res *)desc.data;
883 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
884 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
885
e92a0843 886 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 887 hdev->num_roce_msix =
888 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
889 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
890
891 /* PF should have NIC vectors and Roce vectors,
892 * NIC vectors are queued before Roce vectors.
893 */
894 hdev->num_msi = hdev->num_roce_msix + HCLGE_ROCE_VECTOR_OFFSET;
895 } else {
896 hdev->num_msi =
897 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
898 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
899 }
900
901 return 0;
902}
903
904static int hclge_parse_speed(int speed_cmd, int *speed)
905{
906 switch (speed_cmd) {
907 case 6:
908 *speed = HCLGE_MAC_SPEED_10M;
909 break;
910 case 7:
911 *speed = HCLGE_MAC_SPEED_100M;
912 break;
913 case 0:
914 *speed = HCLGE_MAC_SPEED_1G;
915 break;
916 case 1:
917 *speed = HCLGE_MAC_SPEED_10G;
918 break;
919 case 2:
920 *speed = HCLGE_MAC_SPEED_25G;
921 break;
922 case 3:
923 *speed = HCLGE_MAC_SPEED_40G;
924 break;
925 case 4:
926 *speed = HCLGE_MAC_SPEED_50G;
927 break;
928 case 5:
929 *speed = HCLGE_MAC_SPEED_100G;
930 break;
931 default:
932 return -EINVAL;
933 }
934
935 return 0;
936}
937
938static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
939{
940 struct hclge_cfg_param *req;
941 u64 mac_addr_tmp_high;
942 u64 mac_addr_tmp;
943 int i;
944
945 req = (struct hclge_cfg_param *)desc[0].data;
946
947 /* get the configuration */
948 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
949 HCLGE_CFG_VMDQ_M,
950 HCLGE_CFG_VMDQ_S);
951 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
952 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
953 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
954 HCLGE_CFG_TQP_DESC_N_M,
955 HCLGE_CFG_TQP_DESC_N_S);
956
957 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
958 HCLGE_CFG_PHY_ADDR_M,
959 HCLGE_CFG_PHY_ADDR_S);
960 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
961 HCLGE_CFG_MEDIA_TP_M,
962 HCLGE_CFG_MEDIA_TP_S);
963 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
964 HCLGE_CFG_RX_BUF_LEN_M,
965 HCLGE_CFG_RX_BUF_LEN_S);
966 /* get mac_address */
967 mac_addr_tmp = __le32_to_cpu(req->param[2]);
968 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
969 HCLGE_CFG_MAC_ADDR_H_M,
970 HCLGE_CFG_MAC_ADDR_H_S);
971
972 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
973
974 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
975 HCLGE_CFG_DEFAULT_SPEED_M,
976 HCLGE_CFG_DEFAULT_SPEED_S);
977 for (i = 0; i < ETH_ALEN; i++)
978 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
979
980 req = (struct hclge_cfg_param *)desc[1].data;
981 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
982}
983
984/* hclge_get_cfg: query the static parameter from flash
985 * @hdev: pointer to struct hclge_dev
986 * @hcfg: the config structure to be getted
987 */
988static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
989{
990 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
991 struct hclge_cfg_param *req;
992 int i, ret;
993
994 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
995 req = (struct hclge_cfg_param *)desc[i].data;
996 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
997 true);
998 hnae_set_field(req->offset, HCLGE_CFG_OFFSET_M,
999 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1000 /* Len should be united by 4 bytes when send to hardware */
1001 hnae_set_field(req->offset, HCLGE_CFG_RD_LEN_M,
1002 HCLGE_CFG_RD_LEN_S,
1003 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1004 req->offset = cpu_to_le32(req->offset);
1005 }
1006
1007 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1008 if (ret) {
1009 dev_err(&hdev->pdev->dev,
1010 "get config failed %d.\n", ret);
1011 return ret;
1012 }
1013
1014 hclge_parse_cfg(hcfg, desc);
1015 return 0;
1016}
1017
1018static int hclge_get_cap(struct hclge_dev *hdev)
1019{
1020 int ret;
1021
1022 ret = hclge_query_function_status(hdev);
1023 if (ret) {
1024 dev_err(&hdev->pdev->dev,
1025 "query function status error %d.\n", ret);
1026 return ret;
1027 }
1028
1029 /* get pf resource */
1030 ret = hclge_query_pf_resource(hdev);
1031 if (ret) {
1032 dev_err(&hdev->pdev->dev,
1033 "query pf resource error %d.\n", ret);
1034 return ret;
1035 }
1036
1037 return 0;
1038}
1039
1040static int hclge_configure(struct hclge_dev *hdev)
1041{
1042 struct hclge_cfg cfg;
1043 int ret, i;
1044
1045 ret = hclge_get_cfg(hdev, &cfg);
1046 if (ret) {
1047 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1048 return ret;
1049 }
1050
1051 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1052 hdev->base_tqp_pid = 0;
1053 hdev->rss_size_max = 1;
1054 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 1055 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 1056 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 1057 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 1058 hdev->num_desc = cfg.tqp_desc_num;
1059 hdev->tm_info.num_pg = 1;
1060 hdev->tm_info.num_tc = cfg.tc_num;
1061 hdev->tm_info.hw_pfc_map = 0;
1062
1063 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1064 if (ret) {
1065 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1066 return ret;
1067 }
1068
1069 if ((hdev->tm_info.num_tc > HNAE3_MAX_TC) ||
1070 (hdev->tm_info.num_tc < 1)) {
1071 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
1072 hdev->tm_info.num_tc);
1073 hdev->tm_info.num_tc = 1;
1074 }
1075
1076 /* Currently not support uncontiuous tc */
1077 for (i = 0; i < cfg.tc_num; i++)
1078 hnae_set_bit(hdev->hw_tc_map, i, 1);
1079
1080 if (!hdev->num_vmdq_vport && !hdev->num_req_vfs)
1081 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1082 else
1083 hdev->tx_sch_mode = HCLGE_FLAG_VNET_BASE_SCH_MODE;
1084
1085 return ret;
1086}
1087
1088static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1089 int tso_mss_max)
1090{
1091 struct hclge_cfg_tso_status *req;
1092 struct hclge_desc desc;
1093
1094 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1095
1096 req = (struct hclge_cfg_tso_status *)desc.data;
1097 hnae_set_field(req->tso_mss_min, HCLGE_TSO_MSS_MIN_M,
1098 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
1099 hnae_set_field(req->tso_mss_max, HCLGE_TSO_MSS_MIN_M,
1100 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
1101
1102 return hclge_cmd_send(&hdev->hw, &desc, 1);
1103}
1104
1105static int hclge_alloc_tqps(struct hclge_dev *hdev)
1106{
1107 struct hclge_tqp *tqp;
1108 int i;
1109
1110 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1111 sizeof(struct hclge_tqp), GFP_KERNEL);
1112 if (!hdev->htqp)
1113 return -ENOMEM;
1114
1115 tqp = hdev->htqp;
1116
1117 for (i = 0; i < hdev->num_tqps; i++) {
1118 tqp->dev = &hdev->pdev->dev;
1119 tqp->index = i;
1120
1121 tqp->q.ae_algo = &ae_algo;
1122 tqp->q.buf_size = hdev->rx_buf_len;
1123 tqp->q.desc_num = hdev->num_desc;
1124 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1125 i * HCLGE_TQP_REG_SIZE;
1126
1127 tqp++;
1128 }
1129
1130 return 0;
1131}
1132
1133static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1134 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1135{
1136 struct hclge_tqp_map *req;
1137 struct hclge_desc desc;
1138 int ret;
1139
1140 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1141
1142 req = (struct hclge_tqp_map *)desc.data;
1143 req->tqp_id = cpu_to_le16(tqp_pid);
1144 req->tqp_vf = cpu_to_le16(func_id);
1145 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1146 1 << HCLGE_TQP_MAP_EN_B;
1147 req->tqp_vid = cpu_to_le16(tqp_vid);
1148
1149 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1150 if (ret) {
1151 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1152 ret);
1153 return ret;
1154 }
1155
1156 return 0;
1157}
1158
1159static int hclge_assign_tqp(struct hclge_vport *vport,
1160 struct hnae3_queue **tqp, u16 num_tqps)
1161{
1162 struct hclge_dev *hdev = vport->back;
1163 int i, alloced, func_id, ret;
1164 bool is_pf;
1165
1166 func_id = vport->vport_id;
1167 is_pf = (vport->vport_id == 0) ? true : false;
1168
1169 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1170 alloced < num_tqps; i++) {
1171 if (!hdev->htqp[i].alloced) {
1172 hdev->htqp[i].q.handle = &vport->nic;
1173 hdev->htqp[i].q.tqp_index = alloced;
1174 tqp[alloced] = &hdev->htqp[i].q;
1175 hdev->htqp[i].alloced = true;
1176 ret = hclge_map_tqps_to_func(hdev, func_id,
1177 hdev->htqp[i].index,
1178 alloced, is_pf);
1179 if (ret)
1180 return ret;
1181
1182 alloced++;
1183 }
1184 }
1185 vport->alloc_tqps = num_tqps;
1186
1187 return 0;
1188}
1189
1190static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1191{
1192 struct hnae3_handle *nic = &vport->nic;
1193 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1194 struct hclge_dev *hdev = vport->back;
1195 int i, ret;
1196
1197 kinfo->num_desc = hdev->num_desc;
1198 kinfo->rx_buf_len = hdev->rx_buf_len;
1199 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1200 kinfo->rss_size
1201 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1202 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1203
1204 for (i = 0; i < HNAE3_MAX_TC; i++) {
1205 if (hdev->hw_tc_map & BIT(i)) {
1206 kinfo->tc_info[i].enable = true;
1207 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1208 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1209 kinfo->tc_info[i].tc = i;
1210 } else {
1211 /* Set to default queue if TC is disable */
1212 kinfo->tc_info[i].enable = false;
1213 kinfo->tc_info[i].tqp_offset = 0;
1214 kinfo->tc_info[i].tqp_count = 1;
1215 kinfo->tc_info[i].tc = 0;
1216 }
1217 }
1218
1219 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1220 sizeof(struct hnae3_queue *), GFP_KERNEL);
1221 if (!kinfo->tqp)
1222 return -ENOMEM;
1223
1224 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1225 if (ret) {
1226 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1227 return -EINVAL;
1228 }
1229
1230 return 0;
1231}
1232
1233static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1234{
1235 /* this would be initialized later */
1236}
1237
1238static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1239{
1240 struct hnae3_handle *nic = &vport->nic;
1241 struct hclge_dev *hdev = vport->back;
1242 int ret;
1243
1244 nic->pdev = hdev->pdev;
1245 nic->ae_algo = &ae_algo;
1246 nic->numa_node_mask = hdev->numa_node_mask;
1247
1248 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1249 ret = hclge_knic_setup(vport, num_tqps);
1250 if (ret) {
1251 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1252 ret);
1253 return ret;
1254 }
1255 } else {
1256 hclge_unic_setup(vport, num_tqps);
1257 }
1258
1259 return 0;
1260}
1261
1262static int hclge_alloc_vport(struct hclge_dev *hdev)
1263{
1264 struct pci_dev *pdev = hdev->pdev;
1265 struct hclge_vport *vport;
1266 u32 tqp_main_vport;
1267 u32 tqp_per_vport;
1268 int num_vport, i;
1269 int ret;
1270
1271 /* We need to alloc a vport for main NIC of PF */
1272 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1273
1274 if (hdev->num_tqps < num_vport)
1275 num_vport = hdev->num_tqps;
1276
1277 /* Alloc the same number of TQPs for every vport */
1278 tqp_per_vport = hdev->num_tqps / num_vport;
1279 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1280
1281 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1282 GFP_KERNEL);
1283 if (!vport)
1284 return -ENOMEM;
1285
1286 hdev->vport = vport;
1287 hdev->num_alloc_vport = num_vport;
1288
1289#ifdef CONFIG_PCI_IOV
1290 /* Enable SRIOV */
1291 if (hdev->num_req_vfs) {
1292 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
1293 hdev->num_req_vfs);
1294 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
1295 if (ret) {
1296 hdev->num_alloc_vfs = 0;
1297 dev_err(&pdev->dev, "SRIOV enable failed %d\n",
1298 ret);
1299 return ret;
1300 }
1301 }
1302 hdev->num_alloc_vfs = hdev->num_req_vfs;
1303#endif
1304
1305 for (i = 0; i < num_vport; i++) {
1306 vport->back = hdev;
1307 vport->vport_id = i;
1308
1309 if (i == 0)
1310 ret = hclge_vport_setup(vport, tqp_main_vport);
1311 else
1312 ret = hclge_vport_setup(vport, tqp_per_vport);
1313 if (ret) {
1314 dev_err(&pdev->dev,
1315 "vport setup failed for vport %d, %d\n",
1316 i, ret);
1317 return ret;
1318 }
1319
1320 vport++;
1321 }
1322
1323 return 0;
1324}
1325
acf61ecd
YL		 1326static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1327 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1328{
1329/* TX buffer size is unit by 128 byte */
1330#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1331#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1332 struct hclge_tx_buff_alloc *req;
1333 struct hclge_desc desc;
1334 int ret;
1335 u8 i;
1336
1337 req = (struct hclge_tx_buff_alloc *)desc.data;
1338
1339 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1340 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1341 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1342
46a3df9f
S		 1343 req->tx_pkt_buff[i] =
1344 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1345 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1346 }
46a3df9f
S		 1347
1348 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1349 if (ret) {
1350 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1351 ret);
1352 return ret;
1353 }
1354
1355 return 0;
1356}
1357
acf61ecd
YL		 1358static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1359 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1360{
acf61ecd 1361 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f
S		 1362
1363 if (ret) {
1364 dev_err(&hdev->pdev->dev,
1365 "tx buffer alloc failed %d\n", ret);
1366 return ret;
1367 }
1368
1369 return 0;
1370}
1371
1372static int hclge_get_tc_num(struct hclge_dev *hdev)
1373{
1374 int i, cnt = 0;
1375
1376 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1377 if (hdev->hw_tc_map & BIT(i))
1378 cnt++;
1379 return cnt;
1380}
1381
1382static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1383{
1384 int i, cnt = 0;
1385
1386 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1387 if (hdev->hw_tc_map & BIT(i) &&
1388 hdev->tm_info.hw_pfc_map & BIT(i))
1389 cnt++;
1390 return cnt;
1391}
1392
1393/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1394static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1395 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1396{
1397 struct hclge_priv_buf *priv;
1398 int i, cnt = 0;
1399
1400 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1401 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1402 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1403 priv->enable)
1404 cnt++;
1405 }
1406
1407 return cnt;
1408}
1409
1410/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1411static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1412 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1413{
1414 struct hclge_priv_buf *priv;
1415 int i, cnt = 0;
1416
1417 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1418 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1419 if (hdev->hw_tc_map & BIT(i) &&
1420 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1421 priv->enable)
1422 cnt++;
1423 }
1424
1425 return cnt;
1426}
1427
acf61ecd 1428static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1429{
1430 struct hclge_priv_buf *priv;
1431 u32 rx_priv = 0;
1432 int i;
1433
1434 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1435 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1436 if (priv->enable)
1437 rx_priv += priv->buf_size;
1438 }
1439 return rx_priv;
1440}
1441
acf61ecd 1442static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1443{
1444 u32 i, total_tx_size = 0;
1445
1446 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1447 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1448
1449 return total_tx_size;
1450}
1451
acf61ecd
YL		 1452static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1453 struct hclge_pkt_buf_alloc *buf_alloc,
1454 u32 rx_all)
46a3df9f
S		 1455{
1456 u32 shared_buf_min, shared_buf_tc, shared_std;
1457 int tc_num, pfc_enable_num;
1458 u32 shared_buf;
1459 u32 rx_priv;
1460 int i;
1461
1462 tc_num = hclge_get_tc_num(hdev);
1463 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1464
d221df4e
YL		 1465 if (hnae3_dev_dcb_supported(hdev))
1466 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1467 else
1468 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1469
46a3df9f
S		 1470 shared_buf_tc = pfc_enable_num * hdev->mps +
1471 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1472 hdev->mps;
1473 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1474
acf61ecd 1475 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1476 if (rx_all <= rx_priv + shared_std)
1477 return false;
1478
1479 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1480 buf_alloc->s_buf.buf_size = shared_buf;
1481 buf_alloc->s_buf.self.high = shared_buf;
1482 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1483
1484 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1485 if ((hdev->hw_tc_map & BIT(i)) &&
1486 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1487 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1488 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1489 } else {
acf61ecd
YL		 1490 buf_alloc->s_buf.tc_thrd[i].low = 0;
1491 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1492 }
1493 }
1494
1495 return true;
1496}
1497
acf61ecd
YL		 1498static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1499 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1500{
1501 u32 i, total_size;
1502
1503 total_size = hdev->pkt_buf_size;
1504
1505 /* alloc tx buffer for all enabled tc */
1506 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1507 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1508
1509 if (total_size < HCLGE_DEFAULT_TX_BUF)
1510 return -ENOMEM;
1511
1512 if (hdev->hw_tc_map & BIT(i))
1513 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1514 else
1515 priv->tx_buf_size = 0;
1516
1517 total_size -= priv->tx_buf_size;
1518 }
1519
1520 return 0;
1521}
1522
46a3df9f
S		 1523/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1524 * @hdev: pointer to struct hclge_dev
acf61ecd 1525 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1526 * @return: 0: calculate sucessful, negative: fail
1527 */
acf61ecd
YL		 1528int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1529 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1530{
9ffe79a9 1531 u32 rx_all = hdev->pkt_buf_size;
46a3df9f
S		 1532 int no_pfc_priv_num, pfc_priv_num;
1533 struct hclge_priv_buf *priv;
1534 int i;
1535
acf61ecd 1536 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1537
d602a525
YL		 1538 /* When DCB is not supported, rx private
1539 * buffer is not allocated.
1540 */
1541 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1542 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1543 return -ENOMEM;
1544
1545 return 0;
1546 }
1547
46a3df9f
S		 1548 /* step 1, try to alloc private buffer for all enabled tc */
1549 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1550 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1551 if (hdev->hw_tc_map & BIT(i)) {
1552 priv->enable = 1;
1553 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1554 priv->wl.low = hdev->mps;
1555 priv->wl.high = priv->wl.low + hdev->mps;
1556 priv->buf_size = priv->wl.high +
1557 HCLGE_DEFAULT_DV;
1558 } else {
1559 priv->wl.low = 0;
1560 priv->wl.high = 2 * hdev->mps;
1561 priv->buf_size = priv->wl.high;
1562 }
bb1fe9ea
YL		 1563 } else {
1564 priv->enable = 0;
1565 priv->wl.low = 0;
1566 priv->wl.high = 0;
1567 priv->buf_size = 0;
46a3df9f
S		 1568 }
1569 }
1570
acf61ecd 1571 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1572 return 0;
1573
1574 /* step 2, try to decrease the buffer size of
1575 * no pfc TC's private buffer
1576 */
1577 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1578 priv = &buf_alloc->priv_buf[i];
46a3df9f 1579
bb1fe9ea
YL		 1580 priv->enable = 0;
1581 priv->wl.low = 0;
1582 priv->wl.high = 0;
1583 priv->buf_size = 0;
1584
1585 if (!(hdev->hw_tc_map & BIT(i)))
1586 continue;
1587
1588 priv->enable = 1;
46a3df9f
S		 1589
1590 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1591 priv->wl.low = 128;
1592 priv->wl.high = priv->wl.low + hdev->mps;
1593 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1594 } else {
1595 priv->wl.low = 0;
1596 priv->wl.high = hdev->mps;
1597 priv->buf_size = priv->wl.high;
1598 }
1599 }
1600
acf61ecd 1601 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1602 return 0;
1603
1604 /* step 3, try to reduce the number of pfc disabled TCs,
1605 * which have private buffer
1606 */
1607 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1608 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1609
1610 /* let the last to be cleared first */
1611 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1612 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1613
1614 if (hdev->hw_tc_map & BIT(i) &&
1615 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1616 /* Clear the no pfc TC private buffer */
1617 priv->wl.low = 0;
1618 priv->wl.high = 0;
1619 priv->buf_size = 0;
1620 priv->enable = 0;
1621 no_pfc_priv_num--;
1622 }
1623
acf61ecd 1624 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1625 no_pfc_priv_num == 0)
1626 break;
1627 }
1628
acf61ecd 1629 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1630 return 0;
1631
1632 /* step 4, try to reduce the number of pfc enabled TCs
1633 * which have private buffer.
1634 */
acf61ecd 1635 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1636
1637 /* let the last to be cleared first */
1638 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1639 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1640
1641 if (hdev->hw_tc_map & BIT(i) &&
1642 hdev->tm_info.hw_pfc_map & BIT(i)) {
1643 /* Reduce the number of pfc TC with private buffer */
1644 priv->wl.low = 0;
1645 priv->enable = 0;
1646 priv->wl.high = 0;
1647 priv->buf_size = 0;
1648 pfc_priv_num--;
1649 }
1650
acf61ecd 1651 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1652 pfc_priv_num == 0)
1653 break;
1654 }
acf61ecd 1655 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1656 return 0;
1657
1658 return -ENOMEM;
1659}
1660
acf61ecd
YL		 1661static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1662 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1663{
1664 struct hclge_rx_priv_buff *req;
1665 struct hclge_desc desc;
1666 int ret;
1667 int i;
1668
1669 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
1670 req = (struct hclge_rx_priv_buff *)desc.data;
1671
1672 /* Alloc private buffer TCs */
1673 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1674 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1675
1676 req->buf_num[i] =
1677 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1678 req->buf_num[i] |=
1679 cpu_to_le16(true << HCLGE_TC0_PRI_BUF_EN_B);
1680 }
1681
b8c8bf47 1682 req->shared_buf =
acf61ecd 1683 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1684 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1685
46a3df9f
S		 1686 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1687 if (ret) {
1688 dev_err(&hdev->pdev->dev,
1689 "rx private buffer alloc cmd failed %d\n", ret);
1690 return ret;
1691 }
1692
1693 return 0;
1694}
1695
1696#define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1697
acf61ecd
YL		 1698static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1699 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1700{
1701 struct hclge_rx_priv_wl_buf *req;
1702 struct hclge_priv_buf *priv;
1703 struct hclge_desc desc[2];
1704 int i, j;
1705 int ret;
1706
1707 for (i = 0; i < 2; i++) {
1708 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1709 false);
1710 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1711
1712 /* The first descriptor set the NEXT bit to 1 */
1713 if (i == 0)
1714 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1715 else
1716 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1717
1718 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1719 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1720
1721 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1722 req->tc_wl[j].high =
1723 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1724 req->tc_wl[j].high |=
1725 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1726 HCLGE_RX_PRIV_EN_B);
1727 req->tc_wl[j].low =
1728 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1729 req->tc_wl[j].low |=
1730 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1731 HCLGE_RX_PRIV_EN_B);
1732 }
1733 }
1734
1735 /* Send 2 descriptor at one time */
1736 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1737 if (ret) {
1738 dev_err(&hdev->pdev->dev,
1739 "rx private waterline config cmd failed %d\n",
1740 ret);
1741 return ret;
1742 }
1743 return 0;
1744}
1745
acf61ecd
YL		 1746static int hclge_common_thrd_config(struct hclge_dev *hdev,
1747 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1748{
acf61ecd 1749 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1750 struct hclge_rx_com_thrd *req;
1751 struct hclge_desc desc[2];
1752 struct hclge_tc_thrd *tc;
1753 int i, j;
1754 int ret;
1755
1756 for (i = 0; i < 2; i++) {
1757 hclge_cmd_setup_basic_desc(&desc[i],
1758 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1759 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1760
1761 /* The first descriptor set the NEXT bit to 1 */
1762 if (i == 0)
1763 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1764 else
1765 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1766
1767 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1768 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1769
1770 req->com_thrd[j].high =
1771 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1772 req->com_thrd[j].high |=
1773 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1774 HCLGE_RX_PRIV_EN_B);
1775 req->com_thrd[j].low =
1776 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1777 req->com_thrd[j].low |=
1778 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1779 HCLGE_RX_PRIV_EN_B);
1780 }
1781 }
1782
1783 /* Send 2 descriptors at one time */
1784 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1785 if (ret) {
1786 dev_err(&hdev->pdev->dev,
1787 "common threshold config cmd failed %d\n", ret);
1788 return ret;
1789 }
1790 return 0;
1791}
1792
acf61ecd
YL		 1793static int hclge_common_wl_config(struct hclge_dev *hdev,
1794 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1795{
acf61ecd 1796 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1797 struct hclge_rx_com_wl *req;
1798 struct hclge_desc desc;
1799 int ret;
1800
1801 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1802
1803 req = (struct hclge_rx_com_wl *)desc.data;
1804 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1805 req->com_wl.high |=
1806 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1807 HCLGE_RX_PRIV_EN_B);
1808
1809 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1810 req->com_wl.low |=
1811 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1812 HCLGE_RX_PRIV_EN_B);
1813
1814 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1815 if (ret) {
1816 dev_err(&hdev->pdev->dev,
1817 "common waterline config cmd failed %d\n", ret);
1818 return ret;
1819 }
1820
1821 return 0;
1822}
1823
1824int hclge_buffer_alloc(struct hclge_dev *hdev)
1825{
acf61ecd 1826 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1827 int ret;
1828
acf61ecd
YL		 1829 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1830 if (!pkt_buf)
46a3df9f
S		 1831 return -ENOMEM;
1832
acf61ecd 1833 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1834 if (ret) {
1835 dev_err(&hdev->pdev->dev,
1836 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1837 goto out;
9ffe79a9
YL		 1838 }
1839
acf61ecd 1840 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1841 if (ret) {
1842 dev_err(&hdev->pdev->dev,
1843 "could not alloc tx buffers %d\n", ret);
acf61ecd 1844 goto out;
46a3df9f
S		 1845 }
1846
acf61ecd 1847 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1848 if (ret) {
1849 dev_err(&hdev->pdev->dev,
1850 "could not calc rx priv buffer size for all TCs %d\n",
1851 ret);
acf61ecd 1852 goto out;
46a3df9f
S		 1853 }
1854
acf61ecd 1855 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1856 if (ret) {
1857 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1858 ret);
acf61ecd 1859 goto out;
46a3df9f
S		 1860 }
1861
2daf4a65 1862 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1863 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 1864 if (ret) {
1865 dev_err(&hdev->pdev->dev,
1866 "could not configure rx private waterline %d\n",
1867 ret);
acf61ecd 1868 goto out;
2daf4a65 1869 }
46a3df9f 1870
acf61ecd 1871 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 1872 if (ret) {
1873 dev_err(&hdev->pdev->dev,
1874 "could not configure common threshold %d\n",
1875 ret);
acf61ecd 1876 goto out;
2daf4a65 1877 }
46a3df9f
S		 1878 }
1879
acf61ecd
YL		 1880 ret = hclge_common_wl_config(hdev, pkt_buf);
1881 if (ret)
46a3df9f
S		 1882 dev_err(&hdev->pdev->dev,
1883 "could not configure common waterline %d\n", ret);
46a3df9f 1884
acf61ecd
YL		 1885out:
1886 kfree(pkt_buf);
1887 return ret;
46a3df9f
S		 1888}
1889
1890static int hclge_init_roce_base_info(struct hclge_vport *vport)
1891{
1892 struct hnae3_handle *roce = &vport->roce;
1893 struct hnae3_handle *nic = &vport->nic;
1894
1895 roce->rinfo.num_vectors = vport->back->num_roce_msix;
1896
1897 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1898 vport->back->num_msi_left == 0)
1899 return -EINVAL;
1900
1901 roce->rinfo.base_vector = vport->back->roce_base_vector;
1902
1903 roce->rinfo.netdev = nic->kinfo.netdev;
1904 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1905
1906 roce->pdev = nic->pdev;
1907 roce->ae_algo = nic->ae_algo;
1908 roce->numa_node_mask = nic->numa_node_mask;
1909
1910 return 0;
1911}
1912
1913static int hclge_init_msix(struct hclge_dev *hdev)
1914{
1915 struct pci_dev *pdev = hdev->pdev;
1916 int ret, i;
1917
1918 hdev->msix_entries = devm_kcalloc(&pdev->dev, hdev->num_msi,
1919 sizeof(struct msix_entry),
1920 GFP_KERNEL);
1921 if (!hdev->msix_entries)
1922 return -ENOMEM;
1923
1924 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1925 sizeof(u16), GFP_KERNEL);
1926 if (!hdev->vector_status)
1927 return -ENOMEM;
1928
1929 for (i = 0; i < hdev->num_msi; i++) {
1930 hdev->msix_entries[i].entry = i;
1931 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1932 }
1933
1934 hdev->num_msi_left = hdev->num_msi;
1935 hdev->base_msi_vector = hdev->pdev->irq;
1936 hdev->roce_base_vector = hdev->base_msi_vector +
1937 HCLGE_ROCE_VECTOR_OFFSET;
1938
1939 ret = pci_enable_msix_range(hdev->pdev, hdev->msix_entries,
1940 hdev->num_msi, hdev->num_msi);
1941 if (ret < 0) {
1942 dev_info(&hdev->pdev->dev,
1943 "MSI-X vector alloc failed: %d\n", ret);
1944 return ret;
1945 }
1946
1947 return 0;
1948}
1949
1950static int hclge_init_msi(struct hclge_dev *hdev)
1951{
1952 struct pci_dev *pdev = hdev->pdev;
1953 int vectors;
1954 int i;
1955
1956 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1957 sizeof(u16), GFP_KERNEL);
1958 if (!hdev->vector_status)
1959 return -ENOMEM;
1960
1961 for (i = 0; i < hdev->num_msi; i++)
1962 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1963
1964 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, PCI_IRQ_MSI);
1965 if (vectors < 0) {
1966 dev_err(&pdev->dev, "MSI vectors enable failed %d\n", vectors);
1967 return -EINVAL;
1968 }
1969 hdev->num_msi = vectors;
1970 hdev->num_msi_left = vectors;
1971 hdev->base_msi_vector = pdev->irq;
1972 hdev->roce_base_vector = hdev->base_msi_vector +
1973 HCLGE_ROCE_VECTOR_OFFSET;
1974
1975 return 0;
1976}
1977
1978static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
1979{
1980 struct hclge_mac *mac = &hdev->hw.mac;
1981
1982 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
1983 mac->duplex = (u8)duplex;
1984 else
1985 mac->duplex = HCLGE_MAC_FULL;
1986
1987 mac->speed = speed;
1988}
1989
1990int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
1991{
1992 struct hclge_config_mac_speed_dup *req;
1993 struct hclge_desc desc;
1994 int ret;
1995
1996 req = (struct hclge_config_mac_speed_dup *)desc.data;
1997
1998 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
1999
2000 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2001
2002 switch (speed) {
2003 case HCLGE_MAC_SPEED_10M:
2004 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2005 HCLGE_CFG_SPEED_S, 6);
2006 break;
2007 case HCLGE_MAC_SPEED_100M:
2008 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2009 HCLGE_CFG_SPEED_S, 7);
2010 break;
2011 case HCLGE_MAC_SPEED_1G:
2012 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2013 HCLGE_CFG_SPEED_S, 0);
2014 break;
2015 case HCLGE_MAC_SPEED_10G:
2016 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2017 HCLGE_CFG_SPEED_S, 1);
2018 break;
2019 case HCLGE_MAC_SPEED_25G:
2020 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2021 HCLGE_CFG_SPEED_S, 2);
2022 break;
2023 case HCLGE_MAC_SPEED_40G:
2024 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2025 HCLGE_CFG_SPEED_S, 3);
2026 break;
2027 case HCLGE_MAC_SPEED_50G:
2028 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2029 HCLGE_CFG_SPEED_S, 4);
2030 break;
2031 case HCLGE_MAC_SPEED_100G:
2032 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2033 HCLGE_CFG_SPEED_S, 5);
2034 break;
2035 default:
d7629e74 2036 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 2037 return -EINVAL;
2038 }
2039
2040 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2041 1);
2042
2043 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2044 if (ret) {
2045 dev_err(&hdev->pdev->dev,
2046 "mac speed/duplex config cmd failed %d.\n", ret);
2047 return ret;
2048 }
2049
2050 hclge_check_speed_dup(hdev, duplex, speed);
2051
2052 return 0;
2053}
2054
2055static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2056 u8 duplex)
2057{
2058 struct hclge_vport *vport = hclge_get_vport(handle);
2059 struct hclge_dev *hdev = vport->back;
2060
2061 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2062}
2063
2064static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2065 u8 *duplex)
2066{
2067 struct hclge_query_an_speed_dup *req;
2068 struct hclge_desc desc;
2069 int speed_tmp;
2070 int ret;
2071
2072 req = (struct hclge_query_an_speed_dup *)desc.data;
2073
2074 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2075 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2076 if (ret) {
2077 dev_err(&hdev->pdev->dev,
2078 "mac speed/autoneg/duplex query cmd failed %d\n",
2079 ret);
2080 return ret;
2081 }
2082
2083 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2084 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2085 HCLGE_QUERY_SPEED_S);
2086
2087 ret = hclge_parse_speed(speed_tmp, speed);
2088 if (ret) {
2089 dev_err(&hdev->pdev->dev,
2090 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2091 return -EIO;
2092 }
2093
2094 return 0;
2095}
2096
2097static int hclge_query_autoneg_result(struct hclge_dev *hdev)
2098{
2099 struct hclge_mac *mac = &hdev->hw.mac;
2100 struct hclge_query_an_speed_dup *req;
2101 struct hclge_desc desc;
2102 int ret;
2103
2104 req = (struct hclge_query_an_speed_dup *)desc.data;
2105
2106 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2107 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2108 if (ret) {
2109 dev_err(&hdev->pdev->dev,
2110 "autoneg result query cmd failed %d.\n", ret);
2111 return ret;
2112 }
2113
2114 mac->autoneg = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_AN_B);
2115
2116 return 0;
2117}
2118
2119static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2120{
2121 struct hclge_config_auto_neg *req;
2122 struct hclge_desc desc;
2123 int ret;
2124
2125 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2126
2127 req = (struct hclge_config_auto_neg *)desc.data;
2128 hnae_set_bit(req->cfg_an_cmd_flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2129
2130 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2131 if (ret) {
2132 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2133 ret);
2134 return ret;
2135 }
2136
2137 return 0;
2138}
2139
2140static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2141{
2142 struct hclge_vport *vport = hclge_get_vport(handle);
2143 struct hclge_dev *hdev = vport->back;
2144
2145 return hclge_set_autoneg_en(hdev, enable);
2146}
2147
2148static int hclge_get_autoneg(struct hnae3_handle *handle)
2149{
2150 struct hclge_vport *vport = hclge_get_vport(handle);
2151 struct hclge_dev *hdev = vport->back;
2152
2153 hclge_query_autoneg_result(hdev);
2154
2155 return hdev->hw.mac.autoneg;
2156}
2157
2158static int hclge_mac_init(struct hclge_dev *hdev)
2159{
2160 struct hclge_mac *mac = &hdev->hw.mac;
2161 int ret;
2162
2163 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2164 if (ret) {
2165 dev_err(&hdev->pdev->dev,
2166 "Config mac speed dup fail ret=%d\n", ret);
2167 return ret;
2168 }
2169
2170 mac->link = 0;
2171
2172 ret = hclge_mac_mdio_config(hdev);
2173 if (ret) {
2174 dev_warn(&hdev->pdev->dev,
2175 "mdio config fail ret=%d\n", ret);
2176 return ret;
2177 }
2178
2179 /* Initialize the MTA table work mode */
2180 hdev->accept_mta_mc = true;
2181 hdev->enable_mta = true;
2182 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2183
2184 ret = hclge_set_mta_filter_mode(hdev,
2185 hdev->mta_mac_sel_type,
2186 hdev->enable_mta);
2187 if (ret) {
2188 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2189 ret);
2190 return ret;
2191 }
2192
2193 return hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
2194}
2195
2196static void hclge_task_schedule(struct hclge_dev *hdev)
2197{
2198 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2199 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2200 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2201 (void)schedule_work(&hdev->service_task);
2202}
2203
2204static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2205{
2206 struct hclge_link_status *req;
2207 struct hclge_desc desc;
2208 int link_status;
2209 int ret;
2210
2211 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2212 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2213 if (ret) {
2214 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2215 ret);
2216 return ret;
2217 }
2218
2219 req = (struct hclge_link_status *)desc.data;
2220 link_status = req->status & HCLGE_LINK_STATUS;
2221
2222 return !!link_status;
2223}
2224
2225static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2226{
2227 int mac_state;
2228 int link_stat;
2229
2230 mac_state = hclge_get_mac_link_status(hdev);
2231
2232 if (hdev->hw.mac.phydev) {
2233 if (!genphy_read_status(hdev->hw.mac.phydev))
2234 link_stat = mac_state &
2235 hdev->hw.mac.phydev->link;
2236 else
2237 link_stat = 0;
2238
2239 } else {
2240 link_stat = mac_state;
2241 }
2242
2243 return !!link_stat;
2244}
2245
2246static void hclge_update_link_status(struct hclge_dev *hdev)
2247{
2248 struct hnae3_client *client = hdev->nic_client;
2249 struct hnae3_handle *handle;
2250 int state;
2251 int i;
2252
2253 if (!client)
2254 return;
2255 state = hclge_get_mac_phy_link(hdev);
2256 if (state != hdev->hw.mac.link) {
2257 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2258 handle = &hdev->vport[i].nic;
2259 client->ops->link_status_change(handle, state);
2260 }
2261 hdev->hw.mac.link = state;
2262 }
2263}
2264
2265static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2266{
2267 struct hclge_mac mac = hdev->hw.mac;
2268 u8 duplex;
2269 int speed;
2270 int ret;
2271
2272 /* get the speed and duplex as autoneg'result from mac cmd when phy
2273 * doesn't exit.
2274 */
2275 if (mac.phydev)
2276 return 0;
2277
2278 /* update mac->antoneg. */
2279 ret = hclge_query_autoneg_result(hdev);
2280 if (ret) {
2281 dev_err(&hdev->pdev->dev,
2282 "autoneg result query failed %d\n", ret);
2283 return ret;
2284 }
2285
2286 if (!mac.autoneg)
2287 return 0;
2288
2289 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2290 if (ret) {
2291 dev_err(&hdev->pdev->dev,
2292 "mac autoneg/speed/duplex query failed %d\n", ret);
2293 return ret;
2294 }
2295
2296 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2297 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2298 if (ret) {
2299 dev_err(&hdev->pdev->dev,
2300 "mac speed/duplex config failed %d\n", ret);
2301 return ret;
2302 }
2303 }
2304
2305 return 0;
2306}
2307
2308static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2309{
2310 struct hclge_vport *vport = hclge_get_vport(handle);
2311 struct hclge_dev *hdev = vport->back;
2312
2313 return hclge_update_speed_duplex(hdev);
2314}
2315
2316static int hclge_get_status(struct hnae3_handle *handle)
2317{
2318 struct hclge_vport *vport = hclge_get_vport(handle);
2319 struct hclge_dev *hdev = vport->back;
2320
2321 hclge_update_link_status(hdev);
2322
2323 return hdev->hw.mac.link;
2324}
2325
2326static void hclge_service_timer(unsigned long data)
2327{
2328 struct hclge_dev *hdev = (struct hclge_dev *)data;
2329 (void)mod_timer(&hdev->service_timer, jiffies + HZ);
2330
2331 hclge_task_schedule(hdev);
2332}
2333
2334static void hclge_service_complete(struct hclge_dev *hdev)
2335{
2336 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2337
2338 /* Flush memory before next watchdog */
2339 smp_mb__before_atomic();
2340 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2341}
2342
2343static void hclge_service_task(struct work_struct *work)
2344{
2345 struct hclge_dev *hdev =
2346 container_of(work, struct hclge_dev, service_task);
2347
2348 hclge_update_speed_duplex(hdev);
2349 hclge_update_link_status(hdev);
2350 hclge_update_stats_for_all(hdev);
2351 hclge_service_complete(hdev);
2352}
2353
2354static void hclge_disable_sriov(struct hclge_dev *hdev)
2355{
2a32ca13
AB		 2356 /* If our VFs are assigned we cannot shut down SR-IOV
2357 * without causing issues, so just leave the hardware
2358 * available but disabled
2359 */
2360 if (pci_vfs_assigned(hdev->pdev)) {
2361 dev_warn(&hdev->pdev->dev,
2362 "disabling driver while VFs are assigned\n");
2363 return;
2364 }
46a3df9f 2365
2a32ca13 2366 pci_disable_sriov(hdev->pdev);
46a3df9f
S		 2367}
2368
2369struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2370{
2371 /* VF handle has no client */
2372 if (!handle->client)
2373 return container_of(handle, struct hclge_vport, nic);
2374 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2375 return container_of(handle, struct hclge_vport, roce);
2376 else
2377 return container_of(handle, struct hclge_vport, nic);
2378}
2379
2380static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2381 struct hnae3_vector_info *vector_info)
2382{
2383 struct hclge_vport *vport = hclge_get_vport(handle);
2384 struct hnae3_vector_info *vector = vector_info;
2385 struct hclge_dev *hdev = vport->back;
2386 int alloc = 0;
2387 int i, j;
2388
2389 vector_num = min(hdev->num_msi_left, vector_num);
2390
2391 for (j = 0; j < vector_num; j++) {
2392 for (i = 1; i < hdev->num_msi; i++) {
2393 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2394 vector->vector = pci_irq_vector(hdev->pdev, i);
2395 vector->io_addr = hdev->hw.io_base +
2396 HCLGE_VECTOR_REG_BASE +
2397 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2398 vport->vport_id *
2399 HCLGE_VECTOR_VF_OFFSET;
2400 hdev->vector_status[i] = vport->vport_id;
2401
2402 vector++;
2403 alloc++;
2404
2405 break;
2406 }
2407 }
2408 }
2409 hdev->num_msi_left -= alloc;
2410 hdev->num_msi_used += alloc;
2411
2412 return alloc;
2413}
2414
2415static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2416{
2417 int i;
2418
2419 for (i = 0; i < hdev->num_msi; i++) {
2420 if (hdev->msix_entries) {
2421 if (vector == hdev->msix_entries[i].vector)
2422 return i;
2423 } else {
2424 if (vector == (hdev->base_msi_vector + i))
2425 return i;
2426 }
2427 }
2428 return -EINVAL;
2429}
2430
2431static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2432{
2433 return HCLGE_RSS_KEY_SIZE;
2434}
2435
2436static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2437{
2438 return HCLGE_RSS_IND_TBL_SIZE;
2439}
2440
2441static int hclge_get_rss_algo(struct hclge_dev *hdev)
2442{
2443 struct hclge_rss_config *req;
2444 struct hclge_desc desc;
2445 int rss_hash_algo;
2446 int ret;
2447
2448 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, true);
2449
2450 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2451 if (ret) {
2452 dev_err(&hdev->pdev->dev,
2453 "Get link status error, status =%d\n", ret);
2454 return ret;
2455 }
2456
2457 req = (struct hclge_rss_config *)desc.data;
2458 rss_hash_algo = (req->hash_config & HCLGE_RSS_HASH_ALGO_MASK);
2459
2460 if (rss_hash_algo == HCLGE_RSS_HASH_ALGO_TOEPLITZ)
2461 return ETH_RSS_HASH_TOP;
2462
2463 return -EINVAL;
2464}
2465
2466static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2467 const u8 hfunc, const u8 *key)
2468{
2469 struct hclge_rss_config *req;
2470 struct hclge_desc desc;
2471 int key_offset;
2472 int key_size;
2473 int ret;
2474
2475 req = (struct hclge_rss_config *)desc.data;
2476
2477 for (key_offset = 0; key_offset < 3; key_offset++) {
2478 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2479 false);
2480
2481 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2482 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2483
2484 if (key_offset == 2)
2485 key_size =
2486 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2487 else
2488 key_size = HCLGE_RSS_HASH_KEY_NUM;
2489
2490 memcpy(req->hash_key,
2491 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2492
2493 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2494 if (ret) {
2495 dev_err(&hdev->pdev->dev,
2496 "Configure RSS config fail, status = %d\n",
2497 ret);
2498 return ret;
2499 }
2500 }
2501 return 0;
2502}
2503
2504static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u32 *indir)
2505{
2506 struct hclge_rss_indirection_table *req;
2507 struct hclge_desc desc;
2508 int i, j;
2509 int ret;
2510
2511 req = (struct hclge_rss_indirection_table *)desc.data;
2512
2513 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2514 hclge_cmd_setup_basic_desc
2515 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2516
2517 req->start_table_index = i * HCLGE_RSS_CFG_TBL_SIZE;
2518 req->rss_set_bitmap = HCLGE_RSS_SET_BITMAP_MSK;
2519
2520 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2521 req->rss_result[j] =
2522 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2523
2524 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2525 if (ret) {
2526 dev_err(&hdev->pdev->dev,
2527 "Configure rss indir table fail,status = %d\n",
2528 ret);
2529 return ret;
2530 }
2531 }
2532 return 0;
2533}
2534
2535static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2536 u16 *tc_size, u16 *tc_offset)
2537{
2538 struct hclge_rss_tc_mode *req;
2539 struct hclge_desc desc;
2540 int ret;
2541 int i;
2542
2543 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
2544 req = (struct hclge_rss_tc_mode *)desc.data;
2545
2546 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2547 hnae_set_bit(req->rss_tc_mode[i], HCLGE_RSS_TC_VALID_B,
2548 (tc_valid[i] & 0x1));
2549 hnae_set_field(req->rss_tc_mode[i], HCLGE_RSS_TC_SIZE_M,
2550 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
2551 hnae_set_field(req->rss_tc_mode[i], HCLGE_RSS_TC_OFFSET_M,
2552 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
2553 }
2554
2555 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2556 if (ret) {
2557 dev_err(&hdev->pdev->dev,
2558 "Configure rss tc mode fail, status = %d\n", ret);
2559 return ret;
2560 }
2561
2562 return 0;
2563}
2564
2565static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
2566{
2567#define HCLGE_RSS_INPUT_TUPLE_OTHER 0xf
2568#define HCLGE_RSS_INPUT_TUPLE_SCTP 0x1f
2569 struct hclge_rss_input_tuple *req;
2570 struct hclge_desc desc;
2571 int ret;
2572
2573 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
2574
2575 req = (struct hclge_rss_input_tuple *)desc.data;
2576 req->ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2577 req->ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2578 req->ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2579 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2580 req->ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2581 req->ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2582 req->ipv6_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2583 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2584 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2585 if (ret) {
2586 dev_err(&hdev->pdev->dev,
2587 "Configure rss input fail, status = %d\n", ret);
2588 return ret;
2589 }
2590
2591 return 0;
2592}
2593
2594static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
2595 u8 *key, u8 *hfunc)
2596{
2597 struct hclge_vport *vport = hclge_get_vport(handle);
2598 struct hclge_dev *hdev = vport->back;
2599 int i;
2600
2601 /* Get hash algorithm */
2602 if (hfunc)
2603 *hfunc = hclge_get_rss_algo(hdev);
2604
2605 /* Get the RSS Key required by the user */
2606 if (key)
2607 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
2608
2609 /* Get indirect table */
2610 if (indir)
2611 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2612 indir[i] = vport->rss_indirection_tbl[i];
2613
2614 return 0;
2615}
2616
2617static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
2618 const u8 *key, const u8 hfunc)
2619{
2620 struct hclge_vport *vport = hclge_get_vport(handle);
2621 struct hclge_dev *hdev = vport->back;
2622 u8 hash_algo;
2623 int ret, i;
2624
2625 /* Set the RSS Hash Key if specififed by the user */
2626 if (key) {
2627 /* Update the shadow RSS key with user specified qids */
2628 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
2629
2630 if (hfunc == ETH_RSS_HASH_TOP ||
2631 hfunc == ETH_RSS_HASH_NO_CHANGE)
2632 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2633 else
2634 return -EINVAL;
2635 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
2636 if (ret)
2637 return ret;
2638 }
2639
2640 /* Update the shadow RSS table with user specified qids */
2641 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2642 vport->rss_indirection_tbl[i] = indir[i];
2643
2644 /* Update the hardware */
2645 ret = hclge_set_rss_indir_table(hdev, indir);
2646 return ret;
2647}
2648
2649static int hclge_get_tc_size(struct hnae3_handle *handle)
2650{
2651 struct hclge_vport *vport = hclge_get_vport(handle);
2652 struct hclge_dev *hdev = vport->back;
2653
2654 return hdev->rss_size_max;
2655}
2656
77f255c1 2657int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f
S		 2658{
2659 const u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2660 struct hclge_vport *vport = hdev->vport;
2661 u16 tc_offset[HCLGE_MAX_TC_NUM];
2662 u8 rss_key[HCLGE_RSS_KEY_SIZE];
2663 u16 tc_valid[HCLGE_MAX_TC_NUM];
2664 u16 tc_size[HCLGE_MAX_TC_NUM];
2665 u32 *rss_indir = NULL;
68ece54e 2666 u16 rss_size = 0, roundup_size;
46a3df9f
S		 2667 const u8 *key;
2668 int i, ret, j;
2669
2670 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
2671 if (!rss_indir)
2672 return -ENOMEM;
2673
2674 /* Get default RSS key */
2675 netdev_rss_key_fill(rss_key, HCLGE_RSS_KEY_SIZE);
2676
2677 /* Initialize RSS indirect table for each vport */
2678 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
2679 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
2680 vport[j].rss_indirection_tbl[i] =
68ece54e
YL		 2681 i % vport[j].alloc_rss_size;
2682
2683 /* vport 0 is for PF */
2684 if (j != 0)
2685 continue;
2686
2687 rss_size = vport[j].alloc_rss_size;
46a3df9f
S		 2688 rss_indir[i] = vport[j].rss_indirection_tbl[i];
2689 }
2690 }
2691 ret = hclge_set_rss_indir_table(hdev, rss_indir);
2692 if (ret)
2693 goto err;
2694
2695 key = rss_key;
2696 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
2697 if (ret)
2698 goto err;
2699
2700 ret = hclge_set_rss_input_tuple(hdev);
2701 if (ret)
2702 goto err;
2703
68ece54e
YL		 2704 /* Each TC have the same queue size, and tc_size set to hardware is
2705 * the log2 of roundup power of two of rss_size, the acutal queue
2706 * size is limited by indirection table.
2707 */
2708 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
2709 dev_err(&hdev->pdev->dev,
2710 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
2711 rss_size);
2712 return -EINVAL;
2713 }
2714
2715 roundup_size = roundup_pow_of_two(rss_size);
2716 roundup_size = ilog2(roundup_size);
2717
46a3df9f 2718 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 2719 tc_valid[i] = 0;
46a3df9f 2720
68ece54e
YL		 2721 if (!(hdev->hw_tc_map & BIT(i)))
2722 continue;
2723
2724 tc_valid[i] = 1;
2725 tc_size[i] = roundup_size;
2726 tc_offset[i] = rss_size * i;
46a3df9f 2727 }
68ece54e 2728
46a3df9f
S		 2729 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
2730
2731err:
2732 kfree(rss_indir);
2733
2734 return ret;
2735}
2736
2737int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector_id,
2738 struct hnae3_ring_chain_node *ring_chain)
2739{
2740 struct hclge_dev *hdev = vport->back;
2741 struct hclge_ctrl_vector_chain *req;
2742 struct hnae3_ring_chain_node *node;
2743 struct hclge_desc desc;
2744 int ret;
2745 int i;
2746
2747 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ADD_RING_TO_VECTOR, false);
2748
2749 req = (struct hclge_ctrl_vector_chain *)desc.data;
2750 req->int_vector_id = vector_id;
2751
2752 i = 0;
2753 for (node = ring_chain; node; node = node->next) {
2754 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_TYPE_M,
2755 HCLGE_INT_TYPE_S,
2756 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
2757 hnae_set_field(req->tqp_type_and_id[i], HCLGE_TQP_ID_M,
2758 HCLGE_TQP_ID_S, node->tqp_index);
0305b443
L		 2759 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_GL_IDX_M,
2760 HCLGE_INT_GL_IDX_S,
2761 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
46a3df9f 2762 req->tqp_type_and_id[i] = cpu_to_le16(req->tqp_type_and_id[i]);
0305b443 2763 req->vfid = vport->vport_id;
46a3df9f
S		 2764
2765 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
2766 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
2767
2768 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2769 if (ret) {
2770 dev_err(&hdev->pdev->dev,
2771 "Map TQP fail, status is %d.\n",
2772 ret);
2773 return ret;
2774 }
2775 i = 0;
2776
2777 hclge_cmd_setup_basic_desc(&desc,
2778 HCLGE_OPC_ADD_RING_TO_VECTOR,
2779 false);
2780 req->int_vector_id = vector_id;
2781 }
2782 }
2783
2784 if (i > 0) {
2785 req->int_cause_num = i;
2786
2787 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2788 if (ret) {
2789 dev_err(&hdev->pdev->dev,
2790 "Map TQP fail, status is %d.\n", ret);
2791 return ret;
2792 }
2793 }
2794
2795 return 0;
2796}
2797
2798int hclge_map_handle_ring_to_vector(struct hnae3_handle *handle,
2799 int vector,
2800 struct hnae3_ring_chain_node *ring_chain)
2801{
2802 struct hclge_vport *vport = hclge_get_vport(handle);
2803 struct hclge_dev *hdev = vport->back;
2804 int vector_id;
2805
2806 vector_id = hclge_get_vector_index(hdev, vector);
2807 if (vector_id < 0) {
2808 dev_err(&hdev->pdev->dev,
2809 "Get vector index fail. ret =%d\n", vector_id);
2810 return vector_id;
2811 }
2812
2813 return hclge_map_vport_ring_to_vector(vport, vector_id, ring_chain);
2814}
2815
2816static int hclge_unmap_ring_from_vector(
2817 struct hnae3_handle *handle, int vector,
2818 struct hnae3_ring_chain_node *ring_chain)
2819{
2820 struct hclge_vport *vport = hclge_get_vport(handle);
2821 struct hclge_dev *hdev = vport->back;
2822 struct hclge_ctrl_vector_chain *req;
2823 struct hnae3_ring_chain_node *node;
2824 struct hclge_desc desc;
2825 int i, vector_id;
2826 int ret;
2827
2828 vector_id = hclge_get_vector_index(hdev, vector);
2829 if (vector_id < 0) {
2830 dev_err(&handle->pdev->dev,
2831 "Get vector index fail. ret =%d\n", vector_id);
2832 return vector_id;
2833 }
2834
2835 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_DEL_RING_TO_VECTOR, false);
2836
2837 req = (struct hclge_ctrl_vector_chain *)desc.data;
2838 req->int_vector_id = vector_id;
2839
2840 i = 0;
2841 for (node = ring_chain; node; node = node->next) {
2842 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_TYPE_M,
2843 HCLGE_INT_TYPE_S,
2844 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
2845 hnae_set_field(req->tqp_type_and_id[i], HCLGE_TQP_ID_M,
2846 HCLGE_TQP_ID_S, node->tqp_index);
0305b443
L		 2847 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_GL_IDX_M,
2848 HCLGE_INT_GL_IDX_S,
2849 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
46a3df9f
S		 2850
2851 req->tqp_type_and_id[i] = cpu_to_le16(req->tqp_type_and_id[i]);
0305b443 2852 req->vfid = vport->vport_id;
46a3df9f
S		 2853
2854 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
2855 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
2856
2857 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2858 if (ret) {
2859 dev_err(&hdev->pdev->dev,
2860 "Unmap TQP fail, status is %d.\n",
2861 ret);
2862 return ret;
2863 }
2864 i = 0;
2865 hclge_cmd_setup_basic_desc(&desc,
c5b1b975 2866 HCLGE_OPC_DEL_RING_TO_VECTOR,
46a3df9f
S		 2867 false);
2868 req->int_vector_id = vector_id;
2869 }
2870 }
2871
2872 if (i > 0) {
2873 req->int_cause_num = i;
2874
2875 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2876 if (ret) {
2877 dev_err(&hdev->pdev->dev,
2878 "Unmap TQP fail, status is %d.\n", ret);
2879 return ret;
2880 }
2881 }
2882
2883 return 0;
2884}
2885
2886int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
2887 struct hclge_promisc_param *param)
2888{
2889 struct hclge_promisc_cfg *req;
2890 struct hclge_desc desc;
2891 int ret;
2892
2893 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
2894
2895 req = (struct hclge_promisc_cfg *)desc.data;
2896 req->vf_id = param->vf_id;
2897 req->flag = (param->enable << HCLGE_PROMISC_EN_B);
2898
2899 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2900 if (ret) {
2901 dev_err(&hdev->pdev->dev,
2902 "Set promisc mode fail, status is %d.\n", ret);
2903 return ret;
2904 }
2905 return 0;
2906}
2907
2908void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
2909 bool en_mc, bool en_bc, int vport_id)
2910{
2911 if (!param)
2912 return;
2913
2914 memset(param, 0, sizeof(struct hclge_promisc_param));
2915 if (en_uc)
2916 param->enable = HCLGE_PROMISC_EN_UC;
2917 if (en_mc)
2918 param->enable |= HCLGE_PROMISC_EN_MC;
2919 if (en_bc)
2920 param->enable |= HCLGE_PROMISC_EN_BC;
2921 param->vf_id = vport_id;
2922}
2923
2924static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en)
2925{
2926 struct hclge_vport *vport = hclge_get_vport(handle);
2927 struct hclge_dev *hdev = vport->back;
2928 struct hclge_promisc_param param;
2929
2930 hclge_promisc_param_init(&param, en, en, true, vport->vport_id);
2931 hclge_cmd_set_promisc_mode(hdev, &param);
2932}
2933
2934static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
2935{
2936 struct hclge_desc desc;
2937 struct hclge_config_mac_mode *req =
2938 (struct hclge_config_mac_mode *)desc.data;
2939 int ret;
2940
2941 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
2942 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_TX_EN_B, enable);
2943 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_RX_EN_B, enable);
2944 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_PAD_TX_B, enable);
2945 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_PAD_RX_B, enable);
2946 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_1588_TX_B, 0);
2947 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_1588_RX_B, 0);
2948 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_APP_LP_B, 0);
2949 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_LINE_LP_B, 0);
2950 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_FCS_TX_B, enable);
2951 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_RX_FCS_B, enable);
2952 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2953 HCLGE_MAC_RX_FCS_STRIP_B, enable);
2954 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2955 HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
2956 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2957 HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
2958 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2959 HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
2960
2961 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2962 if (ret)
2963 dev_err(&hdev->pdev->dev,
2964 "mac enable fail, ret =%d.\n", ret);
2965}
2966
2967static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
2968 int stream_id, bool enable)
2969{
2970 struct hclge_desc desc;
2971 struct hclge_cfg_com_tqp_queue *req =
2972 (struct hclge_cfg_com_tqp_queue *)desc.data;
2973 int ret;
2974
2975 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
2976 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
2977 req->stream_id = cpu_to_le16(stream_id);
2978 req->enable |= enable << HCLGE_TQP_ENABLE_B;
2979
2980 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2981 if (ret)
2982 dev_err(&hdev->pdev->dev,
2983 "Tqp enable fail, status =%d.\n", ret);
2984 return ret;
2985}
2986
2987static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
2988{
2989 struct hclge_vport *vport = hclge_get_vport(handle);
2990 struct hnae3_queue *queue;
2991 struct hclge_tqp *tqp;
2992 int i;
2993
2994 for (i = 0; i < vport->alloc_tqps; i++) {
2995 queue = handle->kinfo.tqp[i];
2996 tqp = container_of(queue, struct hclge_tqp, q);
2997 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
2998 }
2999}
3000
3001static int hclge_ae_start(struct hnae3_handle *handle)
3002{
3003 struct hclge_vport *vport = hclge_get_vport(handle);
3004 struct hclge_dev *hdev = vport->back;
3005 int i, queue_id, ret;
3006
3007 for (i = 0; i < vport->alloc_tqps; i++) {
3008 /* todo clear interrupt */
3009 /* ring enable */
3010 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3011 if (queue_id < 0) {
3012 dev_warn(&hdev->pdev->dev,
3013 "Get invalid queue id, ignore it\n");
3014 continue;
3015 }
3016
3017 hclge_tqp_enable(hdev, queue_id, 0, true);
3018 }
3019 /* mac enable */
3020 hclge_cfg_mac_mode(hdev, true);
3021 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
3022 (void)mod_timer(&hdev->service_timer, jiffies + HZ);
3023
3024 ret = hclge_mac_start_phy(hdev);
3025 if (ret)
3026 return ret;
3027
3028 /* reset tqp stats */
3029 hclge_reset_tqp_stats(handle);
3030
3031 return 0;
3032}
3033
3034static void hclge_ae_stop(struct hnae3_handle *handle)
3035{
3036 struct hclge_vport *vport = hclge_get_vport(handle);
3037 struct hclge_dev *hdev = vport->back;
3038 int i, queue_id;
3039
3040 for (i = 0; i < vport->alloc_tqps; i++) {
3041 /* Ring disable */
3042 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3043 if (queue_id < 0) {
3044 dev_warn(&hdev->pdev->dev,
3045 "Get invalid queue id, ignore it\n");
3046 continue;
3047 }
3048
3049 hclge_tqp_enable(hdev, queue_id, 0, false);
3050 }
3051 /* Mac disable */
3052 hclge_cfg_mac_mode(hdev, false);
3053
3054 hclge_mac_stop_phy(hdev);
3055
3056 /* reset tqp stats */
3057 hclge_reset_tqp_stats(handle);
3058}
3059
3060static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3061 u16 cmdq_resp, u8 resp_code,
3062 enum hclge_mac_vlan_tbl_opcode op)
3063{
3064 struct hclge_dev *hdev = vport->back;
3065 int return_status = -EIO;
3066
3067 if (cmdq_resp) {
3068 dev_err(&hdev->pdev->dev,
3069 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3070 cmdq_resp);
3071 return -EIO;
3072 }
3073
3074 if (op == HCLGE_MAC_VLAN_ADD) {
3075 if ((!resp_code) || (resp_code == 1)) {
3076 return_status = 0;
3077 } else if (resp_code == 2) {
3078 return_status = -EIO;
3079 dev_err(&hdev->pdev->dev,
3080 "add mac addr failed for uc_overflow.\n");
3081 } else if (resp_code == 3) {
3082 return_status = -EIO;
3083 dev_err(&hdev->pdev->dev,
3084 "add mac addr failed for mc_overflow.\n");
3085 } else {
3086 dev_err(&hdev->pdev->dev,
3087 "add mac addr failed for undefined, code=%d.\n",
3088 resp_code);
3089 }
3090 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3091 if (!resp_code) {
3092 return_status = 0;
3093 } else if (resp_code == 1) {
3094 return_status = -EIO;
3095 dev_dbg(&hdev->pdev->dev,
3096 "remove mac addr failed for miss.\n");
3097 } else {
3098 dev_err(&hdev->pdev->dev,
3099 "remove mac addr failed for undefined, code=%d.\n",
3100 resp_code);
3101 }
3102 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3103 if (!resp_code) {
3104 return_status = 0;
3105 } else if (resp_code == 1) {
3106 return_status = -EIO;
3107 dev_dbg(&hdev->pdev->dev,
3108 "lookup mac addr failed for miss.\n");
3109 } else {
3110 dev_err(&hdev->pdev->dev,
3111 "lookup mac addr failed for undefined, code=%d.\n",
3112 resp_code);
3113 }
3114 } else {
3115 return_status = -EIO;
3116 dev_err(&hdev->pdev->dev,
3117 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3118 op);
3119 }
3120
3121 return return_status;
3122}
3123
3124static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3125{
3126 int word_num;
3127 int bit_num;
3128
3129 if (vfid > 255 || vfid < 0)
3130 return -EIO;
3131
3132 if (vfid >= 0 && vfid <= 191) {
3133 word_num = vfid / 32;
3134 bit_num = vfid % 32;
3135 if (clr)
3136 desc[1].data[word_num] &= ~(1 << bit_num);
3137 else
3138 desc[1].data[word_num] |= (1 << bit_num);
3139 } else {
3140 word_num = (vfid - 192) / 32;
3141 bit_num = vfid % 32;
3142 if (clr)
3143 desc[2].data[word_num] &= ~(1 << bit_num);
3144 else
3145 desc[2].data[word_num] |= (1 << bit_num);
3146 }
3147
3148 return 0;
3149}
3150
3151static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3152{
3153#define HCLGE_DESC_NUMBER 3
3154#define HCLGE_FUNC_NUMBER_PER_DESC 6
3155 int i, j;
3156
3157 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3158 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3159 if (desc[i].data[j])
3160 return false;
3161
3162 return true;
3163}
3164
3165static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry *new_req,
3166 const u8 *addr)
3167{
3168 const unsigned char *mac_addr = addr;
3169 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3170 (mac_addr[0]) | (mac_addr[1] << 8);
3171 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3172
3173 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3174 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3175}
3176
3177u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3178 const u8 *addr)
3179{
3180 u16 high_val = addr[1] | (addr[0] << 8);
3181 struct hclge_dev *hdev = vport->back;
3182 u32 rsh = 4 - hdev->mta_mac_sel_type;
3183 u16 ret_val = (high_val >> rsh) & 0xfff;
3184
3185 return ret_val;
3186}
3187
3188static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3189 enum hclge_mta_dmac_sel_type mta_mac_sel,
3190 bool enable)
3191{
3192 struct hclge_mta_filter_mode *req;
3193 struct hclge_desc desc;
3194 int ret;
3195
3196 req = (struct hclge_mta_filter_mode *)desc.data;
3197 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3198
3199 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3200 enable);
3201 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3202 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3203
3204 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3205 if (ret) {
3206 dev_err(&hdev->pdev->dev,
3207 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3208 ret);
3209 return ret;
3210 }
3211
3212 return 0;
3213}
3214
3215int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3216 u8 func_id,
3217 bool enable)
3218{
3219 struct hclge_cfg_func_mta_filter *req;
3220 struct hclge_desc desc;
3221 int ret;
3222
3223 req = (struct hclge_cfg_func_mta_filter *)desc.data;
3224 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3225
3226 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3227 enable);
3228 req->function_id = func_id;
3229
3230 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3231 if (ret) {
3232 dev_err(&hdev->pdev->dev,
3233 "Config func_id enable failed for cmd_send, ret =%d.\n",
3234 ret);
3235 return ret;
3236 }
3237
3238 return 0;
3239}
3240
3241static int hclge_set_mta_table_item(struct hclge_vport *vport,
3242 u16 idx,
3243 bool enable)
3244{
3245 struct hclge_dev *hdev = vport->back;
3246 struct hclge_cfg_func_mta_item *req;
3247 struct hclge_desc desc;
3248 int ret;
3249
3250 req = (struct hclge_cfg_func_mta_item *)desc.data;
3251 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
3252 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
3253
3254 hnae_set_field(req->item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
3255 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
3256 req->item_idx = cpu_to_le16(req->item_idx);
3257
3258 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3259 if (ret) {
3260 dev_err(&hdev->pdev->dev,
3261 "Config mta table item failed for cmd_send, ret =%d.\n",
3262 ret);
3263 return ret;
3264 }
3265
3266 return 0;
3267}
3268
3269static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
3270 struct hclge_mac_vlan_tbl_entry *req)
3271{
3272 struct hclge_dev *hdev = vport->back;
3273 struct hclge_desc desc;
3274 u8 resp_code;
3275 int ret;
3276
3277 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3278
3279 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry));
3280
3281 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3282 if (ret) {
3283 dev_err(&hdev->pdev->dev,
3284 "del mac addr failed for cmd_send, ret =%d.\n",
3285 ret);
3286 return ret;
3287 }
3288 resp_code = (desc.data[0] >> 8) & 0xff;
3289
3290 return hclge_get_mac_vlan_cmd_status(vport, desc.retval, resp_code,
3291 HCLGE_MAC_VLAN_REMOVE);
3292}
3293
3294static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
3295 struct hclge_mac_vlan_tbl_entry *req,
3296 struct hclge_desc *desc,
3297 bool is_mc)
3298{
3299 struct hclge_dev *hdev = vport->back;
3300 u8 resp_code;
3301 int ret;
3302
3303 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3304 if (is_mc) {
3305 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3306 memcpy(desc[0].data,
3307 req,
3308 sizeof(struct hclge_mac_vlan_tbl_entry));
3309 hclge_cmd_setup_basic_desc(&desc[1],
3310 HCLGE_OPC_MAC_VLAN_ADD,
3311 true);
3312 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3313 hclge_cmd_setup_basic_desc(&desc[2],
3314 HCLGE_OPC_MAC_VLAN_ADD,
3315 true);
3316 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3317 } else {
3318 memcpy(desc[0].data,
3319 req,
3320 sizeof(struct hclge_mac_vlan_tbl_entry));
3321 ret = hclge_cmd_send(&hdev->hw, desc, 1);
3322 }
3323 if (ret) {
3324 dev_err(&hdev->pdev->dev,
3325 "lookup mac addr failed for cmd_send, ret =%d.\n",
3326 ret);
3327 return ret;
3328 }
3329 resp_code = (desc[0].data[0] >> 8) & 0xff;
3330
3331 return hclge_get_mac_vlan_cmd_status(vport, desc[0].retval, resp_code,
3332 HCLGE_MAC_VLAN_LKUP);
3333}
3334
3335static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
3336 struct hclge_mac_vlan_tbl_entry *req,
3337 struct hclge_desc *mc_desc)
3338{
3339 struct hclge_dev *hdev = vport->back;
3340 int cfg_status;
3341 u8 resp_code;
3342 int ret;
3343
3344 if (!mc_desc) {
3345 struct hclge_desc desc;
3346
3347 hclge_cmd_setup_basic_desc(&desc,
3348 HCLGE_OPC_MAC_VLAN_ADD,
3349 false);
3350 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry));
3351 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3352 resp_code = (desc.data[0] >> 8) & 0xff;
3353 cfg_status = hclge_get_mac_vlan_cmd_status(vport, desc.retval,
3354 resp_code,
3355 HCLGE_MAC_VLAN_ADD);
3356 } else {
3357 mc_desc[0].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
3358 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3359 mc_desc[1].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
3360 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3361 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
3362 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
3363 memcpy(mc_desc[0].data, req,
3364 sizeof(struct hclge_mac_vlan_tbl_entry));
3365 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
3366 resp_code = (mc_desc[0].data[0] >> 8) & 0xff;
3367 cfg_status = hclge_get_mac_vlan_cmd_status(vport,
3368 mc_desc[0].retval,
3369 resp_code,
3370 HCLGE_MAC_VLAN_ADD);
3371 }
3372
3373 if (ret) {
3374 dev_err(&hdev->pdev->dev,
3375 "add mac addr failed for cmd_send, ret =%d.\n",
3376 ret);
3377 return ret;
3378 }
3379
3380 return cfg_status;
3381}
3382
3383static int hclge_add_uc_addr(struct hnae3_handle *handle,
3384 const unsigned char *addr)
3385{
3386 struct hclge_vport *vport = hclge_get_vport(handle);
3387
3388 return hclge_add_uc_addr_common(vport, addr);
3389}
3390
3391int hclge_add_uc_addr_common(struct hclge_vport *vport,
3392 const unsigned char *addr)
3393{
3394 struct hclge_dev *hdev = vport->back;
3395 struct hclge_mac_vlan_tbl_entry req;
3396 enum hclge_cmd_status status;
3397
3398 /* mac addr check */
3399 if (is_zero_ether_addr(addr) ||
3400 is_broadcast_ether_addr(addr) ||
3401 is_multicast_ether_addr(addr)) {
3402 dev_err(&hdev->pdev->dev,
3403 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
3404 addr,
3405 is_zero_ether_addr(addr),
3406 is_broadcast_ether_addr(addr),
3407 is_multicast_ether_addr(addr));
3408 return -EINVAL;
3409 }
3410
3411 memset(&req, 0, sizeof(req));
3412 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3413 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3414 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
3415 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3416 hnae_set_bit(req.egress_port,
3417 HCLGE_MAC_EPORT_SW_EN_B, 0);
3418 hnae_set_bit(req.egress_port,
3419 HCLGE_MAC_EPORT_TYPE_B, 0);
3420 hnae_set_field(req.egress_port, HCLGE_MAC_EPORT_VFID_M,
3421 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
3422 hnae_set_field(req.egress_port, HCLGE_MAC_EPORT_PFID_M,
3423 HCLGE_MAC_EPORT_PFID_S, 0);
3424 req.egress_port = cpu_to_le16(req.egress_port);
3425
3426 hclge_prepare_mac_addr(&req, addr);
3427
3428 status = hclge_add_mac_vlan_tbl(vport, &req, NULL);
3429
3430 return status;
3431}
3432
3433static int hclge_rm_uc_addr(struct hnae3_handle *handle,
3434 const unsigned char *addr)
3435{
3436 struct hclge_vport *vport = hclge_get_vport(handle);
3437
3438 return hclge_rm_uc_addr_common(vport, addr);
3439}
3440
3441int hclge_rm_uc_addr_common(struct hclge_vport *vport,
3442 const unsigned char *addr)
3443{
3444 struct hclge_dev *hdev = vport->back;
3445 struct hclge_mac_vlan_tbl_entry req;
3446 enum hclge_cmd_status status;
3447
3448 /* mac addr check */
3449 if (is_zero_ether_addr(addr) ||
3450 is_broadcast_ether_addr(addr) ||
3451 is_multicast_ether_addr(addr)) {
3452 dev_dbg(&hdev->pdev->dev,
3453 "Remove mac err! invalid mac:%pM.\n",
3454 addr);
3455 return -EINVAL;
3456 }
3457
3458 memset(&req, 0, sizeof(req));
3459 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3460 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3461 hclge_prepare_mac_addr(&req, addr);
3462 status = hclge_remove_mac_vlan_tbl(vport, &req);
3463
3464 return status;
3465}
3466
3467static int hclge_add_mc_addr(struct hnae3_handle *handle,
3468 const unsigned char *addr)
3469{
3470 struct hclge_vport *vport = hclge_get_vport(handle);
3471
3472 return hclge_add_mc_addr_common(vport, addr);
3473}
3474
3475int hclge_add_mc_addr_common(struct hclge_vport *vport,
3476 const unsigned char *addr)
3477{
3478 struct hclge_dev *hdev = vport->back;
3479 struct hclge_mac_vlan_tbl_entry req;
3480 struct hclge_desc desc[3];
3481 u16 tbl_idx;
3482 int status;
3483
3484 /* mac addr check */
3485 if (!is_multicast_ether_addr(addr)) {
3486 dev_err(&hdev->pdev->dev,
3487 "Add mc mac err! invalid mac:%pM.\n",
3488 addr);
3489 return -EINVAL;
3490 }
3491 memset(&req, 0, sizeof(req));
3492 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3493 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3494 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
3495 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3496 hclge_prepare_mac_addr(&req, addr);
3497 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
3498 if (!status) {
3499 /* This mac addr exist, update VFID for it */
3500 hclge_update_desc_vfid(desc, vport->vport_id, false);
3501 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
3502 } else {
3503 /* This mac addr do not exist, add new entry for it */
3504 memset(desc[0].data, 0, sizeof(desc[0].data));
3505 memset(desc[1].data, 0, sizeof(desc[0].data));
3506 memset(desc[2].data, 0, sizeof(desc[0].data));
3507 hclge_update_desc_vfid(desc, vport->vport_id, false);
3508 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
3509 }
3510
3511 /* Set MTA table for this MAC address */
3512 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
3513 status = hclge_set_mta_table_item(vport, tbl_idx, true);
3514
3515 return status;
3516}
3517
3518static int hclge_rm_mc_addr(struct hnae3_handle *handle,
3519 const unsigned char *addr)
3520{
3521 struct hclge_vport *vport = hclge_get_vport(handle);
3522
3523 return hclge_rm_mc_addr_common(vport, addr);
3524}
3525
3526int hclge_rm_mc_addr_common(struct hclge_vport *vport,
3527 const unsigned char *addr)
3528{
3529 struct hclge_dev *hdev = vport->back;
3530 struct hclge_mac_vlan_tbl_entry req;
3531 enum hclge_cmd_status status;
3532 struct hclge_desc desc[3];
3533 u16 tbl_idx;
3534
3535 /* mac addr check */
3536 if (!is_multicast_ether_addr(addr)) {
3537 dev_dbg(&hdev->pdev->dev,
3538 "Remove mc mac err! invalid mac:%pM.\n",
3539 addr);
3540 return -EINVAL;
3541 }
3542
3543 memset(&req, 0, sizeof(req));
3544 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3545 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3546 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
3547 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3548 hclge_prepare_mac_addr(&req, addr);
3549 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
3550 if (!status) {
3551 /* This mac addr exist, remove this handle's VFID for it */
3552 hclge_update_desc_vfid(desc, vport->vport_id, true);
3553
3554 if (hclge_is_all_function_id_zero(desc))
3555 /* All the vfid is zero, so need to delete this entry */
3556 status = hclge_remove_mac_vlan_tbl(vport, &req);
3557 else
3558 /* Not all the vfid is zero, update the vfid */
3559 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
3560
3561 } else {
3562 /* This mac addr do not exist, can't delete it */
3563 dev_err(&hdev->pdev->dev,
d7629e74 3564 "Rm multicast mac addr failed, ret = %d.\n",
46a3df9f
S		 3565 status);
3566 return -EIO;
3567 }
3568
3569 /* Set MTB table for this MAC address */
3570 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
3571 status = hclge_set_mta_table_item(vport, tbl_idx, false);
3572
3573 return status;
3574}
3575
3576static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
3577{
3578 struct hclge_vport *vport = hclge_get_vport(handle);
3579 struct hclge_dev *hdev = vport->back;
3580
3581 ether_addr_copy(p, hdev->hw.mac.mac_addr);
3582}
3583
3584static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p)
3585{
3586 const unsigned char *new_addr = (const unsigned char *)p;
3587 struct hclge_vport *vport = hclge_get_vport(handle);
3588 struct hclge_dev *hdev = vport->back;
3589
3590 /* mac addr check */
3591 if (is_zero_ether_addr(new_addr) ||
3592 is_broadcast_ether_addr(new_addr) ||
3593 is_multicast_ether_addr(new_addr)) {
3594 dev_err(&hdev->pdev->dev,
3595 "Change uc mac err! invalid mac:%p.\n",
3596 new_addr);
3597 return -EINVAL;
3598 }
3599
3600 hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr);
3601
3602 if (!hclge_add_uc_addr(handle, new_addr)) {
3603 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
3604 return 0;
3605 }
3606
3607 return -EIO;
3608}
3609
3610static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
3611 bool filter_en)
3612{
3613 struct hclge_vlan_filter_ctrl *req;
3614 struct hclge_desc desc;
3615 int ret;
3616
3617 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
3618
3619 req = (struct hclge_vlan_filter_ctrl *)desc.data;
3620 req->vlan_type = vlan_type;
3621 req->vlan_fe = filter_en;
3622
3623 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3624 if (ret) {
3625 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
3626 ret);
3627 return ret;
3628 }
3629
3630 return 0;
3631}
3632
3633int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
3634 bool is_kill, u16 vlan, u8 qos, __be16 proto)
3635{
3636#define HCLGE_MAX_VF_BYTES 16
3637 struct hclge_vlan_filter_vf_cfg *req0;
3638 struct hclge_vlan_filter_vf_cfg *req1;
3639 struct hclge_desc desc[2];
3640 u8 vf_byte_val;
3641 u8 vf_byte_off;
3642 int ret;
3643
3644 hclge_cmd_setup_basic_desc(&desc[0],
3645 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
3646 hclge_cmd_setup_basic_desc(&desc[1],
3647 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
3648
3649 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3650
3651 vf_byte_off = vfid / 8;
3652 vf_byte_val = 1 << (vfid % 8);
3653
3654 req0 = (struct hclge_vlan_filter_vf_cfg *)desc[0].data;
3655 req1 = (struct hclge_vlan_filter_vf_cfg *)desc[1].data;
3656
3657 req0->vlan_id = vlan;
3658 req0->vlan_cfg = is_kill;
3659
3660 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
3661 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
3662 else
3663 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
3664
3665 ret = hclge_cmd_send(&hdev->hw, desc, 2);
3666 if (ret) {
3667 dev_err(&hdev->pdev->dev,
3668 "Send vf vlan command fail, ret =%d.\n",
3669 ret);
3670 return ret;
3671 }
3672
3673 if (!is_kill) {
3674 if (!req0->resp_code || req0->resp_code == 1)
3675 return 0;
3676
3677 dev_err(&hdev->pdev->dev,
3678 "Add vf vlan filter fail, ret =%d.\n",
3679 req0->resp_code);
3680 } else {
3681 if (!req0->resp_code)
3682 return 0;
3683
3684 dev_err(&hdev->pdev->dev,
3685 "Kill vf vlan filter fail, ret =%d.\n",
3686 req0->resp_code);
3687 }
3688
3689 return -EIO;
3690}
3691
3692static int hclge_set_port_vlan_filter(struct hnae3_handle *handle,
3693 __be16 proto, u16 vlan_id,
3694 bool is_kill)
3695{
3696 struct hclge_vport *vport = hclge_get_vport(handle);
3697 struct hclge_dev *hdev = vport->back;
3698 struct hclge_vlan_filter_pf_cfg *req;
3699 struct hclge_desc desc;
3700 u8 vlan_offset_byte_val;
3701 u8 vlan_offset_byte;
3702 u8 vlan_offset_160;
3703 int ret;
3704
3705 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
3706
3707 vlan_offset_160 = vlan_id / 160;
3708 vlan_offset_byte = (vlan_id % 160) / 8;
3709 vlan_offset_byte_val = 1 << (vlan_id % 8);
3710
3711 req = (struct hclge_vlan_filter_pf_cfg *)desc.data;
3712 req->vlan_offset = vlan_offset_160;
3713 req->vlan_cfg = is_kill;
3714 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
3715
3716 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3717 if (ret) {
3718 dev_err(&hdev->pdev->dev,
3719 "port vlan command, send fail, ret =%d.\n",
3720 ret);
3721 return ret;
3722 }
3723
3724 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto);
3725 if (ret) {
3726 dev_err(&hdev->pdev->dev,
3727 "Set pf vlan filter config fail, ret =%d.\n",
3728 ret);
3729 return -EIO;
3730 }
3731
3732 return 0;
3733}
3734
3735static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
3736 u16 vlan, u8 qos, __be16 proto)
3737{
3738 struct hclge_vport *vport = hclge_get_vport(handle);
3739 struct hclge_dev *hdev = vport->back;
3740
3741 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
3742 return -EINVAL;
3743 if (proto != htons(ETH_P_8021Q))
3744 return -EPROTONOSUPPORT;
3745
3746 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto);
3747}
3748
3749static int hclge_init_vlan_config(struct hclge_dev *hdev)
3750{
3751#define HCLGE_VLAN_TYPE_VF_TABLE 0
3752#define HCLGE_VLAN_TYPE_PORT_TABLE 1
5e43aef8 3753 struct hnae3_handle *handle;
46a3df9f
S		 3754 int ret;
3755
3756 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_VF_TABLE,
3757 true);
3758 if (ret)
3759 return ret;
3760
3761 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_PORT_TABLE,
3762 true);
5e43aef8
L		 3763 if (ret)
3764 return ret;
46a3df9f 3765
5e43aef8
L		 3766 handle = &hdev->vport[0].nic;
3767 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 3768}
3769
3770static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
3771{
3772 struct hclge_vport *vport = hclge_get_vport(handle);
3773 struct hclge_config_max_frm_size *req;
3774 struct hclge_dev *hdev = vport->back;
3775 struct hclge_desc desc;
3776 int ret;
3777
3778 if ((new_mtu < HCLGE_MAC_MIN_MTU) || (new_mtu > HCLGE_MAC_MAX_MTU))
3779 return -EINVAL;
3780
3781 hdev->mps = new_mtu;
3782 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
3783
3784 req = (struct hclge_config_max_frm_size *)desc.data;
3785 req->max_frm_size = cpu_to_le16(new_mtu);
3786
3787 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3788 if (ret) {
3789 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
3790 return ret;
3791 }
3792
3793 return 0;
3794}
3795
3796static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
3797 bool enable)
3798{
3799 struct hclge_reset_tqp_queue *req;
3800 struct hclge_desc desc;
3801 int ret;
3802
3803 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
3804
3805 req = (struct hclge_reset_tqp_queue *)desc.data;
3806 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
3807 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
3808
3809 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3810 if (ret) {
3811 dev_err(&hdev->pdev->dev,
3812 "Send tqp reset cmd error, status =%d\n", ret);
3813 return ret;
3814 }
3815
3816 return 0;
3817}
3818
3819static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
3820{
3821 struct hclge_reset_tqp_queue *req;
3822 struct hclge_desc desc;
3823 int ret;
3824
3825 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
3826
3827 req = (struct hclge_reset_tqp_queue *)desc.data;
3828 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
3829
3830 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3831 if (ret) {
3832 dev_err(&hdev->pdev->dev,
3833 "Get reset status error, status =%d\n", ret);
3834 return ret;
3835 }
3836
3837 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
3838}
3839
3840static void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
3841{
3842 struct hclge_vport *vport = hclge_get_vport(handle);
3843 struct hclge_dev *hdev = vport->back;
3844 int reset_try_times = 0;
3845 int reset_status;
3846 int ret;
3847
3848 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
3849 if (ret) {
3850 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
3851 return;
3852 }
3853
3854 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, true);
3855 if (ret) {
3856 dev_warn(&hdev->pdev->dev,
3857 "Send reset tqp cmd fail, ret = %d\n", ret);
3858 return;
3859 }
3860
3861 reset_try_times = 0;
3862 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
3863 /* Wait for tqp hw reset */
3864 msleep(20);
3865 reset_status = hclge_get_reset_status(hdev, queue_id);
3866 if (reset_status)
3867 break;
3868 }
3869
3870 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
3871 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
3872 return;
3873 }
3874
3875 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, false);
3876 if (ret) {
3877 dev_warn(&hdev->pdev->dev,
3878 "Deassert the soft reset fail, ret = %d\n", ret);
3879 return;
3880 }
3881}
3882
3883static u32 hclge_get_fw_version(struct hnae3_handle *handle)
3884{
3885 struct hclge_vport *vport = hclge_get_vport(handle);
3886 struct hclge_dev *hdev = vport->back;
3887
3888 return hdev->fw_version;
3889}
3890
3891static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
3892 u32 *rx_en, u32 *tx_en)
3893{
3894 struct hclge_vport *vport = hclge_get_vport(handle);
3895 struct hclge_dev *hdev = vport->back;
3896
3897 *auto_neg = hclge_get_autoneg(handle);
3898
3899 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
3900 *rx_en = 0;
3901 *tx_en = 0;
3902 return;
3903 }
3904
3905 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
3906 *rx_en = 1;
3907 *tx_en = 0;
3908 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
3909 *tx_en = 1;
3910 *rx_en = 0;
3911 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
3912 *rx_en = 1;
3913 *tx_en = 1;
3914 } else {
3915 *rx_en = 0;
3916 *tx_en = 0;
3917 }
3918}
3919
3920static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
3921 u8 *auto_neg, u32 *speed, u8 *duplex)
3922{
3923 struct hclge_vport *vport = hclge_get_vport(handle);
3924 struct hclge_dev *hdev = vport->back;
3925
3926 if (speed)
3927 *speed = hdev->hw.mac.speed;
3928 if (duplex)
3929 *duplex = hdev->hw.mac.duplex;
3930 if (auto_neg)
3931 *auto_neg = hdev->hw.mac.autoneg;
3932}
3933
3934static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
3935{
3936 struct hclge_vport *vport = hclge_get_vport(handle);
3937 struct hclge_dev *hdev = vport->back;
3938
3939 if (media_type)
3940 *media_type = hdev->hw.mac.media_type;
3941}
3942
3943static void hclge_get_mdix_mode(struct hnae3_handle *handle,
3944 u8 *tp_mdix_ctrl, u8 *tp_mdix)
3945{
3946 struct hclge_vport *vport = hclge_get_vport(handle);
3947 struct hclge_dev *hdev = vport->back;
3948 struct phy_device *phydev = hdev->hw.mac.phydev;
3949 int mdix_ctrl, mdix, retval, is_resolved;
3950
3951 if (!phydev) {
3952 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
3953 *tp_mdix = ETH_TP_MDI_INVALID;
3954 return;
3955 }
3956
3957 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
3958
3959 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
3960 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
3961 HCLGE_PHY_MDIX_CTRL_S);
3962
3963 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
3964 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
3965 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
3966
3967 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
3968
3969 switch (mdix_ctrl) {
3970 case 0x0:
3971 *tp_mdix_ctrl = ETH_TP_MDI;
3972 break;
3973 case 0x1:
3974 *tp_mdix_ctrl = ETH_TP_MDI_X;
3975 break;
3976 case 0x3:
3977 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
3978 break;
3979 default:
3980 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
3981 break;
3982 }
3983
3984 if (!is_resolved)
3985 *tp_mdix = ETH_TP_MDI_INVALID;
3986 else if (mdix)
3987 *tp_mdix = ETH_TP_MDI_X;
3988 else
3989 *tp_mdix = ETH_TP_MDI;
3990}
3991
3992static int hclge_init_client_instance(struct hnae3_client *client,
3993 struct hnae3_ae_dev *ae_dev)
3994{
3995 struct hclge_dev *hdev = ae_dev->priv;
3996 struct hclge_vport *vport;
3997 int i, ret;
3998
3999 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4000 vport = &hdev->vport[i];
4001
4002 switch (client->type) {
4003 case HNAE3_CLIENT_KNIC:
4004
4005 hdev->nic_client = client;
4006 vport->nic.client = client;
4007 ret = client->ops->init_instance(&vport->nic);
4008 if (ret)
4009 goto err;
4010
4011 if (hdev->roce_client &&
e92a0843 4012 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 4013 struct hnae3_client *rc = hdev->roce_client;
4014
4015 ret = hclge_init_roce_base_info(vport);
4016 if (ret)
4017 goto err;
4018
4019 ret = rc->ops->init_instance(&vport->roce);
4020 if (ret)
4021 goto err;
4022 }
4023
4024 break;
4025 case HNAE3_CLIENT_UNIC:
4026 hdev->nic_client = client;
4027 vport->nic.client = client;
4028
4029 ret = client->ops->init_instance(&vport->nic);
4030 if (ret)
4031 goto err;
4032
4033 break;
4034 case HNAE3_CLIENT_ROCE:
e92a0843 4035 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 4036 hdev->roce_client = client;
4037 vport->roce.client = client;
4038 }
4039
4040 if (hdev->roce_client) {
4041 ret = hclge_init_roce_base_info(vport);
4042 if (ret)
4043 goto err;
4044
4045 ret = client->ops->init_instance(&vport->roce);
4046 if (ret)
4047 goto err;
4048 }
4049 }
4050 }
4051
4052 return 0;
4053err:
4054 return ret;
4055}
4056
4057static void hclge_uninit_client_instance(struct hnae3_client *client,
4058 struct hnae3_ae_dev *ae_dev)
4059{
4060 struct hclge_dev *hdev = ae_dev->priv;
4061 struct hclge_vport *vport;
4062 int i;
4063
4064 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4065 vport = &hdev->vport[i];
4066 if (hdev->roce_client)
4067 hdev->roce_client->ops->uninit_instance(&vport->roce,
4068 0);
4069 if (client->type == HNAE3_CLIENT_ROCE)
4070 return;
4071 if (client->ops->uninit_instance)
4072 client->ops->uninit_instance(&vport->nic, 0);
4073 }
4074}
4075
4076static int hclge_pci_init(struct hclge_dev *hdev)
4077{
4078 struct pci_dev *pdev = hdev->pdev;
4079 struct hclge_hw *hw;
4080 int ret;
4081
4082 ret = pci_enable_device(pdev);
4083 if (ret) {
4084 dev_err(&pdev->dev, "failed to enable PCI device\n");
4085 goto err_no_drvdata;
4086 }
4087
4088 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4089 if (ret) {
4090 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4091 if (ret) {
4092 dev_err(&pdev->dev,
4093 "can't set consistent PCI DMA");
4094 goto err_disable_device;
4095 }
4096 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
4097 }
4098
4099 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
4100 if (ret) {
4101 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
4102 goto err_disable_device;
4103 }
4104
4105 pci_set_master(pdev);
4106 hw = &hdev->hw;
4107 hw->back = hdev;
4108 hw->io_base = pcim_iomap(pdev, 2, 0);
4109 if (!hw->io_base) {
4110 dev_err(&pdev->dev, "Can't map configuration register space\n");
4111 ret = -ENOMEM;
4112 goto err_clr_master;
4113 }
4114
4115 return 0;
4116err_clr_master:
4117 pci_clear_master(pdev);
4118 pci_release_regions(pdev);
4119err_disable_device:
4120 pci_disable_device(pdev);
4121err_no_drvdata:
4122 pci_set_drvdata(pdev, NULL);
4123
4124 return ret;
4125}
4126
4127static void hclge_pci_uninit(struct hclge_dev *hdev)
4128{
4129 struct pci_dev *pdev = hdev->pdev;
4130
4131 if (hdev->flag & HCLGE_FLAG_USE_MSIX) {
4132 pci_disable_msix(pdev);
4133 devm_kfree(&pdev->dev, hdev->msix_entries);
4134 hdev->msix_entries = NULL;
4135 } else {
4136 pci_disable_msi(pdev);
4137 }
4138
4139 pci_clear_master(pdev);
4140 pci_release_mem_regions(pdev);
4141 pci_disable_device(pdev);
4142}
4143
4144static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
4145{
4146 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 4147 struct hclge_dev *hdev;
4148 int ret;
4149
4150 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
4151 if (!hdev) {
4152 ret = -ENOMEM;
4153 goto err_hclge_dev;
4154 }
4155
4156 hdev->flag |= HCLGE_FLAG_USE_MSIX;
4157 hdev->pdev = pdev;
4158 hdev->ae_dev = ae_dev;
4159 ae_dev->priv = hdev;
4160
46a3df9f
S		 4161 ret = hclge_pci_init(hdev);
4162 if (ret) {
4163 dev_err(&pdev->dev, "PCI init failed\n");
4164 goto err_pci_init;
4165 }
4166
4167 /* Command queue initialize */
4168 ret = hclge_cmd_init(hdev);
4169 if (ret)
4170 goto err_cmd_init;
4171
4172 ret = hclge_get_cap(hdev);
4173 if (ret) {
e00e2197
CIK		 4174 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
4175 ret);
46a3df9f
S		 4176 return ret;
4177 }
4178
4179 ret = hclge_configure(hdev);
4180 if (ret) {
4181 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
4182 return ret;
4183 }
4184
4185 if (hdev->flag & HCLGE_FLAG_USE_MSIX)
4186 ret = hclge_init_msix(hdev);
4187 else
4188 ret = hclge_init_msi(hdev);
4189 if (ret) {
4190 dev_err(&pdev->dev, "Init msix/msi error, ret = %d.\n", ret);
4191 return ret;
4192 }
4193
4194 ret = hclge_alloc_tqps(hdev);
4195 if (ret) {
4196 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
4197 return ret;
4198 }
4199
4200 ret = hclge_alloc_vport(hdev);
4201 if (ret) {
4202 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
4203 return ret;
4204 }
4205
4206 ret = hclge_mac_init(hdev);
4207 if (ret) {
4208 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
4209 return ret;
4210 }
4211 ret = hclge_buffer_alloc(hdev);
4212 if (ret) {
4213 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
4214 return ret;
4215 }
4216
4217 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
4218 if (ret) {
4219 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
4220 return ret;
4221 }
4222
46a3df9f
S		 4223 ret = hclge_init_vlan_config(hdev);
4224 if (ret) {
4225 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
4226 return ret;
4227 }
4228
4229 ret = hclge_tm_schd_init(hdev);
4230 if (ret) {
4231 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
4232 return ret;
68ece54e
YL		 4233 }
4234
4235 ret = hclge_rss_init_hw(hdev);
4236 if (ret) {
4237 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
4238 return ret;
46a3df9f
S		 4239 }
4240
4241 setup_timer(&hdev->service_timer, hclge_service_timer,
4242 (unsigned long)hdev);
4243 INIT_WORK(&hdev->service_task, hclge_service_task);
4244
4245 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
4246 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4247
4248 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
4249 return 0;
4250
4251err_cmd_init:
4252 pci_release_regions(pdev);
4253err_pci_init:
4254 pci_set_drvdata(pdev, NULL);
4255err_hclge_dev:
4256 return ret;
4257}
4258
4259static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
4260{
4261 struct hclge_dev *hdev = ae_dev->priv;
4262 struct hclge_mac *mac = &hdev->hw.mac;
4263
4264 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4265
2a32ca13
AB		 4266 if (IS_ENABLED(CONFIG_PCI_IOV))
4267 hclge_disable_sriov(hdev);
46a3df9f
S		 4268
4269 if (hdev->service_timer.data)
4270 del_timer_sync(&hdev->service_timer);
4271 if (hdev->service_task.func)
4272 cancel_work_sync(&hdev->service_task);
4273
4274 if (mac->phydev)
4275 mdiobus_unregister(mac->mdio_bus);
4276
4277 hclge_destroy_cmd_queue(&hdev->hw);
4278 hclge_pci_uninit(hdev);
4279 ae_dev->priv = NULL;
4280}
4281
4282static const struct hnae3_ae_ops hclge_ops = {
4283 .init_ae_dev = hclge_init_ae_dev,
4284 .uninit_ae_dev = hclge_uninit_ae_dev,
4285 .init_client_instance = hclge_init_client_instance,
4286 .uninit_client_instance = hclge_uninit_client_instance,
4287 .map_ring_to_vector = hclge_map_handle_ring_to_vector,
4288 .unmap_ring_from_vector = hclge_unmap_ring_from_vector,
4289 .get_vector = hclge_get_vector,
4290 .set_promisc_mode = hclge_set_promisc_mode,
4291 .start = hclge_ae_start,
4292 .stop = hclge_ae_stop,
4293 .get_status = hclge_get_status,
4294 .get_ksettings_an_result = hclge_get_ksettings_an_result,
4295 .update_speed_duplex_h = hclge_update_speed_duplex_h,
4296 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
4297 .get_media_type = hclge_get_media_type,
4298 .get_rss_key_size = hclge_get_rss_key_size,
4299 .get_rss_indir_size = hclge_get_rss_indir_size,
4300 .get_rss = hclge_get_rss,
4301 .set_rss = hclge_set_rss,
4302 .get_tc_size = hclge_get_tc_size,
4303 .get_mac_addr = hclge_get_mac_addr,
4304 .set_mac_addr = hclge_set_mac_addr,
4305 .add_uc_addr = hclge_add_uc_addr,
4306 .rm_uc_addr = hclge_rm_uc_addr,
4307 .add_mc_addr = hclge_add_mc_addr,
4308 .rm_mc_addr = hclge_rm_mc_addr,
4309 .set_autoneg = hclge_set_autoneg,
4310 .get_autoneg = hclge_get_autoneg,
4311 .get_pauseparam = hclge_get_pauseparam,
4312 .set_mtu = hclge_set_mtu,
4313 .reset_queue = hclge_reset_tqp,
4314 .get_stats = hclge_get_stats,
4315 .update_stats = hclge_update_stats,
4316 .get_strings = hclge_get_strings,
4317 .get_sset_count = hclge_get_sset_count,
4318 .get_fw_version = hclge_get_fw_version,
4319 .get_mdix_mode = hclge_get_mdix_mode,
4320 .set_vlan_filter = hclge_set_port_vlan_filter,
4321 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
4322};
4323
4324static struct hnae3_ae_algo ae_algo = {
4325 .ops = &hclge_ops,
4326 .name = HCLGE_NAME,
4327 .pdev_id_table = ae_algo_pci_tbl,
4328};
4329
4330static int hclge_init(void)
4331{
4332 pr_info("%s is initializing\n", HCLGE_NAME);
4333
4334 return hnae3_register_ae_algo(&ae_algo);
4335}
4336
4337static void hclge_exit(void)
4338{
4339 hnae3_unregister_ae_algo(&ae_algo);
4340}
4341module_init(hclge_init);
4342module_exit(hclge_exit);
4343
4344MODULE_LICENSE("GPL");
4345MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4346MODULE_DESCRIPTION("HCLGE Driver");
4347MODULE_VERSION(HCLGE_MOD_VERSION);
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