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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
6e861326 | 4 | Copyright(c) 2007-2012 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | /* ethtool support for igb */ | |
29 | ||
30 | #include <linux/vmalloc.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/if_ether.h> | |
36 | #include <linux/ethtool.h> | |
d43c36dc | 37 | #include <linux/sched.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
749ab2cd | 39 | #include <linux/pm_runtime.h> |
9d5c8243 AK |
40 | |
41 | #include "igb.h" | |
42 | ||
43 | struct igb_stats { | |
44 | char stat_string[ETH_GSTRING_LEN]; | |
45 | int sizeof_stat; | |
46 | int stat_offset; | |
47 | }; | |
48 | ||
128e45eb AD |
49 | #define IGB_STAT(_name, _stat) { \ |
50 | .stat_string = _name, \ | |
51 | .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \ | |
52 | .stat_offset = offsetof(struct igb_adapter, _stat) \ | |
53 | } | |
9d5c8243 | 54 | static const struct igb_stats igb_gstrings_stats[] = { |
128e45eb AD |
55 | IGB_STAT("rx_packets", stats.gprc), |
56 | IGB_STAT("tx_packets", stats.gptc), | |
57 | IGB_STAT("rx_bytes", stats.gorc), | |
58 | IGB_STAT("tx_bytes", stats.gotc), | |
59 | IGB_STAT("rx_broadcast", stats.bprc), | |
60 | IGB_STAT("tx_broadcast", stats.bptc), | |
61 | IGB_STAT("rx_multicast", stats.mprc), | |
62 | IGB_STAT("tx_multicast", stats.mptc), | |
63 | IGB_STAT("multicast", stats.mprc), | |
64 | IGB_STAT("collisions", stats.colc), | |
65 | IGB_STAT("rx_crc_errors", stats.crcerrs), | |
66 | IGB_STAT("rx_no_buffer_count", stats.rnbc), | |
67 | IGB_STAT("rx_missed_errors", stats.mpc), | |
68 | IGB_STAT("tx_aborted_errors", stats.ecol), | |
69 | IGB_STAT("tx_carrier_errors", stats.tncrs), | |
70 | IGB_STAT("tx_window_errors", stats.latecol), | |
71 | IGB_STAT("tx_abort_late_coll", stats.latecol), | |
72 | IGB_STAT("tx_deferred_ok", stats.dc), | |
73 | IGB_STAT("tx_single_coll_ok", stats.scc), | |
74 | IGB_STAT("tx_multi_coll_ok", stats.mcc), | |
75 | IGB_STAT("tx_timeout_count", tx_timeout_count), | |
76 | IGB_STAT("rx_long_length_errors", stats.roc), | |
77 | IGB_STAT("rx_short_length_errors", stats.ruc), | |
78 | IGB_STAT("rx_align_errors", stats.algnerrc), | |
79 | IGB_STAT("tx_tcp_seg_good", stats.tsctc), | |
80 | IGB_STAT("tx_tcp_seg_failed", stats.tsctfc), | |
81 | IGB_STAT("rx_flow_control_xon", stats.xonrxc), | |
82 | IGB_STAT("rx_flow_control_xoff", stats.xoffrxc), | |
83 | IGB_STAT("tx_flow_control_xon", stats.xontxc), | |
84 | IGB_STAT("tx_flow_control_xoff", stats.xofftxc), | |
85 | IGB_STAT("rx_long_byte_count", stats.gorc), | |
86 | IGB_STAT("tx_dma_out_of_sync", stats.doosync), | |
87 | IGB_STAT("tx_smbus", stats.mgptc), | |
88 | IGB_STAT("rx_smbus", stats.mgprc), | |
89 | IGB_STAT("dropped_smbus", stats.mgpdc), | |
0a915b95 CW |
90 | IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc), |
91 | IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc), | |
92 | IGB_STAT("os2bmc_tx_by_host", stats.o2bspc), | |
93 | IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc), | |
128e45eb AD |
94 | }; |
95 | ||
96 | #define IGB_NETDEV_STAT(_net_stat) { \ | |
97 | .stat_string = __stringify(_net_stat), \ | |
12dcd86b ED |
98 | .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \ |
99 | .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \ | |
128e45eb AD |
100 | } |
101 | static const struct igb_stats igb_gstrings_net_stats[] = { | |
102 | IGB_NETDEV_STAT(rx_errors), | |
103 | IGB_NETDEV_STAT(tx_errors), | |
104 | IGB_NETDEV_STAT(tx_dropped), | |
105 | IGB_NETDEV_STAT(rx_length_errors), | |
106 | IGB_NETDEV_STAT(rx_over_errors), | |
107 | IGB_NETDEV_STAT(rx_frame_errors), | |
108 | IGB_NETDEV_STAT(rx_fifo_errors), | |
109 | IGB_NETDEV_STAT(tx_fifo_errors), | |
110 | IGB_NETDEV_STAT(tx_heartbeat_errors) | |
9d5c8243 AK |
111 | }; |
112 | ||
128e45eb AD |
113 | #define IGB_GLOBAL_STATS_LEN \ |
114 | (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)) | |
115 | #define IGB_NETDEV_STATS_LEN \ | |
116 | (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats)) | |
117 | #define IGB_RX_QUEUE_STATS_LEN \ | |
118 | (sizeof(struct igb_rx_queue_stats) / sizeof(u64)) | |
12dcd86b ED |
119 | |
120 | #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */ | |
121 | ||
9d5c8243 | 122 | #define IGB_QUEUE_STATS_LEN \ |
317f66bd | 123 | ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \ |
128e45eb | 124 | IGB_RX_QUEUE_STATS_LEN) + \ |
317f66bd | 125 | (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \ |
128e45eb AD |
126 | IGB_TX_QUEUE_STATS_LEN)) |
127 | #define IGB_STATS_LEN \ | |
128 | (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN) | |
129 | ||
9d5c8243 AK |
130 | static const char igb_gstrings_test[][ETH_GSTRING_LEN] = { |
131 | "Register test (offline)", "Eeprom test (offline)", | |
132 | "Interrupt test (offline)", "Loopback test (offline)", | |
133 | "Link test (on/offline)" | |
134 | }; | |
317f66bd | 135 | #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN) |
9d5c8243 AK |
136 | |
137 | static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) | |
138 | { | |
139 | struct igb_adapter *adapter = netdev_priv(netdev); | |
140 | struct e1000_hw *hw = &adapter->hw; | |
317f66bd | 141 | u32 status; |
9d5c8243 AK |
142 | |
143 | if (hw->phy.media_type == e1000_media_type_copper) { | |
144 | ||
145 | ecmd->supported = (SUPPORTED_10baseT_Half | | |
146 | SUPPORTED_10baseT_Full | | |
147 | SUPPORTED_100baseT_Half | | |
148 | SUPPORTED_100baseT_Full | | |
149 | SUPPORTED_1000baseT_Full| | |
150 | SUPPORTED_Autoneg | | |
42f3c43b AA |
151 | SUPPORTED_TP | |
152 | SUPPORTED_Pause); | |
153 | ecmd->advertising = ADVERTISED_TP; | |
9d5c8243 AK |
154 | |
155 | if (hw->mac.autoneg == 1) { | |
156 | ecmd->advertising |= ADVERTISED_Autoneg; | |
157 | /* the e1000 autoneg seems to match ethtool nicely */ | |
158 | ecmd->advertising |= hw->phy.autoneg_advertised; | |
159 | } | |
160 | ||
42f3c43b AA |
161 | if (hw->mac.autoneg != 1) |
162 | ecmd->advertising &= ~(ADVERTISED_Pause | | |
163 | ADVERTISED_Asym_Pause); | |
164 | ||
165 | if (hw->fc.requested_mode == e1000_fc_full) | |
166 | ecmd->advertising |= ADVERTISED_Pause; | |
167 | else if (hw->fc.requested_mode == e1000_fc_rx_pause) | |
168 | ecmd->advertising |= (ADVERTISED_Pause | | |
169 | ADVERTISED_Asym_Pause); | |
170 | else if (hw->fc.requested_mode == e1000_fc_tx_pause) | |
171 | ecmd->advertising |= ADVERTISED_Asym_Pause; | |
172 | else | |
173 | ecmd->advertising &= ~(ADVERTISED_Pause | | |
174 | ADVERTISED_Asym_Pause); | |
175 | ||
9d5c8243 AK |
176 | ecmd->port = PORT_TP; |
177 | ecmd->phy_address = hw->phy.addr; | |
178 | } else { | |
179 | ecmd->supported = (SUPPORTED_1000baseT_Full | | |
180 | SUPPORTED_FIBRE | | |
181 | SUPPORTED_Autoneg); | |
182 | ||
183 | ecmd->advertising = (ADVERTISED_1000baseT_Full | | |
184 | ADVERTISED_FIBRE | | |
f83396ad CW |
185 | ADVERTISED_Autoneg | |
186 | ADVERTISED_Pause); | |
9d5c8243 AK |
187 | |
188 | ecmd->port = PORT_FIBRE; | |
189 | } | |
190 | ||
191 | ecmd->transceiver = XCVR_INTERNAL; | |
192 | ||
317f66bd | 193 | status = rd32(E1000_STATUS); |
9d5c8243 | 194 | |
317f66bd | 195 | if (status & E1000_STATUS_LU) { |
9d5c8243 | 196 | |
317f66bd AD |
197 | if ((status & E1000_STATUS_SPEED_1000) || |
198 | hw->phy.media_type != e1000_media_type_copper) | |
70739497 | 199 | ethtool_cmd_speed_set(ecmd, SPEED_1000); |
317f66bd | 200 | else if (status & E1000_STATUS_SPEED_100) |
70739497 | 201 | ethtool_cmd_speed_set(ecmd, SPEED_100); |
317f66bd | 202 | else |
70739497 | 203 | ethtool_cmd_speed_set(ecmd, SPEED_10); |
9d5c8243 | 204 | |
317f66bd AD |
205 | if ((status & E1000_STATUS_FD) || |
206 | hw->phy.media_type != e1000_media_type_copper) | |
9d5c8243 AK |
207 | ecmd->duplex = DUPLEX_FULL; |
208 | else | |
209 | ecmd->duplex = DUPLEX_HALF; | |
210 | } else { | |
70739497 | 211 | ethtool_cmd_speed_set(ecmd, -1); |
9d5c8243 AK |
212 | ecmd->duplex = -1; |
213 | } | |
214 | ||
dcc3ae9a | 215 | ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE; |
8376dad0 JB |
216 | |
217 | /* MDI-X => 2; MDI =>1; Invalid =>0 */ | |
218 | if (hw->phy.media_type == e1000_media_type_copper) | |
219 | ecmd->eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X : | |
220 | ETH_TP_MDI; | |
221 | else | |
222 | ecmd->eth_tp_mdix = ETH_TP_MDI_INVALID; | |
223 | ||
224 | if (hw->phy.mdix == AUTO_ALL_MODES) | |
225 | ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; | |
226 | else | |
227 | ecmd->eth_tp_mdix_ctrl = hw->phy.mdix; | |
228 | ||
9d5c8243 AK |
229 | return 0; |
230 | } | |
231 | ||
232 | static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) | |
233 | { | |
234 | struct igb_adapter *adapter = netdev_priv(netdev); | |
235 | struct e1000_hw *hw = &adapter->hw; | |
236 | ||
237 | /* When SoL/IDER sessions are active, autoneg/speed/duplex | |
238 | * cannot be changed */ | |
239 | if (igb_check_reset_block(hw)) { | |
d836200a JJ |
240 | dev_err(&adapter->pdev->dev, |
241 | "Cannot change link characteristics when SoL/IDER is active.\n"); | |
9d5c8243 AK |
242 | return -EINVAL; |
243 | } | |
244 | ||
8376dad0 JB |
245 | /* |
246 | * MDI setting is only allowed when autoneg enabled because | |
247 | * some hardware doesn't allow MDI setting when speed or | |
248 | * duplex is forced. | |
249 | */ | |
250 | if (ecmd->eth_tp_mdix_ctrl) { | |
251 | if (hw->phy.media_type != e1000_media_type_copper) | |
252 | return -EOPNOTSUPP; | |
253 | ||
254 | if ((ecmd->eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) && | |
255 | (ecmd->autoneg != AUTONEG_ENABLE)) { | |
256 | dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n"); | |
257 | return -EINVAL; | |
258 | } | |
259 | } | |
260 | ||
9d5c8243 AK |
261 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) |
262 | msleep(1); | |
263 | ||
264 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
265 | hw->mac.autoneg = 1; | |
dcc3ae9a AD |
266 | hw->phy.autoneg_advertised = ecmd->advertising | |
267 | ADVERTISED_TP | | |
268 | ADVERTISED_Autoneg; | |
9d5c8243 | 269 | ecmd->advertising = hw->phy.autoneg_advertised; |
0cce119a AD |
270 | if (adapter->fc_autoneg) |
271 | hw->fc.requested_mode = e1000_fc_default; | |
dcc3ae9a | 272 | } else { |
25db0338 | 273 | u32 speed = ethtool_cmd_speed(ecmd); |
8376dad0 | 274 | /* calling this overrides forced MDI setting */ |
14ad2513 | 275 | if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) { |
9d5c8243 AK |
276 | clear_bit(__IGB_RESETTING, &adapter->state); |
277 | return -EINVAL; | |
278 | } | |
dcc3ae9a | 279 | } |
9d5c8243 | 280 | |
8376dad0 JB |
281 | /* MDI-X => 2; MDI => 1; Auto => 3 */ |
282 | if (ecmd->eth_tp_mdix_ctrl) { | |
283 | /* | |
284 | * fix up the value for auto (3 => 0) as zero is mapped | |
285 | * internally to auto | |
286 | */ | |
287 | if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO) | |
288 | hw->phy.mdix = AUTO_ALL_MODES; | |
289 | else | |
290 | hw->phy.mdix = ecmd->eth_tp_mdix_ctrl; | |
291 | } | |
292 | ||
9d5c8243 | 293 | /* reset the link */ |
9d5c8243 AK |
294 | if (netif_running(adapter->netdev)) { |
295 | igb_down(adapter); | |
296 | igb_up(adapter); | |
297 | } else | |
298 | igb_reset(adapter); | |
299 | ||
300 | clear_bit(__IGB_RESETTING, &adapter->state); | |
301 | return 0; | |
302 | } | |
303 | ||
3145535a NN |
304 | static u32 igb_get_link(struct net_device *netdev) |
305 | { | |
306 | struct igb_adapter *adapter = netdev_priv(netdev); | |
307 | struct e1000_mac_info *mac = &adapter->hw.mac; | |
308 | ||
309 | /* | |
310 | * If the link is not reported up to netdev, interrupts are disabled, | |
311 | * and so the physical link state may have changed since we last | |
312 | * looked. Set get_link_status to make sure that the true link | |
313 | * state is interrogated, rather than pulling a cached and possibly | |
314 | * stale link state from the driver. | |
315 | */ | |
316 | if (!netif_carrier_ok(netdev)) | |
317 | mac->get_link_status = 1; | |
318 | ||
319 | return igb_has_link(adapter); | |
320 | } | |
321 | ||
9d5c8243 AK |
322 | static void igb_get_pauseparam(struct net_device *netdev, |
323 | struct ethtool_pauseparam *pause) | |
324 | { | |
325 | struct igb_adapter *adapter = netdev_priv(netdev); | |
326 | struct e1000_hw *hw = &adapter->hw; | |
327 | ||
328 | pause->autoneg = | |
329 | (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE); | |
330 | ||
0cce119a | 331 | if (hw->fc.current_mode == e1000_fc_rx_pause) |
9d5c8243 | 332 | pause->rx_pause = 1; |
0cce119a | 333 | else if (hw->fc.current_mode == e1000_fc_tx_pause) |
9d5c8243 | 334 | pause->tx_pause = 1; |
0cce119a | 335 | else if (hw->fc.current_mode == e1000_fc_full) { |
9d5c8243 AK |
336 | pause->rx_pause = 1; |
337 | pause->tx_pause = 1; | |
338 | } | |
339 | } | |
340 | ||
341 | static int igb_set_pauseparam(struct net_device *netdev, | |
342 | struct ethtool_pauseparam *pause) | |
343 | { | |
344 | struct igb_adapter *adapter = netdev_priv(netdev); | |
345 | struct e1000_hw *hw = &adapter->hw; | |
346 | int retval = 0; | |
347 | ||
348 | adapter->fc_autoneg = pause->autoneg; | |
349 | ||
350 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
351 | msleep(1); | |
352 | ||
9d5c8243 | 353 | if (adapter->fc_autoneg == AUTONEG_ENABLE) { |
0cce119a | 354 | hw->fc.requested_mode = e1000_fc_default; |
9d5c8243 AK |
355 | if (netif_running(adapter->netdev)) { |
356 | igb_down(adapter); | |
357 | igb_up(adapter); | |
317f66bd | 358 | } else { |
9d5c8243 | 359 | igb_reset(adapter); |
317f66bd | 360 | } |
0cce119a AD |
361 | } else { |
362 | if (pause->rx_pause && pause->tx_pause) | |
363 | hw->fc.requested_mode = e1000_fc_full; | |
364 | else if (pause->rx_pause && !pause->tx_pause) | |
365 | hw->fc.requested_mode = e1000_fc_rx_pause; | |
366 | else if (!pause->rx_pause && pause->tx_pause) | |
367 | hw->fc.requested_mode = e1000_fc_tx_pause; | |
368 | else if (!pause->rx_pause && !pause->tx_pause) | |
369 | hw->fc.requested_mode = e1000_fc_none; | |
370 | ||
371 | hw->fc.current_mode = hw->fc.requested_mode; | |
372 | ||
dcc3ae9a AD |
373 | retval = ((hw->phy.media_type == e1000_media_type_copper) ? |
374 | igb_force_mac_fc(hw) : igb_setup_link(hw)); | |
0cce119a | 375 | } |
9d5c8243 AK |
376 | |
377 | clear_bit(__IGB_RESETTING, &adapter->state); | |
378 | return retval; | |
379 | } | |
380 | ||
9d5c8243 AK |
381 | static u32 igb_get_msglevel(struct net_device *netdev) |
382 | { | |
383 | struct igb_adapter *adapter = netdev_priv(netdev); | |
384 | return adapter->msg_enable; | |
385 | } | |
386 | ||
387 | static void igb_set_msglevel(struct net_device *netdev, u32 data) | |
388 | { | |
389 | struct igb_adapter *adapter = netdev_priv(netdev); | |
390 | adapter->msg_enable = data; | |
391 | } | |
392 | ||
393 | static int igb_get_regs_len(struct net_device *netdev) | |
394 | { | |
7e3b4ffb | 395 | #define IGB_REGS_LEN 739 |
9d5c8243 AK |
396 | return IGB_REGS_LEN * sizeof(u32); |
397 | } | |
398 | ||
399 | static void igb_get_regs(struct net_device *netdev, | |
400 | struct ethtool_regs *regs, void *p) | |
401 | { | |
402 | struct igb_adapter *adapter = netdev_priv(netdev); | |
403 | struct e1000_hw *hw = &adapter->hw; | |
404 | u32 *regs_buff = p; | |
405 | u8 i; | |
406 | ||
407 | memset(p, 0, IGB_REGS_LEN * sizeof(u32)); | |
408 | ||
409 | regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; | |
410 | ||
411 | /* General Registers */ | |
412 | regs_buff[0] = rd32(E1000_CTRL); | |
413 | regs_buff[1] = rd32(E1000_STATUS); | |
414 | regs_buff[2] = rd32(E1000_CTRL_EXT); | |
415 | regs_buff[3] = rd32(E1000_MDIC); | |
416 | regs_buff[4] = rd32(E1000_SCTL); | |
417 | regs_buff[5] = rd32(E1000_CONNSW); | |
418 | regs_buff[6] = rd32(E1000_VET); | |
419 | regs_buff[7] = rd32(E1000_LEDCTL); | |
420 | regs_buff[8] = rd32(E1000_PBA); | |
421 | regs_buff[9] = rd32(E1000_PBS); | |
422 | regs_buff[10] = rd32(E1000_FRTIMER); | |
423 | regs_buff[11] = rd32(E1000_TCPTIMER); | |
424 | ||
425 | /* NVM Register */ | |
426 | regs_buff[12] = rd32(E1000_EECD); | |
427 | ||
428 | /* Interrupt */ | |
fe59de38 AD |
429 | /* Reading EICS for EICR because they read the |
430 | * same but EICS does not clear on read */ | |
431 | regs_buff[13] = rd32(E1000_EICS); | |
9d5c8243 AK |
432 | regs_buff[14] = rd32(E1000_EICS); |
433 | regs_buff[15] = rd32(E1000_EIMS); | |
434 | regs_buff[16] = rd32(E1000_EIMC); | |
435 | regs_buff[17] = rd32(E1000_EIAC); | |
436 | regs_buff[18] = rd32(E1000_EIAM); | |
fe59de38 AD |
437 | /* Reading ICS for ICR because they read the |
438 | * same but ICS does not clear on read */ | |
439 | regs_buff[19] = rd32(E1000_ICS); | |
9d5c8243 AK |
440 | regs_buff[20] = rd32(E1000_ICS); |
441 | regs_buff[21] = rd32(E1000_IMS); | |
442 | regs_buff[22] = rd32(E1000_IMC); | |
443 | regs_buff[23] = rd32(E1000_IAC); | |
444 | regs_buff[24] = rd32(E1000_IAM); | |
445 | regs_buff[25] = rd32(E1000_IMIRVP); | |
446 | ||
447 | /* Flow Control */ | |
448 | regs_buff[26] = rd32(E1000_FCAL); | |
449 | regs_buff[27] = rd32(E1000_FCAH); | |
450 | regs_buff[28] = rd32(E1000_FCTTV); | |
451 | regs_buff[29] = rd32(E1000_FCRTL); | |
452 | regs_buff[30] = rd32(E1000_FCRTH); | |
453 | regs_buff[31] = rd32(E1000_FCRTV); | |
454 | ||
455 | /* Receive */ | |
456 | regs_buff[32] = rd32(E1000_RCTL); | |
457 | regs_buff[33] = rd32(E1000_RXCSUM); | |
458 | regs_buff[34] = rd32(E1000_RLPML); | |
459 | regs_buff[35] = rd32(E1000_RFCTL); | |
460 | regs_buff[36] = rd32(E1000_MRQC); | |
e1739522 | 461 | regs_buff[37] = rd32(E1000_VT_CTL); |
9d5c8243 AK |
462 | |
463 | /* Transmit */ | |
464 | regs_buff[38] = rd32(E1000_TCTL); | |
465 | regs_buff[39] = rd32(E1000_TCTL_EXT); | |
466 | regs_buff[40] = rd32(E1000_TIPG); | |
467 | regs_buff[41] = rd32(E1000_DTXCTL); | |
468 | ||
469 | /* Wake Up */ | |
470 | regs_buff[42] = rd32(E1000_WUC); | |
471 | regs_buff[43] = rd32(E1000_WUFC); | |
472 | regs_buff[44] = rd32(E1000_WUS); | |
473 | regs_buff[45] = rd32(E1000_IPAV); | |
474 | regs_buff[46] = rd32(E1000_WUPL); | |
475 | ||
476 | /* MAC */ | |
477 | regs_buff[47] = rd32(E1000_PCS_CFG0); | |
478 | regs_buff[48] = rd32(E1000_PCS_LCTL); | |
479 | regs_buff[49] = rd32(E1000_PCS_LSTAT); | |
480 | regs_buff[50] = rd32(E1000_PCS_ANADV); | |
481 | regs_buff[51] = rd32(E1000_PCS_LPAB); | |
482 | regs_buff[52] = rd32(E1000_PCS_NPTX); | |
483 | regs_buff[53] = rd32(E1000_PCS_LPABNP); | |
484 | ||
485 | /* Statistics */ | |
486 | regs_buff[54] = adapter->stats.crcerrs; | |
487 | regs_buff[55] = adapter->stats.algnerrc; | |
488 | regs_buff[56] = adapter->stats.symerrs; | |
489 | regs_buff[57] = adapter->stats.rxerrc; | |
490 | regs_buff[58] = adapter->stats.mpc; | |
491 | regs_buff[59] = adapter->stats.scc; | |
492 | regs_buff[60] = adapter->stats.ecol; | |
493 | regs_buff[61] = adapter->stats.mcc; | |
494 | regs_buff[62] = adapter->stats.latecol; | |
495 | regs_buff[63] = adapter->stats.colc; | |
496 | regs_buff[64] = adapter->stats.dc; | |
497 | regs_buff[65] = adapter->stats.tncrs; | |
498 | regs_buff[66] = adapter->stats.sec; | |
499 | regs_buff[67] = adapter->stats.htdpmc; | |
500 | regs_buff[68] = adapter->stats.rlec; | |
501 | regs_buff[69] = adapter->stats.xonrxc; | |
502 | regs_buff[70] = adapter->stats.xontxc; | |
503 | regs_buff[71] = adapter->stats.xoffrxc; | |
504 | regs_buff[72] = adapter->stats.xofftxc; | |
505 | regs_buff[73] = adapter->stats.fcruc; | |
506 | regs_buff[74] = adapter->stats.prc64; | |
507 | regs_buff[75] = adapter->stats.prc127; | |
508 | regs_buff[76] = adapter->stats.prc255; | |
509 | regs_buff[77] = adapter->stats.prc511; | |
510 | regs_buff[78] = adapter->stats.prc1023; | |
511 | regs_buff[79] = adapter->stats.prc1522; | |
512 | regs_buff[80] = adapter->stats.gprc; | |
513 | regs_buff[81] = adapter->stats.bprc; | |
514 | regs_buff[82] = adapter->stats.mprc; | |
515 | regs_buff[83] = adapter->stats.gptc; | |
516 | regs_buff[84] = adapter->stats.gorc; | |
517 | regs_buff[86] = adapter->stats.gotc; | |
518 | regs_buff[88] = adapter->stats.rnbc; | |
519 | regs_buff[89] = adapter->stats.ruc; | |
520 | regs_buff[90] = adapter->stats.rfc; | |
521 | regs_buff[91] = adapter->stats.roc; | |
522 | regs_buff[92] = adapter->stats.rjc; | |
523 | regs_buff[93] = adapter->stats.mgprc; | |
524 | regs_buff[94] = adapter->stats.mgpdc; | |
525 | regs_buff[95] = adapter->stats.mgptc; | |
526 | regs_buff[96] = adapter->stats.tor; | |
527 | regs_buff[98] = adapter->stats.tot; | |
528 | regs_buff[100] = adapter->stats.tpr; | |
529 | regs_buff[101] = adapter->stats.tpt; | |
530 | regs_buff[102] = adapter->stats.ptc64; | |
531 | regs_buff[103] = adapter->stats.ptc127; | |
532 | regs_buff[104] = adapter->stats.ptc255; | |
533 | regs_buff[105] = adapter->stats.ptc511; | |
534 | regs_buff[106] = adapter->stats.ptc1023; | |
535 | regs_buff[107] = adapter->stats.ptc1522; | |
536 | regs_buff[108] = adapter->stats.mptc; | |
537 | regs_buff[109] = adapter->stats.bptc; | |
538 | regs_buff[110] = adapter->stats.tsctc; | |
539 | regs_buff[111] = adapter->stats.iac; | |
540 | regs_buff[112] = adapter->stats.rpthc; | |
541 | regs_buff[113] = adapter->stats.hgptc; | |
542 | regs_buff[114] = adapter->stats.hgorc; | |
543 | regs_buff[116] = adapter->stats.hgotc; | |
544 | regs_buff[118] = adapter->stats.lenerrs; | |
545 | regs_buff[119] = adapter->stats.scvpc; | |
546 | regs_buff[120] = adapter->stats.hrmpc; | |
547 | ||
9d5c8243 AK |
548 | for (i = 0; i < 4; i++) |
549 | regs_buff[121 + i] = rd32(E1000_SRRCTL(i)); | |
550 | for (i = 0; i < 4; i++) | |
83ab50a5 | 551 | regs_buff[125 + i] = rd32(E1000_PSRTYPE(i)); |
9d5c8243 AK |
552 | for (i = 0; i < 4; i++) |
553 | regs_buff[129 + i] = rd32(E1000_RDBAL(i)); | |
554 | for (i = 0; i < 4; i++) | |
555 | regs_buff[133 + i] = rd32(E1000_RDBAH(i)); | |
556 | for (i = 0; i < 4; i++) | |
557 | regs_buff[137 + i] = rd32(E1000_RDLEN(i)); | |
558 | for (i = 0; i < 4; i++) | |
559 | regs_buff[141 + i] = rd32(E1000_RDH(i)); | |
560 | for (i = 0; i < 4; i++) | |
561 | regs_buff[145 + i] = rd32(E1000_RDT(i)); | |
562 | for (i = 0; i < 4; i++) | |
563 | regs_buff[149 + i] = rd32(E1000_RXDCTL(i)); | |
564 | ||
565 | for (i = 0; i < 10; i++) | |
566 | regs_buff[153 + i] = rd32(E1000_EITR(i)); | |
567 | for (i = 0; i < 8; i++) | |
568 | regs_buff[163 + i] = rd32(E1000_IMIR(i)); | |
569 | for (i = 0; i < 8; i++) | |
570 | regs_buff[171 + i] = rd32(E1000_IMIREXT(i)); | |
571 | for (i = 0; i < 16; i++) | |
572 | regs_buff[179 + i] = rd32(E1000_RAL(i)); | |
573 | for (i = 0; i < 16; i++) | |
574 | regs_buff[195 + i] = rd32(E1000_RAH(i)); | |
575 | ||
576 | for (i = 0; i < 4; i++) | |
577 | regs_buff[211 + i] = rd32(E1000_TDBAL(i)); | |
578 | for (i = 0; i < 4; i++) | |
579 | regs_buff[215 + i] = rd32(E1000_TDBAH(i)); | |
580 | for (i = 0; i < 4; i++) | |
581 | regs_buff[219 + i] = rd32(E1000_TDLEN(i)); | |
582 | for (i = 0; i < 4; i++) | |
583 | regs_buff[223 + i] = rd32(E1000_TDH(i)); | |
584 | for (i = 0; i < 4; i++) | |
585 | regs_buff[227 + i] = rd32(E1000_TDT(i)); | |
586 | for (i = 0; i < 4; i++) | |
587 | regs_buff[231 + i] = rd32(E1000_TXDCTL(i)); | |
588 | for (i = 0; i < 4; i++) | |
589 | regs_buff[235 + i] = rd32(E1000_TDWBAL(i)); | |
590 | for (i = 0; i < 4; i++) | |
591 | regs_buff[239 + i] = rd32(E1000_TDWBAH(i)); | |
592 | for (i = 0; i < 4; i++) | |
593 | regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i)); | |
594 | ||
595 | for (i = 0; i < 4; i++) | |
596 | regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i)); | |
597 | for (i = 0; i < 4; i++) | |
598 | regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i)); | |
599 | for (i = 0; i < 32; i++) | |
600 | regs_buff[255 + i] = rd32(E1000_WUPM_REG(i)); | |
601 | for (i = 0; i < 128; i++) | |
602 | regs_buff[287 + i] = rd32(E1000_FFMT_REG(i)); | |
603 | for (i = 0; i < 128; i++) | |
604 | regs_buff[415 + i] = rd32(E1000_FFVT_REG(i)); | |
605 | for (i = 0; i < 4; i++) | |
606 | regs_buff[543 + i] = rd32(E1000_FFLT_REG(i)); | |
607 | ||
608 | regs_buff[547] = rd32(E1000_TDFH); | |
609 | regs_buff[548] = rd32(E1000_TDFT); | |
610 | regs_buff[549] = rd32(E1000_TDFHS); | |
611 | regs_buff[550] = rd32(E1000_TDFPC); | |
f96a8a0b CW |
612 | |
613 | if (hw->mac.type > e1000_82580) { | |
614 | regs_buff[551] = adapter->stats.o2bgptc; | |
615 | regs_buff[552] = adapter->stats.b2ospc; | |
616 | regs_buff[553] = adapter->stats.o2bspc; | |
617 | regs_buff[554] = adapter->stats.b2ogprc; | |
618 | } | |
7e3b4ffb KS |
619 | |
620 | if (hw->mac.type != e1000_82576) | |
621 | return; | |
622 | for (i = 0; i < 12; i++) | |
623 | regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4)); | |
624 | for (i = 0; i < 4; i++) | |
625 | regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4)); | |
626 | for (i = 0; i < 12; i++) | |
627 | regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4)); | |
628 | for (i = 0; i < 12; i++) | |
629 | regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4)); | |
630 | for (i = 0; i < 12; i++) | |
631 | regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4)); | |
632 | for (i = 0; i < 12; i++) | |
633 | regs_buff[607 + i] = rd32(E1000_RDH(i + 4)); | |
634 | for (i = 0; i < 12; i++) | |
635 | regs_buff[619 + i] = rd32(E1000_RDT(i + 4)); | |
636 | for (i = 0; i < 12; i++) | |
637 | regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4)); | |
638 | ||
639 | for (i = 0; i < 12; i++) | |
640 | regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4)); | |
641 | for (i = 0; i < 12; i++) | |
642 | regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4)); | |
643 | for (i = 0; i < 12; i++) | |
644 | regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4)); | |
645 | for (i = 0; i < 12; i++) | |
646 | regs_buff[679 + i] = rd32(E1000_TDH(i + 4)); | |
647 | for (i = 0; i < 12; i++) | |
648 | regs_buff[691 + i] = rd32(E1000_TDT(i + 4)); | |
649 | for (i = 0; i < 12; i++) | |
650 | regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4)); | |
651 | for (i = 0; i < 12; i++) | |
652 | regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4)); | |
653 | for (i = 0; i < 12; i++) | |
654 | regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4)); | |
9d5c8243 AK |
655 | } |
656 | ||
657 | static int igb_get_eeprom_len(struct net_device *netdev) | |
658 | { | |
659 | struct igb_adapter *adapter = netdev_priv(netdev); | |
660 | return adapter->hw.nvm.word_size * 2; | |
661 | } | |
662 | ||
663 | static int igb_get_eeprom(struct net_device *netdev, | |
664 | struct ethtool_eeprom *eeprom, u8 *bytes) | |
665 | { | |
666 | struct igb_adapter *adapter = netdev_priv(netdev); | |
667 | struct e1000_hw *hw = &adapter->hw; | |
668 | u16 *eeprom_buff; | |
669 | int first_word, last_word; | |
670 | int ret_val = 0; | |
671 | u16 i; | |
672 | ||
673 | if (eeprom->len == 0) | |
674 | return -EINVAL; | |
675 | ||
676 | eeprom->magic = hw->vendor_id | (hw->device_id << 16); | |
677 | ||
678 | first_word = eeprom->offset >> 1; | |
679 | last_word = (eeprom->offset + eeprom->len - 1) >> 1; | |
680 | ||
681 | eeprom_buff = kmalloc(sizeof(u16) * | |
682 | (last_word - first_word + 1), GFP_KERNEL); | |
683 | if (!eeprom_buff) | |
684 | return -ENOMEM; | |
685 | ||
686 | if (hw->nvm.type == e1000_nvm_eeprom_spi) | |
312c75ae | 687 | ret_val = hw->nvm.ops.read(hw, first_word, |
9d5c8243 AK |
688 | last_word - first_word + 1, |
689 | eeprom_buff); | |
690 | else { | |
691 | for (i = 0; i < last_word - first_word + 1; i++) { | |
312c75ae | 692 | ret_val = hw->nvm.ops.read(hw, first_word + i, 1, |
9d5c8243 AK |
693 | &eeprom_buff[i]); |
694 | if (ret_val) | |
695 | break; | |
696 | } | |
697 | } | |
698 | ||
699 | /* Device's eeprom is always little-endian, word addressable */ | |
700 | for (i = 0; i < last_word - first_word + 1; i++) | |
701 | le16_to_cpus(&eeprom_buff[i]); | |
702 | ||
703 | memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), | |
704 | eeprom->len); | |
705 | kfree(eeprom_buff); | |
706 | ||
707 | return ret_val; | |
708 | } | |
709 | ||
710 | static int igb_set_eeprom(struct net_device *netdev, | |
711 | struct ethtool_eeprom *eeprom, u8 *bytes) | |
712 | { | |
713 | struct igb_adapter *adapter = netdev_priv(netdev); | |
714 | struct e1000_hw *hw = &adapter->hw; | |
715 | u16 *eeprom_buff; | |
716 | void *ptr; | |
717 | int max_len, first_word, last_word, ret_val = 0; | |
718 | u16 i; | |
719 | ||
720 | if (eeprom->len == 0) | |
721 | return -EOPNOTSUPP; | |
722 | ||
f96a8a0b CW |
723 | if (hw->mac.type == e1000_i211) |
724 | return -EOPNOTSUPP; | |
725 | ||
9d5c8243 AK |
726 | if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) |
727 | return -EFAULT; | |
728 | ||
729 | max_len = hw->nvm.word_size * 2; | |
730 | ||
731 | first_word = eeprom->offset >> 1; | |
732 | last_word = (eeprom->offset + eeprom->len - 1) >> 1; | |
733 | eeprom_buff = kmalloc(max_len, GFP_KERNEL); | |
734 | if (!eeprom_buff) | |
735 | return -ENOMEM; | |
736 | ||
737 | ptr = (void *)eeprom_buff; | |
738 | ||
739 | if (eeprom->offset & 1) { | |
740 | /* need read/modify/write of first changed EEPROM word */ | |
741 | /* only the second byte of the word is being modified */ | |
312c75ae | 742 | ret_val = hw->nvm.ops.read(hw, first_word, 1, |
9d5c8243 AK |
743 | &eeprom_buff[0]); |
744 | ptr++; | |
745 | } | |
746 | if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) { | |
747 | /* need read/modify/write of last changed EEPROM word */ | |
748 | /* only the first byte of the word is being modified */ | |
312c75ae | 749 | ret_val = hw->nvm.ops.read(hw, last_word, 1, |
9d5c8243 AK |
750 | &eeprom_buff[last_word - first_word]); |
751 | } | |
752 | ||
753 | /* Device's eeprom is always little-endian, word addressable */ | |
754 | for (i = 0; i < last_word - first_word + 1; i++) | |
755 | le16_to_cpus(&eeprom_buff[i]); | |
756 | ||
757 | memcpy(ptr, bytes, eeprom->len); | |
758 | ||
759 | for (i = 0; i < last_word - first_word + 1; i++) | |
760 | eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]); | |
761 | ||
312c75ae | 762 | ret_val = hw->nvm.ops.write(hw, first_word, |
9d5c8243 AK |
763 | last_word - first_word + 1, eeprom_buff); |
764 | ||
765 | /* Update the checksum over the first part of the EEPROM if needed | |
766 | * and flush shadow RAM for 82573 controllers */ | |
767 | if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG))) | |
4322e561 | 768 | hw->nvm.ops.update(hw); |
9d5c8243 | 769 | |
d67974f0 | 770 | igb_set_fw_version(adapter); |
9d5c8243 AK |
771 | kfree(eeprom_buff); |
772 | return ret_val; | |
773 | } | |
774 | ||
775 | static void igb_get_drvinfo(struct net_device *netdev, | |
776 | struct ethtool_drvinfo *drvinfo) | |
777 | { | |
778 | struct igb_adapter *adapter = netdev_priv(netdev); | |
9d5c8243 | 779 | |
612a94d6 RJ |
780 | strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver)); |
781 | strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version)); | |
9d5c8243 | 782 | |
d67974f0 CW |
783 | /* |
784 | * EEPROM image version # is reported as firmware version # for | |
785 | * 82575 controllers | |
786 | */ | |
787 | strlcpy(drvinfo->fw_version, adapter->fw_version, | |
788 | sizeof(drvinfo->fw_version)); | |
612a94d6 RJ |
789 | strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), |
790 | sizeof(drvinfo->bus_info)); | |
9d5c8243 AK |
791 | drvinfo->n_stats = IGB_STATS_LEN; |
792 | drvinfo->testinfo_len = IGB_TEST_LEN; | |
793 | drvinfo->regdump_len = igb_get_regs_len(netdev); | |
794 | drvinfo->eedump_len = igb_get_eeprom_len(netdev); | |
795 | } | |
796 | ||
797 | static void igb_get_ringparam(struct net_device *netdev, | |
798 | struct ethtool_ringparam *ring) | |
799 | { | |
800 | struct igb_adapter *adapter = netdev_priv(netdev); | |
9d5c8243 AK |
801 | |
802 | ring->rx_max_pending = IGB_MAX_RXD; | |
803 | ring->tx_max_pending = IGB_MAX_TXD; | |
68fd9910 AD |
804 | ring->rx_pending = adapter->rx_ring_count; |
805 | ring->tx_pending = adapter->tx_ring_count; | |
9d5c8243 AK |
806 | } |
807 | ||
808 | static int igb_set_ringparam(struct net_device *netdev, | |
809 | struct ethtool_ringparam *ring) | |
810 | { | |
811 | struct igb_adapter *adapter = netdev_priv(netdev); | |
68fd9910 | 812 | struct igb_ring *temp_ring; |
6d9f4fc4 | 813 | int i, err = 0; |
0e15439a | 814 | u16 new_rx_count, new_tx_count; |
9d5c8243 AK |
815 | |
816 | if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) | |
817 | return -EINVAL; | |
818 | ||
0e15439a AD |
819 | new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD); |
820 | new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD); | |
9d5c8243 AK |
821 | new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE); |
822 | ||
0e15439a AD |
823 | new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD); |
824 | new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD); | |
9d5c8243 AK |
825 | new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE); |
826 | ||
68fd9910 AD |
827 | if ((new_tx_count == adapter->tx_ring_count) && |
828 | (new_rx_count == adapter->rx_ring_count)) { | |
9d5c8243 AK |
829 | /* nothing to do */ |
830 | return 0; | |
831 | } | |
832 | ||
6d9f4fc4 AD |
833 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) |
834 | msleep(1); | |
835 | ||
836 | if (!netif_running(adapter->netdev)) { | |
837 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 838 | adapter->tx_ring[i]->count = new_tx_count; |
6d9f4fc4 | 839 | for (i = 0; i < adapter->num_rx_queues; i++) |
3025a446 | 840 | adapter->rx_ring[i]->count = new_rx_count; |
6d9f4fc4 AD |
841 | adapter->tx_ring_count = new_tx_count; |
842 | adapter->rx_ring_count = new_rx_count; | |
843 | goto clear_reset; | |
844 | } | |
845 | ||
68fd9910 AD |
846 | if (adapter->num_tx_queues > adapter->num_rx_queues) |
847 | temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring)); | |
848 | else | |
849 | temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring)); | |
68fd9910 | 850 | |
6d9f4fc4 AD |
851 | if (!temp_ring) { |
852 | err = -ENOMEM; | |
853 | goto clear_reset; | |
854 | } | |
9d5c8243 | 855 | |
6d9f4fc4 | 856 | igb_down(adapter); |
9d5c8243 AK |
857 | |
858 | /* | |
859 | * We can't just free everything and then setup again, | |
860 | * because the ISRs in MSI-X mode get passed pointers | |
861 | * to the tx and rx ring structs. | |
862 | */ | |
68fd9910 | 863 | if (new_tx_count != adapter->tx_ring_count) { |
9d5c8243 | 864 | for (i = 0; i < adapter->num_tx_queues; i++) { |
3025a446 AD |
865 | memcpy(&temp_ring[i], adapter->tx_ring[i], |
866 | sizeof(struct igb_ring)); | |
867 | ||
68fd9910 | 868 | temp_ring[i].count = new_tx_count; |
80785298 | 869 | err = igb_setup_tx_resources(&temp_ring[i]); |
9d5c8243 | 870 | if (err) { |
68fd9910 AD |
871 | while (i) { |
872 | i--; | |
873 | igb_free_tx_resources(&temp_ring[i]); | |
874 | } | |
9d5c8243 AK |
875 | goto err_setup; |
876 | } | |
9d5c8243 | 877 | } |
68fd9910 | 878 | |
3025a446 AD |
879 | for (i = 0; i < adapter->num_tx_queues; i++) { |
880 | igb_free_tx_resources(adapter->tx_ring[i]); | |
68fd9910 | 881 | |
3025a446 AD |
882 | memcpy(adapter->tx_ring[i], &temp_ring[i], |
883 | sizeof(struct igb_ring)); | |
884 | } | |
68fd9910 AD |
885 | |
886 | adapter->tx_ring_count = new_tx_count; | |
9d5c8243 AK |
887 | } |
888 | ||
3025a446 | 889 | if (new_rx_count != adapter->rx_ring_count) { |
68fd9910 | 890 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3025a446 AD |
891 | memcpy(&temp_ring[i], adapter->rx_ring[i], |
892 | sizeof(struct igb_ring)); | |
893 | ||
68fd9910 | 894 | temp_ring[i].count = new_rx_count; |
80785298 | 895 | err = igb_setup_rx_resources(&temp_ring[i]); |
9d5c8243 | 896 | if (err) { |
68fd9910 AD |
897 | while (i) { |
898 | i--; | |
899 | igb_free_rx_resources(&temp_ring[i]); | |
900 | } | |
9d5c8243 AK |
901 | goto err_setup; |
902 | } | |
903 | ||
9d5c8243 | 904 | } |
68fd9910 | 905 | |
3025a446 AD |
906 | for (i = 0; i < adapter->num_rx_queues; i++) { |
907 | igb_free_rx_resources(adapter->rx_ring[i]); | |
68fd9910 | 908 | |
3025a446 AD |
909 | memcpy(adapter->rx_ring[i], &temp_ring[i], |
910 | sizeof(struct igb_ring)); | |
911 | } | |
68fd9910 AD |
912 | |
913 | adapter->rx_ring_count = new_rx_count; | |
9d5c8243 | 914 | } |
9d5c8243 | 915 | err_setup: |
6d9f4fc4 | 916 | igb_up(adapter); |
68fd9910 | 917 | vfree(temp_ring); |
6d9f4fc4 AD |
918 | clear_reset: |
919 | clear_bit(__IGB_RESETTING, &adapter->state); | |
9d5c8243 AK |
920 | return err; |
921 | } | |
922 | ||
923 | /* ethtool register test data */ | |
924 | struct igb_reg_test { | |
925 | u16 reg; | |
2d064c06 AD |
926 | u16 reg_offset; |
927 | u16 array_len; | |
928 | u16 test_type; | |
9d5c8243 AK |
929 | u32 mask; |
930 | u32 write; | |
931 | }; | |
932 | ||
933 | /* In the hardware, registers are laid out either singly, in arrays | |
934 | * spaced 0x100 bytes apart, or in contiguous tables. We assume | |
935 | * most tests take place on arrays or single registers (handled | |
936 | * as a single-element array) and special-case the tables. | |
937 | * Table tests are always pattern tests. | |
938 | * | |
939 | * We also make provision for some required setup steps by specifying | |
940 | * registers to be written without any read-back testing. | |
941 | */ | |
942 | ||
943 | #define PATTERN_TEST 1 | |
944 | #define SET_READ_TEST 2 | |
945 | #define WRITE_NO_TEST 3 | |
946 | #define TABLE32_TEST 4 | |
947 | #define TABLE64_TEST_LO 5 | |
948 | #define TABLE64_TEST_HI 6 | |
949 | ||
f96a8a0b CW |
950 | /* i210 reg test */ |
951 | static struct igb_reg_test reg_test_i210[] = { | |
952 | { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
953 | { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | |
954 | { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | |
955 | { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
956 | { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
957 | { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, | |
958 | /* RDH is read-only for i210, only test RDT. */ | |
959 | { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
960 | { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, | |
961 | { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
962 | { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, | |
963 | { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
964 | { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
965 | { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, | |
966 | { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
967 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | |
968 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, | |
969 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, | |
970 | { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | |
971 | { E1000_RA, 0, 16, TABLE64_TEST_LO, | |
972 | 0xFFFFFFFF, 0xFFFFFFFF }, | |
973 | { E1000_RA, 0, 16, TABLE64_TEST_HI, | |
974 | 0x900FFFFF, 0xFFFFFFFF }, | |
975 | { E1000_MTA, 0, 128, TABLE32_TEST, | |
976 | 0xFFFFFFFF, 0xFFFFFFFF }, | |
977 | { 0, 0, 0, 0, 0 } | |
978 | }; | |
979 | ||
d2ba2ed8 AD |
980 | /* i350 reg test */ |
981 | static struct igb_reg_test reg_test_i350[] = { | |
982 | { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
983 | { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | |
984 | { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | |
985 | { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 }, | |
986 | { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
987 | { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1b6e6618 | 988 | { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, |
d2ba2ed8 AD |
989 | { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, |
990 | { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1b6e6618 | 991 | { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, |
d2ba2ed8 AD |
992 | /* RDH is read-only for i350, only test RDT. */ |
993 | { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
994 | { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
995 | { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, | |
996 | { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
997 | { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, | |
998 | { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
999 | { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1b6e6618 | 1000 | { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, |
d2ba2ed8 AD |
1001 | { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, |
1002 | { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1b6e6618 | 1003 | { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, |
d2ba2ed8 AD |
1004 | { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, |
1005 | { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
1006 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | |
1007 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, | |
1008 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, | |
1009 | { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | |
1010 | { E1000_RA, 0, 16, TABLE64_TEST_LO, | |
1011 | 0xFFFFFFFF, 0xFFFFFFFF }, | |
1012 | { E1000_RA, 0, 16, TABLE64_TEST_HI, | |
1013 | 0xC3FFFFFF, 0xFFFFFFFF }, | |
1014 | { E1000_RA2, 0, 16, TABLE64_TEST_LO, | |
1015 | 0xFFFFFFFF, 0xFFFFFFFF }, | |
1016 | { E1000_RA2, 0, 16, TABLE64_TEST_HI, | |
1017 | 0xC3FFFFFF, 0xFFFFFFFF }, | |
1018 | { E1000_MTA, 0, 128, TABLE32_TEST, | |
1019 | 0xFFFFFFFF, 0xFFFFFFFF }, | |
1020 | { 0, 0, 0, 0 } | |
1021 | }; | |
1022 | ||
55cac248 AD |
1023 | /* 82580 reg test */ |
1024 | static struct igb_reg_test reg_test_82580[] = { | |
1025 | { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1026 | { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | |
1027 | { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | |
1028 | { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1029 | { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
1030 | { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1031 | { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | |
1032 | { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
1033 | { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1034 | { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | |
1035 | /* RDH is read-only for 82580, only test RDT. */ | |
1036 | { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
1037 | { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
1038 | { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, | |
1039 | { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
1040 | { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, | |
1041 | { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
1042 | { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1043 | { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | |
1044 | { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
1045 | { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1046 | { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | |
1047 | { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
1048 | { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
1049 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | |
1050 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, | |
1051 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, | |
1052 | { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | |
1053 | { E1000_RA, 0, 16, TABLE64_TEST_LO, | |
1054 | 0xFFFFFFFF, 0xFFFFFFFF }, | |
1055 | { E1000_RA, 0, 16, TABLE64_TEST_HI, | |
1056 | 0x83FFFFFF, 0xFFFFFFFF }, | |
1057 | { E1000_RA2, 0, 8, TABLE64_TEST_LO, | |
1058 | 0xFFFFFFFF, 0xFFFFFFFF }, | |
1059 | { E1000_RA2, 0, 8, TABLE64_TEST_HI, | |
1060 | 0x83FFFFFF, 0xFFFFFFFF }, | |
1061 | { E1000_MTA, 0, 128, TABLE32_TEST, | |
1062 | 0xFFFFFFFF, 0xFFFFFFFF }, | |
1063 | { 0, 0, 0, 0 } | |
1064 | }; | |
1065 | ||
2d064c06 AD |
1066 | /* 82576 reg test */ |
1067 | static struct igb_reg_test reg_test_82576[] = { | |
1068 | { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1069 | { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | |
1070 | { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | |
1071 | { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1072 | { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
1073 | { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1074 | { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | |
2753f4ce AD |
1075 | { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, |
1076 | { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1077 | { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | |
1078 | /* Enable all RX queues before testing. */ | |
1079 | { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, | |
1080 | { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, | |
2d064c06 AD |
1081 | /* RDH is read-only for 82576, only test RDT. */ |
1082 | { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
2753f4ce | 1083 | { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, |
2d064c06 | 1084 | { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, |
2753f4ce | 1085 | { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 }, |
2d064c06 AD |
1086 | { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, |
1087 | { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
1088 | { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, | |
1089 | { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
1090 | { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1091 | { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | |
2753f4ce AD |
1092 | { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, |
1093 | { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1094 | { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | |
2d064c06 AD |
1095 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, |
1096 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, | |
1097 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, | |
1098 | { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | |
1099 | { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1100 | { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, | |
1101 | { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1102 | { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, | |
1103 | { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1104 | { 0, 0, 0, 0 } | |
1105 | }; | |
1106 | ||
1107 | /* 82575 register test */ | |
9d5c8243 | 1108 | static struct igb_reg_test reg_test_82575[] = { |
2d064c06 AD |
1109 | { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, |
1110 | { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | |
1111 | { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | |
1112 | { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1113 | { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
1114 | { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1115 | { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, | |
9d5c8243 | 1116 | /* Enable all four RX queues before testing. */ |
2d064c06 | 1117 | { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, |
9d5c8243 | 1118 | /* RDH is read-only for 82575, only test RDT. */ |
2d064c06 AD |
1119 | { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, |
1120 | { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, | |
1121 | { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, | |
1122 | { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
1123 | { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, | |
1124 | { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
1125 | { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1126 | { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, | |
1127 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | |
1128 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB }, | |
1129 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF }, | |
1130 | { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | |
1131 | { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF }, | |
1132 | { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1133 | { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF }, | |
1134 | { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
9d5c8243 AK |
1135 | { 0, 0, 0, 0 } |
1136 | }; | |
1137 | ||
1138 | static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data, | |
1139 | int reg, u32 mask, u32 write) | |
1140 | { | |
2753f4ce | 1141 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 1142 | u32 pat, val; |
317f66bd | 1143 | static const u32 _test[] = |
9d5c8243 AK |
1144 | {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; |
1145 | for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { | |
2753f4ce | 1146 | wr32(reg, (_test[pat] & write)); |
93ed8359 | 1147 | val = rd32(reg) & mask; |
9d5c8243 | 1148 | if (val != (_test[pat] & write & mask)) { |
d836200a JJ |
1149 | dev_err(&adapter->pdev->dev, |
1150 | "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", | |
9d5c8243 AK |
1151 | reg, val, (_test[pat] & write & mask)); |
1152 | *data = reg; | |
1153 | return 1; | |
1154 | } | |
1155 | } | |
317f66bd | 1156 | |
9d5c8243 AK |
1157 | return 0; |
1158 | } | |
1159 | ||
1160 | static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data, | |
1161 | int reg, u32 mask, u32 write) | |
1162 | { | |
2753f4ce | 1163 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 1164 | u32 val; |
2753f4ce AD |
1165 | wr32(reg, write & mask); |
1166 | val = rd32(reg); | |
9d5c8243 | 1167 | if ((write & mask) != (val & mask)) { |
d836200a JJ |
1168 | dev_err(&adapter->pdev->dev, |
1169 | "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", reg, | |
9d5c8243 AK |
1170 | (val & mask), (write & mask)); |
1171 | *data = reg; | |
1172 | return 1; | |
1173 | } | |
317f66bd | 1174 | |
9d5c8243 AK |
1175 | return 0; |
1176 | } | |
1177 | ||
1178 | #define REG_PATTERN_TEST(reg, mask, write) \ | |
1179 | do { \ | |
1180 | if (reg_pattern_test(adapter, data, reg, mask, write)) \ | |
1181 | return 1; \ | |
1182 | } while (0) | |
1183 | ||
1184 | #define REG_SET_AND_CHECK(reg, mask, write) \ | |
1185 | do { \ | |
1186 | if (reg_set_and_check(adapter, data, reg, mask, write)) \ | |
1187 | return 1; \ | |
1188 | } while (0) | |
1189 | ||
1190 | static int igb_reg_test(struct igb_adapter *adapter, u64 *data) | |
1191 | { | |
1192 | struct e1000_hw *hw = &adapter->hw; | |
1193 | struct igb_reg_test *test; | |
1194 | u32 value, before, after; | |
1195 | u32 i, toggle; | |
1196 | ||
2d064c06 | 1197 | switch (adapter->hw.mac.type) { |
d2ba2ed8 AD |
1198 | case e1000_i350: |
1199 | test = reg_test_i350; | |
1200 | toggle = 0x7FEFF3FF; | |
1201 | break; | |
f96a8a0b CW |
1202 | case e1000_i210: |
1203 | case e1000_i211: | |
1204 | test = reg_test_i210; | |
1205 | toggle = 0x7FEFF3FF; | |
1206 | break; | |
55cac248 AD |
1207 | case e1000_82580: |
1208 | test = reg_test_82580; | |
1209 | toggle = 0x7FEFF3FF; | |
1210 | break; | |
2d064c06 AD |
1211 | case e1000_82576: |
1212 | test = reg_test_82576; | |
317f66bd | 1213 | toggle = 0x7FFFF3FF; |
2d064c06 AD |
1214 | break; |
1215 | default: | |
1216 | test = reg_test_82575; | |
317f66bd | 1217 | toggle = 0x7FFFF3FF; |
2d064c06 AD |
1218 | break; |
1219 | } | |
9d5c8243 AK |
1220 | |
1221 | /* Because the status register is such a special case, | |
1222 | * we handle it separately from the rest of the register | |
1223 | * tests. Some bits are read-only, some toggle, and some | |
1224 | * are writable on newer MACs. | |
1225 | */ | |
1226 | before = rd32(E1000_STATUS); | |
1227 | value = (rd32(E1000_STATUS) & toggle); | |
1228 | wr32(E1000_STATUS, toggle); | |
1229 | after = rd32(E1000_STATUS) & toggle; | |
1230 | if (value != after) { | |
d836200a JJ |
1231 | dev_err(&adapter->pdev->dev, |
1232 | "failed STATUS register test got: 0x%08X expected: 0x%08X\n", | |
1233 | after, value); | |
9d5c8243 AK |
1234 | *data = 1; |
1235 | return 1; | |
1236 | } | |
1237 | /* restore previous status */ | |
1238 | wr32(E1000_STATUS, before); | |
1239 | ||
1240 | /* Perform the remainder of the register test, looping through | |
1241 | * the test table until we either fail or reach the null entry. | |
1242 | */ | |
1243 | while (test->reg) { | |
1244 | for (i = 0; i < test->array_len; i++) { | |
1245 | switch (test->test_type) { | |
1246 | case PATTERN_TEST: | |
2753f4ce AD |
1247 | REG_PATTERN_TEST(test->reg + |
1248 | (i * test->reg_offset), | |
9d5c8243 AK |
1249 | test->mask, |
1250 | test->write); | |
1251 | break; | |
1252 | case SET_READ_TEST: | |
2753f4ce AD |
1253 | REG_SET_AND_CHECK(test->reg + |
1254 | (i * test->reg_offset), | |
9d5c8243 AK |
1255 | test->mask, |
1256 | test->write); | |
1257 | break; | |
1258 | case WRITE_NO_TEST: | |
1259 | writel(test->write, | |
1260 | (adapter->hw.hw_addr + test->reg) | |
2d064c06 | 1261 | + (i * test->reg_offset)); |
9d5c8243 AK |
1262 | break; |
1263 | case TABLE32_TEST: | |
1264 | REG_PATTERN_TEST(test->reg + (i * 4), | |
1265 | test->mask, | |
1266 | test->write); | |
1267 | break; | |
1268 | case TABLE64_TEST_LO: | |
1269 | REG_PATTERN_TEST(test->reg + (i * 8), | |
1270 | test->mask, | |
1271 | test->write); | |
1272 | break; | |
1273 | case TABLE64_TEST_HI: | |
1274 | REG_PATTERN_TEST((test->reg + 4) + (i * 8), | |
1275 | test->mask, | |
1276 | test->write); | |
1277 | break; | |
1278 | } | |
1279 | } | |
1280 | test++; | |
1281 | } | |
1282 | ||
1283 | *data = 0; | |
1284 | return 0; | |
1285 | } | |
1286 | ||
1287 | static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data) | |
1288 | { | |
9d5c8243 | 1289 | *data = 0; |
9d5c8243 | 1290 | |
f96a8a0b CW |
1291 | /* Validate eeprom on all parts but i211 */ |
1292 | if (adapter->hw.mac.type != e1000_i211) { | |
1293 | if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) | |
1294 | *data = 2; | |
1295 | } | |
9d5c8243 AK |
1296 | |
1297 | return *data; | |
1298 | } | |
1299 | ||
1300 | static irqreturn_t igb_test_intr(int irq, void *data) | |
1301 | { | |
317f66bd | 1302 | struct igb_adapter *adapter = (struct igb_adapter *) data; |
9d5c8243 AK |
1303 | struct e1000_hw *hw = &adapter->hw; |
1304 | ||
1305 | adapter->test_icr |= rd32(E1000_ICR); | |
1306 | ||
1307 | return IRQ_HANDLED; | |
1308 | } | |
1309 | ||
1310 | static int igb_intr_test(struct igb_adapter *adapter, u64 *data) | |
1311 | { | |
1312 | struct e1000_hw *hw = &adapter->hw; | |
1313 | struct net_device *netdev = adapter->netdev; | |
2753f4ce | 1314 | u32 mask, ics_mask, i = 0, shared_int = true; |
9d5c8243 AK |
1315 | u32 irq = adapter->pdev->irq; |
1316 | ||
1317 | *data = 0; | |
1318 | ||
1319 | /* Hook up test interrupt handler just for this test */ | |
4eefa8f0 AD |
1320 | if (adapter->msix_entries) { |
1321 | if (request_irq(adapter->msix_entries[0].vector, | |
a0607fd3 | 1322 | igb_test_intr, 0, netdev->name, adapter)) { |
4eefa8f0 AD |
1323 | *data = 1; |
1324 | return -1; | |
1325 | } | |
4eefa8f0 | 1326 | } else if (adapter->flags & IGB_FLAG_HAS_MSI) { |
9d5c8243 | 1327 | shared_int = false; |
4eefa8f0 | 1328 | if (request_irq(irq, |
a0607fd3 | 1329 | igb_test_intr, 0, netdev->name, adapter)) { |
9d5c8243 AK |
1330 | *data = 1; |
1331 | return -1; | |
1332 | } | |
a0607fd3 | 1333 | } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED, |
4eefa8f0 | 1334 | netdev->name, adapter)) { |
9d5c8243 | 1335 | shared_int = false; |
a0607fd3 | 1336 | } else if (request_irq(irq, igb_test_intr, IRQF_SHARED, |
4eefa8f0 | 1337 | netdev->name, adapter)) { |
9d5c8243 AK |
1338 | *data = 1; |
1339 | return -1; | |
1340 | } | |
1341 | dev_info(&adapter->pdev->dev, "testing %s interrupt\n", | |
1342 | (shared_int ? "shared" : "unshared")); | |
317f66bd | 1343 | |
9d5c8243 | 1344 | /* Disable all the interrupts */ |
4eefa8f0 | 1345 | wr32(E1000_IMC, ~0); |
945a5151 | 1346 | wrfl(); |
9d5c8243 AK |
1347 | msleep(10); |
1348 | ||
2753f4ce | 1349 | /* Define all writable bits for ICS */ |
4eefa8f0 | 1350 | switch (hw->mac.type) { |
2753f4ce AD |
1351 | case e1000_82575: |
1352 | ics_mask = 0x37F47EDD; | |
1353 | break; | |
1354 | case e1000_82576: | |
1355 | ics_mask = 0x77D4FBFD; | |
1356 | break; | |
55cac248 AD |
1357 | case e1000_82580: |
1358 | ics_mask = 0x77DCFED5; | |
1359 | break; | |
d2ba2ed8 | 1360 | case e1000_i350: |
f96a8a0b CW |
1361 | case e1000_i210: |
1362 | case e1000_i211: | |
d2ba2ed8 AD |
1363 | ics_mask = 0x77DCFED5; |
1364 | break; | |
2753f4ce AD |
1365 | default: |
1366 | ics_mask = 0x7FFFFFFF; | |
1367 | break; | |
1368 | } | |
1369 | ||
9d5c8243 | 1370 | /* Test each interrupt */ |
2753f4ce | 1371 | for (; i < 31; i++) { |
9d5c8243 AK |
1372 | /* Interrupt to test */ |
1373 | mask = 1 << i; | |
1374 | ||
2753f4ce AD |
1375 | if (!(mask & ics_mask)) |
1376 | continue; | |
1377 | ||
9d5c8243 AK |
1378 | if (!shared_int) { |
1379 | /* Disable the interrupt to be reported in | |
1380 | * the cause register and then force the same | |
1381 | * interrupt and see if one gets posted. If | |
1382 | * an interrupt was posted to the bus, the | |
1383 | * test failed. | |
1384 | */ | |
1385 | adapter->test_icr = 0; | |
2753f4ce AD |
1386 | |
1387 | /* Flush any pending interrupts */ | |
1388 | wr32(E1000_ICR, ~0); | |
1389 | ||
1390 | wr32(E1000_IMC, mask); | |
1391 | wr32(E1000_ICS, mask); | |
945a5151 | 1392 | wrfl(); |
9d5c8243 AK |
1393 | msleep(10); |
1394 | ||
1395 | if (adapter->test_icr & mask) { | |
1396 | *data = 3; | |
1397 | break; | |
1398 | } | |
1399 | } | |
1400 | ||
1401 | /* Enable the interrupt to be reported in | |
1402 | * the cause register and then force the same | |
1403 | * interrupt and see if one gets posted. If | |
1404 | * an interrupt was not posted to the bus, the | |
1405 | * test failed. | |
1406 | */ | |
1407 | adapter->test_icr = 0; | |
2753f4ce AD |
1408 | |
1409 | /* Flush any pending interrupts */ | |
1410 | wr32(E1000_ICR, ~0); | |
1411 | ||
9d5c8243 AK |
1412 | wr32(E1000_IMS, mask); |
1413 | wr32(E1000_ICS, mask); | |
945a5151 | 1414 | wrfl(); |
9d5c8243 AK |
1415 | msleep(10); |
1416 | ||
1417 | if (!(adapter->test_icr & mask)) { | |
1418 | *data = 4; | |
1419 | break; | |
1420 | } | |
1421 | ||
1422 | if (!shared_int) { | |
1423 | /* Disable the other interrupts to be reported in | |
1424 | * the cause register and then force the other | |
1425 | * interrupts and see if any get posted. If | |
1426 | * an interrupt was posted to the bus, the | |
1427 | * test failed. | |
1428 | */ | |
1429 | adapter->test_icr = 0; | |
2753f4ce AD |
1430 | |
1431 | /* Flush any pending interrupts */ | |
1432 | wr32(E1000_ICR, ~0); | |
1433 | ||
1434 | wr32(E1000_IMC, ~mask); | |
1435 | wr32(E1000_ICS, ~mask); | |
945a5151 | 1436 | wrfl(); |
9d5c8243 AK |
1437 | msleep(10); |
1438 | ||
2753f4ce | 1439 | if (adapter->test_icr & mask) { |
9d5c8243 AK |
1440 | *data = 5; |
1441 | break; | |
1442 | } | |
1443 | } | |
1444 | } | |
1445 | ||
1446 | /* Disable all the interrupts */ | |
2753f4ce | 1447 | wr32(E1000_IMC, ~0); |
945a5151 | 1448 | wrfl(); |
9d5c8243 AK |
1449 | msleep(10); |
1450 | ||
1451 | /* Unhook test interrupt handler */ | |
4eefa8f0 AD |
1452 | if (adapter->msix_entries) |
1453 | free_irq(adapter->msix_entries[0].vector, adapter); | |
1454 | else | |
1455 | free_irq(irq, adapter); | |
9d5c8243 AK |
1456 | |
1457 | return *data; | |
1458 | } | |
1459 | ||
1460 | static void igb_free_desc_rings(struct igb_adapter *adapter) | |
1461 | { | |
d7ee5b3a AD |
1462 | igb_free_tx_resources(&adapter->test_tx_ring); |
1463 | igb_free_rx_resources(&adapter->test_rx_ring); | |
9d5c8243 AK |
1464 | } |
1465 | ||
1466 | static int igb_setup_desc_rings(struct igb_adapter *adapter) | |
1467 | { | |
9d5c8243 AK |
1468 | struct igb_ring *tx_ring = &adapter->test_tx_ring; |
1469 | struct igb_ring *rx_ring = &adapter->test_rx_ring; | |
d7ee5b3a | 1470 | struct e1000_hw *hw = &adapter->hw; |
ad93d17e | 1471 | int ret_val; |
9d5c8243 AK |
1472 | |
1473 | /* Setup Tx descriptor ring and Tx buffers */ | |
d7ee5b3a | 1474 | tx_ring->count = IGB_DEFAULT_TXD; |
59d71989 | 1475 | tx_ring->dev = &adapter->pdev->dev; |
d7ee5b3a AD |
1476 | tx_ring->netdev = adapter->netdev; |
1477 | tx_ring->reg_idx = adapter->vfs_allocated_count; | |
9d5c8243 | 1478 | |
d7ee5b3a | 1479 | if (igb_setup_tx_resources(tx_ring)) { |
9d5c8243 AK |
1480 | ret_val = 1; |
1481 | goto err_nomem; | |
1482 | } | |
1483 | ||
d7ee5b3a AD |
1484 | igb_setup_tctl(adapter); |
1485 | igb_configure_tx_ring(adapter, tx_ring); | |
9d5c8243 | 1486 | |
9d5c8243 | 1487 | /* Setup Rx descriptor ring and Rx buffers */ |
d7ee5b3a | 1488 | rx_ring->count = IGB_DEFAULT_RXD; |
59d71989 | 1489 | rx_ring->dev = &adapter->pdev->dev; |
d7ee5b3a | 1490 | rx_ring->netdev = adapter->netdev; |
d7ee5b3a AD |
1491 | rx_ring->reg_idx = adapter->vfs_allocated_count; |
1492 | ||
1493 | if (igb_setup_rx_resources(rx_ring)) { | |
1494 | ret_val = 3; | |
9d5c8243 AK |
1495 | goto err_nomem; |
1496 | } | |
9d5c8243 | 1497 | |
d7ee5b3a AD |
1498 | /* set the default queue to queue 0 of PF */ |
1499 | wr32(E1000_MRQC, adapter->vfs_allocated_count << 3); | |
9d5c8243 | 1500 | |
d7ee5b3a AD |
1501 | /* enable receive ring */ |
1502 | igb_setup_rctl(adapter); | |
1503 | igb_configure_rx_ring(adapter, rx_ring); | |
9d5c8243 | 1504 | |
cd392f5c | 1505 | igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring)); |
9d5c8243 AK |
1506 | |
1507 | return 0; | |
1508 | ||
1509 | err_nomem: | |
1510 | igb_free_desc_rings(adapter); | |
1511 | return ret_val; | |
1512 | } | |
1513 | ||
1514 | static void igb_phy_disable_receiver(struct igb_adapter *adapter) | |
1515 | { | |
1516 | struct e1000_hw *hw = &adapter->hw; | |
1517 | ||
1518 | /* Write out to PHY registers 29 and 30 to disable the Receiver. */ | |
f5f4cf08 AD |
1519 | igb_write_phy_reg(hw, 29, 0x001F); |
1520 | igb_write_phy_reg(hw, 30, 0x8FFC); | |
1521 | igb_write_phy_reg(hw, 29, 0x001A); | |
1522 | igb_write_phy_reg(hw, 30, 0x8FF0); | |
9d5c8243 AK |
1523 | } |
1524 | ||
1525 | static int igb_integrated_phy_loopback(struct igb_adapter *adapter) | |
1526 | { | |
1527 | struct e1000_hw *hw = &adapter->hw; | |
1528 | u32 ctrl_reg = 0; | |
9d5c8243 AK |
1529 | |
1530 | hw->mac.autoneg = false; | |
1531 | ||
8aa23f0d CW |
1532 | if (hw->phy.type == e1000_phy_m88) { |
1533 | if (hw->phy.id != I210_I_PHY_ID) { | |
1534 | /* Auto-MDI/MDIX Off */ | |
1535 | igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); | |
1536 | /* reset to update Auto-MDI/MDIX */ | |
1537 | igb_write_phy_reg(hw, PHY_CONTROL, 0x9140); | |
1538 | /* autoneg off */ | |
1539 | igb_write_phy_reg(hw, PHY_CONTROL, 0x8140); | |
1540 | } else { | |
1541 | /* force 1000, set loopback */ | |
1542 | igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0); | |
1543 | igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); | |
1544 | } | |
9d5c8243 AK |
1545 | } |
1546 | ||
119b0e03 SA |
1547 | /* add small delay to avoid loopback test failure */ |
1548 | msleep(50); | |
1549 | ||
9d5c8243 | 1550 | /* force 1000, set loopback */ |
f5f4cf08 | 1551 | igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); |
9d5c8243 AK |
1552 | |
1553 | /* Now set up the MAC to the same speed/duplex as the PHY. */ | |
1554 | ctrl_reg = rd32(E1000_CTRL); | |
1555 | ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ | |
1556 | ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ | |
1557 | E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ | |
1558 | E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ | |
cdfa9f64 AD |
1559 | E1000_CTRL_FD | /* Force Duplex to FULL */ |
1560 | E1000_CTRL_SLU); /* Set link up enable bit */ | |
9d5c8243 | 1561 | |
8aa23f0d | 1562 | if (hw->phy.type == e1000_phy_m88) |
9d5c8243 | 1563 | ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ |
9d5c8243 AK |
1564 | |
1565 | wr32(E1000_CTRL, ctrl_reg); | |
1566 | ||
1567 | /* Disable the receiver on the PHY so when a cable is plugged in, the | |
1568 | * PHY does not begin to autoneg when a cable is reconnected to the NIC. | |
1569 | */ | |
8aa23f0d | 1570 | if (hw->phy.type == e1000_phy_m88) |
9d5c8243 AK |
1571 | igb_phy_disable_receiver(adapter); |
1572 | ||
8aa23f0d | 1573 | mdelay(500); |
9d5c8243 AK |
1574 | return 0; |
1575 | } | |
1576 | ||
1577 | static int igb_set_phy_loopback(struct igb_adapter *adapter) | |
1578 | { | |
1579 | return igb_integrated_phy_loopback(adapter); | |
1580 | } | |
1581 | ||
1582 | static int igb_setup_loopback_test(struct igb_adapter *adapter) | |
1583 | { | |
1584 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 | 1585 | u32 reg; |
9d5c8243 | 1586 | |
317f66bd AD |
1587 | reg = rd32(E1000_CTRL_EXT); |
1588 | ||
1589 | /* use CTRL_EXT to identify link type as SGMII can appear as copper */ | |
1590 | if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) { | |
a14bc2bb RH |
1591 | if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || |
1592 | (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || | |
1593 | (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || | |
1594 | (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) { | |
1595 | ||
1596 | /* Enable DH89xxCC MPHY for near end loopback */ | |
1597 | reg = rd32(E1000_MPHY_ADDR_CTL); | |
1598 | reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | | |
1599 | E1000_MPHY_PCS_CLK_REG_OFFSET; | |
1600 | wr32(E1000_MPHY_ADDR_CTL, reg); | |
1601 | ||
1602 | reg = rd32(E1000_MPHY_DATA); | |
1603 | reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN; | |
1604 | wr32(E1000_MPHY_DATA, reg); | |
1605 | } | |
1606 | ||
2d064c06 AD |
1607 | reg = rd32(E1000_RCTL); |
1608 | reg |= E1000_RCTL_LBM_TCVR; | |
1609 | wr32(E1000_RCTL, reg); | |
1610 | ||
1611 | wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK); | |
1612 | ||
1613 | reg = rd32(E1000_CTRL); | |
1614 | reg &= ~(E1000_CTRL_RFCE | | |
1615 | E1000_CTRL_TFCE | | |
1616 | E1000_CTRL_LRST); | |
1617 | reg |= E1000_CTRL_SLU | | |
2753f4ce | 1618 | E1000_CTRL_FD; |
2d064c06 AD |
1619 | wr32(E1000_CTRL, reg); |
1620 | ||
1621 | /* Unset switch control to serdes energy detect */ | |
1622 | reg = rd32(E1000_CONNSW); | |
1623 | reg &= ~E1000_CONNSW_ENRGSRC; | |
1624 | wr32(E1000_CONNSW, reg); | |
1625 | ||
1626 | /* Set PCS register for forced speed */ | |
1627 | reg = rd32(E1000_PCS_LCTL); | |
1628 | reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/ | |
1629 | reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ | |
1630 | E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ | |
1631 | E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ | |
1632 | E1000_PCS_LCTL_FSD | /* Force Speed */ | |
1633 | E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ | |
1634 | wr32(E1000_PCS_LCTL, reg); | |
1635 | ||
9d5c8243 | 1636 | return 0; |
9d5c8243 AK |
1637 | } |
1638 | ||
317f66bd | 1639 | return igb_set_phy_loopback(adapter); |
9d5c8243 AK |
1640 | } |
1641 | ||
1642 | static void igb_loopback_cleanup(struct igb_adapter *adapter) | |
1643 | { | |
1644 | struct e1000_hw *hw = &adapter->hw; | |
1645 | u32 rctl; | |
1646 | u16 phy_reg; | |
1647 | ||
a14bc2bb RH |
1648 | if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || |
1649 | (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || | |
1650 | (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || | |
1651 | (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) { | |
1652 | u32 reg; | |
1653 | ||
1654 | /* Disable near end loopback on DH89xxCC */ | |
1655 | reg = rd32(E1000_MPHY_ADDR_CTL); | |
1656 | reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | | |
1657 | E1000_MPHY_PCS_CLK_REG_OFFSET; | |
1658 | wr32(E1000_MPHY_ADDR_CTL, reg); | |
1659 | ||
1660 | reg = rd32(E1000_MPHY_DATA); | |
1661 | reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN; | |
1662 | wr32(E1000_MPHY_DATA, reg); | |
1663 | } | |
1664 | ||
9d5c8243 AK |
1665 | rctl = rd32(E1000_RCTL); |
1666 | rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); | |
1667 | wr32(E1000_RCTL, rctl); | |
1668 | ||
1669 | hw->mac.autoneg = true; | |
f5f4cf08 | 1670 | igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg); |
9d5c8243 AK |
1671 | if (phy_reg & MII_CR_LOOPBACK) { |
1672 | phy_reg &= ~MII_CR_LOOPBACK; | |
f5f4cf08 | 1673 | igb_write_phy_reg(hw, PHY_CONTROL, phy_reg); |
9d5c8243 AK |
1674 | igb_phy_sw_reset(hw); |
1675 | } | |
1676 | } | |
1677 | ||
1678 | static void igb_create_lbtest_frame(struct sk_buff *skb, | |
1679 | unsigned int frame_size) | |
1680 | { | |
1681 | memset(skb->data, 0xFF, frame_size); | |
317f66bd AD |
1682 | frame_size /= 2; |
1683 | memset(&skb->data[frame_size], 0xAA, frame_size - 1); | |
1684 | memset(&skb->data[frame_size + 10], 0xBE, 1); | |
1685 | memset(&skb->data[frame_size + 12], 0xAF, 1); | |
9d5c8243 AK |
1686 | } |
1687 | ||
1688 | static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size) | |
1689 | { | |
317f66bd AD |
1690 | frame_size /= 2; |
1691 | if (*(skb->data + 3) == 0xFF) { | |
1692 | if ((*(skb->data + frame_size + 10) == 0xBE) && | |
1693 | (*(skb->data + frame_size + 12) == 0xAF)) { | |
9d5c8243 | 1694 | return 0; |
317f66bd AD |
1695 | } |
1696 | } | |
9d5c8243 AK |
1697 | return 13; |
1698 | } | |
1699 | ||
ad93d17e AD |
1700 | static int igb_clean_test_rings(struct igb_ring *rx_ring, |
1701 | struct igb_ring *tx_ring, | |
1702 | unsigned int size) | |
1703 | { | |
1704 | union e1000_adv_rx_desc *rx_desc; | |
06034649 AD |
1705 | struct igb_rx_buffer *rx_buffer_info; |
1706 | struct igb_tx_buffer *tx_buffer_info; | |
51a76c30 | 1707 | struct netdev_queue *txq; |
6ad4edfc | 1708 | u16 rx_ntc, tx_ntc, count = 0; |
51a76c30 | 1709 | unsigned int total_bytes = 0, total_packets = 0; |
ad93d17e AD |
1710 | |
1711 | /* initialize next to clean and descriptor values */ | |
1712 | rx_ntc = rx_ring->next_to_clean; | |
1713 | tx_ntc = tx_ring->next_to_clean; | |
60136906 | 1714 | rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); |
ad93d17e | 1715 | |
3ceb90fd | 1716 | while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) { |
ad93d17e | 1717 | /* check rx buffer */ |
06034649 | 1718 | rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc]; |
ad93d17e AD |
1719 | |
1720 | /* unmap rx buffer, will be remapped by alloc_rx_buffers */ | |
59d71989 | 1721 | dma_unmap_single(rx_ring->dev, |
06034649 | 1722 | rx_buffer_info->dma, |
44390ca6 | 1723 | IGB_RX_HDR_LEN, |
59d71989 | 1724 | DMA_FROM_DEVICE); |
06034649 | 1725 | rx_buffer_info->dma = 0; |
ad93d17e AD |
1726 | |
1727 | /* verify contents of skb */ | |
06034649 | 1728 | if (!igb_check_lbtest_frame(rx_buffer_info->skb, size)) |
ad93d17e AD |
1729 | count++; |
1730 | ||
1731 | /* unmap buffer on tx side */ | |
06034649 | 1732 | tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc]; |
51a76c30 JK |
1733 | total_bytes += tx_buffer_info->bytecount; |
1734 | total_packets += tx_buffer_info->gso_segs; | |
06034649 | 1735 | igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
ad93d17e AD |
1736 | |
1737 | /* increment rx/tx next to clean counters */ | |
1738 | rx_ntc++; | |
1739 | if (rx_ntc == rx_ring->count) | |
1740 | rx_ntc = 0; | |
1741 | tx_ntc++; | |
1742 | if (tx_ntc == tx_ring->count) | |
1743 | tx_ntc = 0; | |
1744 | ||
1745 | /* fetch next descriptor */ | |
60136906 | 1746 | rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); |
ad93d17e AD |
1747 | } |
1748 | ||
51a76c30 JK |
1749 | txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); |
1750 | netdev_tx_completed_queue(txq, total_packets, total_bytes); | |
1751 | ||
ad93d17e | 1752 | /* re-map buffers to ring, store next to clean values */ |
cd392f5c | 1753 | igb_alloc_rx_buffers(rx_ring, count); |
ad93d17e AD |
1754 | rx_ring->next_to_clean = rx_ntc; |
1755 | tx_ring->next_to_clean = tx_ntc; | |
1756 | ||
1757 | return count; | |
1758 | } | |
1759 | ||
9d5c8243 AK |
1760 | static int igb_run_loopback_test(struct igb_adapter *adapter) |
1761 | { | |
9d5c8243 AK |
1762 | struct igb_ring *tx_ring = &adapter->test_tx_ring; |
1763 | struct igb_ring *rx_ring = &adapter->test_rx_ring; | |
6ad4edfc AD |
1764 | u16 i, j, lc, good_cnt; |
1765 | int ret_val = 0; | |
44390ca6 | 1766 | unsigned int size = IGB_RX_HDR_LEN; |
ad93d17e AD |
1767 | netdev_tx_t tx_ret_val; |
1768 | struct sk_buff *skb; | |
1769 | ||
1770 | /* allocate test skb */ | |
1771 | skb = alloc_skb(size, GFP_KERNEL); | |
1772 | if (!skb) | |
1773 | return 11; | |
9d5c8243 | 1774 | |
ad93d17e AD |
1775 | /* place data into test skb */ |
1776 | igb_create_lbtest_frame(skb, size); | |
1777 | skb_put(skb, size); | |
9d5c8243 | 1778 | |
317f66bd AD |
1779 | /* |
1780 | * Calculate the loop count based on the largest descriptor ring | |
9d5c8243 AK |
1781 | * The idea is to wrap the largest ring a number of times using 64 |
1782 | * send/receive pairs during each loop | |
1783 | */ | |
1784 | ||
1785 | if (rx_ring->count <= tx_ring->count) | |
1786 | lc = ((tx_ring->count / 64) * 2) + 1; | |
1787 | else | |
1788 | lc = ((rx_ring->count / 64) * 2) + 1; | |
1789 | ||
9d5c8243 | 1790 | for (j = 0; j <= lc; j++) { /* loop count loop */ |
ad93d17e | 1791 | /* reset count of good packets */ |
9d5c8243 | 1792 | good_cnt = 0; |
ad93d17e AD |
1793 | |
1794 | /* place 64 packets on the transmit queue*/ | |
1795 | for (i = 0; i < 64; i++) { | |
1796 | skb_get(skb); | |
cd392f5c | 1797 | tx_ret_val = igb_xmit_frame_ring(skb, tx_ring); |
ad93d17e | 1798 | if (tx_ret_val == NETDEV_TX_OK) |
9d5c8243 | 1799 | good_cnt++; |
ad93d17e AD |
1800 | } |
1801 | ||
9d5c8243 | 1802 | if (good_cnt != 64) { |
ad93d17e | 1803 | ret_val = 12; |
9d5c8243 AK |
1804 | break; |
1805 | } | |
ad93d17e AD |
1806 | |
1807 | /* allow 200 milliseconds for packets to go from tx to rx */ | |
1808 | msleep(200); | |
1809 | ||
1810 | good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size); | |
1811 | if (good_cnt != 64) { | |
1812 | ret_val = 13; | |
9d5c8243 AK |
1813 | break; |
1814 | } | |
1815 | } /* end loop count loop */ | |
ad93d17e AD |
1816 | |
1817 | /* free the original skb */ | |
1818 | kfree_skb(skb); | |
1819 | ||
9d5c8243 AK |
1820 | return ret_val; |
1821 | } | |
1822 | ||
1823 | static int igb_loopback_test(struct igb_adapter *adapter, u64 *data) | |
1824 | { | |
1825 | /* PHY loopback cannot be performed if SoL/IDER | |
1826 | * sessions are active */ | |
1827 | if (igb_check_reset_block(&adapter->hw)) { | |
1828 | dev_err(&adapter->pdev->dev, | |
d836200a | 1829 | "Cannot do PHY loopback test when SoL/IDER is active.\n"); |
f96a8a0b CW |
1830 | *data = 0; |
1831 | goto out; | |
1832 | } | |
9d5c8243 AK |
1833 | *data = igb_setup_desc_rings(adapter); |
1834 | if (*data) | |
1835 | goto out; | |
1836 | *data = igb_setup_loopback_test(adapter); | |
1837 | if (*data) | |
1838 | goto err_loopback; | |
1839 | *data = igb_run_loopback_test(adapter); | |
1840 | igb_loopback_cleanup(adapter); | |
1841 | ||
1842 | err_loopback: | |
1843 | igb_free_desc_rings(adapter); | |
1844 | out: | |
1845 | return *data; | |
1846 | } | |
1847 | ||
1848 | static int igb_link_test(struct igb_adapter *adapter, u64 *data) | |
1849 | { | |
1850 | struct e1000_hw *hw = &adapter->hw; | |
1851 | *data = 0; | |
1852 | if (hw->phy.media_type == e1000_media_type_internal_serdes) { | |
1853 | int i = 0; | |
1854 | hw->mac.serdes_has_link = false; | |
1855 | ||
1856 | /* On some blade server designs, link establishment | |
1857 | * could take as long as 2-3 minutes */ | |
1858 | do { | |
1859 | hw->mac.ops.check_for_link(&adapter->hw); | |
1860 | if (hw->mac.serdes_has_link) | |
1861 | return *data; | |
1862 | msleep(20); | |
1863 | } while (i++ < 3750); | |
1864 | ||
1865 | *data = 1; | |
1866 | } else { | |
1867 | hw->mac.ops.check_for_link(&adapter->hw); | |
1868 | if (hw->mac.autoneg) | |
1869 | msleep(4000); | |
1870 | ||
317f66bd | 1871 | if (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) |
9d5c8243 AK |
1872 | *data = 1; |
1873 | } | |
1874 | return *data; | |
1875 | } | |
1876 | ||
1877 | static void igb_diag_test(struct net_device *netdev, | |
1878 | struct ethtool_test *eth_test, u64 *data) | |
1879 | { | |
1880 | struct igb_adapter *adapter = netdev_priv(netdev); | |
1881 | u16 autoneg_advertised; | |
1882 | u8 forced_speed_duplex, autoneg; | |
1883 | bool if_running = netif_running(netdev); | |
1884 | ||
1885 | set_bit(__IGB_TESTING, &adapter->state); | |
1886 | if (eth_test->flags == ETH_TEST_FL_OFFLINE) { | |
1887 | /* Offline tests */ | |
1888 | ||
1889 | /* save speed, duplex, autoneg settings */ | |
1890 | autoneg_advertised = adapter->hw.phy.autoneg_advertised; | |
1891 | forced_speed_duplex = adapter->hw.mac.forced_speed_duplex; | |
1892 | autoneg = adapter->hw.mac.autoneg; | |
1893 | ||
1894 | dev_info(&adapter->pdev->dev, "offline testing starting\n"); | |
1895 | ||
88a268c1 NN |
1896 | /* power up link for link test */ |
1897 | igb_power_up_link(adapter); | |
1898 | ||
9d5c8243 AK |
1899 | /* Link test performed before hardware reset so autoneg doesn't |
1900 | * interfere with test result */ | |
1901 | if (igb_link_test(adapter, &data[4])) | |
1902 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1903 | ||
1904 | if (if_running) | |
1905 | /* indicate we're in test mode */ | |
1906 | dev_close(netdev); | |
1907 | else | |
1908 | igb_reset(adapter); | |
1909 | ||
1910 | if (igb_reg_test(adapter, &data[0])) | |
1911 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1912 | ||
1913 | igb_reset(adapter); | |
1914 | if (igb_eeprom_test(adapter, &data[1])) | |
1915 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1916 | ||
1917 | igb_reset(adapter); | |
1918 | if (igb_intr_test(adapter, &data[2])) | |
1919 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1920 | ||
1921 | igb_reset(adapter); | |
88a268c1 NN |
1922 | /* power up link for loopback test */ |
1923 | igb_power_up_link(adapter); | |
9d5c8243 AK |
1924 | if (igb_loopback_test(adapter, &data[3])) |
1925 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1926 | ||
1927 | /* restore speed, duplex, autoneg settings */ | |
1928 | adapter->hw.phy.autoneg_advertised = autoneg_advertised; | |
1929 | adapter->hw.mac.forced_speed_duplex = forced_speed_duplex; | |
1930 | adapter->hw.mac.autoneg = autoneg; | |
1931 | ||
1932 | /* force this routine to wait until autoneg complete/timeout */ | |
1933 | adapter->hw.phy.autoneg_wait_to_complete = true; | |
1934 | igb_reset(adapter); | |
1935 | adapter->hw.phy.autoneg_wait_to_complete = false; | |
1936 | ||
1937 | clear_bit(__IGB_TESTING, &adapter->state); | |
1938 | if (if_running) | |
1939 | dev_open(netdev); | |
1940 | } else { | |
1941 | dev_info(&adapter->pdev->dev, "online testing starting\n"); | |
88a268c1 NN |
1942 | |
1943 | /* PHY is powered down when interface is down */ | |
8d420a1b AD |
1944 | if (if_running && igb_link_test(adapter, &data[4])) |
1945 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1946 | else | |
88a268c1 | 1947 | data[4] = 0; |
9d5c8243 AK |
1948 | |
1949 | /* Online tests aren't run; pass by default */ | |
1950 | data[0] = 0; | |
1951 | data[1] = 0; | |
1952 | data[2] = 0; | |
1953 | data[3] = 0; | |
1954 | ||
1955 | clear_bit(__IGB_TESTING, &adapter->state); | |
1956 | } | |
1957 | msleep_interruptible(4 * 1000); | |
1958 | } | |
1959 | ||
1960 | static int igb_wol_exclusion(struct igb_adapter *adapter, | |
1961 | struct ethtool_wolinfo *wol) | |
1962 | { | |
1963 | struct e1000_hw *hw = &adapter->hw; | |
1964 | int retval = 1; /* fail by default */ | |
1965 | ||
1966 | switch (hw->device_id) { | |
1967 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
1968 | /* WoL not supported */ | |
1969 | wol->supported = 0; | |
1970 | break; | |
1971 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
2d064c06 AD |
1972 | case E1000_DEV_ID_82576_FIBER: |
1973 | case E1000_DEV_ID_82576_SERDES: | |
9d5c8243 AK |
1974 | /* Wake events not supported on port B */ |
1975 | if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) { | |
1976 | wol->supported = 0; | |
1977 | break; | |
1978 | } | |
7dfc16fa AD |
1979 | /* return success for non excluded adapter ports */ |
1980 | retval = 0; | |
1981 | break; | |
c8ea5ea9 | 1982 | case E1000_DEV_ID_82576_QUAD_COPPER: |
d5aa2252 | 1983 | case E1000_DEV_ID_82576_QUAD_COPPER_ET2: |
c8ea5ea9 AD |
1984 | /* quad port adapters only support WoL on port A */ |
1985 | if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) { | |
1986 | wol->supported = 0; | |
1987 | break; | |
1988 | } | |
1989 | /* return success for non excluded adapter ports */ | |
1990 | retval = 0; | |
1991 | break; | |
9d5c8243 AK |
1992 | default: |
1993 | /* dual port cards only support WoL on port A from now on | |
1994 | * unless it was enabled in the eeprom for port B | |
1995 | * so exclude FUNC_1 ports from having WoL enabled */ | |
58b8b042 | 1996 | if ((rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) && |
9d5c8243 AK |
1997 | !adapter->eeprom_wol) { |
1998 | wol->supported = 0; | |
1999 | break; | |
2000 | } | |
2001 | ||
2002 | retval = 0; | |
2003 | } | |
2004 | ||
2005 | return retval; | |
2006 | } | |
2007 | ||
2008 | static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) | |
2009 | { | |
2010 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2011 | ||
2012 | wol->supported = WAKE_UCAST | WAKE_MCAST | | |
22939f06 NN |
2013 | WAKE_BCAST | WAKE_MAGIC | |
2014 | WAKE_PHY; | |
9d5c8243 AK |
2015 | wol->wolopts = 0; |
2016 | ||
2017 | /* this function will set ->supported = 0 and return 1 if wol is not | |
2018 | * supported by this hardware */ | |
e1b86d84 RW |
2019 | if (igb_wol_exclusion(adapter, wol) || |
2020 | !device_can_wakeup(&adapter->pdev->dev)) | |
9d5c8243 AK |
2021 | return; |
2022 | ||
2023 | /* apply any specific unsupported masks here */ | |
2024 | switch (adapter->hw.device_id) { | |
2025 | default: | |
2026 | break; | |
2027 | } | |
2028 | ||
2029 | if (adapter->wol & E1000_WUFC_EX) | |
2030 | wol->wolopts |= WAKE_UCAST; | |
2031 | if (adapter->wol & E1000_WUFC_MC) | |
2032 | wol->wolopts |= WAKE_MCAST; | |
2033 | if (adapter->wol & E1000_WUFC_BC) | |
2034 | wol->wolopts |= WAKE_BCAST; | |
2035 | if (adapter->wol & E1000_WUFC_MAG) | |
2036 | wol->wolopts |= WAKE_MAGIC; | |
22939f06 NN |
2037 | if (adapter->wol & E1000_WUFC_LNKC) |
2038 | wol->wolopts |= WAKE_PHY; | |
9d5c8243 AK |
2039 | } |
2040 | ||
2041 | static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) | |
2042 | { | |
2043 | struct igb_adapter *adapter = netdev_priv(netdev); | |
9d5c8243 | 2044 | |
22939f06 | 2045 | if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) |
9d5c8243 AK |
2046 | return -EOPNOTSUPP; |
2047 | ||
e1b86d84 RW |
2048 | if (igb_wol_exclusion(adapter, wol) || |
2049 | !device_can_wakeup(&adapter->pdev->dev)) | |
9d5c8243 AK |
2050 | return wol->wolopts ? -EOPNOTSUPP : 0; |
2051 | ||
9d5c8243 AK |
2052 | /* these settings will always override what we currently have */ |
2053 | adapter->wol = 0; | |
2054 | ||
2055 | if (wol->wolopts & WAKE_UCAST) | |
2056 | adapter->wol |= E1000_WUFC_EX; | |
2057 | if (wol->wolopts & WAKE_MCAST) | |
2058 | adapter->wol |= E1000_WUFC_MC; | |
2059 | if (wol->wolopts & WAKE_BCAST) | |
2060 | adapter->wol |= E1000_WUFC_BC; | |
2061 | if (wol->wolopts & WAKE_MAGIC) | |
2062 | adapter->wol |= E1000_WUFC_MAG; | |
22939f06 NN |
2063 | if (wol->wolopts & WAKE_PHY) |
2064 | adapter->wol |= E1000_WUFC_LNKC; | |
e1b86d84 RW |
2065 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
2066 | ||
9d5c8243 AK |
2067 | return 0; |
2068 | } | |
2069 | ||
9d5c8243 AK |
2070 | /* bit defines for adapter->led_status */ |
2071 | #define IGB_LED_ON 0 | |
2072 | ||
936db355 JK |
2073 | static int igb_set_phys_id(struct net_device *netdev, |
2074 | enum ethtool_phys_id_state state) | |
9d5c8243 AK |
2075 | { |
2076 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2077 | struct e1000_hw *hw = &adapter->hw; | |
2078 | ||
936db355 JK |
2079 | switch (state) { |
2080 | case ETHTOOL_ID_ACTIVE: | |
2081 | igb_blink_led(hw); | |
2082 | return 2; | |
2083 | case ETHTOOL_ID_ON: | |
2084 | igb_blink_led(hw); | |
2085 | break; | |
2086 | case ETHTOOL_ID_OFF: | |
2087 | igb_led_off(hw); | |
2088 | break; | |
2089 | case ETHTOOL_ID_INACTIVE: | |
2090 | igb_led_off(hw); | |
2091 | clear_bit(IGB_LED_ON, &adapter->led_status); | |
2092 | igb_cleanup_led(hw); | |
2093 | break; | |
2094 | } | |
9d5c8243 AK |
2095 | |
2096 | return 0; | |
2097 | } | |
2098 | ||
2099 | static int igb_set_coalesce(struct net_device *netdev, | |
2100 | struct ethtool_coalesce *ec) | |
2101 | { | |
2102 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6eb5a7f1 | 2103 | int i; |
9d5c8243 AK |
2104 | |
2105 | if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) || | |
2106 | ((ec->rx_coalesce_usecs > 3) && | |
2107 | (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) || | |
2108 | (ec->rx_coalesce_usecs == 2)) | |
2109 | return -EINVAL; | |
2110 | ||
4fc82adf AD |
2111 | if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) || |
2112 | ((ec->tx_coalesce_usecs > 3) && | |
2113 | (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) || | |
2114 | (ec->tx_coalesce_usecs == 2)) | |
2115 | return -EINVAL; | |
2116 | ||
2117 | if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs) | |
2118 | return -EINVAL; | |
2119 | ||
831ec0b4 CW |
2120 | /* If ITR is disabled, disable DMAC */ |
2121 | if (ec->rx_coalesce_usecs == 0) { | |
2122 | if (adapter->flags & IGB_FLAG_DMAC) | |
2123 | adapter->flags &= ~IGB_FLAG_DMAC; | |
2124 | } | |
2125 | ||
9d5c8243 | 2126 | /* convert to rate of irq's per second */ |
4fc82adf AD |
2127 | if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) |
2128 | adapter->rx_itr_setting = ec->rx_coalesce_usecs; | |
2129 | else | |
2130 | adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; | |
2131 | ||
2132 | /* convert to rate of irq's per second */ | |
2133 | if (adapter->flags & IGB_FLAG_QUEUE_PAIRS) | |
2134 | adapter->tx_itr_setting = adapter->rx_itr_setting; | |
2135 | else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3) | |
2136 | adapter->tx_itr_setting = ec->tx_coalesce_usecs; | |
2137 | else | |
2138 | adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; | |
9d5c8243 | 2139 | |
047e0030 AD |
2140 | for (i = 0; i < adapter->num_q_vectors; i++) { |
2141 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
0ba82994 AD |
2142 | q_vector->tx.work_limit = adapter->tx_work_limit; |
2143 | if (q_vector->rx.ring) | |
4fc82adf AD |
2144 | q_vector->itr_val = adapter->rx_itr_setting; |
2145 | else | |
2146 | q_vector->itr_val = adapter->tx_itr_setting; | |
2147 | if (q_vector->itr_val && q_vector->itr_val <= 3) | |
2148 | q_vector->itr_val = IGB_START_ITR; | |
047e0030 AD |
2149 | q_vector->set_itr = 1; |
2150 | } | |
9d5c8243 AK |
2151 | |
2152 | return 0; | |
2153 | } | |
2154 | ||
2155 | static int igb_get_coalesce(struct net_device *netdev, | |
2156 | struct ethtool_coalesce *ec) | |
2157 | { | |
2158 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2159 | ||
4fc82adf AD |
2160 | if (adapter->rx_itr_setting <= 3) |
2161 | ec->rx_coalesce_usecs = adapter->rx_itr_setting; | |
9d5c8243 | 2162 | else |
4fc82adf AD |
2163 | ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; |
2164 | ||
2165 | if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) { | |
2166 | if (adapter->tx_itr_setting <= 3) | |
2167 | ec->tx_coalesce_usecs = adapter->tx_itr_setting; | |
2168 | else | |
2169 | ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; | |
2170 | } | |
9d5c8243 AK |
2171 | |
2172 | return 0; | |
2173 | } | |
2174 | ||
9d5c8243 AK |
2175 | static int igb_nway_reset(struct net_device *netdev) |
2176 | { | |
2177 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2178 | if (netif_running(netdev)) | |
2179 | igb_reinit_locked(adapter); | |
2180 | return 0; | |
2181 | } | |
2182 | ||
2183 | static int igb_get_sset_count(struct net_device *netdev, int sset) | |
2184 | { | |
2185 | switch (sset) { | |
2186 | case ETH_SS_STATS: | |
2187 | return IGB_STATS_LEN; | |
2188 | case ETH_SS_TEST: | |
2189 | return IGB_TEST_LEN; | |
2190 | default: | |
2191 | return -ENOTSUPP; | |
2192 | } | |
2193 | } | |
2194 | ||
2195 | static void igb_get_ethtool_stats(struct net_device *netdev, | |
2196 | struct ethtool_stats *stats, u64 *data) | |
2197 | { | |
2198 | struct igb_adapter *adapter = netdev_priv(netdev); | |
12dcd86b ED |
2199 | struct rtnl_link_stats64 *net_stats = &adapter->stats64; |
2200 | unsigned int start; | |
2201 | struct igb_ring *ring; | |
2202 | int i, j; | |
128e45eb | 2203 | char *p; |
9d5c8243 | 2204 | |
12dcd86b ED |
2205 | spin_lock(&adapter->stats64_lock); |
2206 | igb_update_stats(adapter, net_stats); | |
317f66bd | 2207 | |
9d5c8243 | 2208 | for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { |
128e45eb | 2209 | p = (char *)adapter + igb_gstrings_stats[i].stat_offset; |
9d5c8243 AK |
2210 | data[i] = (igb_gstrings_stats[i].sizeof_stat == |
2211 | sizeof(u64)) ? *(u64 *)p : *(u32 *)p; | |
2212 | } | |
128e45eb AD |
2213 | for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) { |
2214 | p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset; | |
2215 | data[i] = (igb_gstrings_net_stats[j].sizeof_stat == | |
2216 | sizeof(u64)) ? *(u64 *)p : *(u32 *)p; | |
2217 | } | |
e21ed353 | 2218 | for (j = 0; j < adapter->num_tx_queues; j++) { |
12dcd86b ED |
2219 | u64 restart2; |
2220 | ||
2221 | ring = adapter->tx_ring[j]; | |
2222 | do { | |
2223 | start = u64_stats_fetch_begin_bh(&ring->tx_syncp); | |
2224 | data[i] = ring->tx_stats.packets; | |
2225 | data[i+1] = ring->tx_stats.bytes; | |
2226 | data[i+2] = ring->tx_stats.restart_queue; | |
2227 | } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start)); | |
2228 | do { | |
2229 | start = u64_stats_fetch_begin_bh(&ring->tx_syncp2); | |
2230 | restart2 = ring->tx_stats.restart_queue2; | |
2231 | } while (u64_stats_fetch_retry_bh(&ring->tx_syncp2, start)); | |
2232 | data[i+2] += restart2; | |
2233 | ||
2234 | i += IGB_TX_QUEUE_STATS_LEN; | |
e21ed353 | 2235 | } |
9d5c8243 | 2236 | for (j = 0; j < adapter->num_rx_queues; j++) { |
12dcd86b ED |
2237 | ring = adapter->rx_ring[j]; |
2238 | do { | |
2239 | start = u64_stats_fetch_begin_bh(&ring->rx_syncp); | |
2240 | data[i] = ring->rx_stats.packets; | |
2241 | data[i+1] = ring->rx_stats.bytes; | |
2242 | data[i+2] = ring->rx_stats.drops; | |
2243 | data[i+3] = ring->rx_stats.csum_err; | |
2244 | data[i+4] = ring->rx_stats.alloc_failed; | |
2245 | } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start)); | |
2246 | i += IGB_RX_QUEUE_STATS_LEN; | |
9d5c8243 | 2247 | } |
12dcd86b | 2248 | spin_unlock(&adapter->stats64_lock); |
9d5c8243 AK |
2249 | } |
2250 | ||
2251 | static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data) | |
2252 | { | |
2253 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2254 | u8 *p = data; | |
2255 | int i; | |
2256 | ||
2257 | switch (stringset) { | |
2258 | case ETH_SS_TEST: | |
2259 | memcpy(data, *igb_gstrings_test, | |
2260 | IGB_TEST_LEN*ETH_GSTRING_LEN); | |
2261 | break; | |
2262 | case ETH_SS_STATS: | |
2263 | for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { | |
2264 | memcpy(p, igb_gstrings_stats[i].stat_string, | |
2265 | ETH_GSTRING_LEN); | |
2266 | p += ETH_GSTRING_LEN; | |
2267 | } | |
128e45eb AD |
2268 | for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) { |
2269 | memcpy(p, igb_gstrings_net_stats[i].stat_string, | |
2270 | ETH_GSTRING_LEN); | |
2271 | p += ETH_GSTRING_LEN; | |
2272 | } | |
9d5c8243 AK |
2273 | for (i = 0; i < adapter->num_tx_queues; i++) { |
2274 | sprintf(p, "tx_queue_%u_packets", i); | |
2275 | p += ETH_GSTRING_LEN; | |
2276 | sprintf(p, "tx_queue_%u_bytes", i); | |
2277 | p += ETH_GSTRING_LEN; | |
04a5fcaa AD |
2278 | sprintf(p, "tx_queue_%u_restart", i); |
2279 | p += ETH_GSTRING_LEN; | |
9d5c8243 AK |
2280 | } |
2281 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2282 | sprintf(p, "rx_queue_%u_packets", i); | |
2283 | p += ETH_GSTRING_LEN; | |
2284 | sprintf(p, "rx_queue_%u_bytes", i); | |
2285 | p += ETH_GSTRING_LEN; | |
8c0ab70a JDB |
2286 | sprintf(p, "rx_queue_%u_drops", i); |
2287 | p += ETH_GSTRING_LEN; | |
04a5fcaa AD |
2288 | sprintf(p, "rx_queue_%u_csum_err", i); |
2289 | p += ETH_GSTRING_LEN; | |
2290 | sprintf(p, "rx_queue_%u_alloc_failed", i); | |
2291 | p += ETH_GSTRING_LEN; | |
9d5c8243 AK |
2292 | } |
2293 | /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */ | |
2294 | break; | |
2295 | } | |
2296 | } | |
2297 | ||
749ab2cd YZ |
2298 | static int igb_ethtool_begin(struct net_device *netdev) |
2299 | { | |
2300 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2301 | pm_runtime_get_sync(&adapter->pdev->dev); | |
2302 | return 0; | |
2303 | } | |
2304 | ||
2305 | static void igb_ethtool_complete(struct net_device *netdev) | |
2306 | { | |
2307 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2308 | pm_runtime_put(&adapter->pdev->dev); | |
2309 | } | |
2310 | ||
cb41145e CW |
2311 | #ifdef CONFIG_IGB_PTP |
2312 | static int igb_ethtool_get_ts_info(struct net_device *dev, | |
2313 | struct ethtool_ts_info *info) | |
2314 | { | |
2315 | struct igb_adapter *adapter = netdev_priv(dev); | |
2316 | ||
2317 | info->so_timestamping = | |
2318 | SOF_TIMESTAMPING_TX_HARDWARE | | |
2319 | SOF_TIMESTAMPING_RX_HARDWARE | | |
2320 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
2321 | ||
2322 | if (adapter->ptp_clock) | |
2323 | info->phc_index = ptp_clock_index(adapter->ptp_clock); | |
2324 | else | |
2325 | info->phc_index = -1; | |
2326 | ||
2327 | info->tx_types = | |
2328 | (1 << HWTSTAMP_TX_OFF) | | |
2329 | (1 << HWTSTAMP_TX_ON); | |
2330 | ||
2331 | info->rx_filters = | |
2332 | (1 << HWTSTAMP_FILTER_NONE) | | |
2333 | (1 << HWTSTAMP_FILTER_ALL) | | |
2334 | (1 << HWTSTAMP_FILTER_SOME) | | |
2335 | (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | | |
2336 | (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | | |
2337 | (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); | |
2338 | ||
2339 | return 0; | |
2340 | } | |
2341 | ||
2342 | #endif | |
0fc0b732 | 2343 | static const struct ethtool_ops igb_ethtool_ops = { |
9d5c8243 AK |
2344 | .get_settings = igb_get_settings, |
2345 | .set_settings = igb_set_settings, | |
2346 | .get_drvinfo = igb_get_drvinfo, | |
2347 | .get_regs_len = igb_get_regs_len, | |
2348 | .get_regs = igb_get_regs, | |
2349 | .get_wol = igb_get_wol, | |
2350 | .set_wol = igb_set_wol, | |
2351 | .get_msglevel = igb_get_msglevel, | |
2352 | .set_msglevel = igb_set_msglevel, | |
2353 | .nway_reset = igb_nway_reset, | |
3145535a | 2354 | .get_link = igb_get_link, |
9d5c8243 AK |
2355 | .get_eeprom_len = igb_get_eeprom_len, |
2356 | .get_eeprom = igb_get_eeprom, | |
2357 | .set_eeprom = igb_set_eeprom, | |
2358 | .get_ringparam = igb_get_ringparam, | |
2359 | .set_ringparam = igb_set_ringparam, | |
2360 | .get_pauseparam = igb_get_pauseparam, | |
2361 | .set_pauseparam = igb_set_pauseparam, | |
9d5c8243 AK |
2362 | .self_test = igb_diag_test, |
2363 | .get_strings = igb_get_strings, | |
936db355 | 2364 | .set_phys_id = igb_set_phys_id, |
9d5c8243 AK |
2365 | .get_sset_count = igb_get_sset_count, |
2366 | .get_ethtool_stats = igb_get_ethtool_stats, | |
2367 | .get_coalesce = igb_get_coalesce, | |
2368 | .set_coalesce = igb_set_coalesce, | |
749ab2cd YZ |
2369 | .begin = igb_ethtool_begin, |
2370 | .complete = igb_ethtool_complete, | |
cb41145e CW |
2371 | #ifdef CONFIG_IGB_PTP |
2372 | .get_ts_info = igb_ethtool_get_ts_info, | |
2373 | #endif | |
9d5c8243 AK |
2374 | }; |
2375 | ||
2376 | void igb_set_ethtool_ops(struct net_device *netdev) | |
2377 | { | |
2378 | SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops); | |
2379 | } |