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b980ac18 | 1 | /* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580 |
d339b133 RC |
2 | * |
3 | * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
74cfb2e1 CW |
15 | * You should have received a copy of the GNU General Public License along with |
16 | * this program; if not, see <http://www.gnu.org/licenses/>. | |
d339b133 RC |
17 | */ |
18 | #include <linux/module.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/pci.h> | |
ba59814b | 21 | #include <linux/ptp_classify.h> |
d339b133 RC |
22 | |
23 | #include "igb.h" | |
24 | ||
25 | #define INCVALUE_MASK 0x7fffffff | |
26 | #define ISGN 0x80000000 | |
27 | ||
b980ac18 | 28 | /* The 82580 timesync updates the system timer every 8ns by 8ns, |
7ebae817 RC |
29 | * and this update value cannot be reprogrammed. |
30 | * | |
d339b133 RC |
31 | * Neither the 82576 nor the 82580 offer registers wide enough to hold |
32 | * nanoseconds time values for very long. For the 82580, SYSTIM always | |
dbedd44e | 33 | * counts nanoseconds, but the upper 24 bits are not available. The |
d339b133 RC |
34 | * frequency is adjusted by changing the 32 bit fractional nanoseconds |
35 | * register, TIMINCA. | |
36 | * | |
37 | * For the 82576, the SYSTIM register time unit is affect by the | |
38 | * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this | |
39 | * field are needed to provide the nominal 16 nanosecond period, | |
40 | * leaving 19 bits for fractional nanoseconds. | |
41 | * | |
7ebae817 RC |
42 | * We scale the NIC clock cycle by a large factor so that relatively |
43 | * small clock corrections can be added or subtracted at each clock | |
44 | * tick. The drawbacks of a large factor are a) that the clock | |
45 | * register overflows more quickly (not such a big deal) and b) that | |
46 | * the increment per tick has to fit into 24 bits. As a result we | |
47 | * need to use a shift of 19 so we can fit a value of 16 into the | |
48 | * TIMINCA register. | |
49 | * | |
d339b133 RC |
50 | * |
51 | * SYSTIMH SYSTIML | |
52 | * +--------------+ +---+---+------+ | |
53 | * 82576 | 32 | | 8 | 5 | 19 | | |
54 | * +--------------+ +---+---+------+ | |
55 | * \________ 45 bits _______/ fract | |
56 | * | |
57 | * +----------+---+ +--------------+ | |
58 | * 82580 | 24 | 8 | | 32 | | |
59 | * +----------+---+ +--------------+ | |
60 | * reserved \______ 40 bits _____/ | |
61 | * | |
62 | * | |
63 | * The 45 bit 82576 SYSTIM overflows every | |
64 | * 2^45 * 10^-9 / 3600 = 9.77 hours. | |
65 | * | |
66 | * The 40 bit 82580 SYSTIM overflows every | |
67 | * 2^40 * 10^-9 / 60 = 18.3 minutes. | |
68 | */ | |
69 | ||
a79f4f88 | 70 | #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9) |
428f1f71 | 71 | #define IGB_PTP_TX_TIMEOUT (HZ * 15) |
a51d8c21 JK |
72 | #define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT) |
73 | #define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0) | |
74 | #define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT) | |
a79f4f88 | 75 | #define IGB_NBITS_82580 40 |
d339b133 | 76 | |
167f3f71 JK |
77 | static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); |
78 | ||
b980ac18 | 79 | /* SYSTIM read access for the 82576 */ |
a79f4f88 | 80 | static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc) |
d339b133 | 81 | { |
d339b133 RC |
82 | struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); |
83 | struct e1000_hw *hw = &igb->hw; | |
a79f4f88 MV |
84 | u64 val; |
85 | u32 lo, hi; | |
d339b133 RC |
86 | |
87 | lo = rd32(E1000_SYSTIML); | |
88 | hi = rd32(E1000_SYSTIMH); | |
89 | ||
90 | val = ((u64) hi) << 32; | |
91 | val |= lo; | |
92 | ||
93 | return val; | |
94 | } | |
95 | ||
b980ac18 | 96 | /* SYSTIM read access for the 82580 */ |
a79f4f88 | 97 | static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc) |
d339b133 | 98 | { |
d339b133 RC |
99 | struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); |
100 | struct e1000_hw *hw = &igb->hw; | |
e5c3370f | 101 | u32 lo, hi; |
a79f4f88 | 102 | u64 val; |
d339b133 | 103 | |
b980ac18 | 104 | /* The timestamp latches on lowest register read. For the 82580 |
7ebae817 RC |
105 | * the lowest register is SYSTIMR instead of SYSTIML. However we only |
106 | * need to provide nanosecond resolution, so we just ignore it. | |
107 | */ | |
e5c3370f | 108 | rd32(E1000_SYSTIMR); |
d339b133 RC |
109 | lo = rd32(E1000_SYSTIML); |
110 | hi = rd32(E1000_SYSTIMH); | |
111 | ||
112 | val = ((u64) hi) << 32; | |
113 | val |= lo; | |
114 | ||
115 | return val; | |
116 | } | |
117 | ||
b980ac18 | 118 | /* SYSTIM read access for I210/I211 */ |
d4c496fe RC |
119 | static void igb_ptp_read_i210(struct igb_adapter *adapter, |
120 | struct timespec64 *ts) | |
e57b8bdb MV |
121 | { |
122 | struct e1000_hw *hw = &adapter->hw; | |
e5c3370f | 123 | u32 sec, nsec; |
e57b8bdb | 124 | |
b980ac18 | 125 | /* The timestamp latches on lowest register read. For I210/I211, the |
e57b8bdb MV |
126 | * lowest register is SYSTIMR. Since we only need to provide nanosecond |
127 | * resolution, we can ignore it. | |
128 | */ | |
e5c3370f | 129 | rd32(E1000_SYSTIMR); |
e57b8bdb MV |
130 | nsec = rd32(E1000_SYSTIML); |
131 | sec = rd32(E1000_SYSTIMH); | |
132 | ||
133 | ts->tv_sec = sec; | |
134 | ts->tv_nsec = nsec; | |
135 | } | |
136 | ||
137 | static void igb_ptp_write_i210(struct igb_adapter *adapter, | |
d4c496fe | 138 | const struct timespec64 *ts) |
e57b8bdb MV |
139 | { |
140 | struct e1000_hw *hw = &adapter->hw; | |
141 | ||
b980ac18 | 142 | /* Writing the SYSTIMR register is not necessary as it only provides |
e57b8bdb MV |
143 | * sub-nanosecond resolution. |
144 | */ | |
145 | wr32(E1000_SYSTIML, ts->tv_nsec); | |
40c9b079 | 146 | wr32(E1000_SYSTIMH, (u32)ts->tv_sec); |
e57b8bdb MV |
147 | } |
148 | ||
a79f4f88 MV |
149 | /** |
150 | * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp | |
151 | * @adapter: board private structure | |
152 | * @hwtstamps: timestamp structure to update | |
153 | * @systim: unsigned 64bit system time value. | |
154 | * | |
155 | * We need to convert the system time value stored in the RX/TXSTMP registers | |
156 | * into a hwtstamp which can be used by the upper level timestamping functions. | |
157 | * | |
158 | * The 'tmreg_lock' spinlock is used to protect the consistency of the | |
159 | * system time value. This is needed because reading the 64 bit time | |
160 | * value involves reading two (or three) 32 bit registers. The first | |
161 | * read latches the value. Ditto for writing. | |
162 | * | |
163 | * In addition, here have extended the system time with an overflow | |
164 | * counter in software. | |
165 | **/ | |
166 | static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter, | |
167 | struct skb_shared_hwtstamps *hwtstamps, | |
168 | u64 systim) | |
169 | { | |
170 | unsigned long flags; | |
171 | u64 ns; | |
172 | ||
173 | switch (adapter->hw.mac.type) { | |
e57b8bdb MV |
174 | case e1000_82576: |
175 | case e1000_82580: | |
ceb5f13b | 176 | case e1000_i354: |
e57b8bdb MV |
177 | case e1000_i350: |
178 | spin_lock_irqsave(&adapter->tmreg_lock, flags); | |
179 | ||
180 | ns = timecounter_cyc2time(&adapter->tc, systim); | |
181 | ||
182 | spin_unlock_irqrestore(&adapter->tmreg_lock, flags); | |
183 | ||
184 | memset(hwtstamps, 0, sizeof(*hwtstamps)); | |
185 | hwtstamps->hwtstamp = ns_to_ktime(ns); | |
186 | break; | |
a79f4f88 MV |
187 | case e1000_i210: |
188 | case e1000_i211: | |
e57b8bdb MV |
189 | memset(hwtstamps, 0, sizeof(*hwtstamps)); |
190 | /* Upper 32 bits contain s, lower 32 bits contain ns. */ | |
191 | hwtstamps->hwtstamp = ktime_set(systim >> 32, | |
192 | systim & 0xFFFFFFFF); | |
a79f4f88 MV |
193 | break; |
194 | default: | |
e57b8bdb | 195 | break; |
a79f4f88 | 196 | } |
a79f4f88 MV |
197 | } |
198 | ||
b980ac18 | 199 | /* PTP clock operations */ |
a79f4f88 | 200 | static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb) |
d339b133 | 201 | { |
a79f4f88 MV |
202 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
203 | ptp_caps); | |
204 | struct e1000_hw *hw = &igb->hw; | |
205 | int neg_adj = 0; | |
d339b133 RC |
206 | u64 rate; |
207 | u32 incvalue; | |
d339b133 RC |
208 | |
209 | if (ppb < 0) { | |
210 | neg_adj = 1; | |
211 | ppb = -ppb; | |
212 | } | |
213 | rate = ppb; | |
214 | rate <<= 14; | |
215 | rate = div_u64(rate, 1953125); | |
216 | ||
217 | incvalue = 16 << IGB_82576_TSYNC_SHIFT; | |
218 | ||
219 | if (neg_adj) | |
220 | incvalue -= rate; | |
221 | else | |
222 | incvalue += rate; | |
223 | ||
224 | wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); | |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
a79f4f88 | 229 | static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb) |
d339b133 | 230 | { |
a79f4f88 MV |
231 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
232 | ptp_caps); | |
233 | struct e1000_hw *hw = &igb->hw; | |
234 | int neg_adj = 0; | |
d339b133 RC |
235 | u64 rate; |
236 | u32 inca; | |
d339b133 RC |
237 | |
238 | if (ppb < 0) { | |
239 | neg_adj = 1; | |
240 | ppb = -ppb; | |
241 | } | |
242 | rate = ppb; | |
243 | rate <<= 26; | |
244 | rate = div_u64(rate, 1953125); | |
245 | ||
246 | inca = rate & INCVALUE_MASK; | |
247 | if (neg_adj) | |
248 | inca |= ISGN; | |
249 | ||
250 | wr32(E1000_TIMINCA, inca); | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
e57b8bdb | 255 | static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta) |
d339b133 | 256 | { |
a79f4f88 MV |
257 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
258 | ptp_caps); | |
d339b133 | 259 | unsigned long flags; |
d339b133 RC |
260 | |
261 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
5ee698e3 | 262 | timecounter_adjtime(&igb->tc, delta); |
d339b133 RC |
263 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); |
264 | ||
265 | return 0; | |
266 | } | |
267 | ||
e57b8bdb MV |
268 | static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta) |
269 | { | |
270 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, | |
271 | ptp_caps); | |
272 | unsigned long flags; | |
d4c496fe | 273 | struct timespec64 now, then = ns_to_timespec64(delta); |
e57b8bdb MV |
274 | |
275 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
276 | ||
277 | igb_ptp_read_i210(igb, &now); | |
d4c496fe RC |
278 | now = timespec64_add(now, then); |
279 | igb_ptp_write_i210(igb, (const struct timespec64 *)&now); | |
e57b8bdb MV |
280 | |
281 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
286 | static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp, | |
d4c496fe | 287 | struct timespec64 *ts) |
d339b133 | 288 | { |
a79f4f88 MV |
289 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
290 | ptp_caps); | |
291 | unsigned long flags; | |
d339b133 | 292 | u64 ns; |
d339b133 RC |
293 | |
294 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
295 | ||
296 | ns = timecounter_read(&igb->tc); | |
297 | ||
298 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
299 | ||
350f66d5 | 300 | *ts = ns_to_timespec64(ns); |
d339b133 RC |
301 | |
302 | return 0; | |
303 | } | |
304 | ||
e57b8bdb | 305 | static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp, |
d4c496fe | 306 | struct timespec64 *ts) |
e57b8bdb MV |
307 | { |
308 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, | |
309 | ptp_caps); | |
310 | unsigned long flags; | |
311 | ||
312 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
313 | ||
314 | igb_ptp_read_i210(igb, ts); | |
315 | ||
316 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
317 | ||
318 | return 0; | |
319 | } | |
320 | ||
321 | static int igb_ptp_settime_82576(struct ptp_clock_info *ptp, | |
d4c496fe | 322 | const struct timespec64 *ts) |
d339b133 | 323 | { |
a79f4f88 MV |
324 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
325 | ptp_caps); | |
d339b133 | 326 | unsigned long flags; |
a79f4f88 | 327 | u64 ns; |
d339b133 | 328 | |
350f66d5 | 329 | ns = timespec64_to_ns(ts); |
d339b133 RC |
330 | |
331 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
332 | ||
333 | timecounter_init(&igb->tc, &igb->cc, ns); | |
334 | ||
335 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
336 | ||
337 | return 0; | |
338 | } | |
339 | ||
e57b8bdb | 340 | static int igb_ptp_settime_i210(struct ptp_clock_info *ptp, |
d4c496fe | 341 | const struct timespec64 *ts) |
e57b8bdb MV |
342 | { |
343 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, | |
344 | ptp_caps); | |
345 | unsigned long flags; | |
346 | ||
347 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
348 | ||
349 | igb_ptp_write_i210(igb, ts); | |
350 | ||
351 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
352 | ||
353 | return 0; | |
354 | } | |
355 | ||
720db4ff RC |
356 | static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext) |
357 | { | |
358 | u32 *ptr = pin < 2 ? ctrl : ctrl_ext; | |
b23c0cc5 | 359 | static const u32 mask[IGB_N_SDP] = { |
720db4ff RC |
360 | E1000_CTRL_SDP0_DIR, |
361 | E1000_CTRL_SDP1_DIR, | |
362 | E1000_CTRL_EXT_SDP2_DIR, | |
363 | E1000_CTRL_EXT_SDP3_DIR, | |
364 | }; | |
365 | ||
366 | if (input) | |
367 | *ptr &= ~mask[pin]; | |
368 | else | |
369 | *ptr |= mask[pin]; | |
370 | } | |
371 | ||
372 | static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin) | |
373 | { | |
b23c0cc5 | 374 | static const u32 aux0_sel_sdp[IGB_N_SDP] = { |
720db4ff RC |
375 | AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, |
376 | }; | |
b23c0cc5 | 377 | static const u32 aux1_sel_sdp[IGB_N_SDP] = { |
720db4ff RC |
378 | AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, |
379 | }; | |
b23c0cc5 | 380 | static const u32 ts_sdp_en[IGB_N_SDP] = { |
720db4ff RC |
381 | TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, |
382 | }; | |
b23c0cc5 | 383 | struct e1000_hw *hw = &igb->hw; |
720db4ff RC |
384 | u32 ctrl, ctrl_ext, tssdp = 0; |
385 | ||
386 | ctrl = rd32(E1000_CTRL); | |
387 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
388 | tssdp = rd32(E1000_TSSDP); | |
389 | ||
390 | igb_pin_direction(pin, 1, &ctrl, &ctrl_ext); | |
391 | ||
392 | /* Make sure this pin is not enabled as an output. */ | |
393 | tssdp &= ~ts_sdp_en[pin]; | |
394 | ||
395 | if (chan == 1) { | |
396 | tssdp &= ~AUX1_SEL_SDP3; | |
397 | tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN; | |
398 | } else { | |
399 | tssdp &= ~AUX0_SEL_SDP3; | |
400 | tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN; | |
401 | } | |
402 | ||
403 | wr32(E1000_TSSDP, tssdp); | |
404 | wr32(E1000_CTRL, ctrl); | |
405 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
406 | } | |
407 | ||
30c72916 | 408 | static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq) |
720db4ff | 409 | { |
b23c0cc5 | 410 | static const u32 aux0_sel_sdp[IGB_N_SDP] = { |
720db4ff RC |
411 | AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, |
412 | }; | |
b23c0cc5 | 413 | static const u32 aux1_sel_sdp[IGB_N_SDP] = { |
720db4ff RC |
414 | AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, |
415 | }; | |
b23c0cc5 | 416 | static const u32 ts_sdp_en[IGB_N_SDP] = { |
720db4ff RC |
417 | TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, |
418 | }; | |
b23c0cc5 | 419 | static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = { |
720db4ff RC |
420 | TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0, |
421 | TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0, | |
422 | }; | |
b23c0cc5 | 423 | static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = { |
720db4ff RC |
424 | TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1, |
425 | TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1, | |
426 | }; | |
30c72916 RC |
427 | static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = { |
428 | TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0, | |
429 | TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0, | |
430 | }; | |
431 | static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = { | |
432 | TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1, | |
433 | TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1, | |
434 | }; | |
b23c0cc5 | 435 | static const u32 ts_sdp_sel_clr[IGB_N_SDP] = { |
720db4ff RC |
436 | TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1, |
437 | TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1, | |
438 | }; | |
b23c0cc5 | 439 | struct e1000_hw *hw = &igb->hw; |
720db4ff RC |
440 | u32 ctrl, ctrl_ext, tssdp = 0; |
441 | ||
442 | ctrl = rd32(E1000_CTRL); | |
443 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
444 | tssdp = rd32(E1000_TSSDP); | |
445 | ||
446 | igb_pin_direction(pin, 0, &ctrl, &ctrl_ext); | |
447 | ||
448 | /* Make sure this pin is not enabled as an input. */ | |
449 | if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin]) | |
450 | tssdp &= ~AUX0_TS_SDP_EN; | |
451 | ||
452 | if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin]) | |
453 | tssdp &= ~AUX1_TS_SDP_EN; | |
454 | ||
455 | tssdp &= ~ts_sdp_sel_clr[pin]; | |
30c72916 RC |
456 | if (freq) { |
457 | if (chan == 1) | |
458 | tssdp |= ts_sdp_sel_fc1[pin]; | |
459 | else | |
460 | tssdp |= ts_sdp_sel_fc0[pin]; | |
461 | } else { | |
462 | if (chan == 1) | |
463 | tssdp |= ts_sdp_sel_tt1[pin]; | |
464 | else | |
465 | tssdp |= ts_sdp_sel_tt0[pin]; | |
466 | } | |
720db4ff RC |
467 | tssdp |= ts_sdp_en[pin]; |
468 | ||
469 | wr32(E1000_TSSDP, tssdp); | |
470 | wr32(E1000_CTRL, ctrl); | |
471 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
472 | } | |
473 | ||
00c65578 RC |
474 | static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp, |
475 | struct ptp_clock_request *rq, int on) | |
476 | { | |
477 | struct igb_adapter *igb = | |
478 | container_of(ptp, struct igb_adapter, ptp_caps); | |
479 | struct e1000_hw *hw = &igb->hw; | |
30c72916 | 480 | u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout; |
00c65578 | 481 | unsigned long flags; |
40c9b079 | 482 | struct timespec64 ts; |
30c72916 | 483 | int use_freq = 0, pin = -1; |
720db4ff | 484 | s64 ns; |
00c65578 RC |
485 | |
486 | switch (rq->type) { | |
720db4ff RC |
487 | case PTP_CLK_REQ_EXTTS: |
488 | if (on) { | |
489 | pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS, | |
490 | rq->extts.index); | |
491 | if (pin < 0) | |
492 | return -EBUSY; | |
493 | } | |
494 | if (rq->extts.index == 1) { | |
495 | tsauxc_mask = TSAUXC_EN_TS1; | |
496 | tsim_mask = TSINTR_AUTT1; | |
497 | } else { | |
498 | tsauxc_mask = TSAUXC_EN_TS0; | |
499 | tsim_mask = TSINTR_AUTT0; | |
500 | } | |
501 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
502 | tsauxc = rd32(E1000_TSAUXC); | |
503 | tsim = rd32(E1000_TSIM); | |
504 | if (on) { | |
505 | igb_pin_extts(igb, rq->extts.index, pin); | |
506 | tsauxc |= tsauxc_mask; | |
507 | tsim |= tsim_mask; | |
508 | } else { | |
509 | tsauxc &= ~tsauxc_mask; | |
510 | tsim &= ~tsim_mask; | |
511 | } | |
512 | wr32(E1000_TSAUXC, tsauxc); | |
513 | wr32(E1000_TSIM, tsim); | |
514 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
515 | return 0; | |
516 | ||
517 | case PTP_CLK_REQ_PEROUT: | |
518 | if (on) { | |
519 | pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT, | |
520 | rq->perout.index); | |
521 | if (pin < 0) | |
522 | return -EBUSY; | |
523 | } | |
524 | ts.tv_sec = rq->perout.period.sec; | |
525 | ts.tv_nsec = rq->perout.period.nsec; | |
40c9b079 | 526 | ns = timespec64_to_ns(&ts); |
720db4ff | 527 | ns = ns >> 1; |
569f3b3d RH |
528 | if (on && ((ns <= 70000000LL) || (ns == 125000000LL) || |
529 | (ns == 250000000LL) || (ns == 500000000LL))) { | |
30c72916 RC |
530 | if (ns < 8LL) |
531 | return -EINVAL; | |
532 | use_freq = 1; | |
720db4ff | 533 | } |
40c9b079 | 534 | ts = ns_to_timespec64(ns); |
720db4ff | 535 | if (rq->perout.index == 1) { |
30c72916 RC |
536 | if (use_freq) { |
537 | tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1; | |
538 | tsim_mask = 0; | |
539 | } else { | |
540 | tsauxc_mask = TSAUXC_EN_TT1; | |
541 | tsim_mask = TSINTR_TT1; | |
542 | } | |
720db4ff RC |
543 | trgttiml = E1000_TRGTTIML1; |
544 | trgttimh = E1000_TRGTTIMH1; | |
30c72916 | 545 | freqout = E1000_FREQOUT1; |
720db4ff | 546 | } else { |
30c72916 RC |
547 | if (use_freq) { |
548 | tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0; | |
549 | tsim_mask = 0; | |
550 | } else { | |
551 | tsauxc_mask = TSAUXC_EN_TT0; | |
552 | tsim_mask = TSINTR_TT0; | |
553 | } | |
720db4ff RC |
554 | trgttiml = E1000_TRGTTIML0; |
555 | trgttimh = E1000_TRGTTIMH0; | |
30c72916 | 556 | freqout = E1000_FREQOUT0; |
720db4ff RC |
557 | } |
558 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
559 | tsauxc = rd32(E1000_TSAUXC); | |
560 | tsim = rd32(E1000_TSIM); | |
30c72916 RC |
561 | if (rq->perout.index == 1) { |
562 | tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1); | |
563 | tsim &= ~TSINTR_TT1; | |
564 | } else { | |
565 | tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0); | |
566 | tsim &= ~TSINTR_TT0; | |
567 | } | |
720db4ff RC |
568 | if (on) { |
569 | int i = rq->perout.index; | |
30c72916 | 570 | igb_pin_perout(igb, i, pin, use_freq); |
720db4ff RC |
571 | igb->perout[i].start.tv_sec = rq->perout.start.sec; |
572 | igb->perout[i].start.tv_nsec = rq->perout.start.nsec; | |
573 | igb->perout[i].period.tv_sec = ts.tv_sec; | |
574 | igb->perout[i].period.tv_nsec = ts.tv_nsec; | |
58c98be1 RC |
575 | wr32(trgttimh, rq->perout.start.sec); |
576 | wr32(trgttiml, rq->perout.start.nsec); | |
30c72916 RC |
577 | if (use_freq) |
578 | wr32(freqout, ns); | |
720db4ff RC |
579 | tsauxc |= tsauxc_mask; |
580 | tsim |= tsim_mask; | |
720db4ff RC |
581 | } |
582 | wr32(E1000_TSAUXC, tsauxc); | |
583 | wr32(E1000_TSIM, tsim); | |
584 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
585 | return 0; | |
586 | ||
00c65578 RC |
587 | case PTP_CLK_REQ_PPS: |
588 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
589 | tsim = rd32(E1000_TSIM); | |
590 | if (on) | |
591 | tsim |= TSINTR_SYS_WRAP; | |
592 | else | |
593 | tsim &= ~TSINTR_SYS_WRAP; | |
594 | wr32(E1000_TSIM, tsim); | |
595 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
596 | return 0; | |
00c65578 RC |
597 | } |
598 | ||
599 | return -EOPNOTSUPP; | |
600 | } | |
601 | ||
102be52f JK |
602 | static int igb_ptp_feature_enable(struct ptp_clock_info *ptp, |
603 | struct ptp_clock_request *rq, int on) | |
d339b133 RC |
604 | { |
605 | return -EOPNOTSUPP; | |
606 | } | |
607 | ||
720db4ff RC |
608 | static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin, |
609 | enum ptp_pin_function func, unsigned int chan) | |
610 | { | |
611 | switch (func) { | |
612 | case PTP_PF_NONE: | |
613 | case PTP_PF_EXTTS: | |
614 | case PTP_PF_PEROUT: | |
615 | break; | |
616 | case PTP_PF_PHYSYNC: | |
617 | return -1; | |
618 | } | |
619 | return 0; | |
620 | } | |
621 | ||
1f6e8178 MV |
622 | /** |
623 | * igb_ptp_tx_work | |
624 | * @work: pointer to work struct | |
625 | * | |
626 | * This work function polls the TSYNCTXCTL valid bit to determine when a | |
627 | * timestamp has been taken for the current stored skb. | |
b980ac18 | 628 | **/ |
167f3f71 | 629 | static void igb_ptp_tx_work(struct work_struct *work) |
1f6e8178 MV |
630 | { |
631 | struct igb_adapter *adapter = container_of(work, struct igb_adapter, | |
632 | ptp_tx_work); | |
633 | struct e1000_hw *hw = &adapter->hw; | |
634 | u32 tsynctxctl; | |
635 | ||
636 | if (!adapter->ptp_tx_skb) | |
637 | return; | |
638 | ||
428f1f71 MV |
639 | if (time_is_before_jiffies(adapter->ptp_tx_start + |
640 | IGB_PTP_TX_TIMEOUT)) { | |
641 | dev_kfree_skb_any(adapter->ptp_tx_skb); | |
642 | adapter->ptp_tx_skb = NULL; | |
ed4420a3 | 643 | clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); |
428f1f71 | 644 | adapter->tx_hwtstamp_timeouts++; |
c5ffe7e1 | 645 | dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n"); |
428f1f71 MV |
646 | return; |
647 | } | |
648 | ||
1f6e8178 MV |
649 | tsynctxctl = rd32(E1000_TSYNCTXCTL); |
650 | if (tsynctxctl & E1000_TSYNCTXCTL_VALID) | |
651 | igb_ptp_tx_hwtstamp(adapter); | |
652 | else | |
653 | /* reschedule to check later */ | |
654 | schedule_work(&adapter->ptp_tx_work); | |
655 | } | |
656 | ||
a79f4f88 | 657 | static void igb_ptp_overflow_check(struct work_struct *work) |
d339b133 | 658 | { |
a79f4f88 MV |
659 | struct igb_adapter *igb = |
660 | container_of(work, struct igb_adapter, ptp_overflow_work.work); | |
d4c496fe | 661 | struct timespec64 ts; |
a79f4f88 | 662 | |
d4c496fe | 663 | igb->ptp_caps.gettime64(&igb->ptp_caps, &ts); |
a79f4f88 | 664 | |
32eaf120 DM |
665 | pr_debug("igb overflow check at %lld.%09lu\n", |
666 | (long long) ts.tv_sec, ts.tv_nsec); | |
a79f4f88 MV |
667 | |
668 | schedule_delayed_work(&igb->ptp_overflow_work, | |
669 | IGB_SYSTIM_OVERFLOW_PERIOD); | |
d339b133 RC |
670 | } |
671 | ||
fc580751 MV |
672 | /** |
673 | * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched | |
674 | * @adapter: private network adapter structure | |
675 | * | |
676 | * This watchdog task is scheduled to detect error case where hardware has | |
677 | * dropped an Rx packet that was timestamped when the ring is full. The | |
678 | * particular error is rare but leaves the device in a state unable to timestamp | |
679 | * any future packets. | |
b980ac18 | 680 | **/ |
fc580751 MV |
681 | void igb_ptp_rx_hang(struct igb_adapter *adapter) |
682 | { | |
683 | struct e1000_hw *hw = &adapter->hw; | |
fc580751 MV |
684 | u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL); |
685 | unsigned long rx_event; | |
fc580751 | 686 | |
462f1188 | 687 | /* Other hardware uses per-packet timestamps */ |
fc580751 MV |
688 | if (hw->mac.type != e1000_82576) |
689 | return; | |
690 | ||
691 | /* If we don't have a valid timestamp in the registers, just update the | |
692 | * timeout counter and exit | |
693 | */ | |
694 | if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) { | |
695 | adapter->last_rx_ptp_check = jiffies; | |
696 | return; | |
697 | } | |
698 | ||
699 | /* Determine the most recent watchdog or rx_timestamp event */ | |
700 | rx_event = adapter->last_rx_ptp_check; | |
5499a968 JK |
701 | if (time_after(adapter->last_rx_timestamp, rx_event)) |
702 | rx_event = adapter->last_rx_timestamp; | |
fc580751 MV |
703 | |
704 | /* Only need to read the high RXSTMP register to clear the lock */ | |
705 | if (time_is_before_jiffies(rx_event + 5 * HZ)) { | |
706 | rd32(E1000_RXSTMPH); | |
707 | adapter->last_rx_ptp_check = jiffies; | |
708 | adapter->rx_hwtstamp_cleared++; | |
c5ffe7e1 | 709 | dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n"); |
fc580751 MV |
710 | } |
711 | } | |
712 | ||
a79f4f88 MV |
713 | /** |
714 | * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp | |
1f6e8178 | 715 | * @adapter: Board private structure. |
a79f4f88 MV |
716 | * |
717 | * If we were asked to do hardware stamping and such a time stamp is | |
718 | * available, then it must have been for this skb here because we only | |
719 | * allow only one such packet into the queue. | |
b980ac18 | 720 | **/ |
167f3f71 | 721 | static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter) |
d339b133 | 722 | { |
a79f4f88 MV |
723 | struct e1000_hw *hw = &adapter->hw; |
724 | struct skb_shared_hwtstamps shhwtstamps; | |
725 | u64 regval; | |
3f544d2a | 726 | int adjust = 0; |
d339b133 | 727 | |
a79f4f88 MV |
728 | regval = rd32(E1000_TXSTMPL); |
729 | regval |= (u64)rd32(E1000_TXSTMPH) << 32; | |
d339b133 | 730 | |
a79f4f88 | 731 | igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); |
3f544d2a NS |
732 | /* adjust timestamp for the TX latency based on link speed */ |
733 | if (adapter->hw.mac.type == e1000_i210) { | |
734 | switch (adapter->link_speed) { | |
735 | case SPEED_10: | |
736 | adjust = IGB_I210_TX_LATENCY_10; | |
737 | break; | |
738 | case SPEED_100: | |
739 | adjust = IGB_I210_TX_LATENCY_100; | |
740 | break; | |
741 | case SPEED_1000: | |
742 | adjust = IGB_I210_TX_LATENCY_1000; | |
743 | break; | |
744 | } | |
745 | } | |
746 | ||
0066c8b6 KG |
747 | shhwtstamps.hwtstamp = |
748 | ktime_add_ns(shhwtstamps.hwtstamp, adjust); | |
3f544d2a | 749 | |
1f6e8178 MV |
750 | skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps); |
751 | dev_kfree_skb_any(adapter->ptp_tx_skb); | |
752 | adapter->ptp_tx_skb = NULL; | |
ed4420a3 | 753 | clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); |
a79f4f88 MV |
754 | } |
755 | ||
b534550a AD |
756 | /** |
757 | * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp | |
758 | * @q_vector: Pointer to interrupt specific structure | |
759 | * @va: Pointer to address containing Rx buffer | |
760 | * @skb: Buffer containing timestamp and packet | |
761 | * | |
762 | * This function is meant to retrieve a timestamp from the first buffer of an | |
763 | * incoming frame. The value is stored in little endian format starting on | |
764 | * byte 8. | |
b980ac18 | 765 | **/ |
b534550a AD |
766 | void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, |
767 | unsigned char *va, | |
768 | struct sk_buff *skb) | |
769 | { | |
ac61d515 | 770 | __le64 *regval = (__le64 *)va; |
0066c8b6 KG |
771 | struct igb_adapter *adapter = q_vector->adapter; |
772 | int adjust = 0; | |
b534550a | 773 | |
b980ac18 | 774 | /* The timestamp is recorded in little endian format. |
b534550a AD |
775 | * DWORD: 0 1 2 3 |
776 | * Field: Reserved Reserved SYSTIML SYSTIMH | |
777 | */ | |
0066c8b6 | 778 | igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), |
b534550a | 779 | le64_to_cpu(regval[1])); |
0066c8b6 KG |
780 | |
781 | /* adjust timestamp for the RX latency based on link speed */ | |
782 | if (adapter->hw.mac.type == e1000_i210) { | |
783 | switch (adapter->link_speed) { | |
784 | case SPEED_10: | |
785 | adjust = IGB_I210_RX_LATENCY_10; | |
786 | break; | |
787 | case SPEED_100: | |
788 | adjust = IGB_I210_RX_LATENCY_100; | |
789 | break; | |
790 | case SPEED_1000: | |
791 | adjust = IGB_I210_RX_LATENCY_1000; | |
792 | break; | |
793 | } | |
794 | } | |
795 | skb_hwtstamps(skb)->hwtstamp = | |
796 | ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust); | |
b534550a AD |
797 | } |
798 | ||
799 | /** | |
800 | * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register | |
801 | * @q_vector: Pointer to interrupt specific structure | |
802 | * @skb: Buffer containing timestamp and packet | |
803 | * | |
804 | * This function is meant to retrieve a timestamp from the internal registers | |
805 | * of the adapter and store it in the skb. | |
b980ac18 | 806 | **/ |
b534550a | 807 | void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, |
a79f4f88 MV |
808 | struct sk_buff *skb) |
809 | { | |
810 | struct igb_adapter *adapter = q_vector->adapter; | |
811 | struct e1000_hw *hw = &adapter->hw; | |
812 | u64 regval; | |
3f544d2a | 813 | int adjust = 0; |
a79f4f88 | 814 | |
b980ac18 | 815 | /* If this bit is set, then the RX registers contain the time stamp. No |
a79f4f88 MV |
816 | * other packet will be time stamped until we read these registers, so |
817 | * read the registers to make them available again. Because only one | |
818 | * packet can be time stamped at a time, we know that the register | |
819 | * values must belong to this one here and therefore we don't need to | |
820 | * compare any of the additional attributes stored for it. | |
821 | * | |
822 | * If nothing went wrong, then it should have a shared tx_flags that we | |
823 | * can turn into a skb_shared_hwtstamps. | |
824 | */ | |
b534550a AD |
825 | if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) |
826 | return; | |
827 | ||
828 | regval = rd32(E1000_RXSTMPL); | |
829 | regval |= (u64)rd32(E1000_RXSTMPH) << 32; | |
a79f4f88 MV |
830 | |
831 | igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); | |
5499a968 | 832 | |
3f544d2a NS |
833 | /* adjust timestamp for the RX latency based on link speed */ |
834 | if (adapter->hw.mac.type == e1000_i210) { | |
835 | switch (adapter->link_speed) { | |
836 | case SPEED_10: | |
837 | adjust = IGB_I210_RX_LATENCY_10; | |
838 | break; | |
839 | case SPEED_100: | |
840 | adjust = IGB_I210_RX_LATENCY_100; | |
841 | break; | |
842 | case SPEED_1000: | |
843 | adjust = IGB_I210_RX_LATENCY_1000; | |
844 | break; | |
845 | } | |
846 | } | |
847 | skb_hwtstamps(skb)->hwtstamp = | |
0066c8b6 | 848 | ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust); |
3f544d2a | 849 | |
5499a968 JK |
850 | /* Update the last_rx_timestamp timer in order to enable watchdog check |
851 | * for error case of latched timestamp on a dropped packet. | |
852 | */ | |
853 | adapter->last_rx_timestamp = jiffies; | |
a79f4f88 MV |
854 | } |
855 | ||
856 | /** | |
6ab5f7b2 JK |
857 | * igb_ptp_get_ts_config - get hardware time stamping config |
858 | * @netdev: | |
859 | * @ifreq: | |
860 | * | |
861 | * Get the hwtstamp_config settings to return to the user. Rather than attempt | |
862 | * to deconstruct the settings from the registers, just return a shadow copy | |
863 | * of the last known settings. | |
864 | **/ | |
865 | int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr) | |
866 | { | |
867 | struct igb_adapter *adapter = netdev_priv(netdev); | |
868 | struct hwtstamp_config *config = &adapter->tstamp_config; | |
869 | ||
870 | return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? | |
871 | -EFAULT : 0; | |
872 | } | |
9f62ecf4 | 873 | |
6ab5f7b2 | 874 | /** |
9f62ecf4 JK |
875 | * igb_ptp_set_timestamp_mode - setup hardware for timestamping |
876 | * @adapter: networking device structure | |
877 | * @config: hwtstamp configuration | |
a79f4f88 MV |
878 | * |
879 | * Outgoing time stamping can be enabled and disabled. Play nice and | |
880 | * disable it when requested, although it shouldn't case any overhead | |
881 | * when no packet needs it. At most one packet in the queue may be | |
882 | * marked for time stamping, otherwise it would be impossible to tell | |
883 | * for sure to which packet the hardware time stamp belongs. | |
884 | * | |
885 | * Incoming time stamping has to be configured via the hardware | |
886 | * filters. Not all combinations are supported, in particular event | |
887 | * type has to be specified. Matching the kind of event packet is | |
888 | * not supported, with the exception of "all V2 events regardless of | |
889 | * level 2 or 4". | |
9f62ecf4 JK |
890 | */ |
891 | static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter, | |
892 | struct hwtstamp_config *config) | |
a79f4f88 | 893 | { |
a79f4f88 | 894 | struct e1000_hw *hw = &adapter->hw; |
a79f4f88 MV |
895 | u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; |
896 | u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; | |
897 | u32 tsync_rx_cfg = 0; | |
898 | bool is_l4 = false; | |
899 | bool is_l2 = false; | |
900 | u32 regval; | |
901 | ||
a79f4f88 | 902 | /* reserved for future extensions */ |
6ab5f7b2 | 903 | if (config->flags) |
a79f4f88 MV |
904 | return -EINVAL; |
905 | ||
6ab5f7b2 | 906 | switch (config->tx_type) { |
a79f4f88 MV |
907 | case HWTSTAMP_TX_OFF: |
908 | tsync_tx_ctl = 0; | |
909 | case HWTSTAMP_TX_ON: | |
910 | break; | |
911 | default: | |
912 | return -ERANGE; | |
913 | } | |
914 | ||
6ab5f7b2 | 915 | switch (config->rx_filter) { |
a79f4f88 MV |
916 | case HWTSTAMP_FILTER_NONE: |
917 | tsync_rx_ctl = 0; | |
918 | break; | |
a79f4f88 MV |
919 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
920 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; | |
921 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; | |
922 | is_l4 = true; | |
923 | break; | |
924 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
925 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; | |
926 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; | |
927 | is_l4 = true; | |
928 | break; | |
3e961a06 MV |
929 | case HWTSTAMP_FILTER_PTP_V2_EVENT: |
930 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
931 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
932 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
a79f4f88 MV |
933 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: |
934 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
3e961a06 | 935 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
a79f4f88 MV |
936 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: |
937 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
a79f4f88 | 938 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; |
6ab5f7b2 | 939 | config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
a79f4f88 MV |
940 | is_l2 = true; |
941 | is_l4 = true; | |
942 | break; | |
3e961a06 MV |
943 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: |
944 | case HWTSTAMP_FILTER_ALL: | |
945 | /* 82576 cannot timestamp all packets, which it needs to do to | |
946 | * support both V1 Sync and Delay_Req messages | |
947 | */ | |
948 | if (hw->mac.type != e1000_82576) { | |
949 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; | |
6ab5f7b2 | 950 | config->rx_filter = HWTSTAMP_FILTER_ALL; |
3e961a06 MV |
951 | break; |
952 | } | |
953 | /* fall through */ | |
a79f4f88 | 954 | default: |
6ab5f7b2 | 955 | config->rx_filter = HWTSTAMP_FILTER_NONE; |
a79f4f88 MV |
956 | return -ERANGE; |
957 | } | |
958 | ||
959 | if (hw->mac.type == e1000_82575) { | |
960 | if (tsync_rx_ctl | tsync_tx_ctl) | |
961 | return -EINVAL; | |
962 | return 0; | |
963 | } | |
964 | ||
b980ac18 | 965 | /* Per-packet timestamping only works if all packets are |
a79f4f88 | 966 | * timestamped, so enable timestamping in all packets as |
b980ac18 | 967 | * long as one Rx filter was configured. |
a79f4f88 MV |
968 | */ |
969 | if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) { | |
970 | tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; | |
971 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; | |
6ab5f7b2 | 972 | config->rx_filter = HWTSTAMP_FILTER_ALL; |
3e961a06 MV |
973 | is_l2 = true; |
974 | is_l4 = true; | |
e57b8bdb MV |
975 | |
976 | if ((hw->mac.type == e1000_i210) || | |
977 | (hw->mac.type == e1000_i211)) { | |
978 | regval = rd32(E1000_RXPBS); | |
979 | regval |= E1000_RXPBS_CFG_TS_EN; | |
980 | wr32(E1000_RXPBS, regval); | |
981 | } | |
a79f4f88 MV |
982 | } |
983 | ||
984 | /* enable/disable TX */ | |
985 | regval = rd32(E1000_TSYNCTXCTL); | |
986 | regval &= ~E1000_TSYNCTXCTL_ENABLED; | |
987 | regval |= tsync_tx_ctl; | |
988 | wr32(E1000_TSYNCTXCTL, regval); | |
989 | ||
990 | /* enable/disable RX */ | |
991 | regval = rd32(E1000_TSYNCRXCTL); | |
992 | regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); | |
993 | regval |= tsync_rx_ctl; | |
994 | wr32(E1000_TSYNCRXCTL, regval); | |
995 | ||
996 | /* define which PTP packets are time stamped */ | |
997 | wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); | |
998 | ||
999 | /* define ethertype filter for timestamped packets */ | |
1000 | if (is_l2) | |
1001 | wr32(E1000_ETQF(3), | |
1002 | (E1000_ETQF_FILTER_ENABLE | /* enable filter */ | |
1003 | E1000_ETQF_1588 | /* enable timestamping */ | |
1004 | ETH_P_1588)); /* 1588 eth protocol type */ | |
1005 | else | |
1006 | wr32(E1000_ETQF(3), 0); | |
1007 | ||
a79f4f88 MV |
1008 | /* L4 Queue Filter[3]: filter by destination port and protocol */ |
1009 | if (is_l4) { | |
1010 | u32 ftqf = (IPPROTO_UDP /* UDP */ | |
1011 | | E1000_FTQF_VF_BP /* VF not compared */ | |
1012 | | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ | |
1013 | | E1000_FTQF_MASK); /* mask all inputs */ | |
1014 | ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ | |
1015 | ||
ba59814b | 1016 | wr32(E1000_IMIR(3), htons(PTP_EV_PORT)); |
a79f4f88 MV |
1017 | wr32(E1000_IMIREXT(3), |
1018 | (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); | |
1019 | if (hw->mac.type == e1000_82576) { | |
1020 | /* enable source port check */ | |
ba59814b | 1021 | wr32(E1000_SPQF(3), htons(PTP_EV_PORT)); |
a79f4f88 MV |
1022 | ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; |
1023 | } | |
1024 | wr32(E1000_FTQF(3), ftqf); | |
1025 | } else { | |
1026 | wr32(E1000_FTQF(3), E1000_FTQF_MASK); | |
1027 | } | |
1028 | wrfl(); | |
1029 | ||
1030 | /* clear TX/RX time stamp registers, just to be sure */ | |
e57b8bdb | 1031 | regval = rd32(E1000_TXSTMPL); |
a79f4f88 | 1032 | regval = rd32(E1000_TXSTMPH); |
e57b8bdb | 1033 | regval = rd32(E1000_RXSTMPL); |
a79f4f88 MV |
1034 | regval = rd32(E1000_RXSTMPH); |
1035 | ||
9f62ecf4 JK |
1036 | return 0; |
1037 | } | |
1038 | ||
1039 | /** | |
1040 | * igb_ptp_set_ts_config - set hardware time stamping config | |
1041 | * @netdev: | |
1042 | * @ifreq: | |
1043 | * | |
1044 | **/ | |
1045 | int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr) | |
1046 | { | |
1047 | struct igb_adapter *adapter = netdev_priv(netdev); | |
1048 | struct hwtstamp_config config; | |
1049 | int err; | |
1050 | ||
1051 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
1052 | return -EFAULT; | |
1053 | ||
1054 | err = igb_ptp_set_timestamp_mode(adapter, &config); | |
1055 | if (err) | |
1056 | return err; | |
1057 | ||
1058 | /* save these settings for future reference */ | |
1059 | memcpy(&adapter->tstamp_config, &config, | |
1060 | sizeof(adapter->tstamp_config)); | |
1061 | ||
1062 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
a79f4f88 | 1063 | -EFAULT : 0; |
d339b133 RC |
1064 | } |
1065 | ||
4f3ce71b JK |
1066 | /** |
1067 | * igb_ptp_init - Initialize PTP functionality | |
1068 | * @adapter: Board private structure | |
1069 | * | |
1070 | * This function is called at device probe to initialize the PTP | |
1071 | * functionality. | |
1072 | */ | |
d339b133 RC |
1073 | void igb_ptp_init(struct igb_adapter *adapter) |
1074 | { | |
1075 | struct e1000_hw *hw = &adapter->hw; | |
201987e3 | 1076 | struct net_device *netdev = adapter->netdev; |
720db4ff | 1077 | int i; |
d339b133 RC |
1078 | |
1079 | switch (hw->mac.type) { | |
e57b8bdb MV |
1080 | case e1000_82576: |
1081 | snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); | |
1082 | adapter->ptp_caps.owner = THIS_MODULE; | |
75517d92 | 1083 | adapter->ptp_caps.max_adj = 999999881; |
e57b8bdb MV |
1084 | adapter->ptp_caps.n_ext_ts = 0; |
1085 | adapter->ptp_caps.pps = 0; | |
1086 | adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576; | |
1087 | adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; | |
d4c496fe RC |
1088 | adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576; |
1089 | adapter->ptp_caps.settime64 = igb_ptp_settime_82576; | |
102be52f | 1090 | adapter->ptp_caps.enable = igb_ptp_feature_enable; |
e57b8bdb | 1091 | adapter->cc.read = igb_ptp_read_82576; |
b57c8940 | 1092 | adapter->cc.mask = CYCLECOUNTER_MASK(64); |
e57b8bdb MV |
1093 | adapter->cc.mult = 1; |
1094 | adapter->cc.shift = IGB_82576_TSYNC_SHIFT; | |
63737166 | 1095 | adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK; |
e57b8bdb | 1096 | break; |
d339b133 | 1097 | case e1000_82580: |
ceb5f13b | 1098 | case e1000_i354: |
e57b8bdb | 1099 | case e1000_i350: |
201987e3 | 1100 | snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); |
a79f4f88 | 1101 | adapter->ptp_caps.owner = THIS_MODULE; |
a79f4f88 MV |
1102 | adapter->ptp_caps.max_adj = 62499999; |
1103 | adapter->ptp_caps.n_ext_ts = 0; | |
1104 | adapter->ptp_caps.pps = 0; | |
1105 | adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; | |
e57b8bdb | 1106 | adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; |
d4c496fe RC |
1107 | adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576; |
1108 | adapter->ptp_caps.settime64 = igb_ptp_settime_82576; | |
102be52f | 1109 | adapter->ptp_caps.enable = igb_ptp_feature_enable; |
a79f4f88 | 1110 | adapter->cc.read = igb_ptp_read_82580; |
b57c8940 | 1111 | adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580); |
a79f4f88 MV |
1112 | adapter->cc.mult = 1; |
1113 | adapter->cc.shift = 0; | |
63737166 | 1114 | adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK; |
d339b133 | 1115 | break; |
e57b8bdb MV |
1116 | case e1000_i210: |
1117 | case e1000_i211: | |
720db4ff RC |
1118 | for (i = 0; i < IGB_N_SDP; i++) { |
1119 | struct ptp_pin_desc *ppd = &adapter->sdp_config[i]; | |
1120 | ||
1121 | snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i); | |
1122 | ppd->index = i; | |
1123 | ppd->func = PTP_PF_NONE; | |
1124 | } | |
201987e3 | 1125 | snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); |
a79f4f88 | 1126 | adapter->ptp_caps.owner = THIS_MODULE; |
e57b8bdb | 1127 | adapter->ptp_caps.max_adj = 62499999; |
720db4ff RC |
1128 | adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS; |
1129 | adapter->ptp_caps.n_per_out = IGB_N_PEROUT; | |
1130 | adapter->ptp_caps.n_pins = IGB_N_SDP; | |
00c65578 | 1131 | adapter->ptp_caps.pps = 1; |
720db4ff | 1132 | adapter->ptp_caps.pin_config = adapter->sdp_config; |
e57b8bdb MV |
1133 | adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; |
1134 | adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210; | |
d4c496fe RC |
1135 | adapter->ptp_caps.gettime64 = igb_ptp_gettime_i210; |
1136 | adapter->ptp_caps.settime64 = igb_ptp_settime_i210; | |
00c65578 | 1137 | adapter->ptp_caps.enable = igb_ptp_feature_enable_i210; |
720db4ff | 1138 | adapter->ptp_caps.verify = igb_ptp_verify_pin; |
d339b133 | 1139 | break; |
d339b133 RC |
1140 | default: |
1141 | adapter->ptp_clock = NULL; | |
1142 | return; | |
1143 | } | |
1144 | ||
e57b8bdb MV |
1145 | spin_lock_init(&adapter->tmreg_lock); |
1146 | INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); | |
d339b133 | 1147 | |
4f3ce71b | 1148 | if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) |
e57b8bdb MV |
1149 | INIT_DELAYED_WORK(&adapter->ptp_overflow_work, |
1150 | igb_ptp_overflow_check); | |
1f6e8178 | 1151 | |
9f62ecf4 JK |
1152 | adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; |
1153 | adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; | |
1154 | ||
4f3ce71b JK |
1155 | igb_ptp_reset(adapter); |
1156 | ||
1ef76158 RC |
1157 | adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, |
1158 | &adapter->pdev->dev); | |
d339b133 RC |
1159 | if (IS_ERR(adapter->ptp_clock)) { |
1160 | adapter->ptp_clock = NULL; | |
1161 | dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n"); | |
1f6e8178 | 1162 | } else { |
d339b133 RC |
1163 | dev_info(&adapter->pdev->dev, "added PHC on %s\n", |
1164 | adapter->netdev->name); | |
462f1188 | 1165 | adapter->ptp_flags |= IGB_PTP_ENABLED; |
1f6e8178 | 1166 | } |
d339b133 RC |
1167 | } |
1168 | ||
a79f4f88 | 1169 | /** |
e3f2350d JK |
1170 | * igb_ptp_suspend - Disable PTP work items and prepare for suspend |
1171 | * @adapter: Board private structure | |
a79f4f88 | 1172 | * |
e3f2350d JK |
1173 | * This function stops the overflow check work and PTP Tx timestamp work, and |
1174 | * will prepare the device for OS suspend. | |
1175 | */ | |
1176 | void igb_ptp_suspend(struct igb_adapter *adapter) | |
d339b133 | 1177 | { |
63737166 | 1178 | if (!(adapter->ptp_flags & IGB_PTP_ENABLED)) |
d3eef8c8 | 1179 | return; |
63737166 JK |
1180 | |
1181 | if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) | |
1182 | cancel_delayed_work_sync(&adapter->ptp_overflow_work); | |
d339b133 | 1183 | |
1f6e8178 | 1184 | cancel_work_sync(&adapter->ptp_tx_work); |
badc26dd MV |
1185 | if (adapter->ptp_tx_skb) { |
1186 | dev_kfree_skb_any(adapter->ptp_tx_skb); | |
1187 | adapter->ptp_tx_skb = NULL; | |
ed4420a3 | 1188 | clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); |
badc26dd | 1189 | } |
e3f2350d JK |
1190 | } |
1191 | ||
1192 | /** | |
1193 | * igb_ptp_stop - Disable PTP device and stop the overflow check. | |
1194 | * @adapter: Board private structure. | |
1195 | * | |
1196 | * This function stops the PTP support and cancels the delayed work. | |
1197 | **/ | |
1198 | void igb_ptp_stop(struct igb_adapter *adapter) | |
1199 | { | |
1200 | igb_ptp_suspend(adapter); | |
1f6e8178 | 1201 | |
d339b133 RC |
1202 | if (adapter->ptp_clock) { |
1203 | ptp_clock_unregister(adapter->ptp_clock); | |
1204 | dev_info(&adapter->pdev->dev, "removed PHC on %s\n", | |
1205 | adapter->netdev->name); | |
462f1188 | 1206 | adapter->ptp_flags &= ~IGB_PTP_ENABLED; |
d339b133 RC |
1207 | } |
1208 | } | |
1f6e8178 MV |
1209 | |
1210 | /** | |
1211 | * igb_ptp_reset - Re-enable the adapter for PTP following a reset. | |
1212 | * @adapter: Board private structure. | |
1213 | * | |
1214 | * This function handles the reset work required to re-enable the PTP device. | |
1215 | **/ | |
1216 | void igb_ptp_reset(struct igb_adapter *adapter) | |
1217 | { | |
1218 | struct e1000_hw *hw = &adapter->hw; | |
8298c1ec | 1219 | unsigned long flags; |
1f6e8178 | 1220 | |
6ab5f7b2 | 1221 | /* reset the tstamp_config */ |
9f62ecf4 | 1222 | igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config); |
6ab5f7b2 | 1223 | |
8298c1ec RC |
1224 | spin_lock_irqsave(&adapter->tmreg_lock, flags); |
1225 | ||
1f6e8178 MV |
1226 | switch (adapter->hw.mac.type) { |
1227 | case e1000_82576: | |
1228 | /* Dial the nominal frequency. */ | |
1229 | wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); | |
1230 | break; | |
1231 | case e1000_82580: | |
ceb5f13b | 1232 | case e1000_i354: |
1f6e8178 MV |
1233 | case e1000_i350: |
1234 | case e1000_i210: | |
1235 | case e1000_i211: | |
1f6e8178 | 1236 | wr32(E1000_TSAUXC, 0x0); |
720db4ff | 1237 | wr32(E1000_TSSDP, 0x0); |
0c375ac1 | 1238 | wr32(E1000_TSIM, TSYNC_INTERRUPTS); |
1f6e8178 MV |
1239 | wr32(E1000_IMS, E1000_IMS_TS); |
1240 | break; | |
1241 | default: | |
1242 | /* No work to do. */ | |
8298c1ec | 1243 | goto out; |
1f6e8178 MV |
1244 | } |
1245 | ||
e57b8bdb MV |
1246 | /* Re-initialize the timer. */ |
1247 | if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { | |
d4c496fe | 1248 | struct timespec64 ts = ktime_to_timespec64(ktime_get_real()); |
e57b8bdb | 1249 | |
8298c1ec | 1250 | igb_ptp_write_i210(adapter, &ts); |
e57b8bdb MV |
1251 | } else { |
1252 | timecounter_init(&adapter->tc, &adapter->cc, | |
1253 | ktime_to_ns(ktime_get_real())); | |
1254 | } | |
8298c1ec RC |
1255 | out: |
1256 | spin_unlock_irqrestore(&adapter->tmreg_lock, flags); | |
4f3ce71b JK |
1257 | |
1258 | wrfl(); | |
1259 | ||
1260 | if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) | |
1261 | schedule_delayed_work(&adapter->ptp_overflow_work, | |
1262 | IGB_SYSTIM_OVERFLOW_PERIOD); | |
1f6e8178 | 1263 | } |