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ixgbe: create conversion functions from link_status to bus/speed
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_common.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
434c5e39 4 Copyright(c) 1999 - 2013 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
ccffad25 31#include <linux/netdevice.h>
9a799d71 32
11afc1b1 33#include "ixgbe.h"
9a799d71
AK		 34#include "ixgbe_common.h"
35#include "ixgbe_phy.h"
36
c44ade9e 37static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 38static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
39static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
c44ade9e
JB		 40static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
41static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
43 u16 count);
44static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
45static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
46static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
9a799d71 48
9a799d71 49static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
eb9c3e3e 50static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
68c7005d
ET		 51static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
52 u16 words, u16 *data);
53static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
54 u16 words, u16 *data);
55static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
56 u16 offset);
ff9d1a5a 57static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
9a799d71 58
67a79df2
AD		 59/**
60 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
61 * control
62 * @hw: pointer to hardware structure
63 *
64 * There are several phys that do not support autoneg flow control. This
65 * function check the device id to see if the associated phy supports
66 * autoneg flow control.
67 **/
db2adc2d 68s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
67a79df2
AD		 69{
70
71 switch (hw->device_id) {
72 case IXGBE_DEV_ID_X540T:
df376f0d 73 case IXGBE_DEV_ID_X540T1:
67a79df2
AD		 74 case IXGBE_DEV_ID_82599_T3_LOM:
75 return 0;
76 default:
77 return IXGBE_ERR_FC_NOT_SUPPORTED;
78 }
79}
80
81/**
82 * ixgbe_setup_fc - Set up flow control
83 * @hw: pointer to hardware structure
84 *
85 * Called at init time to set up flow control.
86 **/
041441d0 87static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
67a79df2
AD		 88{
89 s32 ret_val = 0;
90 u32 reg = 0, reg_bp = 0;
91 u16 reg_cu = 0;
d7bbcd32 92 bool got_lock = false;
67a79df2 93
67a79df2
AD		 94 /*
95 * Validate the requested mode. Strict IEEE mode does not allow
96 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
97 */
98 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
99 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
100 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
101 goto out;
102 }
103
104 /*
105 * 10gig parts do not have a word in the EEPROM to determine the
106 * default flow control setting, so we explicitly set it to full.
107 */
108 if (hw->fc.requested_mode == ixgbe_fc_default)
109 hw->fc.requested_mode = ixgbe_fc_full;
110
111 /*
112 * Set up the 1G and 10G flow control advertisement registers so the
113 * HW will be able to do fc autoneg once the cable is plugged in. If
114 * we link at 10G, the 1G advertisement is harmless and vice versa.
115 */
67a79df2
AD		 116 switch (hw->phy.media_type) {
117 case ixgbe_media_type_fiber:
118 case ixgbe_media_type_backplane:
119 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
120 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
121 break;
67a79df2
AD		 122 case ixgbe_media_type_copper:
123 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
124 MDIO_MMD_AN, &reg_cu);
125 break;
67a79df2 126 default:
041441d0 127 break;
67a79df2
AD		 128 }
129
130 /*
131 * The possible values of fc.requested_mode are:
132 * 0: Flow control is completely disabled
133 * 1: Rx flow control is enabled (we can receive pause frames,
134 * but not send pause frames).
135 * 2: Tx flow control is enabled (we can send pause frames but
136 * we do not support receiving pause frames).
137 * 3: Both Rx and Tx flow control (symmetric) are enabled.
67a79df2
AD		 138 * other: Invalid.
139 */
140 switch (hw->fc.requested_mode) {
141 case ixgbe_fc_none:
142 /* Flow control completely disabled by software override. */
143 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
144 if (hw->phy.media_type == ixgbe_media_type_backplane)
145 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
146 IXGBE_AUTOC_ASM_PAUSE);
147 else if (hw->phy.media_type == ixgbe_media_type_copper)
148 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
149 break;
67a79df2
AD		 150 case ixgbe_fc_tx_pause:
151 /*
152 * Tx Flow control is enabled, and Rx Flow control is
153 * disabled by software override.
154 */
041441d0
AD		 155 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
156 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
67a79df2 157 if (hw->phy.media_type == ixgbe_media_type_backplane) {
041441d0
AD		 158 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
159 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
67a79df2 160 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
041441d0
AD		 161 reg_cu |= IXGBE_TAF_ASM_PAUSE;
162 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
67a79df2
AD		 163 }
164 break;
041441d0
AD		 165 case ixgbe_fc_rx_pause:
166 /*
167 * Rx Flow control is enabled and Tx Flow control is
168 * disabled by software override. Since there really
169 * isn't a way to advertise that we are capable of RX
170 * Pause ONLY, we will advertise that we support both
171 * symmetric and asymmetric Rx PAUSE, as such we fall
172 * through to the fc_full statement. Later, we will
173 * disable the adapter's ability to send PAUSE frames.
174 */
67a79df2
AD		 175 case ixgbe_fc_full:
176 /* Flow control (both Rx and Tx) is enabled by SW override. */
041441d0 177 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
67a79df2 178 if (hw->phy.media_type == ixgbe_media_type_backplane)
041441d0
AD		 179 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
180 IXGBE_AUTOC_ASM_PAUSE;
67a79df2 181 else if (hw->phy.media_type == ixgbe_media_type_copper)
041441d0 182 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
67a79df2 183 break;
67a79df2
AD		 184 default:
185 hw_dbg(hw, "Flow control param set incorrectly\n");
186 ret_val = IXGBE_ERR_CONFIG;
187 goto out;
188 break;
189 }
190
191 if (hw->mac.type != ixgbe_mac_X540) {
192 /*
193 * Enable auto-negotiation between the MAC & PHY;
194 * the MAC will advertise clause 37 flow control.
195 */
196 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
197 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
198
199 /* Disable AN timeout */
200 if (hw->fc.strict_ieee)
201 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
202
203 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
204 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
205 }
206
207 /*
208 * AUTOC restart handles negotiation of 1G and 10G on backplane
209 * and copper. There is no need to set the PCS1GCTL register.
210 *
211 */
212 if (hw->phy.media_type == ixgbe_media_type_backplane) {
d7bbcd32
DS		 213 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
214 * LESM is on, likewise reset_pipeline requries the lock as
215 * it also writes AUTOC.
216 */
217 if ((hw->mac.type == ixgbe_mac_82599EB) &&
218 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
219 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
220 IXGBE_GSSR_MAC_CSR_SM);
221 if (ret_val)
222 goto out;
223
224 got_lock = true;
225 }
226
67a79df2 227 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
d7bbcd32
DS		 228
229 if (hw->mac.type == ixgbe_mac_82599EB)
230 ixgbe_reset_pipeline_82599(hw);
231
232 if (got_lock)
233 hw->mac.ops.release_swfw_sync(hw,
234 IXGBE_GSSR_MAC_CSR_SM);
235
67a79df2
AD		 236 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
237 (ixgbe_device_supports_autoneg_fc(hw) == 0)) {
238 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
239 MDIO_MMD_AN, reg_cu);
240 }
241
242 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
243out:
244 return ret_val;
245}
246
9a799d71 247/**
c44ade9e 248 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
9a799d71
AK		 249 * @hw: pointer to hardware structure
250 *
251 * Starts the hardware by filling the bus info structure and media type, clears
252 * all on chip counters, initializes receive address registers, multicast
253 * table, VLAN filter table, calls routine to set up link and flow control
254 * settings, and leaves transmit and receive units disabled and uninitialized
255 **/
c44ade9e 256s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
9a799d71
AK		 257{
258 u32 ctrl_ext;
259
260 /* Set the media type */
261 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
262
263 /* Identify the PHY */
c44ade9e 264 hw->phy.ops.identify(hw);
9a799d71 265
9a799d71 266 /* Clear the VLAN filter table */
c44ade9e 267 hw->mac.ops.clear_vfta(hw);
9a799d71 268
9a799d71 269 /* Clear statistics registers */
c44ade9e 270 hw->mac.ops.clear_hw_cntrs(hw);
9a799d71
AK		 271
272 /* Set No Snoop Disable */
273 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
274 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
275 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3957d63d 276 IXGBE_WRITE_FLUSH(hw);
9a799d71 277
620fa036 278 /* Setup flow control */
041441d0 279 ixgbe_setup_fc(hw);
620fa036 280
9a799d71
AK		 281 /* Clear adapter stopped flag */
282 hw->adapter_stopped = false;
283
284 return 0;
285}
286
7184b7cf
ET		 287/**
288 * ixgbe_start_hw_gen2 - Init sequence for common device family
289 * @hw: pointer to hw structure
290 *
291 * Performs the init sequence common to the second generation
292 * of 10 GbE devices.
293 * Devices in the second generation:
294 * 82599
295 * X540
296 **/
297s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
298{
299 u32 i;
3d5c5207 300 u32 regval;
7184b7cf
ET		 301
302 /* Clear the rate limiters */
303 for (i = 0; i < hw->mac.max_tx_queues; i++) {
304 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
305 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
306 }
307 IXGBE_WRITE_FLUSH(hw);
308
3d5c5207
ET		 309 /* Disable relaxed ordering */
310 for (i = 0; i < hw->mac.max_tx_queues; i++) {
311 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
bdda1a61 312 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3d5c5207
ET		 313 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
314 }
315
316 for (i = 0; i < hw->mac.max_rx_queues; i++) {
317 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
bdda1a61
AD		 318 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
319 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
3d5c5207
ET		 320 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
321 }
322
7184b7cf
ET		 323 return 0;
324}
325
9a799d71 326/**
c44ade9e 327 * ixgbe_init_hw_generic - Generic hardware initialization
9a799d71
AK		 328 * @hw: pointer to hardware structure
329 *
c44ade9e 330 * Initialize the hardware by resetting the hardware, filling the bus info
9a799d71
AK		 331 * structure and media type, clears all on chip counters, initializes receive
332 * address registers, multicast table, VLAN filter table, calls routine to set
333 * up link and flow control settings, and leaves transmit and receive units
334 * disabled and uninitialized
335 **/
c44ade9e 336s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
9a799d71 337{
794caeb2
PWJ		 338 s32 status;
339
9a799d71 340 /* Reset the hardware */
794caeb2 341 status = hw->mac.ops.reset_hw(hw);
9a799d71 342
794caeb2
PWJ		 343 if (status == 0) {
344 /* Start the HW */
345 status = hw->mac.ops.start_hw(hw);
346 }
9a799d71 347
794caeb2 348 return status;
9a799d71
AK		 349}
350
351/**
c44ade9e 352 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
9a799d71
AK		 353 * @hw: pointer to hardware structure
354 *
355 * Clears all hardware statistics counters by reading them from the hardware
356 * Statistics counters are clear on read.
357 **/
c44ade9e 358s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 359{
360 u16 i = 0;
361
362 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
363 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
364 IXGBE_READ_REG(hw, IXGBE_ERRBC);
365 IXGBE_READ_REG(hw, IXGBE_MSPDC);
366 for (i = 0; i < 8; i++)
367 IXGBE_READ_REG(hw, IXGBE_MPC(i));
368
369 IXGBE_READ_REG(hw, IXGBE_MLFC);
370 IXGBE_READ_REG(hw, IXGBE_MRFC);
371 IXGBE_READ_REG(hw, IXGBE_RLEC);
372 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
9a799d71 373 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
667c7565
ET		 374 if (hw->mac.type >= ixgbe_mac_82599EB) {
375 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
376 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
377 } else {
378 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
379 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
380 }
9a799d71
AK		 381
382 for (i = 0; i < 8; i++) {
383 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
9a799d71 384 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
667c7565
ET		 385 if (hw->mac.type >= ixgbe_mac_82599EB) {
386 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
387 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
388 } else {
389 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
390 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
391 }
9a799d71 392 }
667c7565
ET		 393 if (hw->mac.type >= ixgbe_mac_82599EB)
394 for (i = 0; i < 8; i++)
395 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
9a799d71
AK		 396 IXGBE_READ_REG(hw, IXGBE_PRC64);
397 IXGBE_READ_REG(hw, IXGBE_PRC127);
398 IXGBE_READ_REG(hw, IXGBE_PRC255);
399 IXGBE_READ_REG(hw, IXGBE_PRC511);
400 IXGBE_READ_REG(hw, IXGBE_PRC1023);
401 IXGBE_READ_REG(hw, IXGBE_PRC1522);
402 IXGBE_READ_REG(hw, IXGBE_GPRC);
403 IXGBE_READ_REG(hw, IXGBE_BPRC);
404 IXGBE_READ_REG(hw, IXGBE_MPRC);
405 IXGBE_READ_REG(hw, IXGBE_GPTC);
406 IXGBE_READ_REG(hw, IXGBE_GORCL);
407 IXGBE_READ_REG(hw, IXGBE_GORCH);
408 IXGBE_READ_REG(hw, IXGBE_GOTCL);
409 IXGBE_READ_REG(hw, IXGBE_GOTCH);
f3116f62
ET		 410 if (hw->mac.type == ixgbe_mac_82598EB)
411 for (i = 0; i < 8; i++)
412 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
9a799d71
AK		 413 IXGBE_READ_REG(hw, IXGBE_RUC);
414 IXGBE_READ_REG(hw, IXGBE_RFC);
415 IXGBE_READ_REG(hw, IXGBE_ROC);
416 IXGBE_READ_REG(hw, IXGBE_RJC);
417 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
418 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
419 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
420 IXGBE_READ_REG(hw, IXGBE_TORL);
421 IXGBE_READ_REG(hw, IXGBE_TORH);
422 IXGBE_READ_REG(hw, IXGBE_TPR);
423 IXGBE_READ_REG(hw, IXGBE_TPT);
424 IXGBE_READ_REG(hw, IXGBE_PTC64);
425 IXGBE_READ_REG(hw, IXGBE_PTC127);
426 IXGBE_READ_REG(hw, IXGBE_PTC255);
427 IXGBE_READ_REG(hw, IXGBE_PTC511);
428 IXGBE_READ_REG(hw, IXGBE_PTC1023);
429 IXGBE_READ_REG(hw, IXGBE_PTC1522);
430 IXGBE_READ_REG(hw, IXGBE_MPTC);
431 IXGBE_READ_REG(hw, IXGBE_BPTC);
432 for (i = 0; i < 16; i++) {
433 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
9a799d71 434 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
667c7565
ET		 435 if (hw->mac.type >= ixgbe_mac_82599EB) {
436 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
437 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
438 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
439 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
440 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
441 } else {
442 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
443 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
444 }
9a799d71
AK		 445 }
446
a3aeea0e
ET		 447 if (hw->mac.type == ixgbe_mac_X540) {
448 if (hw->phy.id == 0)
449 hw->phy.ops.identify(hw);
c1085b10
ET		 450 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);
451 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i);
452 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i);
453 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i);
a3aeea0e
ET		 454 }
455
9a799d71
AK		 456 return 0;
457}
458
459/**
289700db 460 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
c44ade9e 461 * @hw: pointer to hardware structure
289700db
DS		 462 * @pba_num: stores the part number string from the EEPROM
463 * @pba_num_size: part number string buffer length
c44ade9e 464 *
289700db 465 * Reads the part number string from the EEPROM.
c44ade9e 466 **/
289700db
DS		 467s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
468 u32 pba_num_size)
c44ade9e
JB		 469{
470 s32 ret_val;
471 u16 data;
289700db
DS		 472 u16 pba_ptr;
473 u16 offset;
474 u16 length;
475
476 if (pba_num == NULL) {
477 hw_dbg(hw, "PBA string buffer was null\n");
478 return IXGBE_ERR_INVALID_ARGUMENT;
479 }
c44ade9e
JB		 480
481 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
482 if (ret_val) {
483 hw_dbg(hw, "NVM Read Error\n");
484 return ret_val;
485 }
c44ade9e 486
289700db 487 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
c44ade9e
JB		 488 if (ret_val) {
489 hw_dbg(hw, "NVM Read Error\n");
490 return ret_val;
491 }
289700db
DS		 492
493 /*
494 * if data is not ptr guard the PBA must be in legacy format which
495 * means pba_ptr is actually our second data word for the PBA number
496 * and we can decode it into an ascii string
497 */
498 if (data != IXGBE_PBANUM_PTR_GUARD) {
499 hw_dbg(hw, "NVM PBA number is not stored as string\n");
500
501 /* we will need 11 characters to store the PBA */
502 if (pba_num_size < 11) {
503 hw_dbg(hw, "PBA string buffer too small\n");
504 return IXGBE_ERR_NO_SPACE;
505 }
506
507 /* extract hex string from data and pba_ptr */
508 pba_num[0] = (data >> 12) & 0xF;
509 pba_num[1] = (data >> 8) & 0xF;
510 pba_num[2] = (data >> 4) & 0xF;
511 pba_num[3] = data & 0xF;
512 pba_num[4] = (pba_ptr >> 12) & 0xF;
513 pba_num[5] = (pba_ptr >> 8) & 0xF;
514 pba_num[6] = '-';
515 pba_num[7] = 0;
516 pba_num[8] = (pba_ptr >> 4) & 0xF;
517 pba_num[9] = pba_ptr & 0xF;
518
519 /* put a null character on the end of our string */
520 pba_num[10] = '\0';
521
522 /* switch all the data but the '-' to hex char */
523 for (offset = 0; offset < 10; offset++) {
524 if (pba_num[offset] < 0xA)
525 pba_num[offset] += '0';
526 else if (pba_num[offset] < 0x10)
527 pba_num[offset] += 'A' - 0xA;
528 }
529
530 return 0;
531 }
532
533 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
534 if (ret_val) {
535 hw_dbg(hw, "NVM Read Error\n");
536 return ret_val;
537 }
538
539 if (length == 0xFFFF || length == 0) {
540 hw_dbg(hw, "NVM PBA number section invalid length\n");
541 return IXGBE_ERR_PBA_SECTION;
542 }
543
544 /* check if pba_num buffer is big enough */
545 if (pba_num_size < (((u32)length * 2) - 1)) {
546 hw_dbg(hw, "PBA string buffer too small\n");
547 return IXGBE_ERR_NO_SPACE;
548 }
549
550 /* trim pba length from start of string */
551 pba_ptr++;
552 length--;
553
554 for (offset = 0; offset < length; offset++) {
555 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
556 if (ret_val) {
557 hw_dbg(hw, "NVM Read Error\n");
558 return ret_val;
559 }
560 pba_num[offset * 2] = (u8)(data >> 8);
561 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
562 }
563 pba_num[offset * 2] = '\0';
c44ade9e
JB		 564
565 return 0;
566}
567
568/**
569 * ixgbe_get_mac_addr_generic - Generic get MAC address
9a799d71
AK		 570 * @hw: pointer to hardware structure
571 * @mac_addr: Adapter MAC address
572 *
573 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
574 * A reset of the adapter must be performed prior to calling this function
575 * in order for the MAC address to have been loaded from the EEPROM into RAR0
576 **/
c44ade9e 577s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
9a799d71
AK		 578{
579 u32 rar_high;
580 u32 rar_low;
581 u16 i;
582
583 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
584 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
585
586 for (i = 0; i < 4; i++)
587 mac_addr[i] = (u8)(rar_low >> (i*8));
588
589 for (i = 0; i < 2; i++)
590 mac_addr[i+4] = (u8)(rar_high >> (i*8));
591
592 return 0;
593}
594
ef1889d5
JK		 595enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status)
596{
597 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
598 case IXGBE_PCI_LINK_WIDTH_1:
599 return ixgbe_bus_width_pcie_x1;
600 case IXGBE_PCI_LINK_WIDTH_2:
601 return ixgbe_bus_width_pcie_x2;
602 case IXGBE_PCI_LINK_WIDTH_4:
603 return ixgbe_bus_width_pcie_x4;
604 case IXGBE_PCI_LINK_WIDTH_8:
605 return ixgbe_bus_width_pcie_x8;
606 default:
607 return ixgbe_bus_width_unknown;
608 }
609}
610
611enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status)
612{
613 switch (link_status & IXGBE_PCI_LINK_SPEED) {
614 case IXGBE_PCI_LINK_SPEED_2500:
615 return ixgbe_bus_speed_2500;
616 case IXGBE_PCI_LINK_SPEED_5000:
617 return ixgbe_bus_speed_5000;
618 case IXGBE_PCI_LINK_SPEED_8000:
619 return ixgbe_bus_speed_8000;
620 default:
621 return ixgbe_bus_speed_unknown;
622 }
623}
624
11afc1b1
PW		 625/**
626 * ixgbe_get_bus_info_generic - Generic set PCI bus info
627 * @hw: pointer to hardware structure
628 *
629 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
630 **/
631s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
632{
633 struct ixgbe_adapter *adapter = hw->back;
634 struct ixgbe_mac_info *mac = &hw->mac;
635 u16 link_status;
636
637 hw->bus.type = ixgbe_bus_type_pci_express;
638
639 /* Get the negotiated link width and speed from PCI config space */
640 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
641 &link_status);
642
ef1889d5
JK		 643 hw->bus.width = ixgbe_convert_bus_width(link_status);
644 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
11afc1b1
PW		 645
646 mac->ops.set_lan_id(hw);
647
648 return 0;
649}
650
651/**
652 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
653 * @hw: pointer to the HW structure
654 *
655 * Determines the LAN function id by reading memory-mapped registers
656 * and swaps the port value if requested.
657 **/
658void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
659{
660 struct ixgbe_bus_info *bus = &hw->bus;
661 u32 reg;
662
663 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
664 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
665 bus->lan_id = bus->func;
666
667 /* check for a port swap */
668 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
669 if (reg & IXGBE_FACTPS_LFS)
670 bus->func ^= 0x1;
671}
672
9a799d71 673/**
c44ade9e 674 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
9a799d71
AK		 675 * @hw: pointer to hardware structure
676 *
677 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
678 * disables transmit and receive units. The adapter_stopped flag is used by
679 * the shared code and drivers to determine if the adapter is in a stopped
680 * state and should not touch the hardware.
681 **/
c44ade9e 682s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
9a799d71 683{
9a799d71
AK		 684 u32 reg_val;
685 u16 i;
686
687 /*
688 * Set the adapter_stopped flag so other driver functions stop touching
689 * the hardware
690 */
691 hw->adapter_stopped = true;
692
693 /* Disable the receive unit */
ff9d1a5a 694 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
9a799d71 695
ff9d1a5a 696 /* Clear interrupt mask to stop interrupts from being generated */
9a799d71
AK		 697 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
698
ff9d1a5a 699 /* Clear any pending interrupts, flush previous writes */
9a799d71
AK		 700 IXGBE_READ_REG(hw, IXGBE_EICR);
701
702 /* Disable the transmit unit. Each queue must be disabled. */
ff9d1a5a
ET		 703 for (i = 0; i < hw->mac.max_tx_queues; i++)
704 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
705
706 /* Disable the receive unit by stopping each queue */
707 for (i = 0; i < hw->mac.max_rx_queues; i++) {
708 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
709 reg_val &= ~IXGBE_RXDCTL_ENABLE;
710 reg_val |= IXGBE_RXDCTL_SWFLSH;
711 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
9a799d71
AK		 712 }
713
ff9d1a5a
ET		 714 /* flush all queues disables */
715 IXGBE_WRITE_FLUSH(hw);
716 usleep_range(1000, 2000);
717
c44ade9e
JB		 718 /*
719 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
720 * access and verify no pending requests
721 */
ff9d1a5a 722 return ixgbe_disable_pcie_master(hw);
9a799d71
AK		 723}
724
725/**
c44ade9e 726 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
9a799d71
AK		 727 * @hw: pointer to hardware structure
728 * @index: led number to turn on
729 **/
c44ade9e 730s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 731{
732 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
733
734 /* To turn on the LED, set mode to ON. */
735 led_reg &= ~IXGBE_LED_MODE_MASK(index);
736 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
737 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 738 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 739
740 return 0;
741}
742
743/**
c44ade9e 744 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
9a799d71
AK		 745 * @hw: pointer to hardware structure
746 * @index: led number to turn off
747 **/
c44ade9e 748s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 749{
750 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
751
752 /* To turn off the LED, set mode to OFF. */
753 led_reg &= ~IXGBE_LED_MODE_MASK(index);
754 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
755 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 756 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 757
758 return 0;
759}
760
9a799d71 761/**
c44ade9e 762 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
9a799d71
AK		 763 * @hw: pointer to hardware structure
764 *
765 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
766 * ixgbe_hw struct in order to set up EEPROM access.
767 **/
c44ade9e 768s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
9a799d71
AK		 769{
770 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
771 u32 eec;
772 u16 eeprom_size;
773
774 if (eeprom->type == ixgbe_eeprom_uninitialized) {
775 eeprom->type = ixgbe_eeprom_none;
c44ade9e
JB		 776 /* Set default semaphore delay to 10ms which is a well
777 * tested value */
778 eeprom->semaphore_delay = 10;
68c7005d
ET		 779 /* Clear EEPROM page size, it will be initialized as needed */
780 eeprom->word_page_size = 0;
9a799d71
AK		 781
782 /*
783 * Check for EEPROM present first.
784 * If not present leave as none
785 */
786 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
787 if (eec & IXGBE_EEC_PRES) {
788 eeprom->type = ixgbe_eeprom_spi;
789
790 /*
791 * SPI EEPROM is assumed here. This code would need to
792 * change if a future EEPROM is not SPI.
793 */
794 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
795 IXGBE_EEC_SIZE_SHIFT);
796 eeprom->word_size = 1 << (eeprom_size +
797 IXGBE_EEPROM_WORD_SIZE_SHIFT);
798 }
799
800 if (eec & IXGBE_EEC_ADDR_SIZE)
801 eeprom->address_bits = 16;
802 else
803 eeprom->address_bits = 8;
804 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
805 "%d\n", eeprom->type, eeprom->word_size,
806 eeprom->address_bits);
807 }
808
809 return 0;
810}
811
11afc1b1 812/**
68c7005d 813 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
11afc1b1 814 * @hw: pointer to hardware structure
68c7005d
ET		 815 * @offset: offset within the EEPROM to write
816 * @words: number of words
817 * @data: 16 bit word(s) to write to EEPROM
11afc1b1 818 *
68c7005d 819 * Reads 16 bit word(s) from EEPROM through bit-bang method
11afc1b1 820 **/
68c7005d
ET		 821s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
822 u16 words, u16 *data)
11afc1b1 823{
68c7005d
ET		 824 s32 status = 0;
825 u16 i, count;
11afc1b1
PW		 826
827 hw->eeprom.ops.init_params(hw);
828
68c7005d
ET		 829 if (words == 0) {
830 status = IXGBE_ERR_INVALID_ARGUMENT;
831 goto out;
832 }
833
834 if (offset + words > hw->eeprom.word_size) {
11afc1b1
PW		 835 status = IXGBE_ERR_EEPROM;
836 goto out;
837 }
838
68c7005d
ET		 839 /*
840 * The EEPROM page size cannot be queried from the chip. We do lazy
841 * initialization. It is worth to do that when we write large buffer.
842 */
843 if ((hw->eeprom.word_page_size == 0) &&
844 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
845 ixgbe_detect_eeprom_page_size_generic(hw, offset);
846
847 /*
848 * We cannot hold synchronization semaphores for too long
849 * to avoid other entity starvation. However it is more efficient
850 * to read in bursts than synchronizing access for each word.
851 */
852 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
853 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
854 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
855 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
856 count, &data[i]);
857
858 if (status != 0)
859 break;
860 }
861
862out:
863 return status;
864}
865
866/**
867 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
868 * @hw: pointer to hardware structure
869 * @offset: offset within the EEPROM to be written to
870 * @words: number of word(s)
871 * @data: 16 bit word(s) to be written to the EEPROM
872 *
873 * If ixgbe_eeprom_update_checksum is not called after this function, the
874 * EEPROM will most likely contain an invalid checksum.
875 **/
876static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
877 u16 words, u16 *data)
878{
879 s32 status;
880 u16 word;
881 u16 page_size;
882 u16 i;
883 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
884
11afc1b1
PW		 885 /* Prepare the EEPROM for writing */
886 status = ixgbe_acquire_eeprom(hw);
887
888 if (status == 0) {
889 if (ixgbe_ready_eeprom(hw) != 0) {
890 ixgbe_release_eeprom(hw);
891 status = IXGBE_ERR_EEPROM;
892 }
893 }
894
895 if (status == 0) {
68c7005d
ET		 896 for (i = 0; i < words; i++) {
897 ixgbe_standby_eeprom(hw);
11afc1b1 898
68c7005d
ET		 899 /* Send the WRITE ENABLE command (8 bit opcode ) */
900 ixgbe_shift_out_eeprom_bits(hw,
901 IXGBE_EEPROM_WREN_OPCODE_SPI,
902 IXGBE_EEPROM_OPCODE_BITS);
11afc1b1 903
68c7005d 904 ixgbe_standby_eeprom(hw);
11afc1b1 905
68c7005d
ET		 906 /*
907 * Some SPI eeproms use the 8th address bit embedded
908 * in the opcode
909 */
910 if ((hw->eeprom.address_bits == 8) &&
911 ((offset + i) >= 128))
912 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
913
914 /* Send the Write command (8-bit opcode + addr) */
915 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
916 IXGBE_EEPROM_OPCODE_BITS);
917 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
918 hw->eeprom.address_bits);
919
920 page_size = hw->eeprom.word_page_size;
921
922 /* Send the data in burst via SPI*/
923 do {
924 word = data[i];
925 word = (word >> 8) | (word << 8);
926 ixgbe_shift_out_eeprom_bits(hw, word, 16);
927
928 if (page_size == 0)
929 break;
930
931 /* do not wrap around page */
932 if (((offset + i) & (page_size - 1)) ==
933 (page_size - 1))
934 break;
935 } while (++i < words);
936
937 ixgbe_standby_eeprom(hw);
938 usleep_range(10000, 20000);
939 }
940 /* Done with writing - release the EEPROM */
941 ixgbe_release_eeprom(hw);
942 }
11afc1b1 943
68c7005d
ET		 944 return status;
945}
946
947/**
948 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
949 * @hw: pointer to hardware structure
950 * @offset: offset within the EEPROM to be written to
951 * @data: 16 bit word to be written to the EEPROM
952 *
953 * If ixgbe_eeprom_update_checksum is not called after this function, the
954 * EEPROM will most likely contain an invalid checksum.
955 **/
956s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
957{
958 s32 status;
11afc1b1 959
68c7005d 960 hw->eeprom.ops.init_params(hw);
11afc1b1 961
68c7005d
ET		 962 if (offset >= hw->eeprom.word_size) {
963 status = IXGBE_ERR_EEPROM;
964 goto out;
11afc1b1
PW		 965 }
966
68c7005d
ET		 967 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
968
11afc1b1
PW		 969out:
970 return status;
971}
972
9a799d71 973/**
68c7005d 974 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
c44ade9e
JB		 975 * @hw: pointer to hardware structure
976 * @offset: offset within the EEPROM to be read
68c7005d
ET		 977 * @words: number of word(s)
978 * @data: read 16 bit words(s) from EEPROM
c44ade9e 979 *
68c7005d 980 * Reads 16 bit word(s) from EEPROM through bit-bang method
c44ade9e 981 **/
68c7005d
ET		 982s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
983 u16 words, u16 *data)
c44ade9e 984{
68c7005d
ET		 985 s32 status = 0;
986 u16 i, count;
c44ade9e
JB		 987
988 hw->eeprom.ops.init_params(hw);
989
68c7005d
ET		 990 if (words == 0) {
991 status = IXGBE_ERR_INVALID_ARGUMENT;
992 goto out;
993 }
994
995 if (offset + words > hw->eeprom.word_size) {
c44ade9e
JB		 996 status = IXGBE_ERR_EEPROM;
997 goto out;
998 }
999
68c7005d
ET		 1000 /*
1001 * We cannot hold synchronization semaphores for too long
1002 * to avoid other entity starvation. However it is more efficient
1003 * to read in bursts than synchronizing access for each word.
1004 */
1005 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1006 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1007 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1008
1009 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1010 count, &data[i]);
1011
1012 if (status != 0)
1013 break;
1014 }
1015
1016out:
1017 return status;
1018}
1019
1020/**
1021 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1022 * @hw: pointer to hardware structure
1023 * @offset: offset within the EEPROM to be read
1024 * @words: number of word(s)
1025 * @data: read 16 bit word(s) from EEPROM
1026 *
1027 * Reads 16 bit word(s) from EEPROM through bit-bang method
1028 **/
1029static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1030 u16 words, u16 *data)
1031{
1032 s32 status;
1033 u16 word_in;
1034 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1035 u16 i;
1036
c44ade9e
JB		 1037 /* Prepare the EEPROM for reading */
1038 status = ixgbe_acquire_eeprom(hw);
1039
1040 if (status == 0) {
1041 if (ixgbe_ready_eeprom(hw) != 0) {
1042 ixgbe_release_eeprom(hw);
1043 status = IXGBE_ERR_EEPROM;
1044 }
1045 }
1046
1047 if (status == 0) {
68c7005d
ET		 1048 for (i = 0; i < words; i++) {
1049 ixgbe_standby_eeprom(hw);
1050 /*
1051 * Some SPI eeproms use the 8th address bit embedded
1052 * in the opcode
1053 */
1054 if ((hw->eeprom.address_bits == 8) &&
1055 ((offset + i) >= 128))
1056 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1057
1058 /* Send the READ command (opcode + addr) */
1059 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1060 IXGBE_EEPROM_OPCODE_BITS);
1061 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1062 hw->eeprom.address_bits);
1063
1064 /* Read the data. */
1065 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1066 data[i] = (word_in >> 8) | (word_in << 8);
1067 }
c44ade9e 1068
68c7005d
ET		 1069 /* End this read operation */
1070 ixgbe_release_eeprom(hw);
1071 }
c44ade9e 1072
68c7005d
ET		 1073 return status;
1074}
c44ade9e 1075
68c7005d
ET		 1076/**
1077 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1078 * @hw: pointer to hardware structure
1079 * @offset: offset within the EEPROM to be read
1080 * @data: read 16 bit value from EEPROM
1081 *
1082 * Reads 16 bit value from EEPROM through bit-bang method
1083 **/
1084s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1085 u16 *data)
1086{
1087 s32 status;
c44ade9e 1088
68c7005d
ET		 1089 hw->eeprom.ops.init_params(hw);
1090
1091 if (offset >= hw->eeprom.word_size) {
1092 status = IXGBE_ERR_EEPROM;
1093 goto out;
c44ade9e
JB		 1094 }
1095
68c7005d
ET		 1096 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1097
c44ade9e
JB		 1098out:
1099 return status;
1100}
1101
1102/**
68c7005d 1103 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
9a799d71 1104 * @hw: pointer to hardware structure
68c7005d
ET		 1105 * @offset: offset of word in the EEPROM to read
1106 * @words: number of word(s)
1107 * @data: 16 bit word(s) from the EEPROM
9a799d71 1108 *
68c7005d 1109 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
9a799d71 1110 **/
68c7005d
ET		 1111s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1112 u16 words, u16 *data)
9a799d71
AK		 1113{
1114 u32 eerd;
68c7005d
ET		 1115 s32 status = 0;
1116 u32 i;
9a799d71 1117
c44ade9e
JB		 1118 hw->eeprom.ops.init_params(hw);
1119
68c7005d
ET		 1120 if (words == 0) {
1121 status = IXGBE_ERR_INVALID_ARGUMENT;
1122 goto out;
1123 }
1124
c44ade9e
JB		 1125 if (offset >= hw->eeprom.word_size) {
1126 status = IXGBE_ERR_EEPROM;
1127 goto out;
1128 }
1129
68c7005d 1130 for (i = 0; i < words; i++) {
d0111575 1131 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
68c7005d 1132 IXGBE_EEPROM_RW_REG_START;
9a799d71 1133
68c7005d
ET		 1134 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1135 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
9a799d71 1136
68c7005d
ET		 1137 if (status == 0) {
1138 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1139 IXGBE_EEPROM_RW_REG_DATA);
1140 } else {
1141 hw_dbg(hw, "Eeprom read timed out\n");
1142 goto out;
1143 }
1144 }
1145out:
1146 return status;
1147}
9a799d71 1148
68c7005d
ET		 1149/**
1150 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1151 * @hw: pointer to hardware structure
1152 * @offset: offset within the EEPROM to be used as a scratch pad
1153 *
1154 * Discover EEPROM page size by writing marching data at given offset.
1155 * This function is called only when we are writing a new large buffer
1156 * at given offset so the data would be overwritten anyway.
1157 **/
1158static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1159 u16 offset)
1160{
1161 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1162 s32 status = 0;
1163 u16 i;
1164
1165 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1166 data[i] = i;
1167
1168 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1169 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1170 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1171 hw->eeprom.word_page_size = 0;
1172 if (status != 0)
1173 goto out;
1174
1175 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1176 if (status != 0)
1177 goto out;
1178
1179 /*
1180 * When writing in burst more than the actual page size
1181 * EEPROM address wraps around current page.
1182 */
1183 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1184
1185 hw_dbg(hw, "Detected EEPROM page size = %d words.",
1186 hw->eeprom.word_page_size);
c44ade9e 1187out:
9a799d71
AK		 1188 return status;
1189}
1190
eb9c3e3e 1191/**
68c7005d
ET		 1192 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1193 * @hw: pointer to hardware structure
1194 * @offset: offset of word in the EEPROM to read
1195 * @data: word read from the EEPROM
1196 *
1197 * Reads a 16 bit word from the EEPROM using the EERD register.
1198 **/
1199s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1200{
1201 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1202}
1203
1204/**
1205 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
eb9c3e3e
ET		 1206 * @hw: pointer to hardware structure
1207 * @offset: offset of word in the EEPROM to write
68c7005d
ET		 1208 * @words: number of words
1209 * @data: word(s) write to the EEPROM
eb9c3e3e 1210 *
68c7005d 1211 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
eb9c3e3e 1212 **/
68c7005d
ET		 1213s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1214 u16 words, u16 *data)
eb9c3e3e
ET		 1215{
1216 u32 eewr;
68c7005d
ET		 1217 s32 status = 0;
1218 u16 i;
eb9c3e3e
ET		 1219
1220 hw->eeprom.ops.init_params(hw);
1221
68c7005d
ET		 1222 if (words == 0) {
1223 status = IXGBE_ERR_INVALID_ARGUMENT;
1224 goto out;
1225 }
1226
eb9c3e3e
ET		 1227 if (offset >= hw->eeprom.word_size) {
1228 status = IXGBE_ERR_EEPROM;
1229 goto out;
1230 }
1231
68c7005d
ET		 1232 for (i = 0; i < words; i++) {
1233 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1234 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1235 IXGBE_EEPROM_RW_REG_START;
eb9c3e3e 1236
68c7005d
ET		 1237 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1238 if (status != 0) {
1239 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1240 goto out;
1241 }
eb9c3e3e 1242
68c7005d 1243 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
eb9c3e3e 1244
68c7005d
ET		 1245 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1246 if (status != 0) {
1247 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1248 goto out;
1249 }
eb9c3e3e
ET		 1250 }
1251
1252out:
1253 return status;
1254}
1255
68c7005d
ET		 1256/**
1257 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1258 * @hw: pointer to hardware structure
1259 * @offset: offset of word in the EEPROM to write
1260 * @data: word write to the EEPROM
1261 *
1262 * Write a 16 bit word to the EEPROM using the EEWR register.
1263 **/
1264s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1265{
1266 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1267}
1268
9a799d71 1269/**
21ce849b 1270 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
9a799d71 1271 * @hw: pointer to hardware structure
21ce849b 1272 * @ee_reg: EEPROM flag for polling
9a799d71 1273 *
21ce849b
MC		 1274 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1275 * read or write is done respectively.
9a799d71 1276 **/
eb9c3e3e 1277static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
9a799d71
AK		 1278{
1279 u32 i;
1280 u32 reg;
1281 s32 status = IXGBE_ERR_EEPROM;
1282
21ce849b
MC		 1283 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1284 if (ee_reg == IXGBE_NVM_POLL_READ)
1285 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1286 else
1287 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1288
1289 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
9a799d71
AK		 1290 status = 0;
1291 break;
1292 }
1293 udelay(5);
1294 }
1295 return status;
1296}
1297
c44ade9e
JB		 1298/**
1299 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1300 * @hw: pointer to hardware structure
1301 *
1302 * Prepares EEPROM for access using bit-bang method. This function should
1303 * be called before issuing a command to the EEPROM.
1304 **/
1305static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1306{
1307 s32 status = 0;
dbf893ee 1308 u32 eec;
c44ade9e
JB		 1309 u32 i;
1310
5e655105 1311 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
c44ade9e
JB		 1312 status = IXGBE_ERR_SWFW_SYNC;
1313
1314 if (status == 0) {
1315 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1316
1317 /* Request EEPROM Access */
1318 eec |= IXGBE_EEC_REQ;
1319 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1320
1321 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1322 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1323 if (eec & IXGBE_EEC_GNT)
1324 break;
1325 udelay(5);
1326 }
1327
1328 /* Release if grant not acquired */
1329 if (!(eec & IXGBE_EEC_GNT)) {
1330 eec &= ~IXGBE_EEC_REQ;
1331 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1332 hw_dbg(hw, "Could not acquire EEPROM grant\n");
1333
5e655105 1334 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
c44ade9e
JB		 1335 status = IXGBE_ERR_EEPROM;
1336 }
c44ade9e 1337
dbf893ee
ET		 1338 /* Setup EEPROM for Read/Write */
1339 if (status == 0) {
1340 /* Clear CS and SK */
1341 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1342 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1343 IXGBE_WRITE_FLUSH(hw);
1344 udelay(1);
1345 }
c44ade9e
JB		 1346 }
1347 return status;
1348}
1349
9a799d71
AK		 1350/**
1351 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1352 * @hw: pointer to hardware structure
1353 *
1354 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1355 **/
1356static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1357{
1358 s32 status = IXGBE_ERR_EEPROM;
dbf893ee 1359 u32 timeout = 2000;
9a799d71
AK		 1360 u32 i;
1361 u32 swsm;
1362
9a799d71
AK		 1363 /* Get SMBI software semaphore between device drivers first */
1364 for (i = 0; i < timeout; i++) {
1365 /*
1366 * If the SMBI bit is 0 when we read it, then the bit will be
1367 * set and we have the semaphore
1368 */
1369 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1370 if (!(swsm & IXGBE_SWSM_SMBI)) {
1371 status = 0;
1372 break;
1373 }
dbf893ee 1374 udelay(50);
9a799d71
AK		 1375 }
1376
51275d37
ET		 1377 if (i == timeout) {
1378 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore "
1379 "not granted.\n");
1380 /*
1381 * this release is particularly important because our attempts
1382 * above to get the semaphore may have succeeded, and if there
1383 * was a timeout, we should unconditionally clear the semaphore
1384 * bits to free the driver to make progress
1385 */
1386 ixgbe_release_eeprom_semaphore(hw);
1387
1388 udelay(50);
1389 /*
1390 * one last try
1391 * If the SMBI bit is 0 when we read it, then the bit will be
1392 * set and we have the semaphore
1393 */
1394 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1395 if (!(swsm & IXGBE_SWSM_SMBI))
1396 status = 0;
1397 }
1398
9a799d71
AK		 1399 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1400 if (status == 0) {
1401 for (i = 0; i < timeout; i++) {
1402 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1403
1404 /* Set the SW EEPROM semaphore bit to request access */
1405 swsm |= IXGBE_SWSM_SWESMBI;
1406 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1407
1408 /*
1409 * If we set the bit successfully then we got the
1410 * semaphore.
1411 */
1412 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1413 if (swsm & IXGBE_SWSM_SWESMBI)
1414 break;
1415
1416 udelay(50);
1417 }
1418
1419 /*
1420 * Release semaphores and return error if SW EEPROM semaphore
1421 * was not granted because we don't have access to the EEPROM
1422 */
1423 if (i >= timeout) {
dbf893ee 1424 hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
b4617240 1425 "not granted.\n");
9a799d71
AK		 1426 ixgbe_release_eeprom_semaphore(hw);
1427 status = IXGBE_ERR_EEPROM;
1428 }
dbf893ee
ET		 1429 } else {
1430 hw_dbg(hw, "Software semaphore SMBI between device drivers "
1431 "not granted.\n");
9a799d71
AK		 1432 }
1433
1434 return status;
1435}
1436
1437/**
1438 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1439 * @hw: pointer to hardware structure
1440 *
1441 * This function clears hardware semaphore bits.
1442 **/
1443static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1444{
1445 u32 swsm;
1446
1447 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1448
1449 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1450 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1451 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
3957d63d 1452 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 1453}
1454
c44ade9e
JB		 1455/**
1456 * ixgbe_ready_eeprom - Polls for EEPROM ready
1457 * @hw: pointer to hardware structure
1458 **/
1459static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1460{
1461 s32 status = 0;
1462 u16 i;
1463 u8 spi_stat_reg;
1464
1465 /*
1466 * Read "Status Register" repeatedly until the LSB is cleared. The
1467 * EEPROM will signal that the command has been completed by clearing
1468 * bit 0 of the internal status register. If it's not cleared within
1469 * 5 milliseconds, then error out.
1470 */
1471 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1472 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1473 IXGBE_EEPROM_OPCODE_BITS);
1474 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1475 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1476 break;
1477
1478 udelay(5);
1479 ixgbe_standby_eeprom(hw);
6403eab1 1480 }
c44ade9e
JB		 1481
1482 /*
1483 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1484 * devices (and only 0-5mSec on 5V devices)
1485 */
1486 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1487 hw_dbg(hw, "SPI EEPROM Status error\n");
1488 status = IXGBE_ERR_EEPROM;
1489 }
1490
1491 return status;
1492}
1493
1494/**
1495 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1496 * @hw: pointer to hardware structure
1497 **/
1498static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1499{
1500 u32 eec;
1501
1502 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1503
1504 /* Toggle CS to flush commands */
1505 eec |= IXGBE_EEC_CS;
1506 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1507 IXGBE_WRITE_FLUSH(hw);
1508 udelay(1);
1509 eec &= ~IXGBE_EEC_CS;
1510 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1511 IXGBE_WRITE_FLUSH(hw);
1512 udelay(1);
1513}
1514
1515/**
1516 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1517 * @hw: pointer to hardware structure
1518 * @data: data to send to the EEPROM
1519 * @count: number of bits to shift out
1520 **/
1521static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1522 u16 count)
1523{
1524 u32 eec;
1525 u32 mask;
1526 u32 i;
1527
1528 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1529
1530 /*
1531 * Mask is used to shift "count" bits of "data" out to the EEPROM
1532 * one bit at a time. Determine the starting bit based on count
1533 */
1534 mask = 0x01 << (count - 1);
1535
1536 for (i = 0; i < count; i++) {
1537 /*
1538 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1539 * "1", and then raising and then lowering the clock (the SK
1540 * bit controls the clock input to the EEPROM). A "0" is
1541 * shifted out to the EEPROM by setting "DI" to "0" and then
1542 * raising and then lowering the clock.
1543 */
1544 if (data & mask)
1545 eec |= IXGBE_EEC_DI;
1546 else
1547 eec &= ~IXGBE_EEC_DI;
1548
1549 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1550 IXGBE_WRITE_FLUSH(hw);
1551
1552 udelay(1);
1553
1554 ixgbe_raise_eeprom_clk(hw, &eec);
1555 ixgbe_lower_eeprom_clk(hw, &eec);
1556
1557 /*
1558 * Shift mask to signify next bit of data to shift in to the
1559 * EEPROM
1560 */
1561 mask = mask >> 1;
6403eab1 1562 }
c44ade9e
JB		 1563
1564 /* We leave the "DI" bit set to "0" when we leave this routine. */
1565 eec &= ~IXGBE_EEC_DI;
1566 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1567 IXGBE_WRITE_FLUSH(hw);
1568}
1569
1570/**
1571 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1572 * @hw: pointer to hardware structure
1573 **/
1574static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1575{
1576 u32 eec;
1577 u32 i;
1578 u16 data = 0;
1579
1580 /*
1581 * In order to read a register from the EEPROM, we need to shift
1582 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1583 * the clock input to the EEPROM (setting the SK bit), and then reading
1584 * the value of the "DO" bit. During this "shifting in" process the
1585 * "DI" bit should always be clear.
1586 */
1587 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1588
1589 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1590
1591 for (i = 0; i < count; i++) {
1592 data = data << 1;
1593 ixgbe_raise_eeprom_clk(hw, &eec);
1594
1595 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1596
1597 eec &= ~(IXGBE_EEC_DI);
1598 if (eec & IXGBE_EEC_DO)
1599 data |= 1;
1600
1601 ixgbe_lower_eeprom_clk(hw, &eec);
1602 }
1603
1604 return data;
1605}
1606
1607/**
1608 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1609 * @hw: pointer to hardware structure
1610 * @eec: EEC register's current value
1611 **/
1612static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1613{
1614 /*
1615 * Raise the clock input to the EEPROM
1616 * (setting the SK bit), then delay
1617 */
1618 *eec = *eec | IXGBE_EEC_SK;
1619 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1620 IXGBE_WRITE_FLUSH(hw);
1621 udelay(1);
1622}
1623
1624/**
1625 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1626 * @hw: pointer to hardware structure
1627 * @eecd: EECD's current value
1628 **/
1629static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1630{
1631 /*
1632 * Lower the clock input to the EEPROM (clearing the SK bit), then
1633 * delay
1634 */
1635 *eec = *eec & ~IXGBE_EEC_SK;
1636 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1637 IXGBE_WRITE_FLUSH(hw);
1638 udelay(1);
1639}
1640
1641/**
1642 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1643 * @hw: pointer to hardware structure
1644 **/
1645static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1646{
1647 u32 eec;
1648
1649 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1650
1651 eec |= IXGBE_EEC_CS; /* Pull CS high */
1652 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1653
1654 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1655 IXGBE_WRITE_FLUSH(hw);
1656
1657 udelay(1);
1658
1659 /* Stop requesting EEPROM access */
1660 eec &= ~IXGBE_EEC_REQ;
1661 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1662
90827996 1663 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
dbf893ee 1664
032b4325
DS		 1665 /*
1666 * Delay before attempt to obtain semaphore again to allow FW
1667 * access. semaphore_delay is in ms we need us for usleep_range
1668 */
1669 usleep_range(hw->eeprom.semaphore_delay * 1000,
1670 hw->eeprom.semaphore_delay * 2000);
c44ade9e
JB		 1671}
1672
9a799d71 1673/**
dbf893ee 1674 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
9a799d71
AK		 1675 * @hw: pointer to hardware structure
1676 **/
a391f1d5 1677u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1678{
1679 u16 i;
1680 u16 j;
1681 u16 checksum = 0;
1682 u16 length = 0;
1683 u16 pointer = 0;
1684 u16 word = 0;
1685
1686 /* Include 0x0-0x3F in the checksum */
1687 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
c44ade9e 1688 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
9a799d71
AK		 1689 hw_dbg(hw, "EEPROM read failed\n");
1690 break;
1691 }
1692 checksum += word;
1693 }
1694
1695 /* Include all data from pointers except for the fw pointer */
1696 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
c44ade9e 1697 hw->eeprom.ops.read(hw, i, &pointer);
9a799d71
AK		 1698
1699 /* Make sure the pointer seems valid */
1700 if (pointer != 0xFFFF && pointer != 0) {
c44ade9e 1701 hw->eeprom.ops.read(hw, pointer, &length);
9a799d71
AK		 1702
1703 if (length != 0xFFFF && length != 0) {
1704 for (j = pointer+1; j <= pointer+length; j++) {
c44ade9e 1705 hw->eeprom.ops.read(hw, j, &word);
9a799d71
AK		 1706 checksum += word;
1707 }
1708 }
1709 }
1710 }
1711
1712 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1713
1714 return checksum;
1715}
1716
1717/**
c44ade9e 1718 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
9a799d71
AK		 1719 * @hw: pointer to hardware structure
1720 * @checksum_val: calculated checksum
1721 *
1722 * Performs checksum calculation and validates the EEPROM checksum. If the
1723 * caller does not need checksum_val, the value can be NULL.
1724 **/
c44ade9e
JB		 1725s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1726 u16 *checksum_val)
9a799d71
AK		 1727{
1728 s32 status;
1729 u16 checksum;
1730 u16 read_checksum = 0;
1731
1732 /*
1733 * Read the first word from the EEPROM. If this times out or fails, do
1734 * not continue or we could be in for a very long wait while every
1735 * EEPROM read fails
1736 */
c44ade9e 1737 status = hw->eeprom.ops.read(hw, 0, &checksum);
9a799d71
AK		 1738
1739 if (status == 0) {
a391f1d5 1740 checksum = hw->eeprom.ops.calc_checksum(hw);
9a799d71 1741
c44ade9e 1742 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
9a799d71
AK		 1743
1744 /*
1745 * Verify read checksum from EEPROM is the same as
1746 * calculated checksum
1747 */
1748 if (read_checksum != checksum)
1749 status = IXGBE_ERR_EEPROM_CHECKSUM;
1750
1751 /* If the user cares, return the calculated checksum */
1752 if (checksum_val)
1753 *checksum_val = checksum;
1754 } else {
1755 hw_dbg(hw, "EEPROM read failed\n");
1756 }
1757
1758 return status;
1759}
1760
c44ade9e
JB		 1761/**
1762 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1763 * @hw: pointer to hardware structure
1764 **/
1765s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1766{
1767 s32 status;
1768 u16 checksum;
1769
1770 /*
1771 * Read the first word from the EEPROM. If this times out or fails, do
1772 * not continue or we could be in for a very long wait while every
1773 * EEPROM read fails
1774 */
1775 status = hw->eeprom.ops.read(hw, 0, &checksum);
1776
1777 if (status == 0) {
a391f1d5 1778 checksum = hw->eeprom.ops.calc_checksum(hw);
c44ade9e 1779 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
8c7bea32 1780 checksum);
c44ade9e
JB		 1781 } else {
1782 hw_dbg(hw, "EEPROM read failed\n");
1783 }
1784
1785 return status;
1786}
1787
9a799d71 1788/**
c44ade9e 1789 * ixgbe_set_rar_generic - Set Rx address register
9a799d71 1790 * @hw: pointer to hardware structure
9a799d71 1791 * @index: Receive address register to write
c44ade9e
JB		 1792 * @addr: Address to put into receive address register
1793 * @vmdq: VMDq "set" or "pool" index
9a799d71
AK		 1794 * @enable_addr: set flag that address is active
1795 *
1796 * Puts an ethernet address into a receive address register.
1797 **/
c44ade9e
JB		 1798s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1799 u32 enable_addr)
9a799d71
AK		 1800{
1801 u32 rar_low, rar_high;
c44ade9e
JB		 1802 u32 rar_entries = hw->mac.num_rar_entries;
1803
c700f4e6
ET		 1804 /* Make sure we are using a valid rar index range */
1805 if (index >= rar_entries) {
1806 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1807 return IXGBE_ERR_INVALID_ARGUMENT;
1808 }
1809
c44ade9e
JB		 1810 /* setup VMDq pool selection before this RAR gets enabled */
1811 hw->mac.ops.set_vmdq(hw, index, vmdq);
9a799d71 1812
c700f4e6
ET		 1813 /*
1814 * HW expects these in little endian so we reverse the byte
1815 * order from network order (big endian) to little endian
1816 */
1817 rar_low = ((u32)addr[0] |
1818 ((u32)addr[1] << 8) |
1819 ((u32)addr[2] << 16) |
1820 ((u32)addr[3] << 24));
1821 /*
1822 * Some parts put the VMDq setting in the extra RAH bits,
1823 * so save everything except the lower 16 bits that hold part
1824 * of the address and the address valid bit.
1825 */
1826 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1827 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1828 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
9a799d71 1829
c700f4e6
ET		 1830 if (enable_addr != 0)
1831 rar_high |= IXGBE_RAH_AV;
9a799d71 1832
c700f4e6
ET		 1833 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1834 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
c44ade9e
JB		 1835
1836 return 0;
1837}
1838
1839/**
1840 * ixgbe_clear_rar_generic - Remove Rx address register
1841 * @hw: pointer to hardware structure
1842 * @index: Receive address register to write
1843 *
1844 * Clears an ethernet address from a receive address register.
1845 **/
1846s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1847{
1848 u32 rar_high;
1849 u32 rar_entries = hw->mac.num_rar_entries;
1850
1851 /* Make sure we are using a valid rar index range */
c700f4e6 1852 if (index >= rar_entries) {
c44ade9e 1853 hw_dbg(hw, "RAR index %d is out of range.\n", index);
c700f4e6 1854 return IXGBE_ERR_INVALID_ARGUMENT;
c44ade9e
JB		 1855 }
1856
c700f4e6
ET		 1857 /*
1858 * Some parts put the VMDq setting in the extra RAH bits,
1859 * so save everything except the lower 16 bits that hold part
1860 * of the address and the address valid bit.
1861 */
1862 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1863 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1864
1865 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1866 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1867
c44ade9e
JB		 1868 /* clear VMDq pool/queue selection for this RAR */
1869 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
9a799d71
AK		 1870
1871 return 0;
1872}
1873
c44ade9e
JB		 1874/**
1875 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
9a799d71
AK		 1876 * @hw: pointer to hardware structure
1877 *
1878 * Places the MAC address in receive address register 0 and clears the rest
c44ade9e 1879 * of the receive address registers. Clears the multicast table. Assumes
9a799d71
AK		 1880 * the receiver is in reset when the routine is called.
1881 **/
c44ade9e 1882s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1883{
1884 u32 i;
2c5645cf 1885 u32 rar_entries = hw->mac.num_rar_entries;
9a799d71
AK		 1886
1887 /*
1888 * If the current mac address is valid, assume it is a software override
1889 * to the permanent address.
1890 * Otherwise, use the permanent address from the eeprom.
1891 */
f8ebc683 1892 if (!is_valid_ether_addr(hw->mac.addr)) {
9a799d71 1893 /* Get the MAC address from the RAR0 for later reference */
c44ade9e 1894 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
9a799d71 1895
ce7194d8 1896 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
9a799d71
AK		 1897 } else {
1898 /* Setup the receive address. */
1899 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
ce7194d8 1900 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
9a799d71 1901
c44ade9e 1902 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
96cc6372
AD		 1903
1904 /* clear VMDq pool/queue selection for RAR 0 */
1905 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
9a799d71 1906 }
c44ade9e 1907 hw->addr_ctrl.overflow_promisc = 0;
9a799d71
AK		 1908
1909 hw->addr_ctrl.rar_used_count = 1;
1910
1911 /* Zero out the other receive addresses. */
c44ade9e 1912 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
9a799d71
AK		 1913 for (i = 1; i < rar_entries; i++) {
1914 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1915 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1916 }
1917
1918 /* Clear the MTA */
9a799d71
AK		 1919 hw->addr_ctrl.mta_in_use = 0;
1920 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1921
1922 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1923 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1924 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1925
c44ade9e
JB		 1926 if (hw->mac.ops.init_uta_tables)
1927 hw->mac.ops.init_uta_tables(hw);
1928
9a799d71
AK		 1929 return 0;
1930}
1931
1932/**
1933 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1934 * @hw: pointer to hardware structure
1935 * @mc_addr: the multicast address
1936 *
1937 * Extracts the 12 bits, from a multicast address, to determine which
1938 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1939 * incoming rx multicast addresses, to determine the bit-vector to check in
1940 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
c44ade9e 1941 * by the MO field of the MCSTCTRL. The MO field is set during initialization
9a799d71
AK		 1942 * to mc_filter_type.
1943 **/
1944static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1945{
1946 u32 vector = 0;
1947
1948 switch (hw->mac.mc_filter_type) {
b4617240 1949 case 0: /* use bits [47:36] of the address */
9a799d71
AK		 1950 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1951 break;
b4617240 1952 case 1: /* use bits [46:35] of the address */
9a799d71
AK		 1953 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1954 break;
b4617240 1955 case 2: /* use bits [45:34] of the address */
9a799d71
AK		 1956 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1957 break;
b4617240 1958 case 3: /* use bits [43:32] of the address */
9a799d71
AK		 1959 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1960 break;
b4617240 1961 default: /* Invalid mc_filter_type */
9a799d71
AK		 1962 hw_dbg(hw, "MC filter type param set incorrectly\n");
1963 break;
1964 }
1965
1966 /* vector can only be 12-bits or boundary will be exceeded */
1967 vector &= 0xFFF;
1968 return vector;
1969}
1970
1971/**
1972 * ixgbe_set_mta - Set bit-vector in multicast table
1973 * @hw: pointer to hardware structure
1974 * @hash_value: Multicast address hash value
1975 *
1976 * Sets the bit-vector in the multicast table.
1977 **/
1978static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1979{
1980 u32 vector;
1981 u32 vector_bit;
1982 u32 vector_reg;
9a799d71
AK		 1983
1984 hw->addr_ctrl.mta_in_use++;
1985
1986 vector = ixgbe_mta_vector(hw, mc_addr);
1987 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1988
1989 /*
1990 * The MTA is a register array of 128 32-bit registers. It is treated
1991 * like an array of 4096 bits. We want to set bit
1992 * BitArray[vector_value]. So we figure out what register the bit is
1993 * in, read it, OR in the new bit, then write back the new value. The
1994 * register is determined by the upper 7 bits of the vector value and
1995 * the bit within that register are determined by the lower 5 bits of
1996 * the value.
1997 */
1998 vector_reg = (vector >> 5) & 0x7F;
1999 vector_bit = vector & 0x1F;
80960ab0 2000 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
9a799d71
AK		 2001}
2002
9a799d71 2003/**
c44ade9e 2004 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
9a799d71 2005 * @hw: pointer to hardware structure
2853eb89 2006 * @netdev: pointer to net device structure
9a799d71
AK		 2007 *
2008 * The given list replaces any existing list. Clears the MC addrs from receive
c44ade9e 2009 * address registers and the multicast table. Uses unused receive address
9a799d71
AK		 2010 * registers for the first multicast addresses, and hashes the rest into the
2011 * multicast table.
2012 **/
2853eb89
JP		 2013s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
2014 struct net_device *netdev)
9a799d71 2015{
22bedad3 2016 struct netdev_hw_addr *ha;
9a799d71 2017 u32 i;
9a799d71
AK		 2018
2019 /*
2020 * Set the new number of MC addresses that we are being requested to
2021 * use.
2022 */
2853eb89 2023 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
9a799d71
AK		 2024 hw->addr_ctrl.mta_in_use = 0;
2025
80960ab0 2026 /* Clear mta_shadow */
9a799d71 2027 hw_dbg(hw, " Clearing MTA\n");
80960ab0 2028 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
9a799d71 2029
80960ab0 2030 /* Update mta shadow */
22bedad3 2031 netdev_for_each_mc_addr(ha, netdev) {
9a799d71 2032 hw_dbg(hw, " Adding the multicast addresses:\n");
22bedad3 2033 ixgbe_set_mta(hw, ha->addr);
9a799d71
AK		 2034 }
2035
2036 /* Enable mta */
80960ab0
ET		 2037 for (i = 0; i < hw->mac.mcft_size; i++)
2038 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2039 hw->mac.mta_shadow[i]);
2040
9a799d71
AK		 2041 if (hw->addr_ctrl.mta_in_use > 0)
2042 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
b4617240 2043 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
9a799d71 2044
c44ade9e 2045 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
9a799d71
AK		 2046 return 0;
2047}
2048
2049/**
c44ade9e 2050 * ixgbe_enable_mc_generic - Enable multicast address in RAR
9a799d71
AK		 2051 * @hw: pointer to hardware structure
2052 *
c44ade9e 2053 * Enables multicast address in RAR and the use of the multicast hash table.
9a799d71 2054 **/
c44ade9e 2055s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
9a799d71 2056{
c44ade9e 2057 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
9a799d71 2058
c44ade9e
JB		 2059 if (a->mta_in_use > 0)
2060 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2061 hw->mac.mc_filter_type);
9a799d71
AK		 2062
2063 return 0;
2064}
2065
2066/**
c44ade9e 2067 * ixgbe_disable_mc_generic - Disable multicast address in RAR
9a799d71 2068 * @hw: pointer to hardware structure
9a799d71 2069 *
c44ade9e 2070 * Disables multicast address in RAR and the use of the multicast hash table.
9a799d71 2071 **/
c44ade9e 2072s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
9a799d71 2073{
c44ade9e 2074 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2b9ade93 2075
c44ade9e
JB		 2076 if (a->mta_in_use > 0)
2077 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
9a799d71
AK		 2078
2079 return 0;
2080}
2081
11afc1b1 2082/**
620fa036 2083 * ixgbe_fc_enable_generic - Enable flow control
11afc1b1 2084 * @hw: pointer to hardware structure
11afc1b1
PW		 2085 *
2086 * Enable flow control according to the current settings.
2087 **/
041441d0 2088s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
11afc1b1
PW		 2089{
2090 s32 ret_val = 0;
620fa036 2091 u32 mflcn_reg, fccfg_reg;
11afc1b1 2092 u32 reg;
16b61beb 2093 u32 fcrtl, fcrth;
041441d0 2094 int i;
70b77628 2095
041441d0
AD		 2096 /*
2097 * Validate the water mark configuration for packet buffer 0. Zero
2098 * water marks indicate that the packet buffer was not configured
2099 * and the watermarks for packet buffer 0 should always be configured.
2100 */
2101 if (!hw->fc.low_water ||
2102 !hw->fc.high_water[0] ||
2103 !hw->fc.pause_time) {
2104 hw_dbg(hw, "Invalid water mark configuration\n");
2105 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
70b77628 2106 goto out;
041441d0 2107 }
70b77628 2108
620fa036 2109 /* Negotiate the fc mode to use */
786e9a5f 2110 ixgbe_fc_autoneg(hw);
11afc1b1 2111
620fa036 2112 /* Disable any previous flow control settings */
11afc1b1 2113 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
041441d0 2114 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
11afc1b1
PW		 2115
2116 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2117 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2118
2119 /*
2120 * The possible values of fc.current_mode are:
2121 * 0: Flow control is completely disabled
2122 * 1: Rx flow control is enabled (we can receive pause frames,
2123 * but not send pause frames).
bb3daa4a
PW		 2124 * 2: Tx flow control is enabled (we can send pause frames but
2125 * we do not support receiving pause frames).
11afc1b1
PW		 2126 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2127 * other: Invalid.
2128 */
2129 switch (hw->fc.current_mode) {
2130 case ixgbe_fc_none:
620fa036
MC		 2131 /*
2132 * Flow control is disabled by software override or autoneg.
2133 * The code below will actually disable it in the HW.
2134 */
11afc1b1
PW		 2135 break;
2136 case ixgbe_fc_rx_pause:
2137 /*
2138 * Rx Flow control is enabled and Tx Flow control is
2139 * disabled by software override. Since there really
2140 * isn't a way to advertise that we are capable of RX
2141 * Pause ONLY, we will advertise that we support both
2142 * symmetric and asymmetric Rx PAUSE. Later, we will
2143 * disable the adapter's ability to send PAUSE frames.
2144 */
2145 mflcn_reg |= IXGBE_MFLCN_RFCE;
2146 break;
2147 case ixgbe_fc_tx_pause:
2148 /*
2149 * Tx Flow control is enabled, and Rx Flow control is
2150 * disabled by software override.
2151 */
2152 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2153 break;
2154 case ixgbe_fc_full:
2155 /* Flow control (both Rx and Tx) is enabled by SW override. */
2156 mflcn_reg |= IXGBE_MFLCN_RFCE;
2157 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2158 break;
2159 default:
2160 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 2161 ret_val = IXGBE_ERR_CONFIG;
11afc1b1
PW		 2162 goto out;
2163 break;
2164 }
2165
620fa036 2166 /* Set 802.3x based flow control settings. */
2132d381 2167 mflcn_reg |= IXGBE_MFLCN_DPF;
11afc1b1
PW		 2168 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2169 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2170
041441d0 2171 fcrtl = (hw->fc.low_water << 10) | IXGBE_FCRTL_XONE;
264857b8 2172
041441d0
AD		 2173 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2174 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2175 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2176 hw->fc.high_water[i]) {
2177 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2178 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2179 } else {
2180 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2181 /*
2182 * In order to prevent Tx hangs when the internal Tx
2183 * switch is enabled we must set the high water mark
2184 * to the maximum FCRTH value. This allows the Tx
2185 * switch to function even under heavy Rx workloads.
2186 */
2187 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
2188 }
11afc1b1 2189
041441d0
AD		 2190 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2191 }
16b61beb 2192
11afc1b1 2193 /* Configure pause time (2 TCs per register) */
041441d0
AD		 2194 reg = hw->fc.pause_time * 0x00010001;
2195 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
2196 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2197
2198 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
11afc1b1
PW		 2199
2200out:
2201 return ret_val;
2202}
2203
0ecc061d 2204/**
67a79df2 2205 * ixgbe_negotiate_fc - Negotiate flow control
0ecc061d 2206 * @hw: pointer to hardware structure
67a79df2
AD		 2207 * @adv_reg: flow control advertised settings
2208 * @lp_reg: link partner's flow control settings
2209 * @adv_sym: symmetric pause bit in advertisement
2210 * @adv_asm: asymmetric pause bit in advertisement
2211 * @lp_sym: symmetric pause bit in link partner advertisement
2212 * @lp_asm: asymmetric pause bit in link partner advertisement
0ecc061d 2213 *
67a79df2
AD		 2214 * Find the intersection between advertised settings and link partner's
2215 * advertised settings
0ecc061d 2216 **/
67a79df2
AD		 2217static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2218 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
0ecc061d 2219{
67a79df2
AD		 2220 if ((!(adv_reg)) || (!(lp_reg)))
2221 return IXGBE_ERR_FC_NOT_NEGOTIATED;
0b0c2b31 2222
67a79df2
AD		 2223 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2224 /*
2225 * Now we need to check if the user selected Rx ONLY
2226 * of pause frames. In this case, we had to advertise
2227 * FULL flow control because we could not advertise RX
2228 * ONLY. Hence, we must now check to see if we need to
2229 * turn OFF the TRANSMISSION of PAUSE frames.
2230 */
2231 if (hw->fc.requested_mode == ixgbe_fc_full) {
2232 hw->fc.current_mode = ixgbe_fc_full;
2233 hw_dbg(hw, "Flow Control = FULL.\n");
2234 } else {
2235 hw->fc.current_mode = ixgbe_fc_rx_pause;
2236 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
2237 }
2238 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2239 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2240 hw->fc.current_mode = ixgbe_fc_tx_pause;
2241 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2242 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2243 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2244 hw->fc.current_mode = ixgbe_fc_rx_pause;
2245 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
0b0c2b31 2246 } else {
67a79df2
AD		 2247 hw->fc.current_mode = ixgbe_fc_none;
2248 hw_dbg(hw, "Flow Control = NONE.\n");
539e5f02 2249 }
67a79df2 2250 return 0;
0b0c2b31
ET		 2251}
2252
2253/**
2254 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2255 * @hw: pointer to hardware structure
2256 *
2257 * Enable flow control according on 1 gig fiber.
2258 **/
2259static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2260{
2261 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
786e9a5f 2262 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
539e5f02
PWJ		 2263
2264 /*
2265 * On multispeed fiber at 1g, bail out if
2266 * - link is up but AN did not complete, or if
2267 * - link is up and AN completed but timed out
2268 */
0b0c2b31
ET		 2269
2270 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
53f096de 2271 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
786e9a5f 2272 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
0b0c2b31 2273 goto out;
539e5f02 2274
0b0c2b31
ET		 2275 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2276 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2277
2278 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2279 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2280 IXGBE_PCS1GANA_ASM_PAUSE,
2281 IXGBE_PCS1GANA_SYM_PAUSE,
2282 IXGBE_PCS1GANA_ASM_PAUSE);
2283
2284out:
2285 return ret_val;
2286}
2287
2288/**
2289 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2290 * @hw: pointer to hardware structure
2291 *
2292 * Enable flow control according to IEEE clause 37.
2293 **/
2294static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2295{
2296 u32 links2, anlp1_reg, autoc_reg, links;
786e9a5f 2297 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
0b0c2b31 2298
9bbe3a57 2299 /*
0b0c2b31
ET		 2300 * On backplane, bail out if
2301 * - backplane autoneg was not completed, or if
2302 * - we are 82599 and link partner is not AN enabled
9bbe3a57 2303 */
0b0c2b31 2304 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
786e9a5f 2305 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
9bbe3a57 2306 goto out;
9bbe3a57 2307
0b0c2b31
ET		 2308 if (hw->mac.type == ixgbe_mac_82599EB) {
2309 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
786e9a5f 2310 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
0b0c2b31 2311 goto out;
0b0c2b31 2312 }
0ecc061d 2313 /*
0b0c2b31 2314 * Read the 10g AN autoc and LP ability registers and resolve
0ecc061d
PWJ		 2315 * local flow control settings accordingly
2316 */
0b0c2b31
ET		 2317 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2318 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
539e5f02 2319
0b0c2b31
ET		 2320 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2321 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2322 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2323
2324out:
2325 return ret_val;
2326}
2327
2328/**
2329 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2330 * @hw: pointer to hardware structure
2331 *
2332 * Enable flow control according to IEEE clause 37.
2333 **/
2334static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2335{
2336 u16 technology_ability_reg = 0;
2337 u16 lp_technology_ability_reg = 0;
2338
2339 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2340 MDIO_MMD_AN,
2341 &technology_ability_reg);
2342 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
2343 MDIO_MMD_AN,
2344 &lp_technology_ability_reg);
2345
2346 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2347 (u32)lp_technology_ability_reg,
2348 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2349 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2350}
2351
2352/**
67a79df2 2353 * ixgbe_fc_autoneg - Configure flow control
11afc1b1
PW		 2354 * @hw: pointer to hardware structure
2355 *
67a79df2
AD		 2356 * Compares our advertised flow control capabilities to those advertised by
2357 * our link partner, and determines the proper flow control mode to use.
11afc1b1 2358 **/
67a79df2 2359void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
11afc1b1 2360{
67a79df2
AD		 2361 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2362 ixgbe_link_speed speed;
2363 bool link_up;
11afc1b1
PW		 2364
2365 /*
67a79df2
AD		 2366 * AN should have completed when the cable was plugged in.
2367 * Look for reasons to bail out. Bail out if:
2368 * - FC autoneg is disabled, or if
2369 * - link is not up.
2370 *
2371 * Since we're being called from an LSC, link is already known to be up.
2372 * So use link_up_wait_to_complete=false.
11afc1b1 2373 */
67a79df2 2374 if (hw->fc.disable_fc_autoneg)
620fa036 2375 goto out;
11afc1b1 2376
67a79df2
AD		 2377 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2378 if (!link_up)
11afc1b1 2379 goto out;
0b0c2b31
ET		 2380
2381 switch (hw->phy.media_type) {
67a79df2 2382 /* Autoneg flow control on fiber adapters */
0b0c2b31 2383 case ixgbe_media_type_fiber:
67a79df2
AD		 2384 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2385 ret_val = ixgbe_fc_autoneg_fiber(hw);
2386 break;
2387
2388 /* Autoneg flow control on backplane adapters */
0b0c2b31 2389 case ixgbe_media_type_backplane:
67a79df2 2390 ret_val = ixgbe_fc_autoneg_backplane(hw);
0b0c2b31
ET		 2391 break;
2392
67a79df2 2393 /* Autoneg flow control on copper adapters */
0b0c2b31 2394 case ixgbe_media_type_copper:
67a79df2
AD		 2395 if (ixgbe_device_supports_autoneg_fc(hw) == 0)
2396 ret_val = ixgbe_fc_autoneg_copper(hw);
0b0c2b31
ET		 2397 break;
2398
2399 default:
620fa036 2400 break;
0b0c2b31 2401 }
539e5f02 2402
11afc1b1 2403out:
67a79df2
AD		 2404 if (ret_val == 0) {
2405 hw->fc.fc_was_autonegged = true;
2406 } else {
2407 hw->fc.fc_was_autonegged = false;
2408 hw->fc.current_mode = hw->fc.requested_mode;
2409 }
11afc1b1
PW		 2410}
2411
9a799d71
AK		 2412/**
2413 * ixgbe_disable_pcie_master - Disable PCI-express master access
2414 * @hw: pointer to hardware structure
2415 *
2416 * Disables PCI-Express master access and verifies there are no pending
2417 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2418 * bit hasn't caused the master requests to be disabled, else 0
2419 * is returned signifying master requests disabled.
2420 **/
ff9d1a5a 2421static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
9a799d71 2422{
a4297dc2 2423 struct ixgbe_adapter *adapter = hw->back;
a4297dc2 2424 s32 status = 0;
ff9d1a5a
ET		 2425 u32 i;
2426 u16 value;
2427
2428 /* Always set this bit to ensure any future transactions are blocked */
2429 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
a4297dc2 2430
ff9d1a5a 2431 /* Exit if master requests are blocked */
a4297dc2
ET		 2432 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2433 goto out;
9a799d71 2434
ff9d1a5a 2435 /* Poll for master request bit to clear */
9a799d71 2436 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
a4297dc2 2437 udelay(100);
ff9d1a5a
ET		 2438 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2439 goto out;
a4297dc2
ET		 2440 }
2441
ff9d1a5a
ET		 2442 /*
2443 * Two consecutive resets are required via CTRL.RST per datasheet
2444 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2445 * of this need. The first reset prevents new master requests from
2446 * being issued by our device. We then must wait 1usec or more for any
2447 * remaining completions from the PCIe bus to trickle in, and then reset
2448 * again to clear out any effects they may have had on our device.
2449 */
a4297dc2 2450 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
ff9d1a5a 2451 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
a4297dc2
ET		 2452
2453 /*
2454 * Before proceeding, make sure that the PCIe block does not have
2455 * transactions pending.
2456 */
a4297dc2 2457 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
9a799d71 2458 udelay(100);
ff9d1a5a
ET		 2459 pci_read_config_word(adapter->pdev, IXGBE_PCI_DEVICE_STATUS,
2460 &value);
2461 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2462 goto out;
9a799d71
AK		 2463 }
2464
ff9d1a5a
ET		 2465 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2466 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
a4297dc2
ET		 2467
2468out:
9a799d71
AK		 2469 return status;
2470}
2471
9a799d71 2472/**
c44ade9e 2473 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
9a799d71 2474 * @hw: pointer to hardware structure
c44ade9e 2475 * @mask: Mask to specify which semaphore to acquire
9a799d71 2476 *
da74cd4a 2477 * Acquires the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2478 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2479 **/
2480s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2481{
2482 u32 gssr;
2483 u32 swmask = mask;
2484 u32 fwmask = mask << 5;
2485 s32 timeout = 200;
2486
2487 while (timeout) {
dbf893ee
ET		 2488 /*
2489 * SW EEPROM semaphore bit is used for access to all
2490 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2491 */
9a799d71 2492 if (ixgbe_get_eeprom_semaphore(hw))
539e5f02 2493 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2494
2495 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2496 if (!(gssr & (fwmask | swmask)))
2497 break;
2498
2499 /*
2500 * Firmware currently using resource (fwmask) or other software
2501 * thread currently using resource (swmask)
2502 */
2503 ixgbe_release_eeprom_semaphore(hw);
032b4325 2504 usleep_range(5000, 10000);
9a799d71
AK		 2505 timeout--;
2506 }
2507
2508 if (!timeout) {
dbf893ee 2509 hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n");
539e5f02 2510 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2511 }
2512
2513 gssr |= swmask;
2514 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2515
2516 ixgbe_release_eeprom_semaphore(hw);
2517 return 0;
2518}
2519
2520/**
2521 * ixgbe_release_swfw_sync - Release SWFW semaphore
2522 * @hw: pointer to hardware structure
c44ade9e 2523 * @mask: Mask to specify which semaphore to release
9a799d71 2524 *
da74cd4a 2525 * Releases the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2526 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2527 **/
2528void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2529{
2530 u32 gssr;
2531 u32 swmask = mask;
2532
2533 ixgbe_get_eeprom_semaphore(hw);
2534
2535 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2536 gssr &= ~swmask;
2537 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2538
2539 ixgbe_release_eeprom_semaphore(hw);
2540}
2541
d2f5e7f3
AS		 2542/**
2543 * ixgbe_disable_rx_buff_generic - Stops the receive data path
2544 * @hw: pointer to hardware structure
2545 *
2546 * Stops the receive data path and waits for the HW to internally
2547 * empty the Rx security block.
2548 **/
2549s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw)
2550{
2551#define IXGBE_MAX_SECRX_POLL 40
2552 int i;
2553 int secrxreg;
2554
2555 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2556 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2557 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2558 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2559 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2560 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2561 break;
2562 else
2563 /* Use interrupt-safe sleep just in case */
db76ad47 2564 udelay(1000);
d2f5e7f3
AS		 2565 }
2566
2567 /* For informational purposes only */
2568 if (i >= IXGBE_MAX_SECRX_POLL)
2569 hw_dbg(hw, "Rx unit being enabled before security "
2570 "path fully disabled. Continuing with init.\n");
2571
2572 return 0;
2573
2574}
2575
2576/**
2577 * ixgbe_enable_rx_buff - Enables the receive data path
2578 * @hw: pointer to hardware structure
2579 *
2580 * Enables the receive data path
2581 **/
2582s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw)
2583{
2584 int secrxreg;
2585
2586 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2587 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2588 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2589 IXGBE_WRITE_FLUSH(hw);
2590
2591 return 0;
2592}
2593
11afc1b1
PW		 2594/**
2595 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2596 * @hw: pointer to hardware structure
2597 * @regval: register value to write to RXCTRL
2598 *
2599 * Enables the Rx DMA unit
2600 **/
2601s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2602{
2603 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2604
2605 return 0;
2606}
87c12017
PW		 2607
2608/**
2609 * ixgbe_blink_led_start_generic - Blink LED based on index.
2610 * @hw: pointer to hardware structure
2611 * @index: led number to blink
2612 **/
2613s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2614{
2615 ixgbe_link_speed speed = 0;
3db1cd5c 2616 bool link_up = false;
87c12017
PW		 2617 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2618 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
d7bbcd32 2619 s32 ret_val = 0;
87c12017
PW		 2620
2621 /*
2622 * Link must be up to auto-blink the LEDs;
2623 * Force it if link is down.
2624 */
2625 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2626
2627 if (!link_up) {
d7bbcd32
DS		 2628 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
2629 * LESM is on.
2630 */
2631 bool got_lock = false;
2632
2633 if ((hw->mac.type == ixgbe_mac_82599EB) &&
2634 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
2635 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
2636 IXGBE_GSSR_MAC_CSR_SM);
2637 if (ret_val)
2638 goto out;
2639
2640 got_lock = true;
2641 }
50ac58ba 2642 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017
PW		 2643 autoc_reg |= IXGBE_AUTOC_FLU;
2644 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
945a5151 2645 IXGBE_WRITE_FLUSH(hw);
d7bbcd32
DS		 2646
2647 if (got_lock)
2648 hw->mac.ops.release_swfw_sync(hw,
2649 IXGBE_GSSR_MAC_CSR_SM);
032b4325 2650 usleep_range(10000, 20000);
87c12017
PW		 2651 }
2652
2653 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2654 led_reg |= IXGBE_LED_BLINK(index);
2655 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2656 IXGBE_WRITE_FLUSH(hw);
2657
d7bbcd32
DS		 2658out:
2659 return ret_val;
87c12017
PW		 2660}
2661
2662/**
2663 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2664 * @hw: pointer to hardware structure
2665 * @index: led number to stop blinking
2666 **/
2667s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2668{
2669 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2670 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
d7bbcd32
DS		 2671 s32 ret_val = 0;
2672 bool got_lock = false;
2673
2674 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
2675 * LESM is on.
2676 */
2677 if ((hw->mac.type == ixgbe_mac_82599EB) &&
2678 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
2679 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
2680 IXGBE_GSSR_MAC_CSR_SM);
2681 if (ret_val)
2682 goto out;
2683
2684 got_lock = true;
2685 }
87c12017
PW		 2686
2687 autoc_reg &= ~IXGBE_AUTOC_FLU;
2688 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2689 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2690
d7bbcd32
DS		 2691 if (hw->mac.type == ixgbe_mac_82599EB)
2692 ixgbe_reset_pipeline_82599(hw);
2693
2694 if (got_lock)
2695 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
2696
87c12017
PW		 2697 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2698 led_reg &= ~IXGBE_LED_BLINK(index);
2699 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2700 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2701 IXGBE_WRITE_FLUSH(hw);
2702
d7bbcd32
DS		 2703out:
2704 return ret_val;
87c12017 2705}
21ce849b
MC		 2706
2707/**
2708 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2709 * @hw: pointer to hardware structure
2710 * @san_mac_offset: SAN MAC address offset
2711 *
2712 * This function will read the EEPROM location for the SAN MAC address
2713 * pointer, and returns the value at that location. This is used in both
2714 * get and set mac_addr routines.
2715 **/
2716static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2717 u16 *san_mac_offset)
2718{
2719 /*
2720 * First read the EEPROM pointer to see if the MAC addresses are
2721 * available.
2722 */
2723 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2724
2725 return 0;
2726}
2727
2728/**
2729 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2730 * @hw: pointer to hardware structure
2731 * @san_mac_addr: SAN MAC address
2732 *
2733 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2734 * per-port, so set_lan_id() must be called before reading the addresses.
2735 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2736 * upon for non-SFP connections, so we must call it here.
2737 **/
2738s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2739{
2740 u16 san_mac_data, san_mac_offset;
2741 u8 i;
2742
2743 /*
2744 * First read the EEPROM pointer to see if the MAC addresses are
2745 * available. If they're not, no point in calling set_lan_id() here.
2746 */
2747 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2748
2749 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2750 /*
2751 * No addresses available in this EEPROM. It's not an
2752 * error though, so just wipe the local address and return.
2753 */
2754 for (i = 0; i < 6; i++)
2755 san_mac_addr[i] = 0xFF;
2756
2757 goto san_mac_addr_out;
2758 }
2759
2760 /* make sure we know which port we need to program */
2761 hw->mac.ops.set_lan_id(hw);
2762 /* apply the port offset to the address offset */
2763 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2764 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2765 for (i = 0; i < 3; i++) {
2766 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2767 san_mac_addr[i * 2] = (u8)(san_mac_data);
2768 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2769 san_mac_offset++;
2770 }
2771
2772san_mac_addr_out:
2773 return 0;
2774}
2775
2776/**
2777 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2778 * @hw: pointer to hardware structure
2779 *
2780 * Read PCIe configuration space, and get the MSI-X vector count from
2781 * the capabilities table.
2782 **/
71161302 2783u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
21ce849b
MC		 2784{
2785 struct ixgbe_adapter *adapter = hw->back;
71161302
ET		 2786 u16 msix_count = 1;
2787 u16 max_msix_count;
2788 u16 pcie_offset;
2789
2790 switch (hw->mac.type) {
2791 case ixgbe_mac_82598EB:
2792 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
2793 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
2794 break;
2795 case ixgbe_mac_82599EB:
2796 case ixgbe_mac_X540:
2797 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
2798 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
2799 break;
2800 default:
2801 return msix_count;
2802 }
2803
2804 pci_read_config_word(adapter->pdev, pcie_offset, &msix_count);
21ce849b
MC		 2805 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2806
71161302 2807 /* MSI-X count is zero-based in HW */
21ce849b
MC		 2808 msix_count++;
2809
71161302
ET		 2810 if (msix_count > max_msix_count)
2811 msix_count = max_msix_count;
2812
21ce849b
MC		 2813 return msix_count;
2814}
2815
2816/**
2817 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2818 * @hw: pointer to hardware struct
2819 * @rar: receive address register index to disassociate
2820 * @vmdq: VMDq pool index to remove from the rar
2821 **/
2822s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2823{
2824 u32 mpsar_lo, mpsar_hi;
2825 u32 rar_entries = hw->mac.num_rar_entries;
2826
c700f4e6
ET		 2827 /* Make sure we are using a valid rar index range */
2828 if (rar >= rar_entries) {
2829 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2830 return IXGBE_ERR_INVALID_ARGUMENT;
2831 }
21ce849b 2832
c700f4e6
ET		 2833 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2834 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
21ce849b 2835
c700f4e6
ET		 2836 if (!mpsar_lo && !mpsar_hi)
2837 goto done;
21ce849b 2838
c700f4e6
ET		 2839 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2840 if (mpsar_lo) {
2841 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2842 mpsar_lo = 0;
2843 }
2844 if (mpsar_hi) {
2845 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2846 mpsar_hi = 0;
2847 }
2848 } else if (vmdq < 32) {
2849 mpsar_lo &= ~(1 << vmdq);
2850 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
21ce849b 2851 } else {
c700f4e6
ET		 2852 mpsar_hi &= ~(1 << (vmdq - 32));
2853 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
21ce849b
MC		 2854 }
2855
c700f4e6
ET		 2856 /* was that the last pool using this rar? */
2857 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2858 hw->mac.ops.clear_rar(hw, rar);
21ce849b
MC		 2859done:
2860 return 0;
2861}
2862
2863/**
2864 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2865 * @hw: pointer to hardware struct
2866 * @rar: receive address register index to associate with a VMDq index
2867 * @vmdq: VMDq pool index
2868 **/
2869s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2870{
2871 u32 mpsar;
2872 u32 rar_entries = hw->mac.num_rar_entries;
2873
c700f4e6
ET		 2874 /* Make sure we are using a valid rar index range */
2875 if (rar >= rar_entries) {
21ce849b 2876 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
c700f4e6
ET		 2877 return IXGBE_ERR_INVALID_ARGUMENT;
2878 }
2879
2880 if (vmdq < 32) {
2881 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2882 mpsar |= 1 << vmdq;
2883 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2884 } else {
2885 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2886 mpsar |= 1 << (vmdq - 32);
2887 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
21ce849b
MC		 2888 }
2889 return 0;
2890}
2891
7fa7c9dc
AD		 2892/**
2893 * This function should only be involved in the IOV mode.
2894 * In IOV mode, Default pool is next pool after the number of
2895 * VFs advertized and not 0.
2896 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
2897 *
2898 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
2899 * @hw: pointer to hardware struct
2900 * @vmdq: VMDq pool index
2901 **/
2902s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
2903{
2904 u32 rar = hw->mac.san_mac_rar_index;
2905
2906 if (vmdq < 32) {
2907 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
2908 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2909 } else {
2910 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2911 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
2912 }
2913
2914 return 0;
2915}
2916
21ce849b
MC		 2917/**
2918 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2919 * @hw: pointer to hardware structure
2920 **/
2921s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2922{
2923 int i;
2924
21ce849b
MC		 2925 for (i = 0; i < 128; i++)
2926 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2927
2928 return 0;
2929}
2930
2931/**
2932 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2933 * @hw: pointer to hardware structure
2934 * @vlan: VLAN id to write to VLAN filter
2935 *
2936 * return the VLVF index where this VLAN id should be placed
2937 *
2938 **/
5d5b7c39 2939static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
21ce849b
MC		 2940{
2941 u32 bits = 0;
2942 u32 first_empty_slot = 0;
2943 s32 regindex;
2944
2945 /* short cut the special case */
2946 if (vlan == 0)
2947 return 0;
2948
2949 /*
2950 * Search for the vlan id in the VLVF entries. Save off the first empty
2951 * slot found along the way
2952 */
2953 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2954 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2955 if (!bits && !(first_empty_slot))
2956 first_empty_slot = regindex;
2957 else if ((bits & 0x0FFF) == vlan)
2958 break;
2959 }
2960
2961 /*
2962 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2963 * in the VLVF. Else use the first empty VLVF register for this
2964 * vlan id.
2965 */
2966 if (regindex >= IXGBE_VLVF_ENTRIES) {
2967 if (first_empty_slot)
2968 regindex = first_empty_slot;
2969 else {
2970 hw_dbg(hw, "No space in VLVF.\n");
2971 regindex = IXGBE_ERR_NO_SPACE;
2972 }
2973 }
2974
2975 return regindex;
2976}
2977
2978/**
2979 * ixgbe_set_vfta_generic - Set VLAN filter table
2980 * @hw: pointer to hardware structure
2981 * @vlan: VLAN id to write to VLAN filter
2982 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2983 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2984 *
2985 * Turn on/off specified VLAN in the VLAN filter table.
2986 **/
2987s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
2988 bool vlan_on)
2989{
2990 s32 regindex;
2991 u32 bitindex;
2992 u32 vfta;
2993 u32 bits;
2994 u32 vt;
2995 u32 targetbit;
2996 bool vfta_changed = false;
2997
2998 if (vlan > 4095)
2999 return IXGBE_ERR_PARAM;
3000
3001 /*
3002 * this is a 2 part operation - first the VFTA, then the
3003 * VLVF and VLVFB if VT Mode is set
3004 * We don't write the VFTA until we know the VLVF part succeeded.
3005 */
3006
3007 /* Part 1
3008 * The VFTA is a bitstring made up of 128 32-bit registers
3009 * that enable the particular VLAN id, much like the MTA:
3010 * bits[11-5]: which register
3011 * bits[4-0]: which bit in the register
3012 */
3013 regindex = (vlan >> 5) & 0x7F;
3014 bitindex = vlan & 0x1F;
3015 targetbit = (1 << bitindex);
3016 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3017
3018 if (vlan_on) {
3019 if (!(vfta & targetbit)) {
3020 vfta |= targetbit;
3021 vfta_changed = true;
3022 }
3023 } else {
3024 if ((vfta & targetbit)) {
3025 vfta &= ~targetbit;
3026 vfta_changed = true;
3027 }
3028 }
3029
3030 /* Part 2
3031 * If VT Mode is set
3032 * Either vlan_on
3033 * make sure the vlan is in VLVF
3034 * set the vind bit in the matching VLVFB
3035 * Or !vlan_on
3036 * clear the pool bit and possibly the vind
3037 */
3038 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3039 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3040 s32 vlvf_index;
3041
3042 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3043 if (vlvf_index < 0)
3044 return vlvf_index;
3045
3046 if (vlan_on) {
3047 /* set the pool bit */
3048 if (vind < 32) {
3049 bits = IXGBE_READ_REG(hw,
3050 IXGBE_VLVFB(vlvf_index*2));
3051 bits |= (1 << vind);
3052 IXGBE_WRITE_REG(hw,
3053 IXGBE_VLVFB(vlvf_index*2),
3054 bits);
3055 } else {
3056 bits = IXGBE_READ_REG(hw,
3057 IXGBE_VLVFB((vlvf_index*2)+1));
3058 bits |= (1 << (vind-32));
3059 IXGBE_WRITE_REG(hw,
3060 IXGBE_VLVFB((vlvf_index*2)+1),
3061 bits);
3062 }
3063 } else {
3064 /* clear the pool bit */
3065 if (vind < 32) {
3066 bits = IXGBE_READ_REG(hw,
3067 IXGBE_VLVFB(vlvf_index*2));
3068 bits &= ~(1 << vind);
3069 IXGBE_WRITE_REG(hw,
3070 IXGBE_VLVFB(vlvf_index*2),
3071 bits);
3072 bits |= IXGBE_READ_REG(hw,
3073 IXGBE_VLVFB((vlvf_index*2)+1));
3074 } else {
3075 bits = IXGBE_READ_REG(hw,
3076 IXGBE_VLVFB((vlvf_index*2)+1));
3077 bits &= ~(1 << (vind-32));
3078 IXGBE_WRITE_REG(hw,
3079 IXGBE_VLVFB((vlvf_index*2)+1),
3080 bits);
3081 bits |= IXGBE_READ_REG(hw,
3082 IXGBE_VLVFB(vlvf_index*2));
3083 }
3084 }
3085
3086 /*
3087 * If there are still bits set in the VLVFB registers
3088 * for the VLAN ID indicated we need to see if the
3089 * caller is requesting that we clear the VFTA entry bit.
3090 * If the caller has requested that we clear the VFTA
3091 * entry bit but there are still pools/VFs using this VLAN
3092 * ID entry then ignore the request. We're not worried
3093 * about the case where we're turning the VFTA VLAN ID
3094 * entry bit on, only when requested to turn it off as
3095 * there may be multiple pools and/or VFs using the
3096 * VLAN ID entry. In that case we cannot clear the
3097 * VFTA bit until all pools/VFs using that VLAN ID have also
3098 * been cleared. This will be indicated by "bits" being
3099 * zero.
3100 */
3101 if (bits) {
3102 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3103 (IXGBE_VLVF_VIEN | vlan));
3104 if (!vlan_on) {
3105 /* someone wants to clear the vfta entry
3106 * but some pools/VFs are still using it.
3107 * Ignore it. */
3108 vfta_changed = false;
3109 }
3110 }
3111 else
3112 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3113 }
3114
3115 if (vfta_changed)
3116 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3117
3118 return 0;
3119}
3120
3121/**
3122 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3123 * @hw: pointer to hardware structure
3124 *
3125 * Clears the VLAN filer table, and the VMDq index associated with the filter
3126 **/
3127s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3128{
3129 u32 offset;
3130
3131 for (offset = 0; offset < hw->mac.vft_size; offset++)
3132 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3133
3134 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3135 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3136 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
3137 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
3138 }
3139
3140 return 0;
3141}
3142
3143/**
3144 * ixgbe_check_mac_link_generic - Determine link and speed status
3145 * @hw: pointer to hardware structure
3146 * @speed: pointer to link speed
3147 * @link_up: true when link is up
3148 * @link_up_wait_to_complete: bool used to wait for link up or not
3149 *
3150 * Reads the links register to determine if link is up and the current speed
3151 **/
3152s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
8c7bea32 3153 bool *link_up, bool link_up_wait_to_complete)
21ce849b 3154{
48de36c5 3155 u32 links_reg, links_orig;
21ce849b
MC		 3156 u32 i;
3157
48de36c5
ET		 3158 /* clear the old state */
3159 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3160
21ce849b 3161 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
48de36c5
ET		 3162
3163 if (links_orig != links_reg) {
3164 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3165 links_orig, links_reg);
3166 }
3167
21ce849b
MC		 3168 if (link_up_wait_to_complete) {
3169 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3170 if (links_reg & IXGBE_LINKS_UP) {
3171 *link_up = true;
3172 break;
3173 } else {
3174 *link_up = false;
3175 }
3176 msleep(100);
3177 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3178 }
3179 } else {
3180 if (links_reg & IXGBE_LINKS_UP)
3181 *link_up = true;
3182 else
3183 *link_up = false;
3184 }
3185
3186 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3187 IXGBE_LINKS_SPEED_10G_82599)
3188 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3189 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
63d778df 3190 IXGBE_LINKS_SPEED_1G_82599)
21ce849b 3191 *speed = IXGBE_LINK_SPEED_1GB_FULL;
63d778df
ET		 3192 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3193 IXGBE_LINKS_SPEED_100_82599)
21ce849b 3194 *speed = IXGBE_LINK_SPEED_100_FULL;
63d778df
ET		 3195 else
3196 *speed = IXGBE_LINK_SPEED_UNKNOWN;
21ce849b 3197
21ce849b
MC		 3198 return 0;
3199}
a391f1d5
DS		 3200
3201/**
49ce9c2c 3202 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
a391f1d5
DS		 3203 * the EEPROM
3204 * @hw: pointer to hardware structure
3205 * @wwnn_prefix: the alternative WWNN prefix
3206 * @wwpn_prefix: the alternative WWPN prefix
3207 *
3208 * This function will read the EEPROM from the alternative SAN MAC address
3209 * block to check the support for the alternative WWNN/WWPN prefix support.
3210 **/
3211s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3212 u16 *wwpn_prefix)
3213{
3214 u16 offset, caps;
3215 u16 alt_san_mac_blk_offset;
3216
3217 /* clear output first */
3218 *wwnn_prefix = 0xFFFF;
3219 *wwpn_prefix = 0xFFFF;
3220
3221 /* check if alternative SAN MAC is supported */
3222 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
3223 &alt_san_mac_blk_offset);
3224
3225 if ((alt_san_mac_blk_offset == 0) ||
3226 (alt_san_mac_blk_offset == 0xFFFF))
3227 goto wwn_prefix_out;
3228
3229 /* check capability in alternative san mac address block */
3230 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3231 hw->eeprom.ops.read(hw, offset, &caps);
3232 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3233 goto wwn_prefix_out;
3234
3235 /* get the corresponding prefix for WWNN/WWPN */
3236 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3237 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
3238
3239 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3240 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
3241
3242wwn_prefix_out:
3243 return 0;
3244}
a985b6c3
GR		 3245
3246/**
3247 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3248 * @hw: pointer to hardware structure
3249 * @enable: enable or disable switch for anti-spoofing
3250 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3251 *
3252 **/
3253void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3254{
3255 int j;
3256 int pf_target_reg = pf >> 3;
3257 int pf_target_shift = pf % 8;
3258 u32 pfvfspoof = 0;
3259
3260 if (hw->mac.type == ixgbe_mac_82598EB)
3261 return;
3262
3263 if (enable)
3264 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3265
3266 /*
3267 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3268 * MAC anti-spoof enables in each register array element.
3269 */
ef89e0a2 3270 for (j = 0; j < pf_target_reg; j++)
a985b6c3
GR		 3271 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3272
a985b6c3
GR		 3273 /*
3274 * The PF should be allowed to spoof so that it can support
ef89e0a2
AD		 3275 * emulation mode NICs. Do not set the bits assigned to the PF
3276 */
3277 pfvfspoof &= (1 << pf_target_shift) - 1;
3278 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3279
3280 /*
3281 * Remaining pools belong to the PF so they do not need to have
3282 * anti-spoofing enabled.
a985b6c3 3283 */
ef89e0a2
AD		 3284 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3285 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
a985b6c3
GR		 3286}
3287
3288/**
3289 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3290 * @hw: pointer to hardware structure
3291 * @enable: enable or disable switch for VLAN anti-spoofing
3292 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3293 *
3294 **/
3295void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3296{
3297 int vf_target_reg = vf >> 3;
3298 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3299 u32 pfvfspoof;
3300
3301 if (hw->mac.type == ixgbe_mac_82598EB)
3302 return;
3303
3304 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3305 if (enable)
3306 pfvfspoof |= (1 << vf_target_shift);
3307 else
3308 pfvfspoof &= ~(1 << vf_target_shift);
3309 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3310}
b776d104
ET		 3311
3312/**
3313 * ixgbe_get_device_caps_generic - Get additional device capabilities
3314 * @hw: pointer to hardware structure
3315 * @device_caps: the EEPROM word with the extra device capabilities
3316 *
3317 * This function will read the EEPROM location for the device capabilities,
3318 * and return the word through device_caps.
3319 **/
3320s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3321{
3322 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3323
3324 return 0;
3325}
80605c65
JF		 3326
3327/**
3328 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3329 * @hw: pointer to hardware structure
3330 * @num_pb: number of packet buffers to allocate
3331 * @headroom: reserve n KB of headroom
3332 * @strategy: packet buffer allocation strategy
3333 **/
3334void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
3335 int num_pb,
3336 u32 headroom,
3337 int strategy)
3338{
3339 u32 pbsize = hw->mac.rx_pb_size;
3340 int i = 0;
3341 u32 rxpktsize, txpktsize, txpbthresh;
3342
3343 /* Reserve headroom */
3344 pbsize -= headroom;
3345
3346 if (!num_pb)
3347 num_pb = 1;
3348
3349 /* Divide remaining packet buffer space amongst the number
3350 * of packet buffers requested using supplied strategy.
3351 */
3352 switch (strategy) {
3353 case (PBA_STRATEGY_WEIGHTED):
3354 /* pba_80_48 strategy weight first half of packet buffer with
3355 * 5/8 of the packet buffer space.
3356 */
3357 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
3358 pbsize -= rxpktsize * (num_pb / 2);
3359 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3360 for (; i < (num_pb / 2); i++)
3361 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3362 /* Fall through to configure remaining packet buffers */
3363 case (PBA_STRATEGY_EQUAL):
3364 /* Divide the remaining Rx packet buffer evenly among the TCs */
3365 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3366 for (; i < num_pb; i++)
3367 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3368 break;
3369 default:
3370 break;
3371 }
3372
3373 /*
3374 * Setup Tx packet buffer and threshold equally for all TCs
3375 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3376 * 10 since the largest packet we support is just over 9K.
3377 */
3378 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3379 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3380 for (i = 0; i < num_pb; i++) {
3381 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3382 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3383 }
3384
3385 /* Clear unused TCs, if any, to zero buffer size*/
3386 for (; i < IXGBE_MAX_PB; i++) {
3387 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3388 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3389 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3390 }
3391}
9612de92
ET		 3392
3393/**
3394 * ixgbe_calculate_checksum - Calculate checksum for buffer
3395 * @buffer: pointer to EEPROM
3396 * @length: size of EEPROM to calculate a checksum for
49ce9c2c 3397 *
9612de92
ET		 3398 * Calculates the checksum for some buffer on a specified length. The
3399 * checksum calculated is returned.
3400 **/
3401static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3402{
3403 u32 i;
3404 u8 sum = 0;
3405
3406 if (!buffer)
3407 return 0;
3408
3409 for (i = 0; i < length; i++)
3410 sum += buffer[i];
3411
3412 return (u8) (0 - sum);
3413}
3414
3415/**
3416 * ixgbe_host_interface_command - Issue command to manageability block
3417 * @hw: pointer to the HW structure
3418 * @buffer: contains the command to write and where the return status will
3419 * be placed
c466d7a7 3420 * @length: length of buffer, must be multiple of 4 bytes
9612de92
ET		 3421 *
3422 * Communicates with the manageability block. On success return 0
3423 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3424 **/
79488c58 3425static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
9612de92
ET		 3426 u32 length)
3427{
331bcf45 3428 u32 hicr, i, bi;
9612de92
ET		 3429 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3430 u8 buf_len, dword_len;
3431
3432 s32 ret_val = 0;
3433
3434 if (length == 0 || length & 0x3 ||
3435 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3436 hw_dbg(hw, "Buffer length failure.\n");
3437 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3438 goto out;
3439 }
3440
3441 /* Check that the host interface is enabled. */
3442 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3443 if ((hicr & IXGBE_HICR_EN) == 0) {
3444 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
3445 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3446 goto out;
3447 }
3448
3449 /* Calculate length in DWORDs */
3450 dword_len = length >> 2;
3451
3452 /*
3453 * The device driver writes the relevant command block
3454 * into the ram area.
3455 */
3456 for (i = 0; i < dword_len; i++)
3457 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
79488c58 3458 i, cpu_to_le32(buffer[i]));
9612de92
ET		 3459
3460 /* Setting this bit tells the ARC that a new command is pending. */
3461 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3462
3463 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
3464 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3465 if (!(hicr & IXGBE_HICR_C))
3466 break;
3467 usleep_range(1000, 2000);
3468 }
3469
3470 /* Check command successful completion. */
3471 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
3472 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3473 hw_dbg(hw, "Command has failed with no status valid.\n");
3474 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3475 goto out;
3476 }
3477
3478 /* Calculate length in DWORDs */
3479 dword_len = hdr_size >> 2;
3480
3481 /* first pull in the header so we know the buffer length */
331bcf45
ET		 3482 for (bi = 0; bi < dword_len; bi++) {
3483 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3484 le32_to_cpus(&buffer[bi]);
79488c58 3485 }
9612de92
ET		 3486
3487 /* If there is any thing in data position pull it in */
3488 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3489 if (buf_len == 0)
3490 goto out;
3491
3492 if (length < (buf_len + hdr_size)) {
3493 hw_dbg(hw, "Buffer not large enough for reply message.\n");
3494 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3495 goto out;
3496 }
3497
331bcf45
ET		 3498 /* Calculate length in DWORDs, add 3 for odd lengths */
3499 dword_len = (buf_len + 3) >> 2;
9612de92 3500
331bcf45
ET		 3501 /* Pull in the rest of the buffer (bi is where we left off)*/
3502 for (; bi <= dword_len; bi++) {
3503 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3504 le32_to_cpus(&buffer[bi]);
3505 }
9612de92
ET		 3506
3507out:
3508 return ret_val;
3509}
3510
3511/**
3512 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3513 * @hw: pointer to the HW structure
3514 * @maj: driver version major number
3515 * @min: driver version minor number
3516 * @build: driver version build number
3517 * @sub: driver version sub build number
3518 *
3519 * Sends driver version number to firmware through the manageability
3520 * block. On success return 0
3521 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3522 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3523 **/
3524s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3525 u8 build, u8 sub)
3526{
3527 struct ixgbe_hic_drv_info fw_cmd;
3528 int i;
3529 s32 ret_val = 0;
3530
3531 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM) != 0) {
3532 ret_val = IXGBE_ERR_SWFW_SYNC;
3533 goto out;
3534 }
3535
3536 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3537 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3538 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3539 fw_cmd.port_num = (u8)hw->bus.func;
3540 fw_cmd.ver_maj = maj;
3541 fw_cmd.ver_min = min;
3542 fw_cmd.ver_build = build;
3543 fw_cmd.ver_sub = sub;
3544 fw_cmd.hdr.checksum = 0;
3545 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3546 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3547 fw_cmd.pad = 0;
3548 fw_cmd.pad2 = 0;
3549
3550 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
79488c58 3551 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
9612de92
ET		 3552 sizeof(fw_cmd));
3553 if (ret_val != 0)
3554 continue;
3555
3556 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3557 FW_CEM_RESP_STATUS_SUCCESS)
3558 ret_val = 0;
3559 else
3560 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3561
3562 break;
3563 }
3564
3565 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3566out:
3567 return ret_val;
3568}
ff9d1a5a
ET		 3569
3570/**
3571 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3572 * @hw: pointer to the hardware structure
3573 *
3574 * The 82599 and x540 MACs can experience issues if TX work is still pending
3575 * when a reset occurs. This function prevents this by flushing the PCIe
3576 * buffers on the system.
3577 **/
3578void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
3579{
3580 u32 gcr_ext, hlreg0;
3581
3582 /*
3583 * If double reset is not requested then all transactions should
3584 * already be clear and as such there is no work to do
3585 */
3586 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
3587 return;
3588
3589 /*
3590 * Set loopback enable to prevent any transmits from being sent
3591 * should the link come up. This assumes that the RXCTRL.RXEN bit
3592 * has already been cleared.
3593 */
3594 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3595 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
3596
3597 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3598 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3599 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
3600 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
3601
3602 /* Flush all writes and allow 20usec for all transactions to clear */
3603 IXGBE_WRITE_FLUSH(hw);
3604 udelay(20);
3605
3606 /* restore previous register values */
3607 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3608 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3609}
e1ea9158
DS		 3610
3611static const u8 ixgbe_emc_temp_data[4] = {
3612 IXGBE_EMC_INTERNAL_DATA,
3613 IXGBE_EMC_DIODE1_DATA,
3614 IXGBE_EMC_DIODE2_DATA,
3615 IXGBE_EMC_DIODE3_DATA
3616};
3617static const u8 ixgbe_emc_therm_limit[4] = {
3618 IXGBE_EMC_INTERNAL_THERM_LIMIT,
3619 IXGBE_EMC_DIODE1_THERM_LIMIT,
3620 IXGBE_EMC_DIODE2_THERM_LIMIT,
3621 IXGBE_EMC_DIODE3_THERM_LIMIT
3622};
3623
3624/**
3625 * ixgbe_get_ets_data - Extracts the ETS bit data
3626 * @hw: pointer to hardware structure
3627 * @ets_cfg: extected ETS data
3628 * @ets_offset: offset of ETS data
3629 *
3630 * Returns error code.
3631 **/
3632static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg,
3633 u16 *ets_offset)
3634{
3635 s32 status = 0;
3636
3637 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset);
3638 if (status)
3639 goto out;
3640
3641 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF)) {
3642 status = IXGBE_NOT_IMPLEMENTED;
3643 goto out;
3644 }
3645
3646 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg);
3647 if (status)
3648 goto out;
3649
3650 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED) {
3651 status = IXGBE_NOT_IMPLEMENTED;
3652 goto out;
3653 }
3654
3655out:
3656 return status;
3657}
3658
3659/**
3660 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
3661 * @hw: pointer to hardware structure
3662 *
3663 * Returns the thermal sensor data structure
3664 **/
3665s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
3666{
3667 s32 status = 0;
3668 u16 ets_offset;
3669 u16 ets_cfg;
3670 u16 ets_sensor;
3671 u8 num_sensors;
3672 u8 i;
3673 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3674
3ca8bc6d
DS		 3675 /* Only support thermal sensors attached to physical port 0 */
3676 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
e1ea9158
DS		 3677 status = IXGBE_NOT_IMPLEMENTED;
3678 goto out;
3679 }
3680
3681 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3682 if (status)
3683 goto out;
3684
3685 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3686 if (num_sensors > IXGBE_MAX_SENSORS)
3687 num_sensors = IXGBE_MAX_SENSORS;
3688
3689 for (i = 0; i < num_sensors; i++) {
3690 u8 sensor_index;
3691 u8 sensor_location;
3692
3693 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
3694 &ets_sensor);
3695 if (status)
3696 goto out;
3697
3698 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3699 IXGBE_ETS_DATA_INDEX_SHIFT);
3700 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3701 IXGBE_ETS_DATA_LOC_SHIFT);
3702
3703 if (sensor_location != 0) {
3704 status = hw->phy.ops.read_i2c_byte(hw,
3705 ixgbe_emc_temp_data[sensor_index],
3706 IXGBE_I2C_THERMAL_SENSOR_ADDR,
3707 &data->sensor[i].temp);
3708 if (status)
3709 goto out;
3710 }
3711 }
3712out:
3713 return status;
3714}
3715
3716/**
3717 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
3718 * @hw: pointer to hardware structure
3719 *
3720 * Inits the thermal sensor thresholds according to the NVM map
3721 * and save off the threshold and location values into mac.thermal_sensor_data
3722 **/
3723s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
3724{
3725 s32 status = 0;
3726 u16 ets_offset;
3727 u16 ets_cfg;
3728 u16 ets_sensor;
3729 u8 low_thresh_delta;
3730 u8 num_sensors;
3731 u8 therm_limit;
3732 u8 i;
3733 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3734
3735 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
3736
3ca8bc6d
DS		 3737 /* Only support thermal sensors attached to physical port 0 */
3738 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
e1ea9158
DS		 3739 status = IXGBE_NOT_IMPLEMENTED;
3740 goto out;
3741 }
3742
3743 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3744 if (status)
3745 goto out;
3746
3747 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
3748 IXGBE_ETS_LTHRES_DELTA_SHIFT);
3749 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3750 if (num_sensors > IXGBE_MAX_SENSORS)
3751 num_sensors = IXGBE_MAX_SENSORS;
3752
3753 for (i = 0; i < num_sensors; i++) {
3754 u8 sensor_index;
3755 u8 sensor_location;
3756
3757 hw->eeprom.ops.read(hw, (ets_offset + 1 + i), &ets_sensor);
3758 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3759 IXGBE_ETS_DATA_INDEX_SHIFT);
3760 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3761 IXGBE_ETS_DATA_LOC_SHIFT);
3762 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
3763
3764 hw->phy.ops.write_i2c_byte(hw,
3765 ixgbe_emc_therm_limit[sensor_index],
3766 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
3767
3768 if (sensor_location == 0)
3769 continue;
3770
3771 data->sensor[i].location = sensor_location;
3772 data->sensor[i].caution_thresh = therm_limit;
3773 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta;
3774 }
3775out:
3776 return status;
3777}
3778
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