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net: ethernet: mediatek: fix logic unbalance between probe and remove
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
CommitLineData
656e7052
JC		 1/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15#include <linux/of_device.h>
16#include <linux/of_mdio.h>
17#include <linux/of_net.h>
18#include <linux/mfd/syscon.h>
19#include <linux/regmap.h>
20#include <linux/clk.h>
21#include <linux/if_vlan.h>
22#include <linux/reset.h>
23#include <linux/tcp.h>
24
25#include "mtk_eth_soc.h"
26
27static int mtk_msg_level = -1;
28module_param_named(msg_level, mtk_msg_level, int, 0);
29MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31#define MTK_ETHTOOL_STAT(x) { #x, \
32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
33
34/* strings used by ethtool */
35static const struct mtk_ethtool_stats {
36 char str[ETH_GSTRING_LEN];
37 u32 offset;
38} mtk_ethtool_stats[] = {
39 MTK_ETHTOOL_STAT(tx_bytes),
40 MTK_ETHTOOL_STAT(tx_packets),
41 MTK_ETHTOOL_STAT(tx_skip),
42 MTK_ETHTOOL_STAT(tx_collisions),
43 MTK_ETHTOOL_STAT(rx_bytes),
44 MTK_ETHTOOL_STAT(rx_packets),
45 MTK_ETHTOOL_STAT(rx_overflow),
46 MTK_ETHTOOL_STAT(rx_fcs_errors),
47 MTK_ETHTOOL_STAT(rx_short_errors),
48 MTK_ETHTOOL_STAT(rx_long_errors),
49 MTK_ETHTOOL_STAT(rx_checksum_errors),
50 MTK_ETHTOOL_STAT(rx_flow_control_packets),
51};
52
549e5495
SW		 53static const char * const mtk_clks_source_name[] = {
54 "ethif", "esw", "gp1", "gp2"
55};
56
656e7052
JC		 57void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
58{
59 __raw_writel(val, eth->base + reg);
60}
61
62u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
63{
64 return __raw_readl(eth->base + reg);
65}
66
67static int mtk_mdio_busy_wait(struct mtk_eth *eth)
68{
69 unsigned long t_start = jiffies;
70
71 while (1) {
72 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
73 return 0;
74 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
75 break;
76 usleep_range(10, 20);
77 }
78
79 dev_err(eth->dev, "mdio: MDIO timeout\n");
80 return -1;
81}
82
379672de
WY		 83static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
84 u32 phy_register, u32 write_data)
656e7052
JC		 85{
86 if (mtk_mdio_busy_wait(eth))
87 return -1;
88
89 write_data &= 0xffff;
90
91 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
92 (phy_register << PHY_IAC_REG_SHIFT) |
93 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
94 MTK_PHY_IAC);
95
96 if (mtk_mdio_busy_wait(eth))
97 return -1;
98
99 return 0;
100}
101
379672de 102static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
656e7052
JC		 103{
104 u32 d;
105
106 if (mtk_mdio_busy_wait(eth))
107 return 0xffff;
108
109 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
110 (phy_reg << PHY_IAC_REG_SHIFT) |
111 (phy_addr << PHY_IAC_ADDR_SHIFT),
112 MTK_PHY_IAC);
113
114 if (mtk_mdio_busy_wait(eth))
115 return 0xffff;
116
117 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
118
119 return d;
120}
121
122static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
123 int phy_reg, u16 val)
124{
125 struct mtk_eth *eth = bus->priv;
126
127 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
128}
129
130static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
131{
132 struct mtk_eth *eth = bus->priv;
133
134 return _mtk_mdio_read(eth, phy_addr, phy_reg);
135}
136
137static void mtk_phy_link_adjust(struct net_device *dev)
138{
139 struct mtk_mac *mac = netdev_priv(dev);
08ef55c6
JC		 140 u16 lcl_adv = 0, rmt_adv = 0;
141 u8 flowctrl;
656e7052
JC		 142 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
143 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
144 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
145 MAC_MCR_BACKPR_EN;
146
147 switch (mac->phy_dev->speed) {
148 case SPEED_1000:
149 mcr |= MAC_MCR_SPEED_1000;
150 break;
151 case SPEED_100:
152 mcr |= MAC_MCR_SPEED_100;
153 break;
154 };
155
156 if (mac->phy_dev->link)
157 mcr |= MAC_MCR_FORCE_LINK;
158
08ef55c6 159 if (mac->phy_dev->duplex) {
656e7052
JC		 160 mcr |= MAC_MCR_FORCE_DPX;
161
08ef55c6
JC		 162 if (mac->phy_dev->pause)
163 rmt_adv = LPA_PAUSE_CAP;
164 if (mac->phy_dev->asym_pause)
165 rmt_adv |= LPA_PAUSE_ASYM;
166
167 if (mac->phy_dev->advertising & ADVERTISED_Pause)
168 lcl_adv |= ADVERTISE_PAUSE_CAP;
169 if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause)
170 lcl_adv |= ADVERTISE_PAUSE_ASYM;
171
172 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
173
174 if (flowctrl & FLOW_CTRL_TX)
175 mcr |= MAC_MCR_FORCE_TX_FC;
176 if (flowctrl & FLOW_CTRL_RX)
177 mcr |= MAC_MCR_FORCE_RX_FC;
178
179 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
180 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
181 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
182 }
656e7052
JC		 183
184 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
185
186 if (mac->phy_dev->link)
187 netif_carrier_on(dev);
188 else
189 netif_carrier_off(dev);
190}
191
192static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
193 struct device_node *phy_node)
194{
195 const __be32 *_addr = NULL;
196 struct phy_device *phydev;
197 int phy_mode, addr;
198
199 _addr = of_get_property(phy_node, "reg", NULL);
200
201 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) {
202 pr_err("%s: invalid phy address\n", phy_node->name);
203 return -EINVAL;
204 }
205 addr = be32_to_cpu(*_addr);
206 phy_mode = of_get_phy_mode(phy_node);
207 if (phy_mode < 0) {
208 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
209 return -EINVAL;
210 }
211
212 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
213 mtk_phy_link_adjust, 0, phy_mode);
977bc20c 214 if (!phydev) {
656e7052 215 dev_err(eth->dev, "could not connect to PHY\n");
977bc20c 216 return -ENODEV;
656e7052
JC		 217 }
218
219 dev_info(eth->dev,
220 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
221 mac->id, phydev_name(phydev), phydev->phy_id,
222 phydev->drv->name);
223
224 mac->phy_dev = phydev;
225
226 return 0;
227}
228
229static int mtk_phy_connect(struct mtk_mac *mac)
230{
231 struct mtk_eth *eth = mac->hw;
232 struct device_node *np;
233 u32 val, ge_mode;
234
235 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
0c72c50f
JC		 236 if (!np && of_phy_is_fixed_link(mac->of_node))
237 if (!of_phy_register_fixed_link(mac->of_node))
238 np = of_node_get(mac->of_node);
656e7052
JC		 239 if (!np)
240 return -ENODEV;
241
242 switch (of_get_phy_mode(np)) {
37920fce
JC		 243 case PHY_INTERFACE_MODE_RGMII_TXID:
244 case PHY_INTERFACE_MODE_RGMII_RXID:
245 case PHY_INTERFACE_MODE_RGMII_ID:
656e7052
JC		 246 case PHY_INTERFACE_MODE_RGMII:
247 ge_mode = 0;
248 break;
249 case PHY_INTERFACE_MODE_MII:
250 ge_mode = 1;
251 break;
8ca7f4fe 252 case PHY_INTERFACE_MODE_REVMII:
656e7052
JC		 253 ge_mode = 2;
254 break;
8ca7f4fe 255 case PHY_INTERFACE_MODE_RMII:
256 if (!mac->id)
257 goto err_phy;
258 ge_mode = 3;
259 break;
656e7052 260 default:
8ca7f4fe 261 goto err_phy;
656e7052
JC		 262 }
263
264 /* put the gmac into the right mode */
265 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
266 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
267 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
268 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
269
270 mtk_phy_connect_node(eth, mac, np);
271 mac->phy_dev->autoneg = AUTONEG_ENABLE;
272 mac->phy_dev->speed = 0;
273 mac->phy_dev->duplex = 0;
b2025c7c 274
275 if (of_phy_is_fixed_link(mac->of_node))
276 mac->phy_dev->supported |=
277 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
278
08ef55c6
JC		 279 mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
280 SUPPORTED_Asym_Pause;
656e7052
JC		 281 mac->phy_dev->advertising = mac->phy_dev->supported |
282 ADVERTISED_Autoneg;
283 phy_start_aneg(mac->phy_dev);
284
e8c2993a 285 of_node_put(np);
286
656e7052 287 return 0;
8ca7f4fe 288
289err_phy:
290 of_node_put(np);
291 dev_err(eth->dev, "invalid phy_mode\n");
292 return -EINVAL;
656e7052
JC		 293}
294
295static int mtk_mdio_init(struct mtk_eth *eth)
296{
297 struct device_node *mii_np;
298 int err;
299
300 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
301 if (!mii_np) {
302 dev_err(eth->dev, "no %s child node found", "mdio-bus");
303 return -ENODEV;
304 }
305
306 if (!of_device_is_available(mii_np)) {
307 err = 0;
308 goto err_put_node;
309 }
310
311 eth->mii_bus = mdiobus_alloc();
312 if (!eth->mii_bus) {
313 err = -ENOMEM;
314 goto err_put_node;
315 }
316
317 eth->mii_bus->name = "mdio";
318 eth->mii_bus->read = mtk_mdio_read;
319 eth->mii_bus->write = mtk_mdio_write;
320 eth->mii_bus->priv = eth;
321 eth->mii_bus->parent = eth->dev;
322
323 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
324 err = of_mdiobus_register(eth->mii_bus, mii_np);
325 if (err)
326 goto err_free_bus;
327
328 return 0;
329
330err_free_bus:
207bdf18 331 mdiobus_free(eth->mii_bus);
656e7052
JC		 332
333err_put_node:
334 of_node_put(mii_np);
335 eth->mii_bus = NULL;
336 return err;
337}
338
339static void mtk_mdio_cleanup(struct mtk_eth *eth)
340{
341 if (!eth->mii_bus)
342 return;
343
344 mdiobus_unregister(eth->mii_bus);
345 of_node_put(eth->mii_bus->dev.of_node);
207bdf18 346 mdiobus_free(eth->mii_bus);
656e7052
JC		 347}
348
349static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask)
350{
7bc9ccec 351 unsigned long flags;
656e7052
JC		 352 u32 val;
353
7bc9ccec 354 spin_lock_irqsave(&eth->irq_lock, flags);
656e7052
JC		 355 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
356 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
7bc9ccec 357 spin_unlock_irqrestore(&eth->irq_lock, flags);
656e7052
JC		 358}
359
360static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask)
361{
7bc9ccec 362 unsigned long flags;
656e7052
JC		 363 u32 val;
364
7bc9ccec 365 spin_lock_irqsave(&eth->irq_lock, flags);
656e7052
JC		 366 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
367 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
7bc9ccec 368 spin_unlock_irqrestore(&eth->irq_lock, flags);
656e7052
JC		 369}
370
371static int mtk_set_mac_address(struct net_device *dev, void *p)
372{
373 int ret = eth_mac_addr(dev, p);
374 struct mtk_mac *mac = netdev_priv(dev);
375 const char *macaddr = dev->dev_addr;
376 unsigned long flags;
377
378 if (ret)
379 return ret;
380
381 spin_lock_irqsave(&mac->hw->page_lock, flags);
382 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
383 MTK_GDMA_MAC_ADRH(mac->id));
384 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
385 (macaddr[4] << 8) | macaddr[5],
386 MTK_GDMA_MAC_ADRL(mac->id));
387 spin_unlock_irqrestore(&mac->hw->page_lock, flags);
388
389 return 0;
390}
391
392void mtk_stats_update_mac(struct mtk_mac *mac)
393{
394 struct mtk_hw_stats *hw_stats = mac->hw_stats;
395 unsigned int base = MTK_GDM1_TX_GBCNT;
396 u64 stats;
397
398 base += hw_stats->reg_offset;
399
400 u64_stats_update_begin(&hw_stats->syncp);
401
402 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
403 stats = mtk_r32(mac->hw, base + 0x04);
404 if (stats)
405 hw_stats->rx_bytes += (stats << 32);
406 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
407 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
408 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
409 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
410 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
411 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
412 hw_stats->rx_flow_control_packets +=
413 mtk_r32(mac->hw, base + 0x24);
414 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
415 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
416 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
417 stats = mtk_r32(mac->hw, base + 0x34);
418 if (stats)
419 hw_stats->tx_bytes += (stats << 32);
420 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
421 u64_stats_update_end(&hw_stats->syncp);
422}
423
424static void mtk_stats_update(struct mtk_eth *eth)
425{
426 int i;
427
428 for (i = 0; i < MTK_MAC_COUNT; i++) {
429 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
430 continue;
431 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
432 mtk_stats_update_mac(eth->mac[i]);
433 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
434 }
435 }
436}
437
438static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
439 struct rtnl_link_stats64 *storage)
440{
441 struct mtk_mac *mac = netdev_priv(dev);
442 struct mtk_hw_stats *hw_stats = mac->hw_stats;
443 unsigned int start;
444
445 if (netif_running(dev) && netif_device_present(dev)) {
446 if (spin_trylock(&hw_stats->stats_lock)) {
447 mtk_stats_update_mac(mac);
448 spin_unlock(&hw_stats->stats_lock);
449 }
450 }
451
452 do {
453 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
454 storage->rx_packets = hw_stats->rx_packets;
455 storage->tx_packets = hw_stats->tx_packets;
456 storage->rx_bytes = hw_stats->rx_bytes;
457 storage->tx_bytes = hw_stats->tx_bytes;
458 storage->collisions = hw_stats->tx_collisions;
459 storage->rx_length_errors = hw_stats->rx_short_errors +
460 hw_stats->rx_long_errors;
461 storage->rx_over_errors = hw_stats->rx_overflow;
462 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
463 storage->rx_errors = hw_stats->rx_checksum_errors;
464 storage->tx_aborted_errors = hw_stats->tx_skip;
465 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
466
467 storage->tx_errors = dev->stats.tx_errors;
468 storage->rx_dropped = dev->stats.rx_dropped;
469 storage->tx_dropped = dev->stats.tx_dropped;
470
471 return storage;
472}
473
474static inline int mtk_max_frag_size(int mtu)
475{
476 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
477 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
478 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
479
480 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
481 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
482}
483
484static inline int mtk_max_buf_size(int frag_size)
485{
486 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
487 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
488
489 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
490
491 return buf_size;
492}
493
494static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
495 struct mtk_rx_dma *dma_rxd)
496{
497 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
498 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
499 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
500 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
501}
502
503/* the qdma core needs scratch memory to be setup */
504static int mtk_init_fq_dma(struct mtk_eth *eth)
505{
605e4fe4 506 dma_addr_t phy_ring_tail;
656e7052
JC		 507 int cnt = MTK_DMA_SIZE;
508 dma_addr_t dma_addr;
509 int i;
510
511 eth->scratch_ring = dma_alloc_coherent(eth->dev,
512 cnt * sizeof(struct mtk_tx_dma),
605e4fe4 513 &eth->phy_scratch_ring,
656e7052
JC		 514 GFP_ATOMIC | __GFP_ZERO);
515 if (unlikely(!eth->scratch_ring))
516 return -ENOMEM;
517
518 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
519 GFP_KERNEL);
562c5a70
JC		 520 if (unlikely(!eth->scratch_head))
521 return -ENOMEM;
522
656e7052
JC		 523 dma_addr = dma_map_single(eth->dev,
524 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
525 DMA_FROM_DEVICE);
526 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
527 return -ENOMEM;
528
529 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
605e4fe4 530 phy_ring_tail = eth->phy_scratch_ring +
656e7052
JC		 531 (sizeof(struct mtk_tx_dma) * (cnt - 1));
532
533 for (i = 0; i < cnt; i++) {
534 eth->scratch_ring[i].txd1 =
535 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
536 if (i < cnt - 1)
605e4fe4 537 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
656e7052
JC		 538 ((i + 1) * sizeof(struct mtk_tx_dma)));
539 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
540 }
541
605e4fe4 542 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
656e7052
JC		 543 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
544 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
545 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
546
547 return 0;
548}
549
550static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
551{
552 void *ret = ring->dma;
553
554 return ret + (desc - ring->phys);
555}
556
557static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
558 struct mtk_tx_dma *txd)
559{
560 int idx = txd - ring->dma;
561
562 return &ring->buf[idx];
563}
564
55a4e778 565static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
656e7052
JC		 566{
567 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
55a4e778 568 dma_unmap_single(eth->dev,
656e7052
JC		 569 dma_unmap_addr(tx_buf, dma_addr0),
570 dma_unmap_len(tx_buf, dma_len0),
571 DMA_TO_DEVICE);
572 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
55a4e778 573 dma_unmap_page(eth->dev,
656e7052
JC		 574 dma_unmap_addr(tx_buf, dma_addr0),
575 dma_unmap_len(tx_buf, dma_len0),
576 DMA_TO_DEVICE);
577 }
578 tx_buf->flags = 0;
579 if (tx_buf->skb &&
580 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
581 dev_kfree_skb_any(tx_buf->skb);
582 tx_buf->skb = NULL;
583}
584
585static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
586 int tx_num, struct mtk_tx_ring *ring, bool gso)
587{
588 struct mtk_mac *mac = netdev_priv(dev);
589 struct mtk_eth *eth = mac->hw;
590 struct mtk_tx_dma *itxd, *txd;
591 struct mtk_tx_buf *tx_buf;
656e7052
JC		 592 dma_addr_t mapped_addr;
593 unsigned int nr_frags;
594 int i, n_desc = 1;
c6f1dc4d 595 u32 txd4 = 0, fport;
656e7052
JC		 596
597 itxd = ring->next_free;
598 if (itxd == ring->last_free)
599 return -ENOMEM;
600
601 /* set the forward port */
c6f1dc4d
SW		 602 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
603 txd4 |= fport;
656e7052
JC		 604
605 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
606 memset(tx_buf, 0, sizeof(*tx_buf));
607
608 if (gso)
609 txd4 |= TX_DMA_TSO;
610
611 /* TX Checksum offload */
612 if (skb->ip_summed == CHECKSUM_PARTIAL)
613 txd4 |= TX_DMA_CHKSUM;
614
615 /* VLAN header offload */
616 if (skb_vlan_tag_present(skb))
617 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
618
55a4e778 619 mapped_addr = dma_map_single(eth->dev, skb->data,
656e7052 620 skb_headlen(skb), DMA_TO_DEVICE);
55a4e778 621 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
656e7052
JC		 622 return -ENOMEM;
623
656e7052
JC		 624 WRITE_ONCE(itxd->txd1, mapped_addr);
625 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
626 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
627 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
628
629 /* TX SG offload */
630 txd = itxd;
631 nr_frags = skb_shinfo(skb)->nr_frags;
632 for (i = 0; i < nr_frags; i++) {
633 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
634 unsigned int offset = 0;
635 int frag_size = skb_frag_size(frag);
636
637 while (frag_size) {
638 bool last_frag = false;
639 unsigned int frag_map_size;
640
641 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
642 if (txd == ring->last_free)
643 goto err_dma;
644
645 n_desc++;
646 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
55a4e778 647 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
656e7052
JC		 648 frag_map_size,
649 DMA_TO_DEVICE);
55a4e778 650 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
656e7052
JC		 651 goto err_dma;
652
653 if (i == nr_frags - 1 &&
654 (frag_size - frag_map_size) == 0)
655 last_frag = true;
656
657 WRITE_ONCE(txd->txd1, mapped_addr);
658 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
659 TX_DMA_PLEN0(frag_map_size) |
369f0453 660 last_frag * TX_DMA_LS0));
c6f1dc4d 661 WRITE_ONCE(txd->txd4, fport);
656e7052
JC		 662
663 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
664 tx_buf = mtk_desc_to_tx_buf(ring, txd);
665 memset(tx_buf, 0, sizeof(*tx_buf));
666
667 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
668 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
669 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
670 frag_size -= frag_map_size;
671 offset += frag_map_size;
672 }
673 }
674
675 /* store skb to cleanup */
676 tx_buf->skb = skb;
677
678 WRITE_ONCE(itxd->txd4, txd4);
679 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
680 (!nr_frags * TX_DMA_LS0)));
681
656e7052
JC		 682 netdev_sent_queue(dev, skb->len);
683 skb_tx_timestamp(skb);
684
685 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
686 atomic_sub(n_desc, &ring->free_count);
687
688 /* make sure that all changes to the dma ring are flushed before we
689 * continue
690 */
691 wmb();
692
693 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
694 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
695
696 return 0;
697
698err_dma:
699 do {
2fae723c 700 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
656e7052
JC		 701
702 /* unmap dma */
55a4e778 703 mtk_tx_unmap(eth, tx_buf);
656e7052
JC		 704
705 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
706 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
707 } while (itxd != txd);
708
709 return -ENOMEM;
710}
711
712static inline int mtk_cal_txd_req(struct sk_buff *skb)
713{
714 int i, nfrags;
715 struct skb_frag_struct *frag;
716
717 nfrags = 1;
718 if (skb_is_gso(skb)) {
719 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
720 frag = &skb_shinfo(skb)->frags[i];
721 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
722 }
723 } else {
724 nfrags += skb_shinfo(skb)->nr_frags;
725 }
726
beeb4ca4 727 return nfrags;
656e7052
JC		 728}
729
ad3cba98
JC		 730static int mtk_queue_stopped(struct mtk_eth *eth)
731{
732 int i;
733
734 for (i = 0; i < MTK_MAC_COUNT; i++) {
735 if (!eth->netdev[i])
736 continue;
737 if (netif_queue_stopped(eth->netdev[i]))
738 return 1;
739 }
740
741 return 0;
742}
743
13c822f6
JC		 744static void mtk_wake_queue(struct mtk_eth *eth)
745{
746 int i;
747
748 for (i = 0; i < MTK_MAC_COUNT; i++) {
749 if (!eth->netdev[i])
750 continue;
751 netif_wake_queue(eth->netdev[i]);
752 }
753}
754
755static void mtk_stop_queue(struct mtk_eth *eth)
756{
757 int i;
758
759 for (i = 0; i < MTK_MAC_COUNT; i++) {
760 if (!eth->netdev[i])
761 continue;
762 netif_stop_queue(eth->netdev[i]);
763 }
764}
765
656e7052
JC		 766static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
767{
768 struct mtk_mac *mac = netdev_priv(dev);
769 struct mtk_eth *eth = mac->hw;
770 struct mtk_tx_ring *ring = &eth->tx_ring;
771 struct net_device_stats *stats = &dev->stats;
34c2e4c9 772 unsigned long flags;
656e7052
JC		 773 bool gso = false;
774 int tx_num;
775
34c2e4c9
JC		 776 /* normally we can rely on the stack not calling this more than once,
777 * however we have 2 queues running on the same ring so we need to lock
778 * the ring access
779 */
780 spin_lock_irqsave(&eth->page_lock, flags);
781
656e7052
JC		 782 tx_num = mtk_cal_txd_req(skb);
783 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
13c822f6 784 mtk_stop_queue(eth);
656e7052
JC		 785 netif_err(eth, tx_queued, dev,
786 "Tx Ring full when queue awake!\n");
34c2e4c9 787 spin_unlock_irqrestore(&eth->page_lock, flags);
656e7052
JC		 788 return NETDEV_TX_BUSY;
789 }
790
791 /* TSO: fill MSS info in tcp checksum field */
792 if (skb_is_gso(skb)) {
793 if (skb_cow_head(skb, 0)) {
794 netif_warn(eth, tx_err, dev,
795 "GSO expand head fail.\n");
796 goto drop;
797 }
798
799 if (skb_shinfo(skb)->gso_type &
800 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
801 gso = true;
802 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
803 }
804 }
805
806 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
807 goto drop;
808
82c6544d 809 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
13c822f6 810 mtk_stop_queue(eth);
82c6544d 811
34c2e4c9 812 spin_unlock_irqrestore(&eth->page_lock, flags);
656e7052
JC		 813
814 return NETDEV_TX_OK;
815
816drop:
34c2e4c9 817 spin_unlock_irqrestore(&eth->page_lock, flags);
656e7052
JC		 818 stats->tx_dropped++;
819 dev_kfree_skb(skb);
820 return NETDEV_TX_OK;
821}
822
823static int mtk_poll_rx(struct napi_struct *napi, int budget,
eece71e8 824 struct mtk_eth *eth)
656e7052
JC		 825{
826 struct mtk_rx_ring *ring = &eth->rx_ring;
827 int idx = ring->calc_idx;
828 struct sk_buff *skb;
829 u8 *data, *new_data;
830 struct mtk_rx_dma *rxd, trxd;
831 int done = 0;
832
833 while (done < budget) {
834 struct net_device *netdev;
835 unsigned int pktlen;
836 dma_addr_t dma_addr;
837 int mac = 0;
838
839 idx = NEXT_RX_DESP_IDX(idx);
840 rxd = &ring->dma[idx];
841 data = ring->data[idx];
842
843 mtk_rx_get_desc(&trxd, rxd);
844 if (!(trxd.rxd2 & RX_DMA_DONE))
845 break;
846
847 /* find out which mac the packet come from. values start at 1 */
848 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
849 RX_DMA_FPORT_MASK;
850 mac--;
851
852 netdev = eth->netdev[mac];
853
854 /* alloc new buffer */
855 new_data = napi_alloc_frag(ring->frag_size);
856 if (unlikely(!new_data)) {
857 netdev->stats.rx_dropped++;
858 goto release_desc;
859 }
55a4e778 860 dma_addr = dma_map_single(eth->dev,
656e7052
JC		 861 new_data + NET_SKB_PAD,
862 ring->buf_size,
863 DMA_FROM_DEVICE);
55a4e778 864 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
656e7052 865 skb_free_frag(new_data);
94321a9f 866 netdev->stats.rx_dropped++;
656e7052
JC		 867 goto release_desc;
868 }
869
870 /* receive data */
871 skb = build_skb(data, ring->frag_size);
872 if (unlikely(!skb)) {
1b430799 873 skb_free_frag(new_data);
94321a9f 874 netdev->stats.rx_dropped++;
656e7052
JC		 875 goto release_desc;
876 }
877 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
878
55a4e778 879 dma_unmap_single(eth->dev, trxd.rxd1,
656e7052
JC		 880 ring->buf_size, DMA_FROM_DEVICE);
881 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
882 skb->dev = netdev;
883 skb_put(skb, pktlen);
884 if (trxd.rxd4 & RX_DMA_L4_VALID)
885 skb->ip_summed = CHECKSUM_UNNECESSARY;
886 else
887 skb_checksum_none_assert(skb);
888 skb->protocol = eth_type_trans(skb, netdev);
889
890 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
891 RX_DMA_VID(trxd.rxd3))
892 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
893 RX_DMA_VID(trxd.rxd3));
894 napi_gro_receive(napi, skb);
895
896 ring->data[idx] = new_data;
897 rxd->rxd1 = (unsigned int)dma_addr;
898
899release_desc:
900 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
901
902 ring->calc_idx = idx;
903 /* make sure that all changes to the dma ring are flushed before
904 * we continue
905 */
906 wmb();
907 mtk_w32(eth, ring->calc_idx, MTK_QRX_CRX_IDX0);
908 done++;
909 }
910
911 if (done < budget)
eece71e8 912 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS);
656e7052
JC		 913
914 return done;
915}
916
80673029 917static int mtk_poll_tx(struct mtk_eth *eth, int budget)
656e7052
JC		 918{
919 struct mtk_tx_ring *ring = &eth->tx_ring;
920 struct mtk_tx_dma *desc;
921 struct sk_buff *skb;
922 struct mtk_tx_buf *tx_buf;
80673029 923 unsigned int done[MTK_MAX_DEVS];
656e7052
JC		 924 unsigned int bytes[MTK_MAX_DEVS];
925 u32 cpu, dma;
926 static int condition;
80673029 927 int total = 0, i;
656e7052
JC		 928
929 memset(done, 0, sizeof(done));
930 memset(bytes, 0, sizeof(bytes));
931
932 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
933 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
934
935 desc = mtk_qdma_phys_to_virt(ring, cpu);
936
937 while ((cpu != dma) && budget) {
938 u32 next_cpu = desc->txd2;
939 int mac;
940
941 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
942 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
943 break;
944
945 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
946 TX_DMA_FPORT_MASK;
947 mac--;
948
949 tx_buf = mtk_desc_to_tx_buf(ring, desc);
950 skb = tx_buf->skb;
951 if (!skb) {
952 condition = 1;
953 break;
954 }
955
956 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
957 bytes[mac] += skb->len;
958 done[mac]++;
959 budget--;
960 }
55a4e778 961 mtk_tx_unmap(eth, tx_buf);
656e7052 962
656e7052
JC		 963 ring->last_free = desc;
964 atomic_inc(&ring->free_count);
965
966 cpu = next_cpu;
967 }
968
969 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
970
971 for (i = 0; i < MTK_MAC_COUNT; i++) {
972 if (!eth->netdev[i] || !done[i])
973 continue;
974 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
975 total += done[i];
976 }
977
ad3cba98
JC		 978 if (mtk_queue_stopped(eth) &&
979 (atomic_read(&ring->free_count) > ring->thresh))
13c822f6 980 mtk_wake_queue(eth);
656e7052
JC		 981
982 return total;
983}
984
80673029 985static void mtk_handle_status_irq(struct mtk_eth *eth)
656e7052 986{
80673029 987 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
656e7052 988
eece71e8 989 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
656e7052 990 mtk_stats_update(eth);
eece71e8
JC		 991 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
992 MTK_INT_STATUS2);
656e7052 993 }
80673029
JC		 994}
995
996static int mtk_napi_tx(struct napi_struct *napi, int budget)
997{
998 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
999 u32 status, mask;
1000 int tx_done = 0;
1001
1002 mtk_handle_status_irq(eth);
1003 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
1004 tx_done = mtk_poll_tx(eth, budget);
1005
1006 if (unlikely(netif_msg_intr(eth))) {
1007 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1008 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1009 dev_info(eth->dev,
1010 "done tx %d, intr 0x%08x/0x%x\n",
1011 tx_done, status, mask);
1012 }
1013
1014 if (tx_done == budget)
1015 return budget;
1016
1017 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1018 if (status & MTK_TX_DONE_INT)
1019 return budget;
1020
1021 napi_complete(napi);
1022 mtk_irq_enable(eth, MTK_TX_DONE_INT);
1023
1024 return tx_done;
1025}
1026
1027static int mtk_napi_rx(struct napi_struct *napi, int budget)
1028{
1029 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1030 u32 status, mask;
1031 int rx_done = 0;
1032
1033 mtk_handle_status_irq(eth);
1034 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS);
1035 rx_done = mtk_poll_rx(napi, budget, eth);
656e7052
JC		 1036
1037 if (unlikely(netif_msg_intr(eth))) {
80673029 1038 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
656e7052 1039 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
80673029
JC		 1040 dev_info(eth->dev,
1041 "done rx %d, intr 0x%08x/0x%x\n",
1042 rx_done, status, mask);
656e7052
JC		 1043 }
1044
80673029 1045 if (rx_done == budget)
656e7052
JC		 1046 return budget;
1047
1048 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
80673029 1049 if (status & MTK_RX_DONE_INT)
656e7052
JC		 1050 return budget;
1051
1052 napi_complete(napi);
80673029 1053 mtk_irq_enable(eth, MTK_RX_DONE_INT);
656e7052
JC		 1054
1055 return rx_done;
1056}
1057
1058static int mtk_tx_alloc(struct mtk_eth *eth)
1059{
1060 struct mtk_tx_ring *ring = &eth->tx_ring;
1061 int i, sz = sizeof(*ring->dma);
1062
1063 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1064 GFP_KERNEL);
1065 if (!ring->buf)
1066 goto no_tx_mem;
1067
1068 ring->dma = dma_alloc_coherent(eth->dev,
1069 MTK_DMA_SIZE * sz,
1070 &ring->phys,
1071 GFP_ATOMIC | __GFP_ZERO);
1072 if (!ring->dma)
1073 goto no_tx_mem;
1074
1075 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
1076 for (i = 0; i < MTK_DMA_SIZE; i++) {
1077 int next = (i + 1) % MTK_DMA_SIZE;
1078 u32 next_ptr = ring->phys + next * sz;
1079
1080 ring->dma[i].txd2 = next_ptr;
1081 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1082 }
1083
1084 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1085 ring->next_free = &ring->dma[0];
12c97c13 1086 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
04698ccc 1087 ring->thresh = MAX_SKB_FRAGS;
656e7052
JC		 1088
1089 /* make sure that all changes to the dma ring are flushed before we
1090 * continue
1091 */
1092 wmb();
1093
1094 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1095 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1096 mtk_w32(eth,
1097 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1098 MTK_QTX_CRX_PTR);
1099 mtk_w32(eth,
1100 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1101 MTK_QTX_DRX_PTR);
1102
1103 return 0;
1104
1105no_tx_mem:
1106 return -ENOMEM;
1107}
1108
1109static void mtk_tx_clean(struct mtk_eth *eth)
1110{
1111 struct mtk_tx_ring *ring = &eth->tx_ring;
1112 int i;
1113
1114 if (ring->buf) {
1115 for (i = 0; i < MTK_DMA_SIZE; i++)
55a4e778 1116 mtk_tx_unmap(eth, &ring->buf[i]);
656e7052
JC		 1117 kfree(ring->buf);
1118 ring->buf = NULL;
1119 }
1120
1121 if (ring->dma) {
1122 dma_free_coherent(eth->dev,
1123 MTK_DMA_SIZE * sizeof(*ring->dma),
1124 ring->dma,
1125 ring->phys);
1126 ring->dma = NULL;
1127 }
1128}
1129
1130static int mtk_rx_alloc(struct mtk_eth *eth)
1131{
1132 struct mtk_rx_ring *ring = &eth->rx_ring;
1133 int i;
1134
1135 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN);
1136 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1137 ring->data = kcalloc(MTK_DMA_SIZE, sizeof(*ring->data),
1138 GFP_KERNEL);
1139 if (!ring->data)
1140 return -ENOMEM;
1141
1142 for (i = 0; i < MTK_DMA_SIZE; i++) {
1143 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1144 if (!ring->data[i])
1145 return -ENOMEM;
1146 }
1147
1148 ring->dma = dma_alloc_coherent(eth->dev,
1149 MTK_DMA_SIZE * sizeof(*ring->dma),
1150 &ring->phys,
1151 GFP_ATOMIC | __GFP_ZERO);
1152 if (!ring->dma)
1153 return -ENOMEM;
1154
1155 for (i = 0; i < MTK_DMA_SIZE; i++) {
1156 dma_addr_t dma_addr = dma_map_single(eth->dev,
1157 ring->data[i] + NET_SKB_PAD,
1158 ring->buf_size,
1159 DMA_FROM_DEVICE);
1160 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1161 return -ENOMEM;
1162 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1163
1164 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1165 }
1166 ring->calc_idx = MTK_DMA_SIZE - 1;
1167 /* make sure that all changes to the dma ring are flushed before we
1168 * continue
1169 */
1170 wmb();
1171
1172 mtk_w32(eth, eth->rx_ring.phys, MTK_QRX_BASE_PTR0);
1173 mtk_w32(eth, MTK_DMA_SIZE, MTK_QRX_MAX_CNT0);
1174 mtk_w32(eth, eth->rx_ring.calc_idx, MTK_QRX_CRX_IDX0);
1175 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_QDMA_RST_IDX);
1176 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1177
1178 return 0;
1179}
1180
1181static void mtk_rx_clean(struct mtk_eth *eth)
1182{
1183 struct mtk_rx_ring *ring = &eth->rx_ring;
1184 int i;
1185
1186 if (ring->data && ring->dma) {
1187 for (i = 0; i < MTK_DMA_SIZE; i++) {
1188 if (!ring->data[i])
1189 continue;
1190 if (!ring->dma[i].rxd1)
1191 continue;
1192 dma_unmap_single(eth->dev,
1193 ring->dma[i].rxd1,
1194 ring->buf_size,
1195 DMA_FROM_DEVICE);
1196 skb_free_frag(ring->data[i]);
1197 }
1198 kfree(ring->data);
1199 ring->data = NULL;
1200 }
1201
1202 if (ring->dma) {
1203 dma_free_coherent(eth->dev,
1204 MTK_DMA_SIZE * sizeof(*ring->dma),
1205 ring->dma,
1206 ring->phys);
1207 ring->dma = NULL;
1208 }
1209}
1210
1211/* wait for DMA to finish whatever it is doing before we start using it again */
1212static int mtk_dma_busy_wait(struct mtk_eth *eth)
1213{
1214 unsigned long t_start = jiffies;
1215
1216 while (1) {
1217 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1218 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1219 return 0;
1220 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1221 break;
1222 }
1223
1224 dev_err(eth->dev, "DMA init timeout\n");
1225 return -1;
1226}
1227
1228static int mtk_dma_init(struct mtk_eth *eth)
1229{
1230 int err;
1231
1232 if (mtk_dma_busy_wait(eth))
1233 return -EBUSY;
1234
1235 /* QDMA needs scratch memory for internal reordering of the
1236 * descriptors
1237 */
1238 err = mtk_init_fq_dma(eth);
1239 if (err)
1240 return err;
1241
1242 err = mtk_tx_alloc(eth);
1243 if (err)
1244 return err;
1245
1246 err = mtk_rx_alloc(eth);
1247 if (err)
1248 return err;
1249
1250 /* Enable random early drop and set drop threshold automatically */
1251 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1252 MTK_QDMA_FC_THRES);
1253 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1254
1255 return 0;
1256}
1257
1258static void mtk_dma_free(struct mtk_eth *eth)
1259{
1260 int i;
1261
1262 for (i = 0; i < MTK_MAC_COUNT; i++)
1263 if (eth->netdev[i])
1264 netdev_reset_queue(eth->netdev[i]);
605e4fe4
JC		 1265 if (eth->scratch_ring) {
1266 dma_free_coherent(eth->dev,
1267 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1268 eth->scratch_ring,
1269 eth->phy_scratch_ring);
1270 eth->scratch_ring = NULL;
1271 eth->phy_scratch_ring = 0;
1272 }
656e7052
JC		 1273 mtk_tx_clean(eth);
1274 mtk_rx_clean(eth);
1275 kfree(eth->scratch_head);
1276}
1277
1278static void mtk_tx_timeout(struct net_device *dev)
1279{
1280 struct mtk_mac *mac = netdev_priv(dev);
1281 struct mtk_eth *eth = mac->hw;
1282
1283 eth->netdev[mac->id]->stats.tx_errors++;
1284 netif_err(eth, tx_err, dev,
1285 "transmit timed out\n");
7c78b4ad 1286 schedule_work(&eth->pending_work);
656e7052
JC		 1287}
1288
80673029 1289static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
656e7052
JC		 1290{
1291 struct mtk_eth *eth = _eth;
656e7052 1292
80673029
JC		 1293 if (likely(napi_schedule_prep(&eth->rx_napi))) {
1294 __napi_schedule(&eth->rx_napi);
1295 mtk_irq_disable(eth, MTK_RX_DONE_INT);
1296 }
656e7052 1297
80673029
JC		 1298 return IRQ_HANDLED;
1299}
1300
1301static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1302{
1303 struct mtk_eth *eth = _eth;
1304
1305 if (likely(napi_schedule_prep(&eth->tx_napi))) {
1306 __napi_schedule(&eth->tx_napi);
1307 mtk_irq_disable(eth, MTK_TX_DONE_INT);
656e7052 1308 }
656e7052
JC		 1309
1310 return IRQ_HANDLED;
1311}
1312
1313#ifdef CONFIG_NET_POLL_CONTROLLER
1314static void mtk_poll_controller(struct net_device *dev)
1315{
1316 struct mtk_mac *mac = netdev_priv(dev);
1317 struct mtk_eth *eth = mac->hw;
1318 u32 int_mask = MTK_TX_DONE_INT | MTK_RX_DONE_INT;
1319
1320 mtk_irq_disable(eth, int_mask);
8186f6e3 1321 mtk_handle_irq_rx(eth->irq[2], dev);
656e7052
JC		 1322 mtk_irq_enable(eth, int_mask);
1323}
1324#endif
1325
1326static int mtk_start_dma(struct mtk_eth *eth)
1327{
1328 int err;
1329
1330 err = mtk_dma_init(eth);
1331 if (err) {
1332 mtk_dma_free(eth);
1333 return err;
1334 }
1335
1336 mtk_w32(eth,
1337 MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN |
1338 MTK_RX_2B_OFFSET | MTK_DMA_SIZE_16DWORDS |
6675086d 1339 MTK_RX_BT_32DWORDS | MTK_NDP_CO_PRO,
656e7052
JC		 1340 MTK_QDMA_GLO_CFG);
1341
1342 return 0;
1343}
1344
1345static int mtk_open(struct net_device *dev)
1346{
1347 struct mtk_mac *mac = netdev_priv(dev);
1348 struct mtk_eth *eth = mac->hw;
1349
1350 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1351 if (!atomic_read(&eth->dma_refcnt)) {
1352 int err = mtk_start_dma(eth);
1353
1354 if (err)
1355 return err;
1356
80673029 1357 napi_enable(&eth->tx_napi);
656e7052
JC		 1358 napi_enable(&eth->rx_napi);
1359 mtk_irq_enable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1360 }
1361 atomic_inc(&eth->dma_refcnt);
1362
1363 phy_start(mac->phy_dev);
1364 netif_start_queue(dev);
1365
1366 return 0;
1367}
1368
1369static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1370{
1371 unsigned long flags;
1372 u32 val;
1373 int i;
1374
1375 /* stop the dma engine */
1376 spin_lock_irqsave(&eth->page_lock, flags);
1377 val = mtk_r32(eth, glo_cfg);
1378 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1379 glo_cfg);
1380 spin_unlock_irqrestore(&eth->page_lock, flags);
1381
1382 /* wait for dma stop */
1383 for (i = 0; i < 10; i++) {
1384 val = mtk_r32(eth, glo_cfg);
1385 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1386 msleep(20);
1387 continue;
1388 }
1389 break;
1390 }
1391}
1392
1393static int mtk_stop(struct net_device *dev)
1394{
1395 struct mtk_mac *mac = netdev_priv(dev);
1396 struct mtk_eth *eth = mac->hw;
1397
1398 netif_tx_disable(dev);
1399 phy_stop(mac->phy_dev);
1400
1401 /* only shutdown DMA if this is the last user */
1402 if (!atomic_dec_and_test(&eth->dma_refcnt))
1403 return 0;
1404
1405 mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
80673029 1406 napi_disable(&eth->tx_napi);
656e7052
JC		 1407 napi_disable(&eth->rx_napi);
1408
1409 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1410
1411 mtk_dma_free(eth);
1412
1413 return 0;
1414}
1415
1416static int __init mtk_hw_init(struct mtk_eth *eth)
1417{
1418 int err, i;
1419
1420 /* reset the frame engine */
1421 reset_control_assert(eth->rstc);
1422 usleep_range(10, 20);
1423 reset_control_deassert(eth->rstc);
1424 usleep_range(10, 20);
1425
1426 /* Set GE2 driving and slew rate */
1427 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1428
1429 /* set GE2 TDSEL */
1430 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1431
1432 /* set GE2 TUNE */
1433 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1434
1435 /* GE1, Force 1000M/FD, FC ON */
1436 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1437
1438 /* GE2, Force 1000M/FD, FC ON */
1439 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1440
1441 /* Enable RX VLan Offloading */
1442 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1443
80673029
JC		 1444 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
1445 dev_name(eth->dev), eth);
1446 if (err)
1447 return err;
1448 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
656e7052
JC		 1449 dev_name(eth->dev), eth);
1450 if (err)
1451 return err;
1452
1453 err = mtk_mdio_init(eth);
1454 if (err)
1455 return err;
1456
1457 /* disable delay and normal interrupt */
1458 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
2ff0bb61 1459 mtk_irq_disable(eth, ~0);
656e7052
JC		 1460 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1461 mtk_w32(eth, 0, MTK_RST_GL);
1462
1463 /* FE int grouping */
80673029
JC		 1464 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1465 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1466 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1467 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1468 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
656e7052
JC		 1469
1470 for (i = 0; i < 2; i++) {
1471 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1472
1473 /* setup the forward port to send frame to QDMA */
1474 val &= ~0xffff;
1475 val |= 0x5555;
1476
1477 /* Enable RX checksum */
1478 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1479
1480 /* setup the mac dma */
1481 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1482 }
1483
1484 return 0;
1485}
1486
1487static int __init mtk_init(struct net_device *dev)
1488{
1489 struct mtk_mac *mac = netdev_priv(dev);
1490 struct mtk_eth *eth = mac->hw;
1491 const char *mac_addr;
1492
1493 mac_addr = of_get_mac_address(mac->of_node);
1494 if (mac_addr)
1495 ether_addr_copy(dev->dev_addr, mac_addr);
1496
1497 /* If the mac address is invalid, use random mac address */
1498 if (!is_valid_ether_addr(dev->dev_addr)) {
1499 random_ether_addr(dev->dev_addr);
1500 dev_err(eth->dev, "generated random MAC address %pM\n",
1501 dev->dev_addr);
1502 dev->addr_assign_type = NET_ADDR_RANDOM;
1503 }
1504
1505 return mtk_phy_connect(mac);
1506}
1507
1508static void mtk_uninit(struct net_device *dev)
1509{
1510 struct mtk_mac *mac = netdev_priv(dev);
1511 struct mtk_eth *eth = mac->hw;
1512
1513 phy_disconnect(mac->phy_dev);
656e7052 1514 mtk_irq_disable(eth, ~0);
656e7052
JC		 1515}
1516
1517static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1518{
1519 struct mtk_mac *mac = netdev_priv(dev);
1520
1521 switch (cmd) {
1522 case SIOCGMIIPHY:
1523 case SIOCGMIIREG:
1524 case SIOCSMIIREG:
1525 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1526 default:
1527 break;
1528 }
1529
1530 return -EOPNOTSUPP;
1531}
1532
1533static void mtk_pending_work(struct work_struct *work)
1534{
7c78b4ad 1535 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
e7d425dc
JC		 1536 int err, i;
1537 unsigned long restart = 0;
656e7052
JC		 1538
1539 rtnl_lock();
656e7052 1540
e7d425dc
JC		 1541 /* stop all devices to make sure that dma is properly shut down */
1542 for (i = 0; i < MTK_MAC_COUNT; i++) {
7c78b4ad 1543 if (!eth->netdev[i])
e7d425dc
JC		 1544 continue;
1545 mtk_stop(eth->netdev[i]);
1546 __set_bit(i, &restart);
1547 }
1548
1549 /* restart DMA and enable IRQs */
1550 for (i = 0; i < MTK_MAC_COUNT; i++) {
1551 if (!test_bit(i, &restart))
1552 continue;
1553 err = mtk_open(eth->netdev[i]);
1554 if (err) {
1555 netif_alert(eth, ifup, eth->netdev[i],
1556 "Driver up/down cycle failed, closing device.\n");
1557 dev_close(eth->netdev[i]);
1558 }
656e7052
JC		 1559 }
1560 rtnl_unlock();
1561}
1562
1563static int mtk_cleanup(struct mtk_eth *eth)
1564{
1565 int i;
1566
1567 for (i = 0; i < MTK_MAC_COUNT; i++) {
656e7052
JC		 1568 if (!eth->netdev[i])
1569 continue;
1570
1571 unregister_netdev(eth->netdev[i]);
1572 free_netdev(eth->netdev[i]);
656e7052 1573 }
7c78b4ad 1574 cancel_work_sync(&eth->pending_work);
656e7052
JC		 1575
1576 return 0;
1577}
1578
1579static int mtk_get_settings(struct net_device *dev,
1580 struct ethtool_cmd *cmd)
1581{
1582 struct mtk_mac *mac = netdev_priv(dev);
1583 int err;
1584
1585 err = phy_read_status(mac->phy_dev);
1586 if (err)
1587 return -ENODEV;
1588
1589 return phy_ethtool_gset(mac->phy_dev, cmd);
1590}
1591
1592static int mtk_set_settings(struct net_device *dev,
1593 struct ethtool_cmd *cmd)
1594{
1595 struct mtk_mac *mac = netdev_priv(dev);
1596
1597 if (cmd->phy_address != mac->phy_dev->mdio.addr) {
1598 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
1599 cmd->phy_address);
1600 if (!mac->phy_dev)
1601 return -ENODEV;
1602 }
1603
1604 return phy_ethtool_sset(mac->phy_dev, cmd);
1605}
1606
1607static void mtk_get_drvinfo(struct net_device *dev,
1608 struct ethtool_drvinfo *info)
1609{
1610 struct mtk_mac *mac = netdev_priv(dev);
1611
1612 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
1613 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
1614 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
1615}
1616
1617static u32 mtk_get_msglevel(struct net_device *dev)
1618{
1619 struct mtk_mac *mac = netdev_priv(dev);
1620
1621 return mac->hw->msg_enable;
1622}
1623
1624static void mtk_set_msglevel(struct net_device *dev, u32 value)
1625{
1626 struct mtk_mac *mac = netdev_priv(dev);
1627
1628 mac->hw->msg_enable = value;
1629}
1630
1631static int mtk_nway_reset(struct net_device *dev)
1632{
1633 struct mtk_mac *mac = netdev_priv(dev);
1634
1635 return genphy_restart_aneg(mac->phy_dev);
1636}
1637
1638static u32 mtk_get_link(struct net_device *dev)
1639{
1640 struct mtk_mac *mac = netdev_priv(dev);
1641 int err;
1642
1643 err = genphy_update_link(mac->phy_dev);
1644 if (err)
1645 return ethtool_op_get_link(dev);
1646
1647 return mac->phy_dev->link;
1648}
1649
1650static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1651{
1652 int i;
1653
1654 switch (stringset) {
1655 case ETH_SS_STATS:
1656 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
1657 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
1658 data += ETH_GSTRING_LEN;
1659 }
1660 break;
1661 }
1662}
1663
1664static int mtk_get_sset_count(struct net_device *dev, int sset)
1665{
1666 switch (sset) {
1667 case ETH_SS_STATS:
1668 return ARRAY_SIZE(mtk_ethtool_stats);
1669 default:
1670 return -EOPNOTSUPP;
1671 }
1672}
1673
1674static void mtk_get_ethtool_stats(struct net_device *dev,
1675 struct ethtool_stats *stats, u64 *data)
1676{
1677 struct mtk_mac *mac = netdev_priv(dev);
1678 struct mtk_hw_stats *hwstats = mac->hw_stats;
1679 u64 *data_src, *data_dst;
1680 unsigned int start;
1681 int i;
1682
1683 if (netif_running(dev) && netif_device_present(dev)) {
1684 if (spin_trylock(&hwstats->stats_lock)) {
1685 mtk_stats_update_mac(mac);
1686 spin_unlock(&hwstats->stats_lock);
1687 }
1688 }
1689
1690 do {
1691 data_src = (u64*)hwstats;
1692 data_dst = data;
1693 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
1694
1695 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
1696 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
1697 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
1698}
1699
1700static struct ethtool_ops mtk_ethtool_ops = {
1701 .get_settings = mtk_get_settings,
1702 .set_settings = mtk_set_settings,
1703 .get_drvinfo = mtk_get_drvinfo,
1704 .get_msglevel = mtk_get_msglevel,
1705 .set_msglevel = mtk_set_msglevel,
1706 .nway_reset = mtk_nway_reset,
1707 .get_link = mtk_get_link,
1708 .get_strings = mtk_get_strings,
1709 .get_sset_count = mtk_get_sset_count,
1710 .get_ethtool_stats = mtk_get_ethtool_stats,
1711};
1712
1713static const struct net_device_ops mtk_netdev_ops = {
1714 .ndo_init = mtk_init,
1715 .ndo_uninit = mtk_uninit,
1716 .ndo_open = mtk_open,
1717 .ndo_stop = mtk_stop,
1718 .ndo_start_xmit = mtk_start_xmit,
1719 .ndo_set_mac_address = mtk_set_mac_address,
1720 .ndo_validate_addr = eth_validate_addr,
1721 .ndo_do_ioctl = mtk_do_ioctl,
1722 .ndo_change_mtu = eth_change_mtu,
1723 .ndo_tx_timeout = mtk_tx_timeout,
1724 .ndo_get_stats64 = mtk_get_stats64,
1725#ifdef CONFIG_NET_POLL_CONTROLLER
1726 .ndo_poll_controller = mtk_poll_controller,
1727#endif
1728};
1729
1730static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
1731{
1732 struct mtk_mac *mac;
1733 const __be32 *_id = of_get_property(np, "reg", NULL);
1734 int id, err;
1735
1736 if (!_id) {
1737 dev_err(eth->dev, "missing mac id\n");
1738 return -EINVAL;
1739 }
1740
1741 id = be32_to_cpup(_id);
1742 if (id >= MTK_MAC_COUNT) {
1743 dev_err(eth->dev, "%d is not a valid mac id\n", id);
1744 return -EINVAL;
1745 }
1746
1747 if (eth->netdev[id]) {
1748 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
1749 return -EINVAL;
1750 }
1751
1752 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
1753 if (!eth->netdev[id]) {
1754 dev_err(eth->dev, "alloc_etherdev failed\n");
1755 return -ENOMEM;
1756 }
1757 mac = netdev_priv(eth->netdev[id]);
1758 eth->mac[id] = mac;
1759 mac->id = id;
1760 mac->hw = eth;
1761 mac->of_node = np;
656e7052
JC		 1762
1763 mac->hw_stats = devm_kzalloc(eth->dev,
1764 sizeof(*mac->hw_stats),
1765 GFP_KERNEL);
1766 if (!mac->hw_stats) {
1767 dev_err(eth->dev, "failed to allocate counter memory\n");
1768 err = -ENOMEM;
1769 goto free_netdev;
1770 }
1771 spin_lock_init(&mac->hw_stats->stats_lock);
d7005652 1772 u64_stats_init(&mac->hw_stats->syncp);
656e7052
JC		 1773 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
1774
1775 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
eaadf9fd 1776 eth->netdev[id]->watchdog_timeo = 5 * HZ;
656e7052
JC		 1777 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
1778 eth->netdev[id]->base_addr = (unsigned long)eth->base;
1779 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
1780 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1781 eth->netdev[id]->features |= MTK_HW_FEATURES;
1782 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
1783
1784 err = register_netdev(eth->netdev[id]);
1785 if (err) {
1786 dev_err(eth->dev, "error bringing up device\n");
1787 goto free_netdev;
1788 }
80673029 1789 eth->netdev[id]->irq = eth->irq[0];
656e7052
JC		 1790 netif_info(eth, probe, eth->netdev[id],
1791 "mediatek frame engine at 0x%08lx, irq %d\n",
80673029 1792 eth->netdev[id]->base_addr, eth->irq[0]);
656e7052
JC		 1793
1794 return 0;
1795
1796free_netdev:
1797 free_netdev(eth->netdev[id]);
1798 return err;
1799}
1800
1801static int mtk_probe(struct platform_device *pdev)
1802{
1803 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1804 struct device_node *mac_np;
1805 const struct of_device_id *match;
1806 struct mtk_soc_data *soc;
1807 struct mtk_eth *eth;
1808 int err;
80673029 1809 int i;
656e7052 1810
656e7052
JC		 1811 match = of_match_device(of_mtk_match, &pdev->dev);
1812 soc = (struct mtk_soc_data *)match->data;
1813
1814 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
1815 if (!eth)
1816 return -ENOMEM;
1817
549e5495 1818 eth->dev = &pdev->dev;
656e7052 1819 eth->base = devm_ioremap_resource(&pdev->dev, res);
621e49f6
VZ		 1820 if (IS_ERR(eth->base))
1821 return PTR_ERR(eth->base);
656e7052
JC		 1822
1823 spin_lock_init(&eth->page_lock);
7bc9ccec 1824 spin_lock_init(&eth->irq_lock);
656e7052
JC		 1825
1826 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1827 "mediatek,ethsys");
1828 if (IS_ERR(eth->ethsys)) {
1829 dev_err(&pdev->dev, "no ethsys regmap found\n");
1830 return PTR_ERR(eth->ethsys);
1831 }
1832
1833 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1834 "mediatek,pctl");
1835 if (IS_ERR(eth->pctl)) {
1836 dev_err(&pdev->dev, "no pctl regmap found\n");
1837 return PTR_ERR(eth->pctl);
1838 }
1839
1840 eth->rstc = devm_reset_control_get(&pdev->dev, "eth");
1841 if (IS_ERR(eth->rstc)) {
1842 dev_err(&pdev->dev, "no eth reset found\n");
1843 return PTR_ERR(eth->rstc);
1844 }
1845
80673029
JC		 1846 for (i = 0; i < 3; i++) {
1847 eth->irq[i] = platform_get_irq(pdev, i);
1848 if (eth->irq[i] < 0) {
1849 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
1850 return -ENXIO;
1851 }
656e7052 1852 }
549e5495
SW		 1853 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
1854 eth->clks[i] = devm_clk_get(eth->dev,
1855 mtk_clks_source_name[i]);
1856 if (IS_ERR(eth->clks[i])) {
1857 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
1858 return -EPROBE_DEFER;
1859 return -ENODEV;
1860 }
1861 }
656e7052 1862
549e5495
SW		 1863 clk_prepare_enable(eth->clks[MTK_CLK_ETHIF]);
1864 clk_prepare_enable(eth->clks[MTK_CLK_ESW]);
1865 clk_prepare_enable(eth->clks[MTK_CLK_GP1]);
1866 clk_prepare_enable(eth->clks[MTK_CLK_GP2]);
656e7052 1867
656e7052 1868 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
7c78b4ad 1869 INIT_WORK(&eth->pending_work, mtk_pending_work);
656e7052
JC		 1870
1871 err = mtk_hw_init(eth);
1872 if (err)
1873 return err;
1874
1875 for_each_child_of_node(pdev->dev.of_node, mac_np) {
1876 if (!of_device_is_compatible(mac_np,
1877 "mediatek,eth-mac"))
1878 continue;
1879
1880 if (!of_device_is_available(mac_np))
1881 continue;
1882
1883 err = mtk_add_mac(eth, mac_np);
1884 if (err)
1885 goto err_free_dev;
1886 }
1887
1888 /* we run 2 devices on the same DMA ring so we need a dummy device
1889 * for NAPI to work
1890 */
1891 init_dummy_netdev(&eth->dummy_dev);
80673029
JC		 1892 netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,
1893 MTK_NAPI_WEIGHT);
1894 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,
656e7052
JC		 1895 MTK_NAPI_WEIGHT);
1896
1897 platform_set_drvdata(pdev, eth);
1898
1899 return 0;
1900
1901err_free_dev:
1902 mtk_cleanup(eth);
1903 return err;
1904}
1905
1906static int mtk_remove(struct platform_device *pdev)
1907{
1908 struct mtk_eth *eth = platform_get_drvdata(pdev);
1909
549e5495
SW		 1910 clk_disable_unprepare(eth->clks[MTK_CLK_ETHIF]);
1911 clk_disable_unprepare(eth->clks[MTK_CLK_ESW]);
1912 clk_disable_unprepare(eth->clks[MTK_CLK_GP1]);
1913 clk_disable_unprepare(eth->clks[MTK_CLK_GP2]);
656e7052 1914
80673029 1915 netif_napi_del(&eth->tx_napi);
656e7052
JC		 1916 netif_napi_del(&eth->rx_napi);
1917 mtk_cleanup(eth);
7c6b0d76 1918 mtk_mdio_cleanup(eth);
656e7052
JC		 1919 platform_set_drvdata(pdev, NULL);
1920
1921 return 0;
1922}
1923
1924const struct of_device_id of_mtk_match[] = {
1925 { .compatible = "mediatek,mt7623-eth" },
1926 {},
1927};
1928
1929static struct platform_driver mtk_driver = {
1930 .probe = mtk_probe,
1931 .remove = mtk_remove,
1932 .driver = {
1933 .name = "mtk_soc_eth",
656e7052
JC		 1934 .of_match_table = of_mtk_match,
1935 },
1936};
1937
1938module_platform_driver(mtk_driver);
1939
1940MODULE_LICENSE("GPL");
1941MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1942MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
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