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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/tcp.h> | |
36 | #include <linux/if_vlan.h> | |
37 | #include <linux/delay.h> | |
5a0e3ad6 | 38 | #include <linux/slab.h> |
1eb8c695 AV |
39 | #include <linux/hash.h> |
40 | #include <net/ip.h> | |
076bb0c8 | 41 | #include <net/busy_poll.h> |
1b136de1 | 42 | #include <net/vxlan.h> |
09d4d087 | 43 | #include <net/devlink.h> |
c27a02cd YP |
44 | |
45 | #include <linux/mlx4/driver.h> | |
46 | #include <linux/mlx4/device.h> | |
47 | #include <linux/mlx4/cmd.h> | |
48 | #include <linux/mlx4/cq.h> | |
49 | ||
50 | #include "mlx4_en.h" | |
51 | #include "en_port.h" | |
52 | ||
d317966b | 53 | int mlx4_en_setup_tc(struct net_device *dev, u8 up) |
897d7846 | 54 | { |
bc6a4744 AV |
55 | struct mlx4_en_priv *priv = netdev_priv(dev); |
56 | int i; | |
d317966b | 57 | unsigned int offset = 0; |
bc6a4744 AV |
58 | |
59 | if (up && up != MLX4_EN_NUM_UP) | |
897d7846 AV |
60 | return -EINVAL; |
61 | ||
bc6a4744 AV |
62 | netdev_set_num_tc(dev, up); |
63 | ||
64 | /* Partition Tx queues evenly amongst UP's */ | |
bc6a4744 | 65 | for (i = 0; i < up; i++) { |
d317966b AV |
66 | netdev_set_tc_queue(dev, i, priv->num_tx_rings_p_up, offset); |
67 | offset += priv->num_tx_rings_p_up; | |
bc6a4744 AV |
68 | } |
69 | ||
897d7846 AV |
70 | return 0; |
71 | } | |
72 | ||
16e5cc64 JF |
73 | static int __mlx4_en_setup_tc(struct net_device *dev, u32 handle, __be16 proto, |
74 | struct tc_to_netdev *tc) | |
e4c6734e | 75 | { |
5eb4dce3 | 76 | if (tc->type != TC_SETUP_MQPRIO) |
e4c6734e JF |
77 | return -EINVAL; |
78 | ||
16e5cc64 | 79 | return mlx4_en_setup_tc(dev, tc->tc); |
e4c6734e JF |
80 | } |
81 | ||
1eb8c695 AV |
82 | #ifdef CONFIG_RFS_ACCEL |
83 | ||
84 | struct mlx4_en_filter { | |
85 | struct list_head next; | |
86 | struct work_struct work; | |
87 | ||
75a353d4 | 88 | u8 ip_proto; |
1eb8c695 AV |
89 | __be32 src_ip; |
90 | __be32 dst_ip; | |
91 | __be16 src_port; | |
92 | __be16 dst_port; | |
93 | ||
94 | int rxq_index; | |
95 | struct mlx4_en_priv *priv; | |
96 | u32 flow_id; /* RFS infrastructure id */ | |
97 | int id; /* mlx4_en driver id */ | |
98 | u64 reg_id; /* Flow steering API id */ | |
99 | u8 activated; /* Used to prevent expiry before filter | |
100 | * is attached | |
101 | */ | |
102 | struct hlist_node filter_chain; | |
103 | }; | |
104 | ||
105 | static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv); | |
106 | ||
75a353d4 EP |
107 | static enum mlx4_net_trans_rule_id mlx4_ip_proto_to_trans_rule_id(u8 ip_proto) |
108 | { | |
109 | switch (ip_proto) { | |
110 | case IPPROTO_UDP: | |
111 | return MLX4_NET_TRANS_RULE_ID_UDP; | |
112 | case IPPROTO_TCP: | |
113 | return MLX4_NET_TRANS_RULE_ID_TCP; | |
114 | default: | |
c3ca5205 | 115 | return MLX4_NET_TRANS_RULE_NUM; |
75a353d4 EP |
116 | } |
117 | }; | |
118 | ||
1eb8c695 AV |
119 | static void mlx4_en_filter_work(struct work_struct *work) |
120 | { | |
121 | struct mlx4_en_filter *filter = container_of(work, | |
122 | struct mlx4_en_filter, | |
123 | work); | |
124 | struct mlx4_en_priv *priv = filter->priv; | |
75a353d4 EP |
125 | struct mlx4_spec_list spec_tcp_udp = { |
126 | .id = mlx4_ip_proto_to_trans_rule_id(filter->ip_proto), | |
1eb8c695 AV |
127 | { |
128 | .tcp_udp = { | |
129 | .dst_port = filter->dst_port, | |
130 | .dst_port_msk = (__force __be16)-1, | |
131 | .src_port = filter->src_port, | |
132 | .src_port_msk = (__force __be16)-1, | |
133 | }, | |
134 | }, | |
135 | }; | |
136 | struct mlx4_spec_list spec_ip = { | |
137 | .id = MLX4_NET_TRANS_RULE_ID_IPV4, | |
138 | { | |
139 | .ipv4 = { | |
140 | .dst_ip = filter->dst_ip, | |
141 | .dst_ip_msk = (__force __be32)-1, | |
142 | .src_ip = filter->src_ip, | |
143 | .src_ip_msk = (__force __be32)-1, | |
144 | }, | |
145 | }, | |
146 | }; | |
147 | struct mlx4_spec_list spec_eth = { | |
148 | .id = MLX4_NET_TRANS_RULE_ID_ETH, | |
149 | }; | |
150 | struct mlx4_net_trans_rule rule = { | |
151 | .list = LIST_HEAD_INIT(rule.list), | |
152 | .queue_mode = MLX4_NET_TRANS_Q_LIFO, | |
153 | .exclusive = 1, | |
154 | .allow_loopback = 1, | |
f9162539 | 155 | .promisc_mode = MLX4_FS_REGULAR, |
1eb8c695 AV |
156 | .port = priv->port, |
157 | .priority = MLX4_DOMAIN_RFS, | |
158 | }; | |
159 | int rc; | |
1eb8c695 AV |
160 | __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16); |
161 | ||
c3ca5205 | 162 | if (spec_tcp_udp.id >= MLX4_NET_TRANS_RULE_NUM) { |
75a353d4 EP |
163 | en_warn(priv, "RFS: ignoring unsupported ip protocol (%d)\n", |
164 | filter->ip_proto); | |
165 | goto ignore; | |
166 | } | |
1eb8c695 AV |
167 | list_add_tail(&spec_eth.list, &rule.list); |
168 | list_add_tail(&spec_ip.list, &rule.list); | |
75a353d4 | 169 | list_add_tail(&spec_tcp_udp.list, &rule.list); |
1eb8c695 | 170 | |
1eb8c695 | 171 | rule.qpn = priv->rss_map.qps[filter->rxq_index].qpn; |
6bbb6d99 | 172 | memcpy(spec_eth.eth.dst_mac, priv->dev->dev_addr, ETH_ALEN); |
1eb8c695 AV |
173 | memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN); |
174 | ||
175 | filter->activated = 0; | |
176 | ||
177 | if (filter->reg_id) { | |
178 | rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id); | |
179 | if (rc && rc != -ENOENT) | |
180 | en_err(priv, "Error detaching flow. rc = %d\n", rc); | |
181 | } | |
182 | ||
183 | rc = mlx4_flow_attach(priv->mdev->dev, &rule, &filter->reg_id); | |
184 | if (rc) | |
185 | en_err(priv, "Error attaching flow. err = %d\n", rc); | |
186 | ||
75a353d4 | 187 | ignore: |
1eb8c695 AV |
188 | mlx4_en_filter_rfs_expire(priv); |
189 | ||
190 | filter->activated = 1; | |
191 | } | |
192 | ||
193 | static inline struct hlist_head * | |
194 | filter_hash_bucket(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip, | |
195 | __be16 src_port, __be16 dst_port) | |
196 | { | |
197 | unsigned long l; | |
198 | int bucket_idx; | |
199 | ||
200 | l = (__force unsigned long)src_port | | |
201 | ((__force unsigned long)dst_port << 2); | |
202 | l ^= (__force unsigned long)(src_ip ^ dst_ip); | |
203 | ||
204 | bucket_idx = hash_long(l, MLX4_EN_FILTER_HASH_SHIFT); | |
205 | ||
206 | return &priv->filter_hash[bucket_idx]; | |
207 | } | |
208 | ||
209 | static struct mlx4_en_filter * | |
210 | mlx4_en_filter_alloc(struct mlx4_en_priv *priv, int rxq_index, __be32 src_ip, | |
75a353d4 EP |
211 | __be32 dst_ip, u8 ip_proto, __be16 src_port, |
212 | __be16 dst_port, u32 flow_id) | |
1eb8c695 AV |
213 | { |
214 | struct mlx4_en_filter *filter = NULL; | |
215 | ||
216 | filter = kzalloc(sizeof(struct mlx4_en_filter), GFP_ATOMIC); | |
217 | if (!filter) | |
218 | return NULL; | |
219 | ||
220 | filter->priv = priv; | |
221 | filter->rxq_index = rxq_index; | |
222 | INIT_WORK(&filter->work, mlx4_en_filter_work); | |
223 | ||
224 | filter->src_ip = src_ip; | |
225 | filter->dst_ip = dst_ip; | |
75a353d4 | 226 | filter->ip_proto = ip_proto; |
1eb8c695 AV |
227 | filter->src_port = src_port; |
228 | filter->dst_port = dst_port; | |
229 | ||
230 | filter->flow_id = flow_id; | |
231 | ||
ee64c0ee | 232 | filter->id = priv->last_filter_id++ % RPS_NO_FILTER; |
1eb8c695 AV |
233 | |
234 | list_add_tail(&filter->next, &priv->filters); | |
235 | hlist_add_head(&filter->filter_chain, | |
236 | filter_hash_bucket(priv, src_ip, dst_ip, src_port, | |
237 | dst_port)); | |
238 | ||
239 | return filter; | |
240 | } | |
241 | ||
242 | static void mlx4_en_filter_free(struct mlx4_en_filter *filter) | |
243 | { | |
244 | struct mlx4_en_priv *priv = filter->priv; | |
245 | int rc; | |
246 | ||
247 | list_del(&filter->next); | |
248 | ||
249 | rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id); | |
250 | if (rc && rc != -ENOENT) | |
251 | en_err(priv, "Error detaching flow. rc = %d\n", rc); | |
252 | ||
253 | kfree(filter); | |
254 | } | |
255 | ||
256 | static inline struct mlx4_en_filter * | |
257 | mlx4_en_filter_find(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip, | |
75a353d4 | 258 | u8 ip_proto, __be16 src_port, __be16 dst_port) |
1eb8c695 | 259 | { |
1eb8c695 AV |
260 | struct mlx4_en_filter *filter; |
261 | struct mlx4_en_filter *ret = NULL; | |
262 | ||
b67bfe0d | 263 | hlist_for_each_entry(filter, |
1eb8c695 AV |
264 | filter_hash_bucket(priv, src_ip, dst_ip, |
265 | src_port, dst_port), | |
266 | filter_chain) { | |
267 | if (filter->src_ip == src_ip && | |
268 | filter->dst_ip == dst_ip && | |
75a353d4 | 269 | filter->ip_proto == ip_proto && |
1eb8c695 AV |
270 | filter->src_port == src_port && |
271 | filter->dst_port == dst_port) { | |
272 | ret = filter; | |
273 | break; | |
274 | } | |
275 | } | |
276 | ||
277 | return ret; | |
278 | } | |
279 | ||
280 | static int | |
281 | mlx4_en_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb, | |
282 | u16 rxq_index, u32 flow_id) | |
283 | { | |
284 | struct mlx4_en_priv *priv = netdev_priv(net_dev); | |
285 | struct mlx4_en_filter *filter; | |
286 | const struct iphdr *ip; | |
287 | const __be16 *ports; | |
75a353d4 | 288 | u8 ip_proto; |
1eb8c695 AV |
289 | __be32 src_ip; |
290 | __be32 dst_ip; | |
291 | __be16 src_port; | |
292 | __be16 dst_port; | |
293 | int nhoff = skb_network_offset(skb); | |
294 | int ret = 0; | |
295 | ||
296 | if (skb->protocol != htons(ETH_P_IP)) | |
297 | return -EPROTONOSUPPORT; | |
298 | ||
299 | ip = (const struct iphdr *)(skb->data + nhoff); | |
300 | if (ip_is_fragment(ip)) | |
301 | return -EPROTONOSUPPORT; | |
302 | ||
75a353d4 EP |
303 | if ((ip->protocol != IPPROTO_TCP) && (ip->protocol != IPPROTO_UDP)) |
304 | return -EPROTONOSUPPORT; | |
1eb8c695 AV |
305 | ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl); |
306 | ||
75a353d4 | 307 | ip_proto = ip->protocol; |
1eb8c695 AV |
308 | src_ip = ip->saddr; |
309 | dst_ip = ip->daddr; | |
310 | src_port = ports[0]; | |
311 | dst_port = ports[1]; | |
312 | ||
1eb8c695 | 313 | spin_lock_bh(&priv->filters_lock); |
75a353d4 EP |
314 | filter = mlx4_en_filter_find(priv, src_ip, dst_ip, ip_proto, |
315 | src_port, dst_port); | |
1eb8c695 AV |
316 | if (filter) { |
317 | if (filter->rxq_index == rxq_index) | |
318 | goto out; | |
319 | ||
320 | filter->rxq_index = rxq_index; | |
321 | } else { | |
322 | filter = mlx4_en_filter_alloc(priv, rxq_index, | |
75a353d4 | 323 | src_ip, dst_ip, ip_proto, |
1eb8c695 AV |
324 | src_port, dst_port, flow_id); |
325 | if (!filter) { | |
326 | ret = -ENOMEM; | |
327 | goto err; | |
328 | } | |
329 | } | |
330 | ||
331 | queue_work(priv->mdev->workqueue, &filter->work); | |
332 | ||
333 | out: | |
334 | ret = filter->id; | |
335 | err: | |
336 | spin_unlock_bh(&priv->filters_lock); | |
337 | ||
338 | return ret; | |
339 | } | |
340 | ||
41d942d5 | 341 | void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv) |
1eb8c695 AV |
342 | { |
343 | struct mlx4_en_filter *filter, *tmp; | |
344 | LIST_HEAD(del_list); | |
345 | ||
346 | spin_lock_bh(&priv->filters_lock); | |
347 | list_for_each_entry_safe(filter, tmp, &priv->filters, next) { | |
348 | list_move(&filter->next, &del_list); | |
349 | hlist_del(&filter->filter_chain); | |
350 | } | |
351 | spin_unlock_bh(&priv->filters_lock); | |
352 | ||
353 | list_for_each_entry_safe(filter, tmp, &del_list, next) { | |
354 | cancel_work_sync(&filter->work); | |
355 | mlx4_en_filter_free(filter); | |
356 | } | |
357 | } | |
358 | ||
359 | static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv) | |
360 | { | |
361 | struct mlx4_en_filter *filter = NULL, *tmp, *last_filter = NULL; | |
362 | LIST_HEAD(del_list); | |
363 | int i = 0; | |
364 | ||
365 | spin_lock_bh(&priv->filters_lock); | |
366 | list_for_each_entry_safe(filter, tmp, &priv->filters, next) { | |
367 | if (i > MLX4_EN_FILTER_EXPIRY_QUOTA) | |
368 | break; | |
369 | ||
370 | if (filter->activated && | |
371 | !work_pending(&filter->work) && | |
372 | rps_may_expire_flow(priv->dev, | |
373 | filter->rxq_index, filter->flow_id, | |
374 | filter->id)) { | |
375 | list_move(&filter->next, &del_list); | |
376 | hlist_del(&filter->filter_chain); | |
377 | } else | |
378 | last_filter = filter; | |
379 | ||
380 | i++; | |
381 | } | |
382 | ||
383 | if (last_filter && (&last_filter->next != priv->filters.next)) | |
384 | list_move(&priv->filters, &last_filter->next); | |
385 | ||
386 | spin_unlock_bh(&priv->filters_lock); | |
387 | ||
388 | list_for_each_entry_safe(filter, tmp, &del_list, next) | |
389 | mlx4_en_filter_free(filter); | |
390 | } | |
391 | #endif | |
392 | ||
80d5c368 PM |
393 | static int mlx4_en_vlan_rx_add_vid(struct net_device *dev, |
394 | __be16 proto, u16 vid) | |
c27a02cd YP |
395 | { |
396 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
397 | struct mlx4_en_dev *mdev = priv->mdev; | |
398 | int err; | |
4c3eb3ca | 399 | int idx; |
c27a02cd | 400 | |
f1b553fb | 401 | en_dbg(HW, priv, "adding VLAN:%d\n", vid); |
c27a02cd | 402 | |
f1b553fb | 403 | set_bit(vid, priv->active_vlans); |
c27a02cd YP |
404 | |
405 | /* Add VID to port VLAN filter */ | |
406 | mutex_lock(&mdev->state_lock); | |
407 | if (mdev->device_up && priv->port_up) { | |
f1b553fb | 408 | err = mlx4_SET_VLAN_FLTR(mdev->dev, priv); |
c27a02cd | 409 | if (err) |
453a6082 | 410 | en_err(priv, "Failed configuring VLAN filter\n"); |
c27a02cd | 411 | } |
4c3eb3ca | 412 | if (mlx4_register_vlan(mdev->dev, priv->port, vid, &idx)) |
9e19b545 | 413 | en_dbg(HW, priv, "failed adding vlan %d\n", vid); |
c27a02cd | 414 | mutex_unlock(&mdev->state_lock); |
4c3eb3ca | 415 | |
8e586137 | 416 | return 0; |
c27a02cd YP |
417 | } |
418 | ||
80d5c368 PM |
419 | static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev, |
420 | __be16 proto, u16 vid) | |
c27a02cd YP |
421 | { |
422 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
423 | struct mlx4_en_dev *mdev = priv->mdev; | |
424 | int err; | |
425 | ||
f1b553fb | 426 | en_dbg(HW, priv, "Killing VID:%d\n", vid); |
c27a02cd | 427 | |
f1b553fb | 428 | clear_bit(vid, priv->active_vlans); |
c27a02cd YP |
429 | |
430 | /* Remove VID from port VLAN filter */ | |
431 | mutex_lock(&mdev->state_lock); | |
2009d005 | 432 | mlx4_unregister_vlan(mdev->dev, priv->port, vid); |
4c3eb3ca | 433 | |
c27a02cd | 434 | if (mdev->device_up && priv->port_up) { |
f1b553fb | 435 | err = mlx4_SET_VLAN_FLTR(mdev->dev, priv); |
c27a02cd | 436 | if (err) |
453a6082 | 437 | en_err(priv, "Failed configuring VLAN filter\n"); |
c27a02cd YP |
438 | } |
439 | mutex_unlock(&mdev->state_lock); | |
8e586137 JP |
440 | |
441 | return 0; | |
c27a02cd YP |
442 | } |
443 | ||
6bbb6d99 YB |
444 | static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac) |
445 | { | |
bab6a9ea YB |
446 | int i; |
447 | for (i = ETH_ALEN - 1; i >= 0; --i) { | |
6bbb6d99 YB |
448 | dst_mac[i] = src_mac & 0xff; |
449 | src_mac >>= 8; | |
450 | } | |
451 | memset(&dst_mac[ETH_ALEN], 0, 2); | |
452 | } | |
453 | ||
837052d0 OG |
454 | |
455 | static int mlx4_en_tunnel_steer_add(struct mlx4_en_priv *priv, unsigned char *addr, | |
456 | int qpn, u64 *reg_id) | |
457 | { | |
458 | int err; | |
837052d0 | 459 | |
5eff6dad OG |
460 | if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN || |
461 | priv->mdev->dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) | |
837052d0 OG |
462 | return 0; /* do nothing */ |
463 | ||
b95089d0 OG |
464 | err = mlx4_tunnel_steer_add(priv->mdev->dev, addr, priv->port, qpn, |
465 | MLX4_DOMAIN_NIC, reg_id); | |
837052d0 OG |
466 | if (err) { |
467 | en_err(priv, "failed to add vxlan steering rule, err %d\n", err); | |
468 | return err; | |
469 | } | |
470 | en_dbg(DRV, priv, "added vxlan steering rule, mac %pM reg_id %llx\n", addr, *reg_id); | |
471 | return 0; | |
472 | } | |
473 | ||
474 | ||
16a10ffd YB |
475 | static int mlx4_en_uc_steer_add(struct mlx4_en_priv *priv, |
476 | unsigned char *mac, int *qpn, u64 *reg_id) | |
477 | { | |
478 | struct mlx4_en_dev *mdev = priv->mdev; | |
479 | struct mlx4_dev *dev = mdev->dev; | |
480 | int err; | |
481 | ||
482 | switch (dev->caps.steering_mode) { | |
483 | case MLX4_STEERING_MODE_B0: { | |
484 | struct mlx4_qp qp; | |
485 | u8 gid[16] = {0}; | |
486 | ||
487 | qp.qpn = *qpn; | |
488 | memcpy(&gid[10], mac, ETH_ALEN); | |
489 | gid[5] = priv->port; | |
490 | ||
491 | err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH); | |
492 | break; | |
493 | } | |
494 | case MLX4_STEERING_MODE_DEVICE_MANAGED: { | |
495 | struct mlx4_spec_list spec_eth = { {NULL} }; | |
496 | __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16); | |
497 | ||
498 | struct mlx4_net_trans_rule rule = { | |
499 | .queue_mode = MLX4_NET_TRANS_Q_FIFO, | |
500 | .exclusive = 0, | |
501 | .allow_loopback = 1, | |
f9162539 | 502 | .promisc_mode = MLX4_FS_REGULAR, |
16a10ffd YB |
503 | .priority = MLX4_DOMAIN_NIC, |
504 | }; | |
505 | ||
506 | rule.port = priv->port; | |
507 | rule.qpn = *qpn; | |
508 | INIT_LIST_HEAD(&rule.list); | |
509 | ||
510 | spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH; | |
511 | memcpy(spec_eth.eth.dst_mac, mac, ETH_ALEN); | |
512 | memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN); | |
513 | list_add_tail(&spec_eth.list, &rule.list); | |
514 | ||
515 | err = mlx4_flow_attach(dev, &rule, reg_id); | |
516 | break; | |
517 | } | |
518 | default: | |
519 | return -EINVAL; | |
520 | } | |
521 | if (err) | |
522 | en_warn(priv, "Failed Attaching Unicast\n"); | |
523 | ||
524 | return err; | |
525 | } | |
526 | ||
527 | static void mlx4_en_uc_steer_release(struct mlx4_en_priv *priv, | |
528 | unsigned char *mac, int qpn, u64 reg_id) | |
529 | { | |
530 | struct mlx4_en_dev *mdev = priv->mdev; | |
531 | struct mlx4_dev *dev = mdev->dev; | |
532 | ||
533 | switch (dev->caps.steering_mode) { | |
534 | case MLX4_STEERING_MODE_B0: { | |
535 | struct mlx4_qp qp; | |
536 | u8 gid[16] = {0}; | |
537 | ||
538 | qp.qpn = qpn; | |
539 | memcpy(&gid[10], mac, ETH_ALEN); | |
540 | gid[5] = priv->port; | |
541 | ||
542 | mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH); | |
543 | break; | |
544 | } | |
545 | case MLX4_STEERING_MODE_DEVICE_MANAGED: { | |
546 | mlx4_flow_detach(dev, reg_id); | |
547 | break; | |
548 | } | |
549 | default: | |
550 | en_err(priv, "Invalid steering mode.\n"); | |
551 | } | |
552 | } | |
553 | ||
554 | static int mlx4_en_get_qp(struct mlx4_en_priv *priv) | |
555 | { | |
556 | struct mlx4_en_dev *mdev = priv->mdev; | |
557 | struct mlx4_dev *dev = mdev->dev; | |
16a10ffd YB |
558 | int index = 0; |
559 | int err = 0; | |
16a10ffd | 560 | int *qpn = &priv->base_qpn; |
9813337a | 561 | u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr); |
16a10ffd YB |
562 | |
563 | en_dbg(DRV, priv, "Registering MAC: %pM for adding\n", | |
564 | priv->dev->dev_addr); | |
565 | index = mlx4_register_mac(dev, priv->port, mac); | |
566 | if (index < 0) { | |
567 | err = index; | |
568 | en_err(priv, "Failed adding MAC: %pM\n", | |
569 | priv->dev->dev_addr); | |
570 | return err; | |
571 | } | |
572 | ||
573 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) { | |
574 | int base_qpn = mlx4_get_base_qpn(dev, priv->port); | |
575 | *qpn = base_qpn + index; | |
576 | return 0; | |
577 | } | |
578 | ||
d57febe1 | 579 | err = mlx4_qp_reserve_range(dev, 1, 1, qpn, MLX4_RESERVE_A0_QP); |
16a10ffd YB |
580 | en_dbg(DRV, priv, "Reserved qp %d\n", *qpn); |
581 | if (err) { | |
582 | en_err(priv, "Failed to reserve qp for mac registration\n"); | |
ba4b87ae IS |
583 | mlx4_unregister_mac(dev, priv->port, mac); |
584 | return err; | |
16a10ffd | 585 | } |
16a10ffd | 586 | |
c07cb4b0 | 587 | return 0; |
16a10ffd YB |
588 | } |
589 | ||
590 | static void mlx4_en_put_qp(struct mlx4_en_priv *priv) | |
591 | { | |
592 | struct mlx4_en_dev *mdev = priv->mdev; | |
593 | struct mlx4_dev *dev = mdev->dev; | |
16a10ffd | 594 | int qpn = priv->base_qpn; |
16a10ffd | 595 | |
83a5a6ce | 596 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) { |
ba4b87ae | 597 | u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr); |
83a5a6ce YB |
598 | en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n", |
599 | priv->dev->dev_addr); | |
600 | mlx4_unregister_mac(dev, priv->port, mac); | |
601 | } else { | |
83a5a6ce YB |
602 | en_dbg(DRV, priv, "Releasing qp: port %d, qpn %d\n", |
603 | priv->port, qpn); | |
604 | mlx4_qp_release_range(dev, qpn, 1); | |
605 | priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC; | |
16a10ffd YB |
606 | } |
607 | } | |
608 | ||
609 | static int mlx4_en_replace_mac(struct mlx4_en_priv *priv, int qpn, | |
90bbb74a | 610 | unsigned char *new_mac, unsigned char *prev_mac) |
16a10ffd YB |
611 | { |
612 | struct mlx4_en_dev *mdev = priv->mdev; | |
613 | struct mlx4_dev *dev = mdev->dev; | |
16a10ffd | 614 | int err = 0; |
9813337a | 615 | u64 new_mac_u64 = mlx4_mac_to_u64(new_mac); |
16a10ffd YB |
616 | |
617 | if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) { | |
c07cb4b0 YB |
618 | struct hlist_head *bucket; |
619 | unsigned int mac_hash; | |
620 | struct mlx4_mac_entry *entry; | |
b67bfe0d | 621 | struct hlist_node *tmp; |
9813337a | 622 | u64 prev_mac_u64 = mlx4_mac_to_u64(prev_mac); |
c07cb4b0 YB |
623 | |
624 | bucket = &priv->mac_hash[prev_mac[MLX4_EN_MAC_HASH_IDX]]; | |
b67bfe0d | 625 | hlist_for_each_entry_safe(entry, tmp, bucket, hlist) { |
c07cb4b0 YB |
626 | if (ether_addr_equal_64bits(entry->mac, prev_mac)) { |
627 | mlx4_en_uc_steer_release(priv, entry->mac, | |
628 | qpn, entry->reg_id); | |
629 | mlx4_unregister_mac(dev, priv->port, | |
630 | prev_mac_u64); | |
631 | hlist_del_rcu(&entry->hlist); | |
632 | synchronize_rcu(); | |
633 | memcpy(entry->mac, new_mac, ETH_ALEN); | |
634 | entry->reg_id = 0; | |
635 | mac_hash = new_mac[MLX4_EN_MAC_HASH_IDX]; | |
636 | hlist_add_head_rcu(&entry->hlist, | |
637 | &priv->mac_hash[mac_hash]); | |
638 | mlx4_register_mac(dev, priv->port, new_mac_u64); | |
639 | err = mlx4_en_uc_steer_add(priv, new_mac, | |
640 | &qpn, | |
641 | &entry->reg_id); | |
2a2083f7 OG |
642 | if (err) |
643 | return err; | |
644 | if (priv->tunnel_reg_id) { | |
645 | mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id); | |
646 | priv->tunnel_reg_id = 0; | |
647 | } | |
648 | err = mlx4_en_tunnel_steer_add(priv, new_mac, qpn, | |
649 | &priv->tunnel_reg_id); | |
c07cb4b0 YB |
650 | return err; |
651 | } | |
652 | } | |
653 | return -EINVAL; | |
16a10ffd YB |
654 | } |
655 | ||
656 | return __mlx4_replace_mac(dev, priv->port, qpn, new_mac_u64); | |
657 | } | |
658 | ||
2695bab2 NO |
659 | static int mlx4_en_do_set_mac(struct mlx4_en_priv *priv, |
660 | unsigned char new_mac[ETH_ALEN + 2]) | |
c27a02cd | 661 | { |
c27a02cd YP |
662 | int err = 0; |
663 | ||
c27a02cd YP |
664 | if (priv->port_up) { |
665 | /* Remove old MAC and insert the new one */ | |
16a10ffd | 666 | err = mlx4_en_replace_mac(priv, priv->base_qpn, |
2695bab2 | 667 | new_mac, priv->current_mac); |
c27a02cd | 668 | if (err) |
453a6082 | 669 | en_err(priv, "Failed changing HW MAC address\n"); |
c27a02cd | 670 | } else |
48e551ff | 671 | en_dbg(HW, priv, "Port is down while registering mac, exiting...\n"); |
c27a02cd | 672 | |
2695bab2 NO |
673 | if (!err) |
674 | memcpy(priv->current_mac, new_mac, sizeof(priv->current_mac)); | |
ee755324 | 675 | |
bfa8ab47 YB |
676 | return err; |
677 | } | |
678 | ||
679 | static int mlx4_en_set_mac(struct net_device *dev, void *addr) | |
680 | { | |
681 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
682 | struct mlx4_en_dev *mdev = priv->mdev; | |
683 | struct sockaddr *saddr = addr; | |
2695bab2 | 684 | unsigned char new_mac[ETH_ALEN + 2]; |
bfa8ab47 YB |
685 | int err; |
686 | ||
687 | if (!is_valid_ether_addr(saddr->sa_data)) | |
688 | return -EADDRNOTAVAIL; | |
689 | ||
bfa8ab47 | 690 | mutex_lock(&mdev->state_lock); |
2695bab2 NO |
691 | memcpy(new_mac, saddr->sa_data, ETH_ALEN); |
692 | err = mlx4_en_do_set_mac(priv, new_mac); | |
693 | if (!err) | |
694 | memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN); | |
c27a02cd | 695 | mutex_unlock(&mdev->state_lock); |
bfa8ab47 YB |
696 | |
697 | return err; | |
c27a02cd YP |
698 | } |
699 | ||
700 | static void mlx4_en_clear_list(struct net_device *dev) | |
701 | { | |
702 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
6d199937 | 703 | struct mlx4_en_mc_list *tmp, *mc_to_del; |
c27a02cd | 704 | |
6d199937 YP |
705 | list_for_each_entry_safe(mc_to_del, tmp, &priv->mc_list, list) { |
706 | list_del(&mc_to_del->list); | |
707 | kfree(mc_to_del); | |
708 | } | |
c27a02cd YP |
709 | } |
710 | ||
711 | static void mlx4_en_cache_mclist(struct net_device *dev) | |
712 | { | |
713 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
22bedad3 | 714 | struct netdev_hw_addr *ha; |
6d199937 | 715 | struct mlx4_en_mc_list *tmp; |
ff6e2163 | 716 | |
0e03567a | 717 | mlx4_en_clear_list(dev); |
6d199937 YP |
718 | netdev_for_each_mc_addr(ha, dev) { |
719 | tmp = kzalloc(sizeof(struct mlx4_en_mc_list), GFP_ATOMIC); | |
720 | if (!tmp) { | |
6d199937 YP |
721 | mlx4_en_clear_list(dev); |
722 | return; | |
723 | } | |
724 | memcpy(tmp->addr, ha->addr, ETH_ALEN); | |
725 | list_add_tail(&tmp->list, &priv->mc_list); | |
726 | } | |
c27a02cd YP |
727 | } |
728 | ||
6d199937 YP |
729 | static void update_mclist_flags(struct mlx4_en_priv *priv, |
730 | struct list_head *dst, | |
731 | struct list_head *src) | |
732 | { | |
733 | struct mlx4_en_mc_list *dst_tmp, *src_tmp, *new_mc; | |
734 | bool found; | |
735 | ||
736 | /* Find all the entries that should be removed from dst, | |
737 | * These are the entries that are not found in src | |
738 | */ | |
739 | list_for_each_entry(dst_tmp, dst, list) { | |
740 | found = false; | |
741 | list_for_each_entry(src_tmp, src, list) { | |
c0623e58 | 742 | if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) { |
6d199937 YP |
743 | found = true; |
744 | break; | |
745 | } | |
746 | } | |
747 | if (!found) | |
748 | dst_tmp->action = MCLIST_REM; | |
749 | } | |
750 | ||
751 | /* Add entries that exist in src but not in dst | |
752 | * mark them as need to add | |
753 | */ | |
754 | list_for_each_entry(src_tmp, src, list) { | |
755 | found = false; | |
756 | list_for_each_entry(dst_tmp, dst, list) { | |
c0623e58 | 757 | if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) { |
6d199937 YP |
758 | dst_tmp->action = MCLIST_NONE; |
759 | found = true; | |
760 | break; | |
761 | } | |
762 | } | |
763 | if (!found) { | |
14f8dc49 JP |
764 | new_mc = kmemdup(src_tmp, |
765 | sizeof(struct mlx4_en_mc_list), | |
6d199937 | 766 | GFP_KERNEL); |
14f8dc49 | 767 | if (!new_mc) |
6d199937 | 768 | return; |
14f8dc49 | 769 | |
6d199937 YP |
770 | new_mc->action = MCLIST_ADD; |
771 | list_add_tail(&new_mc->list, dst); | |
772 | } | |
773 | } | |
774 | } | |
c27a02cd | 775 | |
0eb74fdd | 776 | static void mlx4_en_set_rx_mode(struct net_device *dev) |
c27a02cd YP |
777 | { |
778 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
779 | ||
780 | if (!priv->port_up) | |
781 | return; | |
782 | ||
0eb74fdd | 783 | queue_work(priv->mdev->workqueue, &priv->rx_mode_task); |
c27a02cd YP |
784 | } |
785 | ||
0eb74fdd YB |
786 | static void mlx4_en_set_promisc_mode(struct mlx4_en_priv *priv, |
787 | struct mlx4_en_dev *mdev) | |
c27a02cd | 788 | { |
c96d97f4 | 789 | int err = 0; |
c27a02cd | 790 | |
0eb74fdd | 791 | if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) { |
c27a02cd | 792 | if (netif_msg_rx_status(priv)) |
0eb74fdd YB |
793 | en_warn(priv, "Entering promiscuous mode\n"); |
794 | priv->flags |= MLX4_EN_FLAG_PROMISC; | |
c27a02cd | 795 | |
0eb74fdd | 796 | /* Enable promiscouos mode */ |
c96d97f4 | 797 | switch (mdev->dev->caps.steering_mode) { |
592e49dd | 798 | case MLX4_STEERING_MODE_DEVICE_MANAGED: |
0eb74fdd YB |
799 | err = mlx4_flow_steer_promisc_add(mdev->dev, |
800 | priv->port, | |
801 | priv->base_qpn, | |
f9162539 | 802 | MLX4_FS_ALL_DEFAULT); |
592e49dd | 803 | if (err) |
0eb74fdd YB |
804 | en_err(priv, "Failed enabling promiscuous mode\n"); |
805 | priv->flags |= MLX4_EN_FLAG_MC_PROMISC; | |
592e49dd HHZ |
806 | break; |
807 | ||
c96d97f4 | 808 | case MLX4_STEERING_MODE_B0: |
0eb74fdd YB |
809 | err = mlx4_unicast_promisc_add(mdev->dev, |
810 | priv->base_qpn, | |
811 | priv->port); | |
c96d97f4 | 812 | if (err) |
0eb74fdd YB |
813 | en_err(priv, "Failed enabling unicast promiscuous mode\n"); |
814 | ||
815 | /* Add the default qp number as multicast | |
816 | * promisc | |
817 | */ | |
818 | if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) { | |
819 | err = mlx4_multicast_promisc_add(mdev->dev, | |
820 | priv->base_qpn, | |
821 | priv->port); | |
c96d97f4 | 822 | if (err) |
0eb74fdd YB |
823 | en_err(priv, "Failed enabling multicast promiscuous mode\n"); |
824 | priv->flags |= MLX4_EN_FLAG_MC_PROMISC; | |
c96d97f4 HHZ |
825 | } |
826 | break; | |
c27a02cd | 827 | |
c96d97f4 HHZ |
828 | case MLX4_STEERING_MODE_A0: |
829 | err = mlx4_SET_PORT_qpn_calc(mdev->dev, | |
830 | priv->port, | |
0eb74fdd YB |
831 | priv->base_qpn, |
832 | 1); | |
1679200f | 833 | if (err) |
0eb74fdd | 834 | en_err(priv, "Failed enabling promiscuous mode\n"); |
c96d97f4 | 835 | break; |
1679200f YP |
836 | } |
837 | ||
0eb74fdd YB |
838 | /* Disable port multicast filter (unconditionally) */ |
839 | err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, | |
840 | 0, MLX4_MCAST_DISABLE); | |
841 | if (err) | |
842 | en_err(priv, "Failed disabling multicast filter\n"); | |
0eb74fdd YB |
843 | } |
844 | } | |
845 | ||
846 | static void mlx4_en_clear_promisc_mode(struct mlx4_en_priv *priv, | |
847 | struct mlx4_en_dev *mdev) | |
848 | { | |
849 | int err = 0; | |
850 | ||
851 | if (netif_msg_rx_status(priv)) | |
852 | en_warn(priv, "Leaving promiscuous mode\n"); | |
853 | priv->flags &= ~MLX4_EN_FLAG_PROMISC; | |
854 | ||
855 | /* Disable promiscouos mode */ | |
856 | switch (mdev->dev->caps.steering_mode) { | |
857 | case MLX4_STEERING_MODE_DEVICE_MANAGED: | |
858 | err = mlx4_flow_steer_promisc_remove(mdev->dev, | |
859 | priv->port, | |
f9162539 | 860 | MLX4_FS_ALL_DEFAULT); |
0eb74fdd YB |
861 | if (err) |
862 | en_err(priv, "Failed disabling promiscuous mode\n"); | |
863 | priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC; | |
864 | break; | |
865 | ||
866 | case MLX4_STEERING_MODE_B0: | |
867 | err = mlx4_unicast_promisc_remove(mdev->dev, | |
868 | priv->base_qpn, | |
869 | priv->port); | |
870 | if (err) | |
871 | en_err(priv, "Failed disabling unicast promiscuous mode\n"); | |
872 | /* Disable Multicast promisc */ | |
873 | if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) { | |
874 | err = mlx4_multicast_promisc_remove(mdev->dev, | |
875 | priv->base_qpn, | |
876 | priv->port); | |
877 | if (err) | |
878 | en_err(priv, "Failed disabling multicast promiscuous mode\n"); | |
879 | priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC; | |
880 | } | |
881 | break; | |
882 | ||
883 | case MLX4_STEERING_MODE_A0: | |
884 | err = mlx4_SET_PORT_qpn_calc(mdev->dev, | |
885 | priv->port, | |
886 | priv->base_qpn, 0); | |
887 | if (err) | |
888 | en_err(priv, "Failed disabling promiscuous mode\n"); | |
889 | break; | |
c27a02cd | 890 | } |
0eb74fdd YB |
891 | } |
892 | ||
893 | static void mlx4_en_do_multicast(struct mlx4_en_priv *priv, | |
894 | struct net_device *dev, | |
895 | struct mlx4_en_dev *mdev) | |
896 | { | |
897 | struct mlx4_en_mc_list *mclist, *tmp; | |
898 | u64 mcast_addr = 0; | |
899 | u8 mc_list[16] = {0}; | |
900 | int err = 0; | |
901 | ||
c27a02cd YP |
902 | /* Enable/disable the multicast filter according to IFF_ALLMULTI */ |
903 | if (dev->flags & IFF_ALLMULTI) { | |
904 | err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, | |
905 | 0, MLX4_MCAST_DISABLE); | |
906 | if (err) | |
453a6082 | 907 | en_err(priv, "Failed disabling multicast filter\n"); |
1679200f YP |
908 | |
909 | /* Add the default qp number as multicast promisc */ | |
910 | if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) { | |
c96d97f4 | 911 | switch (mdev->dev->caps.steering_mode) { |
592e49dd HHZ |
912 | case MLX4_STEERING_MODE_DEVICE_MANAGED: |
913 | err = mlx4_flow_steer_promisc_add(mdev->dev, | |
914 | priv->port, | |
915 | priv->base_qpn, | |
f9162539 | 916 | MLX4_FS_MC_DEFAULT); |
592e49dd HHZ |
917 | break; |
918 | ||
c96d97f4 HHZ |
919 | case MLX4_STEERING_MODE_B0: |
920 | err = mlx4_multicast_promisc_add(mdev->dev, | |
921 | priv->base_qpn, | |
922 | priv->port); | |
923 | break; | |
924 | ||
925 | case MLX4_STEERING_MODE_A0: | |
926 | break; | |
927 | } | |
1679200f YP |
928 | if (err) |
929 | en_err(priv, "Failed entering multicast promisc mode\n"); | |
930 | priv->flags |= MLX4_EN_FLAG_MC_PROMISC; | |
931 | } | |
c27a02cd | 932 | } else { |
1679200f YP |
933 | /* Disable Multicast promisc */ |
934 | if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) { | |
c96d97f4 | 935 | switch (mdev->dev->caps.steering_mode) { |
592e49dd HHZ |
936 | case MLX4_STEERING_MODE_DEVICE_MANAGED: |
937 | err = mlx4_flow_steer_promisc_remove(mdev->dev, | |
938 | priv->port, | |
f9162539 | 939 | MLX4_FS_MC_DEFAULT); |
592e49dd HHZ |
940 | break; |
941 | ||
c96d97f4 HHZ |
942 | case MLX4_STEERING_MODE_B0: |
943 | err = mlx4_multicast_promisc_remove(mdev->dev, | |
944 | priv->base_qpn, | |
945 | priv->port); | |
946 | break; | |
947 | ||
948 | case MLX4_STEERING_MODE_A0: | |
949 | break; | |
950 | } | |
1679200f | 951 | if (err) |
25985edc | 952 | en_err(priv, "Failed disabling multicast promiscuous mode\n"); |
1679200f YP |
953 | priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC; |
954 | } | |
ff6e2163 | 955 | |
c27a02cd YP |
956 | err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, |
957 | 0, MLX4_MCAST_DISABLE); | |
958 | if (err) | |
453a6082 | 959 | en_err(priv, "Failed disabling multicast filter\n"); |
c27a02cd YP |
960 | |
961 | /* Flush mcast filter and init it with broadcast address */ | |
962 | mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST, | |
963 | 1, MLX4_MCAST_CONFIG); | |
964 | ||
965 | /* Update multicast list - we cache all addresses so they won't | |
966 | * change while HW is updated holding the command semaphor */ | |
dbd501a8 | 967 | netif_addr_lock_bh(dev); |
c27a02cd | 968 | mlx4_en_cache_mclist(dev); |
dbd501a8 | 969 | netif_addr_unlock_bh(dev); |
6d199937 | 970 | list_for_each_entry(mclist, &priv->mc_list, list) { |
9813337a | 971 | mcast_addr = mlx4_mac_to_u64(mclist->addr); |
c27a02cd YP |
972 | mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, |
973 | mcast_addr, 0, MLX4_MCAST_CONFIG); | |
974 | } | |
975 | err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, | |
976 | 0, MLX4_MCAST_ENABLE); | |
977 | if (err) | |
453a6082 | 978 | en_err(priv, "Failed enabling multicast filter\n"); |
6d199937 YP |
979 | |
980 | update_mclist_flags(priv, &priv->curr_list, &priv->mc_list); | |
981 | list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) { | |
982 | if (mclist->action == MCLIST_REM) { | |
983 | /* detach this address and delete from list */ | |
984 | memcpy(&mc_list[10], mclist->addr, ETH_ALEN); | |
985 | mc_list[5] = priv->port; | |
986 | err = mlx4_multicast_detach(mdev->dev, | |
987 | &priv->rss_map.indir_qp, | |
988 | mc_list, | |
0ff1fb65 HHZ |
989 | MLX4_PROT_ETH, |
990 | mclist->reg_id); | |
6d199937 YP |
991 | if (err) |
992 | en_err(priv, "Fail to detach multicast address\n"); | |
993 | ||
837052d0 OG |
994 | if (mclist->tunnel_reg_id) { |
995 | err = mlx4_flow_detach(priv->mdev->dev, mclist->tunnel_reg_id); | |
996 | if (err) | |
997 | en_err(priv, "Failed to detach multicast address\n"); | |
998 | } | |
999 | ||
6d199937 YP |
1000 | /* remove from list */ |
1001 | list_del(&mclist->list); | |
1002 | kfree(mclist); | |
9c64508a | 1003 | } else if (mclist->action == MCLIST_ADD) { |
6d199937 YP |
1004 | /* attach the address */ |
1005 | memcpy(&mc_list[10], mclist->addr, ETH_ALEN); | |
0ff1fb65 | 1006 | /* needed for B0 steering support */ |
6d199937 YP |
1007 | mc_list[5] = priv->port; |
1008 | err = mlx4_multicast_attach(mdev->dev, | |
1009 | &priv->rss_map.indir_qp, | |
0ff1fb65 HHZ |
1010 | mc_list, |
1011 | priv->port, 0, | |
1012 | MLX4_PROT_ETH, | |
1013 | &mclist->reg_id); | |
6d199937 YP |
1014 | if (err) |
1015 | en_err(priv, "Fail to attach multicast address\n"); | |
1016 | ||
837052d0 OG |
1017 | err = mlx4_en_tunnel_steer_add(priv, &mc_list[10], priv->base_qpn, |
1018 | &mclist->tunnel_reg_id); | |
1019 | if (err) | |
1020 | en_err(priv, "Failed to attach multicast address\n"); | |
6d199937 YP |
1021 | } |
1022 | } | |
c27a02cd | 1023 | } |
0eb74fdd YB |
1024 | } |
1025 | ||
cc5387f7 YB |
1026 | static void mlx4_en_do_uc_filter(struct mlx4_en_priv *priv, |
1027 | struct net_device *dev, | |
1028 | struct mlx4_en_dev *mdev) | |
1029 | { | |
1030 | struct netdev_hw_addr *ha; | |
1031 | struct mlx4_mac_entry *entry; | |
b67bfe0d | 1032 | struct hlist_node *tmp; |
cc5387f7 YB |
1033 | bool found; |
1034 | u64 mac; | |
1035 | int err = 0; | |
1036 | struct hlist_head *bucket; | |
1037 | unsigned int i; | |
1038 | int removed = 0; | |
1039 | u32 prev_flags; | |
1040 | ||
1041 | /* Note that we do not need to protect our mac_hash traversal with rcu, | |
1042 | * since all modification code is protected by mdev->state_lock | |
1043 | */ | |
1044 | ||
1045 | /* find what to remove */ | |
1046 | for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) { | |
1047 | bucket = &priv->mac_hash[i]; | |
b67bfe0d | 1048 | hlist_for_each_entry_safe(entry, tmp, bucket, hlist) { |
cc5387f7 YB |
1049 | found = false; |
1050 | netdev_for_each_uc_addr(ha, dev) { | |
1051 | if (ether_addr_equal_64bits(entry->mac, | |
1052 | ha->addr)) { | |
1053 | found = true; | |
1054 | break; | |
1055 | } | |
1056 | } | |
1057 | ||
1058 | /* MAC address of the port is not in uc list */ | |
2695bab2 NO |
1059 | if (ether_addr_equal_64bits(entry->mac, |
1060 | priv->current_mac)) | |
cc5387f7 YB |
1061 | found = true; |
1062 | ||
1063 | if (!found) { | |
9813337a | 1064 | mac = mlx4_mac_to_u64(entry->mac); |
cc5387f7 YB |
1065 | mlx4_en_uc_steer_release(priv, entry->mac, |
1066 | priv->base_qpn, | |
1067 | entry->reg_id); | |
1068 | mlx4_unregister_mac(mdev->dev, priv->port, mac); | |
1069 | ||
1070 | hlist_del_rcu(&entry->hlist); | |
1071 | kfree_rcu(entry, rcu); | |
1072 | en_dbg(DRV, priv, "Removed MAC %pM on port:%d\n", | |
1073 | entry->mac, priv->port); | |
1074 | ++removed; | |
1075 | } | |
1076 | } | |
1077 | } | |
1078 | ||
1079 | /* if we didn't remove anything, there is no use in trying to add | |
1080 | * again once we are in a forced promisc mode state | |
1081 | */ | |
1082 | if ((priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) && 0 == removed) | |
1083 | return; | |
1084 | ||
1085 | prev_flags = priv->flags; | |
1086 | priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC; | |
1087 | ||
1088 | /* find what to add */ | |
1089 | netdev_for_each_uc_addr(ha, dev) { | |
1090 | found = false; | |
1091 | bucket = &priv->mac_hash[ha->addr[MLX4_EN_MAC_HASH_IDX]]; | |
b67bfe0d | 1092 | hlist_for_each_entry(entry, bucket, hlist) { |
cc5387f7 YB |
1093 | if (ether_addr_equal_64bits(entry->mac, ha->addr)) { |
1094 | found = true; | |
1095 | break; | |
1096 | } | |
1097 | } | |
1098 | ||
1099 | if (!found) { | |
1100 | entry = kmalloc(sizeof(*entry), GFP_KERNEL); | |
1101 | if (!entry) { | |
1102 | en_err(priv, "Failed adding MAC %pM on port:%d (out of memory)\n", | |
1103 | ha->addr, priv->port); | |
1104 | priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC; | |
1105 | break; | |
1106 | } | |
9813337a | 1107 | mac = mlx4_mac_to_u64(ha->addr); |
cc5387f7 YB |
1108 | memcpy(entry->mac, ha->addr, ETH_ALEN); |
1109 | err = mlx4_register_mac(mdev->dev, priv->port, mac); | |
1110 | if (err < 0) { | |
1111 | en_err(priv, "Failed registering MAC %pM on port %d: %d\n", | |
1112 | ha->addr, priv->port, err); | |
1113 | kfree(entry); | |
1114 | priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC; | |
1115 | break; | |
1116 | } | |
1117 | err = mlx4_en_uc_steer_add(priv, ha->addr, | |
1118 | &priv->base_qpn, | |
1119 | &entry->reg_id); | |
1120 | if (err) { | |
1121 | en_err(priv, "Failed adding MAC %pM on port %d: %d\n", | |
1122 | ha->addr, priv->port, err); | |
1123 | mlx4_unregister_mac(mdev->dev, priv->port, mac); | |
1124 | kfree(entry); | |
1125 | priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC; | |
1126 | break; | |
1127 | } else { | |
1128 | unsigned int mac_hash; | |
1129 | en_dbg(DRV, priv, "Added MAC %pM on port:%d\n", | |
1130 | ha->addr, priv->port); | |
1131 | mac_hash = ha->addr[MLX4_EN_MAC_HASH_IDX]; | |
1132 | bucket = &priv->mac_hash[mac_hash]; | |
1133 | hlist_add_head_rcu(&entry->hlist, bucket); | |
1134 | } | |
1135 | } | |
1136 | } | |
1137 | ||
1138 | if (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) { | |
1139 | en_warn(priv, "Forcing promiscuous mode on port:%d\n", | |
1140 | priv->port); | |
1141 | } else if (prev_flags & MLX4_EN_FLAG_FORCE_PROMISC) { | |
1142 | en_warn(priv, "Stop forcing promiscuous mode on port:%d\n", | |
1143 | priv->port); | |
1144 | } | |
1145 | } | |
1146 | ||
0eb74fdd YB |
1147 | static void mlx4_en_do_set_rx_mode(struct work_struct *work) |
1148 | { | |
1149 | struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, | |
1150 | rx_mode_task); | |
1151 | struct mlx4_en_dev *mdev = priv->mdev; | |
1152 | struct net_device *dev = priv->dev; | |
1153 | ||
1154 | mutex_lock(&mdev->state_lock); | |
1155 | if (!mdev->device_up) { | |
1156 | en_dbg(HW, priv, "Card is not up, ignoring rx mode change.\n"); | |
1157 | goto out; | |
1158 | } | |
1159 | if (!priv->port_up) { | |
1160 | en_dbg(HW, priv, "Port is down, ignoring rx mode change.\n"); | |
1161 | goto out; | |
1162 | } | |
1163 | ||
1164 | if (!netif_carrier_ok(dev)) { | |
1165 | if (!mlx4_en_QUERY_PORT(mdev, priv->port)) { | |
1166 | if (priv->port_state.link_state) { | |
1167 | priv->last_link_state = MLX4_DEV_EVENT_PORT_UP; | |
1168 | netif_carrier_on(dev); | |
1169 | en_dbg(LINK, priv, "Link Up\n"); | |
1170 | } | |
1171 | } | |
1172 | } | |
1173 | ||
cc5387f7 YB |
1174 | if (dev->priv_flags & IFF_UNICAST_FLT) |
1175 | mlx4_en_do_uc_filter(priv, dev, mdev); | |
1176 | ||
0eb74fdd | 1177 | /* Promsicuous mode: disable all filters */ |
cc5387f7 YB |
1178 | if ((dev->flags & IFF_PROMISC) || |
1179 | (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC)) { | |
0eb74fdd YB |
1180 | mlx4_en_set_promisc_mode(priv, mdev); |
1181 | goto out; | |
1182 | } | |
1183 | ||
1184 | /* Not in promiscuous mode */ | |
1185 | if (priv->flags & MLX4_EN_FLAG_PROMISC) | |
1186 | mlx4_en_clear_promisc_mode(priv, mdev); | |
1187 | ||
1188 | mlx4_en_do_multicast(priv, dev, mdev); | |
c27a02cd YP |
1189 | out: |
1190 | mutex_unlock(&mdev->state_lock); | |
1191 | } | |
1192 | ||
1193 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1194 | static void mlx4_en_netpoll(struct net_device *dev) | |
1195 | { | |
1196 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1197 | struct mlx4_en_cq *cq; | |
c27a02cd YP |
1198 | int i; |
1199 | ||
1200 | for (i = 0; i < priv->rx_ring_num; i++) { | |
41d942d5 | 1201 | cq = priv->rx_cq[i]; |
c98235cb | 1202 | napi_schedule(&cq->napi); |
c27a02cd YP |
1203 | } |
1204 | } | |
1205 | #endif | |
1206 | ||
ba4b87ae IS |
1207 | static int mlx4_en_set_rss_steer_rules(struct mlx4_en_priv *priv) |
1208 | { | |
1209 | u64 reg_id; | |
1210 | int err = 0; | |
1211 | int *qpn = &priv->base_qpn; | |
1212 | struct mlx4_mac_entry *entry; | |
1213 | ||
1214 | err = mlx4_en_uc_steer_add(priv, priv->dev->dev_addr, qpn, ®_id); | |
1215 | if (err) | |
1216 | return err; | |
1217 | ||
1218 | err = mlx4_en_tunnel_steer_add(priv, priv->dev->dev_addr, *qpn, | |
1219 | &priv->tunnel_reg_id); | |
1220 | if (err) | |
1221 | goto tunnel_err; | |
1222 | ||
1223 | entry = kmalloc(sizeof(*entry), GFP_KERNEL); | |
1224 | if (!entry) { | |
1225 | err = -ENOMEM; | |
1226 | goto alloc_err; | |
1227 | } | |
1228 | ||
1229 | memcpy(entry->mac, priv->dev->dev_addr, sizeof(entry->mac)); | |
1230 | memcpy(priv->current_mac, entry->mac, sizeof(priv->current_mac)); | |
1231 | entry->reg_id = reg_id; | |
1232 | hlist_add_head_rcu(&entry->hlist, | |
1233 | &priv->mac_hash[entry->mac[MLX4_EN_MAC_HASH_IDX]]); | |
1234 | ||
1235 | return 0; | |
1236 | ||
1237 | alloc_err: | |
1238 | if (priv->tunnel_reg_id) | |
1239 | mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id); | |
1240 | ||
1241 | tunnel_err: | |
1242 | mlx4_en_uc_steer_release(priv, priv->dev->dev_addr, *qpn, reg_id); | |
1243 | return err; | |
1244 | } | |
1245 | ||
1246 | static void mlx4_en_delete_rss_steer_rules(struct mlx4_en_priv *priv) | |
1247 | { | |
1248 | u64 mac; | |
1249 | unsigned int i; | |
1250 | int qpn = priv->base_qpn; | |
1251 | struct hlist_head *bucket; | |
1252 | struct hlist_node *tmp; | |
1253 | struct mlx4_mac_entry *entry; | |
1254 | ||
1255 | for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) { | |
1256 | bucket = &priv->mac_hash[i]; | |
1257 | hlist_for_each_entry_safe(entry, tmp, bucket, hlist) { | |
1258 | mac = mlx4_mac_to_u64(entry->mac); | |
1259 | en_dbg(DRV, priv, "Registering MAC:%pM for deleting\n", | |
1260 | entry->mac); | |
1261 | mlx4_en_uc_steer_release(priv, entry->mac, | |
1262 | qpn, entry->reg_id); | |
1263 | ||
1264 | mlx4_unregister_mac(priv->mdev->dev, priv->port, mac); | |
1265 | hlist_del_rcu(&entry->hlist); | |
1266 | kfree_rcu(entry, rcu); | |
1267 | } | |
1268 | } | |
1269 | ||
1270 | if (priv->tunnel_reg_id) { | |
1271 | mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id); | |
1272 | priv->tunnel_reg_id = 0; | |
1273 | } | |
1274 | } | |
1275 | ||
c27a02cd YP |
1276 | static void mlx4_en_tx_timeout(struct net_device *dev) |
1277 | { | |
1278 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1279 | struct mlx4_en_dev *mdev = priv->mdev; | |
b944ebec | 1280 | int i; |
c27a02cd YP |
1281 | |
1282 | if (netif_msg_timer(priv)) | |
453a6082 | 1283 | en_warn(priv, "Tx timeout called on port:%d\n", priv->port); |
c27a02cd | 1284 | |
b944ebec YP |
1285 | for (i = 0; i < priv->tx_ring_num; i++) { |
1286 | if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i))) | |
1287 | continue; | |
1288 | en_warn(priv, "TX timeout on queue: %d, QP: 0x%x, CQ: 0x%x, Cons: 0x%x, Prod: 0x%x\n", | |
41d942d5 EE |
1289 | i, priv->tx_ring[i]->qpn, priv->tx_ring[i]->cqn, |
1290 | priv->tx_ring[i]->cons, priv->tx_ring[i]->prod); | |
b944ebec YP |
1291 | } |
1292 | ||
1e338db5 | 1293 | priv->port_stats.tx_timeout++; |
453a6082 | 1294 | en_dbg(DRV, priv, "Scheduling watchdog\n"); |
1e338db5 | 1295 | queue_work(mdev->workqueue, &priv->watchdog_task); |
c27a02cd YP |
1296 | } |
1297 | ||
1298 | ||
9ed17db1 ED |
1299 | static struct rtnl_link_stats64 * |
1300 | mlx4_en_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) | |
c27a02cd YP |
1301 | { |
1302 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1303 | ||
1304 | spin_lock_bh(&priv->stats_lock); | |
f73a6f43 | 1305 | netdev_stats_to_stats64(stats, &dev->stats); |
c27a02cd YP |
1306 | spin_unlock_bh(&priv->stats_lock); |
1307 | ||
9ed17db1 | 1308 | return stats; |
c27a02cd YP |
1309 | } |
1310 | ||
1311 | static void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv) | |
1312 | { | |
c27a02cd YP |
1313 | struct mlx4_en_cq *cq; |
1314 | int i; | |
1315 | ||
1316 | /* If we haven't received a specific coalescing setting | |
98a1708d | 1317 | * (module param), we set the moderation parameters as follows: |
c27a02cd | 1318 | * - moder_cnt is set to the number of mtu sized packets to |
ecfd2ce1 | 1319 | * satisfy our coalescing target. |
c27a02cd YP |
1320 | * - moder_time is set to a fixed value. |
1321 | */ | |
3db36fb2 | 1322 | priv->rx_frames = MLX4_EN_RX_COAL_TARGET; |
60b9f9e5 | 1323 | priv->rx_usecs = MLX4_EN_RX_COAL_TIME; |
a19a848a YP |
1324 | priv->tx_frames = MLX4_EN_TX_COAL_PKTS; |
1325 | priv->tx_usecs = MLX4_EN_TX_COAL_TIME; | |
48e551ff YB |
1326 | en_dbg(INTR, priv, "Default coalesing params for mtu:%d - rx_frames:%d rx_usecs:%d\n", |
1327 | priv->dev->mtu, priv->rx_frames, priv->rx_usecs); | |
c27a02cd YP |
1328 | |
1329 | /* Setup cq moderation params */ | |
1330 | for (i = 0; i < priv->rx_ring_num; i++) { | |
41d942d5 | 1331 | cq = priv->rx_cq[i]; |
c27a02cd YP |
1332 | cq->moder_cnt = priv->rx_frames; |
1333 | cq->moder_time = priv->rx_usecs; | |
6b4d8d9f AG |
1334 | priv->last_moder_time[i] = MLX4_EN_AUTO_CONF; |
1335 | priv->last_moder_packets[i] = 0; | |
1336 | priv->last_moder_bytes[i] = 0; | |
c27a02cd YP |
1337 | } |
1338 | ||
1339 | for (i = 0; i < priv->tx_ring_num; i++) { | |
41d942d5 | 1340 | cq = priv->tx_cq[i]; |
a19a848a YP |
1341 | cq->moder_cnt = priv->tx_frames; |
1342 | cq->moder_time = priv->tx_usecs; | |
c27a02cd YP |
1343 | } |
1344 | ||
1345 | /* Reset auto-moderation params */ | |
1346 | priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW; | |
1347 | priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW; | |
1348 | priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH; | |
1349 | priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH; | |
1350 | priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL; | |
60b9f9e5 | 1351 | priv->adaptive_rx_coal = 1; |
c27a02cd | 1352 | priv->last_moder_jiffies = 0; |
c27a02cd | 1353 | priv->last_moder_tx_packets = 0; |
c27a02cd YP |
1354 | } |
1355 | ||
1356 | static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv) | |
1357 | { | |
1358 | unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies); | |
c27a02cd YP |
1359 | struct mlx4_en_cq *cq; |
1360 | unsigned long packets; | |
1361 | unsigned long rate; | |
1362 | unsigned long avg_pkt_size; | |
1363 | unsigned long rx_packets; | |
1364 | unsigned long rx_bytes; | |
c27a02cd YP |
1365 | unsigned long rx_pkt_diff; |
1366 | int moder_time; | |
6b4d8d9f | 1367 | int ring, err; |
c27a02cd YP |
1368 | |
1369 | if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ) | |
1370 | return; | |
1371 | ||
6b4d8d9f AG |
1372 | for (ring = 0; ring < priv->rx_ring_num; ring++) { |
1373 | spin_lock_bh(&priv->stats_lock); | |
41d942d5 EE |
1374 | rx_packets = priv->rx_ring[ring]->packets; |
1375 | rx_bytes = priv->rx_ring[ring]->bytes; | |
6b4d8d9f AG |
1376 | spin_unlock_bh(&priv->stats_lock); |
1377 | ||
1378 | rx_pkt_diff = ((unsigned long) (rx_packets - | |
1379 | priv->last_moder_packets[ring])); | |
1380 | packets = rx_pkt_diff; | |
1381 | rate = packets * HZ / period; | |
1382 | avg_pkt_size = packets ? ((unsigned long) (rx_bytes - | |
1383 | priv->last_moder_bytes[ring])) / packets : 0; | |
1384 | ||
1385 | /* Apply auto-moderation only when packet rate | |
1386 | * exceeds a rate that it matters */ | |
1387 | if (rate > (MLX4_EN_RX_RATE_THRESH / priv->rx_ring_num) && | |
1388 | avg_pkt_size > MLX4_EN_AVG_PKT_SMALL) { | |
c27a02cd YP |
1389 | if (rate < priv->pkt_rate_low) |
1390 | moder_time = priv->rx_usecs_low; | |
1391 | else if (rate > priv->pkt_rate_high) | |
1392 | moder_time = priv->rx_usecs_high; | |
1393 | else | |
1394 | moder_time = (rate - priv->pkt_rate_low) * | |
1395 | (priv->rx_usecs_high - priv->rx_usecs_low) / | |
1396 | (priv->pkt_rate_high - priv->pkt_rate_low) + | |
1397 | priv->rx_usecs_low; | |
6b4d8d9f AG |
1398 | } else { |
1399 | moder_time = priv->rx_usecs_low; | |
c27a02cd | 1400 | } |
c27a02cd | 1401 | |
6b4d8d9f AG |
1402 | if (moder_time != priv->last_moder_time[ring]) { |
1403 | priv->last_moder_time[ring] = moder_time; | |
41d942d5 | 1404 | cq = priv->rx_cq[ring]; |
c27a02cd | 1405 | cq->moder_time = moder_time; |
a1c6693a | 1406 | cq->moder_cnt = priv->rx_frames; |
c27a02cd | 1407 | err = mlx4_en_set_cq_moder(priv, cq); |
6b4d8d9f | 1408 | if (err) |
48e551ff YB |
1409 | en_err(priv, "Failed modifying moderation for cq:%d\n", |
1410 | ring); | |
c27a02cd | 1411 | } |
6b4d8d9f AG |
1412 | priv->last_moder_packets[ring] = rx_packets; |
1413 | priv->last_moder_bytes[ring] = rx_bytes; | |
c27a02cd YP |
1414 | } |
1415 | ||
c27a02cd YP |
1416 | priv->last_moder_jiffies = jiffies; |
1417 | } | |
1418 | ||
1419 | static void mlx4_en_do_get_stats(struct work_struct *work) | |
1420 | { | |
bf6aede7 | 1421 | struct delayed_work *delay = to_delayed_work(work); |
c27a02cd YP |
1422 | struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv, |
1423 | stats_task); | |
1424 | struct mlx4_en_dev *mdev = priv->mdev; | |
1425 | int err; | |
1426 | ||
c27a02cd YP |
1427 | mutex_lock(&mdev->state_lock); |
1428 | if (mdev->device_up) { | |
6123db2e JM |
1429 | if (priv->port_up) { |
1430 | err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0); | |
1431 | if (err) | |
1432 | en_dbg(HW, priv, "Could not update stats\n"); | |
2d51837f | 1433 | |
c27a02cd | 1434 | mlx4_en_auto_moderation(priv); |
6123db2e | 1435 | } |
c27a02cd YP |
1436 | |
1437 | queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY); | |
1438 | } | |
d7e1a487 | 1439 | if (mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port]) { |
2695bab2 | 1440 | mlx4_en_do_set_mac(priv, priv->current_mac); |
d7e1a487 YP |
1441 | mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port] = 0; |
1442 | } | |
c27a02cd YP |
1443 | mutex_unlock(&mdev->state_lock); |
1444 | } | |
1445 | ||
b6c39bfc AV |
1446 | /* mlx4_en_service_task - Run service task for tasks that needed to be done |
1447 | * periodically | |
1448 | */ | |
1449 | static void mlx4_en_service_task(struct work_struct *work) | |
1450 | { | |
1451 | struct delayed_work *delay = to_delayed_work(work); | |
1452 | struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv, | |
1453 | service_task); | |
1454 | struct mlx4_en_dev *mdev = priv->mdev; | |
1455 | ||
1456 | mutex_lock(&mdev->state_lock); | |
1457 | if (mdev->device_up) { | |
dc8142ea AV |
1458 | if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) |
1459 | mlx4_en_ptp_overflow_check(mdev); | |
b6c39bfc | 1460 | |
07841f9d | 1461 | mlx4_en_recover_from_oom(priv); |
b6c39bfc AV |
1462 | queue_delayed_work(mdev->workqueue, &priv->service_task, |
1463 | SERVICE_TASK_DELAY); | |
1464 | } | |
1465 | mutex_unlock(&mdev->state_lock); | |
1466 | } | |
1467 | ||
c27a02cd YP |
1468 | static void mlx4_en_linkstate(struct work_struct *work) |
1469 | { | |
1470 | struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, | |
1471 | linkstate_task); | |
1472 | struct mlx4_en_dev *mdev = priv->mdev; | |
1473 | int linkstate = priv->link_state; | |
1474 | ||
1475 | mutex_lock(&mdev->state_lock); | |
1476 | /* If observable port state changed set carrier state and | |
1477 | * report to system log */ | |
1478 | if (priv->last_link_state != linkstate) { | |
1479 | if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) { | |
e5cc44b2 | 1480 | en_info(priv, "Link Down\n"); |
c27a02cd YP |
1481 | netif_carrier_off(priv->dev); |
1482 | } else { | |
e5cc44b2 | 1483 | en_info(priv, "Link Up\n"); |
c27a02cd YP |
1484 | netif_carrier_on(priv->dev); |
1485 | } | |
1486 | } | |
1487 | priv->last_link_state = linkstate; | |
1488 | mutex_unlock(&mdev->state_lock); | |
1489 | } | |
1490 | ||
9e311e77 YA |
1491 | static int mlx4_en_init_affinity_hint(struct mlx4_en_priv *priv, int ring_idx) |
1492 | { | |
1493 | struct mlx4_en_rx_ring *ring = priv->rx_ring[ring_idx]; | |
1494 | int numa_node = priv->mdev->dev->numa_node; | |
9e311e77 YA |
1495 | |
1496 | if (!zalloc_cpumask_var(&ring->affinity_mask, GFP_KERNEL)) | |
1497 | return -ENOMEM; | |
1498 | ||
f36963c9 RR |
1499 | cpumask_set_cpu(cpumask_local_spread(ring_idx, numa_node), |
1500 | ring->affinity_mask); | |
1501 | return 0; | |
9e311e77 YA |
1502 | } |
1503 | ||
1504 | static void mlx4_en_free_affinity_hint(struct mlx4_en_priv *priv, int ring_idx) | |
1505 | { | |
1506 | free_cpumask_var(priv->rx_ring[ring_idx]->affinity_mask); | |
1507 | } | |
c27a02cd | 1508 | |
18cc42a3 | 1509 | int mlx4_en_start_port(struct net_device *dev) |
c27a02cd YP |
1510 | { |
1511 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1512 | struct mlx4_en_dev *mdev = priv->mdev; | |
1513 | struct mlx4_en_cq *cq; | |
1514 | struct mlx4_en_tx_ring *tx_ring; | |
c27a02cd YP |
1515 | int rx_index = 0; |
1516 | int tx_index = 0; | |
c27a02cd YP |
1517 | int err = 0; |
1518 | int i; | |
1519 | int j; | |
1679200f | 1520 | u8 mc_list[16] = {0}; |
c27a02cd YP |
1521 | |
1522 | if (priv->port_up) { | |
453a6082 | 1523 | en_dbg(DRV, priv, "start port called while port already up\n"); |
c27a02cd YP |
1524 | return 0; |
1525 | } | |
1526 | ||
6d199937 YP |
1527 | INIT_LIST_HEAD(&priv->mc_list); |
1528 | INIT_LIST_HEAD(&priv->curr_list); | |
0d256c0e HHZ |
1529 | INIT_LIST_HEAD(&priv->ethtool_list); |
1530 | memset(&priv->ethtool_rules[0], 0, | |
1531 | sizeof(struct ethtool_flow_id) * MAX_NUM_OF_FS_RULES); | |
6d199937 | 1532 | |
c27a02cd YP |
1533 | /* Calculate Rx buf size */ |
1534 | dev->mtu = min(dev->mtu, priv->max_mtu); | |
1535 | mlx4_en_calc_rx_buf(dev); | |
453a6082 | 1536 | en_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size); |
38aab07c | 1537 | |
c27a02cd | 1538 | /* Configure rx cq's and rings */ |
38aab07c YP |
1539 | err = mlx4_en_activate_rx_rings(priv); |
1540 | if (err) { | |
453a6082 | 1541 | en_err(priv, "Failed to activate RX rings\n"); |
38aab07c YP |
1542 | return err; |
1543 | } | |
c27a02cd | 1544 | for (i = 0; i < priv->rx_ring_num; i++) { |
41d942d5 | 1545 | cq = priv->rx_cq[i]; |
c27a02cd | 1546 | |
9e311e77 YA |
1547 | err = mlx4_en_init_affinity_hint(priv, i); |
1548 | if (err) { | |
1549 | en_err(priv, "Failed preparing IRQ affinity hint\n"); | |
1550 | goto cq_err; | |
1551 | } | |
1552 | ||
76532d0c | 1553 | err = mlx4_en_activate_cq(priv, cq, i); |
c27a02cd | 1554 | if (err) { |
453a6082 | 1555 | en_err(priv, "Failed activating Rx CQ\n"); |
9e311e77 | 1556 | mlx4_en_free_affinity_hint(priv, i); |
a4233304 | 1557 | goto cq_err; |
c27a02cd | 1558 | } |
c3f2511f IS |
1559 | |
1560 | for (j = 0; j < cq->size; j++) { | |
1561 | struct mlx4_cqe *cqe = NULL; | |
1562 | ||
1563 | cqe = mlx4_en_get_cqe(cq->buf, j, priv->cqe_size) + | |
1564 | priv->cqe_factor; | |
1565 | cqe->owner_sr_opcode = MLX4_CQE_OWNER_MASK; | |
1566 | } | |
1567 | ||
c27a02cd YP |
1568 | err = mlx4_en_set_cq_moder(priv, cq); |
1569 | if (err) { | |
1a91de28 | 1570 | en_err(priv, "Failed setting cq moderation parameters\n"); |
c27a02cd | 1571 | mlx4_en_deactivate_cq(priv, cq); |
9e311e77 | 1572 | mlx4_en_free_affinity_hint(priv, i); |
c27a02cd YP |
1573 | goto cq_err; |
1574 | } | |
1575 | mlx4_en_arm_cq(priv, cq); | |
41d942d5 | 1576 | priv->rx_ring[i]->cqn = cq->mcq.cqn; |
c27a02cd YP |
1577 | ++rx_index; |
1578 | } | |
1579 | ||
ffe455ad EE |
1580 | /* Set qp number */ |
1581 | en_dbg(DRV, priv, "Getting qp number for port %d\n", priv->port); | |
16a10ffd | 1582 | err = mlx4_en_get_qp(priv); |
1679200f | 1583 | if (err) { |
ffe455ad | 1584 | en_err(priv, "Failed getting eth qp\n"); |
1679200f YP |
1585 | goto cq_err; |
1586 | } | |
1587 | mdev->mac_removed[priv->port] = 0; | |
1588 | ||
6de5f7f6 EBE |
1589 | priv->counter_index = |
1590 | mlx4_get_default_counter_index(mdev->dev, priv->port); | |
1591 | ||
c27a02cd YP |
1592 | err = mlx4_en_config_rss_steer(priv); |
1593 | if (err) { | |
453a6082 | 1594 | en_err(priv, "Failed configuring rss steering\n"); |
1679200f | 1595 | goto mac_err; |
c27a02cd YP |
1596 | } |
1597 | ||
cabdc8ee HHZ |
1598 | err = mlx4_en_create_drop_qp(priv); |
1599 | if (err) | |
1600 | goto rss_err; | |
1601 | ||
c27a02cd YP |
1602 | /* Configure tx cq's and rings */ |
1603 | for (i = 0; i < priv->tx_ring_num; i++) { | |
1604 | /* Configure cq */ | |
41d942d5 | 1605 | cq = priv->tx_cq[i]; |
76532d0c | 1606 | err = mlx4_en_activate_cq(priv, cq, i); |
c27a02cd | 1607 | if (err) { |
453a6082 | 1608 | en_err(priv, "Failed allocating Tx CQ\n"); |
c27a02cd YP |
1609 | goto tx_err; |
1610 | } | |
1611 | err = mlx4_en_set_cq_moder(priv, cq); | |
1612 | if (err) { | |
1a91de28 | 1613 | en_err(priv, "Failed setting cq moderation parameters\n"); |
c27a02cd YP |
1614 | mlx4_en_deactivate_cq(priv, cq); |
1615 | goto tx_err; | |
1616 | } | |
453a6082 | 1617 | en_dbg(DRV, priv, "Resetting index of collapsed CQ:%d to -1\n", i); |
c27a02cd YP |
1618 | cq->buf->wqe_index = cpu_to_be16(0xffff); |
1619 | ||
1620 | /* Configure ring */ | |
41d942d5 | 1621 | tx_ring = priv->tx_ring[i]; |
0e98b523 | 1622 | err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn, |
d317966b | 1623 | i / priv->num_tx_rings_p_up); |
c27a02cd | 1624 | if (err) { |
453a6082 | 1625 | en_err(priv, "Failed allocating Tx ring\n"); |
c27a02cd YP |
1626 | mlx4_en_deactivate_cq(priv, cq); |
1627 | goto tx_err; | |
1628 | } | |
5b263f53 | 1629 | tx_ring->tx_queue = netdev_get_tx_queue(dev, i); |
e22979d9 YP |
1630 | |
1631 | /* Arm CQ for TX completions */ | |
1632 | mlx4_en_arm_cq(priv, cq); | |
1633 | ||
c27a02cd YP |
1634 | /* Set initial ownership of all Tx TXBBs to SW (1) */ |
1635 | for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE) | |
1636 | *((u32 *) (tx_ring->buf + j)) = 0xffffffff; | |
1637 | ++tx_index; | |
1638 | } | |
1639 | ||
1640 | /* Configure port */ | |
1641 | err = mlx4_SET_PORT_general(mdev->dev, priv->port, | |
1642 | priv->rx_skb_size + ETH_FCS_LEN, | |
d53b93f2 YP |
1643 | priv->prof->tx_pause, |
1644 | priv->prof->tx_ppp, | |
1645 | priv->prof->rx_pause, | |
1646 | priv->prof->rx_ppp); | |
c27a02cd | 1647 | if (err) { |
48e551ff YB |
1648 | en_err(priv, "Failed setting port general configurations for port %d, with error %d\n", |
1649 | priv->port, err); | |
c27a02cd YP |
1650 | goto tx_err; |
1651 | } | |
1652 | /* Set default qp number */ | |
1653 | err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0); | |
1654 | if (err) { | |
453a6082 | 1655 | en_err(priv, "Failed setting default qp numbers\n"); |
c27a02cd YP |
1656 | goto tx_err; |
1657 | } | |
c27a02cd | 1658 | |
837052d0 | 1659 | if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { |
1b136de1 | 1660 | err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1); |
837052d0 OG |
1661 | if (err) { |
1662 | en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n", | |
1663 | err); | |
1664 | goto tx_err; | |
1665 | } | |
1666 | } | |
1667 | ||
c27a02cd | 1668 | /* Init port */ |
453a6082 | 1669 | en_dbg(HW, priv, "Initializing port\n"); |
c27a02cd YP |
1670 | err = mlx4_INIT_PORT(mdev->dev, priv->port); |
1671 | if (err) { | |
453a6082 | 1672 | en_err(priv, "Failed Initializing port\n"); |
1679200f | 1673 | goto tx_err; |
c27a02cd YP |
1674 | } |
1675 | ||
ba4b87ae IS |
1676 | /* Set Unicast and VXLAN steering rules */ |
1677 | if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0 && | |
1678 | mlx4_en_set_rss_steer_rules(priv)) | |
1679 | mlx4_warn(mdev, "Failed setting steering rules\n"); | |
1680 | ||
1679200f | 1681 | /* Attach rx QP to bradcast address */ |
c7bf7169 | 1682 | eth_broadcast_addr(&mc_list[10]); |
0ff1fb65 | 1683 | mc_list[5] = priv->port; /* needed for B0 steering support */ |
1679200f | 1684 | if (mlx4_multicast_attach(mdev->dev, &priv->rss_map.indir_qp, mc_list, |
0ff1fb65 HHZ |
1685 | priv->port, 0, MLX4_PROT_ETH, |
1686 | &priv->broadcast_id)) | |
1679200f YP |
1687 | mlx4_warn(mdev, "Failed Attaching Broadcast\n"); |
1688 | ||
b5845f98 HX |
1689 | /* Must redo promiscuous mode setup. */ |
1690 | priv->flags &= ~(MLX4_EN_FLAG_PROMISC | MLX4_EN_FLAG_MC_PROMISC); | |
1691 | ||
c27a02cd | 1692 | /* Schedule multicast task to populate multicast list */ |
0eb74fdd | 1693 | queue_work(mdev->workqueue, &priv->rx_mode_task); |
c27a02cd | 1694 | |
a66132f3 | 1695 | #ifdef CONFIG_MLX4_EN_VXLAN |
9737c6ab | 1696 | if (priv->mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) |
1b136de1 | 1697 | vxlan_get_rx_port(dev); |
a66132f3 | 1698 | #endif |
c27a02cd | 1699 | priv->port_up = true; |
a11faac7 | 1700 | netif_tx_start_all_queues(dev); |
3484aac1 AV |
1701 | netif_device_attach(dev); |
1702 | ||
c27a02cd YP |
1703 | return 0; |
1704 | ||
c27a02cd YP |
1705 | tx_err: |
1706 | while (tx_index--) { | |
41d942d5 EE |
1707 | mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[tx_index]); |
1708 | mlx4_en_deactivate_cq(priv, priv->tx_cq[tx_index]); | |
c27a02cd | 1709 | } |
cabdc8ee HHZ |
1710 | mlx4_en_destroy_drop_qp(priv); |
1711 | rss_err: | |
c27a02cd | 1712 | mlx4_en_release_rss_steer(priv); |
1679200f | 1713 | mac_err: |
16a10ffd | 1714 | mlx4_en_put_qp(priv); |
c27a02cd | 1715 | cq_err: |
9e311e77 | 1716 | while (rx_index--) { |
41d942d5 | 1717 | mlx4_en_deactivate_cq(priv, priv->rx_cq[rx_index]); |
f94813f3 | 1718 | mlx4_en_free_affinity_hint(priv, rx_index); |
9e311e77 | 1719 | } |
38aab07c | 1720 | for (i = 0; i < priv->rx_ring_num; i++) |
41d942d5 | 1721 | mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]); |
c27a02cd YP |
1722 | |
1723 | return err; /* need to close devices */ | |
1724 | } | |
1725 | ||
1726 | ||
3484aac1 | 1727 | void mlx4_en_stop_port(struct net_device *dev, int detach) |
c27a02cd YP |
1728 | { |
1729 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1730 | struct mlx4_en_dev *mdev = priv->mdev; | |
6d199937 | 1731 | struct mlx4_en_mc_list *mclist, *tmp; |
0d256c0e | 1732 | struct ethtool_flow_id *flow, *tmp_flow; |
c27a02cd | 1733 | int i; |
1679200f | 1734 | u8 mc_list[16] = {0}; |
c27a02cd YP |
1735 | |
1736 | if (!priv->port_up) { | |
453a6082 | 1737 | en_dbg(DRV, priv, "stop port called while port already down\n"); |
c27a02cd YP |
1738 | return; |
1739 | } | |
c27a02cd | 1740 | |
0cc5c8bf EE |
1741 | /* close port*/ |
1742 | mlx4_CLOSE_PORT(mdev->dev, priv->port); | |
1743 | ||
c27a02cd YP |
1744 | /* Synchronize with tx routine */ |
1745 | netif_tx_lock_bh(dev); | |
3484aac1 AV |
1746 | if (detach) |
1747 | netif_device_detach(dev); | |
3c05f5ef | 1748 | netif_tx_stop_all_queues(dev); |
c27a02cd YP |
1749 | netif_tx_unlock_bh(dev); |
1750 | ||
3484aac1 AV |
1751 | netif_tx_disable(dev); |
1752 | ||
7c287380 | 1753 | /* Set port as not active */ |
3c05f5ef | 1754 | priv->port_up = false; |
6de5f7f6 | 1755 | priv->counter_index = MLX4_SINK_COUNTER_INDEX(mdev->dev); |
c27a02cd | 1756 | |
db0e7cba AY |
1757 | /* Promsicuous mode */ |
1758 | if (mdev->dev->caps.steering_mode == | |
1759 | MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
1760 | priv->flags &= ~(MLX4_EN_FLAG_PROMISC | | |
1761 | MLX4_EN_FLAG_MC_PROMISC); | |
1762 | mlx4_flow_steer_promisc_remove(mdev->dev, | |
1763 | priv->port, | |
f9162539 | 1764 | MLX4_FS_ALL_DEFAULT); |
db0e7cba AY |
1765 | mlx4_flow_steer_promisc_remove(mdev->dev, |
1766 | priv->port, | |
f9162539 | 1767 | MLX4_FS_MC_DEFAULT); |
db0e7cba AY |
1768 | } else if (priv->flags & MLX4_EN_FLAG_PROMISC) { |
1769 | priv->flags &= ~MLX4_EN_FLAG_PROMISC; | |
1770 | ||
1771 | /* Disable promiscouos mode */ | |
1772 | mlx4_unicast_promisc_remove(mdev->dev, priv->base_qpn, | |
1773 | priv->port); | |
1774 | ||
1775 | /* Disable Multicast promisc */ | |
1776 | if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) { | |
1777 | mlx4_multicast_promisc_remove(mdev->dev, priv->base_qpn, | |
1778 | priv->port); | |
1779 | priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC; | |
1780 | } | |
1781 | } | |
1782 | ||
1679200f | 1783 | /* Detach All multicasts */ |
c7bf7169 | 1784 | eth_broadcast_addr(&mc_list[10]); |
0ff1fb65 | 1785 | mc_list[5] = priv->port; /* needed for B0 steering support */ |
1679200f | 1786 | mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp, mc_list, |
0ff1fb65 | 1787 | MLX4_PROT_ETH, priv->broadcast_id); |
6d199937 YP |
1788 | list_for_each_entry(mclist, &priv->curr_list, list) { |
1789 | memcpy(&mc_list[10], mclist->addr, ETH_ALEN); | |
1679200f YP |
1790 | mc_list[5] = priv->port; |
1791 | mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp, | |
0ff1fb65 | 1792 | mc_list, MLX4_PROT_ETH, mclist->reg_id); |
de123268 OG |
1793 | if (mclist->tunnel_reg_id) |
1794 | mlx4_flow_detach(mdev->dev, mclist->tunnel_reg_id); | |
1679200f YP |
1795 | } |
1796 | mlx4_en_clear_list(dev); | |
6d199937 YP |
1797 | list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) { |
1798 | list_del(&mclist->list); | |
1799 | kfree(mclist); | |
1800 | } | |
1801 | ||
1679200f YP |
1802 | /* Flush multicast filter */ |
1803 | mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, 1, MLX4_MCAST_CONFIG); | |
1804 | ||
6efb5fac HHZ |
1805 | /* Remove flow steering rules for the port*/ |
1806 | if (mdev->dev->caps.steering_mode == | |
1807 | MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
1808 | ASSERT_RTNL(); | |
1809 | list_for_each_entry_safe(flow, tmp_flow, | |
1810 | &priv->ethtool_list, list) { | |
1811 | mlx4_flow_detach(mdev->dev, flow->id); | |
1812 | list_del(&flow->list); | |
1813 | } | |
1814 | } | |
1815 | ||
cabdc8ee HHZ |
1816 | mlx4_en_destroy_drop_qp(priv); |
1817 | ||
c27a02cd YP |
1818 | /* Free TX Rings */ |
1819 | for (i = 0; i < priv->tx_ring_num; i++) { | |
41d942d5 EE |
1820 | mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[i]); |
1821 | mlx4_en_deactivate_cq(priv, priv->tx_cq[i]); | |
c27a02cd YP |
1822 | } |
1823 | msleep(10); | |
1824 | ||
1825 | for (i = 0; i < priv->tx_ring_num; i++) | |
41d942d5 | 1826 | mlx4_en_free_tx_buf(dev, priv->tx_ring[i]); |
c27a02cd | 1827 | |
ba4b87ae IS |
1828 | if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0) |
1829 | mlx4_en_delete_rss_steer_rules(priv); | |
1830 | ||
c27a02cd YP |
1831 | /* Free RSS qps */ |
1832 | mlx4_en_release_rss_steer(priv); | |
1833 | ||
ffe455ad | 1834 | /* Unregister Mac address for the port */ |
16a10ffd | 1835 | mlx4_en_put_qp(priv); |
5930e8d0 | 1836 | if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN)) |
955154fa | 1837 | mdev->mac_removed[priv->port] = 1; |
ffe455ad | 1838 | |
c27a02cd YP |
1839 | /* Free RX Rings */ |
1840 | for (i = 0; i < priv->rx_ring_num; i++) { | |
41d942d5 | 1841 | struct mlx4_en_cq *cq = priv->rx_cq[i]; |
9e77a2b8 | 1842 | |
f4a36751 | 1843 | napi_synchronize(&cq->napi); |
41d942d5 | 1844 | mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]); |
9e77a2b8 | 1845 | mlx4_en_deactivate_cq(priv, cq); |
9e311e77 YA |
1846 | |
1847 | mlx4_en_free_affinity_hint(priv, i); | |
c27a02cd YP |
1848 | } |
1849 | } | |
1850 | ||
1851 | static void mlx4_en_restart(struct work_struct *work) | |
1852 | { | |
1853 | struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, | |
1854 | watchdog_task); | |
1855 | struct mlx4_en_dev *mdev = priv->mdev; | |
1856 | struct net_device *dev = priv->dev; | |
1857 | ||
453a6082 | 1858 | en_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port); |
1e338db5 | 1859 | |
0c5c3252 | 1860 | rtnl_lock(); |
1e338db5 YP |
1861 | mutex_lock(&mdev->state_lock); |
1862 | if (priv->port_up) { | |
3484aac1 | 1863 | mlx4_en_stop_port(dev, 1); |
1e338db5 | 1864 | if (mlx4_en_start_port(dev)) |
453a6082 | 1865 | en_err(priv, "Failed restarting port %d\n", priv->port); |
1e338db5 YP |
1866 | } |
1867 | mutex_unlock(&mdev->state_lock); | |
0c5c3252 | 1868 | rtnl_unlock(); |
c27a02cd YP |
1869 | } |
1870 | ||
b477ba62 | 1871 | static void mlx4_en_clear_stats(struct net_device *dev) |
c27a02cd YP |
1872 | { |
1873 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1874 | struct mlx4_en_dev *mdev = priv->mdev; | |
1875 | int i; | |
c27a02cd | 1876 | |
c27a02cd | 1877 | if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1)) |
453a6082 | 1878 | en_dbg(HW, priv, "Failed dumping statistics\n"); |
c27a02cd | 1879 | |
c27a02cd | 1880 | memset(&priv->pstats, 0, sizeof(priv->pstats)); |
b477ba62 EE |
1881 | memset(&priv->pkstats, 0, sizeof(priv->pkstats)); |
1882 | memset(&priv->port_stats, 0, sizeof(priv->port_stats)); | |
0b131561 MB |
1883 | memset(&priv->rx_flowstats, 0, sizeof(priv->rx_flowstats)); |
1884 | memset(&priv->tx_flowstats, 0, sizeof(priv->tx_flowstats)); | |
1885 | memset(&priv->rx_priority_flowstats, 0, | |
1886 | sizeof(priv->rx_priority_flowstats)); | |
1887 | memset(&priv->tx_priority_flowstats, 0, | |
1888 | sizeof(priv->tx_priority_flowstats)); | |
b42de4d0 | 1889 | memset(&priv->pf_stats, 0, sizeof(priv->pf_stats)); |
c27a02cd YP |
1890 | |
1891 | for (i = 0; i < priv->tx_ring_num; i++) { | |
41d942d5 EE |
1892 | priv->tx_ring[i]->bytes = 0; |
1893 | priv->tx_ring[i]->packets = 0; | |
1894 | priv->tx_ring[i]->tx_csum = 0; | |
63a664b7 | 1895 | priv->tx_ring[i]->tx_dropped = 0; |
45acbac6 ED |
1896 | priv->tx_ring[i]->queue_stopped = 0; |
1897 | priv->tx_ring[i]->wake_queue = 0; | |
1898 | priv->tx_ring[i]->tso_packets = 0; | |
1899 | priv->tx_ring[i]->xmit_more = 0; | |
c27a02cd YP |
1900 | } |
1901 | for (i = 0; i < priv->rx_ring_num; i++) { | |
41d942d5 EE |
1902 | priv->rx_ring[i]->bytes = 0; |
1903 | priv->rx_ring[i]->packets = 0; | |
1904 | priv->rx_ring[i]->csum_ok = 0; | |
1905 | priv->rx_ring[i]->csum_none = 0; | |
f8c6455b | 1906 | priv->rx_ring[i]->csum_complete = 0; |
c27a02cd | 1907 | } |
b477ba62 EE |
1908 | } |
1909 | ||
1910 | static int mlx4_en_open(struct net_device *dev) | |
1911 | { | |
1912 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1913 | struct mlx4_en_dev *mdev = priv->mdev; | |
1914 | int err = 0; | |
1915 | ||
1916 | mutex_lock(&mdev->state_lock); | |
1917 | ||
1918 | if (!mdev->device_up) { | |
1919 | en_err(priv, "Cannot open - device down/disabled\n"); | |
1920 | err = -EBUSY; | |
1921 | goto out; | |
1922 | } | |
1923 | ||
1924 | /* Reset HW statistics and SW counters */ | |
1925 | mlx4_en_clear_stats(dev); | |
c27a02cd | 1926 | |
c27a02cd YP |
1927 | err = mlx4_en_start_port(dev); |
1928 | if (err) | |
453a6082 | 1929 | en_err(priv, "Failed starting port:%d\n", priv->port); |
c27a02cd YP |
1930 | |
1931 | out: | |
1932 | mutex_unlock(&mdev->state_lock); | |
1933 | return err; | |
1934 | } | |
1935 | ||
1936 | ||
1937 | static int mlx4_en_close(struct net_device *dev) | |
1938 | { | |
1939 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1940 | struct mlx4_en_dev *mdev = priv->mdev; | |
1941 | ||
453a6082 | 1942 | en_dbg(IFDOWN, priv, "Close port called\n"); |
c27a02cd YP |
1943 | |
1944 | mutex_lock(&mdev->state_lock); | |
1945 | ||
3484aac1 | 1946 | mlx4_en_stop_port(dev, 0); |
c27a02cd YP |
1947 | netif_carrier_off(dev); |
1948 | ||
1949 | mutex_unlock(&mdev->state_lock); | |
1950 | return 0; | |
1951 | } | |
1952 | ||
fe0af03c | 1953 | void mlx4_en_free_resources(struct mlx4_en_priv *priv) |
c27a02cd YP |
1954 | { |
1955 | int i; | |
1956 | ||
1eb8c695 | 1957 | #ifdef CONFIG_RFS_ACCEL |
1eb8c695 AV |
1958 | priv->dev->rx_cpu_rmap = NULL; |
1959 | #endif | |
1960 | ||
c27a02cd | 1961 | for (i = 0; i < priv->tx_ring_num; i++) { |
41d942d5 | 1962 | if (priv->tx_ring && priv->tx_ring[i]) |
c27a02cd | 1963 | mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]); |
41d942d5 | 1964 | if (priv->tx_cq && priv->tx_cq[i]) |
fe0af03c | 1965 | mlx4_en_destroy_cq(priv, &priv->tx_cq[i]); |
c27a02cd YP |
1966 | } |
1967 | ||
1968 | for (i = 0; i < priv->rx_ring_num; i++) { | |
41d942d5 | 1969 | if (priv->rx_ring[i]) |
68355f71 TLSC |
1970 | mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i], |
1971 | priv->prof->rx_ring_size, priv->stride); | |
41d942d5 | 1972 | if (priv->rx_cq[i]) |
fe0af03c | 1973 | mlx4_en_destroy_cq(priv, &priv->rx_cq[i]); |
c27a02cd | 1974 | } |
044ca2a5 | 1975 | |
c27a02cd YP |
1976 | } |
1977 | ||
18cc42a3 | 1978 | int mlx4_en_alloc_resources(struct mlx4_en_priv *priv) |
c27a02cd | 1979 | { |
c27a02cd YP |
1980 | struct mlx4_en_port_profile *prof = priv->prof; |
1981 | int i; | |
163561a4 | 1982 | int node; |
87a5c389 | 1983 | |
c27a02cd YP |
1984 | /* Create tx Rings */ |
1985 | for (i = 0; i < priv->tx_ring_num; i++) { | |
163561a4 | 1986 | node = cpu_to_node(i % num_online_cpus()); |
c27a02cd | 1987 | if (mlx4_en_create_cq(priv, &priv->tx_cq[i], |
163561a4 | 1988 | prof->tx_ring_size, i, TX, node)) |
c27a02cd YP |
1989 | goto err; |
1990 | ||
d03a68f8 | 1991 | if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[i], |
d03a68f8 IS |
1992 | prof->tx_ring_size, TXBB_SIZE, |
1993 | node, i)) | |
c27a02cd YP |
1994 | goto err; |
1995 | } | |
1996 | ||
1997 | /* Create rx Rings */ | |
1998 | for (i = 0; i < priv->rx_ring_num; i++) { | |
163561a4 | 1999 | node = cpu_to_node(i % num_online_cpus()); |
c27a02cd | 2000 | if (mlx4_en_create_cq(priv, &priv->rx_cq[i], |
163561a4 | 2001 | prof->rx_ring_size, i, RX, node)) |
c27a02cd YP |
2002 | goto err; |
2003 | ||
2004 | if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i], | |
163561a4 EE |
2005 | prof->rx_ring_size, priv->stride, |
2006 | node)) | |
c27a02cd YP |
2007 | goto err; |
2008 | } | |
2009 | ||
1eb8c695 | 2010 | #ifdef CONFIG_RFS_ACCEL |
c66fa19c | 2011 | priv->dev->rx_cpu_rmap = mlx4_get_cpu_rmap(priv->mdev->dev, priv->port); |
1eb8c695 AV |
2012 | #endif |
2013 | ||
c27a02cd YP |
2014 | return 0; |
2015 | ||
2016 | err: | |
453a6082 | 2017 | en_err(priv, "Failed to allocate NIC resources\n"); |
41d942d5 EE |
2018 | for (i = 0; i < priv->rx_ring_num; i++) { |
2019 | if (priv->rx_ring[i]) | |
2020 | mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i], | |
2021 | prof->rx_ring_size, | |
2022 | priv->stride); | |
2023 | if (priv->rx_cq[i]) | |
2024 | mlx4_en_destroy_cq(priv, &priv->rx_cq[i]); | |
2025 | } | |
2026 | for (i = 0; i < priv->tx_ring_num; i++) { | |
2027 | if (priv->tx_ring[i]) | |
2028 | mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]); | |
2029 | if (priv->tx_cq[i]) | |
2030 | mlx4_en_destroy_cq(priv, &priv->tx_cq[i]); | |
2031 | } | |
c27a02cd YP |
2032 | return -ENOMEM; |
2033 | } | |
2034 | ||
2035 | ||
2036 | void mlx4_en_destroy_netdev(struct net_device *dev) | |
2037 | { | |
2038 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
2039 | struct mlx4_en_dev *mdev = priv->mdev; | |
2040 | ||
453a6082 | 2041 | en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port); |
c27a02cd YP |
2042 | |
2043 | /* Unregister device - this will close the port if it was up */ | |
09d4d087 JP |
2044 | if (priv->registered) { |
2045 | devlink_port_type_clear(mlx4_get_devlink_port(mdev->dev, | |
2046 | priv->port)); | |
c27a02cd | 2047 | unregister_netdev(dev); |
09d4d087 | 2048 | } |
c27a02cd YP |
2049 | |
2050 | if (priv->allocated) | |
2051 | mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE); | |
2052 | ||
2053 | cancel_delayed_work(&priv->stats_task); | |
b6c39bfc | 2054 | cancel_delayed_work(&priv->service_task); |
c27a02cd YP |
2055 | /* flush any pending task for this netdev */ |
2056 | flush_workqueue(mdev->workqueue); | |
2057 | ||
90683061 EE |
2058 | if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) |
2059 | mlx4_en_remove_timestamp(mdev); | |
2060 | ||
c27a02cd YP |
2061 | /* Detach the netdev so tasks would not attempt to access it */ |
2062 | mutex_lock(&mdev->state_lock); | |
2063 | mdev->pndev[priv->port] = NULL; | |
5da03547 | 2064 | mdev->upper[priv->port] = NULL; |
c27a02cd YP |
2065 | mutex_unlock(&mdev->state_lock); |
2066 | ||
fe0af03c | 2067 | mlx4_en_free_resources(priv); |
564c274c | 2068 | |
bc6a4744 AV |
2069 | kfree(priv->tx_ring); |
2070 | kfree(priv->tx_cq); | |
2071 | ||
c27a02cd YP |
2072 | free_netdev(dev); |
2073 | } | |
2074 | ||
2075 | static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu) | |
2076 | { | |
2077 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
2078 | struct mlx4_en_dev *mdev = priv->mdev; | |
2079 | int err = 0; | |
2080 | ||
453a6082 | 2081 | en_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n", |
c27a02cd YP |
2082 | dev->mtu, new_mtu); |
2083 | ||
2084 | if ((new_mtu < MLX4_EN_MIN_MTU) || (new_mtu > priv->max_mtu)) { | |
453a6082 | 2085 | en_err(priv, "Bad MTU size:%d.\n", new_mtu); |
c27a02cd YP |
2086 | return -EPERM; |
2087 | } | |
2088 | dev->mtu = new_mtu; | |
2089 | ||
2090 | if (netif_running(dev)) { | |
2091 | mutex_lock(&mdev->state_lock); | |
2092 | if (!mdev->device_up) { | |
2093 | /* NIC is probably restarting - let watchdog task reset | |
2094 | * the port */ | |
453a6082 | 2095 | en_dbg(DRV, priv, "Change MTU called with card down!?\n"); |
c27a02cd | 2096 | } else { |
3484aac1 | 2097 | mlx4_en_stop_port(dev, 1); |
c27a02cd YP |
2098 | err = mlx4_en_start_port(dev); |
2099 | if (err) { | |
453a6082 | 2100 | en_err(priv, "Failed restarting port:%d\n", |
c27a02cd YP |
2101 | priv->port); |
2102 | queue_work(mdev->workqueue, &priv->watchdog_task); | |
2103 | } | |
2104 | } | |
2105 | mutex_unlock(&mdev->state_lock); | |
2106 | } | |
2107 | return 0; | |
2108 | } | |
2109 | ||
100dbda8 | 2110 | static int mlx4_en_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) |
ec693d47 AV |
2111 | { |
2112 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
2113 | struct mlx4_en_dev *mdev = priv->mdev; | |
2114 | struct hwtstamp_config config; | |
2115 | ||
2116 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
2117 | return -EFAULT; | |
2118 | ||
2119 | /* reserved for future extensions */ | |
2120 | if (config.flags) | |
2121 | return -EINVAL; | |
2122 | ||
2123 | /* device doesn't support time stamping */ | |
2124 | if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)) | |
2125 | return -EINVAL; | |
2126 | ||
2127 | /* TX HW timestamp */ | |
2128 | switch (config.tx_type) { | |
2129 | case HWTSTAMP_TX_OFF: | |
2130 | case HWTSTAMP_TX_ON: | |
2131 | break; | |
2132 | default: | |
2133 | return -ERANGE; | |
2134 | } | |
2135 | ||
2136 | /* RX HW timestamp */ | |
2137 | switch (config.rx_filter) { | |
2138 | case HWTSTAMP_FILTER_NONE: | |
2139 | break; | |
2140 | case HWTSTAMP_FILTER_ALL: | |
2141 | case HWTSTAMP_FILTER_SOME: | |
2142 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
2143 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
2144 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
2145 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
2146 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
2147 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
2148 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
2149 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
2150 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
2151 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
2152 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
2153 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
2154 | config.rx_filter = HWTSTAMP_FILTER_ALL; | |
2155 | break; | |
2156 | default: | |
2157 | return -ERANGE; | |
2158 | } | |
2159 | ||
7787fa66 | 2160 | if (mlx4_en_reset_config(dev, config, dev->features)) { |
ec693d47 AV |
2161 | config.tx_type = HWTSTAMP_TX_OFF; |
2162 | config.rx_filter = HWTSTAMP_FILTER_NONE; | |
2163 | } | |
2164 | ||
2165 | return copy_to_user(ifr->ifr_data, &config, | |
2166 | sizeof(config)) ? -EFAULT : 0; | |
2167 | } | |
2168 | ||
100dbda8 BH |
2169 | static int mlx4_en_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) |
2170 | { | |
2171 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
2172 | ||
2173 | return copy_to_user(ifr->ifr_data, &priv->hwtstamp_config, | |
2174 | sizeof(priv->hwtstamp_config)) ? -EFAULT : 0; | |
2175 | } | |
2176 | ||
ec693d47 AV |
2177 | static int mlx4_en_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
2178 | { | |
2179 | switch (cmd) { | |
2180 | case SIOCSHWTSTAMP: | |
100dbda8 BH |
2181 | return mlx4_en_hwtstamp_set(dev, ifr); |
2182 | case SIOCGHWTSTAMP: | |
2183 | return mlx4_en_hwtstamp_get(dev, ifr); | |
ec693d47 AV |
2184 | default: |
2185 | return -EOPNOTSUPP; | |
2186 | } | |
2187 | } | |
2188 | ||
e38af4fa HHZ |
2189 | static netdev_features_t mlx4_en_fix_features(struct net_device *netdev, |
2190 | netdev_features_t features) | |
2191 | { | |
2192 | struct mlx4_en_priv *en_priv = netdev_priv(netdev); | |
2193 | struct mlx4_en_dev *mdev = en_priv->mdev; | |
2194 | ||
2195 | /* Since there is no support for separate RX C-TAG/S-TAG vlan accel | |
2196 | * enable/disable make sure S-TAG flag is always in same state as | |
2197 | * C-TAG. | |
2198 | */ | |
2199 | if (features & NETIF_F_HW_VLAN_CTAG_RX && | |
2200 | !(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) | |
2201 | features |= NETIF_F_HW_VLAN_STAG_RX; | |
2202 | else | |
2203 | features &= ~NETIF_F_HW_VLAN_STAG_RX; | |
2204 | ||
2205 | return features; | |
2206 | } | |
2207 | ||
60d6fe99 AV |
2208 | static int mlx4_en_set_features(struct net_device *netdev, |
2209 | netdev_features_t features) | |
2210 | { | |
2211 | struct mlx4_en_priv *priv = netdev_priv(netdev); | |
f0df3503 | 2212 | bool reset = false; |
537f6f95 SM |
2213 | int ret = 0; |
2214 | ||
f0df3503 MM |
2215 | if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXFCS)) { |
2216 | en_info(priv, "Turn %s RX-FCS\n", | |
2217 | (features & NETIF_F_RXFCS) ? "ON" : "OFF"); | |
2218 | reset = true; | |
2219 | } | |
2220 | ||
78500b8c MM |
2221 | if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXALL)) { |
2222 | u8 ignore_fcs_value = (features & NETIF_F_RXALL) ? 1 : 0; | |
2223 | ||
2224 | en_info(priv, "Turn %s RX-ALL\n", | |
2225 | ignore_fcs_value ? "ON" : "OFF"); | |
2226 | ret = mlx4_SET_PORT_fcs_check(priv->mdev->dev, | |
2227 | priv->port, ignore_fcs_value); | |
2228 | if (ret) | |
2229 | return ret; | |
2230 | } | |
2231 | ||
537f6f95 SM |
2232 | if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_RX)) { |
2233 | en_info(priv, "Turn %s RX vlan strip offload\n", | |
2234 | (features & NETIF_F_HW_VLAN_CTAG_RX) ? "ON" : "OFF"); | |
f0df3503 | 2235 | reset = true; |
537f6f95 | 2236 | } |
60d6fe99 | 2237 | |
cfb53f36 IS |
2238 | if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_TX)) |
2239 | en_info(priv, "Turn %s TX vlan strip offload\n", | |
2240 | (features & NETIF_F_HW_VLAN_CTAG_TX) ? "ON" : "OFF"); | |
2241 | ||
e38af4fa HHZ |
2242 | if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_STAG_TX)) |
2243 | en_info(priv, "Turn %s TX S-VLAN strip offload\n", | |
2244 | (features & NETIF_F_HW_VLAN_STAG_TX) ? "ON" : "OFF"); | |
2245 | ||
241a08c3 IS |
2246 | if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_LOOPBACK)) { |
2247 | en_info(priv, "Turn %s loopback\n", | |
2248 | (features & NETIF_F_LOOPBACK) ? "ON" : "OFF"); | |
2249 | mlx4_en_update_loopback_state(netdev, features); | |
2250 | } | |
79aeaccd | 2251 | |
f0df3503 MM |
2252 | if (reset) { |
2253 | ret = mlx4_en_reset_config(netdev, priv->hwtstamp_config, | |
2254 | features); | |
2255 | if (ret) | |
2256 | return ret; | |
2257 | } | |
60d6fe99 | 2258 | |
f0df3503 | 2259 | return 0; |
60d6fe99 AV |
2260 | } |
2261 | ||
8f7ba3ca RE |
2262 | static int mlx4_en_set_vf_mac(struct net_device *dev, int queue, u8 *mac) |
2263 | { | |
2264 | struct mlx4_en_priv *en_priv = netdev_priv(dev); | |
2265 | struct mlx4_en_dev *mdev = en_priv->mdev; | |
9813337a | 2266 | u64 mac_u64 = mlx4_mac_to_u64(mac); |
8f7ba3ca | 2267 | |
6e522422 | 2268 | if (is_multicast_ether_addr(mac)) |
8f7ba3ca RE |
2269 | return -EINVAL; |
2270 | ||
2271 | return mlx4_set_vf_mac(mdev->dev, en_priv->port, queue, mac_u64); | |
2272 | } | |
2273 | ||
3f7fb021 RE |
2274 | static int mlx4_en_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos) |
2275 | { | |
2276 | struct mlx4_en_priv *en_priv = netdev_priv(dev); | |
2277 | struct mlx4_en_dev *mdev = en_priv->mdev; | |
2278 | ||
2279 | return mlx4_set_vf_vlan(mdev->dev, en_priv->port, vf, vlan, qos); | |
2280 | } | |
2281 | ||
cda373f4 IS |
2282 | static int mlx4_en_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, |
2283 | int max_tx_rate) | |
2284 | { | |
2285 | struct mlx4_en_priv *en_priv = netdev_priv(dev); | |
2286 | struct mlx4_en_dev *mdev = en_priv->mdev; | |
2287 | ||
2288 | return mlx4_set_vf_rate(mdev->dev, en_priv->port, vf, min_tx_rate, | |
2289 | max_tx_rate); | |
2290 | } | |
2291 | ||
e6b6a231 RE |
2292 | static int mlx4_en_set_vf_spoofchk(struct net_device *dev, int vf, bool setting) |
2293 | { | |
2294 | struct mlx4_en_priv *en_priv = netdev_priv(dev); | |
2295 | struct mlx4_en_dev *mdev = en_priv->mdev; | |
2296 | ||
2297 | return mlx4_set_vf_spoofchk(mdev->dev, en_priv->port, vf, setting); | |
2298 | } | |
2299 | ||
2cccb9e4 RE |
2300 | static int mlx4_en_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivf) |
2301 | { | |
2302 | struct mlx4_en_priv *en_priv = netdev_priv(dev); | |
2303 | struct mlx4_en_dev *mdev = en_priv->mdev; | |
2304 | ||
2305 | return mlx4_get_vf_config(mdev->dev, en_priv->port, vf, ivf); | |
2306 | } | |
8f7ba3ca | 2307 | |
948e306d RE |
2308 | static int mlx4_en_set_vf_link_state(struct net_device *dev, int vf, int link_state) |
2309 | { | |
2310 | struct mlx4_en_priv *en_priv = netdev_priv(dev); | |
2311 | struct mlx4_en_dev *mdev = en_priv->mdev; | |
2312 | ||
2313 | return mlx4_set_vf_link_state(mdev->dev, en_priv->port, vf, link_state); | |
2314 | } | |
84c86403 | 2315 | |
62a89055 EBE |
2316 | static int mlx4_en_get_vf_stats(struct net_device *dev, int vf, |
2317 | struct ifla_vf_stats *vf_stats) | |
2318 | { | |
2319 | struct mlx4_en_priv *en_priv = netdev_priv(dev); | |
2320 | struct mlx4_en_dev *mdev = en_priv->mdev; | |
2321 | ||
2322 | return mlx4_get_vf_stats(mdev->dev, en_priv->port, vf, vf_stats); | |
2323 | } | |
2324 | ||
84c86403 HHZ |
2325 | #define PORT_ID_BYTE_LEN 8 |
2326 | static int mlx4_en_get_phys_port_id(struct net_device *dev, | |
02637fce | 2327 | struct netdev_phys_item_id *ppid) |
84c86403 HHZ |
2328 | { |
2329 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
2330 | struct mlx4_dev *mdev = priv->mdev->dev; | |
2331 | int i; | |
2332 | u64 phys_port_id = mdev->caps.phys_port_id[priv->port]; | |
2333 | ||
2334 | if (!phys_port_id) | |
2335 | return -EOPNOTSUPP; | |
2336 | ||
2337 | ppid->id_len = sizeof(phys_port_id); | |
2338 | for (i = PORT_ID_BYTE_LEN - 1; i >= 0; --i) { | |
2339 | ppid->id[i] = phys_port_id & 0xff; | |
2340 | phys_port_id >>= 8; | |
2341 | } | |
2342 | return 0; | |
2343 | } | |
2344 | ||
a66132f3 | 2345 | #ifdef CONFIG_MLX4_EN_VXLAN |
1b136de1 OG |
2346 | static void mlx4_en_add_vxlan_offloads(struct work_struct *work) |
2347 | { | |
2348 | int ret; | |
2349 | struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, | |
2350 | vxlan_add_task); | |
2351 | ||
2352 | ret = mlx4_config_vxlan_port(priv->mdev->dev, priv->vxlan_port); | |
2353 | if (ret) | |
2354 | goto out; | |
2355 | ||
2356 | ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port, | |
2357 | VXLAN_STEER_BY_OUTER_MAC, 1); | |
2358 | out: | |
f4a1edd5 | 2359 | if (ret) { |
1b136de1 | 2360 | en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret); |
f4a1edd5 OG |
2361 | return; |
2362 | } | |
2363 | ||
2364 | /* set offloads */ | |
09067122 AD |
2365 | priv->dev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
2366 | NETIF_F_RXCSUM | | |
2367 | NETIF_F_TSO | NETIF_F_TSO6 | | |
2368 | NETIF_F_GSO_UDP_TUNNEL | | |
3c9346b2 AD |
2369 | NETIF_F_GSO_UDP_TUNNEL_CSUM | |
2370 | NETIF_F_GSO_PARTIAL; | |
1b136de1 OG |
2371 | } |
2372 | ||
2373 | static void mlx4_en_del_vxlan_offloads(struct work_struct *work) | |
2374 | { | |
2375 | int ret; | |
2376 | struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, | |
2377 | vxlan_del_task); | |
f4a1edd5 | 2378 | /* unset offloads */ |
09067122 AD |
2379 | priv->dev->hw_enc_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
2380 | NETIF_F_RXCSUM | | |
2381 | NETIF_F_TSO | NETIF_F_TSO6 | | |
2382 | NETIF_F_GSO_UDP_TUNNEL | | |
3c9346b2 AD |
2383 | NETIF_F_GSO_UDP_TUNNEL_CSUM | |
2384 | NETIF_F_GSO_PARTIAL); | |
1b136de1 OG |
2385 | |
2386 | ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port, | |
2387 | VXLAN_STEER_BY_OUTER_MAC, 0); | |
2388 | if (ret) | |
2389 | en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret); | |
2390 | ||
2391 | priv->vxlan_port = 0; | |
2392 | } | |
2393 | ||
2394 | static void mlx4_en_add_vxlan_port(struct net_device *dev, | |
2395 | sa_family_t sa_family, __be16 port) | |
2396 | { | |
2397 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
2398 | __be16 current_port; | |
2399 | ||
e326f2f1 | 2400 | if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) |
1b136de1 OG |
2401 | return; |
2402 | ||
2403 | if (sa_family == AF_INET6) | |
2404 | return; | |
2405 | ||
2406 | current_port = priv->vxlan_port; | |
2407 | if (current_port && current_port != port) { | |
2408 | en_warn(priv, "vxlan port %d configured, can't add port %d\n", | |
2409 | ntohs(current_port), ntohs(port)); | |
2410 | return; | |
2411 | } | |
2412 | ||
2413 | priv->vxlan_port = port; | |
2414 | queue_work(priv->mdev->workqueue, &priv->vxlan_add_task); | |
2415 | } | |
2416 | ||
2417 | static void mlx4_en_del_vxlan_port(struct net_device *dev, | |
2418 | sa_family_t sa_family, __be16 port) | |
2419 | { | |
2420 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
2421 | __be16 current_port; | |
2422 | ||
2423 | if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) | |
2424 | return; | |
2425 | ||
2426 | if (sa_family == AF_INET6) | |
2427 | return; | |
2428 | ||
2429 | current_port = priv->vxlan_port; | |
2430 | if (current_port != port) { | |
2431 | en_dbg(DRV, priv, "vxlan port %d isn't configured, ignoring\n", ntohs(port)); | |
2432 | return; | |
2433 | } | |
2434 | ||
2435 | queue_work(priv->mdev->workqueue, &priv->vxlan_del_task); | |
2436 | } | |
956bdab2 | 2437 | |
5f35227e JG |
2438 | static netdev_features_t mlx4_en_features_check(struct sk_buff *skb, |
2439 | struct net_device *dev, | |
2440 | netdev_features_t features) | |
956bdab2 | 2441 | { |
8cb65d00 | 2442 | features = vlan_features_check(skb, features); |
09067122 AD |
2443 | features = vxlan_features_check(skb, features); |
2444 | ||
2445 | /* The ConnectX-3 doesn't support outer IPv6 checksums but it does | |
2446 | * support inner IPv6 checksums and segmentation so we need to | |
2447 | * strip that feature if this is an IPv6 encapsulated frame. | |
2448 | */ | |
2449 | if (skb->encapsulation && | |
a547224d AD |
2450 | (skb->ip_summed == CHECKSUM_PARTIAL)) { |
2451 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
2452 | ||
2453 | if (!priv->vxlan_port || | |
2454 | (ip_hdr(skb)->version != 4) || | |
2455 | (udp_hdr(skb)->dest != priv->vxlan_port)) | |
2456 | features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
2457 | } | |
09067122 AD |
2458 | |
2459 | return features; | |
956bdab2 | 2460 | } |
a66132f3 | 2461 | #endif |
1b136de1 | 2462 | |
de1cf8a7 | 2463 | static int mlx4_en_set_tx_maxrate(struct net_device *dev, int queue_index, u32 maxrate) |
c10e4fc6 OG |
2464 | { |
2465 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
2466 | struct mlx4_en_tx_ring *tx_ring = priv->tx_ring[queue_index]; | |
2467 | struct mlx4_update_qp_params params; | |
2468 | int err; | |
2469 | ||
2470 | if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT)) | |
2471 | return -EOPNOTSUPP; | |
2472 | ||
2473 | /* rate provided to us in Mbs, check if it fits into 12 bits, if not use Gbs */ | |
2474 | if (maxrate >> 12) { | |
2475 | params.rate_unit = MLX4_QP_RATE_LIMIT_GBS; | |
2476 | params.rate_val = maxrate / 1000; | |
2477 | } else if (maxrate) { | |
2478 | params.rate_unit = MLX4_QP_RATE_LIMIT_MBS; | |
2479 | params.rate_val = maxrate; | |
2480 | } else { /* zero serves to revoke the QP rate-limitation */ | |
2481 | params.rate_unit = 0; | |
2482 | params.rate_val = 0; | |
2483 | } | |
2484 | ||
2485 | err = mlx4_update_qp(priv->mdev->dev, tx_ring->qpn, MLX4_UPDATE_QP_RATE_LIMIT, | |
2486 | ¶ms); | |
2487 | return err; | |
2488 | } | |
2489 | ||
3addc568 SH |
2490 | static const struct net_device_ops mlx4_netdev_ops = { |
2491 | .ndo_open = mlx4_en_open, | |
2492 | .ndo_stop = mlx4_en_close, | |
2493 | .ndo_start_xmit = mlx4_en_xmit, | |
f813cad8 | 2494 | .ndo_select_queue = mlx4_en_select_queue, |
9ed17db1 | 2495 | .ndo_get_stats64 = mlx4_en_get_stats64, |
0eb74fdd | 2496 | .ndo_set_rx_mode = mlx4_en_set_rx_mode, |
3addc568 | 2497 | .ndo_set_mac_address = mlx4_en_set_mac, |
52255bbe | 2498 | .ndo_validate_addr = eth_validate_addr, |
3addc568 | 2499 | .ndo_change_mtu = mlx4_en_change_mtu, |
ec693d47 | 2500 | .ndo_do_ioctl = mlx4_en_ioctl, |
3addc568 | 2501 | .ndo_tx_timeout = mlx4_en_tx_timeout, |
3addc568 SH |
2502 | .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid, |
2503 | .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid, | |
2504 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2505 | .ndo_poll_controller = mlx4_en_netpoll, | |
2506 | #endif | |
60d6fe99 | 2507 | .ndo_set_features = mlx4_en_set_features, |
e38af4fa | 2508 | .ndo_fix_features = mlx4_en_fix_features, |
e4c6734e | 2509 | .ndo_setup_tc = __mlx4_en_setup_tc, |
1eb8c695 AV |
2510 | #ifdef CONFIG_RFS_ACCEL |
2511 | .ndo_rx_flow_steer = mlx4_en_filter_rfs, | |
9e77a2b8 | 2512 | #endif |
84c86403 | 2513 | .ndo_get_phys_port_id = mlx4_en_get_phys_port_id, |
a66132f3 | 2514 | #ifdef CONFIG_MLX4_EN_VXLAN |
1b136de1 OG |
2515 | .ndo_add_vxlan_port = mlx4_en_add_vxlan_port, |
2516 | .ndo_del_vxlan_port = mlx4_en_del_vxlan_port, | |
5f35227e | 2517 | .ndo_features_check = mlx4_en_features_check, |
a66132f3 | 2518 | #endif |
c10e4fc6 | 2519 | .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate, |
3addc568 SH |
2520 | }; |
2521 | ||
8f7ba3ca RE |
2522 | static const struct net_device_ops mlx4_netdev_ops_master = { |
2523 | .ndo_open = mlx4_en_open, | |
2524 | .ndo_stop = mlx4_en_close, | |
2525 | .ndo_start_xmit = mlx4_en_xmit, | |
2526 | .ndo_select_queue = mlx4_en_select_queue, | |
9ed17db1 | 2527 | .ndo_get_stats64 = mlx4_en_get_stats64, |
8f7ba3ca RE |
2528 | .ndo_set_rx_mode = mlx4_en_set_rx_mode, |
2529 | .ndo_set_mac_address = mlx4_en_set_mac, | |
2530 | .ndo_validate_addr = eth_validate_addr, | |
2531 | .ndo_change_mtu = mlx4_en_change_mtu, | |
2532 | .ndo_tx_timeout = mlx4_en_tx_timeout, | |
2533 | .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid, | |
2534 | .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid, | |
2535 | .ndo_set_vf_mac = mlx4_en_set_vf_mac, | |
3f7fb021 | 2536 | .ndo_set_vf_vlan = mlx4_en_set_vf_vlan, |
cda373f4 | 2537 | .ndo_set_vf_rate = mlx4_en_set_vf_rate, |
e6b6a231 | 2538 | .ndo_set_vf_spoofchk = mlx4_en_set_vf_spoofchk, |
948e306d | 2539 | .ndo_set_vf_link_state = mlx4_en_set_vf_link_state, |
62a89055 | 2540 | .ndo_get_vf_stats = mlx4_en_get_vf_stats, |
2cccb9e4 | 2541 | .ndo_get_vf_config = mlx4_en_get_vf_config, |
8f7ba3ca RE |
2542 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2543 | .ndo_poll_controller = mlx4_en_netpoll, | |
2544 | #endif | |
2545 | .ndo_set_features = mlx4_en_set_features, | |
e38af4fa | 2546 | .ndo_fix_features = mlx4_en_fix_features, |
e4c6734e | 2547 | .ndo_setup_tc = __mlx4_en_setup_tc, |
8f7ba3ca RE |
2548 | #ifdef CONFIG_RFS_ACCEL |
2549 | .ndo_rx_flow_steer = mlx4_en_filter_rfs, | |
2550 | #endif | |
84c86403 | 2551 | .ndo_get_phys_port_id = mlx4_en_get_phys_port_id, |
9737c6ab OG |
2552 | #ifdef CONFIG_MLX4_EN_VXLAN |
2553 | .ndo_add_vxlan_port = mlx4_en_add_vxlan_port, | |
2554 | .ndo_del_vxlan_port = mlx4_en_del_vxlan_port, | |
5f35227e | 2555 | .ndo_features_check = mlx4_en_features_check, |
9737c6ab | 2556 | #endif |
c10e4fc6 | 2557 | .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate, |
8f7ba3ca RE |
2558 | }; |
2559 | ||
5da03547 MS |
2560 | struct mlx4_en_bond { |
2561 | struct work_struct work; | |
2562 | struct mlx4_en_priv *priv; | |
2563 | int is_bonded; | |
2564 | struct mlx4_port_map port_map; | |
2565 | }; | |
2566 | ||
2567 | static void mlx4_en_bond_work(struct work_struct *work) | |
2568 | { | |
2569 | struct mlx4_en_bond *bond = container_of(work, | |
2570 | struct mlx4_en_bond, | |
2571 | work); | |
2572 | int err = 0; | |
2573 | struct mlx4_dev *dev = bond->priv->mdev->dev; | |
2574 | ||
2575 | if (bond->is_bonded) { | |
2576 | if (!mlx4_is_bonded(dev)) { | |
2577 | err = mlx4_bond(dev); | |
2578 | if (err) | |
2579 | en_err(bond->priv, "Fail to bond device\n"); | |
2580 | } | |
2581 | if (!err) { | |
2582 | err = mlx4_port_map_set(dev, &bond->port_map); | |
2583 | if (err) | |
2584 | en_err(bond->priv, "Fail to set port map [%d][%d]: %d\n", | |
2585 | bond->port_map.port1, | |
2586 | bond->port_map.port2, | |
2587 | err); | |
2588 | } | |
2589 | } else if (mlx4_is_bonded(dev)) { | |
2590 | err = mlx4_unbond(dev); | |
2591 | if (err) | |
2592 | en_err(bond->priv, "Fail to unbond device\n"); | |
2593 | } | |
2594 | dev_put(bond->priv->dev); | |
2595 | kfree(bond); | |
2596 | } | |
2597 | ||
2598 | static int mlx4_en_queue_bond_work(struct mlx4_en_priv *priv, int is_bonded, | |
2599 | u8 v2p_p1, u8 v2p_p2) | |
2600 | { | |
2601 | struct mlx4_en_bond *bond = NULL; | |
2602 | ||
2603 | bond = kzalloc(sizeof(*bond), GFP_ATOMIC); | |
2604 | if (!bond) | |
2605 | return -ENOMEM; | |
2606 | ||
2607 | INIT_WORK(&bond->work, mlx4_en_bond_work); | |
2608 | bond->priv = priv; | |
2609 | bond->is_bonded = is_bonded; | |
2610 | bond->port_map.port1 = v2p_p1; | |
2611 | bond->port_map.port2 = v2p_p2; | |
2612 | dev_hold(priv->dev); | |
2613 | queue_work(priv->mdev->workqueue, &bond->work); | |
2614 | return 0; | |
2615 | } | |
2616 | ||
2617 | int mlx4_en_netdev_event(struct notifier_block *this, | |
2618 | unsigned long event, void *ptr) | |
2619 | { | |
2620 | struct net_device *ndev = netdev_notifier_info_to_dev(ptr); | |
2621 | u8 port = 0; | |
2622 | struct mlx4_en_dev *mdev; | |
2623 | struct mlx4_dev *dev; | |
2624 | int i, num_eth_ports = 0; | |
2625 | bool do_bond = true; | |
2626 | struct mlx4_en_priv *priv; | |
2627 | u8 v2p_port1 = 0; | |
2628 | u8 v2p_port2 = 0; | |
2629 | ||
2630 | if (!net_eq(dev_net(ndev), &init_net)) | |
2631 | return NOTIFY_DONE; | |
2632 | ||
2633 | mdev = container_of(this, struct mlx4_en_dev, nb); | |
2634 | dev = mdev->dev; | |
2635 | ||
2636 | /* Go into this mode only when two network devices set on two ports | |
2637 | * of the same mlx4 device are slaves of the same bonding master | |
2638 | */ | |
2639 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { | |
2640 | ++num_eth_ports; | |
2641 | if (!port && (mdev->pndev[i] == ndev)) | |
2642 | port = i; | |
2643 | mdev->upper[i] = mdev->pndev[i] ? | |
2644 | netdev_master_upper_dev_get(mdev->pndev[i]) : NULL; | |
2645 | /* condition not met: network device is a slave */ | |
2646 | if (!mdev->upper[i]) | |
2647 | do_bond = false; | |
2648 | if (num_eth_ports < 2) | |
2649 | continue; | |
2650 | /* condition not met: same master */ | |
2651 | if (mdev->upper[i] != mdev->upper[i-1]) | |
2652 | do_bond = false; | |
2653 | } | |
2654 | /* condition not met: 2 salves */ | |
2655 | do_bond = (num_eth_ports == 2) ? do_bond : false; | |
2656 | ||
2657 | /* handle only events that come with enough info */ | |
2658 | if ((do_bond && (event != NETDEV_BONDING_INFO)) || !port) | |
2659 | return NOTIFY_DONE; | |
2660 | ||
2661 | priv = netdev_priv(ndev); | |
2662 | if (do_bond) { | |
2663 | struct netdev_notifier_bonding_info *notifier_info = ptr; | |
2664 | struct netdev_bonding_info *bonding_info = | |
2665 | ¬ifier_info->bonding_info; | |
2666 | ||
2667 | /* required mode 1, 2 or 4 */ | |
2668 | if ((bonding_info->master.bond_mode != BOND_MODE_ACTIVEBACKUP) && | |
2669 | (bonding_info->master.bond_mode != BOND_MODE_XOR) && | |
2670 | (bonding_info->master.bond_mode != BOND_MODE_8023AD)) | |
2671 | do_bond = false; | |
2672 | ||
2673 | /* require exactly 2 slaves */ | |
2674 | if (bonding_info->master.num_slaves != 2) | |
2675 | do_bond = false; | |
2676 | ||
2677 | /* calc v2p */ | |
2678 | if (do_bond) { | |
2679 | if (bonding_info->master.bond_mode == | |
2680 | BOND_MODE_ACTIVEBACKUP) { | |
2681 | /* in active-backup mode virtual ports are | |
2682 | * mapped to the physical port of the active | |
2683 | * slave */ | |
2684 | if (bonding_info->slave.state == | |
2685 | BOND_STATE_BACKUP) { | |
2686 | if (port == 1) { | |
2687 | v2p_port1 = 2; | |
2688 | v2p_port2 = 2; | |
2689 | } else { | |
2690 | v2p_port1 = 1; | |
2691 | v2p_port2 = 1; | |
2692 | } | |
2693 | } else { /* BOND_STATE_ACTIVE */ | |
2694 | if (port == 1) { | |
2695 | v2p_port1 = 1; | |
2696 | v2p_port2 = 1; | |
2697 | } else { | |
2698 | v2p_port1 = 2; | |
2699 | v2p_port2 = 2; | |
2700 | } | |
2701 | } | |
2702 | } else { /* Active-Active */ | |
2703 | /* in active-active mode a virtual port is | |
2704 | * mapped to the native physical port if and only | |
2705 | * if the physical port is up */ | |
2706 | __s8 link = bonding_info->slave.link; | |
2707 | ||
2708 | if (port == 1) | |
2709 | v2p_port2 = 2; | |
2710 | else | |
2711 | v2p_port1 = 1; | |
2712 | if ((link == BOND_LINK_UP) || | |
2713 | (link == BOND_LINK_FAIL)) { | |
2714 | if (port == 1) | |
2715 | v2p_port1 = 1; | |
2716 | else | |
2717 | v2p_port2 = 2; | |
2718 | } else { /* BOND_LINK_DOWN || BOND_LINK_BACK */ | |
2719 | if (port == 1) | |
2720 | v2p_port1 = 2; | |
2721 | else | |
2722 | v2p_port2 = 1; | |
2723 | } | |
2724 | } | |
2725 | } | |
2726 | } | |
2727 | ||
2728 | mlx4_en_queue_bond_work(priv, do_bond, | |
2729 | v2p_port1, v2p_port2); | |
2730 | ||
2731 | return NOTIFY_DONE; | |
2732 | } | |
2733 | ||
0b131561 MB |
2734 | void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev, |
2735 | struct mlx4_en_stats_bitmap *stats_bitmap, | |
2736 | u8 rx_ppp, u8 rx_pause, | |
2737 | u8 tx_ppp, u8 tx_pause) | |
2738 | { | |
b42de4d0 | 2739 | int last_i = NUM_MAIN_STATS + NUM_PORT_STATS + NUM_PF_STATS; |
0b131561 MB |
2740 | |
2741 | if (!mlx4_is_slave(dev) && | |
2742 | (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN)) { | |
2743 | mutex_lock(&stats_bitmap->mutex); | |
2744 | bitmap_clear(stats_bitmap->bitmap, last_i, NUM_FLOW_STATS); | |
2745 | ||
2746 | if (rx_ppp) | |
2747 | bitmap_set(stats_bitmap->bitmap, last_i, | |
2748 | NUM_FLOW_PRIORITY_STATS_RX); | |
2749 | last_i += NUM_FLOW_PRIORITY_STATS_RX; | |
2750 | ||
2751 | if (rx_pause && !(rx_ppp)) | |
2752 | bitmap_set(stats_bitmap->bitmap, last_i, | |
2753 | NUM_FLOW_STATS_RX); | |
2754 | last_i += NUM_FLOW_STATS_RX; | |
2755 | ||
2756 | if (tx_ppp) | |
2757 | bitmap_set(stats_bitmap->bitmap, last_i, | |
2758 | NUM_FLOW_PRIORITY_STATS_TX); | |
2759 | last_i += NUM_FLOW_PRIORITY_STATS_TX; | |
2760 | ||
2761 | if (tx_pause && !(tx_ppp)) | |
2762 | bitmap_set(stats_bitmap->bitmap, last_i, | |
2763 | NUM_FLOW_STATS_TX); | |
2764 | last_i += NUM_FLOW_STATS_TX; | |
2765 | ||
2766 | mutex_unlock(&stats_bitmap->mutex); | |
2767 | } | |
2768 | } | |
2769 | ||
6fcd2735 | 2770 | void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev, |
0b131561 MB |
2771 | struct mlx4_en_stats_bitmap *stats_bitmap, |
2772 | u8 rx_ppp, u8 rx_pause, | |
2773 | u8 tx_ppp, u8 tx_pause) | |
ffa88f37 | 2774 | { |
6fcd2735 EBE |
2775 | int last_i = 0; |
2776 | ||
3da8a36c EBE |
2777 | mutex_init(&stats_bitmap->mutex); |
2778 | bitmap_zero(stats_bitmap->bitmap, NUM_ALL_STATS); | |
6fcd2735 EBE |
2779 | |
2780 | if (mlx4_is_slave(dev)) { | |
3da8a36c | 2781 | bitmap_set(stats_bitmap->bitmap, last_i + |
6fcd2735 | 2782 | MLX4_FIND_NETDEV_STAT(rx_packets), 1); |
3da8a36c | 2783 | bitmap_set(stats_bitmap->bitmap, last_i + |
6fcd2735 | 2784 | MLX4_FIND_NETDEV_STAT(tx_packets), 1); |
3da8a36c | 2785 | bitmap_set(stats_bitmap->bitmap, last_i + |
6fcd2735 | 2786 | MLX4_FIND_NETDEV_STAT(rx_bytes), 1); |
3da8a36c | 2787 | bitmap_set(stats_bitmap->bitmap, last_i + |
6fcd2735 | 2788 | MLX4_FIND_NETDEV_STAT(tx_bytes), 1); |
3da8a36c | 2789 | bitmap_set(stats_bitmap->bitmap, last_i + |
6fcd2735 | 2790 | MLX4_FIND_NETDEV_STAT(rx_dropped), 1); |
3da8a36c | 2791 | bitmap_set(stats_bitmap->bitmap, last_i + |
6fcd2735 EBE |
2792 | MLX4_FIND_NETDEV_STAT(tx_dropped), 1); |
2793 | } else { | |
3da8a36c | 2794 | bitmap_set(stats_bitmap->bitmap, last_i, NUM_MAIN_STATS); |
ffa88f37 | 2795 | } |
6fcd2735 | 2796 | last_i += NUM_MAIN_STATS; |
ffa88f37 | 2797 | |
3da8a36c | 2798 | bitmap_set(stats_bitmap->bitmap, last_i, NUM_PORT_STATS); |
6fcd2735 | 2799 | last_i += NUM_PORT_STATS; |
ffa88f37 | 2800 | |
b42de4d0 EBE |
2801 | if (mlx4_is_master(dev)) |
2802 | bitmap_set(stats_bitmap->bitmap, last_i, | |
2803 | NUM_PF_STATS); | |
2804 | last_i += NUM_PF_STATS; | |
2805 | ||
0b131561 MB |
2806 | mlx4_en_update_pfc_stats_bitmap(dev, stats_bitmap, |
2807 | rx_ppp, rx_pause, | |
2808 | tx_ppp, tx_pause); | |
2809 | last_i += NUM_FLOW_STATS; | |
2810 | ||
6fcd2735 | 2811 | if (!mlx4_is_slave(dev)) |
3da8a36c | 2812 | bitmap_set(stats_bitmap->bitmap, last_i, NUM_PKT_STATS); |
ffa88f37 EBE |
2813 | } |
2814 | ||
c27a02cd YP |
2815 | int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, |
2816 | struct mlx4_en_port_profile *prof) | |
2817 | { | |
2818 | struct net_device *dev; | |
2819 | struct mlx4_en_priv *priv; | |
c07cb4b0 | 2820 | int i; |
c27a02cd YP |
2821 | int err; |
2822 | ||
f1593d22 | 2823 | dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv), |
d317966b | 2824 | MAX_TX_RINGS, MAX_RX_RINGS); |
41de8d4c | 2825 | if (dev == NULL) |
c27a02cd | 2826 | return -ENOMEM; |
c27a02cd | 2827 | |
d317966b AV |
2828 | netif_set_real_num_tx_queues(dev, prof->tx_ring_num); |
2829 | netif_set_real_num_rx_queues(dev, prof->rx_ring_num); | |
2830 | ||
872bf2fb | 2831 | SET_NETDEV_DEV(dev, &mdev->dev->persist->pdev->dev); |
76a066f2 | 2832 | dev->dev_port = port - 1; |
c27a02cd YP |
2833 | |
2834 | /* | |
2835 | * Initialize driver private data | |
2836 | */ | |
2837 | ||
2838 | priv = netdev_priv(dev); | |
2839 | memset(priv, 0, sizeof(struct mlx4_en_priv)); | |
6de5f7f6 | 2840 | priv->counter_index = MLX4_SINK_COUNTER_INDEX(mdev->dev); |
207af6c5 EE |
2841 | spin_lock_init(&priv->stats_lock); |
2842 | INIT_WORK(&priv->rx_mode_task, mlx4_en_do_set_rx_mode); | |
2843 | INIT_WORK(&priv->watchdog_task, mlx4_en_restart); | |
2844 | INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate); | |
2845 | INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats); | |
2846 | INIT_DELAYED_WORK(&priv->service_task, mlx4_en_service_task); | |
2847 | #ifdef CONFIG_MLX4_EN_VXLAN | |
2848 | INIT_WORK(&priv->vxlan_add_task, mlx4_en_add_vxlan_offloads); | |
2849 | INIT_WORK(&priv->vxlan_del_task, mlx4_en_del_vxlan_offloads); | |
2850 | #endif | |
2851 | #ifdef CONFIG_RFS_ACCEL | |
2852 | INIT_LIST_HEAD(&priv->filters); | |
2853 | spin_lock_init(&priv->filters_lock); | |
2854 | #endif | |
2855 | ||
c27a02cd YP |
2856 | priv->dev = dev; |
2857 | priv->mdev = mdev; | |
ebf8c9aa | 2858 | priv->ddev = &mdev->pdev->dev; |
c27a02cd YP |
2859 | priv->prof = prof; |
2860 | priv->port = port; | |
2861 | priv->port_up = false; | |
c27a02cd | 2862 | priv->flags = prof->flags; |
0fef9d03 | 2863 | priv->pflags = MLX4_EN_PRIV_FLAGS_BLUEFLAME; |
60d6fe99 AV |
2864 | priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE | |
2865 | MLX4_WQE_CTRL_SOLICITED); | |
d317966b | 2866 | priv->num_tx_rings_p_up = mdev->profile.num_tx_rings_p_up; |
c27a02cd | 2867 | priv->tx_ring_num = prof->tx_ring_num; |
fbc6daf1 | 2868 | priv->tx_work_limit = MLX4_EN_DEFAULT_TX_WORK; |
bd635c35 | 2869 | netdev_rss_key_fill(priv->rss_key, sizeof(priv->rss_key)); |
d317966b | 2870 | |
41d942d5 | 2871 | priv->tx_ring = kzalloc(sizeof(struct mlx4_en_tx_ring *) * MAX_TX_RINGS, |
d317966b | 2872 | GFP_KERNEL); |
bc6a4744 AV |
2873 | if (!priv->tx_ring) { |
2874 | err = -ENOMEM; | |
2875 | goto out; | |
2876 | } | |
41d942d5 | 2877 | priv->tx_cq = kzalloc(sizeof(struct mlx4_en_cq *) * MAX_TX_RINGS, |
d317966b | 2878 | GFP_KERNEL); |
bc6a4744 AV |
2879 | if (!priv->tx_cq) { |
2880 | err = -ENOMEM; | |
2881 | goto out; | |
2882 | } | |
c27a02cd | 2883 | priv->rx_ring_num = prof->rx_ring_num; |
08ff3235 | 2884 | priv->cqe_factor = (mdev->dev->caps.cqe_size == 64) ? 1 : 0; |
b1b6b4da | 2885 | priv->cqe_size = mdev->dev->caps.cqe_size; |
c27a02cd YP |
2886 | priv->mac_index = -1; |
2887 | priv->msg_enable = MLX4_EN_MSG_LEVEL; | |
564c274c | 2888 | #ifdef CONFIG_MLX4_EN_DCB |
540b3a39 | 2889 | if (!mlx4_is_slave(priv->mdev->dev)) { |
3742cc65 | 2890 | if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) { |
540b3a39 OG |
2891 | dev->dcbnl_ops = &mlx4_en_dcbnl_ops; |
2892 | } else { | |
2893 | en_info(priv, "enabling only PFC DCB ops\n"); | |
2894 | dev->dcbnl_ops = &mlx4_en_dcbnl_pfc_ops; | |
2895 | } | |
2896 | } | |
564c274c | 2897 | #endif |
c27a02cd | 2898 | |
c07cb4b0 YB |
2899 | for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) |
2900 | INIT_HLIST_HEAD(&priv->mac_hash[i]); | |
16a10ffd | 2901 | |
c27a02cd YP |
2902 | /* Query for default mac and max mtu */ |
2903 | priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port]; | |
6bbb6d99 | 2904 | |
f8c6455b SM |
2905 | if (mdev->dev->caps.rx_checksum_flags_port[priv->port] & |
2906 | MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP) | |
2907 | priv->flags |= MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP; | |
2908 | ||
6bbb6d99 YB |
2909 | /* Set default MAC */ |
2910 | dev->addr_len = ETH_ALEN; | |
2911 | mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]); | |
2912 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
2b3ddf27 JM |
2913 | en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n", |
2914 | priv->port, dev->dev_addr); | |
2915 | err = -EINVAL; | |
2916 | goto out; | |
2917 | } else if (mlx4_is_slave(priv->mdev->dev) && | |
2918 | (priv->mdev->dev->port_random_macs & 1 << priv->port)) { | |
2919 | /* Random MAC was assigned in mlx4_slave_cap | |
2920 | * in mlx4_core module | |
2921 | */ | |
2922 | dev->addr_assign_type |= NET_ADDR_RANDOM; | |
2923 | en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr); | |
c27a02cd YP |
2924 | } |
2925 | ||
2695bab2 | 2926 | memcpy(priv->current_mac, dev->dev_addr, sizeof(priv->current_mac)); |
6bbb6d99 | 2927 | |
c27a02cd YP |
2928 | priv->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + |
2929 | DS_SIZE * MLX4_EN_MAX_RX_FRAGS); | |
2930 | err = mlx4_en_alloc_resources(priv); | |
2931 | if (err) | |
2932 | goto out; | |
2933 | ||
ec693d47 AV |
2934 | /* Initialize time stamping config */ |
2935 | priv->hwtstamp_config.flags = 0; | |
2936 | priv->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF; | |
2937 | priv->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; | |
2938 | ||
c27a02cd YP |
2939 | /* Allocate page for receive rings */ |
2940 | err = mlx4_alloc_hwq_res(mdev->dev, &priv->res, | |
73898db0 | 2941 | MLX4_EN_PAGE_SIZE); |
c27a02cd | 2942 | if (err) { |
453a6082 | 2943 | en_err(priv, "Failed to allocate page for rx qps\n"); |
c27a02cd YP |
2944 | goto out; |
2945 | } | |
2946 | priv->allocated = 1; | |
2947 | ||
c27a02cd YP |
2948 | /* |
2949 | * Initialize netdev entry points | |
2950 | */ | |
8f7ba3ca RE |
2951 | if (mlx4_is_master(priv->mdev->dev)) |
2952 | dev->netdev_ops = &mlx4_netdev_ops_master; | |
2953 | else | |
2954 | dev->netdev_ops = &mlx4_netdev_ops; | |
c27a02cd | 2955 | dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT; |
1eb63a28 BH |
2956 | netif_set_real_num_tx_queues(dev, priv->tx_ring_num); |
2957 | netif_set_real_num_rx_queues(dev, priv->rx_ring_num); | |
3addc568 | 2958 | |
7ad24ea4 | 2959 | dev->ethtool_ops = &mlx4_en_ethtool_ops; |
c27a02cd | 2960 | |
c27a02cd YP |
2961 | /* |
2962 | * Set driver features | |
2963 | */ | |
c8c64cff MM |
2964 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; |
2965 | if (mdev->LSO_support) | |
2966 | dev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; | |
2967 | ||
2968 | dev->vlan_features = dev->hw_features; | |
2969 | ||
ad86107f | 2970 | dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_RXHASH; |
c8c64cff | 2971 | dev->features = dev->hw_features | NETIF_F_HIGHDMA | |
f646968f PM |
2972 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | |
2973 | NETIF_F_HW_VLAN_CTAG_FILTER; | |
537f6f95 SM |
2974 | dev->hw_features |= NETIF_F_LOOPBACK | |
2975 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; | |
c27a02cd | 2976 | |
e38af4fa HHZ |
2977 | if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) { |
2978 | dev->features |= NETIF_F_HW_VLAN_STAG_RX | | |
2979 | NETIF_F_HW_VLAN_STAG_FILTER; | |
2980 | dev->hw_features |= NETIF_F_HW_VLAN_STAG_RX; | |
2981 | } | |
2982 | ||
2983 | if (mlx4_is_slave(mdev->dev)) { | |
2984 | int phv; | |
2985 | ||
2986 | err = get_phv_bit(mdev->dev, port, &phv); | |
2987 | if (!err && phv) { | |
2988 | dev->hw_features |= NETIF_F_HW_VLAN_STAG_TX; | |
2989 | priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV; | |
2990 | } | |
2991 | } else { | |
2992 | if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN && | |
2993 | !(mdev->dev->caps.flags2 & | |
2994 | MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) | |
2995 | dev->hw_features |= NETIF_F_HW_VLAN_STAG_TX; | |
2996 | } | |
2997 | ||
f0df3503 MM |
2998 | if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) |
2999 | dev->hw_features |= NETIF_F_RXFCS; | |
3000 | ||
78500b8c MM |
3001 | if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS) |
3002 | dev->hw_features |= NETIF_F_RXALL; | |
3003 | ||
1eb8c695 | 3004 | if (mdev->dev->caps.steering_mode == |
7d077cd3 MB |
3005 | MLX4_STEERING_MODE_DEVICE_MANAGED && |
3006 | mdev->dev->caps.dmfs_high_steer_mode != MLX4_STEERING_DMFS_A0_STATIC) | |
1eb8c695 AV |
3007 | dev->hw_features |= NETIF_F_NTUPLE; |
3008 | ||
cc5387f7 YB |
3009 | if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0) |
3010 | dev->priv_flags |= IFF_UNICAST_FLT; | |
3011 | ||
947cbb0a EP |
3012 | /* Setting a default hash function value */ |
3013 | if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP) { | |
3014 | priv->rss_hash_fn = ETH_RSS_HASH_TOP; | |
3015 | } else if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR) { | |
3016 | priv->rss_hash_fn = ETH_RSS_HASH_XOR; | |
3017 | } else { | |
3018 | en_warn(priv, | |
3019 | "No RSS hash capabilities exposed, using Toeplitz\n"); | |
3020 | priv->rss_hash_fn = ETH_RSS_HASH_TOP; | |
3021 | } | |
3022 | ||
925ab1aa | 3023 | if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { |
3c9346b2 AD |
3024 | dev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | |
3025 | NETIF_F_GSO_UDP_TUNNEL_CSUM | | |
3026 | NETIF_F_GSO_PARTIAL; | |
3027 | dev->features |= NETIF_F_GSO_UDP_TUNNEL | | |
3028 | NETIF_F_GSO_UDP_TUNNEL_CSUM | | |
3029 | NETIF_F_GSO_PARTIAL; | |
3030 | dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
925ab1aa EE |
3031 | } |
3032 | ||
c27a02cd | 3033 | mdev->pndev[port] = dev; |
5da03547 | 3034 | mdev->upper[port] = NULL; |
c27a02cd YP |
3035 | |
3036 | netif_carrier_off(dev); | |
4801ae70 EE |
3037 | mlx4_en_set_default_moderation(priv); |
3038 | ||
453a6082 YP |
3039 | en_warn(priv, "Using %d TX rings\n", prof->tx_ring_num); |
3040 | en_warn(priv, "Using %d RX rings\n", prof->rx_ring_num); | |
3041 | ||
79aeaccd YB |
3042 | mlx4_en_update_loopback_state(priv->dev, priv->dev->features); |
3043 | ||
90822265 | 3044 | /* Configure port */ |
5c8e9046 | 3045 | mlx4_en_calc_rx_buf(dev); |
90822265 | 3046 | err = mlx4_SET_PORT_general(mdev->dev, priv->port, |
5c8e9046 YP |
3047 | priv->rx_skb_size + ETH_FCS_LEN, |
3048 | prof->tx_pause, prof->tx_ppp, | |
3049 | prof->rx_pause, prof->rx_ppp); | |
90822265 | 3050 | if (err) { |
1a91de28 JP |
3051 | en_err(priv, "Failed setting port general configurations for port %d, with error %d\n", |
3052 | priv->port, err); | |
90822265 YP |
3053 | goto out; |
3054 | } | |
3055 | ||
837052d0 | 3056 | if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { |
1b136de1 | 3057 | err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1); |
837052d0 OG |
3058 | if (err) { |
3059 | en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n", | |
3060 | err); | |
3061 | goto out; | |
3062 | } | |
3063 | } | |
3064 | ||
90822265 YP |
3065 | /* Init port */ |
3066 | en_warn(priv, "Initializing port\n"); | |
3067 | err = mlx4_INIT_PORT(mdev->dev, priv->port); | |
3068 | if (err) { | |
3069 | en_err(priv, "Failed Initializing port\n"); | |
3070 | goto out; | |
3071 | } | |
c27a02cd | 3072 | queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY); |
dc8142ea | 3073 | |
90683061 | 3074 | /* Initialize time stamp mechanism */ |
dc8142ea | 3075 | if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) |
90683061 EE |
3076 | mlx4_en_init_timestamp(mdev); |
3077 | ||
fc9f5ea9 EE |
3078 | queue_delayed_work(mdev->workqueue, &priv->service_task, |
3079 | SERVICE_TASK_DELAY); | |
dc8142ea | 3080 | |
0b131561 MB |
3081 | mlx4_en_set_stats_bitmap(mdev->dev, &priv->stats_bitmap, |
3082 | mdev->profile.prof[priv->port].rx_ppp, | |
3083 | mdev->profile.prof[priv->port].rx_pause, | |
3084 | mdev->profile.prof[priv->port].tx_ppp, | |
3085 | mdev->profile.prof[priv->port].tx_pause); | |
39de961a | 3086 | |
e5eda89d IS |
3087 | err = register_netdev(dev); |
3088 | if (err) { | |
3089 | en_err(priv, "Netdev registration failed for port %d\n", port); | |
3090 | goto out; | |
3091 | } | |
3092 | ||
3093 | priv->registered = 1; | |
09d4d087 JP |
3094 | devlink_port_type_eth_set(mlx4_get_devlink_port(mdev->dev, priv->port), |
3095 | dev); | |
e5eda89d | 3096 | |
c27a02cd YP |
3097 | return 0; |
3098 | ||
3099 | out: | |
3100 | mlx4_en_destroy_netdev(dev); | |
3101 | return err; | |
3102 | } | |
3103 | ||
537f6f95 SM |
3104 | int mlx4_en_reset_config(struct net_device *dev, |
3105 | struct hwtstamp_config ts_config, | |
3106 | netdev_features_t features) | |
3107 | { | |
3108 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
3109 | struct mlx4_en_dev *mdev = priv->mdev; | |
3110 | int port_up = 0; | |
3111 | int err = 0; | |
3112 | ||
3113 | if (priv->hwtstamp_config.tx_type == ts_config.tx_type && | |
3114 | priv->hwtstamp_config.rx_filter == ts_config.rx_filter && | |
f0df3503 MM |
3115 | !DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) && |
3116 | !DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS)) | |
537f6f95 SM |
3117 | return 0; /* Nothing to change */ |
3118 | ||
3119 | if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) && | |
3120 | (features & NETIF_F_HW_VLAN_CTAG_RX) && | |
3121 | (priv->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE)) { | |
3122 | en_warn(priv, "Can't turn ON rx vlan offload while time-stamping rx filter is ON\n"); | |
3123 | return -EINVAL; | |
3124 | } | |
3125 | ||
3126 | mutex_lock(&mdev->state_lock); | |
3127 | if (priv->port_up) { | |
3128 | port_up = 1; | |
3129 | mlx4_en_stop_port(dev, 1); | |
3130 | } | |
3131 | ||
3132 | mlx4_en_free_resources(priv); | |
3133 | ||
3134 | en_warn(priv, "Changing device configuration rx filter(%x) rx vlan(%x)\n", | |
3135 | ts_config.rx_filter, !!(features & NETIF_F_HW_VLAN_CTAG_RX)); | |
3136 | ||
3137 | priv->hwtstamp_config.tx_type = ts_config.tx_type; | |
3138 | priv->hwtstamp_config.rx_filter = ts_config.rx_filter; | |
3139 | ||
3140 | if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX)) { | |
3141 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
3142 | dev->features |= NETIF_F_HW_VLAN_CTAG_RX; | |
3143 | else | |
3144 | dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX; | |
3145 | } else if (ts_config.rx_filter == HWTSTAMP_FILTER_NONE) { | |
3146 | /* RX time-stamping is OFF, update the RX vlan offload | |
3147 | * to the latest wanted state | |
3148 | */ | |
3149 | if (dev->wanted_features & NETIF_F_HW_VLAN_CTAG_RX) | |
3150 | dev->features |= NETIF_F_HW_VLAN_CTAG_RX; | |
3151 | else | |
3152 | dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX; | |
3153 | } | |
3154 | ||
f0df3503 MM |
3155 | if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS)) { |
3156 | if (features & NETIF_F_RXFCS) | |
3157 | dev->features |= NETIF_F_RXFCS; | |
3158 | else | |
3159 | dev->features &= ~NETIF_F_RXFCS; | |
3160 | } | |
3161 | ||
537f6f95 SM |
3162 | /* RX vlan offload and RX time-stamping can't co-exist ! |
3163 | * Regardless of the caller's choice, | |
3164 | * Turn Off RX vlan offload in case of time-stamping is ON | |
3165 | */ | |
3166 | if (ts_config.rx_filter != HWTSTAMP_FILTER_NONE) { | |
3167 | if (dev->features & NETIF_F_HW_VLAN_CTAG_RX) | |
3168 | en_warn(priv, "Turning off RX vlan offload since RX time-stamping is ON\n"); | |
3169 | dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX; | |
3170 | } | |
3171 | ||
3172 | err = mlx4_en_alloc_resources(priv); | |
3173 | if (err) { | |
3174 | en_err(priv, "Failed reallocating port resources\n"); | |
3175 | goto out; | |
3176 | } | |
3177 | if (port_up) { | |
3178 | err = mlx4_en_start_port(dev); | |
3179 | if (err) | |
3180 | en_err(priv, "Failed starting port\n"); | |
3181 | } | |
3182 | ||
3183 | out: | |
3184 | mutex_unlock(&mdev->state_lock); | |
3185 | netdev_features_change(dev); | |
3186 | return err; | |
3187 | } |